2141 files changed, 40302 insertions, 23059 deletions

diff --git a/Kconfig b/Kconfig
index f53759a48e..4b46216665 100644
--- a/Kconfig
+++ b/Kconfig
@@ -268,7 +268,7 @@ config SYS_EXTRA_OPTIONS
 
 config SYS_TEXT_BASE
 	depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP || \
-		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE
+		(M68K && !TARGET_ASTRO_MCF5373L) || MICROBLAZE || MIPS
 	depends on !EFI_APP
 	hex "Text Base"
 	help
diff --git a/Makefile b/Makefile
index 954a865381..0f7d6f32bc 100644
--- a/Makefile
+++ b/Makefile
@@ -3,9 +3,9 @@
 #
 
 VERSION = 2016
-PATCHLEVEL = 05
+PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
 NAME =
 
 # *DOCUMENTATION*
@@ -801,13 +801,6 @@ quiet_cmd_pad_cat = CAT     $@
 cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
 
 all:		$(ALL-y)
-ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
-	@echo "===================== WARNING ======================"
-	@echo "Please convert this board to generic board."
-	@echo "Otherwise it will be removed by the end of 2014."
-	@echo "See doc/README.generic-board for further information"
-	@echo "===================================================="
-endif
 ifeq ($(CONFIG_DM_I2C_COMPAT),y)
 	@echo "===================== WARNING ======================"
 	@echo "This board uses CONFIG_DM_I2C_COMPAT. Please remove"
@@ -1257,13 +1250,6 @@ prepare2: prepare3 outputmakefile
 
 prepare1: prepare2 $(version_h) $(timestamp_h) \
                    include/config/auto.conf
-ifeq ($(CONFIG_HAVE_GENERIC_BOARD),)
-ifeq ($(CONFIG_SYS_GENERIC_BOARD),y)
-	@echo >&2 "  Your architecture does not support generic board."
-	@echo >&2 "  Please undefine CONFIG_SYS_GENERIC_BOARD in your board config file."
-	@/bin/false
-endif
-endif
 ifeq ($(wildcard $(LDSCRIPT)),)
 	@echo >&2 "  Could not find linker script."
 	@/bin/false
@@ -1452,6 +1438,7 @@ clean: $(clean-dirs)
 		-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
 		-o -name '*.symtypes' -o -name 'modules.order' \
 		-o -name modules.builtin -o -name '.tmp_*.o.*' \
+		-o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \
 		-o -name '*.gcno' \) -type f -print | xargs rm -f
 
 # mrproper - Delete all generated files, including .config
diff --git a/README b/README
index 6f4c09a3a1..1d0b946977 100644
--- a/README
+++ b/README
@@ -4048,16 +4048,6 @@ Configuration Settings:
 	If defined, don't allow the -f switch to env set override variable
 	access flags.
 
-- CONFIG_SYS_GENERIC_BOARD
-	This selects the architecture-generic board system instead of the
-	architecture-specific board files. It is intended to move boards
-	to this new framework over time. Defining this will disable the
-	arch/foo/lib/board.c file and use common/board_f.c and
-	common/board_r.c instead. To use this option your architecture
-	must support it (i.e. must select HAVE_GENERIC_BOARD in arch/Kconfig).
-	If you find problems enabling this option on your board please report
-	the problem and send patches!
-
 - CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC (OMAP only)
 	This is set by OMAP boards for the max time that reset should
 	be asserted. See doc/README.omap-reset-time for details on how
diff --git a/arch/Kconfig b/arch/Kconfig
index ec120139cb..566f044308 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -1,13 +1,6 @@
 config CREATE_ARCH_SYMLINK
 	bool
 
-config HAVE_GENERIC_BOARD
-	bool
-
-config SYS_GENERIC_BOARD
-	bool
-	depends on HAVE_GENERIC_BOARD
-
 choice
 	prompt "Architecture select"
 	default SANDBOX
@@ -15,57 +8,39 @@ choice
 config ARC
 	bool "ARC architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config ARM
 	bool "ARM architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC if !ARM64
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config AVR32
 	bool "AVR32 architecture"
 	select CREATE_ARCH_SYMLINK
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config BLACKFIN
 	bool "Blackfin architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config MICROBLAZE
 	bool "MicroBlaze architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config MIPS
 	bool "MIPS architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config NDS32
 	bool "NDS32 architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 
 config NIOS2
 	bool "Nios II architecture"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select OF_CONTROL
 	select DM
@@ -77,14 +52,10 @@ config OPENRISC
 config PPC
 	bool "PowerPC architecture"
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 
 config SANDBOX
 	bool "Sandbox"
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select DM
 	select DM_SPI_FLASH
@@ -99,15 +70,12 @@ config SH
 
 config SPARC
 	bool "SPARC architecture"
-	select HAVE_GENERIC_BOARD
 	select CREATE_ARCH_SYMLINK
 
 config X86
 	bool "x86 architecture"
 	select CREATE_ARCH_SYMLINK
 	select HAVE_PRIVATE_LIBGCC
-	select HAVE_GENERIC_BOARD
-	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
 	select DM
 	select DM_SERIAL
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b65d8e76a..e75c4c0fa6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -64,6 +64,20 @@ config SYS_CPU
         default "sa1100" if CPU_SA1100
 	default "armv8" if ARM64
 
+config SYS_ARM_ARCH
+	int
+	default 4 if CPU_ARM720T
+	default 4 if CPU_ARM920T
+	default 5 if CPU_ARM926EJS
+	default 5 if CPU_ARM946ES
+	default 6 if CPU_ARM1136
+	default 6 if CPU_ARM1176
+	default 7 if CPU_V7
+	default 7 if CPU_V7M
+	default 5 if CPU_PXA
+	default 4 if CPU_SA1100
+	default 8 if ARM64
+
 config SEMIHOSTING
 	bool "support boot from semihosting"
 	help
@@ -77,6 +91,14 @@ config SYS_L2CACHE_OFF
 	  If SoC does not support L2CACHE or one do not want to enable
 	  L2CACHE, choose this option.
 
+config ENABLE_ARM_SOC_BOOT0_HOOK
+	bool "prepare BOOT0 header"
+	help
+	  If the SoC's BOOT0 requires a header area filled with (magic)
+	  values, then choose this option, and create a define called
+	  ARM_SOC_BOOT0_HOOK which contains the required assembler
+	  preprocessor code.
+
 choice
 	prompt "Target select"
 	default TARGET_HIKEY
@@ -339,6 +361,11 @@ config TARGET_RASTABAN
 	select CPU_V7
 	select SUPPORT_SPL
 
+config TARGET_ETAMIN
+        bool "Support etamin"
+        select CPU_V7
+        select SUPPORT_SPL
+
 config TARGET_PXM2
 	bool "Support pxm2"
 	select CPU_V7
@@ -374,18 +401,20 @@ config TARGET_AM335X_EVM
 	select DM_GPIO
 	select TI_I2C_BOARD_DETECT
 
-config TARGET_AM335X_SL50
-	bool "Support am335x_sl50"
+config TARGET_AM335X_SHC
+	bool "Support am335x based shc board from bosch"
 	select CPU_V7
 	select SUPPORT_SPL
 	select DM
 	select DM_SERIAL
+	select DM_GPIO
 
-config TARGET_AM43XX_EVM
-	bool "Support am43xx_evm"
+config TARGET_AM335X_SL50
+	bool "Support am335x_sl50"
 	select CPU_V7
 	select SUPPORT_SPL
-	select TI_I2C_BOARD_DETECT
+	select DM
+	select DM_SERIAL
 
 config TARGET_BAV335X
 	bool "Support bav335x"
@@ -426,7 +455,6 @@ config TARGET_BCMNSP
 
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
-	select CPU_V7
 	select DM
 	select DM_SPI_FLASH
 	select DM_SERIAL
@@ -456,6 +484,13 @@ config ARCH_KEYSTONE
 	select SUPPORT_SPL
 	select CMD_POWEROFF
 
+config ARCH_MESON
+	bool "Amlogic Meson"
+	help
+	  Support for the Meson SoC family developed by Amlogic Inc.,
+	  targeted at media players and tablet computers. We currently
+	  support the S905 (GXBaby) 64-bit SoC.
+
 config ARCH_MX7
 	bool "Freescale MX7"
 	select CPU_V7
@@ -507,6 +542,17 @@ config OMAP54XX
 	select CPU_V7
 	select SUPPORT_SPL
 
+config AM43XX
+	bool "AM43XX SoC"
+	select CPU_V7
+	select SUPPORT_SPL
+	help
+	  Support for AM43xx SOC from Texas Instruments.
+	  The AM43xx high performance SOC features a Cortex-A9
+	  ARM core, a quad core PRU-ICSS for industrial Ethernet
+	  protocols, dual camera support, optional 3D graphics
+	  and an optional customer programmable secure boot.
+
 config RMOBILE
 	bool "Renesas ARM SoCs"
 	select CPU_V7
@@ -538,7 +584,16 @@ config TARGET_CM_T43
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
+	select CMD_BOOTZ
+	select CMD_DHCP
+	select CMD_EXT2
+	select CMD_EXT4
+	select CMD_FAT
+	select CMD_FS_GENERIC
 	select CMD_GPIO
+	select CMD_MII
+	select CMD_MMC if MMC
+	select CMD_PING
 	select CMD_USB
 	select DM
 	select DM_ETH
@@ -546,6 +601,7 @@ config ARCH_SUNXI
 	select DM_KEYBOARD
 	select DM_SERIAL
 	select DM_USB
+	select HUSH_PARSER
 	select OF_BOARD_SETUP
 	select OF_CONTROL
 	select OF_SEPARATE
@@ -594,6 +650,7 @@ config ARCH_ZYNQMP
 	select DM
 	select OF_CONTROL
 	select DM_SERIAL
+	select SUPPORT_SPL
 
 config TEGRA
 	bool "NVIDIA Tegra"
@@ -673,6 +730,33 @@ config TARGET_HIKEY
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+	bool "Support ls1012aqds"
+	select ARM64
+	help
+	  Support for Freescale LS1012AQDS platform.
+	  The LS1012A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
+config TARGET_LS1012ARDB
+	bool "Support ls1012ardb"
+	select ARM64
+	help
+	  Support for Freescale LS1012ARDB platform.
+	  The LS1012A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
+config TARGET_LS1012AFRDM
+	bool "Support ls1012afrdm"
+	select ARM64
+	help
+	  Support for Freescale LS1012AFRDM platform.
+	  The LS1012A Freedom  board (FRDM) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -743,6 +827,7 @@ config ARCH_ROCKCHIP
 
 config TARGET_THUNDERX_88XX
 	bool "Support ThunderX 88xx"
+	select ARM64
 	select OF_CONTROL
 
 endchoice
@@ -771,16 +856,14 @@ source "arch/arm/cpu/armv7/mx6/Kconfig"
 
 source "arch/arm/cpu/armv7/mx5/Kconfig"
 
-source "arch/arm/cpu/armv7/omap3/Kconfig"
-
-source "arch/arm/cpu/armv7/omap4/Kconfig"
-
-source "arch/arm/cpu/armv7/omap5/Kconfig"
+source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
 source "arch/arm/cpu/armv7/rmobile/Kconfig"
 
+source "arch/arm/mach-meson/Kconfig"
+
 source "arch/arm/mach-rockchip/Kconfig"
 
 source "arch/arm/mach-s5pc1xx/Kconfig"
@@ -805,6 +888,7 @@ source "arch/arm/cpu/armv8/Kconfig"
 
 source "arch/arm/imx-common/Kconfig"
 
+source "board/bosch/shc/Kconfig"
 source "board/BuR/kwb/Kconfig"
 source "board/BuR/tseries/Kconfig"
 source "board/CarMediaLab/flea3/Kconfig"
@@ -831,6 +915,9 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index d51634584b..6a07cd178e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -11,7 +11,7 @@ endif
 arch-$(CONFIG_CPU_ARM720T)	=-march=armv4
 arch-$(CONFIG_CPU_ARM920T)	=-march=armv4t
 arch-$(CONFIG_CPU_ARM926EJS)	=-march=armv5te
-arch-$(CONFIG_CPU_ARM946ES)	=-march=armv4
+arch-$(CONFIG_CPU_ARM946ES)	=-march=armv5te
 arch-$(CONFIG_CPU_SA1100)	=-march=armv4
 arch-$(CONFIG_CPU_PXA)		=
 arch-$(CONFIG_CPU_ARM1136)	=-march=armv5
@@ -50,6 +50,7 @@ machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_KEYSTONE)		+= keystone
 # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
 machine-$(CONFIG_KIRKWOOD)		+= kirkwood
+machine-$(CONFIG_ARCH_MESON)		+= meson
 machine-$(CONFIG_ARCH_MVEBU)		+= mvebu
 # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
 # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
diff --git a/arch/arm/cpu/armv7/am33xx/Kconfig b/arch/arm/cpu/armv7/am33xx/Kconfig
new file mode 100644
index 0000000000..dc51e9b697
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/Kconfig
@@ -0,0 +1,40 @@
+if AM43XX
+config TARGET_AM43XX_EVM
+	bool "Support am43xx_evm"
+	select TI_I2C_BOARD_DETECT
+	help
+	  This option specifies support for the AM43xx
+	  GP and HS EVM development platforms.The AM437x
+	  GP EVM is a standalone test, development, and
+	  evaluation module system that enables developers
+	  to write software and develop hardware around
+	  an AM43xx processor subsystem.
+
+config ISW_ENTRY_ADDR
+	hex "Address in memory or XIP flash of bootloader entry point"
+	help
+	  After any reset, the boot ROM on the AM43XX SOC
+	  searches the boot media for a valid boot image.
+	  For non-XIP devices, the ROM then copies the
+	  image into internal memory.
+	  For all boot modes, after the ROM processes the
+	  boot image it eventually computes the entry
+	  point address depending on the device type
+	  (secure/non-secure), boot media (xip/non-xip) and
+	  image headers.
+	default 0x402F4000
+
+config PUB_ROM_DATA_SIZE
+	hex "Size in bytes of the L3 SRAM reserved by ROM to store data"
+	help
+	  During the device boot, the public ROM uses the top of
+	  the public L3 OCMC RAM to store r/w data like stack,
+	  heap, globals etc. When the ROM is copying the boot
+	  image from the boot media into memory, the image must
+	  not spill over into this area. This value can be used
+	  during compile time to determine the maximum size of a
+	  boot image. Once the ROM transfers control to the boot
+	  image, this area is no longer used, and can be reclaimed
+	  for run time use by the boot image.
+	default 0x8400
+endif
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index aae3f096b2..6fda4825fc 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -18,3 +18,5 @@ obj-y	+= ddr.o
 obj-y	+= emif4.o
 obj-y	+= board.o
 obj-y	+= mux.o
+
+obj-$(CONFIG_CLOCK_SYNTHESIZER)	+= clk_synthesizer.o
diff --git a/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
new file mode 100644
index 0000000000..316e677c65
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clk_synthesizer.c
@@ -0,0 +1,104 @@
+/*
+ * clk-synthesizer.c
+ *
+ * Clock synthesizer apis
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/arch/clk_synthesizer.h>
+#include <i2c.h>
+
+/**
+ * clk_synthesizer_reg_read - Read register from synthesizer.
+ * @addr:	addr within the i2c device
+ * buf:		Buffer to which value is to be read.
+ *
+ * For reading the register from this clock synthesizer, a command needs to
+ * be send along with enabling byte read more, and then read can happen.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_read(int addr, uint8_t *buf)
+{
+	int rc;
+
+	/* Enable Bye read */
+	addr = addr | CLK_SYNTHESIZER_BYTE_MODE;
+
+	/* Send the command byte */
+	rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+	if (rc)
+		printf("Failed to send command to clock synthesizer\n");
+
+	/* Read the Data */
+	return i2c_read(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, buf, 1);
+}
+
+/**
+ * clk_synthesizer_reg_write - Write a value to register in synthesizer.
+ * @addr:	addr within the i2c device
+ * val:		Value to be written in the addr.
+ *
+ * Enable the byte read mode in the address and start the i2c transfer.
+ * Returns 0 on success
+ */
+static int clk_synthesizer_reg_write(int addr, uint8_t val)
+{
+	uint8_t cmd[2];
+	int rc = 0;
+
+	/* Enable byte write */
+	cmd[0] = addr | CLK_SYNTHESIZER_BYTE_MODE;
+	cmd[1] = val;
+
+	rc = i2c_write(CLK_SYNTHESIZER_I2C_ADDR, addr, 1, cmd, 2);
+	if (rc)
+		printf("Clock synthesizer reg write failed at addr = 0x%x\n",
+		       addr);
+	return rc;
+}
+
+/**
+ * setup_clock_syntherizer - Program the clock synthesizer to get the desired
+ *				frequency.
+ * @data: Data containing the desired output
+ *
+ * This is a PLL-based high performance synthesizer which gives 3 outputs
+ * as per the PLL_DIV and load capacitor programmed.
+ */
+int setup_clock_synthesizer(struct clk_synth *data)
+{
+	int rc;
+	uint8_t val;
+
+	rc =  i2c_probe(CLK_SYNTHESIZER_I2C_ADDR);
+	if (rc) {
+		printf("i2c probe failed at address 0x%x\n",
+		       CLK_SYNTHESIZER_I2C_ADDR);
+		return rc;
+	}
+
+	rc = clk_synthesizer_reg_read(CLK_SYNTHESIZER_ID_REG, &val);
+	if (val != data->id)
+		return rc;
+
+	/* Crystal Load capacitor selection */
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_XCSEL, data->capacitor);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_MUX_REG, data->mux);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV2_REG, data->pdiv2);
+	if (rc)
+		return rc;
+	rc = clk_synthesizer_reg_write(CLK_SYNTHESIZER_PDIV3_REG, data->pdiv3);
+	if (rc)
+		return rc;
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 92142c8934..7b841b2d55 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -159,3 +159,76 @@ void enable_basic_clocks(void)
 	/* Select the Master osc 24 MHZ as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
 }
+
+/*
+ * Enable Spread Spectrum for the MPU by calculating the required
+ * values and setting the registers accordingly.
+ * @param permille The spreading in permille (10th of a percent)
+ */
+void set_mpu_spreadspectrum(int permille)
+{
+	u32 multiplier_m;
+	u32 predivider_n;
+	u32 cm_clksel_dpll_mpu;
+	u32 cm_clkmode_dpll_mpu;
+	u32 ref_clock;
+	u32 pll_bandwidth;
+	u32 mod_freq_divider;
+	u32 exponent;
+	u32 mantissa;
+	u32 delta_m_step;
+
+	printf("Enabling Spread Spectrum of %d permille for MPU\n",
+	       permille);
+
+	/* Read PLL parameter m and n */
+	cm_clksel_dpll_mpu = readl(&cmwkup->clkseldpllmpu);
+	multiplier_m = (cm_clksel_dpll_mpu >> 8) & 0x3FF;
+	predivider_n = cm_clksel_dpll_mpu & 0x7F;
+
+	/*
+	 * Calculate reference clock (clock after pre-divider),
+	 * its max. PLL bandwidth,
+	 * and resulting mod_freq_divider
+	 */
+	ref_clock = V_OSCK / (predivider_n + 1);
+	pll_bandwidth = ref_clock / 70;
+	mod_freq_divider = ref_clock / (4 * pll_bandwidth);
+
+	/* Calculate Mantissa/Exponent */
+	exponent = 0;
+	mantissa = mod_freq_divider;
+	while ((mantissa > 127) && (exponent < 7)) {
+		exponent++;
+		mantissa /= 2;
+	}
+	if (mantissa > 127)
+		mantissa = 127;
+
+	mod_freq_divider = mantissa << exponent;
+
+	/*
+	 * Calculate Modulation steps
+	 * As we use Downspread only, the spread is twice the value of
+	 * permille, so Div2!
+	 * As it takes the value in percent, divide by ten!
+	 */
+	delta_m_step = ((u32)((multiplier_m * permille) / 10 / 2)) << 18;
+	delta_m_step /= 100;
+	delta_m_step /= mod_freq_divider;
+	if (delta_m_step > 0xFFFFF)
+		delta_m_step = 0xFFFFF;
+
+	/* Setup Spread Spectrum */
+	writel(delta_m_step, &cmwkup->sscdeltamstepdllmpu);
+	writel((exponent << 8) | mantissa, &cmwkup->sscmodfreqdivdpllmpu);
+	cm_clkmode_dpll_mpu = readl(&cmwkup->clkmoddpllmpu);
+	/* clear all SSC flags */
+	cm_clkmode_dpll_mpu &= ~(0xF << CM_CLKMODE_DPLL_SSC_EN_SHIFT);
+	/* enable SSC with Downspread only */
+	cm_clkmode_dpll_mpu |=  CM_CLKMODE_DPLL_SSC_EN_MASK |
+				CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK;
+	writel(cm_clkmode_dpll_mpu, &cmwkup->clkmoddpllmpu);
+	while (!(readl(&cmwkup->clkmoddpllmpu) & 0x2000))
+		;
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 5c2a2ab0f2..73ea955a6c 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -160,7 +160,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
 	u32 *usbclkctrl = 0;
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5294d16708..6d95d327b4 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -3,9 +3,29 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
+
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
 ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+#
+# For booting from SPI use
+# u-boot-spl_HS_SPI_X-LOADER to program flash
+#
+# For booting spl from all other  media
+# use u-boot-spl_HS_ISSW
+#
+# Refer to README.ti-secure for more info
+#
+ALL-y	+= u-boot-spl_HS_ISSW
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += u-boot-spl_HS_SPI_X-LOADER
+else
 ALL-y	+= MLO
 ALL-$(CONFIG_SPL_SPI_SUPPORT) += MLO.byteswap
+endif
 else
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER
+endif
 ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
index 1dfbf54802..02890584a5 100644
--- a/arch/arm/cpu/armv7/ls102xa/spl.c
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -20,7 +20,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig
new file mode 100644
index 0000000000..7b39506ae8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/Kconfig
@@ -0,0 +1,17 @@
+config TI_SECURE_DEVICE
+	bool "HS Device Type Support"
+	depends on OMAP54XX || AM43XX
+	help
+	  If a high secure (HS) device type is being used, this config
+	  must be set. This option impacts various aspects of the
+	  build system (to create signed boot images that can be
+	  authenticated) and the code. See the doc/README.ti-secure
+	  file for further details.
+
+source "arch/arm/cpu/armv7/omap3/Kconfig"
+
+source "arch/arm/cpu/armv7/omap4/Kconfig"
+
+source "arch/arm/cpu/armv7/omap5/Kconfig"
+
+source "arch/arm/cpu/armv7/am33xx/Kconfig"
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 0456263d6e..8333b20001 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -200,7 +200,7 @@ void spl_board_init(void)
 #endif
 }
 
-int board_mmc_init(bd_t *bis)
+__weak int board_mmc_init(bd_t *bis)
 {
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index ef2ac98217..2de9935765 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 			/* Dpll locked with ideal values for nominal opps. */
 			debug("\n %s Dpll already locked with ideal"
 						"nominal opp values", dpll);
+
+			bypass_dpll(base);
 			goto setup_post_dividers;
 		}
 	}
@@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params,
 
 	writel(temp, &dpll_regs->cm_clksel_dpll);
 
+setup_post_dividers:
+	setup_post_dividers(base, params);
+
 	/* Lock */
 	if (lock)
 		do_lock_dpll(base);
 
-setup_post_dividers:
-	setup_post_dividers(base, params);
-
 	/* Wait till the DPLL locks */
 	if (lock)
 		wait_for_lock(base);
diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk
new file mode 100644
index 0000000000..c7bb101be8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk
@@ -0,0 +1,66 @@
+#
+# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+quiet_cmd_mkomapsecimg = MKIMAGE $@
+ifneq ($(TI_SECURE_DEV_PKG),)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
+ifneq ($(CONFIG_SPL_BUILD),)
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+	$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
+else
+cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
+    $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+    $(if $(KBUILD_VERBOSE:1=), >/dev/null)
+endif
+else
+cmd_mkomapsecimg = echo "WARNING:" \
+	"$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \
+	"$@ was NOT created!"
+endif
+else
+cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \
+	"variable must be defined for TI secure devices. $@ was NOT created!"
+endif
+
+# Standard X-LOADER target (QPSI, NOR flash)
+u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For MLO targets (SD card boot) the final file name
+# that is copied to the SD card fAT partition must
+# be MLO, so we make a copy of the output file to a
+# new file with that name
+u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+	@if [ -f $@ ]; then \
+		cp -f $@ MLO; \
+	fi
+
+# Standard 2ND target (certain peripheral boot modes)
+u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# Standard ULO target (certain peripheral boot modes)
+u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# Standard ISSW target (certain devices, various boot modes)
+u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For SPI flash on AM335x and AM43xx, these
+# require special byte swap handling so we use
+# the SPI_X-LOADER target instead of X-LOADER
+# and let the create-boot-image.sh script handle
+# that
+u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin
+	$(call if_changed,mkomapsecimg)
+
+# For supporting single stage XiP QSPI on AM43xx, the
+# image is a full u-boot file, not an SPL. In this case
+# the mkomapsecimg command looks for a u-boot-HS_* prefix
+u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin
+	$(call if_changed,mkomapsecimg)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 01c2d576c9..2f9693f28e 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -65,12 +65,30 @@ static void omap_rev_string(void)
 	u32 major_rev = (omap_rev & 0x00000F00) >> 8;
 	u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
 
+	const char *sec_s;
+
+	switch (get_device_type()) {
+	case TST_DEVICE:
+		sec_s = "TST";
+		break;
+	case EMU_DEVICE:
+		sec_s = "EMU";
+		break;
+	case HS_DEVICE:
+		sec_s = "HS";
+		break;
+	case GP_DEVICE:
+		sec_s = "GP";
+		break;
+	default:
+		sec_s = "?";
+	}
+
 	if (soc_variant)
 		printf("OMAP");
 	else
 		printf("DRA");
-	printf("%x ES%x.%x\n", omap_variant, major_rev,
-	       minor_rev);
+	printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev);
 }
 
 #ifdef CONFIG_SPL_BUILD
@@ -94,6 +112,16 @@ void __weak do_board_detect(void)
 {
 }
 
+/**
+ * vcores_init() - Assign omap_vcores based on board
+ *
+ * Function to pick the vcores based on board. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak vcores_init(void)
+{
+}
+
 void s_init(void)
 {
 }
@@ -131,6 +159,7 @@ void early_system_init(void)
 #endif
 	setup_early_clocks();
 	do_board_detect();
+	vcores_init();
 	prcm_init();
 }
 
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
index 52ea7342df..2d03ebfbd3 100644
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -108,6 +108,6 @@ void omap_die_id_display(void)
 
 	omap_die_id(die_id);
 
-	printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[0], die_id[1],
-		die_id[2], die_id[3]);
+	printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2],
+		die_id[1], die_id[0]);
 }
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 0c44ea53e1..5f5597772b 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -280,6 +280,8 @@ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const arg
 				omap_nand_switch_ecc(1, 1);
 			else if (strncmp(argv[2], "bch8", 4) == 0)
 				omap_nand_switch_ecc(1, 8);
+			else if (strncmp(argv[2], "bch16", 5) == 0)
+				omap_nand_switch_ecc(1, 16);
 			else
 				goto usage;
 		}
@@ -308,8 +310,8 @@ usage:
 U_BOOT_CMD(
 	nandecc, 3, 1,	do_switch_ecc,
 	"switch OMAP3 NAND ECC calculation algorithm",
-	"hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
-	" 8-bit BCH\n"
+	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
+	" and 8-bit/16-bit BCH\n"
 	"                           ecc calculation (second parameter may"
 	" be omitted).\n"
 	"nandecc sw               - Switch to NAND software ecc algorithm."
diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile
index f2930d521c..3caba86791 100644
--- a/arch/arm/cpu/armv7/omap5/Makefile
+++ b/arch/arm/cpu/armv7/omap5/Makefile
@@ -12,4 +12,5 @@ obj-y	+= sdram.o
 obj-y	+= prcm-regs.o
 obj-y	+= hw_data.o
 obj-y	+= abb.o
+obj-y	+= fdt.o
 obj-$(CONFIG_IODELAY_RECALIBRATION) += dra7xx_iodelay.o
diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk
index ef2725affa..a7e55a5e24 100644
--- a/arch/arm/cpu/armv7/omap5/config.mk
+++ b/arch/arm/cpu/armv7/omap5/config.mk
@@ -6,8 +6,14 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+include  $(srctree)/$(CPUDIR)/omap-common/config_secure.mk
+
 ifdef CONFIG_SPL_BUILD
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ALL-y	+= u-boot-spl_HS_MLO u-boot-spl_HS_X-LOADER
+else
 ALL-y	+= MLO
+endif
 else
 ALL-y	+= u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/omap5/fdt.c b/arch/arm/cpu/armv7/omap5/fdt.c
new file mode 100644
index 0000000000..0493cd1eab
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap5/fdt.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2016 Texas Instruments, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <malloc.h>
+
+#include <asm/omap_common.h>
+#include <asm/arch-omap5/sys_proto.h>
+
+#ifdef CONFIG_TI_SECURE_DEVICE
+
+/* Give zero values if not already defined */
+#ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
+#endif
+#ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
+#define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
+#endif
+
+static u32 hs_irq_skip[] = {
+	8,	/* Secure violation reporting interrupt */
+	15,	/* One interrupt for SDMA by secure world */
+	118	/* One interrupt for Crypto DMA by secure world */
+};
+
+static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+	int len, i, old_cnt, new_cnt;
+	u32 *temp;
+	const u32 *p_data;
+
+	/*
+	 * Increase the size of the fdt
+	 * so we have some breathing room
+	 */
+	ret = fdt_increase_size(fdt, 512);
+	if (ret < 0) {
+		printf("Could not increase size of device tree: %s\n",
+		       fdt_strerror(ret));
+		return ret;
+	}
+
+	/* Reserve IRQs that are used/needed by secure world */
+	path = "/ocp/crossbar";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+
+	/* Get current entries */
+	p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
+	if (p_data)
+		old_cnt = len / sizeof(u32);
+	else
+		old_cnt = 0;
+
+	new_cnt = sizeof(hs_irq_skip) /
+				sizeof(hs_irq_skip[0]);
+
+	/* Create new/updated skip list for HS parts */
+	temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
+	for (i = 0; i < new_cnt; i++)
+		temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
+	for (i = 0; i < old_cnt; i++)
+		temp[i + new_cnt] = p_data[i];
+
+	/* Blow away old data and set new data */
+	fdt_delprop(fdt, offs, "ti,irqs-skip");
+	ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
+			  temp,
+			  (old_cnt + new_cnt) * sizeof(u32));
+	free(temp);
+
+	/* Check if the update worked */
+	if (ret < 0) {
+		printf("Could not add ti,irqs-skip property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+
+	return 0;
+}
+
+static int ft_hs_disable_rng(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+
+	/* Make HW RNG reserved for secure world use */
+	path = "/ocp/rng";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+	ret = fdt_setprop_string(fdt, offs,
+				 "status", "disabled");
+	if (ret < 0) {
+		printf("Could not add status property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+	return 0;
+}
+
+#if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
+    (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
+{
+	const char *path;
+	int offs;
+	int ret;
+	u32 temp[2];
+
+	/*
+	 * Update SRAM reservations on secure devices. The OCMC RAM
+	 * is always reserved for secure use from the start of that
+	 * memory region
+	 */
+	path = "/ocp/ocmcram@40300000/sram-hs";
+	offs = fdt_path_offset(fdt, path);
+	if (offs < 0) {
+		debug("Node %s not found.\n", path);
+		return 0;
+	}
+
+	/* relative start offset */
+	temp[0] = cpu_to_fdt32(0);
+	/* reservation size */
+	temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
+				   CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
+	fdt_delprop(fdt, offs, "reg");
+	ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
+	if (ret < 0) {
+		printf("Could not add reg property to node %s: %s\n",
+		       path, fdt_strerror(ret));
+		return ret;
+	}
+
+	return 0;
+}
+#else
+static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
+#endif
+
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+	/* Check we are running on an HS/EMU device type */
+	if (GP_DEVICE != get_device_type()) {
+		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
+		    (ft_hs_disable_rng(fdt, bd) == 0) &&
+		    (ft_hs_fixup_sram(fdt, bd) == 0))
+			return;
+	} else {
+		printf("ERROR: Incorrect device type (GP) detected!");
+	}
+	/* Fixup failed or wrong device type */
+	hang();
+}
+#else
+static void ft_hs_fixups(void *fdt, bd_t *bd)
+{
+}
+#endif
+
+/*
+ * Place for general cpu/SoC FDT fixups. Board specific
+ * fixups should remain in the board files which is where
+ * this function should be called from.
+ */
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+	ft_hs_fixups(fdt, bd);
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 88e8920bad..5b91446a8d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -365,35 +365,35 @@ struct vcores_data omap5430_volts_es2 = {
 };
 
 struct vcores_data dra752_volts = {
-	.mpu.value	= VDD_MPU_DRA752,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA752,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value	= VDD_GPU_DRA752,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS659038_REG_ADDR_SMPS6,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA752,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS659038_REG_ADDR_SMPS7,
 	.core.pmic	= &tps659038,
 
-	.iva.value	= VDD_IVA_DRA752,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS659038_REG_ADDR_SMPS8,
 	.iva.pmic	= &tps659038,
@@ -401,15 +401,15 @@ struct vcores_data dra752_volts = {
 };
 
 struct vcores_data dra722_volts = {
-	.mpu.value	= VDD_MPU_DRA72x,
-	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.value	= VDD_MPU_DRA7,
+	.mpu.efuse.reg	= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.mpu.addr	= TPS65917_REG_ADDR_SMPS1,
 	.mpu.pmic	= &tps659038,
 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
 
-	.core.value	= VDD_CORE_DRA72x,
-	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.value	= VDD_CORE_DRA7,
+	.core.efuse.reg	= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.core.addr	= TPS65917_REG_ADDR_SMPS2,
 	.core.pmic	= &tps659038,
@@ -418,22 +418,22 @@ struct vcores_data dra722_volts = {
 	 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
 	 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
 	 */
-	.gpu.value	= VDD_GPU_DRA72x,
-	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.value	= VDD_GPU_DRA7,
+	.gpu.efuse.reg	= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.gpu.addr	= TPS65917_REG_ADDR_SMPS3,
 	.gpu.pmic	= &tps659038,
 	.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
 
-	.eve.value	= VDD_EVE_DRA72x,
-	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.value	= VDD_EVE_DRA7,
+	.eve.efuse.reg	= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.eve.addr	= TPS65917_REG_ADDR_SMPS3,
 	.eve.pmic	= &tps659038,
 	.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
 
-	.iva.value	= VDD_IVA_DRA72x,
-	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.value	= VDD_IVA_DRA7,
+	.iva.efuse.reg	= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
 	.iva.addr	= TPS65917_REG_ADDR_SMPS3,
 	.iva.pmic	= &tps659038,
@@ -602,7 +602,7 @@ void disable_edma3_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 void enable_usb_clocks(int index)
 {
 	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
@@ -614,9 +614,14 @@ void enable_usb_clocks(int index)
 		setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 			     OPTFCLKEN_REFCLK960M);
 
-		/* Enable 32 KHz clock for dwc3 */
+		/* Enable 32 KHz clock for USB_PHY1 */
 		setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Enable 32 KHz clock for USB_PHY3 */
+		if (is_dra7xx())
+			setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 	} else if (index == 1) {
 		cm_l3init_usb_otg_ss_clkctrl =
 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
@@ -664,9 +669,14 @@ void disable_usb_clocks(int index)
 		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 			     OPTFCLKEN_REFCLK960M);
 
-		/* Disable 32 KHz clock for dwc3 */
+		/* Disable 32 KHz clock for USB_PHY1 */
 		clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
+
+		/* Disable 32 KHz clock for USB_PHY3 */
+		if (is_dra7xx())
+			clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
+				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
 	} else if (index == 1) {
 		cm_l3init_usb_otg_ss_clkctrl =
 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 655e92ba27..b5f1d700fd 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -820,6 +820,7 @@ struct prcm_regs const dra7xx_prcm = {
 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
 	.cm_coreaon_usb_phy1_core_clkctrl	= 0x4a008640,
 	.cm_coreaon_usb_phy2_core_clkctrl	= 0x4a008688,
+	.cm_coreaon_usb_phy3_core_clkctrl	= 0x4a008698,
 	.cm_coreaon_l3init_60m_gfclk_clkctrl	= 0x4a0086c0,
 
 	/* cm1.mpu */
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
index 949abb1c8f..b63036c64e 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -12,6 +12,9 @@
 #include <asm/io.h>
 #include <asm/arch/pwm.h>
 #include <asm/arch/clk.h>
+
+/* Use the old PWM interface for now */
+#undef CONFIG_DM_PWM
 #include <pwm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index a9f4fec387..46f25e63f0 100644
--- a/arch/arm/cpu/armv8/cache.S
+++ b/arch/arm/cpu/armv8/cache.S
@@ -14,15 +14,15 @@
 #include <linux/linkage.h>
 
 /*
- * void __asm_flush_dcache_level(level)
+ * void __asm_dcache_level(level)
  *
- * clean and invalidate one level cache.
+ * flush or invalidate one level cache.
  *
  * x0: cache level
- * x1: 0 flush & invalidate, 1 invalidate only
+ * x1: 0 clean & invalidate, 1 invalidate only
  * x2~x9: clobbered
  */
-ENTRY(__asm_flush_dcache_level)
+ENTRY(__asm_dcache_level)
 	lsl	x12, x0, #1
 	msr	csselr_el1, x12		/* select cache level */
 	isb				/* sync change of cssidr_el1 */
@@ -57,14 +57,14 @@ loop_way:
 	b.ge	loop_set
 
 	ret
-ENDPROC(__asm_flush_dcache_level)
+ENDPROC(__asm_dcache_level)
 
 /*
  * void __asm_flush_dcache_all(int invalidate_only)
  *
- * x0: 0 flush & invalidate, 1 invalidate only
+ * x0: 0 clean & invalidate, 1 invalidate only
  *
- * clean and invalidate all data cache by SET/WAY.
+ * flush or invalidate all data cache by SET/WAY.
  */
 ENTRY(__asm_dcache_all)
 	mov	x1, x0
@@ -87,7 +87,7 @@ loop_level:
 	and	x12, x12, #7		/* x12 <- cache type */
 	cmp	x12, #2
 	b.lt	skip			/* skip if no cache or icache */
-	bl	__asm_flush_dcache_level	/* x1 = 0 flush, 1 invalidate */
+	bl	__asm_dcache_level	/* x1 = 0 flush, 1 invalidate */
 skip:
 	add	x0, x0, #1		/* increment cache level */
 	cmp	x11, x0
@@ -104,19 +104,13 @@ finished:
 ENDPROC(__asm_dcache_all)
 
 ENTRY(__asm_flush_dcache_all)
-	mov	x16, lr
 	mov	x0, #0
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_flush_dcache_all)
 
 ENTRY(__asm_invalidate_dcache_all)
-	mov	x16, lr
 	mov	x0, #0x1
-	bl	__asm_dcache_all
-	mov	lr, x16
-	ret
+	b	__asm_dcache_all
 ENDPROC(__asm_invalidate_dcache_all)
 
 /*
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5f86ef90d2..eb2cbc3f7e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index d93990036b..9a5a6b53f7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -396,9 +396,6 @@ static inline void final_mmu_setup(void)
 	flush_dcache_range((ulong)level0_table,
 			   (ulong)level0_table + gd->arch.tlb_size);
 
-#ifdef CONFIG_SYS_DPAA_FMAN
-	flush_dcache_all();
-#endif
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
 			  MEMORY_ATTRIBUTES);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
index a6ef830069..a6ef830069 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch2
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
index f9323c1d28..f9323c1d28 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
new file mode 100644
index 0000000000..8eee016f11
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
@@ -0,0 +1,129 @@
+SoC overview
+
+	1. LS1043A
+	2. LS2080A
+	3. LS1012A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer
+ - QorIQ platform's trust architecture 2.1
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1e875c4b08..d17227ab2b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -20,6 +20,8 @@
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
+#include <fsl_sec.h>
+#include <asm/arch-fsl-layerscape/soc.h>
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
@@ -75,6 +77,23 @@ void ft_fixup_cpu(void *blob)
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_LSCH2
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	unsigned int svr = in_be32(&gur->svr);
+
+	/* delete crypto node if not on an E-processor */
+	if (!IS_E_PROCESSOR(svr))
+		fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+	else {
+		ccsr_sec_t __iomem *sec;
+
+		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+	}
+#endif
+#endif
+
 #ifdef CONFIG_MP
 	ft_fixup_cpu(blob);
 #endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 453a93d94c..3a77b21d0a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+	defined(CONFIG_SYS_DPAA_FMAN)
+
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -56,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -80,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+	sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 04831ca5bb..5af6b73bc9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
 	bl	ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
 	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
 	str	w0, [x1, #0x10]
+#endif
 
 	/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
@@ -181,6 +183,7 @@ ENTRY(lowlevel_init)
 	ret
 ENDPROC(lowlevel_init)
 
+#ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7
@@ -258,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_cache)
+#endif
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
new file mode 100644
index 0000000000..ff0903cebc
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	{0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+	{0x0008, {NONE, NONE, NONE, SATA1} },
+	{0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+	{0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+	{0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+	{0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0cb010012e..dd633f3690 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,10 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
+#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
@@ -222,7 +226,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {
@@ -271,6 +275,39 @@ static void erratum_a009660(void)
 #endif
 }
 
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+	/* part 1 of 2 */
+	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	/* disables propagation of barrier transactions to DDRC from CCI400 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+	/* disable the re-ordering in DDRC */
+	ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+	/* part 2 of 2 */
+	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+	u32 tmp;
+
+	/* enable propagation of barrier transactions to DDRC from CCI400 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+	/* enable the re-ordering in DDRC */
+	tmp = ddr_in32(&ddr->eor);
+	tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+	ddr_out32(&ddr->eor, tmp);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -295,6 +332,7 @@ void fsl_lsch2_early_init_f(void)
 		 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
 	/* Erratum */
+	erratum_a008850_early(); /* part 1 of 2 */
 	erratum_a009929();
 	erratum_a009660();
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
index c1229c88af..5883c002be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -29,7 +29,7 @@ u32 spl_boot_mode(void)
 	switch (spl_boot_device()) {
 	case BOOT_DEVICE_MMC1:
 #ifdef CONFIG_SPL_FAT_SUPPORT
-		return MMCSD_MODE_FAT;
+		return MMCSD_MODE_FS;
 #else
 		return MMCSD_MODE_RAW;
 #endif
@@ -49,9 +49,6 @@ void board_init_f(ulong dummy)
 #ifdef CONFIG_LS2080A
 	arch_cpu_init();
 #endif
-#ifdef CONFIG_FSL_IFC
-	init_early_memctl_regs();
-#endif
 	board_early_init_f();
 	timer_init();
 #ifdef CONFIG_LS2080A
diff --git a/arch/arm/cpu/armv8/fwcall.c b/arch/arm/cpu/armv8/fwcall.c
index 9efcc5ada9..079e250cbe 100644
--- a/arch/arm/cpu/armv8/fwcall.c
+++ b/arch/arm/cpu/armv8/fwcall.c
@@ -8,6 +8,7 @@
 #include <config.h>
 #include <version.h>
 #include <asm/macro.h>
+#include <asm/psci.h>
 #include <asm/system.h>
 
 /*
@@ -73,3 +74,18 @@ void smc_call(struct pt_regs *args)
 		  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
 		  "x16", "x17");
 }
+
+void __noreturn psci_system_reset(bool conduit_smc)
+{
+	struct pt_regs regs;
+
+	regs.regs[0] = ARM_PSCI_0_2_FN_SYSTEM_RESET;
+
+	if (conduit_smc)
+		smc_call(&regs);
+	else
+		hvc_call(&regs);
+
+	while (1)
+		;
+}
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e933021a17..c1a2f456d5 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -21,6 +21,16 @@
 _start:
 	b	reset
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
 	.align 3
 
 .globl	_TEXT_BASE
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index d0ed2223ff..be8673a7db 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -9,3 +9,4 @@ obj-y	+= clk.o
 obj-y	+= cpu.o
 obj-$(CONFIG_MP)	+= mp.o
 obj-y	+= slcr.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 5dd3cd86cf..509f0aa387 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -63,6 +63,11 @@ static struct mm_region zynqmp_mem_map[] = {
 };
 struct mm_region *mem_map = zynqmp_mem_map;
 
+u64 get_page_table_size(void)
+{
+	return 0x14000;
+}
+
 static unsigned int zynqmp_get_silicon_version_secure(void)
 {
 	u32 ver;
diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c
new file mode 100644
index 0000000000..e3e2a4fb5a
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/spl.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 - 2016 Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <spl.h>
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+
+void board_init_f(ulong dummy)
+{
+	psu_init();
+	board_early_init_r();
+
+#ifdef CONFIG_DEBUG_UART
+	/* Uart debug for sure */
+	debug_uart_init();
+	puts("Debug uart enabled\n"); /* or printch() */
+#endif
+	/* Delay is required for clocks to be propagated */
+	udelay(1000000);
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* No need to call timer init - it is empty for ZynqMP */
+	board_init_r(NULL, 0);
+}
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+	preloader_console_init();
+	board_init();
+}
+#endif
+
+u32 spl_boot_device(void)
+{
+	u32 reg = 0;
+	u8 bootmode;
+
+	reg = readl(&crlapb_base->boot_mode);
+	bootmode = reg & BOOT_MODES_MASK;
+
+	switch (bootmode) {
+	case JTAG_MODE:
+		return BOOT_DEVICE_RAM;
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	case EMMC_MODE:
+	case SD_MODE:
+	case SD_MODE1:
+		return BOOT_DEVICE_MMC1;
+#endif
+	default:
+		printf("Invalid Boot Mode:0x%x\n", bootmode);
+		break;
+	}
+
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_RAM:
+		return 0;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FS;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+__weak void psu_init(void)
+{
+	 /*
+	  * This function is overridden by the one in
+	  * board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
+	  */
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d1f8e22451..a8276138ab 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -21,11 +21,14 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
 	exynos5420-peach-pit.dtb \
 	exynos5800-peach-pi.dtb \
 	exynos5422-odroidxu3.dtb
+dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rk3288-firefly.dtb \
 	rk3288-jerry.dtb \
 	rk3288-rock2-square.dtb \
 	rk3036-sdk.dtb
+dtb-$(CONFIG_ARCH_MESON) += \
+	meson-gxbb-odroidc2.dtb
 dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra20-medcom-wide.dtb \
 	tegra20-paz00.dtb \
@@ -45,6 +48,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
 	tegra124-jetson-tk1.dtb \
 	tegra124-nyan-big.dtb \
 	tegra124-venice2.dtb \
+	tegra186-p2771-0000.dtb \
 	tegra210-e2220-1170.dtb \
 	tegra210-p2371-0000.dtb \
 	tegra210-p2371-2180.dtb \
@@ -88,9 +92,15 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
 	zynqmp-zcu102-revB.dtb			\
 	zynqmp-zc1751-xm015-dc1.dtb		\
 	zynqmp-zc1751-xm016-dc2.dtb		\
+	zynqmp-zc1751-xm018-dc4.dtb		\
 	zynqmp-zc1751-xm019-dc5.dtb
-dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
-dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb am335x-evm.dtb \
+	am335x-evmsk.dtb \
+	am335x-bonegreen.dtb \
+	am335x-icev2.dtb
+dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
+	am43x-epos-evm.dtb \
+	am437x-idk-evm.dtb
 dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
@@ -100,7 +110,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
-	socfpga_cyclone5_sr1500.dtb
+	socfpga_cyclone5_sr1500.dtb			\
+	socfpga_cyclone5_vining_fpga.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
@@ -113,7 +124,10 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
-	fsl-ls1043a-rdb.dtb
+	fsl-ls1043a-rdb.dtb \
+	fsl-ls1012a-qds.dtb \
+	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 
@@ -218,7 +232,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
 	sun8i-h3-orangepi-pc.dtb \
 	sun8i-h3-orangepi-plus.dtb
 dtb-$(CONFIG_MACH_SUN50I) += \
-	pine64_plus.dtb
+	sun50i-a64-pine64-plus.dtb \
+	sun50i-a64-pine64.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index fec78349c1..40a3c35ff8 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -13,6 +13,11 @@
 		};
 	};
 
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
 	memory {
 		device_type = "memory";
 		reg = <0x80000000 0x10000000>; /* 256 MB */
@@ -383,8 +388,7 @@
 	bus-width = <0x4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
-	cd-inverted;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &aes {
diff --git a/arch/arm/dts/am335x-bone.dts b/arch/arm/dts/am335x-bone.dts
index 81441cc823..6b84937204 100644
--- a/arch/arm/dts/am335x-bone.dts
+++ b/arch/arm/dts/am335x-bone.dts
@@ -13,9 +13,6 @@
 / {
 	model = "TI AM335x BeagleBone";
 	compatible = "ti,am335x-bone", "ti,am33xx";
-	chosen {
-		stdout-path = &uart0;
-	};
 };
 
 &ldo3_reg {
diff --git a/arch/arm/dts/am335x-bonegreen.dts b/arch/arm/dts/am335x-bonegreen.dts
new file mode 100644
index 0000000000..9c59da90fa
--- /dev/null
+++ b/arch/arm/dts/am335x-bonegreen.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+/ {
+	model = "TI AM335x BeagleBone Green";
+	compatible = "ti,am335x-bone-green", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+};
+
+&ldo3_reg {
+	regulator-min-microvolt = <1800000>;
+	regulator-max-microvolt = <1800000>;
+	regulator-always-on;
+};
+
+&mmc1 {
+	vmmc-supply = <&vmmcsd_fixed>;
+};
+
+&mmc2 {
+	vmmc-supply = <&vmmcsd_fixed>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_pins>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&am33xx_pinmux {
+	uart2_pins: uart2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)	/* spi0_sclk.uart2_rxd */
+			AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)	/* spi0_d0.uart2_txd */
+		>;
+	};
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+&rtc {
+	system-power-controller;
+};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index c0bc2af9a5..a6f20af648 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -717,7 +717,7 @@
 	bus-width = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 };
 
 &mmc3 {
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
new file mode 100644
index 0000000000..b3e9b61bae
--- /dev/null
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -0,0 +1,720 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x Starter Kit
+ * http://www.ti.com/tool/tmdssk3358
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "TI AM335x EVM-SK";
+	compatible = "ti,am335x-evmsk", "ti,am33xx";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	lis3_reg: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "lis3_reg";
+		regulator-boot-on;
+	};
+
+	wl12xx_vmmc: fixedregulator@2 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&wl12xx_gpio>;
+		compatible = "regulator-fixed";
+		regulator-name = "vwl1271";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio1 29 0>;
+		startup-delay-us = <70000>;
+		enable-active-high;
+	};
+
+	vtt_fixed: fixedregulator@3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	leds {
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds_s0>;
+
+		compatible = "gpio-leds";
+
+		led@1 {
+			label = "evmsk:green:usr0";
+			gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "evmsk:green:usr1";
+			gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "evmsk:green:mmc0";
+			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "evmsk:green:heartbeat";
+			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "off";
+		};
+	};
+
+	gpio_buttons: gpio_buttons@0 {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@1 {
+			label = "button0";
+			linux,code = <0x100>;
+			gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+		};
+
+		switch@2 {
+			label = "button1";
+			linux,code = <0x101>;
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		switch@3 {
+			label = "button2";
+			linux,code = <0x102>;
+			gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
+			wakeup-source;
+		};
+
+		switch@4 {
+			label = "button3";
+			linux,code = <0x103>;
+			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 58 61 66 75 90 125 170 255>;
+		default-brightness-level = <8>;
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "AM335x-EVMSK";
+		simple-audio-card,widgets =
+			"Headphone", "Headphone Jack";
+		simple-audio-card,routing =
+			"Headphone Jack",	"HPLOUT",
+			"Headphone Jack",	"HPROUT";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound_master>;
+		simple-audio-card,frame-master = <&sound_master>;
+		simple-audio-card,bitclock-inversion;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+		};
+
+		sound_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic3106>;
+			system-clock-frequency = <24000000>;
+		};
+	};
+
+	panel {
+		compatible = "ti,tilcdc,panel";
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&lcd_pins_default>;
+		pinctrl-1 = <&lcd_pins_sleep>;
+		status = "okay";
+		panel-info {
+			ac-bias           = <255>;
+			ac-bias-intrpt    = <0>;
+			dma-burst-sz      = <16>;
+			bpp               = <32>;
+			fdd               = <0x80>;
+			sync-edge         = <0>;
+			sync-ctrl         = <1>;
+			raster-order      = <0>;
+			fifo-th           = <0>;
+		};
+		display-timings {
+			480x272 {
+				hactive         = <480>;
+				vactive         = <272>;
+				hback-porch     = <43>;
+				hfront-porch    = <8>;
+				hsync-len       = <4>;
+				vback-porch     = <12>;
+				vfront-porch    = <4>;
+				vsync-len       = <10>;
+				clock-frequency = <9000000>;
+				hsync-active    = <0>;
+				vsync-active    = <0>;
+			};
+		};
+	};
+};
+
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
+
+	lcd_pins_default: lcd_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data0.lcd_data0 */
+			AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data1.lcd_data1 */
+			AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data2.lcd_data2 */
+			AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)	/* lcd_data3.lcd_data3 */
+			AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data4.lcd_data4 */
+			AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data5.lcd_data5 */
+			AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data6.lcd_data6 */
+			AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data7.lcd_data7 */
+			AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data8.lcd_data8 */
+			AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data9.lcd_data9 */
+			AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data10.lcd_data10 */
+			AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data11.lcd_data11 */
+			AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)	/* lcd_data12.lcd_data12 */
+			AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)	/* lcd_data13.lcd_data13 */
+			AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)	/* lcd_data14.lcd_data14 */
+			AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)	/* lcd_data15.lcd_data15 */
+			AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
+			AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
+			AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
+			AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+		>;
+	};
+
+	lcd_pins_sleep: lcd_pins_sleep {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad8.lcd_data23 */
+			AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad9.lcd_data22 */
+			AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad10.lcd_data21 */
+			AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad11.lcd_data20 */
+			AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad12.lcd_data19 */
+			AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad13.lcd_data18 */
+			AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad14.lcd_data17 */
+			AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad15.lcd_data16 */
+			AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)	/* lcd_data0.lcd_data0 */
+			AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)	/* lcd_data1.lcd_data1 */
+			AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)	/* lcd_data2.lcd_data2 */
+			AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)	/* lcd_data3.lcd_data3 */
+			AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)	/* lcd_data4.lcd_data4 */
+			AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)	/* lcd_data5.lcd_data5 */
+			AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)	/* lcd_data6.lcd_data6 */
+			AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)	/* lcd_data7.lcd_data7 */
+			AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)	/* lcd_data8.lcd_data8 */
+			AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)	/* lcd_data9.lcd_data9 */
+			AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)	/* lcd_data10.lcd_data10 */
+			AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)	/* lcd_data11.lcd_data11 */
+			AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)	/* lcd_data12.lcd_data12 */
+			AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)	/* lcd_data13.lcd_data13 */
+			AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)	/* lcd_data14.lcd_data14 */
+			AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)	/* lcd_data15.lcd_data15 */
+			AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_vsync.lcd_vsync */
+			AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.lcd_hsync */
+			AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_pclk.lcd_pclk */
+			AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* lcd_ac_bias_en.lcd_ac_bias_en */
+		>;
+	};
+
+
+	user_leds_s0: user_leds_s0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad4.gpio1_4 */
+			AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad5.gpio1_5 */
+			AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad6.gpio1_6 */
+			AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ad7.gpio1_7 */
+		>;
+	};
+
+	gpio_keys_s0: gpio_keys_s0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_oen_ren.gpio2_3 */
+			AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_advn_ale.gpio2_2 */
+			AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_wait0.gpio0_30 */
+			AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_ben0_cle.gpio2_5 */
+		>;
+	};
+
+	i2c0_pins: pinmux_i2c0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	uart0_pins: pinmux_uart0_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
+		>;
+	};
+
+	clkout2_pin: pinmux_clkout2_pin {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
+		>;
+	};
+
+	ecap2_pins: backlight_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x99c, MUX_MODE4)	/* mcasp0_ahclkr.ecap2_in_pwm2_out */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1 */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
+			AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
+			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+
+			/* Slave 2 */
+			AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
+			AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
+			AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+			/* Slave 2 reset value*/
+			AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	mcasp1_pins: mcasp1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+			AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+		>;
+	};
+
+	mcasp1_pins_sleep: mcasp1_pins_sleep {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc2_pins: pinmux_mmc2_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
+			AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+			AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+		>;
+	};
+
+	wl12xx_gpio: pinmux_wl12xx_gpio {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
+		>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: tps@2d {
+		reg = <0x2d>;
+	};
+
+	lis331dlh: lis331dlh@18 {
+		compatible = "st,lis331dlh", "st,lis3lv02d";
+		reg = <0x18>;
+		Vdd-supply = <&lis3_reg>;
+		Vdd_IO-supply = <&lis3_reg>;
+
+		st,click-single-x;
+		st,click-single-y;
+		st,click-single-z;
+		st,click-thresh-x = <10>;
+		st,click-thresh-y = <10>;
+		st,click-thresh-z = <10>;
+		st,irq1-click;
+		st,irq2-click;
+		st,wakeup-x-lo;
+		st,wakeup-x-hi;
+		st,wakeup-y-lo;
+		st,wakeup-y-hi;
+		st,wakeup-z-lo;
+		st,wakeup-z-hi;
+		st,min-limit-x = <120>;
+		st,min-limit-y = <120>;
+		st,min-limit-z = <140>;
+		st,max-limit-x = <550>;
+		st,max-limit-y = <550>;
+		st,max-limit-z = <750>;
+	};
+
+	tlv320aic3106: tlv320aic3106@1b {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3106";
+		reg = <0x1b>;
+		status = "okay";
+
+		/* Regulators */
+		AVDD-supply = <&vaux2_reg>;
+		IOVDD-supply = <&vaux2_reg>;
+		DRVDD-supply = <&vaux2_reg>;
+		DVDD-supply = <&vbat>;
+	};
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+	dr_mode = "host";
+};
+
+&cppi41dma  {
+	status = "okay";
+};
+
+&epwmss2 {
+	status = "okay";
+
+	ecap2: ecap@48304100 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap2_pins>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1312500>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	dual_emac = <1>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rgmii-txid";
+	dual_emac_res_vlan = <2>;
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmc_reg>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&sham {
+	status = "okay";
+};
+
+&aes {
+	status = "okay";
+};
+
+&gpio0 {
+	ti,no-reset-on-init;
+};
+
+&mmc2 {
+	status = "okay";
+	vmmc-supply = <&wl12xx_vmmc>;
+	ti,non-removable;
+	bus-width = <4>;
+	cap-power-off-card;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	wlcore: wlcore@2 {
+		compatible = "ti,wl1271";
+		reg = <2>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
+		ref-clock-frequency = <38400000>;
+	};
+};
+
+&mcasp1 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mcasp1_pins>;
+	pinctrl-1 = <&mcasp1_pins_sleep>;
+
+	status = "okay";
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializers */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		0 0 1 2
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
+&tscadc {
+	status = "okay";
+	tsc {
+		ti,wires = <4>;
+		ti,x-plate-resistance = <200>;
+		ti,coordinate-readouts = <5>;
+		ti,wire-config = <0x00 0x11 0x22 0x33>;
+	};
+};
+
+&lcdc {
+      status = "okay";
+};
diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts
new file mode 100644
index 0000000000..debc6f6132
--- /dev/null
+++ b/arch/arm/dts/am335x-icev2.dts
@@ -0,0 +1,430 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * AM335x ICE V2 board
+ * http://www.ti.com/tool/tmdsice3359
+ */
+
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+	model = "TI AM3359 ICE-V2";
+	compatible = "ti,am3359-icev2", "ti,am33xx";
+
+	chosen {
+		stdout-path = &uart3;
+		tick-timer = &timer2;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	vtt_fixed: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+		regulator-always-on;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	leds@0 {
+		compatible = "gpio-leds";
+
+		led@0 {
+			label = "out0";
+			gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@1 {
+			label = "out1";
+			gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "out2";
+			gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "out3";
+			gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@4 {
+			label = "out4";
+			gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "out5";
+			gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@6 {
+			label = "out6";
+			gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@7 {
+			label = "out7";
+			gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	/* Tricolor status LEDs */
+	leds@1 {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds>;
+
+		led@0 {
+			label = "status0:red:cpu0";
+			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "cpu0";
+		};
+
+		led@1 {
+			label = "status0:green:usr";
+			gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@2 {
+			label = "status0:yellow:usr";
+			gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@3 {
+			label = "status1:red:mmc0";
+			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+			linux,default-trigger = "mmc0";
+		};
+
+		led@4 {
+			label = "status1:green:usr";
+			gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+
+		led@5 {
+			label = "status1:yellow:usr";
+			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+};
+
+&am33xx_pinmux {
+	user_leds: user_leds {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
+			AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
+			AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
+			AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */
+			AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */
+			AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */
+		>;
+	};
+
+	mmc0_pins_default: mmc0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */
+		>;
+	};
+
+	i2c0_pins_default: i2c0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */
+			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */
+		>;
+	};
+
+	spi0_pins_default: spi0_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */
+			AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */
+		>;
+	};
+
+	uart3_pins_default: uart3_pins_default {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */
+			AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			/* Slave 1, RMII mode */
+			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_crs.rmii1_crs_dv */
+			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))	/* rmii1_refclk.rmii1_refclk */
+			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))	/* mii1_txen.rmii1_txen */
+			/* Slave 2, RMII mode */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wait0.rmii2_crs_dv */
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))	/* mii1_col.rmii2_refclk */
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a11.rmii2_rxd0 */
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_a10.rmii2_rxd1 */
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))	/* gpmc_wpn.rmii2_rxerr */
+			AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a5.rmii2_txd0 */
+			AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a4.rmii2_txd1 */
+			AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))	/* gpmc_a0.rmii2_txen */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			/* Slave 1 reset value */
+			AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+
+			/* Slave 2 reset value */
+			AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+			AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins_default>;
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	tps: power-controller@2d {
+		reg = <0x2d>;
+	};
+
+	tpic2810: gpio@60 {
+		compatible = "ti,tpic2810";
+		reg = <0x60>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+};
+
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vbat>;
+	vcc2-supply = <&vbat>;
+	vcc3-supply = <&vbat>;
+	vcc4-supply = <&vbat>;
+	vcc5-supply = <&vbat>;
+	vcc6-supply = <&vbat>;
+	vcc7-supply = <&vbat>;
+	vccio-supply = <&vbat>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1326000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-always-on;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmc_reg>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins_default>;
+};
+
+&gpio0 {
+	/* Do not idle the GPIO used for holding the VTT regulator */
+	ti,no-reset-on-init;
+	ti,no-idle-on-init;
+
+	p7 {
+		gpio-hog;
+		gpios = <7 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "FET_SWITCH_CTRL";
+	};
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins_default>;
+	status = "okay";
+};
+
+&gpio3 {
+	p4 {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "PR1_MII_CTRL";
+	};
+
+	p10 {
+		gpio-hog;
+		gpios = <10 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "MUX_MII_CTRL";
+	};
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <3>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <2>;
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+	dual_emac;
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+	reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
+};
diff --git a/arch/arm/dts/am4372.dtsi b/arch/arm/dts/am4372.dtsi
index c95d1d3b35..3ffa8e016e 100644
--- a/arch/arm/dts/am4372.dtsi
+++ b/arch/arm/dts/am4372.dtsi
@@ -547,6 +547,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			ranges;
 
 			davinci_mdio: mdio@4a101000 {
diff --git a/arch/arm/dts/am437x-idk-evm.dts b/arch/arm/dts/am437x-idk-evm.dts
new file mode 100644
index 0000000000..478f0a62cb
--- /dev/null
+++ b/arch/arm/dts/am437x-idk-evm.dts
@@ -0,0 +1,420 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "TI AM437x Industrial Development Kit";
+	compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	v24_0d: fixed-regulator-v24_0d {
+		compatible = "regulator-fixed";
+		regulator-name = "V24_0D";
+		regulator-min-microvolt = <24000000>;
+		regulator-max-microvolt = <24000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	v3_3d: fixed-regulator-v3_3d {
+		compatible = "regulator-fixed";
+		regulator-name = "V3_3D";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	vdd_corereg: fixed-regulator-vdd_corereg {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_COREREG";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	vdd_core: fixed-regulator-vdd_core {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_CORE";
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1100000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&vdd_corereg>;
+	};
+
+	v1_8dreg: fixed-regulator-v1_8dreg{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_8DREG";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	v1_8d: fixed-regulator-v1_8d{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_8D";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v1_8dreg>;
+	};
+
+	v1_5dreg: fixed-regulator-v1_5dreg{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_5DREG";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v24_0d>;
+	};
+
+	v1_5d: fixed-regulator-v1_5d{
+		compatible = "regulator-fixed";
+		regulator-name = "V1_5D";
+		regulator-min-microvolt = <1500000>;
+		regulator-max-microvolt = <1500000>;
+		regulator-always-on;
+		regulator-boot-on;
+		vin-supply = <&v1_5dreg>;
+	};
+
+	gpio_keys: gpio_keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&gpio_keys_pins_default>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch@0 {
+			label = "power-button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	/* fixed 32k external oscillator clock */
+	clk_32k_rtc: clk_32k_rtc {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+	};
+};
+
+&am43xx_pinmux {
+	gpio_keys_pins_default: gpio_keys_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9b8, PIN_INPUT | MUX_MODE7)	/* cam0_field.gpio4_2 */
+		>;
+	};
+
+	i2c0_pins_default: i2c0_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+			AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+		>;
+	};
+
+	i2c0_pins_sleep: i2c0_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x98c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	i2c2_pins_default: i2c2_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9e8, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data1.i2c2_scl */
+			AM4372_IOPAD(0x9ec, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE3) /* cam1_data0.i2c2_sda */
+		>;
+	};
+
+	i2c2_pins_sleep: i2c2_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x9e8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9ec, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	mmc1_pins_default: pinmux_mmc1_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+			AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+			AM4372_IOPAD(0x9f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+			AM4372_IOPAD(0x9f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+			AM4372_IOPAD(0x9f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+			AM4372_IOPAD(0x9fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+			AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+		>;
+	};
+
+	mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x900, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x904, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9f8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x9fc, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x960, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	ecap0_pins_default: backlight_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
+		>;
+	};
+
+	cpsw_default: cpsw_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
+			AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
+			AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
+			AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
+			AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td2 */
+			AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td3 */
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rmii1_rclk */
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd2 */
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd3 */
+		>;
+	};
+
+	cpsw_sleep: cpsw_sleep {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	davinci_mdio_default: davinci_mdio_default {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+
+	davinci_mdio_sleep: davinci_mdio_sleep {
+		pinctrl-single,pins = <
+			/* MDIO reset value */
+			AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+
+	qspi_pins_default: qspi_pins_default {
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE3)	/* gpmc_csn0.qspi_csn */
+			AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2)		/* gpmc_csn3.qspi_clk */
+			AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_advn_ale.qspi_d0 */
+			AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_oen_ren.qspi_d1 */
+			AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_wen.qspi_d2 */
+			AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_be0n_cle.qspi_d3 */
+		>;
+	};
+
+	qspi_pins_sleep: qspi_pins_sleep{
+		pinctrl-single,pins = <
+			AM4372_IOPAD(0x87c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x898, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			AM4372_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c0_pins_default>;
+	pinctrl-1 = <&i2c0_pins_sleep>;
+	clock-frequency = <400000>;
+
+	at24@50 {
+		compatible = "at24,24c256";
+		pagesize = <64>;
+		reg = <0x50>;
+	};
+
+	tps: tps62362@60 {
+		compatible = "ti,tps62362";
+		reg = <0x60>;
+		regulator-name = "VDD_MPU";
+		regulator-min-microvolt = <950000>;
+		regulator-max-microvolt = <1330000>;
+		regulator-boot-on;
+		regulator-always-on;
+		ti,vsel0-state-high;
+		ti,vsel1-state-high;
+		vin-supply = <&v3_3d>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&i2c2_pins_default>;
+	pinctrl-1 = <&i2c2_pins_sleep>;
+	clock-frequency = <100000>;
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&ecap0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ecap0_pins_default>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&mmc1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mmc1_pins_default>;
+	pinctrl-1 = <&mmc1_pins_sleep>;
+	vmmc-supply = <&v3_3d>;
+	bus-width = <4>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&qspi {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&qspi_pins_default>;
+	pinctrl-1 = <&qspi_pins_sleep>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * MTD partition table.  The ROM checks the first 512KiB for a
+		 * valid file to boot(XIP).
+		 */
+		partition@0 {
+			label = "QSPI.U_BOOT";
+			reg = <0x00000000 0x000080000>;
+		};
+		partition@1 {
+			label = "QSPI.U_BOOT.backup";
+			reg = <0x00080000 0x00080000>;
+		};
+		partition@2 {
+			label = "QSPI.U-BOOT-SPL_OS";
+			reg = <0x00100000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.U_BOOT_ENV";
+			reg = <0x00110000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.U-BOOT-ENV.backup";
+			reg = <0x00120000 0x00010000>;
+		};
+		partition@5 {
+			label = "QSPI.KERNEL";
+			reg = <0x00130000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.FILESYSTEM";
+			reg = <0x00930000 0x36D0000>;
+		};
+	};
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <0>;
+	phy-mode = "rgmii";
+};
+
+&rtc {
+	clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+	clock-names = "ext-clk", "int-clk";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&cpu {
+	cpu0-supply = <&tps>;
+};
diff --git a/arch/arm/dts/am43x-epos-evm.dts b/arch/arm/dts/am43x-epos-evm.dts
new file mode 100644
index 0000000000..fa4d1e3f32
--- /dev/null
+++ b/arch/arm/dts/am43x-epos-evm.dts
@@ -0,0 +1,806 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+#include <dt-bindings/pinctrl/am43xx.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
+
+/ {
+	model = "TI AM43x EPOS EVM";
+	compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43";
+
+	aliases {
+		display0 = &lcd0;
+	};
+
+	chosen {
+		stdout-path = &uart0;
+		tick-timer = &timer2;
+	};
+
+	vmmcsd_fixed: fixedregulator-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmcsd_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+	};
+
+	vbat: fixedregulator@0 {
+		compatible = "regulator-fixed";
+		regulator-name = "vbat";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+	};
+
+	lcd0: display {
+		compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
+		label = "lcd";
+
+		panel-timing {
+			clock-frequency = <33000000>;
+			hactive = <800>;
+			vactive = <480>;
+			hfront-porch = <210>;
+			hback-porch = <16>;
+			hsync-len = <30>;
+			vback-porch = <10>;
+			vfront-porch = <22>;
+			vsync-len = <13>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <1>;
+		};
+
+		port {
+			lcd_in: endpoint {
+				remote-endpoint = <&dpi_out>;
+			};
+		};
+	};
+
+	matrix_keypad: matrix_keypad@0 {
+		compatible = "gpio-matrix-keypad";
+		debounce-delay-ms = <5>;
+		col-scan-delay-us = <2>;
+
+		row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH		/* Bank0, pin12 */
+			     &gpio0 13 GPIO_ACTIVE_HIGH		/* Bank0, pin13 */
+			     &gpio0 14 GPIO_ACTIVE_HIGH		/* Bank0, pin14 */
+			     &gpio0 15 GPIO_ACTIVE_HIGH>;	/* Bank0, pin15 */
+
+		col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH		/* Bank3, pin9 */
+			     &gpio3 10 GPIO_ACTIVE_HIGH		/* Bank3, pin10 */
+			     &gpio2 18 GPIO_ACTIVE_HIGH		/* Bank2, pin18 */
+			     &gpio2 19 GPIO_ACTIVE_HIGH>;	/* Bank2, pin19 */
+
+		linux,keymap = <0x00000201	/* P1 */
+			0x01000204	/* P4 */
+			0x02000207	/* P7 */
+			0x0300020a	/* NUMERIC_STAR */
+			0x00010202	/* P2 */
+			0x01010205	/* P5 */
+			0x02010208	/* P8 */
+			0x03010200	/* P0 */
+			0x00020203	/* P3 */
+			0x01020206	/* P6 */
+			0x02020209	/* P9 */
+			0x0302020b	/* NUMERIC_POUND */
+			0x00030067	/* UP */
+			0x0103006a	/* RIGHT */
+			0x0203006c	/* DOWN */
+			0x03030069>;	/* LEFT */
+	};
+
+	backlight {
+		compatible = "pwm-backlight";
+		pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
+		brightness-levels = <0 51 53 56 62 75 101 152 255>;
+		default-brightness-level = <8>;
+	};
+
+	sound0: sound@0 {
+		compatible = "simple-audio-card";
+		simple-audio-card,name = "AM43-EPOS-EVM";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Speaker", "Speaker";
+		simple-audio-card,routing =
+			"MIC1LP", "Microphone Jack",
+			"MIC1RP", "Microphone Jack",
+			"MIC1LP", "MICBIAS",
+			"MIC1RP", "MICBIAS",
+			"Headphone Jack", "HPL",
+			"Headphone Jack", "HPR",
+			"Speaker", "SPL",
+			"Speaker", "SPR";
+		simple-audio-card,format = "dsp_b";
+		simple-audio-card,bitclock-master = <&sound0_master>;
+		simple-audio-card,frame-master = <&sound0_master>;
+		simple-audio-card,bitclock-inversion;
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp1>;
+			system-clock-frequency = <12000000>;
+		};
+
+		sound0_master: simple-audio-card,codec {
+			sound-dai = <&tlv320aic3111>;
+			system-clock-frequency = <12000000>;
+		};
+	};
+};
+
+&am43xx_pinmux {
+		cpsw_default: cpsw_default {
+			pinctrl-single,pins = <
+				/* Slave 1 */
+				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs */
+				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+				AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txen.rmii1_txen */
+				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxdv.rmii1_rxdv */
+				AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd1.rmii1_txd1 */
+				AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_txd0.rmii1_txd0 */
+				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+			>;
+		};
+
+		cpsw_sleep: cpsw_sleep {
+			pinctrl-single,pins = <
+				/* Slave 1 reset value */
+				AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+
+		davinci_mdio_default: davinci_mdio_default {
+			pinctrl-single,pins = <
+				/* MDIO */
+				AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+				AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+			>;
+		};
+
+		davinci_mdio_sleep: davinci_mdio_sleep {
+			pinctrl-single,pins = <
+				/* MDIO reset value */
+				AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+
+		i2c0_pins: pinmux_i2c0_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+				AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+			>;
+		};
+
+		nand_flash_x8: nand_flash_x8 {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.SELQSPIorNAND/GPIO */
+				AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+				AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+				AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+				AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+				AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+				AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+				AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+				AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+				AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+				AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpmc_wpn */
+				AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+				AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+				AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+				AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+				AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+			>;
+		};
+
+		ecap0_pins: backlight_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x964, MUX_MODE0)         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+			>;
+		};
+
+		i2c2_pins: pinmux_i2c2_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
+				AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
+			>;
+		};
+
+		spi0_pins: pinmux_spi0_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
+				AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
+				AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
+				AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
+			>;
+		};
+
+		spi1_pins: pinmux_spi1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
+				AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
+				AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
+				AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
+			>;
+		};
+
+		mmc1_pins: pinmux_mmc1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
+			>;
+		};
+
+		qspi1_default: qspi1_default {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2)
+				AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3)
+				AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3)
+			>;
+		};
+
+		pixcir_ts_pins: pixcir_ts_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_a1.gpio1_17 */
+			>;
+		};
+
+		hdq_pins: pinmux_hdq_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
+			>;
+		};
+
+		dss_pins: dss_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
+				AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
+				AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
+				AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
+				AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
+				AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
+				AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
+				AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
+				AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
+				AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
+			>;
+		};
+
+		display_mux_pins: display_mux_pins {
+			pinctrl-single,pins = <
+				/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
+				AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7)
+			>;
+		};
+
+		vpfe1_pins_default: vpfe1_pins_default {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0 */
+				AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0 */
+				AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0 */
+				AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0 */
+				AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0 */
+				AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0 */
+				AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0 */
+				AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0 */
+				AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0 */
+				AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0 */
+				AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0 */
+				AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0 */
+				AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0 */
+			>;
+		};
+
+		vpfe1_pins_sleep: vpfe1_pins_sleep {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+				AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
+			>;
+		};
+
+		mcasp1_pins: mcasp1_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
+				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
+				AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
+				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
+			>;
+		};
+
+		mcasp1_sleep_pins: mcasp1_sleep_pins {
+			pinctrl-single,pins = <
+				AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)
+				AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7)
+			>;
+		};
+};
+
+&mmc1 {
+	status = "okay";
+	vmmc-supply = <&vmmcsd_fixed>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};
+
+&mac {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&cpsw_default>;
+	pinctrl-1 = <&cpsw_sleep>;
+	status = "okay";
+};
+
+&davinci_mdio {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&davinci_mdio_default>;
+	pinctrl-1 = <&davinci_mdio_sleep>;
+	status = "okay";
+};
+
+&cpsw_emac0 {
+	phy_id = <&davinci_mdio>, <16>;
+	phy-mode = "rmii";
+};
+
+&cpsw_emac1 {
+	phy_id = <&davinci_mdio>, <1>;
+	phy-mode = "rmii";
+};
+
+&phy_sel {
+	rmii-clock-ext;
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+
+	tps65218: tps65218@24 {
+		reg = <0x24>;
+		compatible = "ti,tps65218";
+		interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		dcdc1: regulator-dcdc1 {
+			compatible = "ti,tps65218-dcdc1";
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1144000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc2: regulator-dcdc2 {
+			compatible = "ti,tps65218-dcdc2";
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc3: regulator-dcdc3 {
+			compatible = "ti,tps65218-dcdc3";
+			regulator-name = "vdcdc3";
+			regulator-min-microvolt = <1500000>;
+			regulator-max-microvolt = <1500000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc4: regulator-dcdc4 {
+			compatible = "ti,tps65218-dcdc4";
+			regulator-name = "vdcdc4";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		dcdc5: regulator-dcdc5 {
+			compatible = "ti,tps65218-dcdc5";
+			regulator-name = "v1_0bat";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+		};
+
+		dcdc6: regulator-dcdc6 {
+			compatible = "ti,tps65218-dcdc6";
+			regulator-name = "v1_8bat";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		ldo1: regulator-ldo1 {
+			compatible = "ti,tps65218-ldo1";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+
+	at24@50 {
+		compatible = "at24,24c256";
+		pagesize = <64>;
+		reg = <0x50>;
+	};
+
+	pixcir_ts@5c {
+		compatible = "pixcir,pixcir_tangoc";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pixcir_ts_pins>;
+		reg = <0x5c>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
+
+		attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+
+		touchscreen-size-x = <1024>;
+		touchscreen-size-y = <600>;
+	};
+
+	tlv320aic3111: tlv320aic3111@18 {
+		#sound-dai-cells = <0>;
+		compatible = "ti,tlv320aic3111";
+		reg = <0x18>;
+		status = "okay";
+
+		ai31xx-micbias-vg = <MICBIAS_2_0V>;
+
+		/* Regulators */
+		HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+		SPRVDD-supply = <&vbat>; /* vbat */
+		SPLVDD-supply = <&vbat>; /* vbat */
+		AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+		IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
+		DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
+	};
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&display_mux_pins>;
+	status = "okay";
+
+	p1 {
+		/*
+		 * SelLCDorHDMI selects between display and audio paths:
+		 * Low: HDMI display with audio via HDMI
+		 * High: LCD display with analog audio via aic3111 codec
+		 */
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "SelLCDorHDMI";
+	};
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";	/* Disable QSPI when enabling GPMC (NAND) */
+	pinctrl-names = "default";
+	pinctrl-0 = <&nand_flash_x8>;
+	ranges = <0 0 0x08000000 0x01000000>;	/* CS0 space. Min partition = 16MB */
+	nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		ti,nand-ecc-opt = "bch16";
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
+		gpmc,cs-wr-off-ns = <40>;
+		gpmc,adv-on-ns = <0>;  /* cs-on-ns */
+		gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
+		gpmc,we-on-ns = <0>;   /* cs-on-ns */
+		gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
+		gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
+		gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
+		gpmc,access-ns = <30>; /* tCEA + 4*/
+		gpmc,rd-cycle-ns = <40>;
+		gpmc,wr-cycle-ns = <40>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <40>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x00040000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00040000 0x00040000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00080000 0x00040000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x000C0000 0x00040000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot-spl-os";
+			reg = <0x00100000 0x00080000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot";
+			reg = <0x00180000 0x00100000>;
+		};
+		partition@6 {
+			label = "NAND.u-boot-env";
+			reg = <0x00280000 0x00040000>;
+		};
+		partition@7 {
+			label = "NAND.u-boot-env.backup1";
+			reg = <0x002C0000 0x00040000>;
+		};
+		partition@8 {
+			label = "NAND.kernel";
+			reg = <0x00300000 0x00700000>;
+		};
+		partition@9 {
+			label = "NAND.file-system";
+			reg = <0x00a00000 0x1f600000>;
+		};
+	};
+};
+
+&epwmss0 {
+	status = "okay";
+};
+
+&tscadc {
+	status = "okay";
+
+	adc {
+		ti,adc-channels = <0 1 2 3 4 5 6 7>;
+	};
+};
+
+&ecap0 {
+		status = "okay";
+		pinctrl-names = "default";
+		pinctrl-0 = <&ecap0_pins>;
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi1_pins>;
+	status = "okay";
+};
+
+&usb2_phy1 {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "peripheral";
+	status = "okay";
+};
+
+&usb2_phy2 {
+	status = "okay";
+};
+
+&usb2 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&qspi {
+	status = "disabled";	/* Disable GPMC (NAND) when enabling QSPI */
+	pinctrl-names = "default";
+	pinctrl-0 = <&qspi1_default>;
+
+	spi-max-frequency = <48000000>;
+	m25p80@0 {
+		compatible = "mx66l51235l";
+		spi-max-frequency = <48000000>;
+		reg = <0>;
+		spi-cpol;
+		spi-cpha;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* MTD partition table.
+		 * The ROM checks the first 512KiB
+		 * for a valid file to boot(XIP).
+		 */
+		partition@0 {
+			label = "QSPI.U_BOOT";
+			reg = <0x00000000 0x000080000>;
+		};
+		partition@1 {
+			label = "QSPI.U_BOOT.backup";
+			reg = <0x00080000 0x00080000>;
+		};
+		partition@2 {
+			label = "QSPI.U-BOOT-SPL_OS";
+			reg = <0x00100000 0x00010000>;
+		};
+		partition@3 {
+			label = "QSPI.U_BOOT_ENV";
+			reg = <0x00110000 0x00010000>;
+		};
+		partition@4 {
+			label = "QSPI.U-BOOT-ENV.backup";
+			reg = <0x00120000 0x00010000>;
+		};
+		partition@5 {
+			label = "QSPI.KERNEL";
+			reg = <0x00130000 0x0800000>;
+		};
+		partition@6 {
+			label = "QSPI.FILESYSTEM";
+			reg = <0x00930000 0x36D0000>;
+		};
+	};
+};
+
+&hdq {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdq_pins>;
+};
+
+&dss {
+	status = "ok";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&dss_pins>;
+
+	port {
+		dpi_out: endpoint@0 {
+			remote-endpoint = <&lcd_in>;
+			data-lines = <24>;
+		};
+	};
+};
+
+&vpfe1 {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&vpfe1_pins_default>;
+	pinctrl-1 = <&vpfe1_pins_sleep>;
+
+	port {
+		vpfe1_ep: endpoint {
+			/* remote-endpoint = <&sensor>; add once we have it */
+			ti,am437x-vpfe-interface = <0>;
+			bus-width = <8>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+		};
+	};
+};
+
+&mcasp1 {
+	#sound-dai-cells = <0>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&mcasp1_pins>;
+	pinctrl-1 = <&mcasp1_sleep_pins>;
+
+	status = "okay";
+
+	op-mode = <0>;          /* MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	/* 4 serializer */
+	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
+		1 2 0 0
+	>;
+	tx-num-evt = <32>;
+	rx-num-evt = <32>;
+};
+
+&synctimer_32kclk {
+	assigned-clocks = <&mux_synctimer32k_ck>;
+	assigned-clock-parents = <&clkdiv32k_ick>;
+};
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi
index e7fecf7656..0f242e6489 100644
--- a/arch/arm/dts/dra7.dtsi
+++ b/arch/arm/dts/dra7.dtsi
@@ -1411,7 +1411,7 @@
 			ti,irqs-safe-map = <0>;
 		};
 
-		mac: ethernet@4a100000 {
+		mac: ethernet@48484000 {
 			compatible = "ti,cpsw";
 			ti,hwmods = "gmac";
 			clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
@@ -1426,6 +1426,7 @@
 			active_slave = <0>;
 			cpts_clock_mult = <0x80000000>;
 			cpts_clock_shift = <29>;
+			syscon = <&scm_conf>;
 			reg = <0x48484000 0x1000
 			       0x48485200 0x2E00>;
 			#address-cells = <1>;
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 179584c748..8650800f52 100644
--- a/arch/arm/dts/exynos5.dtsi
+++ b/arch/arm/dts/exynos5.dtsi
@@ -163,13 +163,14 @@
 	};
 
 	fimd@14400000 {
+		u-boot,dm-pre-reloc;
 		compatible = "samsung,exynos-fimd";
 		reg = <0x14400000 0x10000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 	};
 
-	dp@145b0000 {
+	dp: dp@145b0000 {
 		compatible = "samsung,exynos5-dp";
 		reg = <0x145b0000 0x1000>;
 		#address-cells = <1>;
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index bda5499988..29c13c1257 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -198,6 +198,20 @@
 			reset-gpios = <&gpx1 5 GPIO_ACTIVE_LOW>;
 			hotplug-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 			edid-emulation = <5>;
+
+			ports {
+				port@0 {
+					bridge_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+
+				port@1 {
+					bridge_in: endpoint {
+						remote-endpoint = <&dp_out>;
+					};
+				};
+			};
 		};
 
 		soundcodec@22 {
@@ -223,6 +237,27 @@
 		};
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+		power-supply = <&fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
+
 	spi@131b0000 {
 		spi-max-frequency = <1000000>;
 		spi-deactivate-delay = <100>;
@@ -337,6 +372,15 @@
 		samsung,dynamic-range = <0>;
 		samsung,ycbcr-coeff = <0>;
 		samsung,color-depth = <1>;
+		samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+
+		ports {
+			port@0 {
+				dp_out: endpoint {
+					remote-endpoint = <&bridge_in>;
+				};
+			};
+		};
 	};
 
 };
diff --git a/arch/arm/dts/exynos5250-spring.dts b/arch/arm/dts/exynos5250-spring.dts
index 81b3d29f9c..693501e4c1 100644
--- a/arch/arm/dts/exynos5250-spring.dts
+++ b/arch/arm/dts/exynos5250-spring.dts
@@ -158,6 +158,27 @@
 		samsung,ycbcr-coeff = <0>;
 		samsung,color-depth = <1>;
 	};
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <1>;
+		enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>;
+		power-supply = <&fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
 };
 
 &i2c_0 {
@@ -385,6 +406,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x0a>;
+	samsung,lane-count = <1>;
+	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port@0 {
+			dp_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &i2c_1 {
 	status = "okay";
 	samsung,i2c-sda-delay = <100>;
@@ -585,6 +625,19 @@
 			0x04 0x59 0x60 /* MPU Clock source: LC => RCO */
 			0x04 0x54 0x14 /* LC -> RCO */
 			0x02 0xa1 0x91>; /* HPD high */
+		ports {
+			port@0 {
+				bridge_out: endpoint {
+					remote-endpoint = <&panel_in>;
+				};
+			};
+
+			port@1 {
+				bridge_in: endpoint {
+					remote-endpoint = <&dp_out>;
+				};
+			};
+		};
 	};
 
 	soundcodec@20 {
diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi
index 7eef3e3f4f..d44c9f647e 100644
--- a/arch/arm/dts/exynos5250.dtsi
+++ b/arch/arm/dts/exynos5250.dtsi
@@ -116,4 +116,11 @@
 		};
 	};
 
+	pwm: pwm@12dd0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x12dd0000 0x100>;
+		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+		#pwm-cells = <3>;
+	};
+
 };
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 16d52f4928..2db4ad2dbd 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -9,6 +9,8 @@
 
 /dts-v1/;
 #include "exynos54xx.dtsi"
+#include <dt-bindings/clock/maxim,max77802.h>
+#include <dt-bindings/regulator/maxim,max77802.h>
 
 / {
 	model = "Samsung/Google Peach Pit board based on Exynos5420";
@@ -29,6 +31,14 @@
 		i2c104 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		power-supply = <&tps65090_fet1>;
+	};
+
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -188,6 +198,20 @@
 				0x04 0x59 0x60
 				0x04 0x54 0x14  /* LC -> RCO */
 				0x02 0xa1 0x91>;  /* HPD high */
+
+			ports {
+				port@0 {
+					bridge_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+
+				port@1 {
+					bridge_in: endpoint {
+						remote-endpoint = <&dp_out>;
+					};
+				};
+			};
 	        };
 	};
 
@@ -203,6 +227,18 @@
 		};
 	};
 
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&tps65090_fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
+		};
+	};
+
 	spi@12d30000 { /* spi1 */
 		spi-max-frequency = <50000000>;
 		firmware_storage_spi: flash@0 {
@@ -254,6 +290,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x06>;
+	samsung,lane-count = <2>;
+	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port@0 {
+			dp_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &spi_2 {
 	spi-max-frequency = <3125000>;
 	spi-deactivate-delay = <200>;
diff --git a/arch/arm/dts/exynos54xx.dtsi b/arch/arm/dts/exynos54xx.dtsi
index daa6a33c5b..b4ddf53a2e 100644
--- a/arch/arm/dts/exynos54xx.dtsi
+++ b/arch/arm/dts/exynos54xx.dtsi
@@ -49,7 +49,7 @@
 		status = "disabled";
 	};
 
-	i2c@12CA0000 {
+	hsi2c_4: i2c@12CA0000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 		compatible = "samsung,exynos5-hsi2c";
@@ -178,7 +178,7 @@
 		samsung,pwm-out-gpio = <&gpb2 0 GPIO_ACTIVE_HIGH>;
 	};
 
-	dp@145b0000 {
+	dp: dp@145b0000 {
 		samsung,lt-status = <0>;
 
 		samsung,master-mode = <0>;
@@ -197,6 +197,13 @@
 		mem-type = "ddr3";
 	};
 
+	pwm: pwm@12dd0000 {
+		compatible = "samsung,exynos4210-pwm";
+		reg = <0x12dd0000 0x100>;
+		samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+		#pwm-cells = <3>;
+	};
+
 	xhci1: xhci@12400000 {
 		compatible = "samsung,exynos5250-xhci";
 		reg = <0x12400000 0x10000>;
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 76826dc23b..4c139bf143 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -30,6 +30,27 @@
 		i2c104 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>;
+		power-supply = <&tps65090_fet1>;
+	};
+
+	panel: panel {
+		compatible = "auo,b133htn01";
+		power-supply = <&tps65090_fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&dp_out>;
+			};
+		};
+	};
+
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -132,6 +153,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x0a>;
+	samsung,lane-count = <2>;
+	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port {
+			dp_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
 &spi_2 {
 	spi-max-frequency = <3125000>;
 	spi-deactivate-delay = <200>;
diff --git a/arch/arm/dts/exynos7420-espresso7420.dts b/arch/arm/dts/exynos7420-espresso7420.dts
new file mode 100644
index 0000000000..f17a8482ff
--- /dev/null
+++ b/arch/arm/dts/exynos7420-espresso7420.dts
@@ -0,0 +1,24 @@
+/*
+ * Samsung Espresso7420 board device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "exynos7420.dtsi"
+/ {
+	model = "Samsung Espresso7420 board based on Exynos7420";
+	compatible = "samsung,espresso7420", "samsung,exynos7420";
+
+	aliases {
+		serial2 = "/serial@14C30000";
+		console = "/serial@14C30000";
+		pinctrl0 = "/pinctrl@13470000";
+	};
+};
+
+&fin_pll {
+	clock-frequency = <24000000>;
+};
diff --git a/arch/arm/dts/exynos7420.dtsi b/arch/arm/dts/exynos7420.dtsi
new file mode 100644
index 0000000000..b398021e30
--- /dev/null
+++ b/arch/arm/dts/exynos7420.dtsi
@@ -0,0 +1,83 @@
+/*
+ * Samsung Exynos7420 SoC device tree source
+ *
+ * Copyright (c) 2016 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos7420-clk.h>
+/ {
+	compatible = "samsung,exynos7420";
+
+	fin_pll: xxti {
+		compatible = "fixed-clock";
+		clock-output-names = "fin_pll";
+		u-boot,dm-pre-reloc;
+		#clock-cells = <0>;
+	};
+
+	clock_topc: clock-controller@10570000 {
+		compatible = "samsung,exynos7-clock-topc";
+		reg = <0x10570000 0x10000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>;
+		clock-names = "fin_pll";
+	};
+
+	clock_top0: clock-controller@105d0000 {
+		compatible = "samsung,exynos7-clock-top0";
+		reg = <0x105d0000 0xb000>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
+			 <&clock_topc DOUT_SCLK_BUS1_PLL>,
+			 <&clock_topc DOUT_SCLK_CC_PLL>,
+			 <&clock_topc DOUT_SCLK_MFC_PLL>;
+		clock-names = "fin_pll", "dout_sclk_bus0_pll",
+			      "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
+			      "dout_sclk_mfc_pll";
+	};
+
+	clock_peric1: clock-controller@14c80000 {
+		compatible = "samsung,exynos7-clock-peric1";
+		reg = <0x14c80000 0xd00>;
+		u-boot,dm-pre-reloc;
+		#clock-cells = <1>;
+		clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
+			 <&clock_top0 CLK_SCLK_UART1>,
+			 <&clock_top0 CLK_SCLK_UART2>,
+			 <&clock_top0 CLK_SCLK_UART3>;
+		clock-names = "fin_pll", "dout_aclk_peric1_66",
+			      "sclk_uart1", "sclk_uart2", "sclk_uart3";
+	};
+
+	pinctrl@13470000 {
+		compatible = "samsung,exynos7420-pinctrl";
+		reg = <0x13470000 0x1000>;
+		u-boot,dm-pre-reloc;
+
+		serial2_bus: serial2-bus {
+			samsung,pins = "gpd1-4", "gpd1-5";
+			samsung,pin-function = <2>;
+			samsung,pin-pud = <3>;
+			samsung,pin-drv = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	serial@14C30000 {
+		compatible = "samsung,exynos4210-uart";
+		reg = <0x14C30000 0x100>;
+		u-boot,dm-pre-reloc;
+		clocks = <&clock_peric1 PCLK_UART2>,
+			 <&clock_peric1 SCLK_UART2>;
+		clock-names = "uart", "clk_uart_baud0";
+		pinctrl-names = "default";
+		pinctrl-0 = <&serial2_bus>;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dts b/arch/arm/dts/fsl-ls1012a-frdm.dts
new file mode 100644
index 0000000000..983e599b9b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1012a-frdm.dtsi b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
new file mode 100644
index 0000000000..25dcdd2929
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-frdm.dtsi
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A FREEDOM Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts
new file mode 100644
index 0000000000..76db36ca39
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi
new file mode 100644
index 0000000000..dde7134626
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A QDS Board";
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi0;
+	};
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
+	dflash1: sst25wf040b {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <1>;
+	};
+
+	dflash2: en25s64 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <2>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547@77 {
+		compatible = "philips,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				/* IRQ10_B */
+				interrupts = <0 150 0x4>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+
+			ina220@41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			eeprom@56 {
+				compatible = "at24,24c512";
+				reg = <0x56>;
+			};
+
+			eeprom@57 {
+				compatible = "at24,24c512";
+				reg = <0x57>;
+			};
+
+			adt7461a@4c {
+				compatible = "adt7461a";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts
new file mode 100644
index 0000000000..f683812c30
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts
@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
new file mode 100644
index 0000000000..bf407aeb94
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A RDB Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
new file mode 100644
index 0000000000..546a87a0a5
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+	compatible = "fsl,ls1012a";
+	interrupt-parent = <&gic>;
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			clocks = <&clockgen 1 0>;
+		};
+
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	gic: interrupt-controller@1400000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+		      <0x0 0x1402000 0 0x2000>, /* GICC */
+		      <0x0 0x1404000 0 0x2000>, /* GICH */
+		      <0x0 0x1406000 0 0x2000>; /* GICV */
+		interrupts = <1 9 0xf08>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1ee1000 {
+			compatible = "fsl,ls1012a-clockgen";
+			reg = <0x0 0x1ee1000 0x0 0x1000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <0 64 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+
+		i2c0: i2c@2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <0 56 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <0 57 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		duart0: serial@21c0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0500 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart1: serial@21c0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0600 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		qspi: quadspi@1550000 {
+			compatible = "fsl,vf610-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			num-cs = <2>;
+			big-endian;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 66b409a05c..bf1dfe6db6 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -240,8 +240,9 @@
 			compatible = "fsl,vf610-qspi";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0x1550000 0x10000>,
-				<0x40000000 0x4000000>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
 			num-cs = <2>;
 			big-endian;
 			status = "disabled";
diff --git a/arch/arm/dts/meson-gxbb-odroidc2.dts b/arch/arm/dts/meson-gxbb-odroidc2.dts
new file mode 100644
index 0000000000..653c2fa785
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb-odroidc2.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ * Copyright (c) 2016 BayLibre, Inc.
+ * Author: Kevin Hilman <khilman@kernel.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxbb.dtsi"
+
+/ {
+	compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
+	model = "Hardkernel ODROID-C2";
+
+	aliases {
+		serial0 = &uart_AO;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>;
+	};
+};
+
+&uart_AO {
+	status = "okay";
+};
diff --git a/arch/arm/dts/meson-gxbb.dtsi b/arch/arm/dts/meson-gxbb.dtsi
new file mode 100644
index 0000000000..832815d804
--- /dev/null
+++ b/arch/arm/dts/meson-gxbb.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "amlogic,meson-gxbb";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <0x2>;
+		#size-cells = <0x0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_EDGE_RISING)>;
+	};
+
+	xtal: xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cbus: cbus@c1100000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xc1100000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
+
+			uart_A: serial@84c0 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x084c0 0x0 0x14>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+		};
+
+		gic: interrupt-controller@c4301000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xc4301000 0 0x1000>,
+			      <0x0 0xc4302000 0 0x2000>,
+			      <0x0 0xc4304000 0 0x2000>,
+			      <0x0 0xc4306000 0 0x2000>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9
+				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+		};
+
+		aobus: aobus@c8100000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xc8100000 0x0 0x100000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
+
+			uart_AO: serial@4c0 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x004c0 0x0 0x14>;
+				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+		};
+
+		apb: apb@d0000000 {
+			compatible = "simple-bus";
+			reg = <0x0 0xd0000000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
+		};
+	};
+};
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
index 5aec1b82bd..072eaa6116 100644
--- a/arch/arm/dts/rk3288-firefly.dtsi
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -146,6 +146,22 @@
 	status = "okay";
 };
 
+&gmac {
+	assigned-clocks = <&cru SCLK_MAC>;
+	assigned-clock-parents = <&ext_gmac>;
+	clock_in_out = "input";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+	phy-supply = <&vcc_lan>;
+	phy-mode = "rgmii";
+	snps,reset-active-low;
+	snps,reset-delays-us = <0 10000 1000000>;
+	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
+	tx_delay = <0x30>;
+	rx_delay = <0x10>;
+	status = "okay";
+};
+
 &hdmi {
 	ddc-i2c-bus = <&i2c5>;
 	status = "okay";
diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts
index 8d7446fd5d..34073c9405 100644
--- a/arch/arm/dts/rk3288-rock2-square.dts
+++ b/arch/arm/dts/rk3288-rock2-square.dts
@@ -111,7 +111,7 @@
 };
 
 &gmac {
-	status = "ok";
+	status = "okay";
 };
 
 &hdmi {
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
new file mode 100644
index 0000000000..f168e4ff99
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga.dts
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "samtec VIN|ING FPGA";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		ethernet0 = &gmac1;
+		udc0 = &usb0;
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	rtc: rtc@68 {
+		compatible = "stm,m41t82";
+		reg = <0x68>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q128@0 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q128", "spi-flash";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+
+	flash1: n25q00@1 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00", "spi-flash";
+		reg = <1>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/pine64_common.dtsi b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index d968d764b8..d5a7249464 100644
--- a/arch/arm/dts/pine64_common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -40,7 +40,23 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include "a64.dtsi"
+#include "sun50i-a64.dtsi"
+
+/ {
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
 
 &mmc0 {
 	pinctrl-names = "default";
@@ -57,20 +73,8 @@
 	status = "okay";
 };
 
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_pins>;
-	status = "okay";
-};
-
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart3_pins_a>;
-	status = "okay";
-};
-
-&uart4 {
+&i2c1 {
 	pinctrl-names = "default";
-	pinctrl-0 = <&uart4_pins>;
+	pinctrl-0 = <&i2c1_pins>;
 	status = "okay";
 };
diff --git a/arch/arm/dts/pine64_plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts
index 5daff514e2..549dc15bd5 100644
--- a/arch/arm/dts/pine64_plus.dts
+++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts
@@ -42,15 +42,11 @@
 
 /dts-v1/;
 
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
+#include "sun50i-a64-pine64-common.dtsi"
 
 / {
 	model = "Pine64+";
-	compatible = "pine64,pine64_plus", "allwinner,a64";
+	compatible = "pine64,pine64-plus", "allwinner,sun50i-a64";
 
 	chosen {
 		stdout-path = "serial0:115200n8";
diff --git a/arch/arm/dts/pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts
index dcc998f24c..ebe029e8a8 100644
--- a/arch/arm/dts/pine64.dts
+++ b/arch/arm/dts/sun50i-a64-pine64.dts
@@ -42,15 +42,11 @@
 
 /dts-v1/;
 
-/memreserve/ 0x45000000 0x00200000;
-/memreserve/ 0x41010000 0x00010800;
-/memreserve/ 0x40100000 0x00006000;
-
-#include "pine64_common.dtsi"
+#include "sun50i-a64-pine64-common.dtsi"
 
 / {
 	model = "Pine64";
-	compatible = "pine64,pine64", "allwinner,a64";
+	compatible = "pine64,pine64", "allwinner,sun50i-a64";
 
 	chosen {
 		stdout-path = "serial0:115200n8";
diff --git a/arch/arm/dts/a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index f3ad00024a..1bd436f847 100644
--- a/arch/arm/dts/a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2016 ARM Ltd.
  * based on the Allwinner H3 dtsi:
- * 	Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
+ *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -46,19 +46,10 @@
 #include <dt-bindings/pinctrl/sun4i-a10.h>
 
 / {
-	compatible = "allwinner,a64";
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	aliases {
-		serial0 = &uart0;
-		serial1 = &uart1;
-		serial2 = &uart2;
-		serial3 = &uart3;
-		serial4 = &uart4;
-	};
-
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -93,18 +84,29 @@
 	};
 
 	psci {
-		compatible = "arm,psci-0.2", "arm,psci";
+		compatible = "arm,psci-0.2";
 		method = "smc";
-		cpu_suspend = <0xc4000001>;
-		cpu_off = <0x84000002>;
-		cpu_on = <0xc4000003>;
 	};
 
-        memory {
+	memory {
 		device_type = "memory";
 		reg = <0x40000000 0>;
 	};
 
+	gic: interrupt-controller@1c81000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+
+		reg = <0x01c81000 0x1000>,
+		      <0x01c82000 0x2000>,
+		      <0x01c84000 0x2000>,
+		      <0x01c86000 0x2000>;
+		interrupts = <GIC_PPI 9
+		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts = <GIC_PPI 13
@@ -136,7 +138,7 @@
 			clock-output-names = "osc32k";
 		};
 
-		pll1: clk@01c20000 {
+		pll1: pll1_clk@1c20000 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-a23-pll1-clk";
 			reg = <0x01c20000 0x4>;
@@ -144,7 +146,7 @@
 			clock-output-names = "pll1";
 		};
 
-		pll6: clk@01c20028 {
+		pll6: pll6_clk@1c20028 {
 			#clock-cells = <1>;
 			compatible = "allwinner,sun6i-a31-pll6-clk";
 			reg = <0x01c20028 0x4>;
@@ -161,23 +163,24 @@
 			clock-output-names = "pll6d2";
 		};
 
-		/* dummy clock until pll6 can be reused */
-		pll8: pll8_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <1>;
-			clock-output-names = "pll8";
+		pll7: pll7_clk@1c2002c {
+			#clock-cells = <1>;
+			compatible = "allwinner,sun6i-a31-pll6-clk";
+			reg = <0x01c2002c 0x4>;
+			clocks = <&osc24M>;
+			clock-output-names = "pll7", "pll7x2";
 		};
 
-		cpu: cpu_clk@01c20050 {
+		cpu: cpu_clk@1c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-cpu-clk";
 			reg = <0x01c20050 0x4>;
 			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 			clock-output-names = "cpu";
+			critical-clocks = <0>;
 		};
 
-		axi: axi_clk@01c20050 {
+		axi: axi_clk@1c20050 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-axi-clk";
 			reg = <0x01c20050 0x4>;
@@ -185,7 +188,7 @@
 			clock-output-names = "axi";
 		};
 
-		ahb1: ahb1_clk@01c20054 {
+		ahb1: ahb1_clk@1c20054 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun6i-a31-ahb1-clk";
 			reg = <0x01c20054 0x4>;
@@ -193,7 +196,7 @@
 			clock-output-names = "ahb1";
 		};
 
-		ahb2: ahb2_clk@01c2005c {
+		ahb2: ahb2_clk@1c2005c {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun8i-h3-ahb2-clk";
 			reg = <0x01c2005c 0x4>;
@@ -201,7 +204,7 @@
 			clock-output-names = "ahb2";
 		};
 
-		apb1: apb1_clk@01c20054 {
+		apb1: apb1_clk@1c20054 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb0-clk";
 			reg = <0x01c20054 0x4>;
@@ -209,7 +212,7 @@
 			clock-output-names = "apb1";
 		};
 
-		apb2: apb2_clk@01c20058 {
+		apb2: apb2_clk@1c20058 {
 			#clock-cells = <0>;
 			compatible = "allwinner,sun4i-a10-apb1-clk";
 			reg = <0x01c20058 0x4>;
@@ -217,92 +220,95 @@
 			clock-output-names = "apb2";
 		};
 
-		bus_gates: clk@01c20060 {
+		bus_gates: bus_gates_clk@1c20060 {
 			#clock-cells = <1>;
-			compatible = "allwinner,a64-bus-gates-clk",
-				     "allwinner,sun8i-h3-bus-gates-clk";
+			compatible = "allwinner,sun50i-a64-bus-gates-clk",
+				     "allwinner,sunxi-multi-bus-gates-clk";
 			reg = <0x01c20060 0x14>;
-			clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
-			clock-names = "ahb1", "ahb2", "apb1", "apb2";
-			clock-indices = <1>,
-					<5>, <6>, <8>,
-					<9>, <10>, <13>,
-					<14>, <17>, <18>,
-					<19>, <20>,
-					<21>, <23>,
-					<24>, <25>,
-					<28>, <29>,
-					<32>, <35>,
-					<36>, <37>,
-					<40>, <43>,
-					<44>, <52>, <53>,
-					<54>, <64>,
-					<65>, <69>, <72>,
-					<76>, <77>, <78>,
-					<96>, <97>, <98>,
-					<101>,
-					<112>, <113>,
-					<114>, <115>,
-					<116>, <135>;
-			clock-output-names = "bus_mipidsi",
-					     "bus_ce", "bus_dma", "bus_mmc0",
-					     "bus_mmc1", "bus_mmc2", "bus_nand",
-					     "bus_sdram", "bus_gmac", "bus_ts",
-					     "bus_hstimer", "bus_spi0",
-					     "bus_spi1", "bus_otg",
-					     "bus_otg_ehci0", "bus_ehci0",
-					     "bus_otg_ohci0", "bus_ohci0",
-					     "bus_ve", "bus_lcd0",
-					     "bus_lcd1", "bus_deint",
-					     "bus_csi", "bus_hdmi",
-					     "bus_de", "bus_gpu", "bus_msgbox",
-					     "bus_spinlock", "bus_codec",
-					     "bus_spdif", "bus_pio", "bus_ths",
-					     "bus_i2s0", "bus_i2s1", "bus_i2s2",
-					     "bus_i2c0", "bus_i2c1", "bus_i2c2",
-					     "bus_scr",
-					     "bus_uart0", "bus_uart1",
-					     "bus_uart2", "bus_uart3",
-					     "bus_uart4", "bus_dbg";
-		};
-
-		mmc0_clk: clk@01c20088 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
-			reg = <0x01c20088 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc0",
-					     "mmc0_output",
-					     "mmc0_sample";
+			ahb1_parent {
+				clocks = <&ahb1>;
+				clock-indices = <1>, <5>,
+						<6>, <8>,
+						<9>, <10>,
+						<13>, <14>,
+						<18>, <19>,
+						<20>, <21>,
+						<23>, <24>,
+						<25>, <28>,
+						<32>, <35>,
+						<36>, <37>,
+						<40>, <43>,
+						<44>, <52>,
+						<53>, <54>,
+						<135>;
+				clock-output-names = "bus_mipidsi", "bus_ce",
+						"bus_dma", "bus_mmc0",
+						"bus_mmc1", "bus_mmc2",
+						"bus_nand", "bus_sdram",
+						"bus_ts", "bus_hstimer",
+						"bus_spi0", "bus_spi1",
+						"bus_otg", "bus_otg_ehci0",
+						"bus_ehci0", "bus_otg_ohci0",
+						"bus_ve", "bus_lcd0",
+						"bus_lcd1", "bus_deint",
+						"bus_csi", "bus_hdmi",
+						"bus_de", "bus_gpu",
+						"bus_msgbox", "bus_spinlock",
+						"bus_dbg";
+			};
+			ahb2_parent {
+				clocks = <&ahb2>;
+				clock-indices = <17>, <29>;
+				clock-output-names = "bus_gmac", "bus_ohci0";
+			};
+			apb1_parent {
+				clocks = <&apb1>;
+				clock-indices = <64>, <65>,
+						<69>, <72>,
+						<76>, <77>,
+						<78>;
+				clock-output-names = "bus_codec", "bus_spdif",
+						"bus_pio", "bus_ths",
+						"bus_i2s0", "bus_i2s1",
+						"bus_i2s2";
+			};
+			abp2_parent {
+				clocks = <&apb2>;
+				clock-indices = <96>, <97>,
+						<98>, <101>,
+						<112>, <113>,
+						<114>, <115>,
+						<116>;
+				clock-output-names = "bus_i2c0", "bus_i2c1",
+						"bus_i2c2", "bus_scr",
+						"bus_uart0", "bus_uart1",
+						"bus_uart2", "bus_uart3",
+						"bus_uart4";
+			};
 		};
 
-		mmc1_clk: clk@01c2008c {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
+		mmc0_clk: mmc0_clk@1c20088 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
+			reg = <0x01c20088 0x4>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc0";
+                };
+
+		mmc1_clk: mmc1_clk@1c2008c {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c2008c 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc1",
-					     "mmc1_output",
-					     "mmc1_sample";
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc1";
 		};
 
-		mmc2_clk: clk@01c20090 {
-			#clock-cells = <1>;
-			compatible = "allwinner,sun4i-a10-mmc-clk";
+		mmc2_clk: mmc2_clk@1c20090 {
+			#clock-cells = <0>;
+			compatible = "allwinner,sun4i-a10-mod0-clk";
 			reg = <0x01c20090 0x4>;
-			clocks = <&osc24M>, <&pll6 0>, <&pll8>;
-			clock-output-names = "mmc2",
-					     "mmc2_output",
-					     "mmc2_sample";
-		};
-	};
-
-	regulators {
-		reg_vcc3v3: vcc3v3 {
-			compatible = "regulator-fixed";
-			regulator-name = "vcc3v3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
+			clocks = <&osc24M>, <&pll6 1>, <&pll7 1>;
+			clock-output-names = "mmc2";
 		};
 	};
 
@@ -312,17 +318,14 @@
 		#size-cells = <1>;
 		ranges;
 
-		mmc0: mmc@01c0f000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
 			reg = <0x01c0f000 0x1000>;
-			clocks = <&bus_gates 8>,
-				 <&mmc0_clk 0>,
-				 <&mmc0_clk 1>,
-				 <&mmc0_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&bus_gates 8>, <&mmc0_clk>,
+				 <&mmc0_clk>, <&mmc0_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
 			resets = <&ahb_rst 8>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
@@ -331,17 +334,14 @@
 			#size-cells = <0>;
 		};
 
-		mmc1: mmc@01c10000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
 			reg = <0x01c10000 0x1000>;
-			clocks = <&bus_gates 9>,
-				 <&mmc1_clk 0>,
-				 <&mmc1_clk 1>,
-				 <&mmc1_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&bus_gates 9>, <&mmc1_clk>,
+				 <&mmc1_clk>, <&mmc1_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
 			resets = <&ahb_rst 9>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
@@ -350,17 +350,14 @@
 			#size-cells = <0>;
 		};
 
-		mmc2: mmc@01c11000 {
-			compatible = "allwinner,sun5i-a13-mmc";
+		mmc2: mmc@1c11000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
 			reg = <0x01c11000 0x1000>;
-			clocks = <&bus_gates 10>,
-				 <&mmc2_clk 0>,
-				 <&mmc2_clk 1>,
-				 <&mmc2_clk 2>;
-			clock-names = "ahb",
-				      "mmc",
-				      "output",
-				      "sample";
+			clocks = <&bus_gates 10>, <&mmc2_clk>,
+				 <&mmc2_clk>, <&mmc2_clk>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
 			resets = <&ahb_rst 10>;
 			reset-names = "ahb";
 			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
@@ -369,8 +366,8 @@
 			#size-cells = <0>;
 		};
 
-		pio: pinctrl@01c20800 {
-			compatible = "allwinner,a64-pinctrl";
+		pio: pinctrl@1c20800 {
+			compatible = "allwinner,sun50i-a64-pinctrl";
 			reg = <0x01c20800 0x400>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
@@ -395,14 +392,28 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			uart1_pins: uart1@0 {
+			uart1_2pins: uart1_2@0 {
+				allwinner,pins = "PG6", "PG7";
+				allwinner,function = "uart1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart1_4pins: uart1_4@0 {
 				allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 				allwinner,function = "uart1";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			uart2_pins: uart2@0 {
+			uart2_2pins: uart2_2@0 {
+				allwinner,pins = "PB0", "PB1";
+				allwinner,function = "uart2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart2_4pins: uart2_4@0 {
 				allwinner,pins = "PB0", "PB1", "PB2", "PB3";
 				allwinner,function = "uart2";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -416,14 +427,28 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			uart3_pins_b: uart3@1 {
+			uart3_2pins_b: uart3_2@1 {
+				allwinner,pins = "PH4", "PH5";
+				allwinner,function = "uart3";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart3_4pins_b: uart3_4@1 {
 				allwinner,pins = "PH4", "PH5", "PH6", "PH7";
 				allwinner,function = "uart3";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
-			uart4_pins: uart4@0 {
+			uart4_2pins: uart4_2@0 {
+				allwinner,pins = "PD2", "PD3";
+				allwinner,function = "uart4";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			uart4_4pins: uart4_4@0 {
 				allwinner,pins = "PD2", "PD3", "PD4", "PD5";
 				allwinner,function = "uart4";
 				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -460,27 +485,48 @@
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
+
+			i2c0_pins: i2c0_pins {
+				allwinner,pins = "PH0", "PH1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c1_pins: i2c1_pins {
+				allwinner,pins = "PH2", "PH3";
+				allwinner,function = "i2c1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c2_pins: i2c2_pins {
+				allwinner,pins = "PE14", "PE15";
+				allwinner,function = "i2c2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
 		};
 
-		ahb_rst: reset@01c202c0 {
+		ahb_rst: reset@1c202c0 {
 			#reset-cells = <1>;
-			compatible = "allwinner,sun6i-a31-ahb1-reset";
+			compatible = "allwinner,sun6i-a31-clock-reset";
 			reg = <0x01c202c0 0xc>;
 		};
 
-		apb1_rst: reset@01c202d0 {
+		apb1_rst: reset@1c202d0 {
 			#reset-cells = <1>;
 			compatible = "allwinner,sun6i-a31-clock-reset";
 			reg = <0x01c202d0 0x4>;
 		};
 
-		apb2_rst: reset@01c202d8 {
+		apb2_rst: reset@1c202d8 {
 			#reset-cells = <1>;
 			compatible = "allwinner,sun6i-a31-clock-reset";
 			reg = <0x01c202d8 0x4>;
 		};
 
-		uart0: serial@01c28000 {
+		uart0: serial@1c28000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28000 0x400>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,11 +534,10 @@
 			reg-io-width = <4>;
 			clocks = <&bus_gates 112>;
 			resets = <&apb2_rst 16>;
-			reset-names = "apb2";
 			status = "disabled";
 		};
 
-		uart1: serial@01c28400 {
+		uart1: serial@1c28400 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28400 0x400>;
 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,11 +545,10 @@
 			reg-io-width = <4>;
 			clocks = <&bus_gates 113>;
 			resets = <&apb2_rst 17>;
-			reset-names = "apb2";
 			status = "disabled";
 		};
 
-		uart2: serial@01c28800 {
+		uart2: serial@1c28800 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28800 0x400>;
 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -512,11 +556,10 @@
 			reg-io-width = <4>;
 			clocks = <&bus_gates 114>;
 			resets = <&apb2_rst 18>;
-			reset-names = "apb2";
 			status = "disabled";
 		};
 
-		uart3: serial@01c28c00 {
+		uart3: serial@1c28c00 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c28c00 0x400>;
 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
@@ -524,11 +567,10 @@
 			reg-io-width = <4>;
 			clocks = <&bus_gates 115>;
 			resets = <&apb2_rst 19>;
-			reset-names = "apb2";
 			status = "disabled";
 		};
 
-		uart4: serial@01c29000 {
+		uart4: serial@1c29000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x01c29000 0x400>;
 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
@@ -536,29 +578,47 @@
 			reg-io-width = <4>;
 			clocks = <&bus_gates 116>;
 			resets = <&apb2_rst 20>;
-			reset-names = "apb2";
 			status = "disabled";
 		};
 
-		rtc: rtc@01f00000 {
+		rtc: rtc@1f00000 {
 			compatible = "allwinner,sun6i-a31-rtc";
 			reg = <0x01f00000 0x54>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
-	};
 
-	gic: interrupt-controller@{
-		compatible = "arm,gic-400";
-		interrupt-controller;
-		#interrupt-cells = <3>;
-		#address-cells = <0>;
+		i2c0: i2c@1c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 96>;
+			resets = <&apb2_rst 0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 
-		reg = <0x01C81000 0x1000>,
-		      <0x01C82000 0x2000>,
-		      <0x01C84000 0x2000>,
-		      <0x01C86000 0x2000>;
-		interrupts = <GIC_PPI 9
-		      (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		i2c1: i2c@1c2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 97>;
+			resets = <&apb2_rst 1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c2: i2c@1c2b400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b400 0x400>;
+			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&bus_gates 98>;
+			resets = <&apb2_rst 2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 };
diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts
new file mode 100644
index 0000000000..5f29ee4501
--- /dev/null
+++ b/arch/arm/dts/tegra186-p2771-0000.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "tegra186.dtsi"
+
+/ {
+	model = "NVIDIA P2771-0000";
+	compatible = "nvidia,p2771-0000", "nvidia,tegra186";
+
+	chosen {
+		stdout-path = &uarta;
+	};
+
+	aliases {
+		sdhci0 = "/sdhci@3460000";
+	};
+
+	memory {
+		reg = <0x0 0x80000000 0x0 0x60000000>;
+	};
+
+	sdhci@3460000 {
+		status = "okay";
+		bus-width = <8>;
+	};
+};
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
new file mode 100644
index 0000000000..18b6a26643
--- /dev/null
+++ b/arch/arm/dts/tegra186.dtsi
@@ -0,0 +1,56 @@
+#include "skeleton.dtsi"
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "nvidia,tegra186";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	gpio@2200000 {
+		compatible = "nvidia,tegra186-gpio";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0x2200000 0x0 0x10000>,
+			<0x0 0x2210000 0x0 0x10000>;
+		interrupts =
+			<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	uarta: serial@3100000 {
+		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
+		reg = <0x0 0x03100000 0x0 0x10000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	sdhci@3460000 {
+		compatible = "nvidia,tegra186-sdhci";
+		reg = <0x0 0x03460000 0x0 0x200>;
+		interrupts = <GIC_SPI 31 0x04>;
+		status = "disabled";
+	};
+
+	gpio@c2f0000 {
+		compatible = "nvidia,tegra186-gpio-aon";
+		reg-names = "security", "gpio";
+		reg =
+			<0x0 0xc2f0000 0x0 0x1000>,
+			<0x0 0xc2f1000 0x0 0x1000>;
+		interrupts =
+			<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
index 88e7f53ed5..b148e9fbd9 100644
--- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts
@@ -49,6 +49,18 @@
 	status = "okay";
 };
 
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
 /* for U-Boot only */
 / {
 	soc {
diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ph1-ld11.dtsi
index 7d498cebe9..e485f90a97 100644
--- a/arch/arm/dts/uniphier-ph1-ld11.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld11.dtsi
@@ -190,6 +190,42 @@
 			reg = <0x59801000 0x400>;
 		};
 
+		usb0: usb@5a800100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a800100 0x100>;
+			interrupts = <0 243 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&mio 3>, <&mio 6>;
+		};
+
+		usb1: usb@5a810100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a810100 0x100>;
+			interrupts = <0 244 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&mio 4>, <&mio 6>;
+		};
+
+		usb2: usb@5a820100 {
+			compatible = "socionext,uniphier-ehci", "generic-ehci";
+			status = "disabled";
+			reg = <0x5a820100 0x100>;
+			interrupts = <0 245 4>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb2>;
+			clocks = <&mio 5>, <&mio 6>;
+		};
+
+		mio: mioctrl@5b3e0000 {
+			compatible = "socionext,ph1-ld11-mioctrl";
+			reg = <0x5b3e0000 0x800>;
+			#clock-cells = <1>;
+		};
+
 		pinctrl: pinctrl@5f801000 {
 			compatible = "socionext,ph1-ld11-pinctrl", "syscon";
 			reg = <0x5f801000 0xe00>;
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index a327557c19..b618a3f484 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -251,7 +251,7 @@
 		slcr: slcr@f8000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
-			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
 			reg = <0xF8000000 0x1000>;
 			ranges;
 			clkc: clkc@100 {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 0000000000..03f1ad7934
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,212 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+	model = "ZynqMP zc1751-xm018-dc4";
+	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+	aliases {
+		can0 = &can0;
+		can1 = &can1;
+		ethernet0 = &gem0;
+		ethernet1 = &gem1;
+		ethernet2 = &gem2;
+		ethernet3 = &gem3;
+		gpio0 = &gpio;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		rtc0 = &rtc;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		bootargs = "earlycon";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+	xlnx,overfetch; /* for testing purpose */
+	xlnx,ratectrl = <0>; /* for testing purpose */
+	xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+	status = "okay";
+	xlnx,ratectrl = <100>; /* for testing purpose */
+	xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+	status = "okay";
+};
+
+&fpd_dma_chan4 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+	status = "okay";
+};
+
+&fpd_dma_chan6 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+	status = "okay";
+};
+
+&fpd_dma_chan8 {
+	status = "okay";
+	xlnx,include-sg; /* for testing purpose */
+};
+
+&lpd_dma_chan1 {
+	status = "okay";
+};
+
+&lpd_dma_chan2 {
+	status = "okay";
+};
+
+&lpd_dma_chan3 {
+	status = "okay";
+};
+
+&lpd_dma_chan4 {
+	status = "okay";
+};
+
+&lpd_dma_chan5 {
+	status = "okay";
+};
+
+&lpd_dma_chan6 {
+	status = "okay";
+};
+
+&lpd_dma_chan7 {
+	status = "okay";
+};
+
+&lpd_dma_chan8 {
+	status = "okay";
+};
+
+&xlnx_dp {
+	status = "okay";
+};
+
+&xlnx_dpdma {
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 90];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy0>;
+	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+		reg = <0>;
+	};
+	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+		reg = <7>;
+	};
+	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+		reg = <3>;
+	};
+	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+		reg = <8>;
+	};
+};
+
+&gem1 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 91];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy7>;
+};
+
+&gem2 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 92];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy3>;
+};
+
+&gem3 {
+	status = "okay";
+	local-mac-address = [00 0a 35 00 02 93];
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy8>;
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index fb95b4828b..619450e1ba 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -253,9 +253,9 @@
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			reg = <0x0 0xf9010000 0x10000>,
-			      <0x0 0xf902f000 0x2000>,
+			      <0x0 0xf9020000 0x20000>,
 			      <0x0 0xf9040000 0x20000>,
-			      <0x0 0xf906f000 0x2000>;
+			      <0x0 0xf9060000 0x20000>;
 			interrupt-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <1 9 0xf04>;
@@ -264,6 +264,7 @@
 
 	amba: amba {
 		compatible = "simple-bus";
+		u-boot,dm-pre-reloc;
 		#address-cells = <2>;
 		#size-cells = <1>;
 		ranges = <0 0 0 0 0xffffffff>;
@@ -674,6 +675,7 @@
 		};
 
 		sdhci0: sdhci@ff160000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -685,6 +687,7 @@
 		};
 
 		sdhci1: sdhci@ff170000 {
+			u-boot,dm-pre-reloc;
 			compatible = "arasan,sdhci-8.9a";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -776,6 +779,7 @@
 		};
 
 		uart0: serial@ff000000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
@@ -786,6 +790,7 @@
 		};
 
 		uart1: serial@ff010000 {
+			u-boot,dm-pre-reloc;
 			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 			status = "disabled";
 			interrupt-parent = <&gic>;
diff --git a/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
new file mode 100644
index 0000000000..a5af0120d8
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clk_synthesizer.h
@@ -0,0 +1,43 @@
+/*
+ * clk-synthesizer.h
+ *
+ * Clock synthesizer header
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CLK_SYNTHESIZER_H
+#define __CLK_SYNTHESIZER_H
+
+#include <common.h>
+
+#define CLK_SYNTHESIZER_ID_REG		0x0
+#define CLK_SYNTHESIZER_XCSEL		0x05
+#define CLK_SYNTHESIZER_MUX_REG		0x14
+#define CLK_SYNTHESIZER_PDIV2_REG	0x16
+#define CLK_SYNTHESIZER_PDIV3_REG	0x17
+
+#define CLK_SYNTHESIZER_BYTE_MODE	0x80
+
+/**
+ * struct clk_synth: This structure holds data neeed for configuring
+ *		     for clock synthesizer.
+ * @id: The id of synthesizer
+ * @capacitor: value of the capacitor attached
+ * @mux: mux settings.
+ * @pdiv2: Div to be applied to second output
+ * @pdiv3: Div to be applied to third output
+ */
+struct clk_synth {
+	u32 id;
+	u32 capacitor;
+	u32 mux;
+	u32 pdiv2;
+	u32 pdiv3;
+};
+
+int setup_clock_synthesizer(struct clk_synth *data);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index a6d2419fb8..acf3fd55a8 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -44,6 +44,9 @@
 /* CM_CLKMODE_DPLL */
 #define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
 #define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
+#define CM_CLKMODE_DPLL_SSC_ACK_MASK		(1 << 13)
+#define CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK	(1 << 14)
+#define CM_CLKMODE_DPLL_SSC_TYPE_MASK		(1 << 15)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
@@ -114,4 +117,5 @@ void enable_basic_clocks(void);
 void do_enable_clocks(u32 *const *, u32 *const *, u8);
 void do_disable_clocks(u32 *const *, u32 *const *, u8);
 
+void set_mpu_spreadspectrum(int permille);
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 112ac5eacd..62bca8cc17 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -99,7 +99,8 @@ struct cm_wkuppll {
 	unsigned int timer0clkctrl;	/* offset 0x10 */
 	unsigned int resv2[3];
 	unsigned int idlestdpllmpu;	/* offset 0x20 */
-	unsigned int resv3[2];
+	unsigned int sscdeltamstepdllmpu; /* off  0x24 */
+	unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
 	unsigned int clkseldpllmpu;	/* offset 0x2c */
 	unsigned int resv4[1];
 	unsigned int idlestdpllddr;	/* offset 0x34 */
@@ -497,6 +498,8 @@ struct ctrl_stat {
 #define OMAP_GPIO_SYSSTATUS		0x0114
 #define OMAP_GPIO_IRQSTATUS1		0x002c
 #define OMAP_GPIO_IRQSTATUS2		0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0	0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1	0x0038
 #define OMAP_GPIO_CTRL			0x0130
 #define OMAP_GPIO_OE			0x0134
 #define OMAP_GPIO_DATAIN		0x0138
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 97bbfe2e65..43e122e261 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -54,6 +54,21 @@
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz	0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz		0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz		0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz		0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz	0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz	0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz		0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz		0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz	0x0
+#define MT41J128MJT125_RD_DQS_400MHz		0x3A
+#define MT41J128MJT125_WR_DQS_400MHz		0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz	0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz	0x96
+
 /* Micron MT41K128M16JT-187E */
 #define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
 #define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
diff --git a/arch/arm/include/asm/arch-bcm281xx/boot0.h b/arch/arm/include/asm/arch-bcm281xx/boot0.h
new file mode 100644
index 0000000000..7e72882725
--- /dev/null
+++ b/arch/arm/include/asm/arch-bcm281xx/boot0.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2016 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.word	0xbabeface;	\
+	.word	_end - _start
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2bef..44fe0c0095 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -14,8 +14,11 @@
 #else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
 #endif
+
+#ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#endif
 
 /*
  * Reserve secure memory
@@ -134,8 +137,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 #define CONFIG_SYS_FSL_ERRATUM_A009635
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009801
 #define CONFIG_SYS_FSL_ERRATUM_A009803
 #define CONFIG_SYS_FSL_ERRATUM_A009942
+#define CONFIG_SYS_FSL_ERRATUM_A010165
 
 /* ARM A57 CORE ERRATA */
 #define CONFIG_ARM_ERRATA_826974
@@ -143,6 +148,7 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS				4
 #define CONFIG_SYS_CACHELINE_SIZE		64
@@ -191,10 +197,38 @@
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
 
+#define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS                         1
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
+
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES		4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9faabd..1cebe2fbb0 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
index f71c2c1773..487cba8080 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -55,7 +55,7 @@ enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,
@@ -134,6 +134,7 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	TX_CLK,
 	SERDES_PRCTL_COUNT
 };
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0bad0c70b8..e98e055d9f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -37,8 +37,6 @@
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR			(CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR			(CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
 
@@ -62,7 +60,11 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE				0xC0000
+#else
 #define PCIE_LUT_BASE				0x10000
+#endif
 #define PCIE_LUT_LCTRL0				0x7F8
 #define PCIE_LUT_DBG				0x7FC
 
@@ -157,6 +159,13 @@ struct sys_info {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
 /* Device Configuration and Pin Control */
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 1d3b33671f..65b3357009 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -77,8 +77,12 @@
 #define CONFIG_SYS_SFP_ADDR		(CONFIG_SYS_IMMR + 0x00e80200)
 
 /* SEC */
-#define CONFIG_SYS_FSL_SEC_ADDR		(CONFIG_SYS_IMMR + 0x07000000)
-#define CONFIG_SYS_FSL_JR0_ADDR		(CONFIG_SYS_IMMR + 0x07010000)
+#define CONFIG_SYS_FSL_SEC_OFFSET		0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Security Monitor */
 #define CONFIG_SYS_SEC_MON_ADDR		(CONFIG_SYS_IMMR + 0x00e90000)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index a3ccdb03c7..db76066c80 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -69,7 +69,12 @@ enum csu_cslx_ind {
 	CSU_CSLX_IIC4 = 77,
 	CSU_CSLX_WDT4,
 	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
 	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
 	CSU_CSLX_FTM2 = 86,
 	CSU_CSLX_FTM1,
 	CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_IIC4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
 	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
 	 {CSU_CSLX_FTM2, CSU_ALL_RW},
 	 {CSU_CSLX_FTM1, CSU_ALL_RW},
 	 {CSU_CSLX_FTM4, CSU_ALL_RW},
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 831d81764e..02ecc6257e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -41,6 +41,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
+#define SVR_LS1012		0x870400
 #define SVR_LS1043		0x879200
 #define SVR_LS1023		0x879208
 #define SVR_LS2045		0x870120
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index d77c04a86a..04abec467c 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -40,6 +40,7 @@
 	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x00700000
+#define CONFIG_SYS_FSL_JR0_OFFSET		0x00710000
 #define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
@@ -131,6 +132,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
new file mode 100644
index 0000000000..f90f632daf
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __GXBB_H__
+#define __GXBB_H__
+
+#define GXBB_PERIPHS_BASE	0xc8834400
+#define GXBB_HIU_BASE		0xc883c000
+#define GXBB_ETH_BASE		0xc9410000
+
+/* Peripherals registers */
+#define GXBB_PERIPHS_ADDR(off)	(GXBB_PERIPHS_BASE + ((off) << 2))
+
+/* GPIO registers 0 to 6 */
+#define _GXBB_GPIO_OFF(n)	((n) == 6 ? 0x08 : 0x0c + 3 * (n))
+#define GXBB_GPIO_EN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
+#define GXBB_GPIO_IN(n)		GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
+#define GXBB_GPIO_OUT(n)	GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
+
+/* Pinmux registers 0 to 12 */
+#define GXBB_PINMUX(n)		GXBB_PERIPHS_ADDR(0x2c + (n))
+
+#define GXBB_ETH_REG_0		GXBB_PERIPHS_ADDR(0x50)
+#define GXBB_ETH_REG_1		GXBB_PERIPHS_ADDR(0x51)
+
+#define GXBB_ETH_REG_0_PHY_INTF		BIT(0)
+#define GXBB_ETH_REG_0_TX_PHASE(x)	(((x) & 3) << 5)
+#define GXBB_ETH_REG_0_TX_RATIO(x)	(((x) & 7) << 7)
+#define GXBB_ETH_REG_0_PHY_CLK_EN	BIT(10)
+#define GXBB_ETH_REG_0_CLK_EN		BIT(12)
+
+/* HIU registers */
+#define GXBB_HIU_ADDR(off)	(GXBB_HIU_BASE + ((off) << 2))
+
+#define GXBB_MEM_PD_REG_0	GXBB_HIU_ADDR(0x40)
+
+/* Ethernet memory power domain */
+#define GXBB_MEM_PD_REG_0_ETH_MASK	(BIT(2) | BIT(3))
+
+/* Clock gates */
+#define GXBB_GCLK_MPEG_0	GXBB_HIU_ADDR(0x50)
+#define GXBB_GCLK_MPEG_1	GXBB_HIU_ADDR(0x51)
+#define GXBB_GCLK_MPEG_2	GXBB_HIU_ADDR(0x52)
+#define GXBB_GCLK_MPEG_OTHER	GXBB_HIU_ADDR(0x53)
+#define GXBB_GCLK_MPEG_AO	GXBB_HIU_ADDR(0x54)
+
+#define GXBB_GCLK_MPEG_1_ETH	BIT(3)
+
+#endif /* __GXBB_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
new file mode 100644
index 0000000000..225438d6dc
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MESON_SM_H__
+#define __MESON_SM_H__
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
+
+#endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 3ab04bf998..ac37e4f8e6 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -227,8 +227,13 @@
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR		    (ATZ2_BASE_ADDR + 0x40000)
 
-#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
-#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+#define CONFIG_SYS_FSL_SEC_OFFSET   0
+#define CONFIG_SYS_FSL_SEC_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET   0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + \
+				     CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 
 #define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index a3106e7e6b..74917f0e69 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -218,10 +218,13 @@
 
 #define FEC_QUIRK_ENET_MAC
 #define SNVS_LPGPR	0x68
-
-#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
-#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
-
+#define CONFIG_SYS_FSL_SEC_OFFSET       0
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
+					 CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET       0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR + \
+					 CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC   1
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/imx-common/regs-lcdif.h>
 #include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index 53cc2b098a..e8aa786d2b 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -59,13 +59,8 @@ struct ctrl_id {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
-/* device type */
-#define DEVICE_MASK		(0x7 << 8)
+/* boot pin mask */
 #define SYSBOOT_MASK		0x1F
-#define TST_DEVICE		0x0
-#define EMU_DEVICE		0x1
-#define HS_DEVICE		0x2
-#define GP_DEVICE		0x3
 
 /* device speed */
 #define SKUID_CLK_MASK		0xf
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 38d50d614f..551c9277f2 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -239,19 +239,22 @@
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA752		1100
-#define VDD_EVE_DRA752		1060
-#define VDD_GPU_DRA752		1060
-#define VDD_CORE_DRA752		1060
-#define VDD_IVA_DRA752		1060
-
-/* DRA72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA72x		1100
-#define VDD_EVE_DRA72x		1060
-#define VDD_GPU_DRA72x		1060
-#define VDD_CORE_DRA72x		1060
-#define VDD_IVA_DRA72x		1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM	1150
+#define VDD_CORE_DRA7_NOM	1150
+#define VDD_EVE_DRA7_NOM	1060
+#define VDD_GPU_DRA7_NOM	1060
+#define VDD_IVA_DRA7_NOM	1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD		1150
+#define VDD_GPU_DRA7_OD		1150
+#define VDD_IVA_DRA7_OD		1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH	1250
+#define VDD_GPU_DRA7_HIGH	1250
+#define VDD_IVA_DRA7_HIGH	1250
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE	0x4A002000
@@ -283,6 +286,20 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH	(DRA752_EFUSE_BASE + 0x1B28)
 
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7			VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7			VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7			VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7			VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7			VDD_IVA_DRA7_NOM
+
+#define STD_FUSE_OPP_VMIN_MPU		STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE		STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE	STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define STD_FUSE_OPP_VMIN_GPU		STD_FUSE_OPP_VMIN_GPU_NOM
+#define STD_FUSE_OPP_VMIN_IVA		STD_FUSE_OPP_VMIN_IVA_NOM
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9aaf..683d905333 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@ struct watchdog {
 #define CPSW_BASE			0x48484000
 #define CPSW_MDIO_BASE			0x48485000
 
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 804266a1b6..ab0e7fae9c 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -51,6 +51,7 @@ void sdelay(unsigned long);
 void setup_early_clocks(void);
 void prcm_init(void);
 void do_board_detect(void);
+void vcores_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index d2690c7788..8a8ca9c9aa 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@ enum {
 	SDIO0_DIV_MASK		= 0x3f,
 };
 
+/* CRU_CLKSEL21_CON */
+enum {
+	MAC_DIV_CON_SHIFT = 0xf,
+	MAC_DIV_CON_MASK = 0x1f,
+
+	RMII_EXTCLK_SHIFT = 4,
+	RMII_EXTCLK_MASK = 1,
+	RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+	RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+	EMAC_PLL_SHIFT = 0,
+	EMAC_PLL_MASK = 0x3,
+	EMAC_PLL_SELECT_NEW = 0x0,
+	EMAC_PLL_SELECT_CODEC = 0x1,
+	EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
 /* CRU_CLKSEL25_CON */
 enum {
 	SPI1_PLL_SHIFT		= 0xf,
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
index 0117a179c9..aaffd19dea 100644
--- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -718,6 +718,40 @@ enum {
 	MSCH0_MAINPARTIALPOP_MASK = 1,
 };
 
+/* GRF_SOC_CON1 */
+enum {
+	RMII_MODE_SHIFT = 0xe,
+	RMII_MODE_MASK = 1,
+	RMII_MODE = 1,
+
+	GMAC_CLK_SEL_SHIFT	= 0xc,
+	GMAC_CLK_SEL_MASK	= 3,
+	GMAC_CLK_SEL_125M	= 0,
+	GMAC_CLK_SEL_25M	= 0x3,
+	GMAC_CLK_SEL_2_5M	= 0x2,
+
+	RMII_CLK_SEL_SHIFT	= 0xb,
+	RMII_CLK_SEL_MASK	= 1,
+	RMII_CLK_SEL_2_5M	= 0,
+	RMII_CLK_SEL_25M,
+
+	GMAC_SPEED_SHIFT	= 0xa,
+	GMAC_SPEED_MASK		= 1,
+	GMAC_SPEED_10M		= 0,
+	GMAC_SPEED_100M,
+
+	GMAC_FLOWCTRL_SHIFT	= 0x9,
+	GMAC_FLOWCTRL_MASK	= 1,
+
+	GMAC_PHY_INTF_SEL_SHIFT	= 0x6,
+	GMAC_PHY_INTF_SEL_MASK	= 0x7,
+	GMAC_PHY_INTF_SEL_RGMII	= 0x1,
+	GMAC_PHY_INTF_SEL_RMII	= 0x4,
+
+	HOST_REMAP_SHIFT	= 0x5,
+	HOST_REMAP_MASK		= 1
+};
+
 /* GRF_SOC_CON2 */
 enum {
 	UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
@@ -765,4 +799,23 @@ enum {
 	PWM_PWM			= 0,
 };
 
+/* GRF_SOC_CON3 */
+enum {
+	RXCLK_DLY_ENA_GMAC_SHIFT	= 0xf,
+	RXCLK_DLY_ENA_GMAC_MASK		= 1,
+	RXCLK_DLY_ENA_GMAC_DISABLE	= 0,
+	RXCLK_DLY_ENA_GMAC_ENABLE,
+
+	TXCLK_DLY_ENA_GMAC_SHIFT	= 0xe,
+	TXCLK_DLY_ENA_GMAC_MASK		= 1,
+	TXCLK_DLY_ENA_GMAC_DISABLE	= 0,
+	TXCLK_DLY_ENA_GMAC_ENABLE,
+
+	CLK_RX_DL_CFG_GMAC_SHIFT	= 0x7,
+	CLK_RX_DL_CFG_GMAC_MASK		= 0x7f,
+
+	CLK_TX_DL_CFG_GMAC_SHIFT	= 0x0,
+	CLK_TX_DL_CFG_GMAC_MASK		= 0x7f,
+};
+
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h
new file mode 100644
index 0000000000..ea5675eb9e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -0,0 +1,14 @@
+/*
+ * Configuration settings for the Allwinner A64 (sun50i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+/* reserve space for BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.space	1532
+
+#endif /* __BOOT0_H */
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index ca9a4f99ad..a0f33b05b5 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -18,6 +18,10 @@
 #define SPL_ADDR		0x0
 #endif
 
+/* The low 8-bits of the 'boot_media' field in the SPL header */
+#define SUNXI_BOOTED_FROM_MMC0	0
+#define SUNXI_BOOTED_FROM_SPI	3
+
 /* boot head definition from sun4i boot code */
 struct boot_file_head {
 	uint32_t b_instruction;	/* one intruction jumping to real code */
@@ -45,7 +49,9 @@ struct boot_file_head {
 		uint8_t spl_signature[4];
 	};
 	uint32_t fel_script_address;
-	uint32_t reserved;		/* padding, align to 32 bytes */
+	uint32_t reserved1[3];
+	uint32_t boot_media;		/* written here by the boot ROM */
+	uint32_t reserved2[5];		/* padding, align to 64 bytes */
 };
 
 #define is_boot0_magic(addr)	(memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index daf5698e66..db60864a25 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -6,6 +6,8 @@
 #ifndef _TEGRA_GPIO_H_
 #define _TEGRA_GPIO_H_
 
+#include <dt-bindings/gpio/tegra-gpio.h>
+
 #define TEGRA_GPIOS_PER_PORT	8
 #define TEGRA_PORTS_PER_BANK	4
 #define MAX_NUM_GPIOS           (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index a20bdaa618..75e56c4ea7 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -134,7 +134,9 @@ struct mmc_host {
 	int id;			/* device id/number, 0-3 */
 	int enabled;		/* 1 to enable, 0 to disable */
 	int width;		/* Bus Width, 1, 4 or 8 */
+#ifndef CONFIG_TEGRA186
 	enum periph_id mmc_id;	/* Peripheral ID: PERIPH_ID_... */
+#endif
 	struct gpio_desc cd_gpio;	/* Change Detect GPIO */
 	struct gpio_desc pwr_gpio;	/* Power GPIO */
 	struct gpio_desc wp_gpio;	/* Write Protect GPIO */
diff --git a/arch/arm/include/asm/arch-tegra124/gpio.h b/arch/arm/include/asm/arch-tegra124/gpio.h
index 1a6dcb8715..ba748a5252 100644
--- a/arch/arm/include/asm/arch-tegra124/gpio.h
+++ b/arch/arm/include/asm/arch-tegra124/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA124_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra186/gpio.h b/arch/arm/include/asm/arch-tegra186/gpio.h
new file mode 100644
index 0000000000..aaecfc7ea6
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_H_
+#define _TEGRA186_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra186/tegra.h b/arch/arm/include/asm/arch-tegra186/tegra.h
new file mode 100644
index 0000000000..8031f23873
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra186/tegra.h
@@ -0,0 +1,16 @@
+/*
+ * (C) Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_TEGRA_H_
+#define _TEGRA186_TEGRA_H_
+
+#define GICD_BASE		0x03881000	/* Generic Int Cntrlr Distrib */
+#define GICC_BASE		0x03882000	/* Generic Int Cntrlr CPU I/F */
+#define NV_PA_SDRAM_BASE	0x80000000
+
+#include <asm/arch-tegra/tegra.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra20/gpio.h b/arch/arm/include/asm/arch-tegra20/gpio.h
index b40b1ff9c5..af301e7150 100644
--- a/arch/arm/include/asm/arch-tegra20/gpio.h
+++ b/arch/arm/include/asm/arch-tegra20/gpio.h
@@ -33,231 +33,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,	/* pin 223 */
-};
-
 #endif	/* TEGRA20_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
index 71af423956..389d5b63e2 100644
--- a/arch/arm/include/asm/arch-tegra210/gpio.h
+++ b/arch/arm/include/asm/arch-tegra210/gpio.h
@@ -41,263 +41,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,
-	GPIO_PFF0,	/* pin 248 */
-	GPIO_PFF1,
-	GPIO_PFF2,
-	GPIO_PFF3,
-	GPIO_PFF4,
-	GPIO_PFF5,
-	GPIO_PFF6,
-	GPIO_PFF7,	/* pin 255 */
-};
-
 #endif	/* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/gpio.h b/arch/arm/include/asm/arch-tegra30/gpio.h
index d2c6c78e08..e384327d2f 100644
--- a/arch/arm/include/asm/arch-tegra30/gpio.h
+++ b/arch/arm/include/asm/arch-tegra30/gpio.h
@@ -40,255 +40,4 @@ struct gpio_ctlr {
 	struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
 };
 
-enum gpio_pin {
-	GPIO_PA0 = 0,	/* pin 0 */
-	GPIO_PA1,
-	GPIO_PA2,
-	GPIO_PA3,
-	GPIO_PA4,
-	GPIO_PA5,
-	GPIO_PA6,
-	GPIO_PA7,
-	GPIO_PB0,	/* pin 8 */
-	GPIO_PB1,
-	GPIO_PB2,
-	GPIO_PB3,
-	GPIO_PB4,
-	GPIO_PB5,
-	GPIO_PB6,
-	GPIO_PB7,
-	GPIO_PC0,	/* pin 16 */
-	GPIO_PC1,
-	GPIO_PC2,
-	GPIO_PC3,
-	GPIO_PC4,
-	GPIO_PC5,
-	GPIO_PC6,
-	GPIO_PC7,
-	GPIO_PD0,	/* pin 24 */
-	GPIO_PD1,
-	GPIO_PD2,
-	GPIO_PD3,
-	GPIO_PD4,
-	GPIO_PD5,
-	GPIO_PD6,
-	GPIO_PD7,
-	GPIO_PE0,	/* pin 32 */
-	GPIO_PE1,
-	GPIO_PE2,
-	GPIO_PE3,
-	GPIO_PE4,
-	GPIO_PE5,
-	GPIO_PE6,
-	GPIO_PE7,
-	GPIO_PF0,	/* pin 40 */
-	GPIO_PF1,
-	GPIO_PF2,
-	GPIO_PF3,
-	GPIO_PF4,
-	GPIO_PF5,
-	GPIO_PF6,
-	GPIO_PF7,
-	GPIO_PG0,	/* pin 48 */
-	GPIO_PG1,
-	GPIO_PG2,
-	GPIO_PG3,
-	GPIO_PG4,
-	GPIO_PG5,
-	GPIO_PG6,
-	GPIO_PG7,
-	GPIO_PH0,	/* pin 56 */
-	GPIO_PH1,
-	GPIO_PH2,
-	GPIO_PH3,
-	GPIO_PH4,
-	GPIO_PH5,
-	GPIO_PH6,
-	GPIO_PH7,
-	GPIO_PI0,	/* pin 64 */
-	GPIO_PI1,
-	GPIO_PI2,
-	GPIO_PI3,
-	GPIO_PI4,
-	GPIO_PI5,
-	GPIO_PI6,
-	GPIO_PI7,
-	GPIO_PJ0,	/* pin 72 */
-	GPIO_PJ1,
-	GPIO_PJ2,
-	GPIO_PJ3,
-	GPIO_PJ4,
-	GPIO_PJ5,
-	GPIO_PJ6,
-	GPIO_PJ7,
-	GPIO_PK0,	/* pin 80 */
-	GPIO_PK1,
-	GPIO_PK2,
-	GPIO_PK3,
-	GPIO_PK4,
-	GPIO_PK5,
-	GPIO_PK6,
-	GPIO_PK7,
-	GPIO_PL0,	/* pin 88 */
-	GPIO_PL1,
-	GPIO_PL2,
-	GPIO_PL3,
-	GPIO_PL4,
-	GPIO_PL5,
-	GPIO_PL6,
-	GPIO_PL7,
-	GPIO_PM0,	/* pin 96 */
-	GPIO_PM1,
-	GPIO_PM2,
-	GPIO_PM3,
-	GPIO_PM4,
-	GPIO_PM5,
-	GPIO_PM6,
-	GPIO_PM7,
-	GPIO_PN0,	/* pin 104 */
-	GPIO_PN1,
-	GPIO_PN2,
-	GPIO_PN3,
-	GPIO_PN4,
-	GPIO_PN5,
-	GPIO_PN6,
-	GPIO_PN7,
-	GPIO_PO0,	/* pin 112 */
-	GPIO_PO1,
-	GPIO_PO2,
-	GPIO_PO3,
-	GPIO_PO4,
-	GPIO_PO5,
-	GPIO_PO6,
-	GPIO_PO7,
-	GPIO_PP0,	/* pin 120 */
-	GPIO_PP1,
-	GPIO_PP2,
-	GPIO_PP3,
-	GPIO_PP4,
-	GPIO_PP5,
-	GPIO_PP6,
-	GPIO_PP7,
-	GPIO_PQ0,	/* pin 128 */
-	GPIO_PQ1,
-	GPIO_PQ2,
-	GPIO_PQ3,
-	GPIO_PQ4,
-	GPIO_PQ5,
-	GPIO_PQ6,
-	GPIO_PQ7,
-	GPIO_PR0,	/* pin 136 */
-	GPIO_PR1,
-	GPIO_PR2,
-	GPIO_PR3,
-	GPIO_PR4,
-	GPIO_PR5,
-	GPIO_PR6,
-	GPIO_PR7,
-	GPIO_PS0,	/* pin 144 */
-	GPIO_PS1,
-	GPIO_PS2,
-	GPIO_PS3,
-	GPIO_PS4,
-	GPIO_PS5,
-	GPIO_PS6,
-	GPIO_PS7,
-	GPIO_PT0,	/* pin 152 */
-	GPIO_PT1,
-	GPIO_PT2,
-	GPIO_PT3,
-	GPIO_PT4,
-	GPIO_PT5,
-	GPIO_PT6,
-	GPIO_PT7,
-	GPIO_PU0,	/* pin 160 */
-	GPIO_PU1,
-	GPIO_PU2,
-	GPIO_PU3,
-	GPIO_PU4,
-	GPIO_PU5,
-	GPIO_PU6,
-	GPIO_PU7,
-	GPIO_PV0,	/* pin 168 */
-	GPIO_PV1,
-	GPIO_PV2,
-	GPIO_PV3,
-	GPIO_PV4,
-	GPIO_PV5,
-	GPIO_PV6,
-	GPIO_PV7,
-	GPIO_PW0,	/* pin 176 */
-	GPIO_PW1,
-	GPIO_PW2,
-	GPIO_PW3,
-	GPIO_PW4,
-	GPIO_PW5,
-	GPIO_PW6,
-	GPIO_PW7,
-	GPIO_PX0,	/* pin 184 */
-	GPIO_PX1,
-	GPIO_PX2,
-	GPIO_PX3,
-	GPIO_PX4,
-	GPIO_PX5,
-	GPIO_PX6,
-	GPIO_PX7,
-	GPIO_PY0,	/* pin 192 */
-	GPIO_PY1,
-	GPIO_PY2,
-	GPIO_PY3,
-	GPIO_PY4,
-	GPIO_PY5,
-	GPIO_PY6,
-	GPIO_PY7,
-	GPIO_PZ0,	/* pin 200 */
-	GPIO_PZ1,
-	GPIO_PZ2,
-	GPIO_PZ3,
-	GPIO_PZ4,
-	GPIO_PZ5,
-	GPIO_PZ6,
-	GPIO_PZ7,
-	GPIO_PAA0,	/* pin 208 */
-	GPIO_PAA1,
-	GPIO_PAA2,
-	GPIO_PAA3,
-	GPIO_PAA4,
-	GPIO_PAA5,
-	GPIO_PAA6,
-	GPIO_PAA7,
-	GPIO_PBB0,	/* pin 216 */
-	GPIO_PBB1,
-	GPIO_PBB2,
-	GPIO_PBB3,
-	GPIO_PBB4,
-	GPIO_PBB5,
-	GPIO_PBB6,
-	GPIO_PBB7,
-	GPIO_PCC0,	/* pin 224 */
-	GPIO_PCC1,
-	GPIO_PCC2,
-	GPIO_PCC3,
-	GPIO_PCC4,
-	GPIO_PCC5,
-	GPIO_PCC6,
-	GPIO_PCC7,
-	GPIO_PDD0,	/* pin 232 */
-	GPIO_PDD1,
-	GPIO_PDD2,
-	GPIO_PDD3,
-	GPIO_PDD4,
-	GPIO_PDD5,
-	GPIO_PDD6,
-	GPIO_PDD7,
-	GPIO_PEE0,	/* pin 240 */
-	GPIO_PEE1,
-	GPIO_PEE2,
-	GPIO_PEE3,
-	GPIO_PEE4,
-	GPIO_PEE5,
-	GPIO_PEE6,
-	GPIO_PEE7,	/* pin 247 */
-};
-
 #endif	/* _TEGRA30_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
index 021626dc14..1db2bd6a4f 100644
--- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h
@@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph);
 
 unsigned int zynqmp_get_silicon_version(void);
 
+void psu_init(void);
+
 #endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 11b80fb190..ae1e42fc06 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -15,6 +15,7 @@
  */
 
 #include <config.h>
+#include <asm/unified.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8fb05e18b9..07f384867e 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -145,6 +145,7 @@ struct prcm_regs {
 	u32 cm_ssc_modfreqdiv_dpll_unipro;
 	u32 cm_coreaon_usb_phy1_core_clkctrl;
 	u32 cm_coreaon_usb_phy2_core_clkctrl;
+	u32 cm_coreaon_usb_phy3_core_clkctrl;
 	u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
 
 	/* cm2.core */
@@ -717,6 +718,17 @@ static inline u8 is_dra72x(void)
 #define DRA722_ES2_0	0x07220200
 
 /*
+ * silicon device type
+ * Moving to common from cpu.h, since it is shared by various omap devices
+ */
+#define DEVICE_MASK         (BIT(8) | BIT(9) | BIT(10))
+#define TST_DEVICE          0x0
+#define EMU_DEVICE          0x1
+#define HS_DEVICE           0x2
+#define GP_DEVICE           0x3
+
+
+/*
  * SRAM scratch space entries
  */
 #define OMAP_SRAM_SCRATCH_OMAP_REV	SRAM_SCRATCH_SPACE_ADDR
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 128a606444..3704f077b0 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -18,7 +18,7 @@
 #ifndef __ARM_PSCI_H__
 #define __ARM_PSCI_H__
 
-/* PSCI interface */
+/* PSCI 0.1 interface */
 #define ARM_PSCI_FN_BASE		0x95c1ba5e
 #define ARM_PSCI_FN(n)			(ARM_PSCI_FN_BASE + (n))
 
@@ -32,6 +32,21 @@
 #define ARM_PSCI_RET_INVAL		(-2)
 #define ARM_PSCI_RET_DENIED		(-3)
 
+/* PSCI 0.2 interface */
+#define ARM_PSCI_0_2_FN_BASE			0x84000000
+#define ARM_PSCI_0_2_FN(n)			(ARM_PSCI_0_2_FN_BASE + (n))
+
+#define ARM_PSCI_0_2_FN_PSCI_VERSION		ARM_PSCI_0_2_FN(0)
+#define ARM_PSCI_0_2_FN_CPU_SUSPEND		ARM_PSCI_0_2_FN(1)
+#define ARM_PSCI_0_2_FN_CPU_OFF			ARM_PSCI_0_2_FN(2)
+#define ARM_PSCI_0_2_FN_CPU_ON			ARM_PSCI_0_2_FN(3)
+#define ARM_PSCI_0_2_FN_AFFINITY_INFO		ARM_PSCI_0_2_FN(4)
+#define ARM_PSCI_0_2_FN_MIGRATE			ARM_PSCI_0_2_FN(5)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE	ARM_PSCI_0_2_FN(6)
+#define ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU	ARM_PSCI_0_2_FN(7)
+#define ARM_PSCI_0_2_FN_SYSTEM_OFF		ARM_PSCI_0_2_FN(8)
+#define ARM_PSCI_0_2_FN_SYSTEM_RESET		ARM_PSCI_0_2_FN(9)
+
 #ifndef __ASSEMBLY__
 int psci_update_dt(void *fdt);
 void psci_board_init(void);
diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h
new file mode 100644
index 0000000000..b8b85b79dd
--- /dev/null
+++ b/arch/arm/include/asm/setjmp.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2016
+ * Alexander Graf <agraf@suse.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SETJMP_H_
+#define _SETJMP_H_	1
+
+struct jmp_buf_data {
+	ulong target;
+	ulong regs[5];
+};
+
+typedef struct jmp_buf_data jmp_buf[1];
+
+static inline int setjmp(jmp_buf jmp)
+{
+	long r = 0;
+
+#ifdef CONFIG_ARM64
+	asm volatile(
+		"adr x1, jmp_target\n"
+		"str x1, %1\n"
+		"stp x26, x27, %2\n"
+		"stp x28, x29, %3\n"
+		"mov x1, sp\n"
+		"str x1, %4\n"
+		"b 2f\n"
+		"jmp_target: "
+		"mov %0, #1\n"
+		"2:\n"
+		: "+r" (r), "=m" (jmp->target),
+		  "=m" (jmp->regs[0]), "=m" (jmp->regs[2]),
+		  "=m" (jmp->regs[4])
+		:
+		: "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+		  "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+		  "x16", "x17", "x18", "x19", "x20", "x21", "x22",
+		  "x23", "x24", "x25", /* x26, x27, x28, x29, sp */
+		  "x30", "cc", "memory");
+#else
+	asm volatile(
+#ifdef CONFIG_SYS_THUMB_BUILD
+		"adr r0, jmp_target + 1\n"
+#else
+		"adr r0, jmp_target\n"
+#endif
+		"mov r1, %1\n"
+		"mov r2, sp\n"
+		"stm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"b 2f\n"
+		"jmp_target: "
+		"mov %0, #1\n"
+		"2:\n"
+		: "+l" (r)
+		: "l" (&jmp->target)
+		: "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */
+		  "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr",
+		  "cc", "memory");
+#endif
+
+printf("%s:%d target=%#lx\n", __func__, __LINE__, jmp->target);
+
+	return r;
+}
+
+static inline __noreturn void longjmp(jmp_buf jmp)
+{
+#ifdef CONFIG_ARM64
+	asm volatile(
+		"ldr x0, %0\n"
+		"ldr x1, %3\n"
+		"mov sp, x1\n"
+		"ldp x26, x27, %1\n"
+		"ldp x28, x25, %2\n"
+		"mov x29, x25\n"
+		"br x0\n"
+		:
+		: "m" (jmp->target), "m" (jmp->regs[0]), "m" (jmp->regs[2]),
+		  "m" (jmp->regs[4])
+		: "x0", "x1", "x25", "x26", "x27", "x28");
+#else
+	asm volatile(
+		"mov r1, %0\n"
+		"ldm r1, {r0, r2, r4, r5, r6, r7}\n"
+		"mov sp, r2\n"
+		"bx r0\n"
+		:
+		: "l" (&jmp->target)
+		: "r1");
+#endif
+
+	while (1) { }
+}
+
+
+#endif /* _SETJMP_H_ */
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9ae890a830..2bdc0bec82 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -128,6 +128,8 @@ void hvc_call(struct pt_regs *args);
  */
 void smc_call(struct pt_regs *args);
 
+void __noreturn psci_system_reset(bool smc);
+
 #endif	/* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
diff --git a/arch/arm/include/asm/ti-common/davinci_nand.h b/arch/arm/include/asm/ti-common/davinci_nand.h
index 11407be144..f343ac2c0f 100644
--- a/arch/arm/include/asm/ti-common/davinci_nand.h
+++ b/arch/arm/include/asm/ti-common/davinci_nand.h
@@ -35,10 +35,12 @@ struct davinci_emif_regs {
 	uint32_t	sdrcr;
 	union {
 		uint32_t abncr[4];
-		uint32_t ab1cr;
-		uint32_t ab2cr;
-		uint32_t ab3cr;
-		uint32_t ab4cr;
+		struct {
+			uint32_t ab1cr;
+			uint32_t ab2cr;
+			uint32_t ab3cr;
+			uint32_t ab4cr;
+		};
 	};
 	uint32_t	sdtimr;
 	uint32_t	ddrsr;
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 0000000000..1b26002305
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,129 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+	.syntax unified
+#endif
+
+#ifdef CONFIG_CPU_V7M
+#define AR_CLASS(x...)
+#define M_CLASS(x...)	x
+#else
+#define AR_CLASS(x...)	x
+#define M_CLASS(x...)
+#endif
+
+#ifdef CONFIG_THUMB2_KERNEL
+
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE	PSR_T_BIT
+
+#define ARM(x...)
+#define THUMB(x...)	x
+#ifdef __ASSEMBLY__
+#define W(instr)	instr.w
+#else
+#define WASM(instr)	#instr ".w"
+#endif
+
+#else	/* !CONFIG_THUMB2_KERNEL */
+
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE	0
+
+#define ARM(x...)	x
+#define THUMB(x...)
+#ifdef __ASSEMBLY__
+#define W(instr)	instr
+#else
+#define WASM(instr)	#instr
+#endif
+
+#endif	/* CONFIG_THUMB2_KERNEL */
+
+#ifndef CONFIG_ARM_ASM_UNIFIED
+
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+	.macro	it, cond
+	.endm
+	.macro	itt, cond
+	.endm
+	.macro	ite, cond
+	.endm
+	.macro	ittt, cond
+	.endm
+	.macro	itte, cond
+	.endm
+	.macro	itet, cond
+	.endm
+	.macro	itee, cond
+	.endm
+	.macro	itttt, cond
+	.endm
+	.macro	ittte, cond
+	.endm
+	.macro	ittet, cond
+	.endm
+	.macro	ittee, cond
+	.endm
+	.macro	itett, cond
+	.endm
+	.macro	itete, cond
+	.endm
+	.macro	iteet, cond
+	.endm
+	.macro	iteee, cond
+	.endm
+#else	/* !__ASSEMBLY__ */
+__asm__(
+"	.macro	it, cond\n"
+"	.endm\n"
+"	.macro	itt, cond\n"
+"	.endm\n"
+"	.macro	ite, cond\n"
+"	.endm\n"
+"	.macro	ittt, cond\n"
+"	.endm\n"
+"	.macro	itte, cond\n"
+"	.endm\n"
+"	.macro	itet, cond\n"
+"	.endm\n"
+"	.macro	itee, cond\n"
+"	.endm\n"
+"	.macro	itttt, cond\n"
+"	.endm\n"
+"	.macro	ittte, cond\n"
+"	.endm\n"
+"	.macro	ittet, cond\n"
+"	.endm\n"
+"	.macro	ittee, cond\n"
+"	.endm\n"
+"	.macro	itett, cond\n"
+"	.endm\n"
+"	.macro	itete, cond\n"
+"	.endm\n"
+"	.macro	iteet, cond\n"
+"	.endm\n"
+"	.macro	iteee, cond\n"
+"	.endm\n");
+#endif	/* __ASSEMBLY__ */
+
+#endif	/* CONFIG_ARM_ASM_UNIFIED */
+
+#endif	/* !__ASM_UNIFIED_H */
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 7a0fb5862e..0e05e87dea 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -5,9 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
-			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o \
-			_uldivmod.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \
+				    lib1funcs.o uldivmod.o div0.o \
+				    div64.o muldi3.o
 
 ifdef CONFIG_CPU_V7M
 obj-y	+= vectors_m.o crt0.o
@@ -46,7 +46,7 @@ obj-y	+= interrupts_64.o
 else
 obj-y	+= interrupts.o
 endif
-ifndef CONFIG_RESET
+ifndef CONFIG_SYSRESET
 obj-y	+= reset.o
 endif
 
@@ -62,9 +62,17 @@ ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y	+= eabi_compat.o
 endif
 
+asflags-y += -DCONFIG_ARM_ASM_UNIFIED
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+asflags-y += -D__LINUX_ARM_ARCH__=4
+else
+asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
 # some files can only build in ARM or THUMB2, not THUMB1
 
 ifdef CONFIG_SYS_THUMB_BUILD
+asflags-$(CONFIG_HAS_THUMB2) += -DCONFIG_THUMB2_KERNEL
 ifndef CONFIG_HAS_THUMB2
 
 # for C files, just apend -marm, which will override previous -mthumb*
@@ -82,6 +90,5 @@ AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
 AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
 AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
 AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
-
 endif
 endif
diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S
deleted file mode 100644
index c463c68f85..0000000000
--- a/arch/arm/lib/_divsi3.S
+++ /dev/null
@@ -1,143 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_DIV_BODY dividend, divisor, result, curbit
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\curbit, \divisor
-	clz	\result, \dividend
-	sub	\result, \curbit, \result
-	mov	\curbit, #1
-	mov	\divisor, \divisor, lsl \result
-	mov	\curbit, \curbit, lsl \result
-	mov	\result, #0
-
-#else
-
-	@ Initially shift the divisor left 3 bits if possible,
-	@ set curbit accordingly.  This allows for curbit to be located
-	@ at the left end of each 4 bit nibbles in the division loop
-	@ to save one loop in most cases.
-	tst	\divisor, #0xe0000000
-	moveq	\divisor, \divisor, lsl #3
-	moveq	\curbit, #8
-	movne	\curbit, #1
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	movlo	\curbit, \curbit, lsl #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	movlo	\curbit, \curbit, lsl #1
-	blo	1b
-
-	mov	\result, #0
-
-#endif
-
-	@ Division loop
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	orrhs	\result,   \result,   \curbit
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	orrhs	\result,   \result,   \curbit,  lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	orrhs	\result,   \result,   \curbit,  lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	orrhs	\result,   \result,   \curbit,  lsr #3
-	cmp	\dividend, #0			@ Early termination?
-	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
-	movne	\divisor,  \divisor, lsr #4
-	bne	1b
-
-.endm
-
-.macro ARM_DIV2_ORDER divisor, order
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	rsb	\order, \order, #31
-
-#else
-
-	cmp	\divisor, #(1 << 16)
-	movhs	\divisor, \divisor, lsr #16
-	movhs	\order, #16
-	movlo	\order, #0
-
-	cmp	\divisor, #(1 << 8)
-	movhs	\divisor, \divisor, lsr #8
-	addhs	\order, \order, #8
-
-	cmp	\divisor, #(1 << 4)
-	movhs	\divisor, \divisor, lsr #4
-	addhs	\order, \order, #4
-
-	cmp	\divisor, #(1 << 2)
-	addhi	\order, \order, #3
-	addls	\order, \order, \divisor, lsr #1
-
-#endif
-
-.endm
-
-	.align	5
-.globl __divsi3
-__divsi3:
-ENTRY(__aeabi_idiv)
-	cmp	r1, #0
-	eor	ip, r0, r1			@ save the sign of the result.
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	subs	r2, r1, #1			@ division by 1 or -1 ?
-	beq	10f
-	movs	r3, r0
-	rsbmi	r3, r0, #0			@ positive dividend value
-	cmp	r3, r1
-	bls	11f
-	tst	r1, r2				@ divisor is power of 2 ?
-	beq	12f
-
-	ARM_DIV_BODY r3, r1, r0, r2
-
-	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-10:	teq	ip, r0				@ same sign ?
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-11:	movlo	r0, #0
-	moveq	r0, ip, asr #31
-	orreq	r0, r0, #1
-	mov	pc, lr
-
-12:	ARM_DIV2_ORDER r1, r2
-
-	cmp	ip, #0
-	mov	r0, r3, lsr r2
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
-ENDPROC(__aeabi_idiv)
diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S
deleted file mode 100644
index c5e1c229df..0000000000
--- a/arch/arm/lib/_modsi3.S
+++ /dev/null
@@ -1,99 +0,0 @@
-#include <linux/linkage.h>
-
-.macro ARM_MOD_BODY dividend, divisor, order, spare
-
-#if __LINUX_ARM_ARCH__ >= 5
-
-	clz	\order, \divisor
-	clz	\spare, \dividend
-	sub	\order, \order, \spare
-	mov	\divisor, \divisor, lsl \order
-
-#else
-
-	mov	\order, #0
-
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-1:	cmp	\divisor, #0x10000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #4
-	addlo	\order, \order, #4
-	blo	1b
-
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-1:	cmp	\divisor, #0x80000000
-	cmplo	\divisor, \dividend
-	movlo	\divisor, \divisor, lsl #1
-	addlo	\order, \order, #1
-	blo	1b
-
-#endif
-
-	@ Perform all needed substractions to keep only the reminder.
-	@ Do comparisons in batch of 4 first.
-	subs	\order, \order, #3		@ yes, 3 is intended here
-	blt	2f
-
-1:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	cmp	\dividend, \divisor,  lsr #1
-	subhs	\dividend, \dividend, \divisor, lsr #1
-	cmp	\dividend, \divisor,  lsr #2
-	subhs	\dividend, \dividend, \divisor, lsr #2
-	cmp	\dividend, \divisor,  lsr #3
-	subhs	\dividend, \dividend, \divisor, lsr #3
-	cmp	\dividend, #1
-	mov	\divisor, \divisor, lsr #4
-	subges	\order, \order, #4
-	bge	1b
-
-	tst	\order, #3
-	teqne	\dividend, #0
-	beq	5f
-
-	@ Either 1, 2 or 3 comparison/substractions are left.
-2:	cmn	\order, #2
-	blt	4f
-	beq	3f
-	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-3:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-	mov	\divisor,  \divisor,  lsr #1
-4:	cmp	\dividend, \divisor
-	subhs	\dividend, \dividend, \divisor
-5:
-.endm
-
-	.align	5
-ENTRY(__modsi3)
-	cmp	r1, #0
-	beq	Ldiv0
-	rsbmi	r1, r1, #0			@ loops below use unsigned.
-	movs	ip, r0				@ preserve sign of dividend
-	rsbmi	r0, r0, #0			@ if negative make positive
-	subs	r2, r1, #1			@ compare divisor with 1
-	cmpne	r0, r1				@ compare dividend with divisor
-	moveq	r0, #0
-	tsthi	r1, r2				@ see if divisor is power of 2
-	andeq	r0, r0, r2
-	bls	10f
-
-	ARM_MOD_BODY r0, r1, r2, r3
-
-10:	cmp	ip, #0
-	rsbmi	r0, r0, #0
-	mov	pc, lr
-ENDPROC(__modsi3)
-
-Ldiv0:
-
-	str	lr, [sp, #-4]!
-	bl	__div0
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	pc, [sp], #4
diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S
deleted file mode 100644
index 3b653bed99..0000000000
--- a/arch/arm/lib/_udivsi3.S
+++ /dev/null
@@ -1,95 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-dividend	.req	r0
-divisor		.req	r1
-result		.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.globl	 __udivsi3
-	.type	__udivsi3 ,function
-	.globl	__aeabi_uidiv
-	.type	__aeabi_uidiv ,function
-	.align	0
- __udivsi3:
- __aeabi_uidiv:
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	mov	result, #0
-	cmp	dividend, divisor
-	bcc	Lgot_result
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions, and note which bits
-	@ are done in the result.  On the final pass, this may subtract
-	@ too much from the dividend, but the result will be ok, since the
-	@ "bit" will have been shifted out at the bottom.
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	orrcs	result, result, curbit
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	result, result, curbit, lsr #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	result, result, curbit, lsr #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	result, result, curbit, lsr #3
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-Lgot_result:
-	mov	r0, result
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __udivsi3       , . -  __udivsi3
-
-ENTRY(__aeabi_uidivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_uidiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_uidivmod)
-
-ENTRY(__aeabi_idivmod)
-
-	stmfd	sp!, {r0, r1, ip, lr}
-	bl	__aeabi_idiv
-	ldmfd	sp!, {r1, r2, ip, lr}
-	mul	r3, r0, r2
-	sub	r1, r1, r3
-	mov	pc, lr
-ENDPROC(__aeabi_idivmod)
diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S
deleted file mode 100644
index b1667376c5..0000000000
--- a/arch/arm/lib/_umodsi3.S
+++ /dev/null
@@ -1,90 +0,0 @@
-#include <linux/linkage.h>
-
-/* # 1 "libgcc1.S" */
-@ libgcc1 routines for ARM cpu.
-@ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk)
-/* # 145 "libgcc1.S" */
-dividend	.req	r0
-divisor		.req	r1
-overdone	.req	r2
-curbit		.req	r3
-/* ip		.req	r12	*/
-/* sp		.req	r13	*/
-/* lr		.req	r14	*/
-/* pc		.req	r15	*/
-	.text
-	.type  __umodsi3       ,function
-	.align 0
- ENTRY(__umodsi3)
-	cmp	divisor, #0
-	beq	Ldiv0
-	mov	curbit, #1
-	cmp	dividend, divisor
-	movcc	pc, lr
-Loop1:
-	@ Unless the divisor is very big, shift it up in multiples of
-	@ four bits, since this is the amount of unwinding in the main
-	@ division loop.  Continue shifting until the divisor is
-	@ larger than the dividend.
-	cmp	divisor, #0x10000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #4
-	movcc	curbit, curbit, lsl #4
-	bcc	Loop1
-Lbignum:
-	@ For very big divisors, we must shift it a bit at a time, or
-	@ we will be in danger of overflowing.
-	cmp	divisor, #0x80000000
-	cmpcc	divisor, dividend
-	movcc	divisor, divisor, lsl #1
-	movcc	curbit, curbit, lsl #1
-	bcc	Lbignum
-Loop3:
-	@ Test for possible subtractions.  On the final pass, this may
-	@ subtract too much from the dividend, so keep track of which
-	@ subtractions are done, we can fix them up afterwards...
-	mov	overdone, #0
-	cmp	dividend, divisor
-	subcs	dividend, dividend, divisor
-	cmp	dividend, divisor, lsr #1
-	subcs	dividend, dividend, divisor, lsr #1
-	orrcs	overdone, overdone, curbit, ror #1
-	cmp	dividend, divisor, lsr #2
-	subcs	dividend, dividend, divisor, lsr #2
-	orrcs	overdone, overdone, curbit, ror #2
-	cmp	dividend, divisor, lsr #3
-	subcs	dividend, dividend, divisor, lsr #3
-	orrcs	overdone, overdone, curbit, ror #3
-	mov	ip, curbit
-	cmp	dividend, #0			@ Early termination?
-	movnes	curbit, curbit, lsr #4		@ No, any more bits to do?
-	movne	divisor, divisor, lsr #4
-	bne	Loop3
-	@ Any subtractions that we should not have done will be recorded in
-	@ the top three bits of "overdone".  Exactly which were not needed
-	@ are governed by the position of the bit, stored in ip.
-	@ If we terminated early, because dividend became zero,
-	@ then none of the below will match, since the bit in ip will not be
-	@ in the bottom nibble.
-	ands	overdone, overdone, #0xe0000000
-	moveq	pc, lr				@ No fixups needed
-	tst	overdone, ip, ror #3
-	addne	dividend, dividend, divisor, lsr #3
-	tst	overdone, ip, ror #2
-	addne	dividend, dividend, divisor, lsr #2
-	tst	overdone, ip, ror #1
-	addne	dividend, dividend, divisor, lsr #1
-	mov	pc, lr
-Ldiv0:
-	str	lr, [sp, #-4]!
-	bl	 __div0       (PLT)
-	mov	r0, #0			@ about as wrong as it could be
-	ldmia	sp!, {pc}
-	.size  __umodsi3       , . -  __umodsi3
-/* # 320 "libgcc1.S" */
-/* # 421 "libgcc1.S" */
-/* # 433 "libgcc1.S" */
-/* # 456 "libgcc1.S" */
-/* # 500 "libgcc1.S" */
-/* # 580 "libgcc1.S" */
-ENDPROC(__umodsi3)
diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/ashldi3.S
index 9c34c212cb..e9ec890881 100644
--- a/arch/arm/lib/_ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,20 @@
 #define ah r1
 #endif
 
-.globl __ashldi3
-__ashldi3:
+.pushsection .text.__ashldi3, "ax"
+ENTRY(__ashldi3)
 ENTRY(__aeabi_llsl)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	ah, ah, lsl r2
 	movpl	ah, al, lsl r3
-	orrmi	ah, ah, al, lsr ip
+ ARM(	orrmi	ah, ah, al, lsr ip	)
+ THUMB(	lsrmi	r3, al, ip		)
+ THUMB(	orrmi	ah, ah, r3		)
 	mov	al, al, lsl r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__ashldi3)
 ENDPROC(__aeabi_llsl)
+.popsection
diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/ashrdi3.S
index c74fd64499..6e15774c0a 100644
--- a/arch/arm/lib/_ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,20 @@
 #define ah r1
 #endif
 
-.globl __ashrdi3
-__ashrdi3:
+.pushsection .text.__ashrdi3, "ax"
+ENTRY(__ashrdi3)
 ENTRY(__aeabi_lasr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	al, al, lsr r2
 	movpl	al, ah, asr r3
-	orrmi	al, al, ah, lsl ip
+ ARM(	orrmi	al, al, ah, lsl ip	)
+ THUMB(	lslmi	r3, ah, ip		)
+ THUMB(	orrmi	al, al, r3		)
 	mov	ah, ah, asr r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__ashrdi3)
 ENDPROC(__aeabi_lasr)
+.popsection
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
new file mode 100644
index 0000000000..b417db222d
--- /dev/null
+++ b/arch/arm/lib/div64.S
@@ -0,0 +1,214 @@
+/*
+ *  linux/arch/arm/lib/div64.S
+ *
+ *  Optimized computation of 64-bit dividend / 32-bit divisor
+ *
+ *  Author:	Nicolas Pitre
+ *  Created:	Oct 5, 2003
+ *  Copyright:	Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#endif
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+/*
+ * __do_div64: perform a division with 64-bit dividend and 32-bit divisor.
+ *
+ * Note: Calling convention is totally non standard for optimal code.
+ *       This is meant to be used by do_div() from include/asm/div64.h only.
+ *
+ * Input parameters:
+ * 	xh-xl	= dividend (clobbered)
+ * 	r4	= divisor (preserved)
+ *
+ * Output values:
+ * 	yh-yl	= result
+ * 	xh	= remainder
+ *
+ * Clobbered regs: xl, ip
+ */
+
+.pushsection .text.__do_div64, "ax"
+ENTRY(__do_div64)
+UNWIND(.fnstart)
+
+	@ Test for easy paths first.
+	subs	ip, r4, #1
+	bls	9f			@ divisor is 0 or 1
+	tst	ip, r4
+	beq	8f			@ divisor is power of 2
+
+	@ See if we need to handle upper 32-bit result.
+	cmp	xh, r4
+	mov	yh, #0
+	blo	3f
+
+	@ Align divisor with upper part of dividend.
+	@ The aligned divisor is stored in yl preserving the original.
+	@ The bit position is stored in ip.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	yl, r4
+	clz	ip, xh
+	sub	yl, yl, ip
+	mov	ip, #1
+	mov	ip, ip, lsl yl
+	mov	yl, r4, lsl yl
+
+#else
+
+	mov	yl, r4
+	mov	ip, #1
+1:	cmp	yl, #0x80000000
+	cmpcc	yl, xh
+	movcc	yl, yl, lsl #1
+	movcc	ip, ip, lsl #1
+	bcc	1b
+
+#endif
+
+	@ The division loop for needed upper bit positions.
+ 	@ Break out early if dividend reaches 0.
+2:	cmp	xh, yl
+	orrcs	yh, yh, ip
+	subscs	xh, xh, yl
+	movsne	ip, ip, lsr #1
+	mov	yl, yl, lsr #1
+	bne	2b
+
+	@ See if we need to handle lower 32-bit result.
+3:	cmp	xh, #0
+	mov	yl, #0
+	cmpeq	xl, r4
+	movlo	xh, xl
+	retlo	lr
+
+	@ The division loop for lower bit positions.
+	@ Here we shift remainer bits leftwards rather than moving the
+	@ divisor for comparisons, considering the carry-out bit as well.
+	mov	ip, #0x80000000
+4:	movs	xl, xl, lsl #1
+	adcs	xh, xh, xh
+	beq	6f
+	cmpcc	xh, r4
+5:	orrcs	yl, yl, ip
+	subcs	xh, xh, r4
+	movs	ip, ip, lsr #1
+	bne	4b
+	ret	lr
+
+	@ The top part of remainder became zero.  If carry is set
+	@ (the 33th bit) this is a false positive so resume the loop.
+	@ Otherwise, if lower part is also null then we are done.
+6:	bcs	5b
+	cmp	xl, #0
+	reteq	lr
+
+	@ We still have remainer bits in the low part.  Bring them up.
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	xh, xl			@ we know xh is zero here so...
+	add	xh, xh, #1
+	mov	xl, xl, lsl xh
+	mov	ip, ip, lsr xh
+
+#else
+
+7:	movs	xl, xl, lsl #1
+	mov	ip, ip, lsr #1
+	bcc	7b
+
+#endif
+
+	@ Current remainder is now 1.  It is worthless to compare with
+	@ divisor at this point since divisor can not be smaller than 3 here.
+	@ If possible, branch for another shift in the division loop.
+	@ If no bit position left then we are done.
+	movs	ip, ip, lsr #1
+	mov	xh, #1
+	bne	4b
+	ret	lr
+
+8:	@ Division by a power of 2: determine what that divisor order is
+	@ then simply shift values around
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	ip, r4
+	rsb	ip, ip, #31
+
+#else
+
+	mov	yl, r4
+	cmp	r4, #(1 << 16)
+	mov	ip, #0
+	movhs	yl, yl, lsr #16
+	movhs	ip, #16
+
+	cmp	yl, #(1 << 8)
+	movhs	yl, yl, lsr #8
+	addhs	ip, ip, #8
+
+	cmp	yl, #(1 << 4)
+	movhs	yl, yl, lsr #4
+	addhs	ip, ip, #4
+
+	cmp	yl, #(1 << 2)
+	addhi	ip, ip, #3
+	addls	ip, ip, yl, lsr #1
+
+#endif
+
+	mov	yh, xh, lsr ip
+	mov	yl, xl, lsr ip
+	rsb	ip, ip, #32
+ ARM(	orr	yl, yl, xh, lsl ip	)
+ THUMB(	lsl	xh, xh, ip		)
+ THUMB(	orr	yl, yl, xh		)
+	mov	xh, xl, lsl ip
+	mov	xh, xh, lsr ip
+	ret	lr
+
+	@ eq -> division by 1: obvious enough...
+9:	moveq	yl, xl
+	moveq	yh, xh
+	moveq	xh, #0
+	reteq	lr
+UNWIND(.fnend)
+
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+Ldiv0_64:
+	@ Division by 0:
+	str	lr, [sp, #-8]!
+	bl	__div0
+
+	@ as wrong as it could be...
+	mov	yl, #0
+	mov	yh, #0
+	mov	xh, #0
+	ldr	pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(__do_div64)
+.popsection
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
new file mode 100644
index 0000000000..76968cee17
--- /dev/null
+++ b/arch/arm/lib/lib1funcs.S
@@ -0,0 +1,429 @@
+/*
+ * linux/arch/arm/lib/lib1funcs.S: Optimized ARM division routines
+ *
+ * Author: Nicolas Pitre <nico@fluxnic.net>
+ *   - contributed to gcc-3.4 on Sep 30, 2003
+ *   - adapted for the Linux kernel on Oct 2, 2003
+ */
+
+/* Copyright 1995, 1996, 1998, 1999, 2000, 2003 Free Software Foundation, Inc.
+
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * U-Boot compatibility bit, define empty UNWIND() macro as, since we
+ * do not support stack unwinding and define CONFIG_AEABI to make all
+ * of the functions available without diverging from Linux code.
+ */
+#ifdef __UBOOT__
+#define UNWIND(x...)
+#define CONFIG_AEABI
+#endif
+
+.macro ARM_DIV_BODY dividend, divisor, result, curbit
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\curbit, \divisor
+	clz	\result, \dividend
+	sub	\result, \curbit, \result
+	mov	\curbit, #1
+	mov	\divisor, \divisor, lsl \result
+	mov	\curbit, \curbit, lsl \result
+	mov	\result, #0
+	
+#else
+
+	@ Initially shift the divisor left 3 bits if possible,
+	@ set curbit accordingly.  This allows for curbit to be located
+	@ at the left end of each 4 bit nibbles in the division loop
+	@ to save one loop in most cases.
+	tst	\divisor, #0xe0000000
+	moveq	\divisor, \divisor, lsl #3
+	moveq	\curbit, #8
+	movne	\curbit, #1
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	movlo	\curbit, \curbit, lsl #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	movlo	\curbit, \curbit, lsl #1
+	blo	1b
+
+	mov	\result, #0
+
+#endif
+
+	@ Division loop
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	orrhs	\result,   \result,   \curbit
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	orrhs	\result,   \result,   \curbit,  lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	orrhs	\result,   \result,   \curbit,  lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	orrhs	\result,   \result,   \curbit,  lsr #3
+	cmp	\dividend, #0			@ Early termination?
+	movsne	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+	movne	\divisor,  \divisor, lsr #4
+	bne	1b
+
+.endm
+
+
+.macro ARM_DIV2_ORDER divisor, order
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	rsb	\order, \order, #31
+
+#else
+
+	cmp	\divisor, #(1 << 16)
+	movhs	\divisor, \divisor, lsr #16
+	movhs	\order, #16
+	movlo	\order, #0
+
+	cmp	\divisor, #(1 << 8)
+	movhs	\divisor, \divisor, lsr #8
+	addhs	\order, \order, #8
+
+	cmp	\divisor, #(1 << 4)
+	movhs	\divisor, \divisor, lsr #4
+	addhs	\order, \order, #4
+
+	cmp	\divisor, #(1 << 2)
+	addhi	\order, \order, #3
+	addls	\order, \order, \divisor, lsr #1
+
+#endif
+
+.endm
+
+
+.macro ARM_MOD_BODY dividend, divisor, order, spare
+
+#if __LINUX_ARM_ARCH__ >= 5
+
+	clz	\order, \divisor
+	clz	\spare, \dividend
+	sub	\order, \order, \spare
+	mov	\divisor, \divisor, lsl \order
+
+#else
+
+	mov	\order, #0
+
+	@ Unless the divisor is very big, shift it up in multiples of
+	@ four bits, since this is the amount of unwinding in the main
+	@ division loop.  Continue shifting until the divisor is 
+	@ larger than the dividend.
+1:	cmp	\divisor, #0x10000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #4
+	addlo	\order, \order, #4
+	blo	1b
+
+	@ For very big divisors, we must shift it a bit at a time, or
+	@ we will be in danger of overflowing.
+1:	cmp	\divisor, #0x80000000
+	cmplo	\divisor, \dividend
+	movlo	\divisor, \divisor, lsl #1
+	addlo	\order, \order, #1
+	blo	1b
+
+#endif
+
+	@ Perform all needed subtractions to keep only the reminder.
+	@ Do comparisons in batch of 4 first.
+	subs	\order, \order, #3		@ yes, 3 is intended here
+	blt	2f
+
+1:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	cmp	\dividend, \divisor,  lsr #1
+	subhs	\dividend, \dividend, \divisor, lsr #1
+	cmp	\dividend, \divisor,  lsr #2
+	subhs	\dividend, \dividend, \divisor, lsr #2
+	cmp	\dividend, \divisor,  lsr #3
+	subhs	\dividend, \dividend, \divisor, lsr #3
+	cmp	\dividend, #1
+	mov	\divisor, \divisor, lsr #4
+	subsge	\order, \order, #4
+	bge	1b
+
+	tst	\order, #3
+	teqne	\dividend, #0
+	beq	5f
+
+	@ Either 1, 2 or 3 comparison/subtractions are left.
+2:	cmn	\order, #2
+	blt	4f
+	beq	3f
+	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+3:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+	mov	\divisor,  \divisor,  lsr #1
+4:	cmp	\dividend, \divisor
+	subhs	\dividend, \dividend, \divisor
+5:
+.endm
+
+
+.pushsection .text.__udivsi3, "ax"
+ENTRY(__udivsi3)
+ENTRY(__aeabi_uidiv)
+UNWIND(.fnstart)
+
+	subs	r2, r1, #1
+	reteq	lr
+	bcc	Ldiv0
+	cmp	r0, r1
+	bls	11f
+	tst	r1, r2
+	beq	12f
+
+	ARM_DIV_BODY r0, r1, r2, r3
+
+	mov	r0, r2
+	ret	lr
+
+11:	moveq	r0, #1
+	movne	r0, #0
+	ret	lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	mov	r0, r0, lsr r2
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__udivsi3)
+ENDPROC(__aeabi_uidiv)
+.popsection
+
+.pushsection .text.__umodsi3, "ax"
+ENTRY(__umodsi3)
+UNWIND(.fnstart)
+
+	subs	r2, r1, #1			@ compare divisor with 1
+	bcc	Ldiv0
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq   r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	retls	lr
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__umodsi3)
+.popsection
+
+.pushsection .text.__divsi3, "ax"
+ENTRY(__divsi3)
+ENTRY(__aeabi_idiv)
+UNWIND(.fnstart)
+
+	cmp	r1, #0
+	eor	ip, r0, r1			@ save the sign of the result.
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	subs	r2, r1, #1			@ division by 1 or -1 ?
+	beq	10f
+	movs	r3, r0
+	rsbmi	r3, r0, #0			@ positive dividend value
+	cmp	r3, r1
+	bls	11f
+	tst	r1, r2				@ divisor is power of 2 ?
+	beq	12f
+
+	ARM_DIV_BODY r3, r1, r0, r2
+
+	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	ret	lr
+
+10:	teq	ip, r0				@ same sign ?
+	rsbmi	r0, r0, #0
+	ret	lr
+
+11:	movlo	r0, #0
+	moveq	r0, ip, asr #31
+	orreq	r0, r0, #1
+	ret	lr
+
+12:	ARM_DIV2_ORDER r1, r2
+
+	cmp	ip, #0
+	mov	r0, r3, lsr r2
+	rsbmi	r0, r0, #0
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__divsi3)
+ENDPROC(__aeabi_idiv)
+.popsection
+
+.pushsection .text.__modsi3, "ax"
+ENTRY(__modsi3)
+UNWIND(.fnstart)
+
+	cmp	r1, #0
+	beq	Ldiv0
+	rsbmi	r1, r1, #0			@ loops below use unsigned.
+	movs	ip, r0				@ preserve sign of dividend
+	rsbmi	r0, r0, #0			@ if negative make positive
+	subs	r2, r1, #1			@ compare divisor with 1
+	cmpne	r0, r1				@ compare dividend with divisor
+	moveq	r0, #0
+	tsthi	r1, r2				@ see if divisor is power of 2
+	andeq	r0, r0, r2
+	bls	10f
+
+	ARM_MOD_BODY r0, r1, r2, r3
+
+10:	cmp	ip, #0
+	rsbmi	r0, r0, #0
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__modsi3)
+.popsection
+
+#ifdef CONFIG_AEABI
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_uidivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}	)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_uidiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_uidivmod)
+.popsection
+
+.pushsection .text.__aeabi_uidivmod, "ax"
+ENTRY(__aeabi_idivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}	)
+
+	stmfd	sp!, {r0, r1, ip, lr}
+	bl	__aeabi_idiv
+	ldmfd	sp!, {r1, r2, ip, lr}
+	mul	r3, r0, r2
+	sub	r1, r1, r3
+	ret	lr
+
+UNWIND(.fnend)
+ENDPROC(__aeabi_idivmod)
+.popsection
+
+#endif
+
+.pushsection .text.Ldiv0, "ax"
+Ldiv0:
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
+
+	str	lr, [sp, #-8]!
+	bl	__div0
+	mov	r0, #0			@ About as wrong as it could be.
+	ldr	pc, [sp], #8
+
+UNWIND(.fnend)
+ENDPROC(Ldiv0)
+.popsection
+
+/* Thumb-1 specialities */
+#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(CONFIG_HAS_THUMB2)
+.pushsection .text.__gnu_thumb1_case_sqi, "ax"
+ENTRY(__gnu_thumb1_case_sqi)
+	push	{r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r1, r1, #1
+	ldrsb	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_sqi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_uqi, "ax"
+ENTRY(__gnu_thumb1_case_uqi)
+	push	{r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r1, r1, #1
+	ldrb	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_uqi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_shi, "ax"
+ENTRY(__gnu_thumb1_case_shi)
+	push	{r0, r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r0, r0, #1
+	lsls	r1, r1, #1
+	ldrsh	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r0, r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_shi)
+.popsection
+
+.pushsection .text.__gnu_thumb1_case_uhi, "ax"
+ENTRY(__gnu_thumb1_case_uhi)
+	push	{r0, r1}
+	mov	r1, lr
+	lsrs	r1, r1, #1
+	lsls	r0, r0, #1
+	lsls	r1, r1, #1
+	ldrh	r1, [r1, r0]
+	lsls	r1, r1, #1
+	add	lr, lr, r1
+	pop	{r0, r1}
+	bx	lr
+ENDPROC(__gnu_thumb1_case_uhi)
+.popsection
+#endif
diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 1f9b916464..ead33e53c7 100644
--- a/arch/arm/lib/_lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -5,6 +5,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 
 #ifdef __ARMEB__
 #define al r1
@@ -14,15 +15,20 @@
 #define ah r1
 #endif
 
-.globl __lshrdi3
-__lshrdi3:
+.pushsection .text.__lshldi3, "ax"
+ENTRY(__lshrdi3)
 ENTRY(__aeabi_llsr)
 
 	subs	r3, r2, #32
 	rsb	ip, r2, #32
 	movmi	al, al, lsr r2
 	movpl	al, ah, lsr r3
-	orrmi	al, al, ah, lsl ip
+ ARM(	orrmi	al, al, ah, lsl ip	)
+ THUMB(	lslmi	r3, ah, ip		)
+ THUMB(	orrmi	al, al, r3		)
 	mov	ah, ah, lsr r2
-	mov	pc, lr
+	ret	lr
+
+ENDPROC(__lshrdi3)
 ENDPROC(__aeabi_llsr)
+.popsection
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index 7d9fc0f9be..00602e9cf8 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,12 +13,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
-#define W(instr)	instr.w
-#else
-#define W(instr)	instr
-#endif
-
 #define LDR1W_SHIFT	0
 #define STR1W_SHIFT	0
 
diff --git a/arch/arm/lib/muldi3.S b/arch/arm/lib/muldi3.S
new file mode 100644
index 0000000000..d7c93e702e
--- /dev/null
+++ b/arch/arm/lib/muldi3.S
@@ -0,0 +1,48 @@
+/*
+ *  linux/arch/arm/lib/muldi3.S
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Oct 19, 2005
+ *  Copyright:  Monta Vista Software, Inc.
+ *
+ *  SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#ifdef __ARMEB__
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#else
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#endif
+
+.pushsection .text.__muldi3, "ax"
+ENTRY(__muldi3)
+ENTRY(__aeabi_lmul)
+
+	mul	xh, yl, xh
+	mla	xh, xl, yh, xh
+	mov	ip, xl, lsr #16
+	mov	yh, yl, lsr #16
+	bic	xl, xl, ip, lsl #16
+	bic	yl, yl, yh, lsl #16
+	mla	xh, yh, ip, xh
+	mul	yh, xl, yh
+	mul	xl, yl, xl
+	mul	ip, yl, ip
+	adds	xl, xl, yh, lsl #16
+	adc	xh, xh, yh, lsr #16
+	adds	xl, xl, ip, lsl #16
+	adc	xh, xh, ip, lsr #16
+	ret	lr
+
+ENDPROC(__muldi3)
+ENDPROC(__aeabi_lmul)
+.popsection
diff --git a/arch/arm/lib/_uldivmod.S b/arch/arm/lib/uldivmod.S
index 426c2f2406..724699658b 100644
--- a/arch/arm/lib/_uldivmod.S
+++ b/arch/arm/lib/uldivmod.S
@@ -9,10 +9,6 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-/* We don't use Thumb instructions for now */
-#define ARM(x...)	x
-#define THUMB(x...)
-
 /*
  * A, Q = r0 + (r1 << 32)
  * B, R = r2 + (r3 << 32)
@@ -37,7 +33,9 @@ THUMB(
 TMP	.req	r8
 )
 
+.pushsection .text.__aeabi_uldivmod, "ax"
 ENTRY(__aeabi_uldivmod)
+
 	stmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) lr}
 	@ Test if B == 0
 	orrs	ip, B_0, B_1		@ Z set -> B == 0
@@ -226,7 +224,9 @@ THUMB(	orrpl	A_0, A_0, TMP		)
 	@ Shift A to the right by the appropriate amount.
 	rsb	D_1, D_0, #32
 	mov	Q_0, A_0, lsr D_0
-	orr	Q_0, A_1, lsl D_1
+ ARM(   orr     Q_0, Q_0, A_1, lsl D_1	)
+ THUMB(	lsl	A_1, D_1		)
+ THUMB(	orr	Q_0, A_1		)
 	mov	Q_1, A_1, lsr D_0
 	@ Move C to R
 	mov	R_0, C_0
@@ -243,3 +243,4 @@ L_div_by_0:
 	mov	R_1, #0
 	ldmfd	sp!, {r4, r5, r6, r7, THUMB(TMP,) pc}
 ENDPROC(__aeabi_uldivmod)
+.popsection
diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S
index 49238ed21e..5cc132b7b8 100644
--- a/arch/arm/lib/vectors.S
+++ b/arch/arm/lib/vectors.S
@@ -60,6 +60,16 @@ _start:
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
+#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
+/*
+ * Various SoCs need something special and SoC-specific up front in
+ * order to boot, allow them to set that in their boot0.h file and then
+ * use it here.
+ */
+#include <asm/arch/boot0.h>
+ARM_SOC_BOOT0_HOOK
+#endif
+
 /*
  *************************************************************************
  *
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 9ce775e0da..73a9c74512 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -71,6 +71,11 @@ config TARGET_AT91SAM9X5EK
 	select CPU_ARM926EJS
 	select SUPPORT_SPL
 
+config TARGET_SAMA5D2_PTC
+	bool "SAMA5D2 PTC board"
+	select CPU_V7
+	select SUPPORT_SPL
+
 config TARGET_SAMA5D2_XPLAINED
 	bool "SAMA5D2 Xplained board"
 	select CPU_V7
@@ -138,6 +143,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
 source "board/atmel/at91sam9n12ek/Kconfig"
 source "board/atmel/at91sam9rlek/Kconfig"
 source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sama5d2_ptc/Kconfig"
 source "board/atmel/sama5d2_xplained/Kconfig"
 source "board/atmel/sama5d3_xplained/Kconfig"
 source "board/atmel/sama5d3xek/Kconfig"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 44245234ee..d2abf310a5 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
 obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
 obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
-obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
+obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
 obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
 obj-y += spl.o
diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c
index 81e9f69c94..76fcada788 100644
--- a/arch/arm/mach-at91/armv7/clock.c
+++ b/arch/arm/mach-at91/armv7/clock.c
@@ -162,6 +162,11 @@ int at91_enable_periph_generated_clk(u32 id, u32 clk_source, u32 div)
 	if (div > 0xff)
 		return -EINVAL;
 
+	if (clk_source == GCK_CSS_UPLL_CLK) {
+		if (at91_upll_clk_enable())
+			return -ENODEV;
+	}
+
 	writel(id, &pmc->pcr);
 	regval = readl(&pmc->pcr);
 	regval &= ~AT91_PMC_PCR_GCKCSS;
@@ -231,6 +236,12 @@ u32 at91_get_periph_generated_clk(u32 id)
 	case AT91_PMC_PCR_GCKCSS_PLLA_CLK:
 		freq = gd->arch.plla_rate_hz;
 		break;
+	case AT91_PMC_PCR_GCKCSS_UPLL_CLK:
+		freq = AT91_UTMI_PLL_CLK_FREQ;
+		break;
+	case AT91_PMC_PCR_GCKCSS_MCK_CLK:
+		freq = gd->arch.mck_rate_hz;
+		break;
 	default:
 		printf("Improper GCK clock source selection!\n");
 		freq = 0;
diff --git a/arch/arm/mach-at91/bootparams_atmel.S b/arch/arm/mach-at91/bootparams_atmel.S
new file mode 100644
index 0000000000..568094b99c
--- /dev/null
+++ b/arch/arm/mach-at91/bootparams_atmel.S
@@ -0,0 +1,18 @@
+/*
+ * Atmel SAMA5Dx boot parameter handling
+ *
+ * Copyright (c) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r0, =bootrom_stash
+	str	r4, [r0, #0]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/mach-at91/include/mach/clk.h b/arch/arm/mach-at91/include/mach/clk.h
index 8577c74b47..ca7d7d0695 100644
--- a/arch/arm/mach-at91/include/mach/clk.h
+++ b/arch/arm/mach-at91/include/mach/clk.h
@@ -20,6 +20,8 @@
 #define GCK_CSS_MCK_CLK		4
 #define GCK_CSS_AUDIO_CLK	5
 
+#define AT91_UTMI_PLL_CLK_FREQ	480000000
+
 static inline unsigned long get_cpu_clk_rate(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h
index b040256ba4..b805a2c934 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -32,6 +32,30 @@ struct atmel_sfr {
 #define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
 #define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
 
+/* Bit field in EBICFG */
+#define AT91_SFR_EBICFG_DRIVE0		(0x3 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_LOW		(0x0 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_MEDIUM		(0x2 << 0)
+#define AT91_SFR_EBICFG_DRIVE0_HIGH		(0x3 << 0)
+#define AT91_SFR_EBICFG_PULL0		(0x3 << 2)
+#define AT91_SFR_EBICFG_PULL0_UP		(0x0 << 2)
+#define AT91_SFR_EBICFG_PULL0_NONE		(0x1 << 2)
+#define AT91_SFR_EBICFG_PULL0_DOWN		(0x3 << 2)
+#define AT91_SFR_EBICFG_SCH0		(0x1 << 4)
+#define AT91_SFR_EBICFG_SCH0_OFF		(0x0 << 4)
+#define AT91_SFR_EBICFG_SCH0_ON			(0x1 << 4)
+#define AT91_SFR_EBICFG_DRIVE1		(0x3 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_LOW		(0x0 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_MEDIUM		(0x2 << 8)
+#define AT91_SFR_EBICFG_DRIVE1_HIGH		(0x3 << 8)
+#define AT91_SFR_EBICFG_PULL1		(0x3 << 10)
+#define AT91_SFR_EBICFG_PULL1_UP		(0x0 << 10)
+#define AT91_SFR_EBICFG_PULL1_NONE		(0x1 << 10)
+#define AT91_SFR_EBICFG_PULL1_DOWN		(0x3 << 10)
+#define AT91_SFR_EBICFG_SCH1		(0x1 << 12)
+#define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
+#define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
+
 /* Bit field in AICREDIR */
 #define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
 
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h
index dd5a2a7523..ee841da971 100644
--- a/arch/arm/mach-at91/include/mach/sama5d2.h
+++ b/arch/arm/mach-at91/include/mach/sama5d2.h
@@ -135,7 +135,11 @@
 /*
  * Address Memory Space
  */
+#define ATMEL_BASE_CS0			0x10000000
 #define ATMEL_BASE_DDRCS		0x20000000
+#define ATMEL_BASE_CS1			0x60000000
+#define ATMEL_BASE_CS2			0x70000000
+#define ATMEL_BASE_CS3			0x80000000
 #define ATMEL_BASE_QSPI0_AES_MEM	0x90000000
 #define ATMEL_BASE_QSPI1_AES_MEM	0x98000000
 #define ATMEL_BASE_SDMMC0		0xa0000000
@@ -165,6 +169,7 @@
  */
 #define ATMEL_BASE_PMECC	(ATMEL_BASE_HSMC + 0x70)
 #define ATMEL_BASE_PMERRLOC	(ATMEL_BASE_HSMC + 0x500)
+#define ATMEL_BASE_SMC		(ATMEL_BASE_HSMC + 0x700)
 
 #define ATMEL_BASE_PIOB		(ATMEL_BASE_PIOA + 0x40)
 #define ATMEL_BASE_PIOC		(ATMEL_BASE_PIOB + 0x40)
@@ -225,6 +230,18 @@
 /* No PMECC Galois table in ROM */
 #define NO_GALOIS_TABLE_IN_ROM
 
+/* Boot modes stored by BootROM in r4 */
+#define ATMEL_SAMA5D2_BOOT_FROM_OFF	0
+#define ATMEL_SAMA5D2_BOOT_FROM_MASK	0xf
+#define ATMEL_SAMA5D2_BOOT_FROM_SPI	(0 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_MCI	(1 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_SMC	(2 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_TWI	(3 << 0)
+#define ATMEL_SAMA5D2_BOOT_FROM_QSPI	(4 << 0)
+
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_OFF	4
+#define ATMEL_SAMA5D2_BOOT_DEV_ID_MASK	0xf
+
 #ifndef __ASSEMBLY__
 unsigned int get_chip_id(void);
 unsigned int get_extension_chip_id(void);
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 27a405a42b..c4ed224d03 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -23,6 +23,40 @@ void at91_disable_wdt(void)
 }
 #endif
 
+#if defined(CONFIG_SAMA5D2)
+struct {
+	u32	r4;
+} bootrom_stash __attribute__((section(".data")));
+
+u32 spl_boot_device(void)
+{
+	u32 dev = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_FROM_OFF) &
+		  ATMEL_SAMA5D2_BOOT_FROM_MASK;
+	u32 off = (bootrom_stash.r4 >> ATMEL_SAMA5D2_BOOT_DEV_ID_OFF) &
+		  ATMEL_SAMA5D2_BOOT_DEV_ID_MASK;
+
+#if defined(CONFIG_SYS_USE_MMC)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_MCI) {
+		if (off == 0)
+			return BOOT_DEVICE_MMC1;
+		if (off == 1)
+			return BOOT_DEVICE_MMC2;
+		printf("ERROR: MMC controller %i not present!\n", dev);
+		hang();
+	}
+#endif
+
+#if defined(CONFIG_SYS_USE_SERIALFLASH) || defined(CONFIG_SYS_USE_SPIFLASH)
+	if (dev == ATMEL_SAMA5D2_BOOT_FROM_SPI)
+		return BOOT_DEVICE_SPI;
+#endif
+
+	printf("ERROR: SMC/TWI/QSPI boot device not supported!\n"
+	       "       Boot device %i, controller number %i\n", dev, off);
+
+	return BOOT_DEVICE_NONE;
+}
+#else
 u32 spl_boot_device(void)
 {
 #ifdef CONFIG_SYS_USE_MMC
@@ -34,12 +68,14 @@ u32 spl_boot_device(void)
 #endif
 	return BOOT_DEVICE_NONE;
 }
+#endif
 
 u32 spl_boot_mode(void)
 {
 	switch (spl_boot_device()) {
 #ifdef CONFIG_SYS_USE_MMC
 	case BOOT_DEVICE_MMC1:
+	case BOOT_DEVICE_MMC2:
 		return MMCSD_MODE_FS;
 		break;
 #endif
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index a6a75974d7..c25fcf3f9f 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -1,9 +1,40 @@
 if ARCH_EXYNOS
 
 choice
-	prompt "EXYNOS board select"
+	prompt "EXYNOS architecture type select"
 	optional
 
+config ARCH_EXYNOS4
+	bool "Exynos4 SoC family"
+	select CPU_V7
+	help
+	  Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
+	  are multiple SoCs in this family including Exynos4210, Exynos4412,
+	  and Exynos4212.
+
+config ARCH_EXYNOS5
+	bool "Exynos5 SoC family"
+	select CPU_V7
+	help
+	  Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
+	  Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
+	  in this family including Exynos5250, Exynos5420 and Exynos5800.
+
+config ARCH_EXYNOS7
+	bool "Exynos7 SoC family"
+	select ARM64
+	help
+	  Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
+	  Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
+	  multiple SoCs in this family including Exynos7420.
+
+endchoice
+
+if ARCH_EXYNOS4
+
+choice
+	prompt "EXYNOS4 board select"
+
 config TARGET_SMDKV310
 	select SUPPORT_SPL
 	bool "Exynos4210 SMDKV310 board"
@@ -25,6 +56,14 @@ config TARGET_TRATS2
 config TARGET_ODROID
 	bool "Exynos4412 Odroid board"
 
+endchoice
+endif
+
+if ARCH_EXYNOS5
+
+choice
+	prompt "EXYNOS5 board select"
+
 config TARGET_ODROID_XU3
 	bool "Exynos5422 Odroid board"
 	select OF_CONTROL
@@ -68,6 +107,25 @@ config TARGET_PEACH_PIT
 	select OF_CONTROL
 
 endchoice
+endif
+
+if ARCH_EXYNOS7
+
+choice
+	prompt "EXYNOS7 board select"
+
+config  TARGET_ESPRESSO7420
+	bool "ESPRESSO7420 board"
+	select ARM64
+	select SUPPORT_SPL
+	select OF_CONTROL
+	select SPL_DISABLE_OF_CONTROL
+	select PINCTRL
+	select PINCTRL_EXYNOS7420
+	select CLK_EXYNOS
+
+endchoice
+endif
 
 config SYS_SOC
 	default "exynos"
@@ -81,5 +139,6 @@ source "board/samsung/odroid/Kconfig"
 source "board/samsung/arndale/Kconfig"
 source "board/samsung/smdk5250/Kconfig"
 source "board/samsung/smdk5420/Kconfig"
+source "board/samsung/espresso7420/Kconfig"
 
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8542f896cf..0cc6c3253a 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -5,7 +5,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= clock.o power.o soc.o system.o pinmux.o tzpc.o
+obj-y	+= soc.o
+obj-$(CONFIG_CPU_V7) += clock.o pinmux.o power.o system.o
+obj-$(CONFIG_ARM64)	+= mmu-arm64.o
 
 obj-$(CONFIG_EXYNOS5420)	+= sec_boot.o
 
@@ -13,6 +15,6 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_EXYNOS5)	+= clock_init_exynos5.o
 obj-$(CONFIG_EXYNOS5)	+= dmc_common.o dmc_init_ddr3.o
 obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
-obj-y	+= spl_boot.o
+obj-y	+= spl_boot.o tzpc.o
 obj-y	+= lowlevel_init.o
 endif
diff --git a/arch/arm/mach-exynos/include/mach/cpu.h b/arch/arm/mach-exynos/include/mach/cpu.h
index 14a1692467..1f722df9dd 100644
--- a/arch/arm/mach-exynos/include/mach/cpu.h
+++ b/arch/arm/mach-exynos/include/mach/cpu.h
@@ -270,7 +270,7 @@ IS_EXYNOS_TYPE(exynos5420, 0x5420)
 IS_EXYNOS_TYPE(exynos5422, 0x5422)
 
 #define SAMSUNG_BASE(device, base)				\
-static inline unsigned int __attribute__((no_instrument_function)) \
+static inline unsigned long __attribute__((no_instrument_function)) \
 	samsung_get_base_##device(void) \
 {								\
 	if (cpu_is_exynos4()) {				\
@@ -288,9 +288,7 @@ static inline unsigned int __attribute__((no_instrument_function)) \
 SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
-SAMSUNG_BASE(dp, DP_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
 SAMSUNG_BASE(i2c, I2C_BASE)
 SAMSUNG_BASE(i2s, I2S_BASE)
 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
diff --git a/arch/arm/mach-exynos/include/mach/dp_info.h b/arch/arm/mach-exynos/include/mach/dp_info.h
index 17e8f56d90..1079e1ef1e 100644
--- a/arch/arm/mach-exynos/include/mach/dp_info.h
+++ b/arch/arm/mach-exynos/include/mach/dp_info.h
@@ -61,7 +61,7 @@ struct edp_video_info {
 	unsigned int color_depth;
 };
 
-struct edp_device_info {
+struct exynos_dp_priv {
 	struct edp_disp_info disp_info;
 	struct edp_link_train_info lt_info;
 	struct edp_video_info video_info;
@@ -72,6 +72,7 @@ struct edp_device_info {
 	unsigned char dpcd_rev;
 	/*support enhanced frame cap */
 	unsigned char dpcd_efc;
+	struct exynos_dp *regs;
 };
 
 enum analog_power_block {
@@ -185,7 +186,7 @@ enum {
 
 
 struct exynos_dp_platform_data {
-	struct edp_device_info *edp_dev_info;
+	struct exynos_dp_priv *edp_dev_info;
 };
 
 #ifdef CONFIG_EXYNOS_DP
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 7fc8e61f9c..81363bd947 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1349,7 +1349,7 @@ enum exynos5420_gpio_pin {
 };
 
 struct gpio_info {
-	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned long reg_addr;	/* Address of register for this part */
 	unsigned int max_gpio;	/* Maximum GPIO in this part */
 };
 
diff --git a/arch/arm/mach-exynos/include/mach/mipi_dsim.h b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
index c9e8e067d7..43b5c017fe 100644
--- a/arch/arm/mach-exynos/include/mach/mipi_dsim.h
+++ b/arch/arm/mach-exynos/include/mach/mipi_dsim.h
@@ -320,7 +320,7 @@ struct mipi_dsim_lcd_device {
 	int			reverse_panel;
 
 	struct mipi_dsim_device *master;
-	void			*platform_data;
+	struct exynos_platform_mipi_dsim *platform_data;
 };
 
 /*
@@ -347,9 +347,10 @@ struct mipi_dsim_lcd_driver {
 };
 
 #ifdef CONFIG_EXYNOS_MIPI_DSIM
-int exynos_mipi_dsi_init(void);
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd);
 #else
-static inline int exynos_mipi_dsi_init(void)
+static inline int exynos_mipi_dsi_init(
+			struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	return 0;
 }
@@ -369,7 +370,8 @@ int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
 						*lcd_dev);
 
 void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd);
-void exynos_init_dsim_platform_data(vidinfo_t *vid);
+struct vidinfo;
+void exynos_init_dsim_platform_data(struct vidinfo *vid);
 
 /* panel driver init based on mipi dsi interface */
 void s6e8ax0_init(void);
diff --git a/arch/arm/mach-exynos/include/mach/power.h b/arch/arm/mach-exynos/include/mach/power.h
index 3f97b31aea..88f70d97a9 100644
--- a/arch/arm/mach-exynos/include/mach/power.h
+++ b/arch/arm/mach-exynos/include/mach/power.h
@@ -1717,7 +1717,7 @@ void set_usbdrd_phy_ctrl(unsigned int enable);
 #define POWER_USB_DRD_PHY_CTRL_EN		(1 << 0)
 #define POWER_USB_DRD_PHY_CTRL_DISABLE		(0 << 0)
 
-void set_dp_phy_ctrl(unsigned int enable);
+void exynos_dp_phy_ctrl(unsigned int enable);
 
 #define EXYNOS_DP_PHY_ENABLE		(1 << 0)
 
diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c
index 6c39cb2052..1e090fd63c 100644
--- a/arch/arm/mach-exynos/lowlevel_init.c
+++ b/arch/arm/mach-exynos/lowlevel_init.c
@@ -216,9 +216,12 @@ int do_lowlevel_init(void)
 	if (actions & DO_CLOCKS) {
 		system_clock_init();
 #ifdef CONFIG_DEBUG_UART
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
+    !defined(CONFIG_SPL_BUILD)
 		exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 		debug_uart_init();
 #endif
+#endif
 		mem_ctrl_init(actions & DO_MEM_RESET);
 		tzpc_init();
 	}
diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c
new file mode 100644
index 0000000000..ba6d99d329
--- /dev/null
+++ b/arch/arm/mach-exynos/mmu-arm64.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_EXYNOS7420
+static struct mm_region exynos7420_mem_map[] = {
+	{
+		.base	= 0x10000000UL,
+		.size	= 0x10000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+				PTE_BLOCK_NON_SHARE |
+				PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	}, {
+		.base	= 0x40000000UL,
+		.size	= 0x80000000UL,
+		.attrs	= PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+				PTE_BLOCK_INNER_SHARE,
+	}, {
+		/* List terminator */
+		.base	= 0,
+		.size	= 0,
+		.attrs	= 0,
+	},
+};
+
+struct mm_region *mem_map = exynos7420_mem_map;
+#endif
diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c
index 12eb79cb0c..fec2df9bd9 100644
--- a/arch/arm/mach-exynos/pinmux.c
+++ b/arch/arm/mach-exynos/pinmux.c
@@ -506,6 +506,9 @@ static int exynos5_pinmux_config(int peripheral, int flags)
 		 */
 		gpio_set_pull(EXYNOS5_GPIO_X07, S5P_GPIO_PULL_NONE);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
@@ -548,6 +551,9 @@ static int exynos5420_pinmux_config(int peripheral, int flags)
 	case PERIPH_ID_I2C10:
 		exynos5420_i2c_config(peripheral);
 		break;
+	case PERIPH_ID_PWM0:
+		gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2));
+		break;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
 		return -1;
diff --git a/arch/arm/mach-exynos/power.c b/arch/arm/mach-exynos/power.c
index cd2d6618ac..c923460275 100644
--- a/arch/arm/mach-exynos/power.c
+++ b/arch/arm/mach-exynos/power.c
@@ -147,7 +147,7 @@ static void exynos5_dp_phy_control(unsigned int enable)
 	writel(cfg, &power->dptx_phy_control);
 }
 
-void set_dp_phy_ctrl(unsigned int enable)
+void exynos_dp_phy_ctrl(unsigned int enable)
 {
 	if (cpu_is_exynos5())
 		exynos5_dp_phy_control(enable);
diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c
index 0f116b141a..f9c7468611 100644
--- a/arch/arm/mach-exynos/soc.c
+++ b/arch/arm/mach-exynos/soc.c
@@ -11,7 +11,9 @@
 
 void reset_cpu(ulong addr)
 {
+#ifdef CONFIG_CPU_V7
 	writel(0x1, samsung_get_base_swreset());
+#endif
 }
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -21,3 +23,11 @@ void enable_caches(void)
 	dcache_enable();
 }
 #endif
+
+#ifdef CONFIG_ARM64
+void lowlevel_init(void)
+{
+	armv8_switch_to_el2();
+	armv8_switch_to_el1();
+}
+#endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index ca2a119d39..0f6bf61867 100644
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -74,4 +74,16 @@
 #define K2G_GPIO_DIR_OFFSET		0x0
 #define K2G_GPIO_SETDATA_OFFSET		0x8
 
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8			(KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT		0x0
+#define RSTMUX_LOCK8_MASK		(0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT		0x1
+#define RSTMUX_OMODE8_MASK		(0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET		0x2
+#define RSTMUX_OMODE8_INT		0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET	0x4
+
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
new file mode 100644
index 0000000000..77d3cfec59
--- /dev/null
+++ b/arch/arm/mach-meson/Kconfig
@@ -0,0 +1,31 @@
+if ARCH_MESON
+
+config MESON_GXBB
+	bool "Support Meson GXBaby"
+	select ARM64
+	select DM
+	select DM_SERIAL
+	help
+	  The Amlogic Meson GXBaby (S905) is an ARM SoC with a
+	  quad-core Cortex-A53 CPU and a Mali-450 GPU.
+
+if MESON_GXBB
+
+config TARGET_ODROID_C2
+	bool "ODROID-C2"
+	help
+	  ODROID-C2 is a single board computer based on Meson GXBaby
+	  with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
+	  slot, eMMC, IR receiver and a 40-pin GPIO header.
+
+endif
+
+config SYS_SOC
+	default "meson"
+
+config SYS_MALLOC_F_LEN
+	default 0x1000
+
+source "board/hardkernel/odroid-c2/Kconfig"
+
+endif
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
new file mode 100644
index 0000000000..bf49b8b1e5
--- /dev/null
+++ b/arch/arm/mach-meson/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += board.o sm.o
diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
new file mode 100644
index 0000000000..64fa3c191e
--- /dev/null
+++ b/arch/arm/mach-meson/board.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <asm/armv8/mmu.h>
+#include <asm/unaligned.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	const fdt64_t *val;
+	int offset;
+	int len;
+
+	offset = fdt_path_offset(gd->fdt_blob, "/memory");
+	if (offset < 0)
+		return -EINVAL;
+
+	val = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
+	if (len < sizeof(*val) * 2)
+		return -EINVAL;
+
+	/* Use unaligned access since cache is still disabled */
+	gd->ram_size = get_unaligned_be64(&val[1]);
+
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	/* Reserve first 16 MiB of RAM for firmware */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
+	gd->bd->bi_dram[0].size = gd->ram_size - (16 * 1024 * 1024);
+}
+
+void reset_cpu(ulong addr)
+{
+	psci_system_reset(true);
+}
+
+static struct mm_region gxbb_mem_map[] = {
+	{
+		.base = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.base = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = gxbb_mem_map;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
new file mode 100644
index 0000000000..1b35a220d3
--- /dev/null
+++ b/arch/arm/mach-meson/sm.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Secure monitor calls.
+ */
+
+#include <common.h>
+#include <asm/arch/gxbb.h>
+#include <linux/kernel.h>
+
+#define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
+#define FN_GET_SHARE_MEM_OUTPUT_BASE	0x82000021
+#define FN_EFUSE_READ			0x82000030
+#define FN_EFUSE_WRITE			0x82000031
+
+static void *shmem_input;
+static void *shmem_output;
+
+static void meson_init_shmem(void)
+{
+	struct pt_regs regs;
+
+	if (shmem_input && shmem_output)
+		return;
+
+	regs.regs[0] = FN_GET_SHARE_MEM_INPUT_BASE;
+	smc_call(&regs);
+	shmem_input = (void *)regs.regs[0];
+
+	regs.regs[0] = FN_GET_SHARE_MEM_OUTPUT_BASE;
+	smc_call(&regs);
+	shmem_output = (void *)regs.regs[0];
+
+	debug("Secure Monitor shmem: 0x%p 0x%p\n", shmem_input, shmem_output);
+}
+
+ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size)
+{
+	struct pt_regs regs;
+
+	meson_init_shmem();
+
+	regs.regs[0] = FN_EFUSE_READ;
+	regs.regs[1] = offset;
+	regs.regs[2] = size;
+
+	smc_call(&regs);
+
+	if (regs.regs[0] == 0)
+		return -1;
+
+	memcpy(buffer, shmem_output, min(size, regs.regs[0]));
+
+	return regs.regs[0];
+}
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d3bddb726a..2a8afac5e1 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -41,6 +41,9 @@ config DM_I2C
 config DM_GPIO
 	default y
 
+config BLK
+	default y
+
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
 endif
diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
index fefb568f7a..b3d2113239 100644
--- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c
@@ -7,24 +7,24 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3036.h>
 #include <asm/arch/hardware.h>
 #include <linux/err.h>
 
-int rk3036_reset_request(struct udevice *dev, enum reset_t type)
+int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3036_cru *cru = rockchip_get_cru();
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
 	switch (type) {
-	case RESET_WARM:
+	case SYSRESET_WARM:
 		writel(0xeca8, &cru->cru_glb_srst_snd_value);
 		break;
-	case RESET_COLD:
+	case SYSRESET_COLD:
 		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
 		break;
 	default:
@@ -34,12 +34,12 @@ int rk3036_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops rk3036_reset = {
-	.request	= rk3036_reset_request,
+static struct sysreset_ops rk3036_sysreset = {
+	.request	= rk3036_sysreset_request,
 };
 
-U_BOOT_DRIVER(reset_rk3036) = {
-	.name	= "rk3036_reset",
-	.id	= UCLASS_RESET,
-	.ops	= &rk3036_reset,
+U_BOOT_DRIVER(sysreset_rk3036) = {
+	.name	= "rk3036_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk3036_sysreset,
 };
diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
index bf7540a5d2..0aad1c2160 100644
--- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -7,25 +7,25 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/cru_rk3288.h>
 #include <asm/arch/hardware.h>
 #include <linux/err.h>
 
-int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	struct rk3288_cru *cru = rockchip_get_cru();
 
 	if (IS_ERR(cru))
 		return PTR_ERR(cru);
 	switch (type) {
-	case RESET_WARM:
+	case SYSRESET_WARM:
 		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xeca8, &cru->cru_glb_srst_snd_value);
 		break;
-	case RESET_COLD:
+	case SYSRESET_COLD:
 		rk_clrreg(&cru->cru_mode_con, 0xffff);
 		writel(0xfdb9, &cru->cru_glb_srst_fst_value);
 		break;
@@ -36,12 +36,12 @@ int rk3288_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops rk3288_reset = {
-	.request	= rk3288_reset_request,
+static struct sysreset_ops rk3288_sysreset = {
+	.request	= rk3288_sysreset_request,
 };
 
-U_BOOT_DRIVER(reset_rk3288) = {
-	.name	= "rk3288_reset",
-	.id	= UCLASS_RESET,
-	.ops	= &rk3288_reset,
+U_BOOT_DRIVER(sysreset_rk3288) = {
+	.name	= "rk3288_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &rk3288_sysreset,
 };
diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c
index 2627eec181..a6cabfb8b0 100644
--- a/arch/arm/mach-snapdragon/reset.c
+++ b/arch/arm/mach-snapdragon/reset.c
@@ -9,12 +9,12 @@
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static int msm_reset_request(struct udevice *dev, enum reset_t type)
+static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
 	phys_addr_t addr = dev_get_addr(dev);
 	if (!addr)
@@ -23,18 +23,18 @@ static int msm_reset_request(struct udevice *dev, enum reset_t type)
 	return -EINPROGRESS;
 }
 
-static struct reset_ops msm_reset_ops = {
-	.request	= msm_reset_request,
+static struct sysreset_ops msm_sysreset_ops = {
+	.request	= msm_sysreset_request,
 };
 
-static const struct udevice_id msm_reset_ids[] = {
+static const struct udevice_id msm_sysreset_ids[] = {
 	{ .compatible = "qcom,pshold" },
 	{ }
 };
 
 U_BOOT_DRIVER(msm_reset) = {
-	.name		= "msm_reset",
-	.id		= UCLASS_RESET,
-	.of_match	= msm_reset_ids,
-	.ops		= &msm_reset_ops,
+	.name		= "msm_sysreset",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= msm_sysreset_ids,
+	.ops		= &msm_sysreset_ops,
 };
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index dea4ce569f..1484607754 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -35,6 +35,10 @@ config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
+	bool "samtec VIN|ING FPGA (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -53,12 +57,14 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
@@ -73,5 +79,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
 
 endif
diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
index ad3d6c4918..25367cf380 100644
--- a/arch/arm/mach-sunxi/Makefile
+++ b/arch/arm/mach-sunxi/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 obj-$(CONFIG_AXP152_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP209_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP221_POWER)	+= pmic_bus.o
+obj-$(CONFIG_AXP809_POWER)	+= pmic_bus.o
 obj-$(CONFIG_AXP818_POWER)	+= pmic_bus.o
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 20149dabc8..bd15b9bfb0 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -247,6 +247,15 @@ u32 spl_boot_device(void)
 	return -1;		/* Never reached */
 }
 
+/*
+ * Properly announce BOOT_DEVICE_BOARD as "FEL".
+ * Overrides weak function from common/spl/spl.c
+ */
+void spl_board_announce_boot_device(void)
+{
+	printf("FEL");
+}
+
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 u32 spl_boot_mode(void)
 {
diff --git a/arch/arm/mach-sunxi/pmic_bus.c b/arch/arm/mach-sunxi/pmic_bus.c
index 5b81a8d8e1..7c57f02792 100644
--- a/arch/arm/mach-sunxi/pmic_bus.c
+++ b/arch/arm/mach-sunxi/pmic_bus.c
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else
@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ba6983f3df..b18a12e342 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -22,6 +22,7 @@ config TEGRA_ARMV7_COMMON
 	select SPL
 	select SUPPORT_SPL
 	select TEGRA_COMMON
+	select TEGRA_GPIO
 
 config TEGRA_ARMV8_COMMON
 	bool "Tegra 64-bit common options"
@@ -50,6 +51,12 @@ config TEGRA124
 
 config TEGRA210
 	bool "Tegra210 family"
+	select TEGRA_GPIO
+	select TEGRA_ARMV8_COMMON
+
+config TEGRA186
+	bool "Tegra186 family"
+	select TEGRA186_GPIO
 	select TEGRA_ARMV8_COMMON
 
 endchoice
@@ -75,5 +82,6 @@ source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"
 source "arch/arm/mach-tegra/tegra124/Kconfig"
 source "arch/arm/mach-tegra/tegra210/Kconfig"
+source "arch/arm/mach-tegra/tegra186/Kconfig"
 
 endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2dbc6999c..12ee1cd749 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -7,6 +7,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifndef CONFIG_TEGRA186
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 obj-y += cpu.o
@@ -30,9 +31,11 @@ obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ARMV7_PSCI) += psci.o
 endif
+endif
 
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_TEGRA30) += tegra30/
 obj-$(CONFIG_TEGRA114) += tegra114/
 obj-$(CONFIG_TEGRA124) += tegra124/
+obj-$(CONFIG_TEGRA186) += tegra186/
 obj-$(CONFIG_TEGRA210) += tegra210/
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
new file mode 100644
index 0000000000..f4b6152a79
--- /dev/null
+++ b/arch/arm/mach-tegra/board186.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = (1.5 * 1024 * 1024 * 1024);
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+void pad_init_mmc(struct mmc_host *host)
+{
+}
+
+int board_mmc_init(bd_t *bd)
+{
+	tegra_mmc_init();
+
+	return 0;
+}
+
+int ft_system_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
new file mode 100644
index 0000000000..97cf23f31f
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -0,0 +1,25 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TEGRA186
+
+choice
+	prompt "Tegra186 board select"
+
+config TARGET_P2771_0000
+	bool "NVIDIA Tegra186 P2771-0000 board"
+	help
+	  P2771-0000 is a P3310 CPU board married to a P2597 I/O board. The
+	  combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+	  micro-B port, Ethernet, USB3 host port, SATA, PCIe, and two GPIO
+	  expansion headers.
+
+endchoice
+
+config SYS_SOC
+	default "tegra186"
+
+source "board/nvidia/p2771-0000/Kconfig"
+
+endif
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
new file mode 100644
index 0000000000..ce4610d8f8
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -0,0 +1,8 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += ../arm64-mmu.o
+obj-y += ../board186.o
+obj-y += ../lowlevel_init.o
+obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 87d1675ffc..ae763ad94e 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B
 	bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC"
 	select CPU_V7
 
+config ARCH_UNIPHIER_LD11
+	bool "UniPhier PH1-LD11 SoC"
+	select ARM64
+	select SPL_SEPARATE_BSS
+
 config ARCH_UNIPHIER_LD20
 	bool "UniPhier PH1-LD20 SoC"
 	select ARM64
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 64412e0ecc..5971ad256b 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void)
 	rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
 
 	writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
-	readq(rom_boot_rsv0);	/* relax */
 
 	unmap_sysmem(rom_boot_rsv0);
 
 	uniphier_smp_setup();
 
-	asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+	asm("dsb	ishst\n" /* Ensure the write to ROM_RSV0 is visible */
+	    "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
 }
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 2a7ae1b529..f853701f44 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -62,6 +62,13 @@ int board_early_init_f(void)
 		uniphier_pxs2_clk_init();
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		uniphier_ld20_pin_init();
+		led_puts("U1");
+		uniphier_ld11_clk_init();
+		break;
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_pin_init();
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index 845f047b02..a45412677a 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -39,6 +39,9 @@ static int uniphier_set_fdt_file(void)
 	int buf_len = 256;
 	int ret;
 
+	if (getenv("fdt_file"))
+		return 0;	/* do nothing if it is already set */
+
 	ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat);
 	if (ret)
 		return -EINVAL;
@@ -56,9 +59,7 @@ static int uniphier_set_fdt_file(void)
 
 	strncat(dtb_name, ".dtb", buf_len);
 
-	setenv("fdt_file", dtb_name);
-
-	return 0;
+	return setenv("fdt_file", dtb_name);
 }
 
 int board_late_init(void)
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f0547c336e..ed308f3ecb 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -165,6 +165,23 @@ static const struct uniphier_board_data uniphier_ld6b_data = {
 };
 #endif
 
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+static const struct uniphier_board_data uniphier_ld11_data = {
+	.dram_freq = 1600,
+	.dram_nr_ch = 2,
+	.dram_ch[0] = {
+		.base = 0x80000000,
+		.size = 0x20000000,
+		.width = 16,
+	},
+	.dram_ch[1] = {
+		.base = 0xa0000000,
+		.size = 0x20000000,
+		.width = 16,
+	},
+};
+#endif
+
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 static const struct uniphier_board_data uniphier_ld20_data = {
 	.dram_freq = 1866,
@@ -216,6 +233,9 @@ static const struct uniphier_board_id uniphier_boards[] = {
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{ "socionext,ph1-ld6b", &uniphier_ld6b_data, },
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	{ "socionext,ph1-ld11", &uniphier_ld11_data, },
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	{ "socionext,ph1-ld20", &uniphier_ld20_data, },
 #endif
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
index 6cd096ec5f..a8980210b1 100644
--- a/arch/arm/mach-uniphier/boot-mode/Makefile
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -11,6 +11,11 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-mode-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= boot-mode-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= boot-mode-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= boot-mode-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= boot-mode-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= boot-mode-ld20.o
 
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_BOARD_LOAD_IMAGE)	+= spl_board.o
+else
 obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
+endif
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
index b092c1bde8..24255a0f50 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c
@@ -9,6 +9,7 @@
 #include <linux/io.h>
 
 #include "../sg-regs.h"
+#include "../soc-info.h"
 #include "boot-device.h"
 
 static struct boot_device_info boot_device_table[] = {
@@ -43,7 +44,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"},
 	{BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"},
 	{BOOT_DEVICE_MMC1, "eMMC (Legacy,         4bit, 1.8V, Training Off)"},
-	{BOOT_DEVICE_NOR,  "NOR Boot (XECS1)"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS1)"},
 };
 
 static int get_boot_mode_sel(void)
@@ -54,8 +55,24 @@ static int get_boot_mode_sel(void)
 u32 uniphier_ld20_boot_device(void)
 {
 	int boot_mode;
+	u32 usb_boot_mask;
 
-	if (~readl(SG_PINMON0) & 0x00000780)
+	switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		usb_boot_mask = 0x00000080;
+		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD20:
+		usb_boot_mask = 0x00000780;
+		break;
+#endif
+	default:
+		BUG();
+	}
+
+	if (~readl(SG_PINMON0) & usb_boot_mask)
 		return BOOT_DEVICE_USB;
 
 	boot_mode = get_boot_mode_sel();
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
index 0597618aa4..b066ed9c4b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld4.c
@@ -36,14 +36,14 @@ struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (3.3V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NOR,  "NOR Boot"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 };
 
 static int get_boot_mode_sel(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
index f9726f1f66..450c43bba5 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pro5.c
@@ -37,7 +37,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128MB, Addr 5)"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
index 4b06f74712..20ff7731d5 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-pxs2.c
@@ -32,17 +32,17 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 4)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+	{BOOT_DEVICE_MMC1, "eMMC (1.8V)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 4)"},
 	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 4)"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS1"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS1"},
-	{BOOT_DEVICE_SPI,  "SPI 4Byte CS0"},
-	{BOOT_DEVICE_SPI,  "SPI 3Byte CS0"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS1)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS1)"},
+	{BOOT_DEVICE_SPI,  "SPI  (4Byte CS0)"},
+	{BOOT_DEVICE_SPI,  "SPI  (3Byte CS0)"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 };
 
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
index a4a3c47bfa..ddf8259c2c 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-sld3.c
@@ -12,7 +12,7 @@
 #include "boot-device.h"
 
 static struct boot_device_info boot_device_table[] = {
-	{BOOT_DEVICE_NOR,  "NOR boot"},
+	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
 	{BOOT_DEVICE_NONE, "External Master"},
 	{BOOT_DEVICE_NONE, "Reserved"},
 	{BOOT_DEVICE_NONE, "Reserved"},
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index b180f44ce8..d34b9af9a1 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -39,7 +39,8 @@ u32 spl_boot_device_raw(void)
 	case SOC_UNIPHIER_LD6B:
 		return uniphier_pxs2_boot_device();
 #endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
 	case SOC_UNIPHIER_LD20:
 		return uniphier_ld20_boot_device();
 #endif
@@ -50,11 +51,30 @@ u32 spl_boot_device_raw(void)
 
 u32 spl_boot_device(void)
 {
-	u32 ret;
+	u32 mode;
 
-	ret = spl_boot_device_raw();
+	mode = spl_boot_device_raw();
 
-	return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret;
+	switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B)
+	case SOC_UNIPHIER_PXS2:
+	case SOC_UNIPHIER_LD6B:
+		if (mode == BOOT_DEVICE_USB)
+			mode = BOOT_DEVICE_NOR;
+		break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
+	case SOC_UNIPHIER_LD20:
+		if (mode == BOOT_DEVICE_MMC1 || mode == BOOT_DEVICE_USB)
+			mode = BOOT_DEVICE_BOARD;
+		break;
+#endif
+	default:
+		break;
+	}
+
+	return mode;
 }
 
 u32 spl_boot_mode(void)
diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
index fa97dc5856..a8ee382248 100644
--- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c
@@ -39,7 +39,8 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		uniphier_pxs2_boot_mode_show();
 		break;
 #endif
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20)
+	case SOC_UNIPHIER_LD11:
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_boot_mode_show();
 		break;
diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c
new file mode 100644
index 0000000000..86292b6f59
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c
@@ -0,0 +1,128 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <asm/processor.h>
+
+#include "../soc-info.h"
+
+void spl_board_announce_boot_device(void)
+{
+	printf("eMMC");
+}
+
+struct uniphier_romfunc_table {
+	void *mmc_send_cmd;
+	void *mmc_card_blockaddr;
+	void *mmc_switch_part;
+	void *mmc_load_image;
+};
+
+static const struct uniphier_romfunc_table uniphier_ld11_romfunc_table = {
+	.mmc_send_cmd = (void *)0x20d8,
+	.mmc_card_blockaddr = (void *)0x1b68,
+	.mmc_switch_part = (void *)0x1c38,
+	.mmc_load_image = (void *)0x2e48,
+};
+
+static const struct uniphier_romfunc_table uniphier_ld20_romfunc_table = {
+	.mmc_send_cmd = (void *)0x2130,
+	.mmc_card_blockaddr = (void *)0x1ba0,
+	.mmc_switch_part = (void *)0x1c70,
+	.mmc_load_image = (void *)0x2ef0,
+};
+
+int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32),
+				 int (**card_blockaddr)(u32),
+				 int (**switch_part)(int),
+				 int (**load_image)(u32, uintptr_t, u32))
+{
+	const struct uniphier_romfunc_table *table;
+
+	switch (uniphier_get_soc_type()) {
+	case SOC_UNIPHIER_LD11:
+		table = &uniphier_ld11_romfunc_table;
+		break;
+	case SOC_UNIPHIER_LD20:
+		table = &uniphier_ld20_romfunc_table;
+		break;
+	default:
+		printf("unsupported SoC\n");
+		return -EINVAL;
+	}
+
+	*send_cmd = table->mmc_send_cmd;
+	*card_blockaddr = table->mmc_card_blockaddr;
+	*switch_part = table->mmc_switch_part;
+	*load_image = table->mmc_load_image;
+
+	return 0;
+}
+
+int spl_board_load_image(void)
+{
+	int (*send_cmd)(u32 cmd, u32 arg);
+	int (*card_blockaddr)(u32 rca);
+	int (*switch_part)(int part);
+	int (*load_image)(u32 dev_addr, uintptr_t load_addr, u32 block_cnt);
+	u32 dev_addr = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
+	const u32 rca = 0x1000; /* RCA assigned by Boot ROM */
+	int ret;
+
+	ret = uniphier_rom_get_mmc_funcptr(&send_cmd, &card_blockaddr,
+					   &switch_part, &load_image);
+	if (ret)
+		return ret;
+
+	/*
+	 * deselect card before SEND_CSD command.
+	 * Do not check the return code.  It fails, but it is OK.
+	 */
+	(*send_cmd)(0x071a0000, 0); /* CMD7 (arg=0) */
+
+	/* reset CMD Line */
+	writeb(0x6, 0x5a00022f);
+	while (readb(0x5a00022f))
+		cpu_relax();
+
+	ret = (*card_blockaddr)(rca);
+	if (ret) {
+		debug("card is block addressing\n");
+	} else {
+		debug("card is byte addressing\n");
+		dev_addr *= 512;
+	}
+
+	ret = (*send_cmd)(0x071a0000, rca << 16); /* CMD7: select card again */
+	if (ret)
+		printf("failed to select card\n");
+
+	ret = (*switch_part)(1); /* Switch to Boot Partition 1 */
+	if (ret)
+		printf("failed to switch partition\n");
+
+	ret = (*load_image)(dev_addr, CONFIG_SYS_TEXT_BASE, 1);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE);
+	if (ret)
+		return ret;
+
+	ret = (*load_image)(dev_addr, spl_image.load_addr,
+			    spl_image.size / 512);
+	if (ret) {
+		printf("failed to load image\n");
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 93e9d91e47..1428e0c9cc 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= clk-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= clk-ld20.o
diff --git a/arch/arm/mach-uniphier/clk/clk-ld11.c b/arch/arm/mach-uniphier/clk/clk-ld11.c
new file mode 100644
index 0000000000..92a07338a8
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ld11.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sg-regs.h"
+
+void uniphier_ld11_clk_init(void)
+{
+	if (readl(SG_PINMON0) & BIT(27)) {
+		/* if booted without stand-by MPU */
+
+		writel(1, SG_ETPHYPSHUT);
+		writel(1, SG_ETPHYCNT);
+
+		udelay(1); /* wait for regulator level 1.1V -> 2.5V */
+
+		writel(3, SG_ETPHYCNT);
+		writel(3, SG_ETPHYPSHUT);
+		writel(7, SG_ETPHYCNT);
+	}
+}
diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c
index f9646c0205..6ad4c76dc4 100644
--- a/arch/arm/mach-uniphier/cpu_info.c
+++ b/arch/arm/mach-uniphier/cpu_info.c
@@ -45,7 +45,7 @@ int print_cpuinfo(void)
 		puts("PH1-LD6b (MN2WS0320)");
 		break;
 	case 0x31:
-		puts("PH1-LD11 ()");
+		puts("PH1-LD11 (SC1405AP1)");
 		break;
 	case 0x32:
 		puts("PH1-LD20 (SC1401AJ1)");
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 41aa53b6b5..5b9d892511 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= umc-sld8.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= umc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= umc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= umc-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= umc-ld20.o
 
 else
diff --git a/arch/arm/mach-uniphier/dram/umc-ld11.c b/arch/arm/mach-uniphier/dram/umc-ld11.c
new file mode 100644
index 0000000000..1be18a867c
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/umc-ld11.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <asm/processor.h>
+
+#include "../init.h"
+#include "umc64-regs.h"
+
+#define CONFIG_DDR_FREQ		1866
+
+#define DRAM_CH_NR	2
+
+enum dram_freq {
+	DRAM_FREQ_1600M,
+	DRAM_FREQ_NR,
+};
+
+enum dram_size {
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+/* umc */
+static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
+static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
+static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
+static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
+static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+
+static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
+		       unsigned long size, int ch)
+{
+	writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
+	writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
+	writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
+	writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
+	writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
+	writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
+
+	writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
+	writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+
+	writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
+	writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+
+	writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
+	writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+
+	writel(0x00000003, dc_base + UMC_ACSSETA);
+	writel(0x00000103, dc_base + UMC_FLOWCTLG);
+	writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
+	writel(0x02020200, dc_base + UMC_SPCSETB);
+	writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
+	writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
+
+	return 0;
+}
+
+static int umc_ch_init(void __iomem *umc_ch_base,
+		       enum dram_freq freq, unsigned long size, int ch)
+{
+	void __iomem *dc_base  = umc_ch_base;
+
+	return umc_dc_init(dc_base, freq, size, ch);
+}
+
+static void um_init(void __iomem *um_base)
+{
+	writel(0x00000001, um_base + UMC_SIORST);
+	writel(0x00000001, um_base + UMC_VO0RST);
+	writel(0x00000001, um_base + UMC_VPERST);
+	writel(0x00000001, um_base + UMC_RGLRST);
+	writel(0x00000001, um_base + UMC_A2DRST);
+	writel(0x00000001, um_base + UMC_DMDRST);
+}
+
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
+{
+	void __iomem *um_base = (void __iomem *)0x5B800000;
+	void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+	enum dram_freq freq;
+	int ch, ret;
+
+	switch (bd->dram_freq) {
+	case 1600:
+		freq = DRAM_FREQ_1600M;
+		break;
+	default:
+		pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
+		return -EINVAL;
+	}
+
+	for (ch = 0; ch < bd->dram_nr_ch; ch++) {
+		unsigned long size = bd->dram_ch[ch].size;
+		unsigned int width = bd->dram_ch[ch].width;
+
+		ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
+		if (ret) {
+			pr_err("failed to initialize UMC ch%d\n", ch);
+			return ret;
+		}
+
+		umc_ch_base += 0x00200000;
+	}
+
+	um_init(um_base);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c
index 4614dac5d2..186a398a60 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20.c
+++ b/arch/arm/mach-uniphier/dram/umc-ld20.c
@@ -15,7 +15,7 @@
 
 #include "../init.h"
 #include "ddrphy-ld20-regs.h"
-#include "umc-ld20-regs.h"
+#include "umc64-regs.h"
 
 #define DRAM_CH_NR	3
 
@@ -200,9 +200,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
 	writel(umc_dataset[freq], dc_base + UMC_DATASET);
 
 	writel(0x00400020, dc_base + UMC_DCCGCTL);
-	writel(0x00000003, dc_base + UMC_ACSCTLA);
+	writel(0x00000003, dc_base + UMC_ACSSETA);
 	writel(0x00000103, dc_base + UMC_FLOWCTLG);
-	writel(0x00010200, dc_base + UMC_ACSSETA);
+	writel(0x00010200, dc_base + UMC_ACSSETB);
 
 	writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA);
 	writel(0x00004444, dc_base + UMC_FLOWCTLC);
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc64-regs.h
index 46e513cd09..860d04e381 100644
--- a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h
+++ b/arch/arm/mach-uniphier/dram/umc64-regs.h
@@ -18,13 +18,15 @@
 #define UMC_INITSET		0x00000040
 #define UMC_INITSTAT		0x00000044
 #define UMC_CMDCTLE		0x00000050
+#define UMC_CMDCTLF		0x00000054
+#define UMC_CMDCTLG		0x00000058
 #define UMC_SPCSETB		0x00000084
 #define   UMC_SPCSETB_AREFMD_MASK	(0x3)	/* Auto Refresh Mode */
 #define   UMC_SPCSETB_AREFMD_ARB	(0x0)	/* control by arbitor */
 #define   UMC_SPCSETB_AREFMD_CONT	(0x1)	/* control by DRAMCONT */
 #define   UMC_SPCSETB_AREFMD_REG	(0x2)	/* control by register */
-#define UMC_ACSCTLA		0x000000C0
-#define UMC_ACSSETA		0x000000C4
+#define UMC_ACSSETA		0x000000C0
+#define UMC_ACSSETB		0x000000C4
 #define UMC_MEMCONF0A		0x00000200
 #define UMC_MEMCONF0B		0x00000204
 #define UMC_MEMCONFCH		0x00000240
@@ -32,6 +34,7 @@
 #define UMC_FLOWCTLA		0x00000400
 #define UMC_FLOWCTLB		0x00000404
 #define UMC_FLOWCTLC		0x00000408
+#define UMC_ACFETCHCTRL		0x00000460
 #define UMC_FLOWCTLG		0x00000508
 #define UMC_RDATACTL_D0		0x00000600
 #define UMC_WDATACTL_D0		0x00000604
@@ -42,6 +45,7 @@
 #define UMC_ODTCTL_D1		0x0000061C
 #define UMC_RESPCTL		0x00000624
 #define UMC_DIRECTBUSCTRLA	0x00000680
+#define UMC_DEBUGC		0x00000718
 #define UMC_DCCGCTL		0x00000720
 #define UMC_DICGCTLA		0x00000724
 #define UMC_DICGCTLB		0x00000728
@@ -70,4 +74,12 @@
 #define UMC_MBUS9		0x00002478
 #define UMC_MBUS10		0x000024F8
 
+/* UMC1 register */
+#define UMC_SIORST		0x00000728
+#define UMC_VO0RST		0x0000073c
+#define UMC_VPERST		0x00000744
+#define UMC_RGLRST		0x00000750
+#define UMC_A2DRST		0x00000764
+#define UMC_DMDRST		0x00000770
+
 #endif /* UMC_LD20_REGS_H */
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
index 9242b416c5..755a3618b5 100644
--- a/arch/arm/mach-uniphier/early-clk/Makefile
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= early-clk-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= early-clk-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= early-clk-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= early-clk-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-clk-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-clk-ld20.o
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
new file mode 100644
index 0000000000..c94d83c4ed
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/io.h>
+
+#include "../init.h"
+#include "../sc64-regs.h"
+
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd)
+{
+	u32 tmp;
+
+	/* deassert reset */
+	tmp = readl(SC_RSTCTRL7);
+	tmp |= SC_RSTCTRL7_UMC31 | SC_RSTCTRL7_UMC30;
+	writel(tmp, SC_RSTCTRL7);
+
+	/* provide clocks */
+	tmp = readl(SC_CLKCTRL4);
+	tmp |= SC_CLKCTRL4_PERI;
+	writel(tmp, SC_CLKCTRL4);
+
+	tmp = readl(SC_CLKCTRL7);
+	tmp |= SC_CLKCTRL7_UMC31 | SC_CLKCTRL7_UMC30;
+	writel(tmp, SC_CLKCTRL7);
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
index a1039025ca..7177a8cf8f 100644
--- a/arch/arm/mach-uniphier/early-pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -3,4 +3,5 @@
 #
 
 obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= early-pinctrl-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= early-pinctrl-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= early-pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index ab0a68d83d..cba0bc9d37 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_init(const struct uniphier_board_data *bd);
 
 #if defined(CONFIG_MICRO_SUPPORT_CARD)
@@ -81,6 +82,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
 int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
 
 int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@@ -91,6 +93,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
+int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);
 
 void uniphier_sld3_pin_init(void);
 void uniphier_ld4_pin_init(void);
@@ -105,6 +108,7 @@ void uniphier_ld4_clk_init(void);
 void uniphier_pro4_clk_init(void);
 void uniphier_pro5_clk_init(void);
 void uniphier_pxs2_clk_init(void);
+void uniphier_ld11_clk_init(void);
 void uniphier_ld20_clk_init(void);
 
 void cci500_init(int nr_slaves);
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
index b58e6c885a..dcaa4451ad 100644
--- a/arch/arm/mach-uniphier/init/Makefile
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= init-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= init-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= init-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= init-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= init-ld11.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= init-ld20.o
diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c
new file mode 100644
index 0000000000..de2dc62b5d
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ld11.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+#include "../init.h"
+#include "../micro-support-card.h"
+
+int uniphier_ld11_init(const struct uniphier_board_data *bd)
+{
+	uniphier_sbc_init_savepin(bd);
+	uniphier_pxs2_sbc_init(bd);
+	uniphier_ld20_early_pin_init(bd);
+
+	support_card_reset();
+
+	support_card_init();
+
+	led_puts("L0");
+
+	memconf_init(bd);
+
+	led_puts("L1");
+
+	uniphier_ld11_early_clk_init(bd);
+
+	led_puts("L2");
+
+	led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+	preloader_console_init();
+#endif
+
+	led_puts("L4");
+
+	{
+		int res;
+
+		res = uniphier_ld11_umc_init(bd);
+		if (res < 0) {
+			while (1)
+				;
+		}
+	}
+
+	led_puts("L5");
+
+	dcache_disable();
+
+	led_puts("L6");
+
+	return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c
index 660ad457dc..7f66053e1f 100644
--- a/arch/arm/mach-uniphier/init/init-ld20.c
+++ b/arch/arm/mach-uniphier/init/init-ld20.c
@@ -51,5 +51,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd)
 
 	led_puts("L5");
 
+	dcache_disable();
+
 	return 0;
 }
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
index 15a53ce068..77e5b99047 100644
--- a/arch/arm/mach-uniphier/init/init.c
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -55,6 +55,11 @@ void spl_board_init(void)
 		uniphier_pxs2_init(param);
 		break;
 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+	case SOC_UNIPHIER_LD11:
+		uniphier_ld11_init(param);
+		break;
+#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
 	case SOC_UNIPHIER_LD20:
 		uniphier_ld20_init(param);
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
index b579cb06e7..7f4d9f76a8 100644
--- a/arch/arm/mach-uniphier/pinctrl/Makefile
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= pinctrl-sld8.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= pinctrl-pro5.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= pinctrl-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= pinctrl-ld6b.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= pinctrl-ld20.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= pinctrl-ld20.o
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
index 38da253975..ec3c22c28d 100644
--- a/arch/arm/mach-uniphier/sbc/Makefile
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -9,4 +9,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= sbc-savepin.o sbc-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= sbc-savepin.o
 obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= sbc-savepin.o sbc-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD11)	+= sbc-savepin.o sbc-pxs2.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD20)	+= sbc-savepin.o sbc-pxs2.o
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h
index 1d71ce87ae..a179d615be 100644
--- a/arch/arm/mach-uniphier/sg-regs.h
+++ b/arch/arm/mach-uniphier/sg-regs.h
@@ -59,6 +59,9 @@
 
 #define SG_MEMCONF_SPARSEMEM		(0x1 << 4)
 
+#define SG_ETPHYPSHUT			(SG_CTRL_BASE | 0x554)
+#define SG_ETPHYCNT			(SG_CTRL_BASE | 0x550)
+
 /* Pin Control */
 #define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)
 
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index d396a13b6f..db3c579293 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,41 +1,5 @@
 if ARCH_ZYNQ
 
-config ZYNQ_CUSTOM_INIT
-	bool "Use custom ps7_init provided by Xilinx tool"
-	help
-	  U-Boot includes ps7_init_gpl.[ch] for some Zynq board variants.
-	  If you want to override them with customized ones
-	  or ps7_init code for your board is missing, please say Y here
-	  and add ones into board/xilinx/zynq/custom_hw_platform/ directory.
-
-choice
-	prompt "Xilinx Zynq board select"
-	default TARGET_ZYNQ_ZC702
-
-config TARGET_ZYNQ_ZED
-	bool "Zynq ZedBoard"
-
-config TARGET_ZYNQ_MICROZED
-	bool "Zynq MicroZed"
-
-config TARGET_ZYNQ_PICOZED
-	bool "Zynq PicoZed"
-
-config TARGET_ZYNQ_ZC702
-	bool "Zynq ZC702 Board"
-
-config TARGET_ZYNQ_ZC706
-	bool "Zynq ZC706 Board"
-
-config TARGET_ZYNQ_ZC770
-	bool "Zynq ZC770 Board"
-	select ZYNQ_CUSTOM_INIT
-
-config TARGET_ZYNQ_ZYBO
-	bool "Zynq Zybo Board"
-
-endchoice
-
 config SYS_BOARD
 	default "zynq"
 
@@ -46,11 +10,11 @@ config SYS_SOC
 	default "zynq"
 
 config SYS_CONFIG_NAME
-	default "zynq_zed" if TARGET_ZYNQ_ZED
-	default "zynq_microzed" if TARGET_ZYNQ_MICROZED
-	default "zynq_picozed" if TARGET_ZYNQ_PICOZED
-	default "zynq_zc70x" if TARGET_ZYNQ_ZC702 || TARGET_ZYNQ_ZC706
-	default "zynq_zc770" if TARGET_ZYNQ_ZC770
-	default "zynq_zybo" if TARGET_ZYNQ_ZYBO
+	string "Board configuration name"
+	default "zynq-common"
+	help
+	  This option contains information about board configuration name.
+	  Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+	  will be used for board configuration.
 
 endif
diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c
index 723019d252..6c5415ac8f 100644
--- a/arch/arm/mach-zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -90,3 +90,28 @@ __weak void ps7_init(void)
 	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
 	 */
 }
+
+__weak int ps7_post_config(void)
+{
+	/*
+	 * This function is overridden by the one in
+	 * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists.
+	 */
+	return 0;
+}
+
+void spl_board_prepare_for_boot(void)
+{
+	ps7_post_config();
+	debug("SPL bye\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 8b047ec7c8..7d48e9a46b 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -6,28 +6,8 @@
 #ifndef __ASM_U_BOOT_H__
 #define __ASM_U_BOOT_H__ 1
 
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-typedef struct bd_info {
-	unsigned char		bi_phy_id[4];
-	unsigned long		bi_board_number;
-	void			*bi_boot_params;
-	struct {
-		unsigned long	start;
-		unsigned long	size;
-	}			bi_dram[CONFIG_NR_DRAM_BANKS];
-	unsigned long		bi_flashstart;
-	unsigned long		bi_flashsize;
-	unsigned long		bi_flashoffset;
-} bd_t;
-
-#define bi_memstart bi_dram[0].start
-#define bi_memsize bi_dram[0].size
-
-#endif
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_AVR32
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 911c0d398c..82038443c9 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -14,47 +14,8 @@
 #ifndef __U_BOOT_H__
 #define __U_BOOT_H__
 
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
-	unsigned long bi_memstart;	/* start of DRAM memory */
-	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
-	unsigned long bi_flashstart;	/* start of FLASH memory */
-	unsigned long bi_flashsize;	/* size  of FLASH memory */
-	unsigned long bi_flashoffset;	/* reserved area for startup monitor */
-	unsigned long bi_sramstart;	/* start of SRAM memory */
-	unsigned long bi_sramsize;	/* size  of SRAM memory */
-	unsigned long bi_mbar_base;	/* base of internal registers */
-	unsigned long bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-	unsigned long bi_boot_params;	/* where this board expects params */
-	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
-#ifdef CONFIG_PCI
-	unsigned long bi_pcifreq;	/* pci Freq in MHz */
-#endif
-#ifdef CONFIG_EXTRA_CLOCK
-	unsigned long bi_inpfreq;	/* input Freq in MHz */
-	unsigned long bi_vcofreq;	/* vco Freq in MHz */
-	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
-#endif
-} bd_t;
-
-#endif				/* __ASSEMBLY__ */
-
-#endif				/* !CONFIG_SYS_GENERIC_BOARD */
-
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_M68K
diff --git a/arch/microblaze/include/asm/asm.h b/arch/microblaze/include/asm/asm.h
index 11f3dd0f0e..94f0562759 100644
--- a/arch/microblaze/include/asm/asm.h
+++ b/arch/microblaze/include/asm/asm.h
@@ -50,7 +50,7 @@
 #define NOP	__asm__ __volatile__ ("nop");
 
 /* use machine status registe USE_MSR_REG */
-#if XILINX_USE_MSR_INSTR == 1
+#if CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR == 1
 #define MSRSET(val) \
 	__asm__ __volatile__ ("msrset r0," #val );
 
diff --git a/arch/microblaze/include/asm/string.h b/arch/microblaze/include/asm/string.h
index 724f5bdfa6..8f67ec785d 100644
--- a/arch/microblaze/include/asm/string.h
+++ b/arch/microblaze/include/asm/string.h
@@ -17,13 +17,11 @@
 #define __MICROBLAZE_STRING_H__
 
 #if 0
-#define __HAVE_ARCH_BCOPY
 #define __HAVE_ARCH_MEMCPY
 #define __HAVE_ARCH_MEMSET
 #define __HAVE_ARCH_MEMMOVE
 
 extern void *memcpy (void *, const void *, __kernel_size_t);
-extern void bcopy (const char *, char *, int);
 extern void *memset (void *, int, __kernel_size_t);
 extern void *memmove (void *, const void *, __kernel_size_t);
 #endif
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dc34c18258..5c30ae981d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -23,12 +23,19 @@ config TARGET_QEMU_MIPS
 
 config TARGET_MALTA
 	bool "Support malta"
+	select DM
+	select DM_SERIAL
 	select DYNAMIC_IO_PORT_BASE
+	select OF_CONTROL
+	select OF_ISA_BUS
 	select SUPPORTS_BIG_ENDIAN
 	select SUPPORTS_LITTLE_ENDIAN
 	select SUPPORTS_CPU_MIPS32_R1
 	select SUPPORTS_CPU_MIPS32_R2
 	select SUPPORTS_CPU_MIPS32_R6
+	select SUPPORTS_CPU_MIPS64_R1
+	select SUPPORTS_CPU_MIPS64_R2
+	select SUPPORTS_CPU_MIPS64_R6
 	select SWAP_IO_SPACE
 	select MIPS_L1_CACHE_SHIFT_6
 
@@ -221,6 +228,9 @@ config MIPS_TUNE_14KC
 config MIPS_TUNE_24KC
 	bool
 
+config MIPS_TUNE_34KC
+	bool
+
 config MIPS_TUNE_74KC
 	bool
 
@@ -236,6 +246,40 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
 	bool
 
+config SYS_DCACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 Dcache, if known at compile time.
+
+config SYS_DCACHE_LINE_SIZE
+	hex
+	default 0
+	help
+	  The size of L1 Dcache lines, if known at compile time.
+
+config SYS_ICACHE_SIZE
+	int
+	default 0
+	help
+	  The total size of the L1 ICache, if known at compile time.
+
+config SYS_ICACHE_LINE_SIZE
+	int
+	default 0
+	help
+	  The size of L1 Icache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
+	help
+	  Select this (or let it be auto-selected by not defining any cache
+	  sizes) in order to allow U-Boot to automatically detect the sizes
+	  of caches at runtime. This has a small cost in code size & runtime
+	  so if you know the cache configuration for your system at compile
+	  time it would be beneficial to configure it.
+
 config MIPS_L1_CACHE_SHIFT_4
 	bool
 
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 655a493382..efe7e44236 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -4,6 +4,12 @@
 
 head-y := arch/mips/cpu/start.o
 
+ifeq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y := $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+endif
+endif
+
 libs-y += arch/mips/cpu/
 libs-y += arch/mips/lib/
 
@@ -28,6 +34,7 @@ arch-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,-mips64r6
 tune-$(CONFIG_MIPS_TUNE_4KC) += -mtune=4kc
 tune-$(CONFIG_MIPS_TUNE_14KC) += -mtune=14kc
 tune-$(CONFIG_MIPS_TUNE_24KC) += -mtune=24kc
+tune-$(CONFIG_MIPS_TUNE_34KC) += -mtune=34kc
 tune-$(CONFIG_MIPS_TUNE_74KC) += -mtune=74kc
 
 # Include default header files
diff --git a/arch/mips/config.mk b/arch/mips/config.mk
index 609a998f3b..dcd346002c 100644
--- a/arch/mips/config.mk
+++ b/arch/mips/config.mk
@@ -65,7 +65,7 @@ else
 PF_ABICALLS			:= -mabicalls
 PF_PIC				:= -fpic
 PF_PIE				:= -pie
-PF_OBJCOPY			:= -j .got -j .u_boot_list -j .rel.dyn -j .padding
+PF_OBJCOPY			:= -j .got -j .rel.dyn -j .padding
 PF_OBJCOPY			+= -j .dtb.init.rodata
 endif
 
@@ -74,4 +74,5 @@ PLATFORM_CPPFLAGS		+= -msoft-float
 PLATFORM_LDFLAGS		+= -G 0 -static -n -nostdlib
 PLATFORM_RELFLAGS		+= -ffunction-sections -fdata-sections
 LDFLAGS_FINAL			+= --gc-sections $(PF_PIE)
-OBJCOPYFLAGS			+= -j .text -j .rodata -j .data $(PF_OBJCOPY)
+OBJCOPYFLAGS			+= -j .text -j .rodata -j .data -j .u_boot_list
+OBJCOPYFLAGS			+= $(PF_OBJCOPY)
diff --git a/arch/mips/cpu/u-boot-spl.lds b/arch/mips/cpu/u-boot-spl.lds
new file mode 100644
index 0000000000..07004ea111
--- /dev/null
+++ b/arch/mips/cpu/u-boot-spl.lds
@@ -0,0 +1,90 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text : {
+		*(.text*)
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} > .spl_mem
+
+	. = ALIGN(4);
+	.data : {
+		*(SORT_BY_ALIGNMENT(.data*))
+		*(SORT_BY_ALIGNMENT(.sdata*))
+	} > .spl_mem
+
+#ifdef CONFIG_SPL_DM
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	} > .spl_mem
+#endif
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.bss (NOLOAD) : {
+		__bss_start = .;
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > .bss_mem
+
+	.rel.dyn (NOLOAD) : {
+		*(.rel.dyn)
+	}
+
+	.dynsym : {
+		*(.dynsym)
+	}
+
+	.dynbss : {
+		*(.dynbss)
+	}
+
+	.dynstr : {
+		*(.dynstr)
+	}
+
+	.dynamic : {
+		*(.dynamic)
+	}
+
+	.plt : {
+		*(.plt)
+	}
+
+	.interp : {
+		*(.interp)
+	}
+
+	.gnu : {
+		*(.gnu*)
+	}
+
+	.MIPS.stubs : {
+		*(.MIPS.stubs)
+	}
+
+	.hash : {
+		*(.hash)
+	}
+}
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index a94b745550..2f04d73b83 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -4,6 +4,7 @@
 
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
+dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
diff --git a/arch/mips/dts/ap121.dts b/arch/mips/dts/ap121.dts
index e31f601d03..a934a588ff 100644
--- a/arch/mips/dts/ap121.dts
+++ b/arch/mips/dts/ap121.dts
@@ -41,3 +41,8 @@
 		reg = <0>;
 	};
 };
+
+&gmac0 {
+	phy-mode = "rmii";
+	status = "okay";
+};
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi
index 00896b2be4..971f13e83d 100644
--- a/arch/mips/dts/ar933x.dtsi
+++ b/arch/mips/dts/ar933x.dtsi
@@ -75,7 +75,7 @@
 			};
 
 			gmac0: eth@0x19000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x19000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rmii";
@@ -92,7 +92,7 @@
 			};
 
 			gmac1: eth@0x1a000000 {
-				compatible = "qca,ag7240-mac";
+				compatible = "qca,ag933x-mac";
 				reg = <0x1a000000 0x200>;
 				phy = <&phy0>;
 				phy-mode = "rgmii";
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
new file mode 100644
index 0000000000..d339229c2a
--- /dev/null
+++ b/arch/mips/dts/mti,malta.dts
@@ -0,0 +1,32 @@
+/dts-v1/;
+
+/memreserve/ 0x00000000 0x00001000;	/* Exception vectors */
+/memreserve/ 0x000f0000 0x00010000;	/* PIIX4 ISA memory */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mti,malta";
+
+	chosen {
+		stdout-path = &uart0;
+	};
+
+	isa@0 {
+		compatible = "isa";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		ranges = <1 0 0 0x1000>;
+
+		uart0: serial@3f8 {
+			compatible = "ns16550a";
+
+			reg = <1 0x3f8 0x40>;
+			reg-shift = <0>;
+
+			clock-frequency = <1843200>;
+
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/mips/include/asm/cache.h b/arch/mips/include/asm/cache.h
index 806bd26ba9..0cea581e5d 100644
--- a/arch/mips/include/asm/cache.h
+++ b/arch/mips/include/asm/cache.h
@@ -12,4 +12,11 @@
 
 #define ARCH_DMA_MINALIGN	(L1_CACHE_BYTES)
 
+/*
+ * CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
+ * DMA buffer alignment. Satisfy those drivers by providing it as a synonym
+ * of ARCH_DMA_MINALIGN for now.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
+
 #endif /* __MIPS_CACHE_H__ */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 3f230b08f6..37f8ed52e6 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -15,14 +15,6 @@ struct arch_global_data {
 #ifdef CONFIG_DYNAMIC_IO_PORT_BASE
 	unsigned long io_port_base;
 #endif
-#ifdef CONFIG_JZSOC
-	/* There are other clocks in the jz4740 */
-	unsigned long per_clk;	/* Peripheral bus clock */
-	unsigned long dev_clk;	/* Device clock */
-	unsigned long sys_clk;
-	unsigned long tbl;
-	unsigned long lastinc;
-#endif
 #ifdef CONFIG_ARCH_ATH79
 	unsigned long id;
 	unsigned long soc;
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 723a60a199..5b86386bc1 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -92,11 +92,8 @@ static inline unsigned long virt_to_phys(volatile const void *address)
 #ifdef CONFIG_64BIT
 	if (addr < CKSEG0)
 		return XPHYSADDR(addr);
-
-	return CPHYSADDR(addr);
-#else
-	return addr - PAGE_OFFSET + PHYS_OFFSET;
 #endif
+	return CPHYSADDR(addr);
 }
 
 /*
diff --git a/arch/mips/include/asm/jz4740.h b/arch/mips/include/asm/jz4740.h
deleted file mode 100644
index 7a7cfff29a..0000000000
--- a/arch/mips/include/asm/jz4740.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
- * head file for Ingenic Semiconductor's JZ4740 CPU.
- */
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include <asm/addrspace.h>
-#include <asm/cacheops.h>
-
-/* Boot ROM Specification  */
-/* NOR Boot config */
-#define JZ4740_NORBOOT_8BIT	0x00000000	/* 8-bit data bus flash */
-#define JZ4740_NORBOOT_16BIT	0x10101010	/* 16-bit data bus flash */
-#define JZ4740_NORBOOT_32BIT	0x20202020	/* 32-bit data bus flash */
-/* NAND Boot config */
-#define JZ4740_NANDBOOT_B8R3	0xffffffff	/* 8-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B8R2	0xf0f0f0f0	/* 8-bit bus & 2 row cycles */
-#define JZ4740_NANDBOOT_B16R3	0x0f0f0f0f	/* 16-bit bus & 3 row cycles */
-#define JZ4740_NANDBOOT_B16R2	0x00000000	/* 16-bit bus & 2 row cycles */
-
-/* 1st-level interrupts */
-#define JZ4740_IRQ_I2C		1
-#define JZ4740_IRQ_UHC		3
-#define JZ4740_IRQ_UART0	9
-#define JZ4740_IRQ_SADC		12
-#define JZ4740_IRQ_MSC		14
-#define JZ4740_IRQ_RTC		15
-#define JZ4740_IRQ_SSI		16
-#define JZ4740_IRQ_CIM		17
-#define JZ4740_IRQ_AIC		18
-#define JZ4740_IRQ_ETH		19
-#define JZ4740_IRQ_DMAC		20
-#define JZ4740_IRQ_TCU2		21
-#define JZ4740_IRQ_TCU1		22
-#define JZ4740_IRQ_TCU0		23
-#define JZ4740_IRQ_UDC		24
-#define JZ4740_IRQ_GPIO3	25
-#define JZ4740_IRQ_GPIO2	26
-#define JZ4740_IRQ_GPIO1	27
-#define JZ4740_IRQ_GPIO0	28
-#define JZ4740_IRQ_IPU		29
-#define JZ4740_IRQ_LCD		30
-/* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA_0	32  /* 32 to 37 for DMAC channel 0 to 5 */
-#define JZ4740_IRQ_GPIO_0	48  /* 48 to 175 for GPIO pin 0 to 127 */
-
-/* Register Definitions */
-#define JZ4740_CPM_BASE		0x10000000
-#define JZ4740_INTC_BASE	0x10001000
-#define JZ4740_TCU_BASE		0x10002000
-#define JZ4740_WDT_BASE		0x10002000
-#define JZ4740_RTC_BASE		0x10003000
-#define JZ4740_GPIO_BASE	0x10010000
-#define JZ4740_AIC_BASE		0x10020000
-#define JZ4740_ICDC_BASE	0x10020000
-#define JZ4740_MSC_BASE		0x10021000
-#define JZ4740_UART0_BASE	0x10030000
-#define JZ4740_I2C_BASE		0x10042000
-#define JZ4740_SSI_BASE		0x10043000
-#define JZ4740_SADC_BASE	0x10070000
-#define JZ4740_EMC_BASE		0x13010000
-#define JZ4740_DMAC_BASE	0x13020000
-#define JZ4740_UHC_BASE		0x13030000
-#define JZ4740_UDC_BASE		0x13040000
-#define JZ4740_LCD_BASE		0x13050000
-#define JZ4740_SLCD_BASE	0x13050000
-#define JZ4740_CIM_BASE		0x13060000
-#define JZ4740_ETH_BASE		0x13100000
-
-/* 8bit Mode Register of SDRAM bank 0 */
-#define JZ4740_EMC_SDMR0	(JZ4740_EMC_BASE + 0xa000)
-
-/* GPIO (General-Purpose I/O Ports) */
-/*  = 0,1,2,3 */
-#define GPIO_PXPIN(n)	\
-	(JZ4740_GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
-#define GPIO_PXDAT(n)	\
-	(JZ4740_GPIO_BASE + (0x10 + (n)*0x100)) /* Port Data Register */
-#define GPIO_PXDATS(n)	\
-	(JZ4740_GPIO_BASE + (0x14 + (n)*0x100)) /* Port Data Set Register */
-#define GPIO_PXDATC(n)	\
-	(JZ4740_GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
-#define GPIO_PXIM(n)	\
-	(JZ4740_GPIO_BASE + (0x20 + (n)*0x100)) /* Interrupt Mask Register */
-#define GPIO_PXIMS(n)	\
-	(JZ4740_GPIO_BASE + (0x24 + (n)*0x100)) /* Interrupt Mask Set Reg */
-#define GPIO_PXIMC(n)	\
-	(JZ4740_GPIO_BASE + (0x28 + (n)*0x100)) /* Interrupt Mask Clear Reg */
-#define GPIO_PXPE(n)	\
-	(JZ4740_GPIO_BASE + (0x30 + (n)*0x100)) /* Pull Enable Register */
-#define GPIO_PXPES(n)	\
-	(JZ4740_GPIO_BASE + (0x34 + (n)*0x100)) /* Pull Enable Set Reg. */
-#define GPIO_PXPEC(n)	\
-	(JZ4740_GPIO_BASE + (0x38 + (n)*0x100)) /* Pull Enable Clear Reg. */
-#define GPIO_PXFUN(n)	\
-	(JZ4740_GPIO_BASE + (0x40 + (n)*0x100)) /* Function Register */
-#define GPIO_PXFUNS(n)	\
-	(JZ4740_GPIO_BASE + (0x44 + (n)*0x100)) /* Function Set Register */
-#define GPIO_PXFUNC(n)	\
-	(JZ4740_GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
-#define GPIO_PXSEL(n)	\
-	(JZ4740_GPIO_BASE + (0x50 + (n)*0x100)) /* Select Register */
-#define GPIO_PXSELS(n)	\
-	(JZ4740_GPIO_BASE + (0x54 + (n)*0x100)) /* Select Set Register */
-#define GPIO_PXSELC(n)	\
-	(JZ4740_GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
-#define GPIO_PXDIR(n)	\
-	(JZ4740_GPIO_BASE + (0x60 + (n)*0x100)) /* Direction Register */
-#define GPIO_PXDIRS(n)	\
-	(JZ4740_GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */
-#define GPIO_PXDIRC(n)	\
-	(JZ4740_GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
-#define GPIO_PXTRG(n)	\
-	(JZ4740_GPIO_BASE + (0x70 + (n)*0x100)) /* Trigger Register */
-#define GPIO_PXTRGS(n)	\
-	(JZ4740_GPIO_BASE + (0x74 + (n)*0x100)) /* Trigger Set Register */
-#define GPIO_PXTRGC(n)	\
-	(JZ4740_GPIO_BASE + (0x78 + (n)*0x100)) /* Trigger Set Register */
-
-/* Static Memory Control Register */
-#define EMC_SMCR_STRV_BIT	24
-#define EMC_SMCR_STRV_MASK	(0x0f << EMC_SMCR_STRV_BIT)
-#define EMC_SMCR_TAW_BIT	20
-#define EMC_SMCR_TAW_MASK	(0x0f << EMC_SMCR_TAW_BIT)
-#define EMC_SMCR_TBP_BIT	16
-#define EMC_SMCR_TBP_MASK	(0x0f << EMC_SMCR_TBP_BIT)
-#define EMC_SMCR_TAH_BIT	12
-#define EMC_SMCR_TAH_MASK	(0x07 << EMC_SMCR_TAH_BIT)
-#define EMC_SMCR_TAS_BIT	8
-#define EMC_SMCR_TAS_MASK	(0x07 << EMC_SMCR_TAS_BIT)
-#define EMC_SMCR_BW_BIT		6
-#define EMC_SMCR_BW_MASK	(0x03 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_8BIT	(0 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_16BIT	(1 << EMC_SMCR_BW_BIT)
-  #define EMC_SMCR_BW_32BIT	(2 << EMC_SMCR_BW_BIT)
-#define EMC_SMCR_BCM		(1 << 3)
-#define EMC_SMCR_BL_BIT		1
-#define EMC_SMCR_BL_MASK	(0x03 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_4		(0 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_8		(1 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_16	(2 << EMC_SMCR_BL_BIT)
-  #define EMC_SMCR_BL_32	(3 << EMC_SMCR_BL_BIT)
-#define EMC_SMCR_SMT		(1 << 0)
-
-/* Static Memory Bank Addr Config Reg */
-#define EMC_SACR_BASE_BIT	8
-#define EMC_SACR_BASE_MASK	(0xff << EMC_SACR_BASE_BIT)
-#define EMC_SACR_MASK_BIT	0
-#define EMC_SACR_MASK_MASK	(0xff << EMC_SACR_MASK_BIT)
-
-/* NAND Flash Control/Status Register */
-#define EMC_NFCSR_NFCE4		(1 << 7) /* NAND Flash Enable */
-#define EMC_NFCSR_NFE4		(1 << 6) /* NAND Flash FCE# Assertion Enable */
-#define EMC_NFCSR_NFCE3		(1 << 5)
-#define EMC_NFCSR_NFE3		(1 << 4)
-#define EMC_NFCSR_NFCE2		(1 << 3)
-#define EMC_NFCSR_NFE2		(1 << 2)
-#define EMC_NFCSR_NFCE1		(1 << 1)
-#define EMC_NFCSR_NFE1		(1 << 0)
-
-/* NAND Flash ECC Control Register */
-#define EMC_NFECR_PRDY		(1 << 4) /* Parity Ready */
-#define EMC_NFECR_RS_DECODING	(0 << 3) /* RS is in decoding phase */
-#define EMC_NFECR_RS_ENCODING	(1 << 3) /* RS is in encoding phase */
-#define EMC_NFECR_HAMMING	(0 << 2) /* Use HAMMING Correction Algorithm */
-#define EMC_NFECR_RS		(1 << 2) /* Select RS Correction Algorithm */
-#define EMC_NFECR_ERST		(1 << 1) /* ECC Reset */
-#define EMC_NFECR_ECCE		(1 << 0) /* ECC Enable */
-
-/* NAND Flash ECC Data Register */
-#define EMC_NFECC_ECC2_BIT	16
-#define EMC_NFECC_ECC2_MASK	(0xff << EMC_NFECC_ECC2_BIT)
-#define EMC_NFECC_ECC1_BIT	8
-#define EMC_NFECC_ECC1_MASK	(0xff << EMC_NFECC_ECC1_BIT)
-#define EMC_NFECC_ECC0_BIT	0
-#define EMC_NFECC_ECC0_MASK	(0xff << EMC_NFECC_ECC0_BIT)
-
-/* NAND Flash Interrupt Status Register */
-#define EMC_NFINTS_ERRCNT_BIT	29       /* Error Count */
-#define EMC_NFINTS_ERRCNT_MASK	(0x7 << EMC_NFINTS_ERRCNT_BIT)
-#define EMC_NFINTS_PADF		(1 << 4) /* Padding Finished */
-#define EMC_NFINTS_DECF		(1 << 3) /* Decoding Finished */
-#define EMC_NFINTS_ENCF		(1 << 2) /* Encoding Finished */
-#define EMC_NFINTS_UNCOR	(1 << 1) /* Uncorrectable Error Occurred */
-#define EMC_NFINTS_ERR		(1 << 0) /* Error Occurred */
-
-/* NAND Flash Interrupt Enable Register */
-#define EMC_NFINTE_PADFE	(1 << 4) /* Padding Finished Interrupt */
-#define EMC_NFINTE_DECFE	(1 << 3) /* Decoding Finished Interrupt */
-#define EMC_NFINTE_ENCFE	(1 << 2) /* Encoding Finished Interrupt */
-#define EMC_NFINTE_UNCORE	(1 << 1) /* Uncorrectable Error Occurred Intr */
-#define EMC_NFINTE_ERRE		(1 << 0) /* Error Occurred Interrupt */
-
-/* NAND Flash RS Error Report Register */
-#define EMC_NFERR_INDEX_BIT	16       /* Error Symbol Index */
-#define EMC_NFERR_INDEX_MASK	(0x1ff << EMC_NFERR_INDEX_BIT)
-#define EMC_NFERR_MASK_BIT	0        /* Error Symbol Value */
-#define EMC_NFERR_MASK_MASK	(0x1ff << EMC_NFERR_MASK_BIT)
-
-/* DRAM Control Register */
-#define EMC_DMCR_BW_BIT		31
-#define EMC_DMCR_BW		(1 << EMC_DMCR_BW_BIT)
-#define EMC_DMCR_CA_BIT		26
-#define EMC_DMCR_CA_MASK	(0x07 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_8		(0 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_9		(1 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_10	(2 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_11	(3 << EMC_DMCR_CA_BIT)
-  #define EMC_DMCR_CA_12	(4 << EMC_DMCR_CA_BIT)
-#define EMC_DMCR_RMODE		(1 << 25)
-#define EMC_DMCR_RFSH		(1 << 24)
-#define EMC_DMCR_MRSET		(1 << 23)
-#define EMC_DMCR_RA_BIT		20
-#define EMC_DMCR_RA_MASK	(0x03 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_11	(0 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_12	(1 << EMC_DMCR_RA_BIT)
-  #define EMC_DMCR_RA_13	(2 << EMC_DMCR_RA_BIT)
-#define EMC_DMCR_BA_BIT		19
-#define EMC_DMCR_BA		(1 << EMC_DMCR_BA_BIT)
-#define EMC_DMCR_PDM		(1 << 18)
-#define EMC_DMCR_EPIN		(1 << 17)
-#define EMC_DMCR_TRAS_BIT	13
-#define EMC_DMCR_TRAS_MASK	(0x07 << EMC_DMCR_TRAS_BIT)
-#define EMC_DMCR_RCD_BIT	11
-#define EMC_DMCR_RCD_MASK	(0x03 << EMC_DMCR_RCD_BIT)
-#define EMC_DMCR_TPC_BIT	8
-#define EMC_DMCR_TPC_MASK	(0x07 << EMC_DMCR_TPC_BIT)
-#define EMC_DMCR_TRWL_BIT	5
-#define EMC_DMCR_TRWL_MASK	(0x03 << EMC_DMCR_TRWL_BIT)
-#define EMC_DMCR_TRC_BIT	2
-#define EMC_DMCR_TRC_MASK	(0x07 << EMC_DMCR_TRC_BIT)
-#define EMC_DMCR_TCL_BIT	0
-#define EMC_DMCR_TCL_MASK	(0x03 << EMC_DMCR_TCL_BIT)
-
-/* Refresh Time Control/Status Register */
-#define EMC_RTCSR_CMF		(1 << 7)
-#define EMC_RTCSR_CKS_BIT	0
-#define EMC_RTCSR_CKS_MASK	(0x07 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_DISABLE	(0 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4	(1 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_16	(2 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_64	(3 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_256	(4 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_1024	(5 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_2048	(6 << EMC_RTCSR_CKS_BIT)
-  #define EMC_RTCSR_CKS_4096	(7 << EMC_RTCSR_CKS_BIT)
-
-/* SDRAM Bank Address Configuration Register */
-#define EMC_DMAR_BASE_BIT	8
-#define EMC_DMAR_BASE_MASK	(0xff << EMC_DMAR_BASE_BIT)
-#define EMC_DMAR_MASK_BIT	0
-#define EMC_DMAR_MASK_MASK	(0xff << EMC_DMAR_MASK_BIT)
-
-/* Mode Register of SDRAM bank 0 */
-#define EMC_SDMR_BM		(1 << 9) /* Write Burst Mode */
-#define EMC_SDMR_OM_BIT		7        /* Operating Mode */
-#define EMC_SDMR_OM_MASK	(3 << EMC_SDMR_OM_BIT)
-  #define EMC_SDMR_OM_NORMAL	(0 << EMC_SDMR_OM_BIT)
-#define EMC_SDMR_CAS_BIT	4        /* CAS Latency */
-#define EMC_SDMR_CAS_MASK	(7 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_1	(1 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_2	(2 << EMC_SDMR_CAS_BIT)
-  #define EMC_SDMR_CAS_3	(3 << EMC_SDMR_CAS_BIT)
-#define EMC_SDMR_BT_BIT		3        /* Burst Type */
-#define EMC_SDMR_BT_MASK	(1 << EMC_SDMR_BT_BIT)
-  #define EMC_SDMR_BT_SEQ	(0 << EMC_SDMR_BT_BIT) /* Sequential */
-  #define EMC_SDMR_BT_INT	(1 << EMC_SDMR_BT_BIT) /* Interleave */
-#define EMC_SDMR_BL_BIT		0        /* Burst Length */
-#define EMC_SDMR_BL_MASK	(7 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_1		(0 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_2		(1 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_4		(2 << EMC_SDMR_BL_BIT)
-  #define EMC_SDMR_BL_8		(3 << EMC_SDMR_BL_BIT)
-
-#define EMC_SDMR_CAS2_16BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS2_32BIT \
-	(EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-#define EMC_SDMR_CAS3_16BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2)
-#define EMC_SDMR_CAS3_32BIT \
-	(EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4)
-
-/* RTC Control Register */
-#define RTC_RCR_WRDY	(1 << 7)  /* Write Ready Flag */
-#define RTC_RCR_HZ	(1 << 6)  /* 1Hz Flag */
-#define RTC_RCR_HZIE	(1 << 5)  /* 1Hz Interrupt Enable */
-#define RTC_RCR_AF	(1 << 4)  /* Alarm Flag */
-#define RTC_RCR_AIE	(1 << 3)  /* Alarm Interrupt Enable */
-#define RTC_RCR_AE	(1 << 2)  /* Alarm Enable */
-#define RTC_RCR_RTCE	(1 << 0)  /* RTC Enable */
-
-/* RTC Regulator Register */
-#define RTC_RGR_LOCK		(1 << 31) /* Lock Bit */
-#define RTC_RGR_ADJC_BIT	16
-#define RTC_RGR_ADJC_MASK	(0x3ff << RTC_RGR_ADJC_BIT)
-#define RTC_RGR_NC1HZ_BIT	0
-#define RTC_RGR_NC1HZ_MASK	(0xffff << RTC_RGR_NC1HZ_BIT)
-
-/* Hibernate Control Register */
-#define RTC_HCR_PD		(1 << 0)  /* Power Down */
-
-/* Hibernate Wakeup Filter Counter Register */
-#define RTC_HWFCR_BIT		5
-#define RTC_HWFCR_MASK		(0x7ff << RTC_HWFCR_BIT)
-
-/* Hibernate Reset Counter Register */
-#define RTC_HRCR_BIT		5
-#define RTC_HRCR_MASK		(0x7f << RTC_HRCR_BIT)
-
-/* Hibernate Wakeup Control Register */
-#define RTC_HWCR_EALM		(1 << 0)  /* RTC alarm wakeup enable */
-
-/* Hibernate Wakeup Status Register */
-#define RTC_HWRSR_HR		(1 << 5)  /* Hibernate reset */
-#define RTC_HWRSR_PPR		(1 << 4)  /* PPR reset */
-#define RTC_HWRSR_PIN		(1 << 1)  /* Wakeup pin status bit */
-#define RTC_HWRSR_ALM		(1 << 0)  /* RTC alarm status bit */
-
-/* Clock Control Register */
-#define CPM_CPCCR_I2CS		(1 << 31)
-#define CPM_CPCCR_CLKOEN	(1 << 30)
-#define CPM_CPCCR_UCS		(1 << 29)
-#define CPM_CPCCR_UDIV_BIT	23
-#define CPM_CPCCR_UDIV_MASK	(0x3f << CPM_CPCCR_UDIV_BIT)
-#define CPM_CPCCR_CE		(1 << 22)
-#define CPM_CPCCR_PCS		(1 << 21)
-#define CPM_CPCCR_LDIV_BIT	16
-#define CPM_CPCCR_LDIV_MASK	(0x1f << CPM_CPCCR_LDIV_BIT)
-#define CPM_CPCCR_MDIV_BIT	12
-#define CPM_CPCCR_MDIV_MASK	(0x0f << CPM_CPCCR_MDIV_BIT)
-#define CPM_CPCCR_PDIV_BIT	8
-#define CPM_CPCCR_PDIV_MASK	(0x0f << CPM_CPCCR_PDIV_BIT)
-#define CPM_CPCCR_HDIV_BIT	4
-#define CPM_CPCCR_HDIV_MASK	(0x0f << CPM_CPCCR_HDIV_BIT)
-#define CPM_CPCCR_CDIV_BIT	0
-#define CPM_CPCCR_CDIV_MASK	(0x0f << CPM_CPCCR_CDIV_BIT)
-
-/* I2S Clock Divider Register */
-#define CPM_I2SCDR_I2SDIV_BIT	0
-#define CPM_I2SCDR_I2SDIV_MASK	(0x1ff << CPM_I2SCDR_I2SDIV_BIT)
-
-/* LCD Pixel Clock Divider Register */
-#define CPM_LPCDR_PIXDIV_BIT	0
-#define CPM_LPCDR_PIXDIV_MASK	(0x1ff << CPM_LPCDR_PIXDIV_BIT)
-
-/* MSC Clock Divider Register */
-#define CPM_MSCCDR_MSCDIV_BIT	0
-#define CPM_MSCCDR_MSCDIV_MASK	(0x1f << CPM_MSCCDR_MSCDIV_BIT)
-
-/* PLL Control Register */
-#define CPM_CPPCR_PLLM_BIT	23
-#define CPM_CPPCR_PLLM_MASK	(0x1ff << CPM_CPPCR_PLLM_BIT)
-#define CPM_CPPCR_PLLN_BIT	18
-#define CPM_CPPCR_PLLN_MASK	(0x1f << CPM_CPPCR_PLLN_BIT)
-#define CPM_CPPCR_PLLOD_BIT	16
-#define CPM_CPPCR_PLLOD_MASK	(0x03 << CPM_CPPCR_PLLOD_BIT)
-#define CPM_CPPCR_PLLS		(1 << 10)
-#define CPM_CPPCR_PLLBP		(1 << 9)
-#define CPM_CPPCR_PLLEN		(1 << 8)
-#define CPM_CPPCR_PLLST_BIT	0
-#define CPM_CPPCR_PLLST_MASK	(0xff << CPM_CPPCR_PLLST_BIT)
-
-/* Low Power Control Register */
-#define CPM_LCR_DOZE_DUTY_BIT	3
-#define CPM_LCR_DOZE_DUTY_MASK	(0x1f << CPM_LCR_DOZE_DUTY_BIT)
-#define CPM_LCR_DOZE_ON		(1 << 2)
-#define CPM_LCR_LPM_BIT		0
-#define CPM_LCR_LPM_MASK	(0x3 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_IDLE	(0x0 << CPM_LCR_LPM_BIT)
-  #define CPM_LCR_LPM_SLEEP	(0x1 << CPM_LCR_LPM_BIT)
-
-/* Clock Gate Register */
-#define CPM_CLKGR_UART1		(1 << 15)
-#define CPM_CLKGR_UHC		(1 << 14)
-#define CPM_CLKGR_IPU		(1 << 13)
-#define CPM_CLKGR_DMAC		(1 << 12)
-#define CPM_CLKGR_UDC		(1 << 11)
-#define CPM_CLKGR_LCD		(1 << 10)
-#define CPM_CLKGR_CIM		(1 << 9)
-#define CPM_CLKGR_SADC		(1 << 8)
-#define CPM_CLKGR_MSC		(1 << 7)
-#define CPM_CLKGR_AIC1		(1 << 6)
-#define CPM_CLKGR_AIC2		(1 << 5)
-#define CPM_CLKGR_SSI		(1 << 4)
-#define CPM_CLKGR_I2C		(1 << 3)
-#define CPM_CLKGR_RTC		(1 << 2)
-#define CPM_CLKGR_TCU		(1 << 1)
-#define CPM_CLKGR_UART0		(1 << 0)
-
-/* Sleep Control Register */
-#define CPM_SCR_O1ST_BIT	8
-#define CPM_SCR_O1ST_MASK	(0xff << CPM_SCR_O1ST_BIT)
-#define CPM_SCR_UDCPHY_ENABLE	(1 << 6)
-#define CPM_SCR_USBPHY_DISABLE	(1 << 7)
-#define CPM_SCR_OSC_ENABLE	(1 << 4)
-
-/* Hibernate Control Register */
-#define CPM_HCR_PD		(1 << 0)
-
-/* Wakeup Filter Counter Register in Hibernate Mode */
-#define CPM_HWFCR_TIME_BIT	0
-#define CPM_HWFCR_TIME_MASK	(0x3ff << CPM_HWFCR_TIME_BIT)
-
-/* Reset Counter Register in Hibernate Mode */
-#define CPM_HRCR_TIME_BIT	0
-#define CPM_HRCR_TIME_MASK	(0x7f << CPM_HRCR_TIME_BIT)
-
-/* Wakeup Control Register in Hibernate Mode */
-#define CPM_HWCR_WLE_LOW	(0 << 2)
-#define CPM_HWCR_WLE_HIGH	(1 << 2)
-#define CPM_HWCR_PIN_WAKEUP	(1 << 1)
-#define CPM_HWCR_RTC_WAKEUP	(1 << 0)
-
-/* Wakeup Status Register in Hibernate Mode */
-#define CPM_HWSR_WSR_PIN	(1 << 1)
-#define CPM_HWSR_WSR_RTC	(1 << 0)
-
-/* Reset Status Register */
-#define CPM_RSR_HR		(1 << 2)
-#define CPM_RSR_WR		(1 << 1)
-#define CPM_RSR_PR		(1 << 0)
-
-/* Register definitions */
-#define TCU_TCSR_PWM_SD		(1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH	(1 << 8)
-#define TCU_TCSR_PWM_EN		(1 << 7)
-#define TCU_TCSR_PRESCALE_BIT	3
-#define TCU_TCSR_PRESCALE_MASK	(0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1	(0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4	(0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16	(0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64	(0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256	(0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024	(0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN		(1 << 2)
-#define TCU_TCSR_RTC_EN		(1 << 1)
-#define TCU_TCSR_PCK_EN		(1 << 0)
-
-#define TCU_TER_TCEN5		(1 << 5)
-#define TCU_TER_TCEN4		(1 << 4)
-#define TCU_TER_TCEN3		(1 << 3)
-#define TCU_TER_TCEN2		(1 << 2)
-#define TCU_TER_TCEN1		(1 << 1)
-#define TCU_TER_TCEN0		(1 << 0)
-
-#define TCU_TESR_TCST5		(1 << 5)
-#define TCU_TESR_TCST4		(1 << 4)
-#define TCU_TESR_TCST3		(1 << 3)
-#define TCU_TESR_TCST2		(1 << 2)
-#define TCU_TESR_TCST1		(1 << 1)
-#define TCU_TESR_TCST0		(1 << 0)
-
-#define TCU_TECR_TCCL5		(1 << 5)
-#define TCU_TECR_TCCL4		(1 << 4)
-#define TCU_TECR_TCCL3		(1 << 3)
-#define TCU_TECR_TCCL2		(1 << 2)
-#define TCU_TECR_TCCL1		(1 << 1)
-#define TCU_TECR_TCCL0		(1 << 0)
-
-#define TCU_TFR_HFLAG5		(1 << 21)
-#define TCU_TFR_HFLAG4		(1 << 20)
-#define TCU_TFR_HFLAG3		(1 << 19)
-#define TCU_TFR_HFLAG2		(1 << 18)
-#define TCU_TFR_HFLAG1		(1 << 17)
-#define TCU_TFR_HFLAG0		(1 << 16)
-#define TCU_TFR_FFLAG5		(1 << 5)
-#define TCU_TFR_FFLAG4		(1 << 4)
-#define TCU_TFR_FFLAG3		(1 << 3)
-#define TCU_TFR_FFLAG2		(1 << 2)
-#define TCU_TFR_FFLAG1		(1 << 1)
-#define TCU_TFR_FFLAG0		(1 << 0)
-
-#define TCU_TFSR_HFLAG5		(1 << 21)
-#define TCU_TFSR_HFLAG4		(1 << 20)
-#define TCU_TFSR_HFLAG3		(1 << 19)
-#define TCU_TFSR_HFLAG2		(1 << 18)
-#define TCU_TFSR_HFLAG1		(1 << 17)
-#define TCU_TFSR_HFLAG0		(1 << 16)
-#define TCU_TFSR_FFLAG5		(1 << 5)
-#define TCU_TFSR_FFLAG4		(1 << 4)
-#define TCU_TFSR_FFLAG3		(1 << 3)
-#define TCU_TFSR_FFLAG2		(1 << 2)
-#define TCU_TFSR_FFLAG1		(1 << 1)
-#define TCU_TFSR_FFLAG0		(1 << 0)
-
-#define TCU_TFCR_HFLAG5		(1 << 21)
-#define TCU_TFCR_HFLAG4		(1 << 20)
-#define TCU_TFCR_HFLAG3		(1 << 19)
-#define TCU_TFCR_HFLAG2		(1 << 18)
-#define TCU_TFCR_HFLAG1		(1 << 17)
-#define TCU_TFCR_HFLAG0		(1 << 16)
-#define TCU_TFCR_FFLAG5		(1 << 5)
-#define TCU_TFCR_FFLAG4		(1 << 4)
-#define TCU_TFCR_FFLAG3		(1 << 3)
-#define TCU_TFCR_FFLAG2		(1 << 2)
-#define TCU_TFCR_FFLAG1		(1 << 1)
-#define TCU_TFCR_FFLAG0		(1 << 0)
-
-#define TCU_TMR_HMASK5		(1 << 21)
-#define TCU_TMR_HMASK4		(1 << 20)
-#define TCU_TMR_HMASK3		(1 << 19)
-#define TCU_TMR_HMASK2		(1 << 18)
-#define TCU_TMR_HMASK1		(1 << 17)
-#define TCU_TMR_HMASK0		(1 << 16)
-#define TCU_TMR_FMASK5		(1 << 5)
-#define TCU_TMR_FMASK4		(1 << 4)
-#define TCU_TMR_FMASK3		(1 << 3)
-#define TCU_TMR_FMASK2		(1 << 2)
-#define TCU_TMR_FMASK1		(1 << 1)
-#define TCU_TMR_FMASK0		(1 << 0)
-
-#define TCU_TMSR_HMST5		(1 << 21)
-#define TCU_TMSR_HMST4		(1 << 20)
-#define TCU_TMSR_HMST3		(1 << 19)
-#define TCU_TMSR_HMST2		(1 << 18)
-#define TCU_TMSR_HMST1		(1 << 17)
-#define TCU_TMSR_HMST0		(1 << 16)
-#define TCU_TMSR_FMST5		(1 << 5)
-#define TCU_TMSR_FMST4		(1 << 4)
-#define TCU_TMSR_FMST3		(1 << 3)
-#define TCU_TMSR_FMST2		(1 << 2)
-#define TCU_TMSR_FMST1		(1 << 1)
-#define TCU_TMSR_FMST0		(1 << 0)
-
-#define TCU_TMCR_HMCL5		(1 << 21)
-#define TCU_TMCR_HMCL4		(1 << 20)
-#define TCU_TMCR_HMCL3		(1 << 19)
-#define TCU_TMCR_HMCL2		(1 << 18)
-#define TCU_TMCR_HMCL1		(1 << 17)
-#define TCU_TMCR_HMCL0		(1 << 16)
-#define TCU_TMCR_FMCL5		(1 << 5)
-#define TCU_TMCR_FMCL4		(1 << 4)
-#define TCU_TMCR_FMCL3		(1 << 3)
-#define TCU_TMCR_FMCL2		(1 << 2)
-#define TCU_TMCR_FMCL1		(1 << 1)
-#define TCU_TMCR_FMCL0		(1 << 0)
-
-#define TCU_TSR_WDTS		(1 << 16)
-#define TCU_TSR_STOP5		(1 << 5)
-#define TCU_TSR_STOP4		(1 << 4)
-#define TCU_TSR_STOP3		(1 << 3)
-#define TCU_TSR_STOP2		(1 << 2)
-#define TCU_TSR_STOP1		(1 << 1)
-#define TCU_TSR_STOP0		(1 << 0)
-
-#define TCU_TSSR_WDTSS		(1 << 16)
-#define TCU_TSSR_STPS5		(1 << 5)
-#define TCU_TSSR_STPS4		(1 << 4)
-#define TCU_TSSR_STPS3		(1 << 3)
-#define TCU_TSSR_STPS2		(1 << 2)
-#define TCU_TSSR_STPS1		(1 << 1)
-#define TCU_TSSR_STPS0		(1 << 0)
-
-#define TCU_TSSR_WDTSC		(1 << 16)
-#define TCU_TSSR_STPC5		(1 << 5)
-#define TCU_TSSR_STPC4		(1 << 4)
-#define TCU_TSSR_STPC3		(1 << 3)
-#define TCU_TSSR_STPC2		(1 << 2)
-#define TCU_TSSR_STPC1		(1 << 1)
-#define TCU_TSSR_STPC0		(1 << 0)
-
-/* Register definition */
-#define WDT_TCSR_PRESCALE_BIT	3
-#define WDT_TCSR_PRESCALE_MASK	(0x7 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1	(0x0 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE4	(0x1 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE16	(0x2 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE64	(0x3 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE256	(0x4 << WDT_TCSR_PRESCALE_BIT)
-  #define WDT_TCSR_PRESCALE1024	(0x5 << WDT_TCSR_PRESCALE_BIT)
-#define WDT_TCSR_EXT_EN		(1 << 2)
-#define WDT_TCSR_RTC_EN		(1 << 1)
-#define WDT_TCSR_PCK_EN		(1 << 0)
-#define WDT_TCER_TCEN		(1 << 0)
-
-/*
- * Define macros for UART_IER
- * UART Interrupt Enable Register
- */
-#define UART_IER_RIE	(1 << 0) /* 0: receive fifo full interrupt disable */
-#define UART_IER_TIE	(1 << 1) /* 0: transmit fifo empty interrupt disable */
-#define UART_IER_RLIE	(1 << 2) /* 0: receive line status interrupt disable */
-#define UART_IER_MIE	(1 << 3) /* 0: modem status interrupt disable */
-#define UART_IER_RTIE	(1 << 4) /* 0: receive timeout interrupt disable */
-
-/*
- * Define macros for UART_ISR
- * UART Interrupt Status Register
- */
-#define UART_ISR_IP	(1 << 0) /* 0: interrupt is pending 1: no interrupt */
-#define UART_ISR_IID	(7 << 1) /* Source of Interrupt */
-#define UART_ISR_IID_MSI  (0 << 1) /* Modem status interrupt */
-#define UART_ISR_IID_THRI (1 << 1) /* Transmitter holding register empty */
-#define UART_ISR_IID_RDI  (2 << 1) /* Receiver data interrupt */
-#define UART_ISR_IID_RLSI (3 << 1) /* Receiver line status interrupt */
-/* FIFO mode select, set when UART_FCR.FE is set to 1 */
-#define UART_ISR_FFMS	(3 << 6)
-#define UART_ISR_FFMS_NO_FIFO	(0 << 6)
-#define UART_ISR_FFMS_FIFO_MODE	(3 << 6)
-
-/*
- * Define macros for UART_FCR
- * UART FIFO Control Register
- */
-#define UART_FCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
-#define UART_FCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
-#define UART_FCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UART_FCR_DMS	(1 << 3)	/* 0: disable DMA mode */
-#define UART_FCR_UUE	(1 << 4)	/* 0: disable UART */
-#define UART_FCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
-#define UART_FCR_RTRG_1	(0 << 6)
-#define UART_FCR_RTRG_4	(1 << 6)
-#define UART_FCR_RTRG_8	(2 << 6)
-#define UART_FCR_RTRG_15	(3 << 6)
-
-/*
- * Define macros for UART_LCR
- * UART Line Control Register
- */
-#define UART_LCR_WLEN	(3 << 0)	/* word length */
-#define UART_LCR_WLEN_5	(0 << 0)
-#define UART_LCR_WLEN_6	(1 << 0)
-#define UART_LCR_WLEN_7	(2 << 0)
-#define UART_LCR_WLEN_8	(3 << 0)
-#define UART_LCR_STOP	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_1	(0 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UART_LCR_STOP_2	(1 << 2)
-	/* 0: 1 stop bit when word length is 5,6,7,8
-	   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-
-#define UART_LCR_PE	(1 << 3) /* 0: parity disable */
-#define UART_LCR_PROE	(1 << 4) /* 0: even parity  1: odd parity */
-#define UART_LCR_SPAR	(1 << 5) /* 0: sticky parity disable */
-#define UART_LCR_SBRK	(1 << 6) /* write 0 normal, write 1 send break */
-/* 0: access UART_RDR/TDR/IER  1: access UART_DLLR/DLHR */
-#define UART_LCR_DLAB	(1 << 7)
-
-/*
- * Define macros for UART_LSR
- * UART Line Status Register
- */
-/* 0: receive FIFO is empty  1: receive data is ready */
-#define UART_LSR_DR	(1 << 0)
-/* 0: no overrun error */
-#define UART_LSR_ORER	(1 << 1)
-/* 0: no parity error */
-#define UART_LSR_PER	(1 << 2)
-/* 0; no framing error */
-#define UART_LSR_FER	(1 << 3)
-/* 0: no break detected  1: receive a break signal */
-#define UART_LSR_BRK	(1 << 4)
-/* 1: transmit FIFO half "empty" */
-#define UART_LSR_TDRQ	(1 << 5)
-/* 1: transmit FIFO and shift registers empty */
-#define UART_LSR_TEMT	(1 << 6)
-/* 0: no receive error  1: receive error in FIFO mode */
-#define UART_LSR_RFER	(1 << 7)
-
-/*
- * Define macros for UART_MCR
- * UART Modem Control Register
- */
-#define UART_MCR_DTR	(1 << 0) /* 0: DTR_ ouput high */
-#define UART_MCR_RTS	(1 << 1) /* 0: RTS_ output high */
-/* 0: UART_MSR.RI is set to 0 and RI_ input high */
-#define UART_MCR_OUT1	(1 << 2)
-/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */
-#define UART_MCR_OUT2	(1 << 3)
-#define UART_MCR_LOOP	(1 << 4) /* 0: normal  1: loopback mode */
-#define UART_MCR_MCE	(1 << 7) /* 0: modem function is disable */
-
-/*
- * Define macros for UART_MSR
- * UART Modem Status Register
- */
-#define UART_MSR_DCTS	(1 << 0) /* 0: no change on CTS_ since last read */
-#define UART_MSR_DDSR	(1 << 1) /* 0: no change on DSR_ since last read */
-#define UART_MSR_DRI	(1 << 2) /* 0: no change on RI_  since last read */
-#define UART_MSR_DDCD	(1 << 3) /* 0: no change on DCD_ since last read */
-#define UART_MSR_CTS	(1 << 4) /* 0: CTS_ pin is high */
-#define UART_MSR_DSR	(1 << 5) /* 0: DSR_ pin is high */
-#define UART_MSR_RI	(1 << 6) /* 0: RI_ pin is high */
-#define UART_MSR_DCD	(1 << 7) /* 0: DCD_ pin is high */
-
-/*
- * Define macros for SIRCR
- * Slow IrDA Control Register
- */
-#define SIRCR_TSIRE (1 << 0) /* 0: TX is in UART mode 1: IrDA mode */
-#define SIRCR_RSIRE (1 << 1) /* 0: RX is in UART mode 1: IrDA mode */
-#define SIRCR_TPWS  (1 << 2) /* 0: transmit 0 pulse width is 3/16 of bit length
-				1: 0 pulse width is 1.6us for 115.2Kbps */
-#define SIRCR_TXPL  (1 << 3) /* 0: encoder generates a positive pulse for 0 */
-#define SIRCR_RXPL  (1 << 4) /* 0: decoder interprets positive pulse as 0 */
-
-/* MSC Clock and Control Register (MSC_STRPCL) */
-#define MSC_STRPCL_EXIT_MULTIPLE	(1 << 7)
-#define MSC_STRPCL_EXIT_TRANSFER	(1 << 6)
-#define MSC_STRPCL_START_READWAIT	(1 << 5)
-#define MSC_STRPCL_STOP_READWAIT	(1 << 4)
-#define MSC_STRPCL_RESET		(1 << 3)
-#define MSC_STRPCL_START_OP		(1 << 2)
-#define MSC_STRPCL_CLOCK_CONTROL_BIT	0
-#define MSC_STRPCL_CLOCK_CONTROL_MASK	(0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_STOP	(0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-#define MSC_STRPCL_CLOCK_CONTROL_START	(0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)
-
-/* MSC Status Register (MSC_STAT) */
-#define MSC_STAT_IS_RESETTING		(1 << 15)
-#define MSC_STAT_SDIO_INT_ACTIVE	(1 << 14)
-#define MSC_STAT_PRG_DONE		(1 << 13)
-#define MSC_STAT_DATA_TRAN_DONE		(1 << 12)
-#define MSC_STAT_END_CMD_RES		(1 << 11)
-#define MSC_STAT_DATA_FIFO_AFULL	(1 << 10)
-#define MSC_STAT_IS_READWAIT		(1 << 9)
-#define MSC_STAT_CLK_EN			(1 << 8)
-#define MSC_STAT_DATA_FIFO_FULL		(1 << 7)
-#define MSC_STAT_DATA_FIFO_EMPTY	(1 << 6)
-#define MSC_STAT_CRC_RES_ERR		(1 << 5)
-#define MSC_STAT_CRC_READ_ERROR		(1 << 4)
-#define MSC_STAT_CRC_WRITE_ERROR_BIT	2
-#define MSC_STAT_CRC_WRITE_ERROR_MASK	(0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No error on transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR_NO	(0 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* Card observed erroneous transmission of data */
-  #define MSC_STAT_CRC_WRITE_ERROR	(1 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-/* No CRC status is sent back */
-  #define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)
-#define MSC_STAT_TIME_OUT_RES		(1 << 1)
-#define MSC_STAT_TIME_OUT_READ		(1 << 0)
-
-/* MSC Bus Clock Control Register (MSC_CLKRT) */
-#define MSC_CLKRT_CLK_RATE_BIT		0
-#define MSC_CLKRT_CLK_RATE_MASK		(0x7 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_1  (0x0 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_2  (0x1 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_4  (0x2 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_8  (0x3 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_16  (0x4 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_32  (0x5 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_64  (0x6 << MSC_CLKRT_CLK_RATE_BIT)
-  #define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)
-
-/* MSC Command Sequence Control Register (MSC_CMDAT) */
-#define MSC_CMDAT_IO_ABORT	(1 << 11)
-#define MSC_CMDAT_BUS_WIDTH_BIT	9
-#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT)
-#define MSC_CMDAT_DMA_EN	(1 << 8)
-#define MSC_CMDAT_INIT		(1 << 7)
-#define MSC_CMDAT_BUSY		(1 << 6)
-#define MSC_CMDAT_STREAM_BLOCK	(1 << 5)
-#define MSC_CMDAT_WRITE		(1 << 4)
-#define MSC_CMDAT_READ		(0 << 4)
-#define MSC_CMDAT_DATA_EN	(1 << 3)
-#define MSC_CMDAT_RESPONSE_BIT	0
-#define MSC_CMDAT_RESPONSE_MASK	(0x7 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_NONE	(0x0 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R1	(0x1 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R2	(0x2 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R3	(0x3 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R4	(0x4 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R5	(0x5 << MSC_CMDAT_RESPONSE_BIT)
-#define MSC_CMDAT_RESPONSE_R6	(0x6 << MSC_CMDAT_RESPONSE_BIT)
-
-/* MSC Interrupts Mask Register (MSC_IMASK) */
-#define MSC_IMASK_SDIO			(1 << 7)
-#define MSC_IMASK_TXFIFO_WR_REQ		(1 << 6)
-#define MSC_IMASK_RXFIFO_RD_REQ		(1 << 5)
-#define MSC_IMASK_END_CMD_RES		(1 << 2)
-#define MSC_IMASK_PRG_DONE		(1 << 1)
-#define MSC_IMASK_DATA_TRAN_DONE	(1 << 0)
-
-#ifndef __ASSEMBLY__
-/* INTC (Interrupt Controller) */
-struct jz4740_intc {
-	uint32_t isr;		/* interrupt source register */
-	uint32_t imr;		/* interrupt mask register */
-	uint32_t imsr;		/* interrupt mask set register */
-	uint32_t imcr;		/* interrupt mask clear register */
-	uint32_t ipr;		/* interrupt pending register */
-};
-
-/* RTC */
-struct jz4740_rtc {
-	uint32_t rcr;		/* rtc control register */
-	uint32_t rsr;		/* rtc second register */
-	uint32_t rsar;		/* rtc second alarm register */
-	uint32_t rgr;		/* rtc regulator register */
-	uint32_t hcr;		/* hibernate control register */
-	uint32_t hwfcr;		/* hibernate wakeup filter counter reg */
-	uint32_t hrcr;		/* hibernate reset counter reg */
-	uint32_t hwcr;		/* hibernate wakeup control register */
-	uint32_t hwrsr;		/* hibernate wakeup status reg */
-	uint32_t hspr;		/* scratch pattern register */
-};
-
-/* CPM (Clock reset and Power control Management) */
-struct jz4740_cpm {
-	uint32_t cpccr; /* 0x00 clock control reg */
-	uint32_t lcr;	/* 0x04 low power control reg */
-	uint32_t rsr;	/* 0x08 reset status reg */
-	uint32_t pad00;
-	uint32_t cppcr; /* 0x10 pll control reg */
-	uint32_t pad01[3];
-	uint32_t clkgr;	/* 0x20 clock gate reg */
-	uint32_t scr;	/* 0x24 sleep control reg */
-	uint32_t pad02[14];
-	uint32_t i2scd; /* 0x60 I2S device clock divider reg */
-	uint32_t lpcdr; /* 0x64 LCD pix clock divider reg */
-	uint32_t msccdr; /* 0x68 MSC device clock divider reg */
-	uint32_t uhccdr; /* 0x6C UHC 48M clock divider reg */
-	uint32_t uhcts; /* 0x70 UHC PHY test point reg */
-	uint32_t ssicd; /* 0x74 SSI clock divider reg */
-};
-
-/* TCU (Timer Counter Unit) */
-struct jz4740_tcu {
-	uint32_t pad00[4];
-	uint32_t ter;	/* 0x10  Timer Counter Enable Register */
-	uint32_t tesr;	/* 0x14  Timer Counter Enable Set Register */
-	uint32_t tecr;	/* 0x18  Timer Counter Enable Clear Register */
-	uint32_t tsr;	/* 0x1C  Timer Stop Register */
-	uint32_t tfr;	/* 0x20  Timer Flag Register */
-	uint32_t tfsr;	/* 0x24  Timer Flag Set Register */
-	uint32_t tfcr;	/* 0x28  Timer Flag Clear Register */
-	uint32_t tssr;	/* 0x2C  Timer Stop Set Register */
-	uint32_t tmr;	/* 0x30  Timer Mask Register */
-	uint32_t tmsr;	/* 0x34  Timer Mask Set Register */
-	uint32_t tmcr;	/* 0x38  Timer Mask Clear Register */
-	uint32_t tscr;	/* 0x3C  Timer Stop Clear Register */
-	uint32_t tdfr0;	/* 0x40  Timer Data Full Register */
-	uint32_t tdhr0;	/* 0x44  Timer Data Half Register */
-	uint32_t tcnt0;	/* 0x48  Timer Counter Register */
-	uint32_t tcsr0;	/* 0x4C  Timer Control Register */
-	uint32_t tdfr1;	/* 0x50 */
-	uint32_t tdhr1;	/* 0x54 */
-	uint32_t tcnt1;	/* 0x58 */
-	uint32_t tcsr1;	/* 0x5C */
-	uint32_t tdfr2;	/* 0x60 */
-	uint32_t tdhr2;	/* 0x64 */
-	uint32_t tcnt2;	/* 0x68 */
-	uint32_t tcsr2;	/* 0x6C */
-	uint32_t tdfr3;	/* 0x70 */
-	uint32_t tdhr3;	/* 0x74 */
-	uint32_t tcnt3;	/* 0x78 */
-	uint32_t tcsr3;	/* 0x7C */
-	uint32_t tdfr4;	/* 0x80 */
-	uint32_t tdhr4;	/* 0x84 */
-	uint32_t tcnt4;	/* 0x88 */
-	uint32_t tcsr4;	/* 0x8C */
-	uint32_t tdfr5;	/* 0x90 */
-	uint32_t tdhr5;	/* 0x94 */
-	uint32_t tcnt5;	/* 0x98 */
-	uint32_t tcsr5;	/* 0x9C */
-};
-
-/* WDT (WatchDog Timer) */
-struct jz4740_wdt {
-	uint16_t tdr; /* 0x00 watchdog timer data reg*/
-	uint16_t pad00;
-	uint8_t tcer; /* 0x04 watchdog counter enable reg*/
-	uint8_t pad01[3];
-	uint16_t tcnt; /* 0x08 watchdog timer counter*/
-	uint16_t pad02;
-	uint16_t tcsr; /* 0x0C watchdog timer control reg*/
-	uint16_t pad03;
-};
-
-struct jz4740_uart {
-	uint8_t rbr_thr_dllr;
-		/* 0x00 R  8b receive buffer reg */
-		/* 0x00 W  8b transmit hold reg */
-		/* 0x00 RW 8b divisor latch low reg */
-	uint8_t pad00[3];
-	uint8_t dlhr_ier;
-		/* 0x04 RW 8b divisor latch high reg */
-		/* 0x04 RW 8b interrupt enable reg */
-	uint8_t pad01[3];
-	uint8_t iir_fcr;
-		/* 0x08 R  8b interrupt identification reg */
-		/* 0x08 W  8b FIFO control reg */
-	uint8_t pad02[3];
-	uint8_t lcr;	/* 0x0C RW 8b Line control reg */
-	uint8_t pad03[3];
-	uint8_t mcr;	/* 0x10 RW 8b modem control reg */
-	uint8_t pad04[3];
-	uint8_t lsr;	/* 0x14 R  8b line status reg */
-	uint8_t pad05[3];
-	uint8_t msr;	/* 0x18 R  8b modem status reg */
-	uint8_t pad06[3];
-	uint8_t spr;	/* 0x1C RW 8b scratch pad reg */
-	uint8_t pad07[3];
-	uint8_t isr;	/* 0x20 RW 8b infrared selection reg */
-	uint8_t pad08[3];
-	uint8_t umr;	/* 0x24 RW 8b */
-};
-
-/* MSC */
-struct jz4740_msc {
-	uint16_t strpcl;/* 0x00 */
-	uint32_t stat;	/* 0x04 */
-	uint16_t clkrt;	/* 0x08 */
-	uint32_t cmdat;	/* 0x0C */
-	uint16_t resto;	/* 0x10 */
-	uint16_t rdto;	/* 0x14 */
-	uint16_t blklen;/* 0x18 */
-	uint16_t nob;	/* 0x1C */
-	uint16_t snob;	/* 0x20 */
-	uint16_t imask;	/* 0x24 */
-	uint16_t ireg;	/* 0x28 */
-	uint8_t  cmd;	/* 0x2C */
-	uint32_t arg;	/* 0x30 */
-	uint16_t res;	/* 0x34 */
-	uint32_t rxfifo;/* 0x38 */
-	uint32_t txfifo;/* 0x3C */
-};
-
-/* External Memory Controller */
-struct jz4740_emc {
-	uint32_t bcr; /* 0x00 BCR */
-	uint32_t pad00[3];
-	uint32_t smcr[5];
-		/* x10 Static Memory Control Register 0 */
-		/* x14 Static Memory Control Register 1 */
-		/* x18 Static Memory Control Register 2 */
-		/* x1c Static Memory Control Register 3 */
-		/* x20 Static Memory Control Register 4 */
-	uint32_t pad01[3];
-	uint32_t sacr[5];
-		/* x30 Static Memory Bank 0 Addr Config Reg */
-		/* x34 Static Memory Bank 1 Addr Config Reg */
-		/* x38 Static Memory Bank 2 Addr Config Reg */
-		/* x3c Static Memory Bank 3 Addr Config Reg */
-		/* x40 Static Memory Bank 4 Addr Config Reg */
-	uint32_t pad02[3];
-	uint32_t nfcsr; /* x050 NAND Flash Control/Status Register */
-
-	uint32_t pad03[11];
-	uint32_t dmcr; /* x80 DRAM Control Register */
-	uint16_t rtcsr; /* x84 Refresh Time Control/Status Register */
-	uint16_t pad04;
-	uint16_t rtcnt; /* x88 Refresh Timer Counter */
-	uint16_t pad05;
-	uint16_t rtcor; /* x8c Refresh Time Constant Register */
-	uint16_t pad06;
-	uint32_t dmar0; /* x90 SDRAM Bank 0 Addr Config Register */
-	uint32_t pad07[27];
-	uint32_t nfecr; /* x100 NAND Flash ECC Control Register */
-	uint32_t nfecc; /* x104 NAND Flash ECC Data Register */
-	uint8_t nfpar[12];
-		/* x108 NAND Flash RS Parity 0 Register */
-		/* x10c NAND Flash RS Parity 1 Register */
-		/* x110 NAND Flash RS Parity 2 Register */
-	uint32_t nfints; /* x114 NAND Flash Interrupt Status Register */
-	uint32_t nfinte; /* x118 NAND Flash Interrupt Enable Register */
-	uint32_t nferr[4];
-		/* x11c NAND Flash RS Error Report 0 Register */
-		/* x120 NAND Flash RS Error Report 1 Register */
-		/* x124 NAND Flash RS Error Report 2 Register */
-		/* x128 NAND Flash RS Error Report 3 Register */
-};
-
-#define __gpio_as_nand()			\
-do {						\
-	writel(0x02018000, GPIO_PXFUNS(1));	\
-	writel(0x02018000, GPIO_PXSELC(1));	\
-	writel(0x02018000, GPIO_PXPES(1));	\
-	writel(0x30000000, GPIO_PXFUNS(2));	\
-	writel(0x30000000, GPIO_PXSELC(2));	\
-	writel(0x30000000, GPIO_PXPES(2));	\
-	writel(0x40000000, GPIO_PXFUNC(2));	\
-	writel(0x40000000, GPIO_PXSELC(2));	\
-	writel(0x40000000, GPIO_PXDIRC(2));	\
-	writel(0x40000000, GPIO_PXPES(2));	\
-	writel(0x00400000, GPIO_PXFUNS(1));	\
-	writel(0x00400000, GPIO_PXSELC(1));	\
-} while (0)
-
-#define __gpio_as_sdram_16bit_4720()		\
-do {						\
-	writel(0x5442bfaa, GPIO_PXFUNS(0));	\
-	writel(0x5442bfaa, GPIO_PXSELC(0));	\
-	writel(0x5442bfaa, GPIO_PXPES(0));	\
-	writel(0x81f9ffff, GPIO_PXFUNS(1));	\
-	writel(0x81f9ffff, GPIO_PXSELC(1));	\
-	writel(0x81f9ffff, GPIO_PXPES(1));	\
-	writel(0x01000000, GPIO_PXFUNS(2));	\
-	writel(0x01000000, GPIO_PXSELC(2));	\
-	writel(0x01000000, GPIO_PXPES(2));	\
-} while (0)
-
-#define __gpio_as_lcd_18bit()			\
-do {						\
-	writel(0x003fffff, GPIO_PXFUNS(2));	\
-	writel(0x003fffff, GPIO_PXSELC(2));	\
-	writel(0x003fffff, GPIO_PXPES(2));	\
-} while (0)
-
-/* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 */
-#define __gpio_as_msc()				\
-do {						\
-	writel(0x00003f00, GPIO_PXFUNS(3));	\
-	writel(0x00003f00, GPIO_PXSELC(3));	\
-	writel(0x00003f00, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_get_port(p)	(readl(GPIO_PXPIN(p)))
-
-#define __gpio_disable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXPES(p));	\
-} while (0)
-
-#define __gpio_enable_pull(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel(1 << (o), GPIO_PXPEC(p));	\
-} while (0)
-
-#define __gpio_port_as_output(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRS(p));	\
-} while (0)
-
-#define __gpio_port_as_input(p, o)		\
-do {						\
-	writel(1 << (o), GPIO_PXFUNC(p));	\
-	writel(1 << (o), GPIO_PXSELC(p));	\
-	writel(1 << (o), GPIO_PXDIRC(p));	\
-} while (0)
-
-#define __gpio_as_output(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_output(p, o);		\
-} while (0)
-
-#define __gpio_as_input(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	__gpio_port_as_input(p, o);		\
-} while (0)
-
-#define __gpio_set_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATS(p));	\
-} while (0)
-
-#define __gpio_clear_pin(n)			\
-do {						\
-	unsigned int p, o;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	writel((1 << o), GPIO_PXDATC(p));	\
-} while (0)
-
-#define __gpio_get_pin(n)			\
-({						\
-	unsigned int p, o, v;			\
-	p = (n) / 32;				\
-	o = (n) % 32;				\
-	if (__gpio_get_port(p) & (1 << o))	\
-		v = 1;				\
-	else					\
-		v = 0;				\
-	v;					\
-})
-
-#define __gpio_as_uart0()			\
-do {						\
-	writel(0x06000000, GPIO_PXFUNS(3));	\
-	writel(0x06000000, GPIO_PXSELS(3));	\
-	writel(0x06000000, GPIO_PXPES(3));	\
-} while (0)
-
-#define __gpio_jtag_to_uart0()			\
-do {						\
-	writel(0x80000000, GPIO_PXSELS(2));	\
-} while (0)
-
-/* Clock Control Register */
-#define __cpm_get_pllm()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLM_MASK)	\
-	 >> CPM_CPPCR_PLLM_BIT)
-#define __cpm_get_plln()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLN_MASK)	\
-	 >> CPM_CPPCR_PLLN_BIT)
-#define __cpm_get_pllod()					\
-	((readl(JZ4740_CPM_BASE + 0x10) & CPM_CPPCR_PLLOD_MASK)	\
-	 >> CPM_CPPCR_PLLOD_BIT)
-#define __cpm_get_hdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_HDIV_MASK)	\
-	 >> CPM_CPCCR_HDIV_BIT)
-#define __cpm_get_pdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_PDIV_MASK)	\
-	 >> CPM_CPCCR_PDIV_BIT)
-#define __cpm_get_cdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_CDIV_MASK)	\
-	 >> CPM_CPCCR_CDIV_BIT)
-#define __cpm_get_mdiv()					\
-	((readl(JZ4740_CPM_BASE + 0x00) & CPM_CPCCR_MDIV_MASK)	\
-	 >> CPM_CPCCR_MDIV_BIT)
-
-static inline unsigned int __cpm_get_pllout(void)
-{
-	uint32_t m, n, no, pllout;
-	uint32_t od[4] = {1, 2, 2, 4};
-
-	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
-	uint32_t cppcr = readl(&cpm->cppcr);
-
-	if ((cppcr & CPM_CPPCR_PLLEN) && !(cppcr & CPM_CPPCR_PLLBP)) {
-		m = __cpm_get_pllm() + 2;
-		n = __cpm_get_plln() + 2;
-		no = od[__cpm_get_pllod()];
-		pllout = (CONFIG_SYS_EXTAL / (n * no)) * m;
-	} else
-		pllout = CONFIG_SYS_EXTAL;
-
-	return pllout;
-}
-
-extern void pll_init(void);
-extern void sdram_init(void);
-extern void calc_clocks(void);
-extern void rtc_init(void);
-
-#endif	/* !__ASSEMBLY__ */
-#endif	/* __JZ4740_H__ */
diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h
index a5b2fc08f8..1f527bb8ec 100644
--- a/arch/mips/include/asm/u-boot-mips.h
+++ b/arch/mips/include/asm/u-boot-mips.h
@@ -1,23 +1,8 @@
 /*
  * SPDX-License-Identifier:	GPL-2.0+
- *
- * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  */
 
-static inline unsigned long bss_start(void)
-{
-	extern char __bss_start[];
-	return (unsigned long) &__bss_start;
-}
+#ifndef _U_BOOT_MIPS_H_
+#define _U_BOOT_MIPS_H_
 
-static inline unsigned long bss_end(void)
-{
-	extern ulong __bss_end;
-	return (unsigned long) &__bss_end;
-}
-
-static inline unsigned long image_copy_end(void)
-{
-	extern char __image_copy_end[];
-	return (unsigned long) &__image_copy_end;
-}
+#endif /* _U_BOOT_MIPS_H_ */
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 4909a2a5c4..af03e8d5be 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -15,25 +15,9 @@
 #ifndef _U_BOOT_H_
 #define _U_BOOT_H_	1
 
-#ifdef CONFIG_SYS_GENERIC_BOARD
-
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
 
-#else /* !CONFIG_SYS_GENERIC_BOARD */
-
-typedef struct bd_info {
-	unsigned long	bi_arch_number;	/* unique id for this board */
-	unsigned long	bi_boot_params;	/* where this board expects params */
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size  of FLASH memory */
-	unsigned long	bi_flashoffset;	/* reserved area for startup monitor */
-} bd_t;
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
-
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_MIPS
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005b67..5f520c069f 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,23 +9,13 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-
 static inline unsigned long icache_line_size(void)
 {
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
-
-static inline unsigned long dcache_line_size(void)
-{
-	return CONFIG_SYS_CACHELINE_SIZE;
-}
+	unsigned long conf1, il;
 
-#else /* !CONFIG_SYS_CACHELINE_SIZE */
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_ICACHE_LINE_SIZE;
 
-static inline unsigned long icache_line_size(void)
-{
-	unsigned long conf1, il;
 	conf1 = read_c0_config1();
 	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
 	if (!il)
@@ -36,6 +26,10 @@ static inline unsigned long icache_line_size(void)
 static inline unsigned long dcache_line_size(void)
 {
 	unsigned long conf1, dl;
+
+	if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
+		return CONFIG_SYS_DCACHE_LINE_SIZE;
+
 	conf1 = read_c0_config1();
 	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
 	if (!dl)
@@ -43,84 +37,59 @@ static inline unsigned long dcache_line_size(void)
 	return 2 << dl;
 }
 
-#endif /* !CONFIG_SYS_CACHELINE_SIZE */
+#define cache_loop(start, end, lsize, ops...) do {			\
+	const void *addr = (const void *)(start & ~(lsize - 1));	\
+	const void *aend = (const void *)((end - 1) & ~(lsize - 1));	\
+	const unsigned int cache_ops[] = { ops };			\
+	unsigned int i;							\
+									\
+	for (; addr <= aend; addr += lsize) {				\
+		for (i = 0; i < ARRAY_SIZE(cache_ops); i++)		\
+			mips_cache(cache_ops[i], addr);			\
+	}								\
+} while (0)
 
 void flush_cache(ulong start_addr, ulong size)
 {
 	unsigned long ilsize = icache_line_size();
 	unsigned long dlsize = dcache_line_size();
-	const void *addr, *aend;
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (size == 0)
 		return;
 
-	addr = (const void *)(start_addr & ~(dlsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
-
 	if (ilsize == dlsize) {
 		/* flush I-cache & D-cache simultaneously */
-		while (1) {
-			mips_cache(HIT_WRITEBACK_INV_D, addr);
-			mips_cache(HIT_INVALIDATE_I, addr);
-			if (addr == aend)
-				break;
-			addr += dlsize;
-		}
+		cache_loop(start_addr, start_addr + size, ilsize,
+			   HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
 		return;
 	}
 
 	/* flush D-cache */
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += dlsize;
-	}
+	cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
 
 	/* flush I-cache */
-	addr = (const void *)(start_addr & ~(ilsize - 1));
-	aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
-	while (1) {
-		mips_cache(HIT_INVALIDATE_I, addr);
-		if (addr == aend)
-			break;
-		addr += ilsize;
-	}
+	cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
 }
 
 void flush_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_WRITEBACK_INV_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
-	const void *addr = (const void *)(start_addr & ~(lsize - 1));
-	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
 	/* aend will be miscalculated when size is zero, so we return here */
 	if (start_addr == stop)
 		return;
 
-	while (1) {
-		mips_cache(HIT_INVALIDATE_D, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}
+	cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
 }
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3af52..bc8ab27b58 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,16 +99,16 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t2, CONFIG_SYS_ICACHE_SIZE
-	li	t8, CONFIG_SYS_CACHELINE_SIZE
+	li	t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
 	l1_info	t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 	li	t3, CONFIG_SYS_DCACHE_SIZE
-	li	t9, CONFIG_SYS_CACHELINE_SIZE
+	li	t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
 	l1_info	t3, t9, MIPS_CONF1_DA_SHF
 #endif
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
 	/* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
 	li	v0, CONFIG_SYS_ICACHE_SIZE
 #else
diff --git a/arch/mips/mach-ath79/ar933x/clk.c b/arch/mips/mach-ath79/ar933x/clk.c
index 9fcd4961f5..6d98efc480 100644
--- a/arch/mips/mach-ath79/ar933x/clk.c
+++ b/arch/mips/mach-ath79/ar933x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,7 +17,7 @@ static u32 ar933x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR933X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/ar933x/ddr.c b/arch/mips/mach-ath79/ar933x/ddr.c
index 91452bcc53..2a25e23869 100644
--- a/arch/mips/mach-ath79/ar933x/ddr.c
+++ b/arch/mips/mach-ath79/ar933x/ddr.c
@@ -10,7 +10,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -114,7 +114,7 @@ void ddr_init(void)
 	writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
 	writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR933X_BOOTSTRAP_DDR2) {
 		/* AHB maximum timeout */
 		writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
@@ -268,6 +268,8 @@ void ddr_tap_tuning(void)
 	dir = 1;
 	tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
 	val = tap;
+	upper = tap;
+	lower = tap;
 	while (!done) {
 		err = 0;
 
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c
index 9c65184e7a..9b41d3de60 100644
--- a/arch/mips/mach-ath79/ar934x/clk.c
+++ b/arch/mips/mach-ath79/ar934x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 #include <wait_bit.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -119,7 +119,7 @@ void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
 	writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
 
 	/* Test for 40MHz XTAL */
-	reg = get_bootstrap();
+	reg = ath79_get_bootstrap();
 	if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
 		xtal_40 = 1;
 		cpu_srif = 0x41c00000;
@@ -214,7 +214,7 @@ static u32 ar934x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & AR934X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c
index 4621d5845c..2ba1efa3e3 100644
--- a/arch/mips/mach-ath79/ar934x/ddr.c
+++ b/arch/mips/mach-ath79/ar934x/ddr.c
@@ -11,7 +11,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,7 +45,7 @@ void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
 	ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 			       MAP_NOCACHE);
 
-	reg = get_bootstrap();
+	reg = ath79_get_bootstrap();
 	if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) {	/* DDR */
 		if (reg & AR934X_BOOTSTRAP_DDR1) {	/* DDR 1 */
 			memtype = AR934X_DDR1;
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
index a8e51cb4cf..7b4852416b 100644
--- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
+++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h
@@ -331,6 +331,7 @@
 #define AR933X_PLL_CPU_CONFIG_REG			0x00
 #define AR933X_PLL_CLK_CTRL_REG				0x08
 #define AR933X_PLL_DITHER_FRAC_REG			0x10
+#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG		0x24
 
 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT		10
 #define AR933X_PLL_CPU_CONFIG_NINT_MASK			0x3f
@@ -660,6 +661,7 @@
 
 #define AR933X_RESET_GE1_MDIO				BIT(23)
 #define AR933X_RESET_GE0_MDIO				BIT(22)
+#define AR933X_RESET_ETH_SWITCH_ANALOG			BIT(14)
 #define AR933X_RESET_GE1_MAC				BIT(13)
 #define AR933X_RESET_WMAC				BIT(11)
 #define AR933X_RESET_GE0_MAC				BIT(9)
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h
index 17af08223f..582c0282e5 100644
--- a/arch/mips/mach-ath79/include/mach/ath79.h
+++ b/arch/mips/mach-ath79/include/mach/ath79.h
@@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void)
 	return soc_is_tp9343() || soc_is_qca9561();
 }
 
+u32 ath79_get_bootstrap(void);
 int ath79_eth_reset(void);
 int ath79_usb_reset(void);
 
diff --git a/arch/mips/mach-ath79/include/mach/reset.h b/arch/mips/mach-ath79/include/mach/reset.h
deleted file mode 100644
index c383bfe608..0000000000
--- a/arch/mips/mach-ath79/include/mach/reset.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_MACH_RESET_H
-#define __ASM_MACH_RESET_H
-
-#include <linux/types.h>
-
-u32 get_bootstrap(void);
-
-#endif /* __ASM_MACH_RESET_H */
diff --git a/arch/mips/mach-ath79/qca953x/clk.c b/arch/mips/mach-ath79/qca953x/clk.c
index ef0a28e505..533356c6a1 100644
--- a/arch/mips/mach-ath79/qca953x/clk.c
+++ b/arch/mips/mach-ath79/qca953x/clk.c
@@ -9,7 +9,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -17,7 +17,7 @@ static u32 qca953x_get_xtal(void)
 {
 	u32 val;
 
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
 		return 40000000;
 	else
diff --git a/arch/mips/mach-ath79/qca953x/ddr.c b/arch/mips/mach-ath79/qca953x/ddr.c
index ac0130cff0..c6049d8958 100644
--- a/arch/mips/mach-ath79/qca953x/ddr.c
+++ b/arch/mips/mach-ath79/qca953x/ddr.c
@@ -10,7 +10,7 @@
 #include <asm/addrspace.h>
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
-#include <mach/reset.h>
+#include <mach/ath79.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -226,7 +226,7 @@ void ddr_init(void)
 
 	regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
 			   MAP_NOCACHE);
-	val = get_bootstrap();
+	val = ath79_get_bootstrap();
 	if (val & QCA953X_BOOTSTRAP_DDR1) {
 		writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF);
 		udelay(10);
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 188eccb9bf..073a179baf 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -45,7 +45,7 @@ void _machine_restart(void)
 		/* NOP */;
 }
 
-u32 get_bootstrap(void)
+u32 ath79_get_bootstrap(void)
 {
 	void __iomem *base;
 	u32 reg = 0;
@@ -81,14 +81,15 @@ static int eth_init_ar933x(void)
 					  MAP_NOCACHE);
 	const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO |
 			 AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO |
-			 AR933X_RESET_ETH_SWITCH;
+			 AR933X_RESET_ETH_SWITCH |
+			 AR933X_RESET_ETH_SWITCH_ANALOG;
 
 	/* Clear MDIO slave EN bit. */
 	clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17));
 	mdelay(10);
 
 	/* Get Atheros S26 PHY out of reset. */
-	clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG,
+	clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG,
 			0x1f, 0x10);
 	mdelay(10);
 
@@ -135,6 +136,23 @@ static int eth_init_ar934x(void)
 	return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_eth_reset(void)
 {
 	/*
@@ -145,6 +163,8 @@ int ath79_eth_reset(void)
 		return eth_init_ar933x();
 	if (soc_is_ar934x())
 		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
 	return -EINVAL;
 }
@@ -184,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
 	return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_usb_reset(void)
 {
 	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -203,6 +252,8 @@ int ath79_usb_reset(void)
 		return usb_reset_ar933x(reset_regs);
 	if (soc_is_ar934x())
 		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
 	return -EINVAL;
 }
diff --git a/arch/nios2/cpu/fdt.c b/arch/nios2/cpu/fdt.c
index 79f72aa12f..a44f51a7f2 100644
--- a/arch/nios2/cpu/fdt.c
+++ b/arch/nios2/cpu/fdt.c
@@ -12,7 +12,7 @@
 
 #include <common.h>
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
 
@@ -35,4 +35,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 */
 	fdt_fixup_ethernet(blob);
 }
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/arch/openrisc/lib/Makefile b/arch/openrisc/lib/Makefile
index dfa72d915f..3a2f6ec243 100644
--- a/arch/openrisc/lib/Makefile
+++ b/arch/openrisc/lib/Makefile
@@ -5,6 +5,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= board.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= timer.o
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
deleted file mode 100644
index b7fbd2f125..0000000000
--- a/arch/openrisc/lib/board.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2011
- * Julius Baxter, julius@opencores.org
- *
- * (C) Copyright 2003, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * (C) Copyright 2000-2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <console.h>
-#include <stdio_dev.h>
-#include <watchdog.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <net.h>
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-#endif
-#ifdef CONFIG_CMD_NAND
-#include <nand.h>	/* cannot even include nand.h if it isnt configured */
-#endif
-
-#include <timestamp.h>
-#include <version.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependend #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-
-extern int cache_init(void);
-
-/*
- * Initialization sequence
- */
-static int (* const init_sequence[])(void) = {
-	cache_init,
-	timer_init,		/* initialize timer */
-	env_init,
-	serial_init,
-	console_init_f,
-	display_options,
-	checkcpu,
-	checkboard,
-};
-
-
-/***********************************************************************/
-void board_init(void)
-{
-	bd_t *bd;
-	int i;
-
-	gd = (gd_t *)CONFIG_SYS_GBL_DATA_ADDR;
-
-	memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-
-	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
-	gd->baudrate = CONFIG_BAUDRATE;
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
-	bd = gd->bd;
-	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
-	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
-	bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE;
-#endif
-
-	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
-		WATCHDOG_RESET();
-		if (init_sequence[i]())
-			hang();
-	}
-
-	WATCHDOG_RESET();
-
-	/* The Malloc area is immediately below the monitor copy in RAM */
-	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-
-#ifndef CONFIG_SYS_NO_FLASH
-	WATCHDOG_RESET();
-	bd->bi_flashsize = flash_init();
-#endif
-
-#ifdef CONFIG_CMD_NAND
-	puts("NAND:  ");
-	nand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
-	puts("MMC:   ");
-	mmc_initialize(bd);
-#endif
-
-	WATCHDOG_RESET();
-	env_relocate();
-
-	WATCHDOG_RESET();
-	stdio_init();
-	jumptable_init();
-	console_init_r();
-
-	WATCHDOG_RESET();
-	interrupt_init();
-
-#if defined(CONFIG_BOARD_LATE_INIT)
-	board_late_init();
-#endif
-
-#if defined(CONFIG_CMD_NET)
-	puts("NET:   ");
-	eth_initialize();
-#endif
-
-	/* main_loop */
-	for (;;) {
-		WATCHDOG_RESET();
-		main_loop();
-	}
-}
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
index 6451ea9a4a..68c5f8a27b 100644
--- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -70,7 +70,7 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config,
 		mddrc_config = &default_mddrc_config;
 	if (dram_init_seq == NULL) {
 		dram_init_seq = default_init_seq;
-		seq_sz = sizeof(default_init_seq)/sizeof(u32);
+		seq_sz = ARRAY_SIZE(default_init_seq);
 	}
 
 	/* Initialize IO Control */
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
index 7a463b5e09..84fabbd473 100644
--- a/arch/powerpc/cpu/mpc5xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -96,7 +96,7 @@ unsigned long get_tbclk (void)
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
@@ -117,7 +117,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
 	do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
 #endif
-#if defined(CONFIG_OF_IDE_FIXUP)
+#ifdef CONFIG_OF_IDE_FIXUP
 	if (!ide_device_present(0)) {
 		/* NO CF card detected -> delete ata node in DTS */
 		int nodeoffset = 0;
@@ -132,10 +132,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 		}
 	}
 
-#endif
+#endif /* CONFIG_OF_IDE_FIXUP */
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #ifdef CONFIG_MPC5xxx_FEC
 /* Default initializations for FEC controllers.  To override,
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
index 54793f0523..b4c5543eb5 100644
--- a/arch/powerpc/cpu/mpc5xxx/start.S
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -83,8 +83,7 @@ _start:
 	 * This function is called when the platform is build with SPL
 	 * support from the main (full-blown) U-Boot. And the GD needs
 	 * to get cleared (again) so that the following generic
-	 * board support code, defined via CONFIG_SYS_GENERIC_BOARD,
-	 * initializes all variables correctly.
+	 * board support code initializes all variables correctly.
 	 */
 	mr	r3, r2		/* parameter 1:	 GD pointer		*/
 	li	r4,0		/* parameter 2:	 value to fill		*/
diff --git a/arch/powerpc/cpu/mpc8260/cpu.c b/arch/powerpc/cpu/mpc8260/cpu.c
index 6eed6f53a3..9f2be3cb22 100644
--- a/arch/powerpc/cpu/mpc8260/cpu.c
+++ b/arch/powerpc/cpu/mpc8260/cpu.c
@@ -284,7 +284,7 @@ void watchdog_reset (void)
 #endif /* CONFIG_WATCHDOG */
 
 /* ------------------------------------------------------------------------- */
-#if defined(CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 void ft_cpu_setup (void *blob, bd_t *bd)
 {
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@@ -303,7 +303,7 @@ void ft_cpu_setup (void *blob, bd_t *bd)
 		"clock-frequency", bd->bi_intfreq, 1);
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 }
-#endif /* CONFIG_OF_LIBFDT */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 /*
  * Initializes on-chip ethernet controllers.
diff --git a/arch/powerpc/cpu/mpc8260/cpu_init.c b/arch/powerpc/cpu/mpc8260/cpu_init.c
index a9bb5adeb2..55130f7831 100644
--- a/arch/powerpc/cpu/mpc8260/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8260/cpu_init.c
@@ -253,7 +253,7 @@ int prt_8260_rsr (void)
 		RSR_ESRS, "External Soft"}, {
 		RSR_EHRS, "External Hard"}
 	};
-	static int n = sizeof bits / sizeof bits[0];
+	static int n = ARRAY_SIZE(bits);
 	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index 9bb395e6a2..a11ad1e9d0 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -362,7 +362,7 @@ int fec_initialize(bd_t *bis)
 	struct eth_device* dev;
 	int i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 	{
 		dev = (struct eth_device*) malloc(sizeof *dev);
 		memset(dev, 0, sizeof *dev);
@@ -432,7 +432,7 @@ static elbt_prdesc rxeacc_descs[] = {
 	{ offsetof(elbt_rxeacc, badlen),	"Bad Frame Length"	},
 	{ offsetof(elbt_rxeacc, badbit),	"Data Compare Errors"	},
 };
-static int rxeacc_ndesc = sizeof (rxeacc_descs) / sizeof (rxeacc_descs[0]);
+static int rxeacc_ndesc = ARRAY_SIZE(rxeacc_descs);
 
 typedef
 	struct {
@@ -449,7 +449,7 @@ static elbt_prdesc txeacc_descs[] = {
 	{ offsetof(elbt_txeacc, un),		"Underrun"		},
 	{ offsetof(elbt_txeacc, csl),		"Carrier Sense Lost"	},
 };
-static int txeacc_ndesc = sizeof (txeacc_descs) / sizeof (txeacc_descs[0]);
+static int txeacc_ndesc = ARRAY_SIZE(txeacc_descs);
 
 typedef
 	struct {
@@ -500,7 +500,7 @@ static elbt_prdesc epram_descs[] = {
 	{ offsetof(fcc_enet_t, fen_p512c),	"512-1023 Octet Frames"	},
 	{ offsetof(fcc_enet_t, fen_p1024c),	"1024-1518 Octet Frames"},
 };
-static int epram_ndesc = sizeof (epram_descs) / sizeof (epram_descs[0]);
+static int epram_ndesc = ARRAY_SIZE(epram_descs);
 
 /*
  * given an elbt_prdesc array and an array of base addresses, print
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 0791043ee1..f911275b25 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -484,7 +484,7 @@ int prt_83xx_rsr(void)
 		RSR_SRS,  "External/Internal Soft"}, {
 		RSR_HRS,  "External/Internal Hard"}
 	};
-	static int n = sizeof bits / sizeof bits[0];
+	static int n = ARRAY_SIZE(bits);
 	ulong rsr = gd->arch.reset_status;
 	int i;
 	char *sep;
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index 2e91f51fce..5498c19e25 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -412,7 +412,7 @@ int get_clocks(void)
 #endif
 
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
-	if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
+	if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
 		/* corecnf_tab_index is too high, possibly wrong value */
 		return -11;
 	}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index f168375b45..61f5639e0d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -958,6 +958,15 @@ int cpu_init_r(void)
 
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
+
+#if defined(CONFIG_PPC_C29X)
+	if ((SVR_SOC_VER(svr) == SVR_C292) ||
+	    (SVR_SOC_VER(svr) == SVR_C293))
+		sec_init_idx(1);
+
+	if (SVR_SOC_VER(svr) == SVR_C293)
+		sec_init_idx(2);
+#endif
 #endif
 
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 14358aeb03..51f1beef51 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -424,7 +424,7 @@ int fec_initialize(bd_t *bis)
 	struct eth_device* dev;
 	int i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 	{
 		dev = (struct eth_device*) malloc(sizeof *dev);
 		memset(dev, 0, sizeof *dev);
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 82a151a0d0..4c51225868 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -720,16 +720,39 @@ enable_l2_cluster_l2:
 	ori	r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
 	sync
 	stw	r4, 0(r3)	/* invalidate L2 */
+	/* Poll till the bits are cleared */
 1:	sync
 	lwz	r0, 0(r3)
 	twi	0, r0, 0
 	isync
 	and.	r1, r0, r4
 	bne	1b
+
+	/* L2PE must be set before L2 cache is enabled */
+	lis	r4, (L2CSR0_L2PE)@h
+	ori	r4, r4, (L2CSR0_L2PE)@l
+	sync
+	stw	r4, 0(r3)	/* enable L2 parity/ECC error checking */
+	/* Poll till the bit is set */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	beq	1b
+
 	lis	r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
 	ori	r4, r4, (L2CSR0_L2REP_MODE)@l
 	sync
 	stw	r4, 0(r3)	/* enable L2 */
+	/* Poll till the bit is set */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	beq	1b
+
 delete_ccsr_l2_tlb:
 	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
 #endif
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index ea4ab3a042..f1ae358466 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -137,7 +137,7 @@ int fec_initialize(bd_t *bis)
 	struct ether_fcc_info_s *efis;
 	int             i;
 
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++) {
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) {
 
 		dev = malloc(sizeof(*dev));
 		if (dev == NULL)
@@ -879,7 +879,7 @@ void mii_init (void)
 
 	/* Setup the pin configuration of the FEC(s)
 	*/
-	for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+	for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++)
 		fec_pin_init(ether_fcc_info[i].ether_index);
 }
 
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 5f5c72002e..4013a0c24a 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -449,13 +449,6 @@ cpu_init_f (void)
 	mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
 	      PLB4Ax_ACR_RDP_4DEEP);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
-
-#ifndef CONFIG_SYS_GENERIC_BOARD
-	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
-
-	/* Clear initial global data */
-	memset((void *)gd, 0, sizeof(gd_t));
-#endif
 }
 
 /*
diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c
index eef9c5a17f..c73509b3ee 100644
--- a/arch/powerpc/cpu/ppc4xx/fdt.c
+++ b/arch/powerpc/cpu/ppc4xx/fdt.c
@@ -11,7 +11,7 @@
 #include <asm/cache.h>
 #include <asm/ppc4xx.h>
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/4xx_pcie.h>
@@ -160,4 +160,4 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 	 */
 	fdt_pcie_setup(blob);
 }
-#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c
index 339d38aa99..a42327eb3d 100644
--- a/arch/powerpc/cpu/ppc4xx/reginfo.c
+++ b/arch/powerpc/cpu/ppc4xx/reginfo.c
@@ -321,7 +321,7 @@ void ppc4xx_reginfo(void)
 	PRINT_DCR(OPB2PLB40_BCTRL);
 	PRINT_DCR(P4P3BO0_CFG);
 #endif
-	n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]);
+	n = ARRAY_SIZE(ppc4xx_reg);
 	for (i = 0; i < n; i++) {
 		value = 0;
 		type = ppc4xx_reg[i].type;
diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c
index d4ef36d39f..cd63456e70 100644
--- a/arch/powerpc/cpu/ppc4xx/sdram.c
+++ b/arch/powerpc/cpu/ppc4xx/sdram.c
@@ -33,7 +33,7 @@ sdram_conf_t mb0cf[] = {
 sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #endif
 
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
 
 #ifdef CONFIG_SYS_SDRAM_CASL
 static ulong ns2clks(ulong ns)
@@ -266,7 +266,7 @@ sdram_conf_t mb0cf[] = CONFIG_SYS_SDRAM_TABLE;
 #define CONFIG_SYS_SDRAM0_CFG0		0x82000000 /* DCEN=1, PMUD=0, 64-bit */
 #endif
 
-#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0]))
+#define N_MB0CF (ARRAY_SIZE(mb0cf))
 
 #define NUM_TRIES 64
 #define NUM_READS 10
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 137afce37a..b432b18c74 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -760,7 +760,6 @@ _start:
 #endif
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
 	mr	r3, r1
 	bl	board_init_f_alloc_reserve
 	mr	r1, r3
@@ -768,7 +767,6 @@ _start:
 	li	r0,0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
-#endif
 	li	r3, 0
 	bl	board_init_f
 	/* NOTREACHED - board_init_f() does not return */
@@ -1037,14 +1035,12 @@ _start:
 	GET_GOT			/* initialize GOT access			*/
 
 	bl	cpu_init_f	/* run low-level CPU init code	   (from Flash) */
-#ifdef CONFIG_SYS_GENERIC_BOARD
 	mr	r3, r1
 	bl	board_init_f_alloc_reserve
 	mr	r1, r3
 	bl	board_init_f_init_reserve
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
-#endif
 	li	r3, 0
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 	/* NOTREACHED - board_init_f() does not return */
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index da7352abb2..41b6677bba 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -14,6 +14,8 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
+#ifndef CONFIG_MPC85XX_GPIO
 #include <asm/mpc85xx_gpio.h>
+#endif
 
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index eccc146dae..505d355bc8 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT	8
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET	0x20000
 
 #elif defined(CONFIG_QEMU_E500)
 #define CONFIG_MAX_CPUS			1
@@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 07d2adf71f..c045a24d1a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -265,6 +265,7 @@ typedef struct ccsr_pcix {
 #define PIWAR_WRITE_SNOOP	0x00005000
 #define PIWAR_MEM_2G		0x0000001e
 
+#ifndef CONFIG_MPC85XX_GPIO
 typedef struct ccsr_gpio {
 	u32	gpdir;
 	u32	gpodr;
@@ -273,6 +274,7 @@ typedef struct ccsr_gpio {
 	u32	gpimr;
 	u32	gpicr;
 } ccsr_gpio_t;
+#endif
 
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index a61e998df6..74b620294e 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -14,112 +14,8 @@
 #ifndef __U_BOOT_H__
 #define __U_BOOT_H__
 
-/*
- * Board information passed to Linux kernel from U-Boot
- *
- * include/asm-ppc/u-boot.h
- */
-
-#ifdef CONFIG_SYS_GENERIC_BOARD
 /* Use the generic board which requires a unified bd_info */
 #include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-
-typedef struct bd_info {
-	unsigned long	bi_memstart;	/* start of DRAM memory */
-	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-	unsigned long	bi_flashstart;	/* start of FLASH memory */
-	unsigned long	bi_flashsize;	/* size	 of FLASH memory */
-	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long	bi_sramstart;	/* start of SRAM memory */
-	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_MPC8260) \
-	|| defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
-	unsigned long	bi_immr_base;	/* base of IMMR register */
-#endif
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	bi_mbar_base;	/* base of internal registers */
-#endif
-#if defined(CONFIG_MPC83xx)
-	unsigned long	bi_immrbar;
-#endif
-	unsigned long	bi_bootflags;	/* boot / reboot flag (Unused) */
-	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* OLD: see README.enetaddr */
-	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
-	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
-	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-#if defined(CONFIG_CPM2)
-	unsigned long	bi_cpmfreq;	/* CPM_CLK Freq, in MHz */
-	unsigned long	bi_brgfreq;	/* BRG_CLK Freq, in MHz */
-	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
-	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
-#endif
-#if defined(CONFIG_MPC512X)
-	unsigned long	bi_ipsfreq;	/* IPS Bus Freq, in MHz */
-#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
-	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
-	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
-#endif
-#if defined(CONFIG_405)   || \
-    defined(CONFIG_405GP) || \
-    defined(CONFIG_405EP) || \
-    defined(CONFIG_405EZ) || \
-    defined(CONFIG_405EX) || \
-    defined(CONFIG_440)
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[32];	/* Version of the ROM (AMCC) */
-	unsigned int	bi_procfreq;	/* CPU (Internal) Freq, in Hz */
-	unsigned int	bi_plb_busfreq;	/* PLB Bus speed, in Hz */
-	unsigned int	bi_pci_busfreq;	/* PCI Bus speed, in Hz */
-	unsigned char	bi_pci_enetaddr[6];	/* PCI Ethernet MAC address */
-#endif
-
-#ifdef CONFIG_HAS_ETH1
-	unsigned char   bi_enet1addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH2
-	unsigned char	bi_enet2addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH3
-	unsigned char   bi_enet3addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH4
-	unsigned char   bi_enet4addr[6];	/* OLD: see README.enetaddr */
-#endif
-#ifdef CONFIG_HAS_ETH5
-	unsigned char   bi_enet5addr[6];	/* OLD: see README.enetaddr */
-#endif
-
-#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
-    defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
-    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	unsigned int	bi_opbfreq;		/* OPB clock in Hz */
-	int		bi_iic_fast[2];		/* Use fast i2c mode */
-#endif
-#if defined(CONFIG_4xx)
-#if defined(CONFIG_440GX) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT)
-	int		bi_phynum[4];           /* Determines phy mapping */
-	int		bi_phymode[4];          /* Determines phy mode */
-#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440)
-	int		bi_phynum[2];           /* Determines phy mapping */
-	int		bi_phymode[2];          /* Determines phy mode */
-#else
-	int		bi_phynum[1];           /* Determines phy mapping */
-	int		bi_phymode[1];          /* Determines phy mode */
-#endif
-#endif /* defined(CONFIG_4xx) */
-} bd_t;
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_PPC
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 05b22bb5f7..3c97476a83 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -29,11 +29,6 @@ obj-y	+= ticks.o
 obj-y	+= reloc.o
 
 obj-$(CONFIG_BAT_RW) += bat_rw.o
-ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y	+= board.o
-endif
-endif
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cache.o
 obj-y	+= extable.o
diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index b96dbc60e0..66cf02dbd0 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,6 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbst's to get to ram */
+#endif
 	blr
 
 /*
@@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
 	li	r5,L1_CACHE_BYTES-1
 	andc	r3,r3,r5
 	subf	r4,r3,r4
@@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range)
 	addi	r3,r3,L1_CACHE_BYTES
 	bdnz	1b
 	sync				/* wait for dcbi's to get to ram */
+#endif
 	blr
 
diff --git a/arch/powerpc/lib/ppcstring.S b/arch/powerpc/lib/ppcstring.S
index 8152ac9b0f..56bb3b824e 100644
--- a/arch/powerpc/lib/ppcstring.S
+++ b/arch/powerpc/lib/ppcstring.S
@@ -92,13 +92,6 @@ memset:
 	bdnz	8b
 	blr
 
-	.globl	bcopy
-bcopy:
-	mr	r6,r3
-	mr	r3,r4
-	mr	r4,r6
-	b	memcpy
-
 	.globl	memmove
 memmove:
 	cmplw	0,r3,r4
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index d2a7dc9b45..2b4dbd341f 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -360,8 +360,8 @@ int state_init(void)
 	assert(state->ram_buf);
 
 	/* No reset yet, so mark it as such. Always allow power reset */
-	state->last_reset = RESET_COUNT;
-	state->reset_allowed[RESET_POWER] = true;
+	state->last_sysreset = SYSRESET_COUNT;
+	state->sysreset_allowed[SYSRESET_POWER] = true;
 
 	/*
 	 * Example of how to use GPIOs:
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 89300096a5..686c215aea 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -216,6 +216,17 @@
 		};
 	};
 
+	mbox: mbox {
+		compatible = "sandbox,mbox";
+		#mbox-cells = <1>;
+	};
+
+	mbox-test {
+		compatible = "sandbox,mbox-test";
+		mboxes = <&mbox 100>, <&mbox 1>;
+		mbox-names = "other", "test";
+	};
+
 	mmc {
 		compatible = "sandbox,mmc";
 	};
diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index 8317db1ad3..427af2c970 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -41,6 +41,26 @@ int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
 int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
 
 /**
+ * Set or reset the simulated open drain mode of a GPIO (used only in sandbox
+ * test code)
+ *
+ * @param gp	GPIO number
+ * @param value	value to set (0 for enabled open drain mode, non-zero for
+ * 		disabled)
+ * @return -1 on error, 0 if ok
+ */
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value);
+
+/**
+ * Return the state of the simulated open drain mode of a GPIO (used only in
+ * sandbox test code)
+ *
+ * @param gp	GPIO number
+ * @return -1 on error, 0 if GPIO is input, >0 if output
+ */
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset);
+
+/**
  * Return the simulated direction of a GPIO (used only in sandbox test code)
  *
  * @param gp	GPIO number
diff --git a/arch/sandbox/include/asm/mbox.h b/arch/sandbox/include/asm/mbox.h
new file mode 100644
index 0000000000..2d7b7d03e5
--- /dev/null
+++ b/arch/sandbox/include/asm/mbox.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __SANDBOX_MBOX_H
+#define __SANDBOX_MBOX_H
+
+#include <common.h>
+
+#define SANDBOX_MBOX_PING_XOR 0x12345678
+
+struct udevice;
+
+int sandbox_mbox_test_get(struct udevice *dev);
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg);
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg);
+int sandbox_mbox_test_free(struct udevice *dev);
+
+#endif
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 11856c2fed..149f28d873 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -7,7 +7,7 @@
 #define __SANDBOX_STATE_H
 
 #include <config.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <stdbool.h>
 #include <linux/stringify.h>
 
@@ -60,8 +60,8 @@ struct sandbox_state {
 	bool write_state;		/* Write sandbox state on exit */
 	bool ignore_missing_state_on_read;	/* No error if state missing */
 	bool show_lcd;			/* Show LCD on start-up */
-	enum reset_t last_reset;	/* Last reset type */
-	bool reset_allowed[RESET_COUNT];	/* Allowed reset types */
+	enum sysreset_t last_sysreset;	/* Last system reset type */
+	bool sysreset_allowed[SYSRESET_COUNT];	/* Allowed system reset types */
 	enum state_terminal_raw term_raw;	/* Terminal raw/cooked */
 	bool skip_delays;		/* Ignore any time delays (for test) */
 	bool show_test_output;		/* Don't suppress stdout in tests */
diff --git a/arch/sh/cpu/sh2/cpu.c b/arch/sh/cpu/sh2/cpu.c
index a2f856f459..9a93cf573f 100644
--- a/arch/sh/cpu/sh2/cpu.c
+++ b/arch/sh/cpu/sh2/cpu.c
@@ -83,3 +83,9 @@ int dcache_status(void)
 {
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh2/start.S b/arch/sh/cpu/sh2/start.S
index ebf731a3ab..6171edcce2 100644
--- a/arch/sh/cpu/sh2/start.S
+++ b/arch/sh/cpu/sh2/start.S
@@ -46,8 +46,9 @@ _init:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -62,4 +63,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:	.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh3/cpu.c b/arch/sh/cpu/sh3/cpu.c
index ea0006a650..494f908f64 100644
--- a/arch/sh/cpu/sh3/cpu.c
+++ b/arch/sh/cpu/sh3/cpu.c
@@ -66,3 +66,9 @@ int dcache_status(void)
 {
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh3/start.S b/arch/sh/cpu/sh3/start.S
index 7a934e24d4..9ed7198f2b 100644
--- a/arch/sh/cpu/sh3/start.S
+++ b/arch/sh/cpu/sh3/start.S
@@ -45,8 +45,9 @@ _sh_start:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -61,4 +62,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:	.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index e8ee0a45ab..de90ca777f 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -75,3 +75,9 @@ int cpu_eth_init(bd_t *bis)
 #endif
 	return 0;
 }
+
+void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaaddr)
+{
+	/* TODO(sh maintainer): Implement this */
+	while (1);
+}
diff --git a/arch/sh/cpu/sh4/start.S b/arch/sh/cpu/sh4/start.S
index 21644b5e67..77fc221aa5 100644
--- a/arch/sh/cpu/sh4/start.S
+++ b/arch/sh/cpu/sh4/start.S
@@ -42,8 +42,9 @@ _sh_start:
 	mov.l	._gd_init, r13		/* global data */
 	mov.l	._stack_init, r15	/* stack */
 
-	mov.l	._sh_generic_init, r0
-	jsr	@r0
+	#TODO(sh maintainer): Fix this up to call the correct code
+	#mov.l	._sh_generic_init, r0
+	#jsr	@r0
 	nop
 
 loop:
@@ -58,4 +59,4 @@ loop:
 ._bss_end:		.long	bss_end
 ._gd_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE)
 ._stack_init:		.long	(_sh_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
-._sh_generic_init:	.long	sh_generic_init
+#._sh_generic_init:	.long	sh_generic_init
diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds
index 30c7a9d3f8..78611c21e6 100644
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -67,6 +67,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index ea37c24497..716d8e9f2d 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -12,16 +12,8 @@
 #ifndef __ASM_SH_U_BOOT_H_
 #define __ASM_SH_U_BOOT_H_
 
-typedef struct bd_info {
-	unsigned long   bi_memstart;    /* start of DRAM memory */
-	phys_size_t	bi_memsize;     /* size  of DRAM memory in bytes */
-	unsigned long   bi_flashstart;  /* start of FLASH memory */
-	unsigned long   bi_flashsize;   /* size  of FLASH memory */
-	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
-	unsigned long   bi_sramstart;   /* start of SRAM memory */
-	unsigned long   bi_sramsize;    /* size  of SRAM memory */
-	unsigned long	bi_boot_params; /* where this board expects params */
-} bd_t;
+/* Use the generic board which requires a unified bd_info */
+#include <asm-generic/u-boot.h>
 
 /* For image.h:image_check_target_arch() */
 #define IH_ARCH_DEFAULT IH_ARCH_SH
diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile
index f7ae4f86ef..c5cf89f493 100644
--- a/arch/sh/lib/Makefile
+++ b/arch/sh/lib/Makefile
@@ -6,7 +6,6 @@
 #
 
 
-obj-y	+= board.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 ifeq ($(CONFIG_CPU_SH2),y)
 obj-y	+= time_sh2.o
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
deleted file mode 100644
index 69cdca3744..0000000000
--- a/arch/sh/lib/board.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) 2007, 2008, 2010
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <console.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <watchdog.h>
-#include <net.h>
-#include <mmc.h>
-#include <environment.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern int cpu_init(void);
-extern int board_init(void);
-extern int dram_init(void);
-extern int timer_init(void);
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
-#ifndef CONFIG_SYS_NO_FLASH
-static int sh_flash_init(void)
-{
-	gd->bd->bi_flashsize = flash_init();
-
-	if (gd->bd->bi_flashsize >= (1024 * 1024))
-		printf("Flash: %ldMB\n", gd->bd->bi_flashsize / (1024*1024));
-	else
-		printf("Flash: %ldKB\n", gd->bd->bi_flashsize / 1024);
-
-	return 0;
-}
-#endif /* CONFIG_SYS_NO_FLASH */
-
-#if defined(CONFIG_CMD_NAND)
-# include <nand.h>
-# define INIT_FUNC_NAND_INIT nand_init,
-#else
-# define INIT_FUNC_NAND_INIT
-#endif /* CONFIG_CMD_NAND */
-
-#if defined(CONFIG_WATCHDOG)
-extern int watchdog_init(void);
-extern int watchdog_disable(void);
-# undef INIT_FUNC_WATCHDOG_INIT
-# define INIT_FUNC_WATCHDOG_INIT	watchdog_init,
-# define WATCHDOG_DISABLE       	watchdog_disable
-#else
-# define INIT_FUNC_WATCHDOG_INIT
-# define WATCHDOG_DISABLE
-#endif /* CONFIG_WATCHDOG */
-
-#if defined(CONFIG_CMD_IDE)
-# include <ide.h>
-# define INIT_FUNC_IDE_INIT	ide_init,
-#else
-# define INIT_FUNC_IDE_INIT
-#endif /* CONFIG_CMD_IDE */
-
-#if defined(CONFIG_PCI)
-#include <pci.h>
-static int sh_pci_init(void)
-{
-	pci_init();
-	return 0;
-}
-# define INIT_FUNC_PCI_INIT sh_pci_init,
-#else
-# define INIT_FUNC_PCI_INIT
-#endif /* CONFIG_PCI */
-
-static int sh_mem_env_init(void)
-{
-	mem_malloc_init(CONFIG_SYS_TEXT_BASE - GENERATED_GBL_DATA_SIZE -
-			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
-	env_relocate();
-	jumptable_init();
-	return 0;
-}
-
-#if defined(CONFIG_CMD_MMC)
-static int sh_mmc_init(void)
-{
-	puts("MMC:   ");
-	mmc_initialize(gd->bd);
-	return 0;
-}
-#endif
-
-typedef int (init_fnc_t) (void);
-
-init_fnc_t *init_sequence[] =
-{
-	cpu_init,		/* basic cpu dependent setup */
-	board_init,		/* basic board dependent setup */
-	interrupt_init,	/* set up exceptions */
-	env_init,		/* event init */
-	serial_init,	/* SCIF init */
-	INIT_FUNC_WATCHDOG_INIT	/* watchdog init */
-	console_init_f,
-	display_options,
-	checkcpu,
-	checkboard,		/* Check support board */
-	dram_init,		/* SDRAM init */
-	timer_init,		/* SuperH Timer (TCNT0 only) init */
-	sh_mem_env_init,
-#ifndef CONFIG_SYS_NO_FLASH
-	sh_flash_init,	/* Flash memory init*/
-#endif
-	INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */
-	INIT_FUNC_PCI_INIT	/* PCI init */
-	stdio_init,
-	console_init_r,
-	interrupt_init,
-#ifdef CONFIG_BOARD_LATE_INIT
-	board_late_init,
-#endif
-#if defined(CONFIG_CMD_MMC)
-	sh_mmc_init,
-#endif
-	NULL			/* Terminate this list */
-};
-
-void sh_generic_init(void)
-{
-	bd_t *bd;
-	init_fnc_t **init_fnc_ptr;
-
-	memset(gd, 0, GENERATED_GBL_DATA_SIZE);
-
-	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
-
-	gd->bd = (bd_t *)(gd + 1);	/* At end of global data */
-	gd->baudrate = CONFIG_BAUDRATE;
-
-	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
-
-	bd = gd->bd;
-	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
-#ifndef CONFIG_SYS_NO_FLASH
-	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
-#endif
-#if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
-	bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
-	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
-#endif
-
-	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
-		WATCHDOG_RESET();
-		if ((*init_fnc_ptr) () != 0)
-			hang();
-	}
-
-#ifdef CONFIG_WATCHDOG
-	/* disable watchdog if environment is set */
-	{
-		char *s = getenv("watchdog");
-		if (s != NULL)
-			if (strncmp(s, "off", 3) == 0)
-				WATCHDOG_DISABLE();
-	}
-#endif /* CONFIG_WATCHDOG*/
-
-
-#ifdef CONFIG_BITBANGMII
-	bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
-	puts("Net:   ");
-	eth_initialize();
-#endif /* CONFIG_CMD_NET */
-
-	while (1) {
-		WATCHDOG_RESET();
-		main_loop();
-	}
-}
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 396023eee8..29d2307fa5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -274,6 +274,13 @@ config ENABLE_MRC_CACHE
 	  to be used for speeding up boot time on future reboots and/or
 	  power cycles.
 
+	  For platforms that use Intel FSP for the memory initialization,
+	  please check FSP output HOB via U-Boot command 'fsp hob' to see
+	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
+	  If such GUID does not exist, MRC cache is not avaiable on such
+	  platform (eg: Intel Queensbay), which means selecting this option
+	  here does not make any difference.
+
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	depends on !HAVE_FSP
@@ -439,21 +446,13 @@ config GENERATE_MP_TABLE
 config GENERATE_ACPI_TABLE
 	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
 	default n
+	select QFW if QEMU
 	help
 	  The Advanced Configuration and Power Interface (ACPI) specification
 	  provides an open standard for device configuration and management
 	  by the operating system. It defines platform-independent interfaces
 	  for configuration and power management monitoring.
 
-config QEMU_ACPI_TABLE
-	bool "Load ACPI table from QEMU fw_cfg interface"
-	depends on GENERATE_ACPI_TABLE && QEMU
-	default y
-	help
-	  By default, U-Boot generates its own ACPI tables. This option, if
-	  enabled, disables U-Boot's version and loads ACPI tables generated
-	  by QEMU.
-
 config GENERATE_SMBIOS_TABLE
 	bool "Generate an SMBIOS (System Management BIOS) table"
 	default y
@@ -465,6 +464,22 @@ config GENERATE_SMBIOS_TABLE
 
 	  Check http://www.dmtf.org/standards/smbios for details.
 
+config SMBIOS_MANUFACTURER
+	string "SMBIOS Manufacturer"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_VENDOR
+	help
+	  The board manufacturer to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_VENDOR).
+
+config SMBIOS_PRODUCT_NAME
+	string "SMBIOS Product Name"
+	depends on GENERATE_SMBIOS_TABLE
+	default SYS_BOARD
+	help
+	  The product name to store in SMBIOS structures.
+	  Change this to override the default one (CONFIG_SYS_BOARD).
+
 endmenu
 
 config MAX_PIRQ_LINKS
@@ -539,6 +554,20 @@ config SEABIOS
 
 	  Check http://www.seabios.org/SeaBIOS for details.
 
+config HIGH_TABLE_SIZE
+	hex "Size of configuration tables which reside in high memory"
+	default 0x10000
+	depends on SEABIOS
+	help
+	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
+	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
+	  puts a copy of configuration tables in high memory region which
+	  is reserved on the stack before relocation. The region size is
+	  determined by this option.
+
+	  Increse it if the default size does not fit the board's needs.
+	  This is most likely due to a large ACPI DSDT table is used.
+
 source "arch/x86/lib/efi/Kconfig"
 
 endmenu
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 5be5491643..a0216f3059 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += cpu.o
 obj-y += early_uart.o
 obj-y += fsp_configs.o
 obj-y += valleyview.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c
new file mode 100644
index 0000000000..5ee4868cf8
--- /dev/null
+++ b/arch/x86/cpu/baytrail/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_MOBILE;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x0d;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index 25382f9aab..b31f24e262 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -53,14 +53,6 @@ int arch_misc_init(void)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
 #endif
 
 void reset_cpu(ulong addr)
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index f0798a7f9e..317f57d3f9 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -109,7 +109,8 @@ static void pch_enable_ioapic(void)
 {
 	u32 reg32;
 
-	io_apic_set_id(0x02);
+	/* Make sure this is a unique ID within system */
+	io_apic_set_id(0x04);
 
 	/* affirm full set of redirection table entries ("write once") */
 	reg32 = io_apic_read(0x01);
diff --git a/arch/x86/cpu/broadwell/sdram.c b/arch/x86/cpu/broadwell/sdram.c
index 4bf5d15b26..e7befde6ad 100644
--- a/arch/x86/cpu/broadwell/sdram.c
+++ b/arch/x86/cpu/broadwell/sdram.c
@@ -190,11 +190,6 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
 	return 0;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 int dram_init(void)
 {
 	struct pei_data _pei_data __aligned(8);
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 845f86a176..1b042037bb 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -39,15 +39,7 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-	if (gd->flags & GD_FLG_COLD_BOOT)
-		timestamp_add_to_bootstage();
-
-	return 0;
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
 	/*
 	 * Un-cache the ROM so the kernel has one
@@ -79,6 +71,16 @@ void board_final_cleanup(void)
 	}
 }
 
+int last_stage_init(void)
+{
+	if (gd->flags & GD_FLG_COLD_BOOT)
+		timestamp_add_to_bootstage();
+
+	board_final_cleanup();
+
+	return 0;
+}
+
 int misc_init_r(void)
 {
 	return 0;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 233a6c8695..e522ff3b7f 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -25,10 +25,12 @@
 #include <errno.h>
 #include <malloc.h>
 #include <asm/control_regs.h>
+#include <asm/coreboot_tables.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/microcode.h>
 #include <asm/mp.h>
+#include <asm/mrccache.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
 #include <asm/post.h>
@@ -661,10 +663,20 @@ void show_boot_progress(int val)
 }
 
 #ifndef CONFIG_SYS_COREBOOT
+/*
+ * Implement a weak default function for boards that optionally
+ * need to clean up the system before jumping to the kernel.
+ */
+__weak void board_final_cleanup(void)
+{
+}
+
 int last_stage_init(void)
 {
 	write_tables();
 
+	board_final_cleanup();
+
 	return 0;
 }
 #endif
@@ -741,3 +753,18 @@ int cpu_init_r(void)
 
 	return 0;
 }
+
+#ifndef CONFIG_EFI_STUB
+int reserve_arch(void)
+{
+#ifdef CONFIG_ENABLE_MRC_CACHE
+	mrccache_reserve();
+#endif
+
+#ifdef CONFIG_SEABIOS
+	high_table_reserve();
+#endif
+
+	return 0;
+}
+#endif
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index 10dc4d47f0..dd2819a12c 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -15,14 +15,14 @@
 #include <dm.h>
 #include <asm/cache.h>
 #include <asm/control_regs.h>
+#include <asm/i8259.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
-#include <asm/processor-flags.h>
-#include <linux/compiler.h>
+#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/processor-flags.h>
 #include <asm/processor.h>
 #include <asm/u-boot-x86.h>
-#include <asm/i8259.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -266,6 +266,8 @@ int interrupt_init(void)
 	i8259_init();
 #endif
 
+	lapic_setup();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts();
 
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 2950783055..df3cd0abc7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -13,6 +13,7 @@
 #include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
+#include <asm/tables.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -121,6 +122,11 @@ static int create_pirq_routing_table(struct udevice *dev)
 	priv->irq_mask = fdtdec_get_int(blob, node,
 					"intel,pirq-mask", PIRQ_BITMAP);
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
+		/* Reserve IRQ9 for SCI */
+		priv->irq_mask &= ~(1 << 9);
+	}
+
 	if (priv->config == PIRQ_VIA_IBASE) {
 		int ibase_off;
 
@@ -142,6 +148,9 @@ static int create_pirq_routing_table(struct udevice *dev)
 		priv->ibase &= ~0xf;
 	}
 
+	priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit");
+	priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0);
+
 	cell = fdt_getprop(blob, node, "intel,pirq-routing", &len);
 	if (!cell || len % sizeof(struct pirq_routing))
 		return -EINVAL;
@@ -206,11 +215,30 @@ static int create_pirq_routing_table(struct udevice *dev)
 
 	rt->size = irq_entries * sizeof(struct irq_info) + 32;
 
+	/* Fix up the table checksum */
+	rt->checksum = table_compute_checksum(rt, rt->size);
+
 	pirq_routing_table = rt;
 
 	return 0;
 }
 
+static void irq_enable_sci(struct udevice *dev)
+{
+	struct irq_router *priv = dev_get_priv(dev);
+
+	if (priv->actl_8bit) {
+		/* Bit7 must be turned on to enable ACPI */
+		dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80);
+	} else {
+		/* Write 0 to enable SCI on IRQ9 */
+		if (priv->config == PIRQ_VIA_PCI)
+			dm_pci_write_config32(dev->parent, priv->actl_addr, 0);
+		else
+			writel(0, priv->ibase + priv->actl_addr);
+	}
+}
+
 int irq_router_common_init(struct udevice *dev)
 {
 	int ret;
@@ -224,6 +252,9 @@ int irq_router_common_init(struct udevice *dev)
 	pirq_route_irqs(dev, pirq_routing_table->slots,
 			get_irq_slot_count(pirq_routing_table));
 
+	if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
+		irq_enable_sci(dev);
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 88ab7973fd..ff1faa5014 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -12,7 +12,6 @@
 #include <fdtdec.h>
 #include <rtc.h>
 #include <pci.h>
-#include <asm/acpi.h>
 #include <asm/intel_regs.h>
 #include <asm/interrupt.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index cef425669c..38e244b05e 100644
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,10 +12,8 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/msr-index.h>
 #include <asm/mtrr.h>
@@ -419,7 +417,6 @@ static int model_206ax_init(struct udevice *dev)
 
 	/* Enable the local cpu apics */
 	enable_lapic_tpr();
-	lapic_setup();
 
 	/* Enable virtualization if enabled in CMOS */
 	enable_vmx();
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index f7e0bc3f18..491f2894f9 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -10,7 +10,6 @@
 #include <common.h>
 #include <dm.h>
 #include <asm/msr.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/intel_regs.h>
 #include <asm/io.h>
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index e35e543c3e..9d9f63d70c 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -201,11 +201,6 @@ static int recovery_mode_enabled(void)
 	return false;
 }
 
-int reserve_arch(void)
-{
-	return mrccache_reserve();
-}
-
 static int copy_spd(struct udevice *dev, struct pei_data *peid)
 {
 	const void *data;
diff --git a/arch/x86/cpu/lapic.c b/arch/x86/cpu/lapic.c
index 30d23130eb..fbea2d1572 100644
--- a/arch/x86/cpu/lapic.c
+++ b/arch/x86/cpu/lapic.c
@@ -65,23 +65,27 @@ void lapic_write(unsigned long reg, unsigned long v)
 
 void enable_lapic(void)
 {
-	msr_t msr;
-
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.hi &= 0xffffff00;
-	msr.lo |= MSR_IA32_APICBASE_ENABLE;
-	msr.lo &= ~MSR_IA32_APICBASE_BASE;
-	msr.lo |= LAPIC_DEFAULT_BASE;
-	msr_write(MSR_IA32_APICBASE, msr);
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
+
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.hi &= 0xffffff00;
+		msr.lo |= MSR_IA32_APICBASE_ENABLE;
+		msr.lo &= ~MSR_IA32_APICBASE_BASE;
+		msr.lo |= LAPIC_DEFAULT_BASE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 void disable_lapic(void)
 {
-	msr_t msr;
+	if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
+		msr_t msr;
 
-	msr = msr_read(MSR_IA32_APICBASE);
-	msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
-	msr_write(MSR_IA32_APICBASE, msr);
+		msr = msr_read(MSR_IA32_APICBASE);
+		msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
+		msr_write(MSR_IA32_APICBASE, msr);
+	}
 }
 
 unsigned long lapicid(void)
@@ -120,7 +124,6 @@ int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 
 void lapic_setup(void)
 {
-#ifdef CONFIG_SMP
 	/* Only Pentium Pro and later have those MSR stuff */
 	debug("Setting up local apic: ");
 
@@ -150,11 +153,7 @@ void lapic_setup(void)
 		    LAPIC_DELIVERY_MODE_NMI));
 
 	debug("apic_id: 0x%02lx, ", lapicid());
-#else /* !CONFIG_SMP */
-	/* Only Pentium Pro and later have those MSR stuff */
-	debug("Disabling local apic: ");
-	disable_lapic();
-#endif /* CONFIG_SMP */
+
 	debug("done.\n");
 	post_code(POST_LAPIC);
 }
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2604a687ab..2b6b3bd04e 100644
--- a/arch/x86/cpu/mp_init.c
+++ b/arch/x86/cpu/mp_init.c
@@ -11,6 +11,7 @@
 #include <dm.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/atomic.h>
 #include <asm/cpu.h>
 #include <asm/interrupt.h>
@@ -21,7 +22,6 @@
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/sipi.h>
-#include <asm/fw_cfg.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>
 #include <dm/lists.h>
@@ -408,8 +408,6 @@ static int init_bsp(struct udevice **devp)
 	cpu_get_name(processor_name);
 	debug("CPU: %s\n", processor_name);
 
-	lapic_setup();
-
 	apic_id = lapicid();
 	ret = find_cpu_by_apic_id(apic_id, devp);
 	if (ret) {
@@ -420,7 +418,7 @@ static int init_bsp(struct udevice **devp)
 	return 0;
 }
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 static int qemu_cpu_fixup(void)
 {
 	int ret;
@@ -496,7 +494,7 @@ int mp_init(struct mp_params *p)
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_QEMU
+#ifdef CONFIG_QFW
 	ret = qemu_cpu_fixup();
 	if (ret)
 		return ret;
diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile
index 6eeddf154e..a080c5e2f4 100644
--- a/arch/x86/cpu/qemu/Makefile
+++ b/arch/x86/cpu/qemu/Makefile
@@ -7,4 +7,5 @@
 ifndef CONFIG_EFI_STUB
 obj-y += car.o dram.o
 endif
-obj-y += cpu.o fw_cfg.o qemu.o
+obj-y += qemu.o
+obj-$(CONFIG_QFW) += cpu.o e820.o
diff --git a/arch/x86/cpu/qemu/cpu.c b/arch/x86/cpu/qemu/cpu.c
index a1b70c6bde..b1a965e715 100644
--- a/arch/x86/cpu/qemu/cpu.c
+++ b/arch/x86/cpu/qemu/cpu.c
@@ -8,8 +8,8 @@
 #include <cpu.h>
 #include <dm.h>
 #include <errno.h>
+#include <qfw.h>
 #include <asm/cpu.h>
-#include <asm/fw_cfg.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/x86/cpu/qemu/e820.c b/arch/x86/cpu/qemu/e820.c
new file mode 100644
index 0000000000..63853e4b22
--- /dev/null
+++ b/arch/x86/cpu/qemu/e820.c
@@ -0,0 +1,43 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/e820.h>
+
+unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
+{
+	entries[0].addr = 0;
+	entries[0].size = ISA_START_ADDRESS;
+	entries[0].type = E820_RAM;
+
+	entries[1].addr = ISA_START_ADDRESS;
+	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
+	entries[1].type = E820_RESERVED;
+
+	/*
+	 * since we use memalign(malloc) to allocate high memory for
+	 * storing ACPI tables, we need to reserve them in e820 tables,
+	 * otherwise kernel will reclaim them and data will be corrupted
+	 */
+	entries[2].addr = ISA_END_ADDRESS;
+	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
+	entries[2].type = E820_RAM;
+
+	/* for simplicity, reserve entire malloc space */
+	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
+	entries[3].size = TOTAL_MALLOC_LEN;
+	entries[3].type = E820_RESERVED;
+
+	entries[4].addr = gd->relocaddr;
+	entries[4].size = gd->ram_size - gd->relocaddr;
+	entries[4].type = E820_RESERVED;
+
+	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
+	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
+	entries[5].type = E820_RESERVED;
+
+	return 6;
+}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7ad0ee49a1..680e558ee8 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -6,15 +6,59 @@
 
 #include <common.h>
 #include <pci.h>
+#include <qfw.h>
 #include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/device.h>
 #include <asm/arch/qemu.h>
-#include <asm/fw_cfg.h>
 
 static bool i440fx;
 
+#ifdef CONFIG_QFW
+
+/* on x86, the qfw registers are all IO ports */
+#define FW_CONTROL_PORT	0x510
+#define FW_DATA_PORT		0x511
+#define FW_DMA_PORT_LOW	0x514
+#define FW_DMA_PORT_HIGH	0x518
+
+static void qemu_x86_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
+{
+	uint32_t i = 0;
+	uint8_t *data = address;
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 *
+	 * Note: on platform where the control register is IO port, the
+	 * endianness is little endian.
+	 */
+	if (entry != FW_CFG_INVALID)
+		outw(cpu_to_le16(entry), FW_CONTROL_PORT);
+
+	/* the endianness of data register is string-preserving */
+	while (size--)
+		data[i++] = inb(FW_DATA_PORT);
+}
+
+static void qemu_x86_fwcfg_read_entry_dma(struct fw_cfg_dma_access *dma)
+{
+	/* the DMA address register is big endian */
+	outl(cpu_to_be32((uint32_t)dma), FW_DMA_PORT_HIGH);
+
+	while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR)
+		__asm__ __volatile__ ("pause");
+}
+
+static struct fw_cfg_arch_ops fwcfg_x86_ops = {
+	.arch_read_pio = qemu_x86_fwcfg_read_entry_pio,
+	.arch_read_dma = qemu_x86_fwcfg_read_entry_dma
+};
+#endif
+
 static void enable_pm_piix(void)
 {
 	u8 en;
@@ -88,7 +132,9 @@ static void qemu_chipset_init(void)
 		enable_pm_ich9();
 	}
 
-	qemu_fwcfg_init();
+#ifdef CONFIG_QFW
+	qemu_fwcfg_init(&fwcfg_x86_ops);
+#endif
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 6d670d75c1..93ce412166 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -6,3 +6,4 @@
 
 obj-y += car.o dram.o irq.o msg_port.o quark.o
 obj-y += mrc.o mrc_util.o hte.o smc.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c
new file mode 100644
index 0000000000..8f69829608
--- /dev/null
+++ b/arch/x86/cpu/quark/acpi.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/mpspec.h>
+#include <asm/tables.h>
+#include <asm/arch/iomap.h>
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+		      void *dsdt)
+{
+	struct acpi_table_header *header = &(fadt->header);
+	u16 pmbase = ACPI_PM1_BASE_ADDRESS;
+
+	memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+
+	acpi_fill_header(header, "FACP");
+	header->length = sizeof(struct acpi_fadt);
+	header->revision = 4;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	fadt->preferred_pm_profile = ACPI_PM_UNSPECIFIED;
+	fadt->sci_int = 9;
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0;
+	fadt->pstate_cnt = 0;
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = 0x0;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = ACPI_GPE0_BASE_ADDRESS;
+	fadt->gpe1_blk = 0;
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 0;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
+	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0x00;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES;
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+		ACPI_FADT_POWER_BUTTON | ACPI_FADT_SLEEP_BUTTON |
+		ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
+		ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->reset_reg.addrl = IO_PORT_RESET;
+	fadt->reset_reg.addrh = 0;
+	fadt->reset_value = SYS_RST | RST_CPU;
+
+	fadt->x_firmware_ctl_l = (u32)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.access_size = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.access_size = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.access_size = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = table_compute_checksum(fadt, header->length);
+}
+
+static int acpi_create_madt_irq_overrides(u32 current)
+{
+	struct acpi_madt_irqoverride *irqovr;
+	u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
+	int length = 0;
+
+	irqovr = (void *)current;
+	length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+	irqovr = (void *)(current + length);
+	length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags);
+
+	return length;
+}
+
+u32 acpi_fill_madt(u32 current)
+{
+	current += acpi_create_madt_lapics(current);
+
+	current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+			io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irq_overrides(current);
+
+	return current;
+}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index afb3463797..bdd360a99f 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <mmc.h>
 #include <asm/io.h>
+#include <asm/ioapic.h>
 #include <asm/mrccache.h>
 #include <asm/mtrr.h>
 #include <asm/pci.h>
@@ -338,6 +339,9 @@ int arch_misc_init(void)
 	mrccache_save();
 #endif
 
+	/* Assign a unique I/O APIC ID */
+	io_apic_set_id(1);
+
 	return 0;
 }
 
@@ -360,12 +364,3 @@ void board_final_cleanup(void)
 
 	return;
 }
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
-	return mrccache_reserve();
-#else
-	return 0;
-#endif
-}
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 4ea9262251..4a50d8665e 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -84,6 +84,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -249,10 +250,10 @@
 #include "microcode/m0230671117.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@2 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 478dece1ae..1a4ecaad0e 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -88,6 +88,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -269,10 +270,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 };
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 337513be57..78a1ef415c 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -154,6 +154,7 @@
 			irq-router {
 				compatible = "intel,queensbay-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xcee0>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 21c36412e2..da3cbff5cb 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -29,6 +29,18 @@
 		stdout-path = &pciuart0;
 	};
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "cpu-x86";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+	};
+
 	tsc-timer {
 		clock-frequency = <400000000>;
 	};
@@ -88,6 +100,7 @@
 			irq-router {
 				compatible = "intel,quark-irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-addr = <0x58>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0xdef8>;
 				intel,pirq-routing = <
diff --git a/arch/x86/dts/microcode/m0130673322.dtsi b/arch/x86/dts/microcode/m0130673322.dtsi
deleted file mode 100644
index 90bf2fb712..0000000000
--- a/arch/x86/dts/microcode/m0130673322.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x322>;
-intel,date-code = <0x4012014>;
-intel,processor-signature = <0x30673>;
-intel,checksum = <0x17b0d914>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x22030000	0x14200104	0x73060300
-	0x14d9b017	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x22030000
-	0x00000000	0x00000000	0x31031420	0x11320000
-	0x01000000	0x73060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x0ae10178	0x7c98f9d1	0x41962d85	0x19391270
-	0xcf3c0336	0xc1f13d6f	0xe46abaf6	0x3b65ca6b
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0x8514b971	0x40df7b4a	0x6a6b7285
-	0x7978ef59	0x319bddf5	0x04c68e5a	0xe1c28b10
-	0x172f63dc	0x306fb95d	0x31d881e8	0x69f8e08d
-	0x617a99e1	0x1ab6b574	0x2951fa5b	0xcc7e3e94
-	0xff379d19	0x5c035dec	0xe28ed726	0x22b8a5ac
-	0xd08b3ac5	0x45c03b9e	0xcea4083c	0xc26758aa
-	0xbe7cf81e	0x43d898f3	0x5c45a635	0xc9cac095
-	0xb89aea20	0x2c02b40e	0xe3a8b48d	0xeabfb60e
-	0x776ed2a9	0x080ae6d5	0x7f64b1df	0x00e40ee6
-	0x0f1c10f4	0x792e5423	0x787f5459	0x63a8b02c
-	0x3fd6a255	0x049cae26	0x0949f5ff	0x9aebb236
-	0xecc01775	0x91b57b84	0xe0e45ea3	0x5a8bf79e
-	0x356a843a	0x2406795f	0x8aaae5d8	0x6a8c877c
-	0xa8b2b8f4	0x04cf8f49	0x422d9e2c	0xf09f9896
-	0xe9b92215	0x9c98fb44	0x88556b7f	0x519d6f4c
-	0x9e8a016b	0xcb18d16c	0x419b4ee7	0x080b49c8
-	0xc51b875e	0x46aabc9c	0x262d27eb	0x93ea189d
-	0xdd0da69d	0x3e5b17e8	0xcc78509a	0x00b07e6e
-	0x363d5a70	0x64572070	0x8a84abc4	0x1cb03838
-	0x965fd76a	0x540aafc9	0x83a91654	0x1a722e67
-	0x4bf98ce1	0x2b3c2ff9	0x972cebd4	0xf3a68395
-	0x2613e422	0xf8d031d7	0xb1c79a0f	0xfd44f65b
-	0xa7012a9b	0xd9a15a60	0xc311fc0c	0x6f52f878
-	0x3d68381d	0xd2a035d7	0xb790c50e	0x9f1e5010
-	0x41877064	0xa9d1e4ae	0xfe9abbd5	0x60c2c748
-	0x8167e5ad	0x022dbfb3	0x75abe483	0x51c37170
-	0x09b8590d	0xc1bb323d	0x2c7336b1	0xd4d0d49b
-	0xc7f6152b	0x7919d596	0x1e1ff62e	0xc49604a0
-	0x33857369	0xeaa3f382	0x98b8cd86	0x176e1bf3
-	0x1a68867b	0x6af0a11c	0x69a82b25	0x48c72525
-	0xa00aae2d	0xb09f67f4	0x1a99f83d	0x7266cca3
-	0x8d03a7da	0x2e1d7c49	0x01ac68ae	0x93188770
-	0x0609e769	0x982ed28d	0xe40999e0	0x8932ebab
-	0x5637ad5a	0x2725e8ad	0x56d7caaf	0xc351faa2
-	0x09dbd737	0x0d2f3bf0	0x0623330d	0xdd547489
-	0xcca7e722	0xa9096d13	0x95b17818	0xc092cb81
-	0x72c6eefc	0x1811c37e	0x78161497	0x8be0c4c6
-	0xd63aeb19	0x91ab68df	0x8f2e5e4d	0xf4c74566
-	0x7677a553	0x19698ac3	0xedca0620	0x77f32470
-	0x031e011b	0x751f6696	0xb277d06e	0x3eae2742
-	0x133e621a	0x38fa3172	0x9398cc1c	0xf42a507b
-	0x4547d933	0x63a91eb0	0xf5bcf6a4	0x926ba056
-	0x0adf5bce	0x140f53e4	0x7ff6bb5c	0x87dd79ba
-	0xbba240ac	0x694f743d	0x709cdb20	0x5b4d4401
-	0xc9693610	0x55f9f268	0x1142bc3f	0xf8fe3689
-	0x04a93c4c	0x33dedc46	0xdc73c725	0x2f5ba264
-	0x5b7a6a69	0x024b64f5	0x6e8bfa12	0x62bf2aa7
-	0x520f5a07	0x3c7c4292	0xb7ad2613	0x1f78fc87
-	0xd5284e4e	0x2c730f33	0x8861e947	0x8bacef7d
-	0xbafa2608	0x14ed0b5b	0x3b9bfb02	0x24ced271
-	0x002b2941	0x22d4431c	0x855f4248	0x5ec46e29
-	0x6f1f42fb	0x5dd24fe0	0x290961f6	0xf392dbaf
-	0xa1a8d9c2	0x61e18f4e	0xfda59a70	0x5498daa5
-	0x5ae7ea6f	0xf058c635	0x6817ebee	0x8e30dc8b
-	0x7c8d79be	0x5fb15b9b	0xeed64741	0xe2642a94
-	0x680d7e6e	0x3cbad7aa	0x808c415f	0xe9323aa2
-	0xaadf5b25	0xf60abf13	0xd5c47967	0xc248d0b3
-	0x0f232cbd	0x84092449	0x5744384b	0x5e153ded
-	0x8bb19817	0x34430271	0x917d2315	0x1fc790c7
-	0xc21b5db6	0xec578b1f	0x903a286e	0xca0c59bc
-	0x03e95c7a	0x8c659e99	0x7b09da0a	0xd61e7517
-	0x90b1c519	0x8deac92c	0xf99c7bec	0xb6257d92
-	0x3d61c16e	0xebd58be0	0xb470e655	0xa44bbf4f
-	0xfebe5313	0x4662110a	0x5d42ccd9	0x140845ec
-	0xc80329a9	0x915ca966	0x71e33828	0xe46c870a
-	0x7da9a490	0x255544da	0xa20fb8df	0xf94062b3
-	0xb2df5870	0xebf31e88	0x6e723e2f	0xe6ba9cf1
-	0x7e7084c2	0x1782ac71	0x0a0b0127	0xe9234e38
-	0x881356d6	0xb27a54b6	0x5594730e	0x9a14bd8f
-	0x6dba7da9	0x1069e285	0x02a52798	0x61ea7d86
-	0x665b2572	0x29d41eb5	0x1d211169	0x1218b345
-	0xbfbd264c	0x5b8b0625	0xbbfdcf39	0x6768dfce
-	0x0b5f10cb	0xe159414c	0x74356ed6	0x70077f49
-	0x672107e8	0x11616856	0x824e6f2f	0x99614958
-	0x5857305d	0x416a193f	0x010d266c	0xe5194f03
-	0x152d6516	0xeb83872e	0x4923cc1f	0x1191d1ca
-	0x23feb738	0x6817c1d7	0xe49129ed	0x4a53132a
-	0xdb46b95b	0x3f970366	0x93f1a518	0xae8d72ae
-	0xb689d915	0x0bdfda17	0x2ac7238d	0x1c4291e7
-	0xc5b11085	0x3c51c1ba	0x9fd63edd	0xe464d740
-	0xc17f2789	0x0adef6b9	0xf9aaf83e	0xfb2a9798
-	0x7f16268b	0x4c8ca6c5	0x2b17be52	0x00c91157
-	0xb69eb5db	0xe55ed94a	0xdf13b5a5	0xbb52d1e3
-	0x651bb017	0xc7795724	0x0dfd4711	0x02d2d6e0
-	0xc835e771	0x8ab5dd50	0x7caca109	0xd5c18d6e
-	0xbef0e727	0xaff2dd07	0xf1062a32	0x26d14796
-	0x97f6e36c	0xf845278e	0x185eb5b3	0xcde4e201
-	0x13166ab7	0xcdcebcdc	0x143ef0c7	0x2349893f
-	0x9dfcb70e	0x7ef72725	0x141c5b71	0x7da0f5d3
-	0x76bebb67	0x28bc0a83	0xb67ecf0f	0xd60a1303
-	0x9391b279	0x6ad41154	0x317896b0	0x1237efa6
-	0x7b2a2e6c	0x3ad9a110	0xb44357d4	0xb32e39fe
-	0x2358d28e	0x76e847d9	0x3e85db01	0x6c74e466
-	0x9e4e6b32	0x13072a53	0x5972132e	0xd97cb04d
-	0x55ee6a0b	0xc1434b92	0x772f6a1d	0x0f81f7a6
-	0x072aa8f7	0x179da0e0	0x976bd78c	0x2e43c16b
-	0x4f4a6b51	0x92d9c61b	0xa9c15fe4	0x3f8a527a
-	0x3a232408	0x543d7957	0x21cbd682	0x896de3b0
-	0xba6b3df6	0x2ec86e51	0x2be889e3	0xae764ff0
-	0x3a2f0003	0x7a5f7949	0x577fb5ce	0xb5cbd1a6
-	0xc910ffe2	0x7fd76712	0xfc1e93ff	0xbee7b15c
-	0x5db2356d	0x9721a3fd	0x0d408aed	0x4df4c922
-	0x45d5be91	0x6c79b1fc	0xf0bf73bd	0x3f6a73b6
-	0xdcc1b51e	0x2049fe2d	0xf2b2ad4b	0xd0484d3a
-	0x1f097d3f	0xced1bf3d	0x10f4416b	0x73cb307c
-	0x4b4d94b4	0x2918ece0	0x0cfe69f3	0xb7e86cfb
-	0xa6c373b4	0x0d862b62	0x1735cd72	0xef23c127
-	0x09809c16	0x86cfb70b	0xe67c6903	0x743223a7
-	0x13c7d27f	0xb70a58cc	0x82c57566	0x2ead3c65
-	0xf9409863	0xf2b578ef	0x1622a34d	0x5ae8e861
-	0xf4384016	0x443ff5f4	0x088b8510	0xd738d1c5
-	0x577d624b	0x5adf3973	0x5f79add3	0xed7e7145
-	0x29008fc0	0xd5b278cf	0x5b4c08c2	0xb063af5c
-	0x67d41bd9	0x2d11424a	0x727924de	0x8903a86f
-	0xb122d314	0xd9675c8b	0xc2eb1382	0x4c4185da
-	0x257a0fe1	0xc3fd536b	0xadbfc223	0xc940dab4
-	0x2e83d4b0	0xf1135ad4	0xfeb1cc1a	0x9178ae04
-	0x996d72ba	0x07f6bf0f	0x6588f833	0x44f95205
-	0xee4e6897	0xa9006735	0xa5f5502c	0xeb61aca6
-	0xf2ceddb5	0x40ef9001	0xf862c3d7	0x73deaad3
-	0x7b1d8b1d	0x467bcbcf	0x7f76f969	0x6c8e7f8c
-	0xfb8e27c3	0x5075ce65	0x1c8628a8	0x7b6e3e32
-	0x4885fc9f	0xa9fa768c	0x15426120	0x1df9d006
-	0x31c52df4	0x1457f5c6	0xde5f2daa	0xfa250108
-	0xbcf7e460	0x565d4679	0x82c94142	0xae76342a
-	0x85aca7c7	0x8bc49e03	0x73f03da3	0x1e500b4c
-	0x250288a2	0x25a39951	0x66087700	0x6317754b
-	0x6ff62bdc	0xa519ad4f	0xa537b8ac	0xea6292ab
-	0xb5d66b68	0x15997d1f	0x0fdbf04a	0xaa2b1a25
-	0x74b72321	0xf8b1753a	0x33658d1e	0xb1cc5d96
-	0x5b0da6af	0x48f24997	0xb031146e	0xfe98e8d1
-	0x9bd75bf0	0x0ae088fe	0xb8fce721	0x964bc398
-	0xe82daef6	0x393884b5	0xa814f792	0xb3667bde
-	0x1d1cf32d	0xce862720	0x7b69e921	0xabd26f33
-	0x61fad35f	0xd7144eeb	0x74016bce	0x1d56277b
-	0x7f934eed	0xb1a3396a	0xd5090c7a	0x4ea94d12
-	0x1455ac10	0x7c37294c	0x06c60a9a	0xa735ab29
-	0xbffb880f	0x59e2cb48	0x54cca9d7	0xb569da05
-	0x595e72ec	0x7c82f204	0x7690420d	0xe02fbb37
-	0x4dbf4e68	0x221eda99	0x31868046	0xda435487
-	0xb4c0dcc4	0x37610096	0x35569b02	0xefcd4ecf
-	0x7b6917bf	0x45946a25	0x5d42a84a	0x8c3801b7
-	0x5ac838fa	0x7a7f252d	0xbccf3cb5	0x99a54c4c
-	0x39145831	0xfd5c1af3	0xcabb180c	0x8f0fe9dd
-	0xabd42357	0x3b6d9aa9	0x0e87ede1	0x65ea46ae
-	0xd89b618e	0x1e5cc772	0xfb43c9b4	0xdad3fdb2
-	0x96be6600	0x4887696e	0x82a4e73a	0xb2ca2cf0
-	0xc6840738	0x397d27a9	0xce971271	0x067e4de6
-	0xb593f079	0x6a77de2f	0xf9a92497	0xdc3e94aa
-	0x03239a80	0x7f38430a	0xf7f87908	0x682a8425
-	0x2d491962	0xb5737b4b	0xa26434e5	0x238ced20
-	0x1ed9fcbe	0x283a8f7b	0x18f33cf6	0x29f27cd5
-	0xd95018aa	0x883dbd25	0xfb216723	0xe939d42c
-	0xf4b1207d	0x54f5e102	0xbe2e46eb	0xb2ca8219
-	0xab181ad4	0x3a7dc3e6	0xf3713256	0x53f081ab
-	0xd630a7a3	0x07c40bc3	0x7a1fde0c	0xb368bab8
-	0xc0baaad3	0xf070baac	0xe4ab7a4f	0x82a8cf5e
-	0x9c3d7bb5	0xfe5f74a3	0x02548e86	0x2710ff5d
-	0x1b42a8c4	0x34d4f5d8	0x8dfde8f2	0xf2949298
-	0xe9d711bf	0x44d91e17	0x51ba8b32	0xbc3f60cc
-	0xa0d6c440	0xf71959b4	0x3b5f0603	0x02465794
-	0xff5d9b8a	0xd4a4abcf	0x8123626c	0x883ed4e4
-	0x9eaeaa09	0x91c38865	0xa0aaeebf	0xc48983ab
-	0x1df7a001	0x7519a65e	0x5ef3cd1d	0x8348225d
-	0x0f318b0b	0xbab1d51b	0x15ba9b84	0xef8c57bf
-	0x15d0a8c1	0x0b542fb4	0x1d51ccc8	0x6c297041
-	0xf3bee946	0x6a8c3d64	0x6e16361d	0xed50ca69
-	0x8c1f66ba	0xff7220e0	0x84a87cba	0x15d75922
-	0x77546d82	0x7bd456e3	0x10166195	0x55604f1f
-	0x894280d2	0x0ed406c4	0xc1b4058e	0x645252e5
-	0x670ea74e	0xd5b07337	0x9944e2cf	0xf2ac2579
-	0xd00c3ae8	0x2df3146d	0x4ee1c72a	0x3a3621cf
-	0x8c099145	0xf5f530e6	0x210da136	0x7908cec6
-	0xc6e47e22	0xe9bcbe4e	0x94cbcb12	0xb81f0792
-	0x1111f81e	0x4df4ac93	0x335c69be	0x9e3546b9
-	0x06c046b4	0x6f29a99c	0xbcd48ee7	0xeb011efe
-	0x41e80474	0xcee30bf4	0xad4e2ae0	0x6929a359
-	0xbdaa88e3	0x9e68a38e	0x16bbdac7	0x020d8d61
-	0x7bab6738	0x559cddbd	0xa6ae3d0c	0xe032c355
-	0xcb45a045	0x9f7680b2	0xc1cb73da	0x466052f7
-	0x488cb929	0xd93f0307	0xb2c9d81c	0xe25fdcd9
-	0xfe8b08c4	0xae6230bd	0x5238b335	0x3474b2a5
-	0x480ce0b7	0xd9a2942f	0xe830fa5b	0x3efa774f
-	0x84e53e93	0xf49e7d79	0x59897b26	0x75b1080f
-	0xc2212b0f	0xe5fe56bd	0x4556e908	0x1bd0bb17
-	0x2f159d20	0x866477e5	0x4e95a374	0xbdc9fd65
-	0x2ff87073	0x5d7dceea	0x69ada0c7	0x89f16ad0
-	0x97da55d8	0xe4457728	0x5ab7613e	0xf6bbe6ec
-	0x56b83617	0x9119b521	0x4fabf948	0x2e1ab994
-	0xd16363f0	0xaee14b3f	0x5461ea55	0x55d95d02
-	0xf72c902c	0x1ede6c56	0x697006d9	0x4d15007f
-	0x0c1cb5e5	0x55d3d5d5	0x1f18d76f	0x55c9f017
-	0x3e1d3b5b	0x8f775636	0x97e6bf8f	0x360a9fb5
-	0x1e080721	0xf9825356	0x30e900f3	0x55453bfe
-	0xbd8f1df0	0x35b43ba8	0x45db013f	0x20484d34
-	0x944ca654	0x79c2c151	0xd4e9b39b	0x1b2e79b6
-	0x554314d6	0xce4ee44d	0xd0394232	0x9da4db20
-	0xa70beed6	0x4ae4ed10	0x4c244770	0x4b91208c
-	0x39a01e0b	0x5eea0a55	0x4b36ffbe	0x6fd18df2
-	0x43fd13e3	0xa99302bc	0x63762b5d	0xd014d6b4
-	0xbf0e53d2	0x0f5b5aa5	0x3c23f5b7	0x16335036
-	0xe011bd10	0x66e596a3	0xf463e3ad	0x9670c0a3
-	0x4004e177	0xbd2b3260	0x01967017	0x1159a682
-	0x62931eb8	0xc581df9e	0x6710932f	0xfb2bb0b2
-	0xb8a0339c	0xc66f0fff	0x333f5ee3	0xc06f8586
-	0x7b9f47f1	0x9aaedaa3	0x6044562a	0x26c73565
-	0x82c6e5b2	0x39d4eed0	0x83b7432e	0x0c4f0e4a
-	0x4d9df788	0x989e7f41	0x61cacc3b	0xdc34efeb
-	0x240b22a8	0x70a508b0	0x7554f517	0x7269f02b
-	0xd27ffcf6	0x96a5879f	0x0650f7e4	0xdc1fc1ac
-	0x80781334	0x04ab3381	0x8bad17c1	0x18311833
-	0x65f06ee9	0xfaac30e1	0xe39b8b54	0x20b988ce
-	0xa6a818f3	0x75ac753b	0x66f815a4	0x224d7121
-	0x63dc6031	0xcfeed2c7	0x3ccd07d7	0x9df44157
-	0xb9dcca97	0xcf5178f1	0x10e8fb28	0xa1faa527
-	0x8851846e	0x01f56075	0x2dd4fff2	0x40786960
-	0x41aa9e6c	0xf7c85573	0x64a36432	0x4449e726
-	0x7aa7bb0d	0x08f596cc	0x248e1eb3	0x5c5567cb
-	0x62ffd012	0x2d79ce59	0xf9ed4239	0xe98e107a
-	0x4da25561	0xc6f83333	0x1ca0482d	0xcc3f3b69
-	0xa9f48711	0x99139510	0xc5777d2b	0x9c80814d
-	0xab47fbe4	0xf302d145	0x20aecccc	0x3be9e431
-	0x7dc34793	0x4d38171c	0xaa34e505	0xc32e492b
-	0x4f31bd0b	0xb7549889	0xdb3da9cf	0x084d0791
-	0xa4c63c9f	0x62e770e9	0x862fdb93	0x52c45b9e
-	0xf21019a5	0xdde6aa07	0xcb46386e	0x830693a8
-	0x651510c8	0xf3af66a4	0x78775e07	0xc9f22414
-	0x5769f089	0xac2ae873	0x044357d8	0x9fdc76f8
-	0xea16ade5	0x144e9211	0x181ade72	0xba50ce80
-	0x4573571a	0x5437c668	0x39c3b81d	0x013d766d
-	0xc1754b48	0xa611fa3b	0x725eae72	0x04b02ca9
-	0x186a2541	0xa2784e47	0x8b7601bb	0x7f9132e3
-	0x3295d5b5	0x4b470dee	0xaf5ec559	0xc4c442d6
-	0x5b07293d	0x9a68b079	0xc1408c0c	0xc2371025
-	0x4af99e8c	0x332c416a	0xec04321b	0xb8493ffb
-	0x51eab7de	0x26d7e9db	0x7880126e	0x439be5e3
-	0x7e8910f0	0xa8ba727b	0x88cb04df	0x70750495
-	0xc13413f6	0x684312db	0x0579d5b1	0x05fe44f7
-	0x627e04f3	0xe85b47da	0xbf646f0b	0x2ddf4932
-	0x1bcb6fc0	0x611de27d	0xb3ee1bed	0x247dad06
-	0xa7107d34	0xba434b88	0x6eb90466	0x45a65871
-	0xa9a67088	0x6af3b796	0xf5b73689	0xcab03ca4
-	0xca1f25e6	0xd4b7c32b	0x5908c88d	0xac6c1fa3
-	0x653184a5	0x062bc0bf	0x383de594	0x17064fc6
-	0x0650dbad	0xaec15153	0xab0572ff	0xab8c6f3c
-	0x37a93f91	0xbe51b8c5	0xabcd8573	0x05b3ad78
-	0xad6c9ecc	0xf302c7ab	0x4b3b88f7	0x805a0107
-	0xa5821ddd	0xc36f10ad	0x374b1056	0x79e69f8c
-	0x8368b6cf	0xf69458a7	0x9fad691d	0xb937724e
-	0xc542bfb1	0x37c0178d	0xc4707414	0xd6c7fa86
-	0xb3933710	0x227800f4	0x6dca3e39	0xd88bdb91
-	0x03755bda	0xa7f2d11d	0x4ab40803	0xf353e7ed
-	0xf2464ee4	0x8e58cea4	0xd05807fd	0xd8d8da5f
-	0x1a461333	0x5e84830d	0xb94ea4bc	0x5bf3506f
-	0x76461ba7	0xabe88c54	0x124c2e39	0xc3b01867
-	0xc6b0d4d1	0x9cc3c7be	0x8039ce38	0xfceb0e88
-	0xa965c5ce	0x9ff3811a	0x1af1c60e	0xae9c5f9b
-	0xee28bd50	0x202cbd2e	0x340a1312	0xa8f7115e
-	0xb000cf3a	0x21ff4052	0xa555f08f	0x1bead4d7
-	0xac14e135	0x449e208c	0x05ef8d94	0xb555a613
-	0x9d65a902	0x3ad8cc2a	0x55170533	0x75782927
-	0xefd4b5e5	0x6127ef1e	0x23fb5114	0x7ca3e1bc
-	0xc08957ba	0x44c4e2cd	0xc0b97ef9	0xea99db5a
-	0x53fdeb31	0x61721ee2	0xe41ef3c1	0x5f4788f5
-	0xa8543eca	0x3f36d642	0xda6eccef	0x0341c756
-	0xbfe7d2b9	0x66bb5cef	0xbfb43507	0xbd9c878e
-	0x94f307bc	0x7cd56198	0xf98596ba	0x21e9c50b
-	0xb9c9d725	0xf16211c2	0xe594b398	0x7e01aefc
-	0x745e5ddb	0x00bae556	0xc317ed35	0x4269b4c6
-	0x02f6b67d	0xccb4aa57	0x8a3fa0fa	0xcc660149
-	0x57cf5e87	0x4ed03819	0x77286134	0x631cc0a5
-	0x877fe8e0	0xa48856dc	0xe1c57e93	0xef04482a
-	0x40cd9ac8	0xc7f43528	0x473306c8	0x01eb339e
-	0x52612a88	0x65c3212f	0x7cc5f5e6	0xd3efbc2a
-	0xf2537dbc	0xa9428ffd	0x76ff40f9	0x0ad4a8e6
-	0x2020fbab	0xf8c5bbe4	0xb409e5a0	0x358d7b37
-	0x08220bd3	0xd3707d96	0x5e2f5edc	0x638feed5
-	0x045afa36	0x4f1604b4	0xd4dc85c7	0x37f97cef
-	0xe1c8f5a6	0xd16fdbbc	0x986137fd	0x25b3e84c
-	0x7f73be76	0xe25dbdcb	0x1f13d28a	0x7a31215b
-	0x241967d2	0x2c5b4063	0xe8339988	0x13689262
-	0x0b6d2b79	0x58773464	0xe822e560	0x77d6ba8e
-	0x6ae6c07f	0x105e1e88	0x0045bc6d	0x88ad198e
-	0xa350b9de	0xd5d0b3e6	0xc4e1cd14	0x47ca431a
-	0x2ee94476	0xa2aae1f9	0xfa2042a7	0x37b0cf82
-	0xb1aca28e	0x9a019883	0xbfb11afb	0x754ffff9
-	0xf065a9b5	0x916e14f2	0x93fba80f	0x1dd82da0
-	0xe41c950a	0x12b374bb	0x0f4d533f	0xbef539e2
-	0x1eb5c86a	0x577dd484	0x98900e2f	0xcaec8695
-	0x6a6ab336	0x135e9e68	0xc9b62a35	0xb8982b6c
-	0x5bcdb533	0x389b1517	0xbb106e40	0xd402a301
-	0x7446687b	0x35eda3ec	0xd44ceb2a	0xcfa4e441
-	0x29664690	0x598a273e	0xf2a144b1	0x68f81403
-	0xca53e666	0x064e69a4	0x87bb8ca8	0x58193c68
-	0x9b34b17a	0xde2bffc7	0xf72594dc	0x388d3f3f
-	0x638a1273	0x5ccf3567	0xcf1017a9	0xe616a6fd
-	0x64cab73c	0xd209b022	0x6f08cd26	0xc30f57b1
-	0xac2295b2	0x0c05b1c8	0xf7915ad8	0x9bcf836f
-	0x56d8b57a	0xc8b65a2c	0x11868dd3	0xea4764f8
-	0xa7bd30e8	0x8c895321	0xd276a894	0x86042daa
-	0xaf6cd261	0x18cc4ea4	0x2c2185f6	0x2bf3ae70
-	0xf3023c31	0x49f4b0e2	0x1e00afc3	0x2053b3c6
-	0xb188c9cc	0x7437a27a	0x1b29925e	0xbc488906
-	0x81cd9003	0x332fcf9b	0xeb20987a	0x831f912a
-	0x857387da	0xaf1edccb	0xfe01d809	0x05351b4a
-	0x31ec96ac	0x4f064e52	0x10ec8119	0x96c2d29f
-	0xc6e1f3fe	0x15b0d45f	0xdca23bc6	0x7b672563
-	0xa94fdc1b	0x7dd22f4f	0xd4d2260f	0xc9e055ff
-	0x89e066cc	0x98200d25	0xcba82cf7	0xffb8475b
-	0x26550a20	0xf5b4f84a	0x506cb84b	0x00d92997
-	0x7a5c5535	0xe11194eb	0x1ff21f4b	0x725d2be5
-	0xbe89242f	0x0b18afa7	0x6f5b1433	0x829bdaf9
-	0x42db07b9	0x479493cb	0xabd2ead3	0xea6afa58
-	0xf994c740	0x4cb77f7e	0xb946cbdc	0xfe558e82
-	0xa2ed5c20	0x7012b99c	0x72a41e08	0x2058815b
-	0x0528d06d	0xe6dbd7e1	0x3d1f6f9e	0xca78b63c
-	0x91fa57a2	0xb6d524a7	0x1a61863d	0x89c25c5f
-	0x16960596	0x6ebed63e	0xfcd617d1	0x0a927121
-	0x887fdc75	0xec27c8de	0x8c91a821	0xd6bb116d
-	0x51fe2c18	0x4af774d9	0x7aa13fdb	0xfc6ff59d
-	0x27dd287b	0xe7e3151c	0x835552ea	0xe628aa1c
-	0xe0edda2a	0x1957ade4	0x52336fae	0x9cecef28
-	0x2be84cbf	0xa5959450	0x65299682	0x8151d4f8
-	0x716a5209	0x0a8ca663	0x2187bc46	0x000767f5
-	0xe7295b8d	0xa8bc7a6c	0x2b4d2f10	0xf251372f
-	0x92ff27ff	0x9bfd83e8	0x8e2b593e	0x8915fd15
-	0x1e44eed0	0x4a3a4679	0xce135f45	0xf996ec1b
-	0xfd86c8ac	0x25b008fa	0x8973cf58	0x481512ae
-	0xf2bc46f1	0x8b3a92bf	0xbf2a7b24	0xb19e88be
-	0x1823f658	0xa8486c11	0x237771c0	0x6f5f0da2
-	0xb05a42e3	0xb562583c	0xa13d37f7	0xe8eede16
-	0xc5154af2	0xfdf7f9b9	0x0b907685	0x1f567e56
-	0x19987b40	0xc82974ab	0xf02ae429	0x9c356634
-	0xb85ba9e9	0xda2141b7	0xd44e331f	0x1dd722d3
-	0x68fd2f4e	0x4e7f88a2	0xab7314b3	0x3dd05c4e
-	0x1bb4093f	0xff73db9b	0xf917c6e0	0xae822501
-	0x05cab9fe	0x67c91c76	0x1ebd2575	0x1ae193fd
-	0x6f154ae6	0x13780ac7	0x6ff5bf0c	0x6b664594
-	0x494a71d1	0x9bc35a0f	0xb34f175b	0x0069468c
-	0x9b125042	0x7df22e49	0xf39cf8ed	0xbe020df1
-	0xe206848b	0x8c428e75	0xc76c05d4	0x0089e2c4
-	0x5bf9a75a	0x30677869	0x544797ed	0x68456dbd
-	0x45b8f0aa	0xac5c82d1	0x05aefb75	0x6d5c28bf
-	0x009ddb3b	0x551ff144	0xd19127ea	0xfc860071
-	0x30c93457	0xa4c4b56a	0x6928a07c	0x9f63e6a7
-	0x9fa2b174	0x7c1b2fa4	0x4a5a1f25	0x24acb022
-	0x0c3c11f4	0xc7d4cec8	0x4484a031	0x6d3cc1c7
-	0x2eb86733	0x8cd4f77d	0x7b551519	0x124b6805
-	0x57385eef	0x3efd3da9	0xea300d5d	0xe64fc82d
-	0x7d33386b	0x3933c4d3	0xe3cb61f8	0xc6fe8846
-	0xbe0df669	0x8646e4cf	0x194a444a	0x404c81af
-	0x9448791e	0x586f2132	0x3def508a	0xa3edebe5
-	0x2f3b0b5c	0xc974f91f	0x400ec25b	0xf1513ffb
-	0xc13b8859	0x32ac4d39	0xf8f334b2	0xab53ba5d
-	0x9e196996	0xf14d8046	0x22fcb441	0xf27ac4c8
-	0xbbdf5623	0x255df428	0xd95a2352	0x8d26f0dd
-	0x60a301d1	0x4a2e3e49	0x4654b081	0xf775e35f
-	0x592b5eba	0x6a3f9583	0x6ec3d395	0xc8ab02e8
-	0xf343f806	0x62745498	0xb499dbf3	0xd427334a
-	0xdf0b61e7	0xda67999e	0x14f9be12	0xf164898a
-	0xd6347aa7	0x079a537e	0x294542e1	0x687b7b6b
-	0x8478cffc	0xf335963f	0x6c1b9ac2	0x68ff2779
-	0xe3d3f8a8	0x5453c548	0xd968189b	0x13ad95b4
-	0xd71bee24	0x3939f36e	0xb19b3595	0x001961aa
-	0x5f2f001a	0x77137eea	0x477698a0	0x1c07c440
-	0x9606b6d3	0x6ce95229	0x25445629	0x5a935f13
-	0x3e2154aa	0x6876442c	0xd9175c78	0xc94d2535
-	0xf2070dd4	0xd4d1f50b	0xa04d18e5	0x3456cfa4
-	0xc7610f62	0xb705a1a8	0xb8766e3e	0x225642de
-	0x4be5b1b5	0x44d32453	0x80b8a9d4	0x7297d633
-	0x09e8aa04	0x540929ec	0xbcc58c41	0x6dcf7b61
-	0x6992928c	0xcd40ff22	0x13e4a724	0xd331d5f3
-	0xa512aeb5	0x1c1c4ae8	0x5f0fe5d2	0x3d539538
-	0x383c214c	0xd0a983e9	0x977e8682	0xf38a571d
-	0xdb92de78	0x04ba543f	0xb531e880	0xfea55473
-	0xd6d17b05	0xbdd676ed	0xfc7d4f68	0x8b5170ed
-	0xa738734f	0x8a25fff2	0xb1b0239f	0x60545acb
-	0xcfb00725	0x35f58585	0xcce4ed42	0x05da1c3f
-	0x29428b1b	0x099680c9	0xb4608916	0xa9f177b7
-	0x3b393c9d	0x92d19426	0x472dfe73	0x7b12de81
-	0x557ec0f2	0x166fa28f	0xfb6855da	0x592d3e69
-	0x373a1dba	0x9c76abae	0x13c7f717	0xbc53e796
-	0xb2d39602	0xf1efa3b2	0x00046c93	0x1faf82fa
-	0x55dec395	0x22a034c8	0x576bd5f2	0x97c36a45
-	0x08a1a923	0x9ac2f22c	0xb029e4bf	0x6c4ca958
-	0xed7276cb	0xa0924918	0x1894c9d8	0xdb993c42
-	0xc31c6e18	0xbadc738b	0x57f95d64	0x4d766a25
-	0xea41493b	0x60c19727	0xe7c63d8a	0xcbc52763
-	0x7882b244	0xe2da61e5	0xd19111df	0x526d01d2
-	0x4e7021db	0xa13fb9fb	0x23e082cd	0xb426b603
-	0x9cac0cdc	0x44a94870	0xd0adbbe2	0x9b77a80b
-	0xe1845f75	0xa1704da3	0x2d1c6207	0xba3ee883
-	0x0c3089d8	0x0cba7fdb	0xcb069fb0	0x38738df4
-	0x89971c2a	0xfbaeb7e6	0x459e1365	0x45fba877
-	0x02046ea3	0xd9d0bdb7	0x83c74383	0xc248e9d5
-	0xaae85a56	0x33092ec7	0x6bece02b	0x3b7af1d3
-	0xc92b6e83	0xba032588	0x70e61198	0xa5eb1239
-	0x4d9a6456	0x7d3fe964	0xdb3eb780	0x7e188648
-	0x511a6402	0x48c4ade9	0xba7e9153	0x09490df7
-	0x11b5ea7c	0x4e63145f	0x07ca7947	0xc337360a
-	0x2b399632	0x5d1fef78	0x9b1e439e	0x8daa70b7
-	0xf55a59bb	0xc3a8c84c	0x4d18eb22	0x74568737
-	0xf0419b6a	0xbab459a5	0x0cb07a0a	0xeeb8e086
-	0x0a9241a7	0x419c5ce5	0xec841275	0x3ec13615
-	0x49e42b6f	0x2dae6c7d	0x3fc35088	0x1b92ff9e
-	0x573b1cda	0x54381503	0x29a5b7b6	0x82994130
-	0xffb93c4c	0xc0a66aa1	0x68889181	0x0826e555
-	0xe81cdf31	0x740109a6	0xb8835558	0xaa5d9aac
-	0x0d97ea3b	0x89f744c6	0x2b702162	0x992fe0ea
-	0xab3a585a	0x3e7554db	0x9d97ebdc	0x9939bce8
-	0x486a5f50	0x804ccd06	0xff2e15cc	0x67bf77cb
-	0xf9beadd4	0x2da33477	0x18adbaf0	0xdb00dae4
-	0xe727033c	0xd10ce1ac	0x4f8c4a29	0x281bf150
-	0x764e1387	0x8c65a901	0x841521e3	0x31d9dfd7
-	0x1e7ba122	0xe8fd6d3b	0x4bfe880b	0xd2c1c20f
-	0x9a07169f	0xedbb94b8	0xe9cbcd9e	0x33cac378
-	0xa42fef1e	0xf0e5ff32	0xa86b9038	0x7dbec0cd
-	0x7ad1abe8	0x5e3e4e8f	0xc4dfe8cd	0x86630ba1
-	0x02003c6f	0xbcb50d9c	0x65d874b1	0x01a09ddd
-	0xc97d3d65	0x2d02bedf	0x6fc63309	0x214b421b
-	0x72e0a28d	0xd9c8a577	0x1c8665a1	0xd33b4583
-	0xfa004d9b	0x5c2470b7	0xc671fed3	0xe033617a
-	0x5a86c333	0x13388e4e	0x3bccdcda	0xc62fd60b
-	0xcae17379	0xf6d84d27	0xaaa52422	0x5771e380
-	0xeb1feaf3	0x3c28e7fe	0xa0fded4c	0x5f63a3c7
-	0x3b42ed09	0x1748d617	0xbc2d4fd6	0x3416fabc
-	0xc1e60e41	0x48ffe41d	0x4ea5532b	0xba7dba76
-	0x21378ac1	0x7425d0f3	0x426b3153	0xdc57d14a
-	0x54997f9a	0xeda2a56a	0xfcec5ef5	0x6fd7acb3
-	0xf2691009	0xc1a219e3	0x09a82589	0xc6e1792c
-	0xb4674578	0x0aaf55d2	0x23c7e9dc	0x7607d612
-	0x580fc695	0xd24b2629	0x0a8726a1	0x3544e0a2
-	0xc1de7011	0x30982b80	0x9cf4f328	0x02b22d26
-	0x78e33c10	0x2ce6bb5a	0x92280ed7	0x2ce5b007
-	0x64552836	0xda4a7b51	0xa6122870	0x00b28bb1
-	0xb98cda46	0x84cbe910	0xeccb62a8	0xe13c3645
-	0x2f4494e4	0xed0da7b1	0xb8aa8a1a	0x1adcbc0a
-	0xdab03e90	0x904d9041	0xaa8fe377	0x087cf59e
-	0xa123b5aa	0x633c29c0	0x36d915d6	0x8f5cacbb
-	0x8834d1b5	0xa2c12731	0xfab5176b	0xe1888d76
-	0x4875b9d7	0x5747b32c	0x73fc6d36	0x202ffb90
-	0x62900e06	0xa5f2a41f	0x497589c6	0x7ec701fd
-	0x45801f09	0x1833e8fd	0x734acfc5	0x2f65bdb8
-	0xe6add84d	0x4ad6dfaa	0xf59dd63b	0xb2150e00
-	0xed32ddd6	0x370ce8d7	0x5fec9315	0xb8e6ba73
-	0xccb15a6b	0x302a0084	0x9e49e2ce	0x7af3bc8b
-	0x488e6ee3	0xcdbf0b31	0x762ce0d4	0xc50a111c
-	0xd07d6e3e	0x18c391a2	0x1a7a559d	0x10b4b3bd
-	0xd0703a3d	0x4e431eb9	0xf78edbe3	0x896604ba
-	0xc0e8d4c9	0xd42f2292	0x5414ea6f	0x0ce7d429
-	0xbb659e0d	0x46fa830f	0xdad39c12	0x0f65fa5b
-	0xa002e598	0x5408cfcf	0xc1c3a5e0	0x28ca35fc
-	0x52b2b588	0xb76e1f54	0xb6c355c7	0x08e3ba79
-	0xfd89c1f8	0x6ebf03a9	0x51ebb756	0x729e1c5c
-	0x1ed0cce2	0x29733f1c	0x42b76fcc	0xd94022b4
-	0x3efc8ac9	0x3f23eae1	0xa0ccf230	0x9da59cf1
-	0x5f6db360	0x922686e1	0xc9138d5d	0xda43fd20
-	0xe0757988	0xa315c62f	0xe3642291	0xc45d9701
-	0x2c394ee3	0xab92e7bf	0xf6037b8e	0x1f523243
-	0xe91791d1	0x19961c4d	0x35d3b069	0x1596143c
-	0x203bca40	0xd26d72c1	0x94c059c2	0xae0df468
-	0x3b0909a4	0x34aa916f	0xe0c254e6	0xd0969c55
-	0xa9b0b923	0x80a9dd5c	0xe79b8d8a	0x3599f269
-	0x623c20dd	0x41e11b9c	0x40fcee5d	0x65dfa8f5
-	0xbffa7357	0xa5b8f59e	0x2bb8191f	0x226a1b43
-	0x910b6d4f	0x73837092	0xd666f5da	0x14fd4426
-	0xd41a8547	0x6f4e928d	0x8096c2f2	0x525ba180
-	0xc6a28d43	0x960b7cb0	0xb76dacbc	0x024de046
-	0xc8e3c937	0x0217493b	0x1516dc22	0xe19e70d0
-	0x655321c8	0xa46a9105	0x61ec2a61	0x1400405b
-	0xcd0a758d	0xdc792982	0xbd994932	0x6565c8b2
-	0x187be349	0x0afa44ad	0x714870fc	0xede1b8dc
-	0x2c4ac6b5	0x7d9793ea	0xe0bc3c0d	0xaa56f23a
-	0x7fd4e2ec	0x2131ad26	0x2cd34428	0x45e9dec0
-	0xc15b692a	0xae73e713	0x37c5c3d4	0x70ff213c
-	0x4d6322fe	0xa29a9b4a	0xca7d3c65	0x1024df74
-	0x308f4a3f	0x4f48c7d9	0x0c71a17b	0x540441ed
-	0xbc2f36a8	0x2592d7d4	0xbb643dd3	0xb8fb607b
-	0x6b2b339b	0x9a40ecc7	0x59226bdc	0x42a5c04c
-	0x6a1dc320	0x14e3c7c4	0x39cb912c	0xcf5eb477
-	0xa3a43975	0x79f92cc3	0xe9d4cdfd	0x02dc8fb3
-	0x240b6842	0xe9ff7bed	0x8f5269b3	0xc4f44baa
-	0x1f1c74b8	0xb5c39051	0x291cce82	0xfc129a8b
-	0x0fae02cf	0x31b4d4cc	0x1dfe9722	0x093cd430
-	0x96c2a838	0x19b3a068	0xa7ead8c3	0xa2b3b92c
-	0x2e1dc49f	0xe2f84217	0x670e73d3	0xd7c3710e
-	0x94e4a7c9	0x33e063ab	0x35176206	0x910504bf
-	0xb04b61d3	0xbed9c702	0x5d6c4cc3	0x63276a86
-	0x0bfe5143	0x7ed925a1	0xc455934b	0x402a8b04
-	0x01c03292	0x5de0933c	0xd932d260	0xb5b3b5ce
-	0xde53664e	0xeaec4fc0	0x506030ac	0x6fbd8304
-	0x0b0e4881	0x99c16b3a	0x6fc976ad	0xeae57df9
-	0xc53a953c	0xca681bc7	0x905e49e1	0x405d42c5
-	0xef39b878	0x57ded0df	0x56b98e32	0x392ce7d0
-	0xaa7fbfb5	0x6ff550e8	0xf346ae82	0x2b25a8dc
-	0x3ff980eb	0x302aff14	0x1a43c7ae	0x23f8ec16
-	0xf774024b	0x1c4e163d	0x6b6f9408	0x0646b4e5
-	0x2e55bfcb	0x14e3f7bf	0x86fec07a	0xda898470
-	0xd99a274a	0x8630e98f	0x8c843f0e	0xa840c028
-	0x950d7fb1	0xeca930fd	0xd281c9e3	0x29b3aed6
-	0xc419314d	0xa6147b28	0xb504311a	0x91c07531
-	0xe19ac720	0xfa8cfb5c	0xf8158bcd	0x42202a1d
-	0xfff43b87	0xdc6fa0d9	0x8a599eeb	0xac3a8df2
-	0x83ffa50f	0x346a8ff1	0x0947d1ca	0x318a8949
-	0xe409dd30	0xf73ac9cd	0x9504c972	0xa2392b4c
-	0x5594ac9f	0x7a45c3e8	0x181d42db	0x085e24a9
-	0x6cb3e60b	0x3568d771	0xfa96b628	0x945817e8
-	0xca9d28da	0xcd3a174b	0x7f84ca3d	0x90381d0e
-	0x09a6f9d7	0x11396376	0x4d158586	0xcc451745
-	0x9844225c	0xa45b8a9c	0x0c64efde	0x7429ee29
-	0x308c39b5	0xa3454fb6	0xf949f709	0x09391206
-	0x0168257e	0x94e10cb6	0x48e49996	0x92928443
-	0x4a826036	0x9a777b3f	0xf77adfdf	0xc111b354
-	0xa7ece533	0x050706ac	0x91ed3fd2	0xca15baf6
-	0xd1714105	0xb564c842	0x886800cc	0xd57309e1
-	0x38e4fa43	0xb74fe550	0x26f300bc	0x6349cbe6
-	0x4bc132ae	0x310c1d40	0x3353100c	0x0a308892
-	0xea6ab62d	0x0a438e7c	0xb000cf51	0xa21aadb3
-	0xd3628343	0xee7f1a6f	0x3ee28d91	0xa846f25a
-	0xc898e7c0	0x1198f67e	0x2401caf3	0x78d7acfc
-	0xbc592220	0x1efd847f	0x1e3e935d	0xdb9025f6
-	0x41ab6bb6	0x08a10f85	0x160dc5b4	0x4f0ed74e
-	0x8c3db59d	0x34034397	0xe26017c3	0x03fe3b41
-	0xc4480582	0x7c0c85de	0x4957c26d	0x9eb32143
-	0x28676ce2	0xe3627f34	0x71e3afb1	0x7e978fbe
-	0x3b3ee0f9	0xb5ae1bcf	0x474dc4cc	0x470e2114
-	0x2490e60c	0xbb534e7c	0x7a8ad252	0x7cc08810
-	0x9ea23718	0x04ecf4e1	0x732a9f10	0x62c69e22
-	0x5a94fb4e	0xc1da497b	0x3ab3f2b9	0x09ff7310
-	0xd7749df9	0x170471dd	0xaa551e91	0x2d605856
-	0x66a13f75	0x0be4b8a2	0xe64a0c3f	0x288e5671
-	0x5ee690c8	0x9e1c4b10	0x9f055568	0x8c6ff177
-	0xa7229231	0x19e678db	0xd90be83f	0x0cf70d67
-	0x47462463	0x327fdd91	0x51986170	0x3ad883b2
-	0xa32fa5f2	0x82167691	0x74b6c59e	0x3eae0a3a
-	0x569386dc	0x6d67fc33	0xa0943958	0x40b2939f
-	0x334acedf	0x91b6a866	0x5debd880	0xa6f3712d
-	0xbe8ca5c8	0x4b43fa68	0x72b677d7	0xa42b4d60
-	0xc719163c	0xa469fbb9	0xb484def6	0x508ddfd1
-	0x23bf14bd	0x857a13ad	0xf7a47090	0xe6816794
-	0xbf6d3db3	0xd19fe091	0xb9421e39	0x35b184c2
-	0xa5c94a6c	0x13b2b25c	0x5c7b45cf	0x648fdd47
-	0x8832d949	0x0e2380c2	0x2f8e4f88	0xc01022aa
-	0x4dec89bb	0x0a2c5bff	0xa97e58f8	0x304dddd1
-	0x468828ac	0x603da881	0x646ddc90	0x1afa151b
-	0x985bf8ad	0x6e3635d5	0x181268c6	0x420e1647
-	0x913af569	0x14075a17	0x803aba15	0x2a2562b7
-	0x2f0627db	0x52785b48	0x36ce7fc3	0x6057349e
-	0x4affb11c	0x84e82be9	0xa0f60f66	0x1d176256
-	0x9f1dba85	0x2852129f	0x4592540a	0xae083e7e
-	0x744edf82	0x75a1e1b7	0x518fbebc	0xf1828d15
-	0xfa1e31b7	0x88ebf51e	0x0a648385	0x956c002d
-	0xc8b660cd	0xa82eeb58	0x0754bcf9	0xc4873df1
-	0xf06c843b	0x7e5ac181	0x59661ea5	0xef2ae542
-	0x0fea9691	0x9493a352	0xb401f705	0x85573914
-	0x4e1eefc9	0x45e51c5f	0xd713688c	0x97efca3f
-	0x292d0e73	0x8db44fd8	0x9f4479e0	0xc049ff9a
-	0xfac5ddbb	0x4d610fdf	0xa9e01cdf	0x93b4dafd
-	0x925004b9	0xb0796ea4	0x7e166ac1	0xd030c4ea
-	0xa9f34c73	0x276cbadb	0xf3b9c282	0xa5bd6a69
-	0x53df3f11	0xded46173	0x70bff329	0x0ddd0e77
-	0x52e4a782	0xf01b024c	0xda90618a	0x34a2dd05
-	0xc144d1fe	0xbaca12a5	0xbbd28cf1	0xc54d84f5
-	0x0e7cb67b	0xe009e900	0x23657441	0x2214b4fe
-	0x37693ee7	0x62e093d0	0xf79ca670	0xf1bc6cec
-	0x1b91f787	0xc9d234c4	0x2a193a4c	0x8c2bfaf4
-	0x75f4514b	0x03501d9a	0x5554de35	0x5ff35a26
-	0x670ad976	0xbc8151eb	0x725fb971	0x5768e86f
-	0x7fdcf5ad	0xe814f3ce	0xe8b9510a	0x55bf074a
-	0x415fc288	0xa1a360c5	0xf5fef671	0x2d6253fd
-	0x7fa09b81	0x2bb2e018	0x7159e648	0x10d5d59d
-	0x462047cd	0x77583e64	0x47f1074c	0xc3c0e0d3
-	0x023a55b5	0x4ad55057	0xe6d4b9d2	0x9cdd844f
-	0x87eff8f4	0xd95c1e55	0x7499004e	0x2a43a598
-	0x0c1472b4	0x33c90a5c	0xc4703c62	0xf293e2d9
-	0xc3153c7e	0x6eeffef9	0x115e14ec	0x4ad27157
-	0x888d87c3	0x33edc70f	0x7c38ce66	0x61c10a52
-	0x5db41c48	0x8e309060	0x7b847b63	0x6b619cd1
-	0x12855e03	0x52c3281e	0x704f969e	0xf9ab7862
-	0xb143fc54	0x1ac23fd5	0x89dcd807	0x40a7ffc7
-	0xc84245b8	0x0248d94d	0x29aca158	0x92d7b241
-	0x751588ff	0xe8203587	0xc5bd7cdc	0x9de82608
-	0xb075493c	0x5d43c228	0xff6a5345	0xa64cae5c
-	0x4a1a9a26	0x08c60b16	0x9399ba46	0x3f535d1c
-	0x3b9a6ab1	0xa446115c	0xa77bd99c	0x2431dc72
-	0x729a637f	0x13f960d4	0x230d4e9f	0x0c608153
-	0x9b9670fc	0x72494838	0x14832ade	0x65aba892
-	0xd6434455	0x17697982	0x68b9bb34	0x1d700b3f
-	0x6d0dda39	0x30e0d15e	0x87de41fa	0x9fc55b16
-	0x0f5730d3	0xc3ea8127	0xeee64f5f	0xa02c5baf
-	0x64e18d74	0x31de5660	0x5cf8d724	0x6c07ceca
-	0x409e862a	0xd4ee7999	0x90c22c99	0x59cd395f
-	0x09c36563	0x1993b09f	0xb0c4e064	0x8d6870a5
-	0xe2e8e337	0xe8bef0cd	0x708d869e	0xdf808519
-	0x6fa61e32	0x27161ea8	0x063c783c	0x2aa55c1a
-	0xa6fcc8a3	0x918b284d	0xbb7870b9	0x788102c3
-	0x3e49edfa	0x6c5eae4e	0x1c9fc361	0x554ca60b
-	0xa08364d3	0xa7bd4442	0x204822a5	0x000b71a2
-	0xd4dff005	0x43265901	0xbdb99200	0xc438e254
-	0xa4982e58	0x02812101	0xfacbff1d	0xeec56aaa
-	0xa5525774	0x21ada574	0xffe2f703	0x15d30ea7
-	0x600696f9	0xc7ff3f59	0xdb57c175	0xa16f78df
-	0x54a15622	0xe3742dcf	0x06d32994	0xd48463a2
-	0x44c7c25a	0x41d6ded1	0x3b314de0	0x09992482
-	0xbeb183c5	0xa0a65c27	0x842075b7	0x9b97e3c6
-	0xd9545fc7	0x16d00629	0xd85640df	0xe79e694a
-	0xe818d277	0x1c3d4623	0x23a9a926	0x83ac1b3d
-	0x39e890c8	0xb3738b84	0x54b772ef	0x74518f0c
-	0x7190098e	0xe26aff75	0xf6237011	0xbd3400fe
-	0xda1b8fa6	0xdbf5566b	0x5155cef3	0xddbf1973
-	0x34e2cb2e	0x535fd6b8	0xbfd337aa	0x6dd1fb0e
-	0x52b04fbb	0xab5eca05	0xdb740dc1	0x104e6131
-	0xbf4dcb75	0xaeff3524	0x4257c6b9	0xbf1c8cbb
-	0x0a69ed82	0x90d991c7	0xea075cba	0x5e3c8330
-	0x823116f8	0xba8f8a2d	0xcb98a1e9	0x8b2655c6
-	0xd2f11133	0x3422f3ba	0x3e3a5742	0xdb9714fd
-	0x91701f60	0xeba19983	0x8bf9f157	0xec87cd03
-	0xb63260fa	0x207c345c	0x0c838d5a	0x736415ba
-	0x9638ab07	0xb32c72bc	0x304d191b	0x7775adc8
-	0x57ece662	0x0467bb66	0xb7cf80e8	0x4c635024
-	0x176946c3	0x29cba0ae	0xf214b3f2	0x6e727126
-	0x87b3747c	0x4c19b86b	0xfcc66fce	0x86681713
-	0x636387f1	0x589e78f3	0x2e8abf1c	0x22c828f7
-	0x99653c62	0x8e3bd31c	0x79187a73	0xc6d0e5e2
-	0x8005a045	0x78a38c60	0xe1e8ff4b	0x1102d320
-	0xaaf4ba7a	0x7223d041	0x45f73e81	0xaf7168af
-	0x218ab3ae	0x8b1956a7	0x4db00173	0x482c3bc2
-	0xd982b945	0x4bd7757d	0x0c5ef18e	0x74e66de3
-	0xcf421ae1	0xf2ddc098	0xcec27e0c	0xe79e711c
-	0x6f76e136	0xa8d72245	0x196390a6	0xbf56633d
-	0xd1156298	0x5712cd8b	0xaed801ae	0xa345fab5
-	0xfde1ba97	0x437a0b29	0xfc5628a4	0x93acf698
-	0x83ce0bff	0x212f15c3	0x723ef016	0xe793bd50
-	0x8bc51b39	0x42f17ad2	0x1df73878	0x19af3c24
-	0xf55b6f93	0x506138d0	0x164c542a	0x8d4e1a26
-	0x6c606f83	0x6fbebdf5	0x0e4ad76e	0xabd88e6b
-	0x0e0d74e6	0xd139e08d	0x8b6cf03b	0x04a527b1
-	0xe619c7a8	0xbf0d57f6	0xb38a5f5f	0x3f328013
-	0x374c0a9d	0xff36910c	0xe950a494	0xfc477720
-	0x37bd9390	0x4667497e	0x724eb66b	0x86bda8f7
-	0x52efc959	0x32d5c2bd	0xddbb49ca	0x9c1eef2c
-	0x508d8b81	0xc33d7001	0x360ae3c7	0x1197f6c2
-	0x25efc933	0x4ad234a5	0x9e9c8658	0xc16d4aff
-	0xbc428573	0x30e8b4c0	0x728c2c48	0xf34e1e70
-	0xd62187c5	0xca869f89	0x34685a33	0x85d9b877
-	0x9f77605f	0x93724d34	0x5fc8e8d1	0x70dd81a6
-	0x643e543b	0xe4ad6c73	0xd6b4e5cd	0x387519c3
-	0x719d8c6a	0xb2e0565f	0x02235c90	0x230c9b5e
-	0xe76841a3	0xc2833be0	0x4dab4a72	0x0ae6c0a9
-	0x0b5e12e2	0x4cda3610	0x954b6ff8	0x6d89a683
-	0x3583e633	0xdc540da7	0xe2955deb	0x0f290d9d
-	0xb01e57c4	0x977f4588	0x24b95f0c	0x45529128
-	0x4528b5ee	0x27511439	0xd088d9bc	0x7c471853
-	0xf03b8455	0xbda4a828	0xf49736df	0x50eb17c3
-	0x2affe0e6	0x6727858c	0x6500b8f0	0x0483aa89
-	0x0e1f6a41	0x72666733	0x85617ce8	0xa0c86838
-	0xbccd2eed	0x06e8462d	0xc947bf5c	0x4d2d0a53
-	0x02e70008	0x5039a596	0xb0118cc1	0x690ba325
-	0x057ca95e	0x032cc1ba	0x3dae2c88	0x4eaa740e
-	0xf07b09b5	0x6b2c2135	0xeca746b7	0x76019533
-	0x4cf477b7	0x31848299	0x6b5c7df9	0xc0db5ff1
-	0x7cd3e08d	0xe25fa562	0x260d66a4	0xda30cf2c
-	0x14ab6c70	0x029a8dd5	0x7cd5fe2d	0x98ea5852
-	0x555cf635	0x6c72ccbd	0x64120bef	0xd9e19613
-	0xf26ac6e8	0xafea03a4	0xc14a11d7	0xb2f8420e
-	0xe319634a	0x8a8fedd9	0x6ce0da89	0x74269f31
-	0xd7e0d776	0x86ae9513	0x48bdea80	0xb2e4c581
-	0xab25566e	0x9ccb71a5	0x7cedb09f	0xd2bdade6
-	0x39c96ad5	0xe8ebbeec	0xac8a2e2a	0x915be930
-	0x95e7c98b	0xd00e1d3b	0xdacd08ac	0xd9f515fd
-	0x45cd3946	0x828a2cc3	0xfbe1bd9a	0xc5e1ebcd
-	0xac69128c	0xcd6423ba	0xd8653b60	0x48f0614f
-	0x0c1ebbbe	0x7ab89792	0x9a4b0097	0x2bda854d
-	0xf17ab2c9	0xcde54eb9	0x4b53a030	0xe2399c4c
-	0x19454a2f	0x473fe390	0x3a42c16c	0xc4c106a9
-	0xf5d96e73	0x2ab4078c	0x5d20e7ba	0x47880aab
-	0xff5e0d78	0xa374bdc2	0xc17109ea	0x39fce648
-	0x00821cbe	0xc54a60ee	0xd753386e	0x7b28fc16
-	0xb6309bbe	0xaefd0548	0x41168500	0xee5989a3
-	0xe0177f09	0xc9fc9eb6	0x09a6e188	0x45776a0d
-	0xf19a4830	0xc6774893	0x814b2e43	0xf8be5e3c
-	0x22fa8237	0x75c98f46	0xb1c52edc	0x443d54f8
-	0x6a1a886e	0xc7f33598	0xaa794644	0x685e5ca2
-	0x97a735ba	0x3c1a391c	0x13f6f89a	0x660d7041
-	0x333c3eef	0x40541bb9	0x5c3724d5	0xc348023e
-	0x89791dd9	0xe72fba89	0x5af98b2c	0xb534fd29
-	0x64d0e6b1	0xa578e77f	0xf311215e	0x634cc8cb
-	0xbc534e51	0xdfce3ac7	0x90f88f51	0xb3f7dd48
-	0x20b3e0ae	0xf4456e85	0xacb3925b	0x2eb3ce78
-	0x37e61d82	0x724b9cbc	0x1462d9c1	0xd3f49dc4
-	0xc1ffcc00	0x7c3e3f86	0x6f283bf8	0xf43671ab
-	0x90cbfb35	0x55390829	0xc8fd0d31	0xc687c45d
-	0x724ee656	0xfc1eab3c	0x3c8c2f04	0x3caa3af4
-	0xbe220358	0x4d5b49a2	0x12cf4893	0x867173fb
-	0xccd4b513	0x7c94a1bb	0x86c42c18	0x2b2070f3
-	0xd2a70638	0x9d7c07e3	0xd02ed59e	0xd349488f
-	0x1e85754d	0x333db889	0x0d0defdf	0xef282e45
-	0xac3f6c29	0xd65a68d1	0x5d0914e4	0x395ec78a
-	0xb056aa6b	0x4d98d059	0x7ae08f88	0x25c923d2
-	0x79670f38	0xa881d62f	0x89cd5015	0xfb01da43
-	0x5861244c	0x05e201eb	0x41d71eda	0xb2babb53
-	0xc3845fb3	0x1f3b5c56	0xde6c10ac	0x73adb998
-	0x714aac3f	0x4ad9fc65	0x3acdd014	0xeb319d58
-	0x48842806	0x47ec1040	0xbfdf0052	0x3c478ec6
-	0x83b43a0f	0x9e727e69	0x9f4d5925	0x9f45c13e
-	0x30b8572b	0x26edf8cb	0x577e8b9d	0x9b98d7b3
-	0xa44a9bbb	0x903e39eb	0x51226dbc	0x933a52b7
-	0x14c6dc86	0xbc24db59	0x21054454	0x98fc5fa6
-	0x2c9d8606	0x19178173	0xeda24205	0x90dfaca4
-	0x21d562ad	0x7e3ad05e	0x2b3a40a4	0x46513f35
-	0x0d13a598	0x8bf71ca2	0x6a36c430	0xe66f5587
-	0xc9f13bd6	0xb6534a8b	0x8a3fbfd6	0x38cdfe6c
-	0x1a1c89f8	0x6d782709	0x7919c451	0x6ccc96fa
-	0x334029b2	0xa638356e	0x001e709f	0xb2132b06
-	0x483f1933	0x189ab8f9	0x4ba0ec13	0x490aee0a
-	0xda63f1fc	0x5679d38a	0xcf1e92f3	0xe7257fbe
-	0xfeb733d7	0x0704860a	0x34ce2032	0x663b948f
-	0x544cc928	0x8c23d5aa	0x67986469	0x93f9ac08
-	0x4fa9a13f	0x9eb311d4	0x41a64161	0x29d1050a
-	0xa5285c24	0xb53d03a6	0xc5de26f3	0x7876d1c5
-	0xbdcdcb4b	0x79d1196c	0xe9890732	0x3e58a8c0
-	0x874f03c7	0xfdfc9cac	0x5d57fa57	0xa3ef01df
-	0x47bcff48	0x8beb1aae	0xf4bb4f9b	0xa5c83b64
-	0xd69ab0ce	0x40f6691d	0x2eb8fb7d	0x22640f8d
-	0xac1ba157	0x3687d705	0x7fac8727	0x4ad75cd8
-	0x7016d2e9	0x25c36c08	0x7e4248ea	0x292bda19
-	0x2acf589d	0x0ef7726d	0x835f9e62	0x3f9a1973
-	0xbb6d2588	0x078ff6b4	0xaec22b5d	0xc740501e
-	0xa2ab115a	0xea993e64	0xa0cc3ed1	0x934e4e0e
-	0xd732b66d	0x5fd28c47	0xe4ccb898	0xc6a101c0
-	0x78274bae	0x625df6a1	0xaf774052	0x3b7c08d2
-	0x6180ac39	0x3e5aa769	0x6ec74578	0x6b5d27b9
-	0x98e58a17	0x119dd7d4	0x39429c5a	0xe3d5b391
-	0xbb8fddb8	0x5929801c	0x68cef71c	0xc36fa301
-	0xeace4850	0x29f4f97d	0xa58bad79	0x2823998f
-	0x0fe1352b	0x5960ded0	0x69308816	0x0d7e33c8
-	0x2fb13bfa	0xff6a326f	0x69cb631a	0x839ea2a1
-	0x528a8065	0x34cbebfa	0xd4432cc4	0xe13b550b
-	0xe046569f	0x87b41fb1	0x7751107c	0x0ef6e60b
-	0x856ffc50	0x11995683	0x77c2ebf1	0x4dec97f9
-	0x3a28ebc0	0xb7bfa04a	0x40cdceb0	0xd559dd06
-	0x61c2cd6a	0x8a906fa2	0xd55f43d6	0x7fb3ac35
-	0x8cea4e81	0x1d359c2e	0xec447c57	0x3414f7f1
-	0x18243b84	0xdf76849f	0xd753044a	0x7af2d51e
-	0xaee26ecc	0xae6946b2	0x7478c675	0x88b22f49
-	0x4de13fc9	0xd35c5956	0xeebb60b6	0xa15b1736
-	0xa6e78d78	0xfd5e30b3	0xb4fade2d	0x964eb418
-	0xe9035f51	0x22ab8242	0xfaa64053	0xdfe03834
-	0x47beb588	0xb82a0887	0x11182e85	0x2f2f9a67
-	0x4b612f11	0xae04077e	0x7f783c25	0x883a34e1
-	0x32d43beb	0x6f0536f7	0x85c1537e	0xfb26199a
-	0x45417e88	0x4af2c8cf	0x0a334486	0x2a3e6838
-	0x31b8725b	0x63d64541	0x7e516a0e	0x7e42e766
-	0x4cf30198	0x68abecff	0x7fb49c43	0x8f5b558b
-	0x32b99abe	0x67337248	0x224c3411	0x4e7c41b7
-	0xd3aee3a2	0xca19e704	0x2a430b7d	0xe9aee453
-	0xf4ce492d	0x48fab2a9	0x42ec2076	0x0182cea5
-	0x8a6373c7	0x18f41b5d	0xdd062fd5	0xb1db44a7
-	0x285ad917	0xeaaabbd1	0x359b1b23	0xcc123c8e
-	0x38b70cb9	0xb01ae722	0xa6e72010	0xb647530e
-	0xf9651d41	0x366d6d0f	0x4b656a6d	0xd36637f0
-	0x4b5ab8bf	0xc22fdb1e	0xc57c8250	0x799f4e60
-	0xb55bd50b	0xe8a3432b	0xe752e4e0	0xd0c86482
-	0x122991f1	0x5bec598e	0xbcb89abd	0x739f61d0
-	0xd230ae2a	0xd0b99c05	0x2a998a6d	0xab715831
-	0xb7dd1939	0x57db0ea7	0xed1f4952	0x49274caa
-	0x35e319b0	0xed2c9cb3	0x601caa20	0xfe782688
-	0x64b6d30b	0xcd5c325c	0x2c836157	0xa3552f79
-	0x188094db	0xa42dd7e8	0xc09c2dda	0x02d98d8d
-	0xed270d28	0xb0f38ada	0x5d7b4261	0xb41df8d8
-	0x7341b6ae	0x024ce90a	0x0727ae4c	0xa8dd3a0d
-	0x390f84d5	0x43f5bd12	0xd11fb61f	0x6fc330e1
-	0x7f2d7fa6	0xf758a4e0	0xceb1f3c3	0x2f341836
-	0x98fb470f	0x5bf68e58	0x1917a5b2	0x75f33be6
-	0x16e22316	0x8aa810a0	0x1fc6c9b2	0x22179249
-	0x3de701e9	0xec48d8b6	0xe85248c1	0x314ce9c1
-	0xddeb2f47	0x0187909e	0xaa755f62	0xb2019460
-	0xb2016a9c	0x91f789be	0xe5925997	0xe4864300
-	0x1fd13759	0x0ad97c1d	0x7cf08c01	0x7eac2dd6
-	0xcf61a7f3	0xaf9e108f	0x939a2fd9	0x0cb48e78
-	0xe6ea1a8b	0x0b968273	0xef1c9310	0xf60e82b7
-	0xe76e9bed	0xb8fa9668	0xf889765b	0x0e51eed6
-	0x6b6566ea	0xa8f7e2c5	0x9d8c283a	0x879afdcf
-	0x944873c5	0x58afcfa2	0x2e60600e	0x59666667
-	0xc812b833	0x5842d0be	0xdbdc0829	0x786bcff9
-	0x5857ba06	0x6968c729	0xf5447949	0xdb1ceeb0
-	0xaf04d1f5	0x30614f7f	0x3e80fdc9	0x8a6e1ce0
-	0xa267d7d5	0x8896143e	0x24e59072	0x68122e1d
-	0x3ce24add	0xda677bdc	0x8c3f74ef	0xfa60e825
-	0xf5c136cc	0x2cc5f249	0xa1c6b642	0x47a2305f
-	0x52cadbc8	0x4d0c32f6	0x07f4d344	0x1f496d59
-	0x5699b970	0xb8cbe564	0x707f7a2e	0x818bfd45
-	0x800a8be0	0xd3de4f1f	0x62de0a3a	0x6b342869
-	0x054daa7c	0xc72b945f	0x1612f126	0xdb4ad492
-	0xa28c467b	0x78542799	0x61607353	0x39f1c142
-	0xebf30ad6	0xabe076d0	0x5125cce4	0x5584149c
-	0x65fa33f4	0x878a918f	0x8c7e5c37	0x334c4284
-	0xbfd816e1	0x0f0f3460	0xd54519fd	0x03701ca9
-	0x64885229	0x00e841d0	0x756a9472	0x0c16c5f6
-	0x65560e81	0x129b6995	0x91c9dd1e	0xe9730dae
-	0xce47f2a2	0xead8a0ee	0xcd58078f	0x7ca2df31
-	0x0ebbf13d	0x3c74e061	0xb7f3980a	0x0d354b88
-	0xfd8db90c	0xec6726d0	0x6bfce0f5	0xea98b7a0
-	0xac5ddde2	0xb372a14c	0x47b09ed5	0x531bd5c3
-	0xcfaf5a0a	0x51d6394f	0xe9efdfa8	0x37c79445
-	0xb13ebf62	0x46715efb	0x31e6a0d7	0xfa48ab48
-	0xc6552f2c	0x3067b978	0x0afa4ab7	0xc2c17055
-	0x68dd427d	0xeac01e43	0xe90f12d8	0x6d97c3b1
-	0xe0d339b0	0x2f3c84cd	0xca3eb3b1	0xbc0d86e1
-	0x3566f657	0x083374b0	0x199c677f	0xa4a8a4d3
-	0x224dd5a8	0x8f304abf	0xe1019878	0x9b290d4c
-	0x5cef7341	0x59ff7e48	0xc91663ac	0xb0b1bede
-	0xe9d8a9a5	0x8f34cb70	0x588d00d6	0xb7fe69b6
-	0x29036caa	0xd21d7998	0x4edc3ee9	0xdbd94f37
-	0x99c63455	0xac94efda	0x545635dc	0xb787b5e1
-	0x8228666b	0xc7cd8170	0x4f1924a5	0x437884c1
-	0xfa9236fb	0x1f0f949c	0xd1dc0597	0x56082a24
-	0x04e51919	0x05dd926f	0x06d264ac	0xaa672d38
-	0x5a3e396b	0xab48a57c	0x53489bd1	0xb36b3ba2
-	0x55164db6	0x5b52c5f9	0x68aa8b7f	0x922ce829
-	0x09e6e5bd	0xbc488a86	0xc0fb6dab	0x98e7754b
-	0x4c9ad717	0xe3ae7045	0x0b498742	0x80a4384b
-	0x0dfe0b99	0x70eab3b9	0xbee30b9f	0x4237ca85
-	0xe67662b1	0xdae3dce5	0x47c84a45	0xf72febf2
-	0xa58dfdc8	0x77ae88d4	0x038c76b7	0xae699990
-	0xf5f10de7	0x65d4c59a	0x004a8b4b	0x67c788ec
-	0x71c918d7	0x0ec70171	0x7041de53	0x43591e1c
-	0x807242f8	0xa27fe146	0x0055fc7e	0x2f08467e
-	0x5e04a068	0x54dab094	0x4f6e8c7a	0x20ac2825
-	0x47949a42	0x9181486c	0x038e3132	0x7c1c51be
-	0x97544f38	0xe2d27588	0x64889c21	0xdad9a1a9
-	0xf1d328a4	0x7d47991f	0x2faa1b85	0x2430cab0
-	0x0e849f91	0x213686c1	0xa2635f37	0xee7983ae
-	0x87871273	0x6867d60f	0x04cb29ae	0x4e0ee4ee
-	0xfbd2666a	0xfd7fe017	0x870b26ee	0xc42e104b
-	0x78919117	0x19590e66	0x9e1a5039	0x9609471b
-	0x4057fde6	0xc1f27544	0x30af8a8b	0x2ea267a6
-	0xcfd886b6	0xe632b1f3	0x3f10bc50	0xf38a1bd8
-	0x7ae1e284	0xe3876d7a	0xb4ce64f8	0xf74b4100
-	0xa97686da	0x17ebacde	0x2ab068e8	0xcebd1076
-	0xee8f81d8	0x0d394301	0x6f32c277	0xa926dc1c
-	0xd5d2ea55	0xdc016b6b	0x6a96022f	0x0143e314
-	0x23836eed	0xa3e18369	0xd2a155bd	0x8022cef6
-	0x080b32a8	0x74ba38f0	0xd1ca2089	0x7c80219e
-	0xf536af16	0xd7a337e3	0xa33600a6	0x39c7754d
-	0x7d215312	0x1dd65026	0x8cb496c7	0x89dfd508
-	0x9f945a1c	0x45caec32	0x020a1edc	0x5917baa3
-	0x296b4b1a	0xcfaa2023	0x63e7a0e5	0xc48b19ae
-	0x78d98b1e	0xc5d6be01	0xfe4ef13d	0xea6c9915
-	0xb8190f09	0xf1793822	0x9acf1593	0xc7710fa0
-	0x6b9a9f3d	0x0220ee2a	0x5d63043d	0x7292a0d5
-	0xba9a1682	0x6f1e7c19	0xed7cc52e	0x6bb89645
-	0x4370269c	0x9cb2c1a1	0xa7135973	0xfd1f3bbb
-	0x50e6eb67	0xf2b9bd22	0xd891f6a7	0x4e0a7449
-	0xc3dc0005	0x878e3333	0x3b4b8686	0xb215c65c
-	0x5d8d24c0	0x8d203496	0xff20d243	0x0a6c1253
-	0x2385c79f	0x52e8d6dc	0xda4bb8b7	0xfab66d97
-	0x05a4a795	0x6876e856	0x9dabedc2	0x53550c20
-	0xb3bba16e	0x853bf1cf	0xb85b906d	0x3f374468
-	0x62e07c2c	0x6903a495	0xdb119586	0x07e91546
-	0xa8388945	0x5a4e1dda	0xf054cdad	0x4b052880
-	0xe9bbc9ec	0xe3555e11	0xd4d6479a	0xcad6a986
-	0x31d9c4ae	0x510ff951	0xcb2f3164	0xbe283401
-	0x0c390b9e	0x0c9cb487	0xe64e8ffe	0x611a63c0
-	0xa1d700a5	0x3f864335	0xd1fdf32d	0x7a3aeb09
-	0xabbc8c4d	0x4d703604	0x6532c8e7	0xccebc529
-	0xf3c0f514	0x1567f19d	0x591abf6c	0x6c7fc459
-	0x0858b061	0x092b2489	0x33c1a9cd	0xd6cc8e2e
-	0x7c1ffeb3	0x3f45cf40	0x1fbcbd39	0xc6f0e628
-	0xb88bab4d	0xc699de42	0xb62d850c	0xf71a6768
-	0x2866b891	0x13093fcc	0xc730c502	0x2deaeff4
-	0xb1bc8535	0x4303997b	0xb31ebd2f	0x82debe94
-	0x843fa02d	0xba29f80d	0x03cb58c1	0xef1d2017
-	0x0b5aadf0	0x6c5c3286	0xf084faeb	0x8b96a39b
-	0x67cb38f8	0xf686ee62	0xbfdc22a1	0xee3f779c
-	0x8ec73c8c	0xb448536d	0x67bb5d68	0x4369ea8d
-	0x4b5367cd	0x2dbbc0be	0x8f5986e7	0x798c8392
-	0xd3aac078	0x0081c0bd	0x94d9d70b	0x40bdeae8
-	0x6b528e89	0xb0713745	0x063e535f	0x7d696463
-	0x64f0666b	0x68a82e8c	0xc749dd19	0x875883cc
-	0x3d35728d	0x4c0e5d8d	0x135f11b3	0xb649b37f
-	0x8aead5cb	0xdfbd573e	0x563bf917	0xcdb75f08
-	0x024b93fb	0xc6477eea	0xd88ce51d	0x95f7d77f
-	0x0b561446	0x2fb6992c	0x4b48c8b1	0x940da60f
-	0xf1be60b9	0x66d8641b	0x17a0ce15	0x49d22f40
-	0xb8c494da	0x91930bb1	0xcd317991	0x4c5b4c23
-	0xafda60eb	0x212c9f04	0xe4732f4e	0xf731ae57
-	0x19165943	0x2d9288c3	0xc9c45dd3	0x2e05b148
-	0x225a256a	0xc0249ea2	0xe96733d1	0x56a6803f
-	0x20458549	0x28210fd6	0x13da740e	0xf0f0be41
-	0x029c1fa9	0xb1daf3f7	0x1bf0c9aa	0x6f0d5221
-	0x998b3616	0xa02212a3	0xe76b39b1	0xba0823e6
-	0x146da6a4	0x858a3e0e	0x58e75b32	0x732f75ed
-	0x8d88385e	0xe0e7ed55	0xc08ca86d	0x97e2ef67
-	0xbb048208	0xd384c40b	0x8595bc69	0x65581977
-	0x7b091c4c	0x60bfbbb5	0x23bcf38f	0x32e4621a
-	0x7f790d95	0x72c3267c	0x34dd0c12	0x27438915
-	0x5619893a	0x09d55159	0xdba7eef9	0x7413634f
-	0xf4883417	0x59a2f28e	0x491f5779	0x0c138f9c
-	0xc52a03de	0xcb1f92d0	0xb6cfcd21	0xbba95c83
-	0x5302f12d	0xfc4c030f	0x18722dde	0x131cd3b1
-	0xa19a1cdb	0x103d9216	0x403e45db	0x5cab72f3
-	0x17e18f5c	0xbad9d0d9	0xd0d2e010	0x798106fc
-	0x3abace6c	0x2c3131c6	0xf9529b61	0x27cfa158
-	0x8890951f	0x87ccf0f3	0xa112b1e8	0x3e0eb033
-	0xd7469e14	0xb6ccd2ca	0x3d238069	0xb32f057e
-	0x8d2c939b	0x18d8aa3d	0xdb3cdb2b	0x861ba258
-	0x46e7b170	0x4830d004	0xeea1b8b2	0x44e29b51
-	0x0cdd8591	0xf93ad973	0x9383c44d	0x24e323be
-	0xaaac87a1	0x84eb09d7	0x1f66b641	0x303f92b4
-	0x81a63a86	0x516321e4	0xe33dfe2e	0x371a4624
-	0x8f936425	0x596976ca	0x7b1947ef	0x83a9db29
-	0xc5f337b0	0xe4d51b73	0xb35b56ce	0xb9cac5ba
-	0x51705ecf	0x93e7d63f	0x5ee7d916	0x479f25b9
-	0xe90bb406	0xfcd6e78d	0xbd8ed9b7	0xbca7c8b7
-	0xdf95f4cb	0xc28baeba	0xb4534bbb	0x98b4f840
-	0xf2218357	0x726e4f81	0x7591ebc4	0xc0523d15
-	0x6bc82550	0xedfbcfa0	0x57280f50	0xbe7e420c
-	0xd1152012	0xbf3ee0a2	0x11825710	0x18e728d1
-	0xb8af00b5	0x2d1e940d	0x1c9ade8f	0x923ed269
-	0xfd8c2580	0xf6477ff7	0x476a486e	0xd09c18dd
-	0xaede7959	0x55fb68fc	0xe5692f7f	0x0bf4bd18
-	0xf5fede2b	0x07bb05e7	0x1bb8ec54	0xa46bba84
-	0x15051826	0x762ce6ae	0xa0246225	0x35c38cab
-	0xbbd00a24	0x8205d3f4	0x4cb33ba4	0x293013fd
-	0xd4f67965	0xe9c1951b	0xff108efa	0xb8e68197
-	0x36d51e4c	0x2959f7f9	0xf2e4206f	0xc9973e09
-	0xb61ce3fa	0x9543be90	0x63642668	0xcaaf02be
-	0x7346a8eb	0x4111f5b5	0xa453cc2b	0xdb524b49
-	0x4d528cfa	0x71e5fc4d	0x62cbbab2	0x8423f40b
-	0x1a4db908	0x560c41c2	0x03982d88	0xa49c553a
-	0x529f6acc	0x82dae294	0x6c5dbaa4	0xfb4ae1f2
-	0x36e31345	0xb5cba88e	0x3704c623	0xe35245ea
-	0xa412107c	0x35faf59c	0x08ceb649	0xbd67a6b9
-	0xe37ddfdf	0x21303abc	0xb7de5e8e	0x88d9366f
-	0x49bdd73c	0xeca0cd02	0xfe1e01eb	0x30a56c2d
-	0x0cae1f5b	0xe77521c7	0x5ca59eaf	0x1288aa13
-	0xc60bc96f	0xf7292504	0x2b037e4d	0xf34757b4
-	0xedcdc492	0x39044092	0x5d710fbb	0xb8658511
-	0xe23e4d57	0x595d4d3f	0xc0f80105	0xfe952879
-	0xe81e2cb6	0x4f5a8fed	0x3bd0d700	0x211887d3
-	0x6ea6e78a	0xe066640c	0x0d29c725	0xdabbeedd
-	0xd2aca4d4	0x65c4a06a	0x6645b62f	0xb1de0cd7
-	0x022e07ea	0xe9f9248b	0x0a2251da	0xdf34159c
-	0x7894bab3	0x72e465eb	0x37448fca	0xbfbc1911
-	0xa79e4938	0x48b83ec3	0xb9c6833f	0x19d24abb
-	0xa434e777	0x77947277	0x2309612e	0x546a6ebb
-	0x4c96447e	0xab918dce	0x5075ba1d	0x0aa55a7c
-	0xadcce25b	0x837819d4	0x90d62a9d	0xf116ede5
-	0xb056cc7f	0xb036353e	0xb7c1af8d	0x014c2cd1
-	0x356f1593	0x008c2634	0xf7cd0cb0	0x02b0576c
-	0x5364c954	0x5b40800b	0x60054bd7	0xef31bb60
-	0x1a85370a	0x458c4348	0x435b8da2	0xd8df0e06
-	0xde0cf1b8	0xd3c6171c	0x0bc14938	0xdc874128
-	0x694f96cc	0x7b6687e0	0x9ca59f25	0x617aea60
-	0x63ebcc8d	0x4bb44d00	0xce46d01c	0x4ab07a75
-	0x64757638	0xe5903811	0x3562895b	0x760627ce
-	0x8939cc7f	0x225db9b1	0x730062d9	0x7a5a7a15
-	0x49678fc3	0x8620cb95	0x9439dee1	0x501f2cae
-	0x3d08a33c	0x352de5c1	0xe7b24442	0x6ec76b79
-	0xc575a1e8	0xb7024b20	0xc9dbb9f0	0xfe2303c0
-	0xba3716ae	0x0cf37bdc	0x1c68a4a7	0x7ba0d609
-	0x43003a93	0x17dd96c3	0xb884aa37	0x15b2d65f
-	0xf6016133	0xd1fd7e04	0xc0a22822	0xf8c26247
-	0x818c35fa	0x4e2b3605	0x83923c44	0x4ddd4397
-	0x6faf6a11	0x50438703	0x67796dac	0x3443b780
-	0x484f5bb9	0x8ead98ea	0x472ae543	0x94b0b17b
-	0x1307833e	0xcb0e8286	0xb02e1ab1	0x36a89f9a
-	0x372e82f0	0x84741303	0x111ad8ae	0xb1eeacb7
-	0xd7d8ccd6	0x5f779f32	0x0d65184c	0x0a398467
-	0xc07c099f	0x0704ffdc	0xa10b2f17	0x4c926dc9
-	0xd80829ee	0x0821015a	0x512e6d0e	0x57b514dd
-	0x509cdfd6	0x7e08ef24	0xf536c381	0x65483797
-	0x439311fd	0xabed0f15	0x51a372c2	0xdd24c506
-	0x839cdd63	0x0c21c8dd	0x513d9eb4	0x43c6a95e
-	0x5d543848	0x64843a49	0x687bbf41	0x93d3bce3
-	0xcf85eea3	0x5f3a6fc4	0xe7b45979	0x4c5848ce
-	0x924188e3	0xbcbded12	0x0cc18c86	0xf3fd5723
-	0x148dddb6	0x77cb388f	0x30afd47c	0xa306c453
-	0x1da0b234	0x0f206f46	0xf25975bb	0x9c75d28f
-	0xc60ad2fe	0x0067c5b0	0x497a1617	0x81d330e6
-	0x2c5362ef	0x86a54b1e	0x80ad976e	0x0a86ed37
-	0x1183b84e	0x2e2ce6e5	0x10b02598	0xd56fb0b7
-	0xe3e0bca5	0x755d2333	0xe0be1b85	0x6c976f4a
-	0x555a1465	0x8ab38399	0x51d4a5c8	0xec3d86e1
-	0x2a85d0dd	0x0d31c16f	0x603f2d48	0x274d5d68
-	0x292e7df9	0xe444f292	0x329946f1	0x132c3230
-	0xb2c3ec05	0x88362f92	0x763dc2fa	0x7ee6f3ab
-	0x7ca649e8	0xafee8a8b	0xeef65517	0x4789c1e3
-	0x85bd4cb3	0xc87762d3	0xfa528ba7	0xa8e20dde
-	0xd369c227	0x97e7f300	0x8256f4ce	0xdd5d2901
-	0x1e37c55e	0xbb6e22fa	0xd9424392	0x8798d9a5
-	0xc118ddb2	0xc3c91c40	0xe68ead77	0x8cf3655b
-	0x4381e8fc	0xc94f312a	0x0b372483	0x70b620df
-	0x53820813	0xb50d6f0c	0x64a53e9e	0x6f7f19f3
-	0x6315f718	0x9aafff2e	0xf3b5a338	0xf1f3293c
-	0x750ac26c	0xefe3ddf9	0xdc7369eb	0x024dafe0
-	0xf56354fe	0xf0afaf86	0x7da1df00	0x7447ffa2
-	0x4afd091f	0x24f39c82	0x3b3c8aa3	0xd90fc65d
-	0x10d90b8a	0xf05d49fd	0x281320fe	0x75f62523
-	0x0537b558	0xf52ae61c	0x77961852	0xbd0db386
-	0xcb650cb6	0x7387ec69	0x320764c4	0xf5013b3f
-	0x4f4239c8	0x4983a307	0xf510f405	0x7e355790
-	0x4f8480d2	0x50dd84ca	0x66947bed	0x56efdfe0
-	0xa593407d	0xdac216de	0x642a5f74	0x92bb9c2f
-	0xf37abdd9	0xa24b1b64	0xca1f722c	0xaa5de969
-	0xb6cb128a	0x697f787b	0x5bd74fb3	0x6de74e39
-	0x2bc9a4aa	0x634455ab	0xa82aecc4	0x69647f0d
-	0x4be06592	0x0c220c92	0xb08adf1f	0xd4571d2a
-	0x0fadece6	0x297c124f	0x2830a499	0x3cc8363f
-	0x44e34d3a	0x27b4d820	0x98be7f08	0x43417964
-	0x8a3af8ac	0x89c42336	0xe55d19dd	0x00ee1f6e
-	0x47d48658	0x55986f58	0x11ccb046	0xf3b97a07
-	0x7ed364a3	0x106cfcd0	0xc1533857	0x3add2c15
-	0x143852c7	0x55b38512	0x49a85ce8	0xd61a285d
-	0x513bd0b9	0x21bde48e	0x4f231482	0x93aa6dde
-	0x88035659	0xa83e3d2b	0x542513f8	0xe6e74a1c
-	0x06092343	0xd37c8770	0x41553ead	0x09980a79
-	0xb0e45895	0x80db4662	0xa6ce0960	0x965cfa7e
-	0xfea96644	0x2a79157e	0xf020e115	0x61823e96
-	0xf14f63d7	0xd753d1bd	0xd24a060d	0xfd2691b9
-	0x18da9d0e	0x9f3c93c4	0x2730e0f2	0xb47e2afa
-	0x920fda38	0xb5d89646	0xfb4728e5	0x7e78c2cb
-	0xe46f812c	0xe51cc5c0	0x9d2957fc	0x548798a1
-	0x240c2103	0xd650ff70	0x15c49ff6	0x99587c0a
-	0x1bb4a5ca	0xd6db66e7	0xec2d3ac5	0x54164690
-	0xe61bd6f8	0xc7a45cf8	0xee25f4f4	0xd1eb3ae7
-	0x90085a1b	0x46a7a74b	0x829717f2	0x7f0769cd
-	0x3ef72792	0x0c8617a7	0xa86becad	0x9dfe5329
-	0x1a33c5a6	0x47d4c75b	0x2e10b45f	0xbd11762e
-	0x15b72a9b	0x015c7f84	0x379c6bd2	0x27525345
-	0xff3ac5a6	0xac916082	0xf5c24317	0xcc43fc64
-	0x7f092c8d	0x931d9a0c	0x5a07f13e	0x3e1aa46b
-	0x717a343f	0xd51221c4	0xc9422fcd	0x63f7af00
-	0xde81a497	0x0322d271	0x972a4065	0xd75df029
-	0x343a94a0	0x8c225f7d	0xb4abe87e	0x3cb8ba1b
-	0x0babab14	0xf29704e7	0xd7134233	0x391f1a35
-	0x33aca565	0xe6ae586b	0x0470a42c	0x570efddf
-	0xfea26a3b	0xcee8d934	0x99ece522	0xb8af1375
-	0xfe4dea4b	0xb96a32c2	0x3469ef9c	0x029fade7
-	0xc4e77d55	0xc0449b95	0x63336e95	0x8d46c2e0
-	0xd86d6e23	0xd365b781	0xe73ba0fe	0x10a354c5
-	0x2d4511a0	0x077206cf	0x1c0dbd55	0x03396771
-	0x8bce27af	0x70355b4b	0xc2275e58	0x3cfa4df5
-	0xc8b3b9b8	0xf3fd510f	0x6b055de5	0xb3fef295
-	0x42b95a20	0x5b5e75e7	0x0aaaa734	0x636d50ae
-	0x8329283e	0x446e76f3	0x6adc320d	0x69a3e9df
-	0x1da68939	0x6f071783	0x498dfee5	0xaece51ed
-	0x4f8a72a8	0x4f2f2f65	0xdac3ba47	0xcbab0287
-	0xf966cb4d	0xba27861f	0x54c79a21	0x44e2359a
-	0x6e6b0e7f	0xceae84fb	0xb1530a59	0xecb8cd96
-	0xff60633e	0xed748fe3	0xf1ab0d95	0x59997216
-	0x6894cf41	0x948fc7bc	0xfb162ae5	0xeb9951a1
-	0x99d0a7a3	0x9234587f	0xcd42615b	0x6f9ad0e8
-	0xeb936dbe	0xbe72b62c	0x44ab5e9f	0xed736b08
-	0xffaedca9	0x103b89bb	0x7896b40e	0x13a5a924
-	0x56786357	0x02ab80ec	0x72ef47fd	0x81bf0fd7
-	0x6661b300	0xaefadc79	0x9968433a	0x16f3718b
-	0xe997a663	0xbbb55a49	0xf9b9a710	0x5727271f
-	0x20e9bf55	0x358e3986	0xd1214e1f	0x4d42c46f
-	0xa6bf8194	0x0c14a853	0x7b51aeb0	0x2f3d4de4
-	0x3d6ffef6	0x4e94ba19	0x71a9c861	0xcade2398
-	0xe0b3eb18	0xc9f028b0	0x7d29d2d0	0x372ec60a
-	0x288a5bfd	0x4fc2bab3	0xc01dd045	0x8222e147
-	0xe06676de	0x750bbfea	0x586ffb3d	0x2addb655
-	0x767a6528	0x78abceec	0x1646cb38	0x21e26890
-	0xd2a7937b	0x2463457c	0x764103fb	0xd540867f
-	0x3566875f	0x007449ba	0xf9c0c523	0x2c51c86c
-	0x437e1196	0x69fc0059	0xe0103408	0x19f23997
-	0x23fdf335	0x7262eef4	0xcbe09390	0x583d0099
-	0xe862084d	0x19fffbab	0xd2958a5a	0xcb165416
-	0x32f3a97c	0xe502303a	0x16c4eda5	0xa1bcfd1d
-	0xc4f35053	0xfd037f66	0xdeac9fee	0xbfb167b1
-	0x39804db6	0x0bc2011d	0xf56bcd68	0x368cb345
-	0x52fcb352	0xc306c535	0xf6bff09c	0xa429cbf7
-	0x7e504be4	0xd2240214	0xf09ee41f	0xcbcf1fe4
-	0x70f96a85	0x8394bf28	0x3cc19a50	0x49581f96
-	0x58da5ae0	0x94708c48	0x63febeaa	0x4f656940
-	0xa7fd6879	0x65524f66	0x5f7ee0df	0x11d487f9
-	0xb494641e	0x7eb57255	0x5aa208c0	0x5666243a
-	0x7d5970b5	0x71ea69a1	0x67059c9d	0xd3bde5bc
-	0xe952b3fe	0x27bbf258	0x197504f4	0x5da6649d
-	0xecddf4de	0x2d040d3d	0xbc9d3ab6	0xd8cdfb81
-	0xb36ab627	0x7a548111	0xaaeefa4c	0x0e55b263
-	0x4f9da6e6	0x26a137dd	0xdea03395	0x23b87267
-	0x5b3cc98a	0x206de858	0x8d2e5cd2	0xb60f14e6
-	0xfc10356f	0xeecae1d5	0x39783cbe	0x1a1c9a70
-	0xb52c6f05	0x64adf10b	0xe12d9f3b	0xb3fb7cf1
-	0x9051fdea	0xc16ed3bc	0x697199b0	0x08f34342
-	0x2fb2bab6	0x729ed2b8	0x7691088b	0x82bc9cc1
-	0xafce7ac3	0xe167bbb9	0x362e5d43	0x945510ec
-	0xf32dce5e	0x4aec9a82	0xb80520d3	0xd8fcbe40
-	0xf4877350	0xcfdd487e	0x8c9ff8b5	0x84ce70df
-	0xffa6abd3	0xf9d2f273	0x342dbff8	0xa72580e3
-	0x6ffccdc3	0x0c7ccc0f	0x6b24afd4	0x82b71a25
-	0x1ba361f2	0x6ed8a67d	0x243ce000	0xd16b2e19
-	0x86d3c3e6	0xca209063	0xaff0b983	0xf411f71f
-	0x0f2ca724	0xa6fb0fb6	0xfa663640	0xe40fe20e
-	0xf8e2a5cc	0x1a0e8862	0x11de13a4	0xc811e4a7
-	0xfe6fa8e6	0xfefce644	0x8f7fcde9	0x94477c62
-	0xec9b942f	0xfda6b166	0x91330c4d	0xd059d679
-	0x96b0f7a1	0x22df13ce	0x3f36c3e9	0xc814e342
-	0x7b7dce7c	0x1000640a	0x8cbe7a56	0x622fa655
-	0x209d82d7	0x55668514	0x1534f8af	0xc2b7dc1f
-	0xd89da0dc	0x3ddfe751	0x0532dfe4	0xd39c360c
-	0x090f91d6	0x48587117	0x8ee383fe	0xf5ffdee4
-	0xd8bca448	0xd26d6d82	0xe8adcc12	0x8b14b8c1
-	0x7f872f36	0xb8cb0e16	0x76d60c06	0xf62ddbec
-	0x3ec7c151	0xe418a789	0x920a3bf8	0xc5b62e09
-	0x4974ea7e	0x0d8d7962	0x5bbb246a	0x37183d1c
-	0xf25c63dd	0xb15730a5	0x903e3400	0xdab426eb
-	0x0323289f	0x9bc16f49	0x2dfd02a1	0x3ab916a1
-	0xcb6f770a	0x342021b2	0xf9f5c9c0	0x9c8d53a5
-	0x3d53f39b	0x8e693c58	0xebecc732	0xbf30c538
-	0x96648d11	0x60f62751	0x29745559	0x8e365fb3
-	0x7d0b1179	0xea5abbb2	0xe45c4af0	0x53056b1d
-	0xac7b03dd	0x7015c355	0xf17f8dfd	0xe1ace271
-	0x9abacdc0	0x5ccedc75	0x478c717d	0xc01dfdad
-	0x26fb551f	0x73e61f00	0x8bc0b111	0xb6855743
-	0x28690dc2	0xf13b6766	0xc098861c	0x5c0ffa55
-	0x271e7d0c	0x66b47b80	0x9921a158	0xd9c560d0
-	0xb29b6ee7	0x50a9bc97	0xbec4d91e	0xdb2c1fcc
-	0xdf215786	0x1541e380	0x59cae516	0x2342b2ee
-	0x8088cd9b	0x7312579d	0xb17be14a	0xa1638c41
-	0x805c6b18	0xb8a56151	0x56f0a6da	0x96b114d2
-	0x0845ea7c	0x23e8f7eb	0x4e88e7ce	0x84640f2c
-	0xacf8eebe	0x4039725a	0x49bf9982	0xfbcfcbd9
-	0xfbbfb1c1	0x8041659b	0x5b8ee4f3	0x1b6d7a38
-	0xeb634fc4	0xbf818ab6	0x8076c921	0xc50be762
-	0x24c43f4b	0x3252acca	0xa7528630	0x9885b151
-	0x9154b37f	0xfd9d3ab1	0x4f93c117	0x578fba44
-	0xa56851fc	0x9d8083de	0x769f6fb4	0xd89fec27
-	0x747c8071	0xe6b2b747	0x8196e2a8	0x3ed6c699
-	0x8716f1df	0x65325e96	0xfbc715d5	0xb06f9171
-	0x7aa9cbdd	0x84bda56b	0xdeab06ee	0x80432d8b
-	0xd76f0a57	0xe0ed5f9a	0x70f991a2	0xf1a9e557
-	0xcbecbcdd	0xcf0d91fc	0x6751fd67	0x590f206a
-	0xa26d8130	0x1df02179	0x826303ce	0x6cd58190
-	0x1219d005	0x4bb2f3b2	0x0dbd8193	0xd8d8f582
-	0xa5867eed	0x2d6b8ec9	0x5f85ec18	0x7983775a
-	0x214ca0c1	0x9af3febb	0x213d6568	0x2f8e8c43
-	0x92add018	0x6e33e00f	0x6fa6834f	0xc3c2cbbc
-	0x1c65c8c5	0x1827f812	0x868d3a09	0xdac83ade
-	0x57623da5	0x5ff83257	0x0992e621	0x25cc9ca9
-	0x10580130	0xff2ae8fe	0x40a58253	0xffdc24d5
-	0x3e4dbe68	0x291b11f7	0xb3594b9a	0x570c7b6d
-	0x38d31bd4	0x7155ba24	0x84d56490	0xd98842d5
-	0xe037d2f6	0xdd2ba821	0xbeb861d5	0x0fda5758
-	0x5921c665	0x98c7676d	0x8eee487b	0xac0f2411
-	0xb332d321	0xa0816c65	0x76edde5c	0xab868b36
-	0x3f8da4fd	0x516af4e7	0xabf748a8	0xbe7820fc
-	0xbf763827	0xa03a3566	0x8a63e804	0xb4f8f901
-	0x5d262ee9	0xaf905cf5	0x896d0c94	0x5f992cab
-	0x81c2faf9	0xda3c686a	0xb01a06dc	0x45ef0c90
-	0xf2ca525f	0x0e74fe18	0x36ecdb11	0x494125d2
-	0x226b4aab	0x3e92ae29	0x5bb48774	0xc2c2ef90
-	0xa9e77d5a	0x409db546	0x7728f003	0x72229503
-	0x2e8febab	0x8322cfbc	0x5eaf74e9	0x621837f8
-	0xc70668d1	0xb25c1325	0xd741c010	0xf52e3166
-	0x71ef7a87	0x74cc93a4	0x7c25ecf4	0xb8b8e20f
-	0x3658c239	0xbc58fba7	0xf13ec858	0x9271b2a1
-	0x37084dd5	0x6fc92e82	0x44a6abe6	0x92b9238a
-	0x9ad3a57e	0xd75daf92	0x8ea573d6	0x69ce1fb6
-	0xe80df5f2	0xcc1c6ae7	0x6d565a77	0x6981ae63
-	0x18af1922	0x6e8a7af8	0x10716aa0	0xa7da9970
-	0x1abbc7cd	0x114f814a	0x4ebb0c07	0xc8fe6a69
-	0x93d7bc2e	0x0a16181c	0x0379c950	0x4b2e8c18
-	0x670b83f8	0x82a75eda	0x6eb772dd	0x42cfe197
-	0xd91ec29c	0x29fb4812	0xab693ead	0xb2f25a1c
-	0x0b9df6cf	0xb7a1aba2	0x1d7d90bf	0x7de14655
-	0x649965f6	0x11fbe065	0xa54ac5a3	0x418bd3df
-	0x4223c00f	0x7bfcf9ae	0xbd979739	0x6a2ee697
-	0x54e7d9c8	0x73803bdb	0x06654716	0x72225136
-	0xfaef3873	0x0b4b40dd	0xd3b98b57	0xc56cbab5
-	0x32174c47	0x4d4d8c32	0xd6f1bf93	0xeefb6950
-	0xb84ed0da	0x590723d4	0x2d006f09	0xc4bc139c
-	0x55434982	0x8734189f	0x0e314a50	0x94340d09
-	0x021c24a4	0x0b0f022d	0xa61f9025	0x71eb72b6
-	0x744ccea1	0x2030b859	0x78203d74	0x0b8a8389
-	0xd5211777	0x2609edfc	0x6134eede	0xec74584f
-	0x0bdb2d06	0xb1768f76	0x56221895	0xfc49bdae
-	0xbcc6e6ed	0xfeb19c0c	0x18652996	0xaa1a0164
-	0x3ffdcb94	0x2dc1b090	0xb68bf220	0xc33b967d
-	0xc907a1aa	0xa3968cb1	0xb3cc65e5	0x33e2b077
-	0x2bb22904	0xe0fe8fc2	0x4affcc46	0x6b0f0bbc
-	0x5d1bef41	0x2de11c7f	0xb0d864ee	0x6e96d8dd
-	0x59c1c108	0xb2544572	0xab3400af	0x604aefcd
-	0x81be22c3	0x6741e6ca	0x3a93dc1c	0x7b10e639
-	0x0add7a92	0x39fc1df3	0x884f150b	0xd666a96d
-	0x87da0c1a	0xf0f73c15	0xc0c00957	0x011ba61d
-	0xa77e9463	0x96020e4e	0x92416e99	0x881e89c4
-	0x46981327	0x3bc624f4	0x57f226f5	0xac340cd8
-	0x3ce239b2	0xec6b33bc	0xa9123e11	0x70640b6b
-	0xc30f59f0	0x411576fe	0x5ab12c3b	0x3cc20b85
-	0x924b3be2	0xd1fc7a28	0xa4b0cf7a	0x88098404
-	0xbbd331e3	0xff2b6047	0x2a1ab042	0xdf220849
-	0xaf774ae3	0x5a8da79d	0xf18450c8	0x8e6e235f
-	0x1dd3c039	0x1a867ae2	0xe4ccd1f4	0x50dd3f39
-	0x8be186ba	0xc7e30fe2	0x17552d4d	0xffac16e4
-	0x4094bbc4	0xc18a2513	0x650e707f	0x8ecdbba2
-	0xf53e8e7d	0x047dbce2	0x7fc2a89f	0x07628f94
-	0x2a8bfc67	0x0d738727	0x7b5c2fd4	0x2c89d27f
-	0x47f37a64	0xc63debc9	0x15d6c414	0x242c300a
-	0x645d95ab	0x29e1a49d	0xaf77fab1	0x643b4cd5
-	0x3e0f63db	0x4f7cc43a	0x33d6797b	0x497d4332
-	0x7160786f	0xe0c5b75d	0xfb08ecb2	0x26063065
-	0x9835bf7c	0xf5465591	0x63155d2d	0x14babba1
-	0x384a0879	0x460db3b1	0xcd37760b	0xad675a77
-	0xf1dceded	0x69df690a	0x44c6f456	0x87d6a7a4
-	0x4e0d6504	0xf967f55f	0xca9bb20d	0xd5eb41f6
-	0xa9aa9b2a	0xa907387b	0x965b6f23	0xdcd47eb5
-	0x43b5b1a0	0xec876728	0xee7339e8	0x10c5ee16
-	0x1bd8c0bb	0x7235ae07	0x063e3564	0x388d0bb5
-	0x80f9a9f6	0xaf96f714	0x6895c899	0x00ad21bd
-	0xee67961b	0x873781a9	0x22cf435a	0xee90cf3e
-	0xc9a4fadd	0x9bc1af4c	0x35c0e803	0x211ce71a
-	0xb9af86bb	0x97828ab5	0x9dbd002a	0x1cc981c7
-	0xefb36876	0xea739a75	0x5d5abcc1	0xd42260f2
-	0x95083e0a	0x31fb0b51	0xf243ab8f	0x628b1913
-	0xe74eb210	0x620b7d9f	0xc81666d2	0xc8fd1ce1
-	0xf054bd9e	0x78ba7618	0xe1df4e38	0x5e381b3a
-	0xcc68da1b	0xb3ce70ac	0x7ecda229	0xf8778140
-	0xae823fa1	0x12af1708	0xc9373879	0x1e687d29
-	0x96062069	0xf1bfde2b	0x999ff6c0	0x8cbeddf0
-	0xc825a2bb	0x78106bbb	0x87a964fc	0xb358ec2f
-	0x4d959300	0x0fe9706a	0xabb1d003	0x72b65294
-	0x43816b1f	0x6c83b958	0x5549567c	0xb474aa55
-	0x98851640	0x751a670f	0x25900026	0x2ab174e3
-	0x1952c3dd	0x38b47c29	0x32c0af52	0x460c8fad
-	0x85a1004e	0x8cbddcd7	0x66578310	0x4904dcfb
-	0x04b7a746	0x00c91fb7	0xb1ab2edb	0xd0178ae2
-	0xc4b8b57e	0x981d4753	0xfdd8939a	0xa8a05055
-	0x47c8c30e	0x0fab4f6b	0x6ea54079	0x23dc4151
-	0xc23e83aa	0x2ed2ce8a	0xff95b763	0x08df1d51
-	0xd16d104e	0x0fa3ee3b	0xdcfe8541	0xa0622490
-	0x085e5c0f	0xd9bc007b	0x24794e89	0xce341d16
-	0xf090a98c	0x317150a2	0xcc036257	0x3296722d
-	0x9c8d4f58	0x7ca5f53b	0xb0e4f9d4	0x1f178bbe
-	0xc0dcde7c	0x18551596	0x0507b8e2	0x3c40a8ca
-	0xc632f82b	0x5d1965f9	0x92a00465	0x13a8ca32
-	0xc0b6756f	0x669d706c	0x58056b22	0xaa25fd37
-	0x128b731c	0xb141ed31	0x0a8d3ddf	0x48b63bd1
-	0xd24c5c4e	0x0ccd96b8	0x4b1ff726	0x309be62b
-	0x26002e68	0x436f2bd0	0xacb62068	0xce098f50
-	0x330e6160	0x434da66d	0xce14054a	0x0a877e41
-	0x705eb2fb	0x8433fc7e	0xc1bd475b	0xb550de6d
-	0xf4faf808	0x9f9b6ebe	0x0ff98ef7	0xace2766f
-	0x01cc9606	0xd9654327	0x3544cf5b	0xbffbcd80
-	0xb4a5948f	0xcded4d04	0x69ef5a24	0xf5ae46de
-	0xe2139499	0x549f82bf	0x2cdfc6b7	0x5fdd2462
-	0x63c68a37	0x8bce0d04	0x9c66ae30	0x9fd94951
-	0x5774366d	0xd671675a	0x5582f253	0x436c5b6b
-	0xfc151e77	0x1974df45	0x5ea9eac2	0x30689b8a
-	0x9806681a	0xb74d3ec8	0x4f207181	0x668b4951
-	0xb06514b2	0xeccffed1	0x16188ff2	0x5914d385
-	0xed4b7023	0xfb0640e8	0x179adcda	0x6e806687
-	0xb4f0ac07	0x35813615	0x143e66b4	0x1b012a50
-	0x384f31c5	0x1500dbca	0x06e47afe	0xa8a17374
-	0x9d0f5c57	0x4574db82	0x91b3680e	0x794683a7
-	0x30c25d5d	0xf8748c08	0x2e601dfc	0x553152f7
-	0xec5d489a	0x4bd37616	0xdc04dc7b	0xf0a35ba2
-	0xb36975db	0xbfe6f98a	0x6d744996	0x5507380b
-	0x4191e01a	0x0092c384	0xcf3a4388	0x6b0e89c7
-	0xded7b820	0x1fbd6bba	0x3af210b1	0xfc4a608e
-	0xa920eb22	0x22db2d65	0x7d6f0447	0x090f3679
-	0xc4c759cd	0x9758aac6	0xa63251a9	0x47b7a974
-	0x65421071	0xdca8495e	0x96f879d7	0x1d22ea6f
-	0x46dd72ba	0xe0c59ccc	0x15737309	0x6d945f11
-	0xbcb15c8a	0xb11ef0b9	0xe2072633	0xccbd61dc
-	0xfcb51c44	0xd2315c65	0x3087a6f8	0x5609ee34
-	0x94c7f951	0x0a057b31	0x6e6f2733	0x179facec
-	0x36c005b9	0x60184919	0x50b3db1f	0x7a827d7f
-	0x88755ecc	0x3fb0d6c3	0x63b150d4	0xe2ec3004
-	0xe0ee30f1	0x118d7040	0x2f4689e7	0xa78be0be
-	0x3c9bb853	0x75c326cc	0x84097407	0xb0107b5e
-	0x83a56a91	0x14e60445	0x0fa72553	0x1385e6ce
-	0x9b8bbdcd	0xe6aa6a9b	0xc2072ccc	0xee916592
-	0xe44082e1	0x43dbf6d8	0x09f821fc	0xdc84b023
-	0x0e6a518b	0x945fb180	0x185d0841	0x9ece88f8
-	0x844558c2	0xed85f422	0xeceb983c	0x6db16826
-	0x7612b243	0xee3bf226	0xb8eebb7b	0x22e16615
-	0xc892bb7a	0xdc475a47	0xae390e93	0xe00baa1b
-	0x725fca23	0xbb868b3a	0x17c62a69	0xeccd3731
-	0xbe1a4223	0x05c8fd7e	0xa8354afa	0xbbb09f8c
-	0x31a77e83	0x01f17a68	0x5f37c847	0xa0fdd7db
-	0x9f8da870	0x98f02167	0x1e966884	0x00e19b81
-	0x50c91add	0x6aba2a55	0x60be9575	0x3da40b37
-	0xde13ff4d	0x5b7a79ec	0x4700ffd9	0xfee5ea61
-	0xaf4d1d1e	0xfccb6f04	0xcf5076d2	0x48c4c98a
-	0xd6a8915e	0xe4a58522	0x6bf3a6a9	0x4e7c2f15
-	0xcd7e8d2f	0x843b56b1	0xa35f1a5d	0x1ca226dc
-	0x917fb163	0x44751f0a	0xd96fa8aa	0x5028dccc
-	0x7792dd96	0x2a9d749d	0xe48385fb	0xde111e91
-	0x805e6581	0x3d9b9fad	0x5b750544	0x03785b71
-	0x9b583214	0x80022658	0xcf1f3730	0xa1be7be7
-	0x6c1e26f2	0x26de584b	0xb4fc8e35	0x072b520b
-	0x55db3ac9	0x81e9d490	0x4b5ea53e	0xd5628e00
-	0x71bfcac3	0x79956bbf	0x275fab80	0x2ad497ed
-	0x423854b2	0x686451ad	0xfd59d64e	0x9f2049d7
-	0xcb0f8f32	0x74d7545d	0x4f9c1df8	0x6fbf0afa
-	0x7ef06915	0xc5117549	0xf20088b4	0x731a5ccf
-	0xe78bbe74	0xdcb4996e	0x7062a6f1	0xa624b59a
-	0x7b2d5e41	0xc1065234	0xa7c32078	0x367e7134
-	0x86f55f58	0x3084ee83	0x0c599d1f	0x69380e2e
-	0xe59482b3	0x7096432e	0x81124388	0x5be8d01e
-	0xeb25ec24	0x8b47e9ad	0x432216fd	0xdc496dea
-	0xcb05fefe	0xe76eb9ab	0x8ed568d2	0xfa963d68
-	0x70ed6f4e	0xb2b88d58	0x15fc42bb	0xe992ec48
-	0x359856b3	0x4a0f7741	0x3f0b6eca	0x07c16950
-	0xcb9dae59	0x209570c2	0xf196555d	0xbf7c0a0f
-	0x4a814210	0xf8f206c7	0x8bbb0763	0x360fa596
-	0x13d46195	0x901170e8	0x6dc2e376	0xbfa00989
-	0xd12cab90	0xf4f4699d	0xbc88b362	0x4827dbd5
-	0x7cde5cf5	0xe45dff5e	0x2d661b05	0x8902d99e
-	0x6c9f3584	0x0db3f864	0x1132773f	0x3e944120
-	0x27058ae1	0xef978864	0xe58eff42	0x020ae503
-	0x77fe075b	0x9c577e08	0x210b42b9	0xcb8160c0
-	0x09f99f36	0x6a0b6bee	0x6f18b0ef	0x5452ee3f
-	0x6c8c4a4d	0x480cb803	0x892f3973	0x066dbb63
-	0xf7f845c8	0x7ceeee7e	0x7c26c5ce	0xec89119a
-	0xc64bdc20	0xf46e4324	0xff34c833	0x555b4b3c
-	0x23ff2701	0x52360759	0xf60acad8	0x241ccb7b
-	0x29e14901	0xcc068e2b	0xedd0ee02	0xc33a425d
-	0x7d889b28	0x88577f8d	0xaaf614b1	0x8e8c8eb5
-	0x81a363f8	0x29f5bcc6	0x08aeb8e9	0x6f9ee222
-	0x1c50045b	0x792c9434	0x62bc2601	0xc9289175
-	0x374fc38c	0xbae91a86	0x3268e89b	0x5b008f10
-	0x0ea6b759	0x9d43ce10	0x09b30dd2	0x643e2b94
-	0x5c19bafb	0x29515176	0x56a81f95	0x60a80534
-	0x22fa0a73	0x1259cf8d	0x323fa5b3	0x6322f1d0
-	0x30581c47	0x50458048	0xd711c1b6	0x4a34236e
-	0xb60a2e40	0x58df96c9	0x947b90d7	0xd327d664
-	0x5fe528db	0xf6d9c575	0xb0a251b9	0xed961301
-	0x2fee3cf9	0xb687e226	0x78fc46c2	0x29e9fef4
-	0x84bff086	0xd0482ed1	0x018996f1	0xb8b9cdf8
-	0x20885e68	0xa6f848e2	0xfddabc3e	0x5c9a7f67
-	0x7cbc3e40	0x5197ebe2	0x41a15775	0x8024fd2a
-	0x7864106f	0x7cfaf482	0x27798720	0x4956355f
-	0x30f7195e	0x6ea09dd6	0x6f2b5f3c	0xf38df38e
-	0xcae7e8cb	0xf8a80b0b	0xbeb227ba	0xbbfa2428
-	0xbbba3ab6	0xbf83edbc	0x2cdcaa9b	0x2b0841a7
-	0x79d52e5e	0x40260460	0xb27709be	0x07e3bf6a
-	0xbdccc2b9	0x369d0069	0x9d745e50	0xff251486
-	0x1e14957f	0xf7253467	0x9a31eeb9	0x4d77108a
-	0x44fefc47	0xd02d4082	0x232e3fc1	0xce39396b
-	0xd7a13714	0x2bd57e7e	0x00876803	0xee73377e
-	0x78bb6240	0x2ae63c46	0x11e009d2	0x922539cd
-	0xf3bef05a	0xf0c664c3	0x6e132a0b	0xb0c5bddd
-	0x40c66494	0xd7d0d02a	0xa73110d0	0x4b409d78
-	0x6f49bf88	0xcfc9d22e	0x4836da89	0xde5a80be
-	0xb9c8bdb3	0xe99b2e9d	0xf1b05e68	0x8ab599fc
-	0x22675035	0x3c8480c0	0xfa3cd457	0xba617098
-	0x422eca1c	0x0cdc0d01	0x4779b95e	0xccfa0bfa
-	0xd22674a4	0x76462be6	0x3015ab3b	0x7891688e
-	0x1c83bf8b	0xaa55839a	0x7a71a83f	0xad451c1b
-	0xf8b8bf06	0xc75a91be	0xcac50366	0x87e365ae
-	0x9013ac11	0xe9cec5a5	0xef4d88f5	0x15c27162
-	0x3dcaf8ae	0xe023891b	0x7b6f1706	0x2f1198e4
-	0x048e34ba	0xb647b5e8	0xa1826caa	0xed3bc134
-	0x43b14d28	0xf0c49b54	0x1a6362d4	0xc77fa378
-	0x3bb12e79	0xcba4cd2b	0x620f2476	0x7729add6
-	0x9876c439	0x5f7d8795	0x858f7ac8	0x68b94589
-	0x1321d70b	0x5353a2fc	0x912a5ea4	0x390cf0f5
-	0x37320473	0x51b3cacf	0xe45046d2	0x9188dcc5
-	0xb3713b54	0xc9b936e3	0xe9f24574	0x5977a68c
-	0xc23c56bd	0xcfc39ca9	0xc891b8d0	0x3683ef22
-	0xc1ce304a	0x3ebf1ce1	0x52cd1cc0	0x3777d973
-	0xde614072	0xf2efe226	0xbe1f9f9b	0x92a1896b
-	0x9ca62763	0xcf5703be	0xa6d9c56a	0x185260d6
-	0xd9e3b86f	0x5c47180b	0x71a7a219	0xe9974375
-	0xf22af4d3	0xfbc92962	0x968c3fe4	0xc584b60e
-	0xb9abee26	0x7e9737d8	0x5947da83	0x2f8ccad0
-	0x7b4ee942	0x51ad62dc	0xf517400c	0xe2bf9e37
-	0x63057e05	0xe1bfabf8	0xbf118805	0xc038de9c
-	0x7aa57b7b	0x05584eff	0xb15ea286	0x26c6a6c0
-	0x8e1392e8	0x7dbf22e1	0x3546f5bd	0x0f84ed9b
-	0x0b01da4d	0x6dc47417	0xadc6f687	0x4160c045
-	0xdc26765f	0x63b70c6e	0x8f177107	0x6a5f13cd
-	0xb56fce56	0x5d1f5ed1	0x62f6a18e	0xf7235691
-	0x222fa999	0xd48b1435	0xe597d406	0x8dacf828
-	0x694ecd8c	0xe5283c02	0x60bcdcd3	0xfb9eb384
-	0x9895492c	0xd38172dd	0xe7b6dff6	0x0ead5894
-	0x910e2675	0x97d9ee09	0x270b2d8a	0xd03e25e0
-	0x9e7bbb69	0x57ab1d31	0xf2e7a13d	0x9c8e5baf
-	0x65fa03f4	0xc66bcbfc	0xf2d8bfe1	0x23059412
-	0xa3ae7654	0x3a4734a3	0x32c0a8d3	0x4e007b8a
-	0x5ce30660	0xbd10c57c	0x5365f540	0xeaed3002
-	0xc377d84d	0x87097a59	0x929edec9	0x5878368b
-	0xbd450478	0xc3fab275	0x128fdced	0xb706fbb5
-	0x146f1d41	0x86782651	0xa530ca29	0xa3e1b6be
-	0x25390048	0x572b4a05	0x8c9b4c90	0xb05428cd
-	0x33fabab5	0xd16e513e	0x1d6cc812	0x4d80a6ed
-	0xd6a5a07e	0xc0ee4c19	0x544b75d1	0x3f887360
-	0xb2f46d1d	0x21609cbd	0xe340211d	0xe9202fb6
-	0x3023b005	0x3341ead9	0x76c99537	0xc9d76547
-	0xfb736c3f	0xf6385346	0x93fe2a05	0x92de6df5
-	0x7793acd1	0x68249b3e	0xc22cae3b	0x668988e0
-	0xdc1ea28c	0x7ef72b95	0x974098f9	0xb214701c
-	0xc2de7d98	0xeb1d443e	0x5975f0ec	0x21d67037
-	0x721e8e99	0x42105562	0x74b1e821	0x20193b2c
-	0x743a7bb3	0x24643c9c	0x240b331c	0xdf125e2e
-	0xcb4b0205	0x19edb174	0x505eb85c	0x1830bf22
-	0x6bf7a528	0x86a7281d	0xfee3488d	0x6c26f4ab
-	0xbff4ce7a	0xff7cfaf1	0x5df6fd66	0x523f0802
-	0xf8a87595	0x463b5c19	0x72c564fd	0x2e4797d6
-	0x1f04a1af	0x0be96baf	0x44552094	0x2a158f50
-	0x83dac587	0xad4c881d	0x3178e710	0xe938d1be
-	0xab715a65	0xc34b451e	0x1942832e	0x91557ecb
-	0xdaf0606d	0xa64623d9	0x84e11fbb	0xa9c9d11b
-	0x577a15b1	0xd49a2f23	0x6f204e0b	0x0a6e6a2f
-	0xdaf13637	0x6b4ef557	0xdcaac9a3	0xad97c404
-	0x8471691a	0x50ca3cf5	0xde57c446	0x70aa02f1
-	0x84baa6de	0x0232bc79	0xa06427af	0xd2ce56be
-	0x5da13949	0x254f5f4c	0x3fc3fd02	0x00b5f8eb
-	0x54a0d4b8	0x5e3ec3b1	0xc6718376	0x5acce6d8
-	0x614c56e0	0x89a6b00e	0x6cb4e087	0xa9822fe9
-	0xdea290c6	0xb294582f	0x36f9640e	0x30d0afc4
-	0xef7d75b9	0xfd9aae2d	0xd6729573	0xac442321
-	0x158224fc	0xfd6632df	0x10cebf98	0xc3864dd8
-	0x31577c58	0x49e71f9c	0xb96d876c	0xd867604e
-	0xba74c3f0	0xad69752f	0x716eb51a	0x469d9d03
-	0xda4b2e16	0x9e80a908	0x9bcb18e8	0x2f1c595a
-	0xe823ecfa	0xdfd5badc	0xe460e9e0	0xae418438
-	0x457811b4	0x29df713a	0xd90b0d29	0x415ba2de
-	0xa0af6489	0x4922a50e	0x2efa0b0b	0x9394e4cc
-	0x0ef8f59b	0x0f851711	0xa4670f3b	0xcc6bbfc6
-	0xae194dfe	0x78e51752	0x4c65a2d2	0x1b0741cd
-	0xc9f401c0	0x4a678062	0x290d2bc5	0x1a4279c4
-	0xb5f9160f	0x40ef7c77	0xa9bcfba9	0xaec75f21
-	0x53d6258e	0x8587eb74	0x0721d492	0x2c6a6e2d
-	0x8e6cb70e	0xa6bee309	0x6faf5706	0xf8eee239
-	0x52c85943	0x8c198893	0x3db37858	0x557fbf2e
-	0x92f1a0e5	0xbd279594	0x46d65132	0x90a2c32a
-	0xd11db660	0xc73b3922	0x9d1075ff	0xdb80a1cb
-	0x54158743	0x39694d0a	0x4a0ddc7c	0x721f9dc9
-	0x04b1b044	0x3bb40aed	0x6be7a88a	0x429a3b09
-	0xa6e9dfa8	0xba412f0c	0x354f08d2	0xa4569516
-	0x928cca34	0x398b1a99	0xb7e80291	0xe67d7b71
-	0xa6582bf0	0x556ebb23	0xdc6d9f6a	0x11b3b753
-	0xbdf31ae5	0xd3399560	0x6148cec8	0x5188689e
-	0xde18f46b	0x3da414ad	0x4c44ad29	0x68582541
-	0x75c8b1e6	0x7ba572de	0xd753ed20	0x4a9c4578
-	0xf1c9159d	0xcfd9da31	0x46799fbe	0x1aee4426
-	0xdcdf7b57	0x327db61b	0xa160ea1c	0x84a01fc2
-	0xbe0aa020	0x5963688b	0x24f32751	0x885b4177
-	0x26cde88c	0x39e6df90	0x1c7fee90	0x882a5c0c
-	0x56f1f2e0	0x10bb9f52	0x4f0502aa	0xeae6e5b9
-	0x65e7ee25	0x8ed230ac	0x38b5e02c	0x5f5311f7
-	0x929491c0	0xdd923e62	0x5bc6166e	0xa3c89f4e
-	0x5844fb12	0x0c40f02f	0xdda07582	0x8ca1b803
-	0x9398b0d0	0x4dba17f9	0xb9879c85	0x26956147
-	0x3c26a130	0x58cdc52b	0x21fa4801	0x9d965ce6
-	0xb9942dac	0xd83d1518	0x36e630dc	0x50bb2822
-	0xcd472a65	0x6feee2f4	0x4853b680	0x7f54945f
-	0xa522c561	0x28134f6a	0x89b46cb2	0x4fe0047e
-	0xad602b28	0x4942494f	0x1536ea37	0x40ea6278
-	0x5020bdb1	0xad3c9f7e	0x1356d0ce	0x411700c8
-	0x1ba61954	0x65dece8c	0xb788efb9	0x26efcd5e
-	0x9833fa21	0xea0052b8	0x119a994f	0xa71b168b
-	0x164a96e0	0x0bd1b4e9	0xaae1e562	0xb550f48c
-	0x3a3b55e1	0x4d921246	0xcb28af65	0xdd2388ff
-	0xa63988c3	0x7dfa5a8b	0xc7c44102	0xc75e9f3a
-	0x5e4305db	0xacb34d1c	0x9b50976b	0xad3f6379
-	0x6cd20ee3	0xba806f21	0xcd0fcf4a	0x18a55973
-	0xbafe5266	0x03ee9b8c	0xa35fbfde	0x7f2eb71b
-	0x23d9aa11	0x0e183c35	0xefb0ae3e	0xc6093786
-	0x5b380af5	0x64838229	0x3bd69926	0xe9758e1d
-	0xde439e4a	0x0cbc4bdd	0xda5858e8	0xbe8afc07
-	0x676379e1	0xccc4c628	0x763e3b38	0xb4823c67
-	0x9f4aa538	0xd8d33f50	0x41291e48	0xaed28ade
-	0x6c72eea8	0xa751f4e8	0x3a75dba2	0x5073e3bd
-	0xf10b4756	0xdf46ab98	0x9ad689f1	0xc2ba74a4
-	0xf2ce9419	0x4cf9732e	0x75cf58ca	0x249e3c52
-	0x95d10a93	0x51120008	0x7438d467	0x0a5e7f2d
-	0xb7a44e46	0xe31e5dee	0x26e2ed14	0x8f16a7d2
-	0xfcda431c	0xab32ada3	0x3a863c94	0x5fe91346
-	0x2a92c590	0xb8c17e6b	0xcaf753fe	0x50283647
-	0x533c8f3c	0x1233e1c1	0x7a5b2eb0	0x79b4ba22
-	0x3164670c	0x201c500d	0xafeac6bf	0x2fbb0884
-	0x915de3b0	0xbf733b7f	0xc45d1a42	0xa3b86d4a
-	0x333ef605	0x6348522a	0xd28d1d19	0xa2cad790
-	0xf8ad449c	0x05aacdcf	0x64500018	0xb1d8cb18
-	0x9e4a2ecc	0x091282c7	0xfd64bcf8	0xe1e7c24d
-	0xfcd0f386	0x0c9faa0e	0xa82f265c	0x83cafc3e
-	0xcad43563	0xc110837c	0x2a2da74f	0xbd98e00b
-	0x5c24553d	0x41c75caa	0xe75cb110	0xa004b946
-	0xd4daa77c	0x88d07273	0x0c75c7eb	0xaf05657a
-	0xbe1f8336	0x122a7acc	0xe0e5c29d	0xd5896217
-	0xfb2f909a	0xa74b6458	0xb33a1a38	0x815f7832
-	0x9584b271	0x9a3bb26e	0x39aa6d36	0x2fba41db
-	0x133797be	0x9993699e	0xdb50268d	0xccd54ff0
-	0xb7a33011	0x71db612b	0xef9a4429	0x7217f1d0
-	0x0ee420ba	0x1f7eb025	0x26572853	0x72712e17
-	0x5bd7be37	0x74b2288e	0x3ffd1f1f	0xed566562
-	0x744f4159	0xdbedb36b	0x69e25131	0x604ccb70
-	0x50d83542	0xe4704ddb	0xdc5144aa	0x33467434
-	0x1c7c4f2b	0xac774e8e	0xce9c4d1b	0xa0e3c7f7
-	0xffbecc1c	0xa1c25fb2	0x0e9f6039	0xbe9ed6d0
-	0xf958fb6a	0xaec3fba8	0x2944e767	0x77dc717e
-	0x06e9fe1d	0xaf3a4928	0x7d4f3f29	0xead3972b
-	0x65670bc4	0xd058cc70	0x9fb58c45	0xf5f08926
-	0x9aed1955	0xb1a5d161	0x14b5aa11	0x66e14cee
-	0x28d7aae3	0xae45fcec	0x92dc7dc3	0xe9eda97f
-	0xbee84f22	0xea6f71ac	0x6347c2b8	0xe919afff
-	0x2c409d7c	0xa9800c52	0xd8033a17	0xc3794565
-	0xb5311fe8	0x80d8a030	0xf9cf179a	0x508ea242
-	0x4464cd33	0x91da91a8	0x6c0806cd	0xb5473d09
-	0x0a0b99b3	0xdaf528eb	0xca1e99e7	0x064055ef
-	0xc2dce623	0x0b4c15ac	0x23c13327	0x3f9fc266
-	0x335d9c40	0xaca940c2	0xc18c0797	0xd5027a07
-	0xb0a4d322	0x2e601275	0x6cc88888	0x658eaf8d
-	0x509e2247	0xbae254d6	0xf097f138	0xa163751e
-	0x19558f7c	0xb66f0cd4	0x87b1d966	0x81dd2cad
-	0xf0c25e6d	0xb8e72dd1	0x00f15f42	0x6d2c1c68
-	0x43c7e436	0x68eedad4	0xc2686b38	0x6ff30211
-	0x197c7734	0x905b8602	0x6ab9d204	0x0d16385c
-	0xb1cb5e16	0x8249a5c4	0x29d1ce0e	0x779f7b63
-	0x63042725	0x12ce98e3	0x11282058	0xca3a9eb2
-	0xdb8294e7	0x423e41ac	0xc3ab2774	0xca658d6d
-	0x519f8896	0xaf6010f0	0xd57a94aa	0xcc17df91
-	0x7d25cf8b	0x041e6835	0xa056d9e0	0xf90f3964
-	0x7f99ae59	0xd80125d7	0x9961d6e5	0x41b3da06
-	0x65c254e4	0x787d2c61	0x16aafb02	0x157ab4a8
-	0xdee3674a	0x1ed1b601	0x2e36dae9	0xad57ad38
-	0xaaf25b15	0xd3c37a01	0x68ca9eba	0x2a1bc480
-	0xba157917	0xc00017c0	0x190bd74a	0xd6c6c1cd
-	0x4efd4f71	0x388ed702	0xc8812950	0xd0019ca4
-	0xd44cc835	0xd838fd6a	0x1432ce88	0xce98d932
-	0xaea21cf4	0x54a44cdf	0xdb4dc5ad	0x1d23a7ae
-	0x5ae126ad	0x100dcb50	0xa9727413	0xcf1c61cc
-	0x72f9d2f8	0x4d32d201	0xe27586a8	0x0a1cc932
-	0x21858469	0xf1cda3f2	0x59703f35	0xbd81f9f4
-	0xad6ac9cc	0x25665703	0x1212d5cc	0x98a243d3
-	0x8f47e113	0xd98feef4	0x3c93e832	0xfd67097a
-	0x0c73fea5	0x6132ec59	0x1dc9bdb7	0x791f79eb
-	0x84d83574	0xbd5817e6	0x7d5a0f8d	0x18482a08
-	0x53ac8e4f	0xadd3378f	0xd48540ac	0x4082f5d2
-	0x3ff5badc	0x24855b3d	0x7bb948f8	0x72637822
-	0x0687e93b	0x61290b4b	0xd9f20b3f	0xcc0e5beb
-	0x141ca01f	0xecd1337b	0x8576ec65	0xb6f825a2
-	0x8b84e8b6	0x5bac53f1	0xd4edd06a	0x76ae712b
-	0xdc00a887	0x798c2ee1	0xe74a5ab5	0x1539fa68
-	0xa30817da	0x06f7c53a	0x1930c59d	0xd4232359
-	0x0dfb1427	0x58d7180b	0x53bf57f9	0x5f001d08
-	0xd08128ed	0x3208b7be	0x5c2aba8c	0x0abbd0d0
-	0x424f2041	0x7982f731	0x010ec811	0xa3489c82
-	0x71ffdfa7	0xda0ed41f	0x8a9e806b	0xfa9bddcb
-	0x7a9e1a41	0x53c7603f	0x9e3df28d	0xd06dd100
-	0x2cc64f4a	0x0dfdccf2	0xb4eb9101	0xf56d506d
-	0xdaeed218	0x45523a16	0x4d6d68ba	0xff9a8f72
-	0x5358b2f1	0x2511a591	0x9ea2c2fb	0x08cafc7d
-	0x7ed34bb1	0x0cf2301e	0x62b6c05d	0xc05095ec
-	0x52128c55	0x030576af	0xef5f37a5	0xdf5ae47a
-	0x39e55496	0xb2c2129e	0xb2d67d77	0xc5adf049
-	0x15a1cb4f	0x981948e5	0x7d18acc0	0xec7abb43
-	0x23f7e366	0xa919a355	0x23872683	0xb7b6d84b
-	0x4767dab1	0xd133feb1	0x2e5536cd	0x587683d4
-	0xa181575c	0x4329e640	0x1244ae40	0x5be82f66
-	0x4b28dc4b	0x4106c9a9	0x517fad7e	0x9e334ca8
-	0x3c3ba741	0xe902a475	0x91d046a8	0x31361f96
-	0x911b83bc	0x6607fac7	0xdfbc6390	0x7213aab0
-	0x8ca8a47a	0x4f3d1f3a	0x3ee76c84	0x22bac3f0
-	0x475f3cab	0x05d05569	0x92b3f912	0xc632a733
-	0xd79b7448	0x595b82fa	0x6013b96e	0x6d03b5eb
-	0xe37045fb	0x6e4add26	0x11f116da	0x4ac8bd3b
-	0xacb5f8a9	0x8fb943d6	0xa9ac31c7	0xf1ba9752
-	0x43a6b29a	0xf123766f	0x536fcc32	0xcf8168ad
-	0xd8fb1e4d	0xb9562fa5	0xfe6d8dea	0xd31ab16c
-	0xf7dfc381	0xb70f11cb	0x371c6688	0xac3fccee
-	0xf130a51b	0xc5b8cad7	0x0cb13762	0x64ae00f2
-	0x45cfad12	0x753d6a4a	0xc6f69472	0x695fba60
-	0x49d1f754	0x9db947f2	0x2364ae20	0x197492e4
-	0xc5b9562e	0x34963cec	0xdc26402a	0xa1c88d01
-	0x58e27195	0x9d60f5c4	0x3e200a43	0x7e9827f2
-	0x0a4feee5	0xd401e139	0x17352152	0xd509564a
-	0x4b3142ed	0xef7567fd	0x9a619dbf	0x56ec2cb7
-	0xc64bb290	0x3d69fd89	0x897325a1	0x74e2cb7c
-	0xf270fdac	0x2beb6a4f	0x5b60de30	0x49df7517
-	0x294966cf	0x87f5f667	0x4a9e1f6a	0xabc332c3
-	0xfaf358aa	0x5baa6cfb	0x36b99bfa	0x40259687
-	0x584539e2	0x2710ce99	0xec1959aa	0x642c8413
-	0xfc005d36	0x2b2e6245	0x0012d041	0x09f6b626
-	0x70fe9e2b	0x3cf30c5c	0x69d0a3ed	0xfe621601
-	0xb6fa9267	0xe9b507dc	0x49f35866	0x4b97647a
-	0x9e721adb	0x89e6e8d6	0x407a2f49	0xd977cbaa
-	0xd9359f5d	0x7b69702d	0x22d6e818	0x57eaa5a3
-	0xdd5063b0	0x4d7d2312	0x7a865203	0xb7f0905f
-	0xdd2c2b87	0x7215803c	0x1abe5307	0x2926f38b
-	0xf6b0cacc	0x96f50647	0xb612feb7	0x6915bfcc
-	0x058b5cb0	0xc39e47d5	0x7513abdd	0x9e43972a
-	0x1e55f640	0x896db1c5	0xd9382d2c	0xa52c1f99
-	0x8afaf5cf	0x36500aa3	0x2e65fa1a	0xbb40d668
-	0x81188e3f	0x143fba69	0x3f61fc90	0x438d759c
-	0x893bb96a	0x069f349f	0xffdc43c7	0x6ebfa943
-	0x671b4751	0x629cec23	0xe717fb9c	0x53fadc0a
-	0xddc1e212	0xb99788ba	0x78378cf8	0x2ed91106
-	0xec1de376	0x98d86b3a	0x312a190f	0x0208a0da
-	0x6dcb469f	0xe6407c6b	0x1c7fea86	0x83841afa
-	0xa9caaffe	0x86e3fd0a	0x918af9b0	0x0fabdf39
-	0xdd9fc8f7	0xf9ddd98f	0x3dd0acce	0x2064360b
-	0x29006620	0x5d7733c2	0x682c4093	0xf038a8b4
-	0x3a688845	0xf9d0b9d2	0x27f51a57	0xb63b063c
-	0x533b082b	0x7f0d0dd1	0x7abdb018	0xea6f6176
-	0x13394ac6	0x825339bb	0x1835fd8d	0xaa46df84
-	0x0751fe4b	0xbc9fb7c7	0x233873ff	0xca200e1c
-	0x668fd5a5	0xda059135	0x2baf8828	0x7a2efc0e
-	0x7c63d98c	0xe71ea373	0x0f218e88	0xa031f88f
-	0xf32bccf3	0xf15eadad	0x6df44be6	0xb2536e4b
-	0x2903a9aa	0x42ef8689	0x444432f2	0xd27a6c4c
-	0x0992a32e	0xaf6e65d2	0xcbefdf23	0xe602151e
-	0x21beace6	0xd9b992b2	0xe43286cb	0xdb315c09
-	0x0de7672d	0x9d518ff0	0x75c4e9a0	0x64b2f70a
-	0x9deb697d	0x5bcf59b8	0x2e4b9a8a	0xd9294b49
-	0x3fee760e	0xfba8fec6	0x1c140305	0xe400487f
-	0xc4cd4a38	0x14e6f1c6	0xdf98e7f8	0xfa6c4992
-	0x62908c82	0x37393196	0xc02464b8	0x4b119742
-	0x83e5e79d	0x15ddd908	0xf75d1820	0x363025b9
-	0xd9e1a04b	0x9e110da7	0xd8caf954	0x30f62bc6
-	0x875fd2b7	0x8b67bc8e	0xd5c77d4c	0x1a8ce00a
-	0x7cfb14dd	0x3a39fd65	0xaecc2b5f	0xb017dbb5
-	0x6a57b4f3	0xa27b6509	0xcdb06076	0x000d6366
-	0x66e4f311	0xf22e25d7	0xf91d9bc5	0x5f9d3a05
-	0x3b37c96c	0xb0596f50	0x53c24ede	0xb620106a
-	0x5e675314	0xd98d5b02	0x75261f6e	0x5610c20f
-	0xedcbe43f	0xbe85b8c2	0x16f7ffb4	0x55eb91fc
-	0x2605ab1b	0x5ad3b426	0x3658d764	0x639c0560
-	0x987249ed	0xdc470fa2	0x0d112f6e	0xd8ab77f7
-	0xaed9455f	0xd9f6a341	0xb9b21249	0x3ff2b69f
-	0x37ad61d4	0xdd6a089f	0x609233f7	0x46a923f4
-	0xe5c23e8b	0x6aff8687	0x5e8ece1e	0xc65e1e4f
-	0xfb96cf51	0x9b697cce	0xb08e02e2	0xf874e0e9
-	0xbc983fa6	0x870375e3	0xc88bcd2b	0xc6bb19ae
-	0xaa0c99e3	0xb301ab7f	0x024ba529	0x4449828a
-	0xd226454a	0x0a610f3a	0xf302a0f4	0x021a3cc2
-	0xa9e4b6ea	0x0b690b92	0x3379c01c	0x36265ea4
-	0x29fbc8a3	0xe6279573	0x3cdb8a1e	0x005b5332
-	0xbab71a8e	0x9677db73	0xa8a6d6ea	0xf0afbd3d
-	0x576fbee6	0x49a54473	0xfa7c6e95	0xcb914daf
-	0x58266856	0xa6b53a63	0x7136515a	0x2a3da411
-	0xb1c994e0	0xbdaecd7b	0x5b436ff8	0x6334ec5f
-	0x0172b5d2	0x57acd652	0xca4efacd	0x87e7d313
-	0x78ac87c8	0xaf7602aa	0x3769ff6e	0x86d39747
-	0xd32a7aa7	0x840cb30c	0x3e7da9b1	0x3c905b44
-	0x90290dd7	0xebc85f3e	0x32693a53	0xc7140058
-	0x6ca5cf6c	0xdabfbc3b	0x3d559486	0xe5ce93b9
-	0x8d3c428a	0x9d18b8ee	0x404f58d3	0x151b4a78
-	0x2f393e9e	0x69c59344	0x7879e974	0xc32217f5
-	0xb946562f	0x1d1b8745	0x3666cd1a	0xc6a1e2ef
-	0xe22d2e5e	0x9e7ed504	0xe6c32118	0xb2919117
-	0xb2bad34c	0xe7177e87	0x47b68328	0xe579fe7b
-	0xd0d33f00	0x96923c90	0x5ff2bf45	0xff074961
-	0x4dce1092	0xe8a89464	0xc0b1ea51	0xd65f0f12
-	0x6b2389bb	0x48fa0960	0x82722b27	0x62625540
-	0xd4ff4985	0x768b7c26	0xb36a4ec6	0xf6a66375
-	0x1c89e246	0xb629fce9	0x6aa72399	0xd783733f
-	0x6478b123	0xa374412c	0x11b5cfc8	0x73cf2286
-	0x443f5601	0xd817fca7	0xb2ce2d63	0xf6c63479
-	0xd16b0550	0xf2a52ac4	0x7843803c	0x1ac3b58b
-	0x7f96b915	0x732403a1	0x64634349	0xd2ec0bf9
-	0x10410c08	0xe95d8dfa	0xaaeb33a5	0x57893eaa
-	0xb59afac2	0xe9fd6dd2	0x50d11a7f	0xde479c58
-	0x9dac27dc	0xebba7d8b	0x17fa1420	0x74a1678c
-	0x71ccdaa3	0x5e44b0bb	0x5927a75a	0x7b7580a8
-	0x33330c9a	0x40192652	0xba6308de	0xecc81fbe
-	0x41d48824	0x6ce4e0c7	0x145e9225	0xf8484bee
-	0xc8675611	0x750ec207	0xfa5f5b85	0x618b9f8a
-	0x007cdb05	0x67f98d4b	0x1035f305	0x8d700e9b
-	0x9857a0bf	0x4b774ad8	0x8960c81e	0x344a9462
-	0xee2680d0	0xebb5f6cf	0x7397c9f2	0xcafa01ec
-	0xaf69f3f4	0x0a1699cb	0x90ed82f8	0xc5c8ac04
-	0xe50bd06d	0xf75741c6	0xea52365c	0xd0c03f33
-	0xb5e4e95c	0xebf55379	0x0aae6e4a	0x29f8b91b
-	0xef8ad2b9	0x7bebf2ca	0xb194b728	0x7df7b083
-	0x0ea527c4	0x6d55939f	0xb9242c58	0xb3e1f570
-	0x4fba0507	0x82d7259b	0xb5be7b54	0x0aff6ff9
-	0x88391023	0xfe352956	0x4a6bfb30	0xa00c9644
-	0xc478d534	0x0cdb509d	0x9611713c	0xd7c442be
-	0x8d16889f	0x93abfefe	0x435fa757	0x40d95d3d
-	0x11b7bdce	0xd074874b	0xdce6add2	0x0b652a4e
-	0x595a88e6	0x307a223d	0xb624b9bd	0x855ba51f
-	0xad43c800	0x1fcf6afd	0x4bdd921a	0xd6777384
-	0x8da9f15f	0x5fb03ee2	0x5e6d04e2	0xb33751cf
-	0x55d9d38e	0x41589fad	0x6d311b4a	0x43046a7a
-	0x8d9c7304	0xe25f9788	0x8b459e1b	0xc9a3cfe2
-	0xe6ab721e	0x4de3c89c	0x5c2d2398	0x085d8d69
-	0x4e27ce73	0x1cc1f44e	0x05aeaebe	0x8cedb916
-	0x370b4d46	0x1bc29579	0x33d08b75	0x06b77cff
-	0x155693d7	0x125d3f0b	0xd8714e15	0x3b7427ba
-	0x13f6684d	0x834ee449	0xc5a45189	0xb2ad214c
-	0xa61be586	0x4e4727cd	0x563d1c31	0xd4ba1cc3
-	0xdb08cd16	0x4940a42c	0x43dfd0cc	0x9d43222c
-	0x638a0d11	0xc33d3992	0x98bf11f0	0x1aebf6b5
-	0x1e206582	0x5647f772	0x9255ad74	0x75915665
-	0x0fe7dd12	0x9def740a	0x9361bdf1	0xc1409fc0
-	0xd3bac631	0x7492ee87	0xe1e99dde	0x2fbaf552
-	0xfc24f52c	0xc080882a	0x0a2417c8	0xcea3da70
-	0x4fe34fad	0xb4e55427	0xd5d54d76	0xf36686ba
-	0xd6ab1798	0x1868e364	0xa380f948	0x0eaee02a
-	0xad5a44e8	0xb6d119f4	0x82a43444	0xafad0e68
-	0x595c3ab7	0x385746b3	0x32df6d2a	0x0b01b2de
-	0x51d3d6bc	0x107d8620	0x6d215143	0x29d0e901
-	0xbc57a3ec	0xd584ba34	0x8c244547	0x23d396fa
-	0xffb03cb4	0x8396c1a7	0x3f251905	0x8bc769b3
-	0x68f4696c	0xfc297895	0x9ec65e40	0x22deb20b
-	0x5d1def76	0xa7a095b1	0x3aa6a458	0x6ca11880
-	0xcde44ece	0x62b59f4c	0x067f272d	0x9a5aae97
-	0xc60a8d62	0xeb0f40c9	0x83ebae30	0x07dc9cb0
-	0x05dbdc76	0x0c108eb1	0x314f9247	0x7bfd6072
-	0xf648e1c0	0xae70bd5e	0x7c27b4d1	0xb0cff1c3
-	0x8c2dd93c	0x580a4b19	0xfaa1ee8b	0x4173a23f
-	0x838fa15b	0x2b0fe3c5	0x8059250d	0x659a445d
-	0x2a1c1968	0xbf13412b	0x1a9f915e	0xaf80263d
-	0x24508a66	0xe381d252	0x4e0f55a2	0x7ce1f4fb
-	0xc145da4d	0xbd4b29c3	0x27540ac2	0x23ad4b42
-	0x8e6bcda5	0x20061c20	0x1d3cb3fd	0x5c5498f3
-	0xc468681d	0x4c28ef55	0xf0165c1d	0x2dd6d032
-	0x7e347ccc	0xe04db59c	0x7caa883b	0x1f43df4f
-	0xc300031c	0x85f19e9b	0x22811fa7	0x2622940e
-	0x6299f57b	0x5c106568	0xd7da296e	0xccd36b39
-	0xe349afc0	0xd2c2463e	0xf7f55aef	0x0e0a7e3d
-	0x6b6fc6d1	0x8854098e	0xc87edace	0x8190c437
-	0x333b8ec6	0xe49b3a5b	0x4aecd4e3	0x14cc5f22
-	0xa11faf96	0x3d1cd023	0xae614c70	0x0ab662b4
-	0x908d8082	0x76316cd0	0x3068ec32	0x829b047d
-	0xf08d1b94	0x3b2b33f6	0x03df9ae8	0x40f632d0
-	0x3590085b	0xa33aad24	0x39597da2	0x99415f4e
-	0x7aed6e11	0x61a920ab	0xca851d8b	0x2606f821
-	0xeb7c0e8b	0x8bd6edb1	0x725b39f6	0x3afa6248
-	0x03540044	0xfb118ecf	0x8e18bd5a	0x2a85cc05
-	0x4ecac12f	0xf53a4d25	0x8e3fc6fe	0x32233799
-	0xc7ebb5e6	0x058fdcaa	0xe6db17ed	0x2751405c
-	0xa195a515	0x34410c51	0x4517154e	0xbbb5674f
-	0x28050e40	0x8fd71724	0xbe78711c	0xc1b18693
-	0xd202b9d2	0xdf4e0b62	0x460349da	0x71463aef
-	0xb2fb55d3	0x54a972dd	0x49379f09	0x7a7fdff3
-	0xbd82d4f8	0xd2894393	0xa82bca57	0xe61ca9b4
-	0x9e08e6a0	0x53dffe9d	0xe7ae1c5c	0x65bff365
-	0x7564aef8	0xd94abd3b	0x18d1ba52	0x64a759f0
-	0x65c5dd4f	0x6f9d433a	0x57cb5a25	0xc1862d25
-	0xcf50223f	0x90c2724d	0xf5527605	0xb085f18a
-	0x41e2b17d	0xfb1cabc4	0xd8ab04cc	0x761c2166
-	0x8365afd4	0xc3276657	0x14f64be6	0x5dd779b7
-	0x3b3f1faa	0x358d01e8	0x4c821ddd	0x7ada9f95
-	0x2970bad5	0x3b54a4bd	0x3ca7f039	0xcb67aabc
-	0x3b264655	0x96401a5e	0xa3990376	0x90834685
-	0x8ba56352	0xee98c564	0x4a0534ed	0x7d70fad6
-	0x5d73a1e7	0x23fd8de5	0x39c52296	0xefef1540
-	0x7bc934dc	0xeed157b4	0x898d8bfa	0x5761e88f
-	0x73af2674	0x2fb88d9e	0x28de1281	0x9aa76119
-	0xa3ac21ea	0x28ce635c	0x7596d79a	0xd3295e0b
-	0x7826630d	0xd815ef01	0x27cf2899	0xf3de6a01
-	0xcbb32e58	0x6c57be3c	0x292f819f	0xaa4623d6
-	0xb96ab772	0x90a6f778	0x44b9933b	0xa43e7543
-	0xb9f417b7	0x7a6537a5	0xf36a6da2	0x0a9bb3fb
-	0x177c1f28	0x0512c07f	0xdda55932	0x060dda31
-	0x14465771	0xf3f96780	0xb459e5e3	0x49aaefbd
-	0xb07db15d	0x2ac82807	0x8404060d	0x417d036b
-	0x70946fb1	0xe39e68f5	0x5f9b3035	0xf0335e7f
-	0x2ba457c6	0x2d97ba3a	0xc05156e7	0xbbc9afb2
-	0xd25981ea	0xe70d060b	0x805c231d	0xae471b34
-	0x31964d8d	0x3f34e35a	0x8355ee21	0x73822024
-	0x9ce5f2d6	0xdff19812	0xae55cbaa	0x55f5ecbd
-	0xfe558210	0x09b95751	0x41ee7cb8	0xd2b9fa15
-	0x342c07e5	0x7ee50e8e	0xb6154e01	0xdbf4df3a
-	0xd43e2c77	0xc3ff0498	0xd8106f33	0x9bdb25bd
-	0x40cb843e	0x106b08a9	0x3227ce7b	0x58bb7cb6
-	0xb84e3244	0x3f1d0e20	0x76dcbcfd	0xb750bce7
-	0xa8c11f3f	0x161a8610	0xdc1ef5bd	0x14270b6e
-	0x285e7898	0x68375db6	0x01d23b44	0x35a17fb0
-	0x7c9ad882	0x7bda2e0b	0xca67bfcf	0x6e2dd9ab
-	0x227a6aba	0x5d295397	0x5061f96e	0x47a20c68
-	0xf5427e3d	0x3a0a3165	0x2438fd9c	0x2dc91147
-	0xeabab62a	0xdc358e4d	0x7e1fcc9b	0xdc2a328e
-	0x6e6bf75c	0x68c45517	0x594fe5a7	0x2feac658
-	0x1f0a4d49	0x97575e83	0xcccbdab8	0xc13f3b64
-	0x8bfe659f	0xa4ebf545	0x2c3cf874	0x7d78ceba
-	0x46ac5d6e	0x09309533	0x78ffb6e3	0x7336541e
-	0x3d270f70	0xd71e72b4	0x9772402a	0x4ed185b7
-	0x213da698	0x78a54587	0x18054eb4	0x99179a25
-	0xf758337b	0x94629a30	0xec6bf4e0	0x255ac299
-	0xe56f52b1	0x1c2a6136	0xfb7cc1f6	0x87b53b53
-	0x079ca1f7	0x3a8c340f	0xeb70ef48	0xfd1caae4
-	0x564445e7	0xc1d5c663	0x658fb5fa	0x62d2debe
-	0xc0907042	0xb5402269	0x16965193	0xc038c21f
-	0x780f8b76	0x33ffeb3d	0x03ad9602	0x4a7b6432
-	0x93c2b2f5	0x40720fcd	0xf44c164f	0xcbd43d01
-	0xcf7098cd	0xc43242fa	0xc530a6b3	0xcc33c1f7
-	0xde3d648c	0xf1def13d	0x2a22f5d1	0x77704fc6
-	0x08ed5552	0x3e2295d0	0x00584764	0x6af8585e
-	0x43f845da	0xa92e38df	0xd98c12b4	0xb4fac901
-	0x0b05a079	0xa05f215a	0x27d635c6	0x9fc897e5
-	0x0eb91a30	0x43bdad4c	0x705df05f	0x6b7864b7
-	0x1b6380ba	0x4a64e8ec	0x517b7b68	0x67336d4b
-	0xc6d51eab	0xfac40c57	0xb977cbcd	0x0674e5dc
-	0x74ce2339	0x891cc5f5	0x3230ca78	0xa8a653a0
-	0xa8d4b370	0x496d2f7f	0x6ca677c5	0x54260ac2
-	0x630e1143	0xcbf6f819	0x546b2874	0x02267559
-	0xa2e23914	0x7c9a0393	0x1704bcb3	0x6d680415
-	0x91da300d	0xe2ce21d2	0xc38faf3e	0xcc8be7cb
-	0x14496036	0xc98e253a	0x05ca6582	0x8c566616
-	0xd26204dc	0x3335bd81	0xa94e5af0	0x76fbb455
-	0x23b27f08	0xc4db6f93	0x5cb5401c	0x7cb2ed29
-	0x7cbbad8b	0xfc1e8f5e	0x2bc79e28	0xf69228fe
-	0xbde16357	0xc9ac3b53	0xa6afbc74	0x984bb3f4
-	0x98a8b9d6	0xdd21c848	0x33e65c3a	0xc53c772c
-	0x633022f8	0xa324bd5a	0xd260a77a	0x668ca5d3
-	0x4b79a6b3	0xbfd19bbe	0xca2eb497	0x8e7eb5c9
-	0x169b2184	0x0503d4f6	0x24f35c00	0x0ac930ab
-	0xf694120f	0xcee12db4	0x9305757c	0x798a2db2
-	0xed27ebec	0x2f35829b	0x4294e805	0xa7994ad7
-	0x49fd229c	0x5d63fe52	0xb7cd7641	0x1a68af3b
-	0x6f952e97	0x1c02f4de	0xca3a1515	0xed5bf092
-	0x123c32ea	0x602030aa	0x7811cd1f	0x1b6c38dc
-	0xeb7712b4	0x4aa767e1	0x6b49d384	0x7ba4ee1a
-	0x87f02cd2	0xb8e6b0b1	0x090e9f89	0x95f8b90e
-	0x8d76892c	0x0be06870	0x9ec963c1	0x75d67c9d
-	0xdde23799	0xf9e3be20	0x549442fc	0x09cb0906
-	0x95ee6c4b	0x25a2d9b7	0x98154023	0xdda91829
-	0x0c46879b	0xfbf0e362	0xb7223786	0x7cfbc839
-	0x3b251e5c	0x8be187a6	0xa24f9da6	0xc3192693
-	0x7a8ac8b9	0xc493ca03	0xc736b974	0x369db725
-	0x85a6e92f	0x26dbef75	0xa61a71e9	0x38a08fb9
-	0x4a214ed6	0x57fc6f4b	0x9cf91617	0x322e13fe
-	0x5ac816a3	0x748a9728	0xdc777bd6	0x69fb5335
-	0x258439e8	0xf171a221	0xfa7a07af	0x26447b9f
-	0xadcf3734	0x5af34b97	0xf8b4b0dd	0x08c79517
-	0x28861618	0x64692555	0x19fe9897	0xe3bda02c
-	0x77df51ff	0x93dedf7a	0xc7cb57c4	0x02ee5928
-	0xd4aeb644	0x01d511e6	0x6512bd02	0x5d8f90f8
-	0xe77ccfe0	0xe6ee3ecd	0x5403139e	0x6f7075e5
-	0xb6484511	0x3bd42a35	0x5dcea90c	0x5bb1c6e1
-	0xb69b5847	0xfe106914	0x74442ce9	0x10997c57
-	0x1595af7f	0x9f04a8bb	0xa7d2870e	0x19e57681
-	0x54b276be	0x11c3e3f9	0xc5401783	0x9c413cda
-	0xa6aa9e8d	0x23ff8569	0xf1797ea7	0x86ce3e8e
-	0x9ef0a776	0x56a1c30d	0xf5e18916	0xb11464d1
-	0x7f313c1e	0x49c15cff	0xe2dcfb73	0x637819d8
-	0x2d6ce0e2	0x2170cd43	0xb750902d	0x5eb02cd2
-	0x6cadb7d4	0x89b96f3b	0x8d749ca2	0x8ac7abb7
-	0x31fbdb51	0x7a6df774	0xfb9139f0	0x56f3d9c3
-	0x0f104f2f	0xfaba3c49	0xe53aefff	0x932237d0
-	0x8ee10e80	0xadad6e20	0x19883a1a	0xf45a543b
-	0xd560ff0a	0x8c7b4e03	0xe35696d6	0x9e0ec159
-	0xfc2cbae5	0x6ce2cddc	0x14a72474	0x89757fe3
-	0x6b788e7b	0xc16fa200	0xad36bdf7	0x57bdc4d1
-	0x55146f2b	0xa57db4c5	0x313952e1	0x2c55d0d2
-	0x32ab0208	0x10f846bc	0xdcba1674	0x436485bb
-	0x932704de	0xcd7e2e1c	0x59f78879	0x7ca21395
-	0xbcc07be6	0x2b101e5b	0x38924c37	0xb90928f4
-	0x8f824214	0x55699b67	0x54cba493	0xe71c27a3
-	0xdde01c05	0x48d822fd	0x734ed8fe	0x29dbf298
-	0x9ef3a499	0xfb517934	0x19c8ce8b	0x38b8bf00
-	0x75da50eb	0x237f3b1d	0xa8940707	0xa98a4149
-	0x35ec2d39	0xee862d31	0x36659949	0x8f3dffc2
-	0x70afb227	0x94f443c1	0xb6f9308e	0x0e8ebd54
-	0x92b8960f	0x56d21560	0x8453d1ca	0x74c680c0
-	0x2d706dfc	0xd0b81c18	0xbac65445	0x40a34988
-	0x498145a9	0xf436ae10	0x9b72fec6	0xb4100aed
-	0xe305983c	0x349fe379	0xbf31cfa7	0xba624703
-	0x4a491754	0xf973a686	0xa2ba725c	0xd0a23615
-	0x31903086	0x4ae46e45	0x0f705e05	0x4ea6bbc8
-	0xbf299e43	0x0689709c	0x9fc93571	0x07cbc14f
-	0x542ef992	0x80ce91f1	0xf86014aa	0x17d533d1
-	0xb55e63e2	0xe02e0e4c	0x88a5ed22	0x6302126a
-	0x56b32e90	0x5fec4381	0xe2e98b3f	0x30693509
-	0x862e1d75	0x2da30e3c	0xad992d90	0xc62cae4b
-	0x379c77ba	0x467ea8f1	0x8a820048	0x74cc474e
-	0x6bca3803	0x18aaa3f3	0x1fafd26a	0x0865f360
-	0xe3479d10	0x6cefb2b9	0xf6612730	0x2e0f222a
-	0x749a89e0	0x75b1fa05	0xe2ea0874	0x5d422c20
-	0x24707d46	0x6d475835	0xed1e556e	0x6aa4543e
-	0x28b36c16	0x22d83c4a	0x8c3e6d51	0x42a94c9f
-	0x0c603d0e	0xa8c7f417	0x845997ff	0xdc79494e
-	0xa130d628	0xc2df082a	0xa3a2c27e	0x3f93b00f
-	0x1521a7e5	0xca15bae4	0x57e4e836	0xb915a471
-	0xd9147115	0xad52f80e	0x5fd2a2be	0x15972ed7
-	0xb69ec21c	0x502f2627	0xfb46a1ca	0xea685d34
-	0x9226f7f2	0x4b41927d	0x7965eaa0	0xb702e76f
-	0x79a54721	0x5b8e984a	0x37efcd59	0xfeabf30a
-	0xd4ad7db5	0xbb2282ab	0x8a5c840b	0x2ba370c5
-	0xdef5758d	0xa69a9aa1	0x46082250	0x6e8e8477
-	0xf6280c61	0xf99e4a14	0xcf3c5cbd	0xcce657f0
-	0xca635eae	0x0be182b5	0x58e8b43a	0x5c717ce5
-	0xaa7aaff7	0xc329c6b6	0xf1cc91ef	0x8d7cc520
-	0xda155783	0xd5e2e54c	0xf466f010	0xc5dfac4a
-	0x606ad5de	0xf4992f1a	0x1344c9ce	0x4aea9020
-	0xa30447c7	0x0a99ad18	0xd3caa96c	0xfe5b0b4e
-	0x7b50bbd1	0x33e50575	0xa22d1d06	0x73a1820d
-	0xce4c4c8c	0x2cde7764	0x511d1c26	0xad0cf826
-	0x086dc311	0x3060ef7d	0xe6fdc617	0x3050b179
-	0x1dbb5316	0x4145fcb7	0x2eb62505	0x2e1359e2
-	0x79cab612	0xaa9282c9	0x7eede562	0xb016f7ed
-	0x1445fefb	0x809b2e00	0xfafaa754	0x69ac113c
-	0x548a6e3a	0x6d444c14	0xb3d355d8	0xbbadcd2b
-	0x3032d634	0x7df39948	0x4c1f9098	0xa9d138ce
-	0x42823bbe	0x2ef39e3f	0xaaf9ef1d	0x63369afb
-	0x2bb76c9d	0xb7d38558	0x354160ce	0xc04c6378
-	0x6c71ab10	0x7914af1a	0x1c1a4694	0x2f9fce8a
-	0xe28f18d3	0x3acaa573	0x2503b236	0x90ca20e1
-	0xd2c77ccc	0xc3005311	0x836d9430	0xe91d8463
-	0xb53e4cb7	0x4e373c67	0xd06ef659	0x27e1a21c
-	0x285c0391	0x32046fa9	0x8b1b9c92	0x49a22f4e
-	0x81411430	0x050110e3	0x56144e6a	0x47fb824a
-	0xdb2e9a6a	0xb5fe97a9	0xabd37259	0x93da3055
-	0x19fb35e6	0x66661115	0xa27149a2	0xfb7d94b5
-	0xa315f9af	0xd7d97596	0x134d7d09	0xd5cde0e9
-	0xbc3f143a	0x1b2061ea	0xd7b15227	0xe8f506e3
-	0x0aa17e92	0xc8565276	0xc7d90586	0x22a26c8e
-	0x6d462029	0xe7b1ad73	0xd11fa609	0x67643f2c
-	0x64f1ef34	0xa0e7e0b6	0x9687611d	0x09c2d32b
-	0xb494937a	0xcc36510c	0x70555bfd	0xfa25e917
-	0x7d88b6da	0x30f3b531	0xd19b224a	0x999d0f7a
-	0x9fe0da18	0x45947b87	0x536dbf3b	0xa6f5182d
-	0xdf11f95d	0xa5abcdbf	0x7528110b	0xf54fe792
-	0x71a97619	0x680bd3ff	0x6981ea39	0x683ff854
-	0x302fbbe4	0x12129f84	0xf63cd448	0x69fe289b
-	0x568da933	0x2f1e1146	0xe7404e52	0xcd329394
-	0x02e41762	0x94456d4d	0xe9416a20	0x4e5920e7
-	0xe8db71fe	0x527a5313	0xe42c7d9e	0x58c8c1fb
-	0x28949bc1	0x312fdf97	0x3569f41f	0x3ed5f092
-	0x44baef39	0x5c11d5ad	0xb5d172cf	0xa9e4cfa3
-	0xbc5ed197	0x2f290ead	0x747f53ed	0xadf1b698
-	0x1b90440a	0x4cdfe154	0x9b24b832	0xeb97d794
-	0xc90fe91e	0x4fef1271	0x8bf96025	0xbdb49f79
-	0x63910640	0x26a05cce	0x3318e422	0xb2fc61de
-	0xf14cedd1	0x4bd7687a	0x8c4c91dc	0x48a857a2
-	0xb47aac94	0x787526e2	0x99349c7a	0x0bd6ba75
-	0xbfbc4b0b	0x040fbec9	0xd00de44b	0xc4c7f0f5
-	0x74a8653b	0xbd3cc036	0xa601a4f3	0xb82c0da0
-	0x2709b674	0x73065351	0xaf4cd23f	0x3481ea0f
-	0x6a1fa77c	0x26a9d280	0x95f4a170	0x393e7590
-	0x015b3d73	0x36d91e55	0x61a7f3f5	0xf6d39c21
-	0xd9ee4701	0xe57af451	0x5e141761	0xf6b6e472
-	0xa6efc965	0x9606aa1b	0xfb8ce005	0x831ab2d1
-	0xfe7a1af6	0x5e326881	0xa0ad32ae	0x15f86ecc
-	0xa1a634d2	0x3a40c4a9	0x88e10130	0x2e6c4556
-	0x8526aa32	0xa81b0d30	0x19c83936	0xdcaa556b
-	0x6dc8064e	0x5709ad31	0x1b6fba18	0x9ebe34b1
-	0x28abc3e6	0xd76c3908	0x4374657e	0x6f0fc085
-	0x4f19a108	0xb774421d	0x405228d5	0x123dbbab
-	0x18535471	0xfc6bde41	0xd4b2d82e	0x65b85772
-	0x64731e41	0x29e886f6	0x4c2c7eda	0x91586a5f
-	0x15b2407b	0x5fa08a72	0x56898e51	0x5424e976
-	0x19ce4a36	0x0ada4656	0xe634446a	0x478da533
-	0x36f1c763	0x01ec46c3	0x5e1d1040	0xf6da1918
-	0x831f8f94	0x43ddb630	0x80b5d4e5	0xfc403ba5
-	0x40dcdd4e	0xa19d0aa9	0x6c32fad7	0x7cdd6f3d
-	0x8e9c123a	0x42c4edd0	0xc8247030	0xf0e6cebb
-	0xf8d1425f	0xcfa8e403	0x67646391	0x9dee9f9b
-	0x5683c4f6	0xd958ae1c	0xc62eedfa	0xbd67ea10
-	0x253398d4	0x18b7f92a	0xf101a7de	0x60066732
-	0x4ca1e3dc	0x6e1eb0a0	0x115aa9e1	0x8370aae0
-	0xe46756d8	0xa02eb1aa	0x854dbb8a	0x6334873e
-	0x87613a81	0xb5bd56df	0x491371d1	0x02bbace8
-	0x2a2e45f9	0x91bdc460	0x2bcf90b6	0x81df2f07
-	0x34aa2dd5	0x5b54a117	0xb7a5bd42	0x713e2287
-	0x1ea184d6	0x176bdda0	0xa19c0d86	0x4180fd5c
-	0xd018a4cc	0x60120a37	0x8f6e094b	0xfebe1b15
-	0x42866bb7	0x4a9f772e	0x0bcf9cad	0xd936a924
-	0xec6cf0a1	0x1f9ccf16	0x81f8229f	0xdcef1733
-	0xb4a31fca	0xefbf0a0a	0x057e0b4b	0x59491c96
-	0x70ce99bb	0x908ce274	0x637ae09c	0x479fdd52
-	0x11ea6250	0x7778cdf6	0xd0ffe2ca	0x539b18dc
-	0xbcdab649	0x3066399b	0xd685edc0	0x79d8d588
-	0x32942aa1	0xd03531f7	0x5d024d56	0x4dc99729
-	0xd1efff53	0xdf3ce9a1	0x31462a0e	0xe5427113
-	0x395e2980	0xcf5c9d4e	0x91e11088	0x7e4d31e2
-	0x5ff91ae8	0x9340e815	0xfcb89789	0xcb1b2f58
-	0x655aa934	0x2eb022da	0x419104a9	0x6b648411
-	0x582048e2	0xa0db392a	0x1e1d6443	0xf3c7a401
-	0x1e737591	0x452af94c	0xfcb74331	0x2da70f75
-	0xa8b59eb9	0x736224c8	0x5ba81657	0xfb36eac0
-	0x4e0336b4	0x8925a32c	0xa4d60fde	0x8a95ff27
-	0x57a7e536	0x7e6a2f58	0xd9e9751e	0x817cc66a
-	0xca4bd134	0x627382fe	0x00e56736	0x74844fbc
-	0xab1f8265	0xa32955e3	0x41cd361a	0xb3ae6366
-	0x1f77ea37	0x2200c6ef	0x81854e76	0x49ed4e92
-	0xb57a7fbd	0x7b9de6d2	0x128feedf	0x57bb65fd
-	0x20ccd650	0xdcde5458	0xd5461b27	0x465147f4
-	0x70719068	0x2cb48f5d	0x6edc0d43	0x83dbda97
-	0xf077ea64	0xf61423e2	0x39a55177	0xb23ff07c
-	0xa02e4ca4	0x9e6250d3	0x77f1df9c	0x238c632e
-	0xce253a6a	0x096327c5	0x87f1db29	0xd75ac0de
-	0x456704b5	0x9ee7046e	0xd693dfe0	0xf995c6b9
-	0xa354d140	0xf16bf090	0xaf511cdd	0xdc56d21e
-	0xd7cc4d4c	0x5398cc1e	0xe5444b3b	0xe192f473
-	0xd09ae67d	0x8af2775e	0xc1af44a9	0x57bc4586
-	0xa6ff5419	0xdd4ba49d	0xec4864fa	0xda9d0357
-	0x84dfbe33	0xf41ba9c4	0x99e2bda8	0x9fba720b
-	0xa7dd9e92	0xa0d43386	0x3e0f9ef2	0x6e388282
-	0x8f47ea95	0xac920523	0xa98ae8a5	0xf6a6a4d4
-	0xc3fa2e55	0x74a21b36	0x9c0b14b2	0xc6b8a79a
-	0x367b7036	0x24b9f255	0x0b543b75	0xb630fa41
-	0x1b260452	0x7daf6714	0xdb8a13d9	0xede8f6bc
-	0x47a21d0c	0x01d9ca54	0x4a8e5cd4	0x257cd217
-	0x7504cecc	0x973bbf11	0x992b731e	0xaab55b65
-	0x77e2f058	0xf580b58e	0xb10419fe	0x679aa4df
-	0x296c1d64	0x751380f0	0x8f70f0de	0x3f78bdb8
-	0x1ee68ad6	0x7d5d50e4	0x823710a4	0x18b98d13
-	0x86bdf798	0x953b8131	0xb5da3d24	0x2eccd3b1
-	0x828a154c	0xed51b913	0x566e58ef	0xab8ff1b4
-	0xc744d227	0xe705bbc6	0x6032eb64	0x5495e4a5
-	0xe83add11	0x08429de8	0xa2e397dc	0x4f00c90b
-	0xcb7672e8	0xa1d55607	0x0741ca2a	0x323d64f2
-	0xa700ef1e	0x6ccb2967	0x07c29e41	0x018440a9
-	0xbb1880cc	0x35502720	0x8a13a96e	0xe2bfcd29
-	0xa76ad3aa	0xd95be915	0x6dd66033	0x41d655f3
-	0x02009028	0xb44ec634	0x82e61d87	0x216e624a
-	0x7fc79105	0xac0307cb	0xd22fa331	0x63746b2f
-	0xe51ab72d	0x9b550c82	0xb28dbc01	0xd569d017
-	0xd168d372	0x8d6bfe6b	0x5820751c	0x820a4e23
-	0x13cfd07a	0x678c8319	0xd1e65476	0x752967ee
-	0xafb28392	0x390d5488	0x53668098	0xa0c92673
-	0xaf0549c2	0x644f51c3	0xd59df083	0x7cb37a42
-	0x12261017	0x038c15b3	0xccc30b03	0x85ee24ce
-	0x1e029b23	0xb6bb2845	0xb62a305e	0x2d0cf4e9
-	0x182b887f	0xec423ce7	0x8c1c0b25	0xc83b4737
-	0x71fb9023	0x63d639f6	0x16c1ce44	0x66ac8331
-	0xd9aa0975	0xba3d445c	0x5d097729	0xb353a034
-	0x23811786	0xb81394b5	0x5323f1b3	0x7a3e1576
-	0x3f2867ad	0x0bc88c8e	0x74b60d63	0xd56335de
-	0x0d40f71c	0x55ec2524	0xea3a2c78	0x19e5e0ae
-	0x9bf3d033	0xf57bbc94	0x05b6ac55	0x4c368744
-	0xae8c68f2	0xf23aad06	0xcf94d185	0x2360ff3d
-	0x0e8a87f9	0xb97c8d33	0xa7122e6e	0x5ad4dc50
-	0x6145ff8e	0x617389df	0xe8a0e09b	0x4d40ce6f
-	0xee2b65fa	0x4104d368	0xf4bc9d85	0x0b67abbc
-	0x7bbad9ff	0x26b293a2	0x06055372	0xbbb05665
-	0x0560311d	0x421dc535	0x9c451ac7	0x38c83a74
-	0xc8921ff8	0x634d52c5	0x6e66dae7	0x1c86fae3
-	0x5a0645bd	0x6e5fddc9	0x86852d55	0x76207d9a
-	0x6a4b7990	0x661c00eb	0xb268e55b	0x17daec24
-	0xa2854da4	0x9b1f3f63	0xdd200bc5	0x0b50aecf
-	0x8242f913	0xc7ab6eea	0xaa977c22	0x748d0d1b
-	0x4490aae4	0xaa293e18	0x69aa0720	0x6115eb81
-	0xa5b187fe	0x828bfe34	0x5fb6d155	0xe764d755
-	0x08833186	0x8475cce3	0x718bfb48	0x063b287b
-	0x7ea71b59	0xbedbfd29	0x3736aa07	0xe2dfd533
-	0xf2ea49a3	0x96b0983a	0xc1f60b14	0x511bed9e
-	0xac976686	0x9c60ce3d	0xfffd0b07	0x59d7cf79
-	0x477942b4	0xff2f43cf	0xeb4b899b	0x37a47783
-	0x8e6602a7	0xb6bfc410	0x7685c6e4	0xb7ec103a
-	0xd54fdb01	0x3933d261	0x725982d1	0x86ada0a9
-	0x83788370	0xbafb1498	0x13972979	0x2157be41
-	0x5e976c80	0x05501107	0xb3b66da9	0xeebcb8fb
-	0x42ac1fee	0x1dba34a9	0x3f5a7582	0x362e7ed7
-	0xaa69be91	0x419f4d18	0xb09a9967	0x31aba127
-	0xaa247bff	0xb31f4958	0xe79562af	0xfb73878c
-	0x47dc697a	0x5d08fa9b	0x91dcd3c2	0x53e52d33
-	0xc84ddc84	0xdb5f8e17	0xe51889e2	0xb1aff523
-	0x4ffa0702	0x2c72b35a	0x9a4246fc	0x62420517
-	0xaad11acc	0x18190bf9	0x11e140de	0xacc99086
-	0x39347992	0x191a53d7	0xbe92c4ef	0x9a934b5d
-	0x64cf7353	0xe30a3e8d	0x0aa6db52	0xb0a7e26d
-	0xc8fe2f52	0x2e274a07	0x0c94b6ba	0xf80eaf3c
-	0x1ba3e94e	0x5853ffe3	0x11652833	0xce7b0839
-	0xd1893c23	0xd06d2078	0xa65f020e	0x281e6a7d
-	0xdf1da5a2	0xcdf69d20	0x74fa9b92	0xd98d6000
-	0xb732496c	0xbd12f87e	0x561dc55a	0x651d42ff
-	0x5736b74a	0x2c48a906	0xfdcbaf15	0xf76606e1
-	0x80dd0254	0x8105e60b	0x143200b2	0x0f02f524
-	0x1580d2c6	0x7281c6fc	0xc971cd31	0xd4a57180
-	0x5051e5ec	0x193c72eb	0x930332c4	0x488d7403
-	0xa93e425c	0x93e8ca97	0xa0a55070	0xafd8f8fc
-	0xc424f1bf	0x11050ed2	0x855d0923	0xa0fcef35
-	0x61f9e84a	0xc2196706	0x7221d5f7	0x96d036a5
-	0x137ca3fb	0xfd632623	0x30b10850	0xdda390eb
-	0x270fc9af	0xe6a8d748	0xf55bc288	0x8cc912d1
-	0xf2d9cd15	0x5ded2f07	0x2de9b076	0xf5088354
-	0x885becf4	0x959ef88a	0x0d9ea589	0x2ceb0a27
-	0x8925270e	0xca5ecd99	0x8ba9265c	0x209eb0b7
-	0x2e8b51d8	0xc598e096	0x23c17aa7	0xf600bcae
-	0x7b33f831	0x223e1501	0x361c9f12	0xe6aeea94
-	0xa5c6948f	0xd1daf8cc	0x0b0e0b54	0xb0cea6c7
-	0xa437fbc8	0xdb4139ab	0xcbbad47a	0x124e2117
-	0xfb80c5dd	0xef085f4a	0xd24c5fa8	0x2548a1db
-	0x5e6cdeb2	0x8e4f0290	0x78cd8245	0x1ebb5eb6
-	0xd9bf1208	0xf20eaf0a	0x544df94d	0xebc9c742
-	0xbc5b4bbe	0x33f6fcaf	0x32efb07a	0x55d91b59
-	0x2c0ed1bf	0x39985cb7	0x4cab882f	0x530cdaca
-	0xccc78cfd	0xdd834c48	0x7ce7898d	0xf7458891
-	0x933c2ae8	0xa06c5762	0x2eb03e35	0x8e938b71
-	0x3636f142	0x0026efb8	0x183d71c4	0x7e8ff92a
-	0x63265ea6	0x0f1352b8	0x73f8a8fa	0x6594e921
-	0x401f88db	0x64abd8e6	0x994140c7	0xb2258b0c
-	0x9bd6e6a1	0x92bab589	0x5919a943	0x29ab4d8e
-	0x33cbb8d4	0x57084d92	0x006c4d50	0x57c49e54
-	0xec1ecfe6	0xeaa8109a	0x269d94a5	0x4a664f84
-	0x2bda2944	0xdafb85c7	0x2a7b4b8c	0xd8f124d6
-	0xbbac0e70	0xeac5a129	0x308d7e39	0x99a023a9
-	0xf616fc22	0x76fcc40f	0x7f745409	0x83872303
-	0x0b067846	0xdf90a414	0xb6d9b6e1	0x8d0f93d8
-	0x6f76a627	0x02f89060	0x392cb9e0	0x6acf19a9
-	0x7cffe4d1	0x9928b4a0	0x87a031bf	0xecff42d5
-	0xa376e023	0x69d2e1e3	0x1fb67afd	0x5396049a
-	0x45538549	0xec0e6f60	0xf1ab27e5	0xc679e764
-	0xee430c38	0xa6b0c2dc	0x92824db1	0x65d5ffe7
-	0x448b17d7	0x9c67c8e0	0x14b36e2a	0x283de0a8
-	0xc59bb35d	0x8faf1ca7	0x4265db7f	0xb0e74749
-	0x0924d389	0xc22bf3fa	0x017c143d	0x93b4e0d4
-	0xf8aa8e07	0x07e0293d	0x5b40bba8	0x619c8946
-	0xc817ee7a	0x82fd526b	0x3e5b0f9a	0x5b352d98
-	0xc786d63a	0xcbec5c0d	0xd05e9640	0x7cab758e
-	0xaa9bd61d	0x205ff53f	0x2f093865	0x55ef390d
-	0x4b008d12	0x0344c52d	0x64820f87	0x8e9c5202
-	0xdd3f2276	0xf3b46630	0x80e85ea0	0x9aea428f
-	0xa205b11f	0xa8506b8f	0x2c89f419	0xb0b9694b
-	0x21029e6a	0x5e05869b	0x3baf3c6f	0xde680ae1
-	0xd65b5eb0	0x99a6937c	0x52a78fe0	0x6f577b06
-	0x8dea8d63	0x2417d49c	0x1a0ecb5d	0x91f22002
-	0xc540298f	0xea9f8f6d	0x01ccfdb5	0x287138c1
-	0xef206774	0x9d5deed8	0xba844833	0xf612317d
-	0xe0bd4bb4	0x595d0440	0x73643204	0x2c21370c
-	0xf9d5df6e	0x05614527	0x73c4edee	0x33f45ded
-	0xbc47170a	0x24b94b30	0xff304e54	0x4e0c3b53
-	0x658af390	0x402418bf	0x9db7318c	0x058721ed
-	0x896bdd56	0xa956c5cd	0x3f928400	0x94c93146
-	0x56600758	0xf46f4f66	0xa5bf66d5	0x0e8b5870
-	0x8ba7e755	0x4177fee6	0x32cc8824	0x90b677d8
-	0x307e9dd3	0x853a7e3b	0xa2f064a4	0xa42dbd46
-	0x243ed6a9	0x7164eb1f	0x9e97212a	0x9757d142
-	0xde296a05	0x8699a74a	0xeb02fa7d	0xf80b41fa
-	0xd9dd2198	0xd7ffbd00	0x21b15853	0x11b78093
-	0xbb329142	0x5260fb1f	0x22fb24fe	0x7a5e7e71
-	0x71434197	0xc5ddca32	0x930c8cb9	0x65192958
-	0xad1a41f1	0xc77442ca	0x72b64ff7	0xa90bcde5
-	0x184a19de	0x71df036e	0x1b69b0ed	0x023c391f
-	0xd9847da5	0xca57d383	0x0d21255d	0x2ea68d9b
-	0x0189eeb5	0x1ea62386	0x4c8d42f0	0xac20dd55
-	0xacceef1d	0x972f56e3	0x0bc40455	0x3853c5a7
-	0xcab0d1f5	0x0d2a990b	0x525be1ba	0x5cc6daf5
-	0x4d564f06	0x834d8f94	0xc0c055e1	0xef34557b
-	0x354537de	0x7207e6b8	0x659c9298	0xa88ac04e
-	0x80d8014a	0x7f4f6e7b	0x1136e621	0xb1b62f79
-	0x8d4613ec	0x673699ee	0xdd6d7741	0xdba1ffa9
-	0xe219e1b3	0x8bf64c21	0x14aadc3b	0xc4dc4e19
-	0x47ae1e52	0xc5409e4b	0xce8d29d8	0xe0b1cf25
-	0xcaf06411	0xd5450dcc	0xf14f29ee	0xf3611dd5
-	0x52bc02f3	0x886b68aa	0x3b2853ef	0x110aafb0
-	0x6b6d765a	0x87fbaa12	0xc79f134e	0x88b910fb
-	0xe04aa148	0x33feeccf	0x3be43d3b	0x067854eb
-	0xf22561e5	0x56c3abc3	0xcf0ff408	0x6291d940
-	0xe26819d9	0xcfd04da7	0x94ab2808	0x156dcd0a
-	0xb6d1c47b	0xdca4aa76	0x877f870d	0x4e06ec17
-	0xbb560b01	0xbe1b62e7	0xd98b51b2	0x7083e3d5
-	0x427ab621	0xe5fce36f	0x606dc14a	0xe4b70b49
-	0x982d2446	0xf2d2e82a	0x60836061	0x681317fe
-	0x1667e3c8	0xf6eef490	0x1ad768d2	0xbc86ae5c
-	0xfbb392de	0x868caaaf	0x8429b5ff	0x266b6d5b
-	0x372e8f2e	0x6e875cce	0x3a972f08	0xabddef20
-	0xc777c559	0xd8f924a4	0xad39137e	0x4c16a4f0
-	0x91d51877	0xae645599	0x4d09feb1	0x0cdededf
-	0x5749b5b8	0x513c9745	0xf4da62f7	0x6583b20d
-	0xb599bb89	0xaf6bea53	0x7275f6b3	0xdefc5092
-	0x01a3734f	0xd95f4c5f	0x37bce97c	0x63610b99
-	0x30555fe4	0x20af2f26	0xf84b2652	0x67ef6d87
-	0x2119805a	0xcc79747f	0xaa479405	0x63a02857
-	0x1953fc39	0x4f952879	0x886bfe97	0xf0067752
-	0xa08b5005	0xcd9a5ebb	0xb04486e6	0x560c79ae
-	0xe8faf52c	0x64a9a961	0xae9a5f1b	0x74cb5ef7
-	0xf8d0269d	0x2fb63c57	0xd78a9a90	0x99cc0a42
-	0x46bb0252	0xe56b026b	0xfb5ff703	0xdc8e0588
-	0xe5d9e280	0xa73ec2b3	0xe21bccb0	0xe22ee743
-	0xd1bb3217	0x5d4b3f92	0x0a627d8b	0xf2fd974a
-	0xad0a57c4	0x261ba12e	0x1670f842	0x996ab25d
-	0xf6f8043d	0xa6cbb362	0xcac3044e	0x6fe01268
-	0xa54ab676	0x54d7444a	0xf3be5437	0x6b2b737c
-	0xbe10300c	0xea505599	0xd60a15f6	0xd971ecc0
-	0x9c480c46	0x2233038d	0x66d38df9	0xcb566912
-	0x63cffade	0x75811ca6	0x8dbfa4cc	0xee5fc07b
-	0x23329e49	0x39ee07e5	0x5de33ff1	0x601f8348
-	0xb60a8bc3	0x832d3660	0xd1bee11b	0x1a38d12c
-	0xaf00744f	0x21c2639b	0x0fd34252	0xcd63a9f1
-	0x60f34993	0xf8728afe	0x75f8bb5c	0x74a250ca
-	0xb9f51490	0x6ac643a6	0x4011a0e5	0x77288317
-	0x57f772b9	0x92c0715c	0xd5d0e030	0xde335025
-	0x669f6b14	0x55c74853	0xf3ac7cd5	0x38284e8c
-	0xb0fda481	0xf9b7f045	0x839293cc	0xdf91a0a0
-	0x18d20454	0xf73214fc	0x09577b9d	0xb5febd00
-	0xd9b96c88	0xb454ea2c	0x6204a932	0x736edf8a
-	0x9724f56e	0x3092f58d	0xac17cced	0x5ae87e39
-	0x28dd2a0d	0x3806d96f	0x5e7c8c68	0x72df4471
-	0x0207de38	0xf026ecac	0x13258e9a	0x34a8e8ce
-	0xdd7d7286	0x8d7553af	0x11ebac36	0xfb9965ff
-	0x9beda82d	0x1cd898cf	0x1b791830	0xe96ca8f0
-	0xa0d274d6	0xdd6fea3a	0x7537177f	0xdd93627c
-	0x60b64e47	0x10f30724	0x12489cf7	0x4587e1ac
-	0xe7835522	0x61d48d9d	0x6afd081d	0xafbbcf2c
-	0xe31d79cd	0x49ae4218	0x7c2c4a33	0x4fdf949d
-	0x52ccd576	0xef2c3d62	0xfd5b75db	0xe6a5c2e9
-	0x04fc9c6e	0x47fde414	0x8a87ebfa	0x850904e4
-	0x2f49b552	0xb5f186fd	0x772a4ba3	0x48d0be3c
-	0x846c7d78	0xc1c2a1d7	0xb9375f9d	0x302ed828
-	0xf79208f1	0x8fdc4f71	0xc749ed51	0x1cd0c28c
-	0xee5a5f7e	0x7f02b7ca	0xdc3b531f	0x99c0119d
-	0x428e5474	0x10515459	0x8d804d27	0xb7c00220
-	0x264c2695	0x7aa6e5af	0xef807715	0xa444f446
-	0xe51c7755	0xcd825b6c	0x39afa440	0x88638e46
-	0x4ea4366d	0xddfc9854	0x99696f2d	0x210592ea
-	0xf4763dcf	0x7358acdb	0xedfc8523	0xe46031c8
-	0xc9762414	0xa71a348b	0x084b6c82	0x9162e0d7
-	0xda6a5b8a	0x68ca14d5	0x6385741f	0xb103d4c2
-	0x44299ef8	0x9aba89fa	0x2c87dcfd	0x476865df
-	0x1189dbb2	0xdcd9d19c	0xac2bbd51	0xa71526f5
-	0x745222d7	0x4813ca98	0xcfa5802c	0x5d2b3907
-	0x8a17d1b8	0xea56f907	0x3ea58d71	0x933fa242
-	0x021f46a7	0xab8d4e86	0xfa4eb33e	0xaecbd5c3
-	0xb3258e74	0xaac9f193	0x415a5518	0x28b13031
-	0xbae39e53	0x1072fd5a	0x4e0fbf55	0xb02c5d77
-	0x5949c780	0xbecf72df	0x15e52c72	0x3ffeb165
-	0xa8e73d50	0xa52fd918	0x2b3c4d7c	0xa1e9e021
-	0xd8e91949	0x63bf63ed	0x8f2e150a	0x9cbceca9
-	0x33b10a97	0x4d2c69f7	0xf26371bf	0x0b5214ec
-	0x10eb7fca	0x1958b429	0x25f190be	0xafcfb396
-	0x7aec0c45	0xf9a0f163	0x9c966818	0x28f83619
-	0xe35c61d4	0x1ad8a656	0x576dba63	0x7aa44804
-	0xf941b7b8	0xc5faf3cc	0xdf1fd628	0xc009417b
-	0x366ea78d	0xd3cb7030	0xf3f12e97	0x5298cc89
-	0xbb43c8ef	0xd0a8ef96	0x564bced6	0xbcbd865c
-	0x5c80b1d7	0x131ccb04	0x7502d06e	0x465f5cb0
-	0x93320c4c	0x9df42986	0xbdb1fe26	0x48ae8bdd
-	0xaf44e912	0x6aa468a5	0x67ecbb05	0x30b7c0a5
-	0x3ad75711	0xa2d5f63c	0x30150058	0x4d748121
-	0x70804875	0xf46b6ea6	0xa3fcbb7b	0x1af6b4c4
-	0x48496de1	0xdb1a2321	0x758eb79a	0xf35f697f
-	0xb4ff9dfa	0x38ab5b31	0xc918f6f1	0xb3a259fb
-	0x3610afe7	0xdfcaaa0b	0x00c747dc	0x96c40b4a
-	0x5c815168	0x29198fee	0xc94eeea9	0x70432b55
-	0x5de7bbd4	0x0995652d	0x4b3e846c	0x7e4c9ca1
-	0x7c0e91e6	0x401a820e	0x3ca3429a	0xd3812f44
-	0x9cb6a5eb	0xf03ce395	0xefca548b	0x8943bc10
-	0x472b2108	0x82d4a386	0x1d0ef931	0x94cd70ef
-	0x2d00d619	0x40d36f80	0x238ccc47	0xe0856568
-	0x9f06ad8b	0x95a4052f	0x287a57fb	0x9e9f9891
-	0x62bc3a31	0x24c3c1f8	0xbabdc3c4	0xfa40629d
-	0xd16f1f33	0xa9f7600d	0xbcbdb2d9	0x214f24be
-	0x623ea3b0	0x8d650418	0xe86635b7	0xb834745f
-	0x20771340	0x3c69a0b2	0x8b7c84cc	0x740e475c
-	0xe5a540eb	0x9e216852	0x1383201e	0xfbf1f572
-	0x9680d736	0x3d7f8d69	0x615ea313	0x87bc1297
-	0xe552725c	0x9bfee104	0xf2e87d90	0xde9188b4
-	0x028d268b	0x51c75c60	0xed93377f	0xc380d9d9
-	0xe858bf8c	0x5d0b4a40	0x05a3171f	0x76ae3ec0
-	0xf86e3fe6	0xc3d78254	0x7cd640c5	0x6835dacb
-	0x983bd9a8	0x05d1e564	0xc5d5e9b3	0xf81c6560
-	0x8ecba474	0x071daa33	0xf5010276	0x5432ba59
-	0x10f2dbc1	0xbe892680	0x7e92d3d7	0x8d2f0113
-	0x37fa8034	0xb13058f4	0x44684553	0x2bd0e36a
-	0x67ea83ef	0x815e7115	0x3cd123af	0xd9aec852
-	0x67c61c95	0x861d068a	0x60c7797e	0xd9733b31
-	0x9ed29f37	0x1ccc8e08	0x34bcfa7f	0x1c66914d
-	0xc64dc834	0xad884c08	0x2b22b8de	0x53d6fd78
-	0x0355dcc8	0xfd363485	0x62370358	0x0dcb046d
-	0x22fe7d2f	0x5fdd1117	0xccd6d8d1	0xe97925a4
-	0x309aca3d	0x56c31fb9	0xe6f81e08	0x24fc0560
-	0xa78d459b	0x4940b35b	0x9a4a2fdb	0x203eafb8
-	0x91e5fcab	0xfb9be08e	0x9cb903ac	0x31598d89
-	0x4f41986c	0x77206f4e	0x61811c9d	0xff51d95b
-	0x2d7b4c66	0x84ceb768	0xfb135597	0x58087b13
-	0xa1681cc2	0x14009e31	0x778c3fec	0xe3faf2fb
-	0x5092b2c9	0x8919c362	0x34e2b174	0x7bb04f44
-	0x63c39b5e	0x8ef696ff	0x2e4c612d	0x77d390e2
-	0x5dc958a1	0x528bb31a	0x1cb07e7a	0xe37c9c53
-	0x002856d7	0x6a10b962	0x423a7b39	0xc6da9227
-	0x207800e9	0xe200c119	0x0e5af6f3	0xfb580459
-	0x71dc40a0	0x70434cd9	0x13f7f455	0xdf3fd7ca
-	0x37cbc698	0xf5a5808d	0xa7bfdf32	0x8a0774c7
-	0x75b67d50	0x5a6908c9	0x23611a6d	0x8b50c483
-	0xfe1e2eba	0x7ee1c732	0x2191e47f	0x9e63eb3a
-	0x379cd875	0x4df7258d	0x166a8aa8	0x1c94586a
-	0x2456c4d3	0x000185fa	0x7a196b46	0x914e789c
-	0xf562c939	0xb3bad5db	0xc2c19b89	0x8a621ffd
-	0x0c807ce0	0x701a938f	0x69234cdd	0x36a00f09
-	0x964c43f7	0xcf71cd85	0x5f504e16	0x446c6388
-	0x25742397	0xf1a375c8	0x6bcf822c	0x1b175fd7
-	0x0fe78e56	0xfe7817d6	0x66da0366	0x904e8327
-	0x5a0749fa	0xef3ede57	0xd0fa2ac8	0x89791771
-	0xa5cd616f	0xe9ef2860	0x9b533bc3	0x1d746f03
-	0xf4bb82b5	0xacae0438	0x840b3e34	0x30371a0d
-	0x8590acf3	0xeb4ff7e4	0x40437052	0xba847bf6
-	0x24059538	0x44daca63	0x23b32e28	0x091386e0
-	0xc480e66a	0xe4a839f5	0x34929bcc	0xb9051207
-	0xd21252f9	0xc6524769	0x8c422851	0x36280aad
-	0xbf00b1a1	0x4e36c85d	0x7949e8ef	0xf76be57e
-	0x373a0ab9	0x1b7555a0	0x0c2caf56	0xc9241f75
-	0xbe5b0ee8	0x5a486f75	0xfb2c050d	0x6aeda464
-	0x3fa744ee	0xf6e055a1	0x0a7324ab	0xfab58776
-	0x09baaf66	0x459ce186	0xc6eb1894	0x56a4ce4a
-	0x58ce1069	0xf4debf5e	0x04a145b9	0x1a246583
-	0x9b07fe23	0xd4d37068	0x7321e0bf	0x2dfe17f3
-	0x426dd8a7	0xc561a2d5	0x7f515a47	0xe57d37fa
-	0xa85f0aa5	0xffb78cd7	0xf30c4551	0x3572c02b
-	0x6f4a4cbd	0x7322ecc7	0x170a7b9a	0xa1e80d28
-	0x5a366af2	0x4f24a3a7	0xfefd29ca	0x0d7b02dc
-	0x1adde2e1	0x5c426cc5	0xb1e53b76	0x5dba2c5c
-	0x1458b6ca	0x73cea912	0x39626c25	0x7547e76d
-	0xfcddbb97	0xf03d59ee	0x3cfdab3d	0x309db86e
-	0x3de8df47	0x4a570e6d	0x09c9579a	0x19ac033e
-	0x0a7a9a86	0x3662d261	0x048fa67f	0x4aa4009e
-	0xc7660654	0x524d81f1	0x3157ec52	0x857d1f10
-	0x3770162e	0x3d1ff919	0x732d2b13	0x84187da0
-	0x95722d45	0x362cada5	0x5d67637f	0xdaae8465
-	0x9f5c0699	0xab9aba98	0x6f97d3fa	0xf9cc4120
-	0x0ca1872c	0x1a832c9e	0x7b74d6ae	0x98dca967
-	0x03eb7699	0x5fd02b54	0x962c6224	0xde1ab807
-	0x800af435	0x2458a4ca	0x717de910	0x31648afc
-	0x871527de	0x3cb93892	0x45237e37	0x446b1315
-	0xecd807e8	0x70f38e30	0x140dc60e	0xaef7b7c1
-	0xadec312e	0x94d45820	0xb8960073	0xe8dd5bac
-	0x7616ab11	0x0c3cc190	0x516003e3	0x323cdb39
-	0xd679f9f4	0xd7c179d2	0xdfbc5e24	0xaa1226df
-	0x3cd41b0e	0x88f436f0	0xbd5b6cb1	0xb78c69aa
-	0x982e0ca0	0x91f852a3	0xb331636a	0x28df67ee
-	0x81b029a1	0x9e7375e3	0x56e874c0	0x8b93a735
-	0xa47eaa4e	0x772ad825	0xfb83ba8b	0xc08db79a
-	0xcb7a34be	0x14214d72	0x7d6fa82e	0xe75c7002
-	0xa6290902	0x716d04c1	0xc75f0a97	0xb68e0912
-	0x08b5ef1b	0x507ecac3	0x2d740b08	0x43b6c7bf
-	0x3965675a	0xf56dc4fd	0x1ba44239	0x36753f70
-	0x0b2452fc	0xe36bafe9	0xfc3134c3	0x2ac78286
-	0x69ba53b8	0x225b9bd9	0xaf426f79	0x99bd2d3e
-	0x0bcb8e18	0x28c87047	0x2045b3b9	0x730ec870
-	0xe6558839	0x9ca3de82	0x263a41e7	0x1c8ea255
-	0x334eb3ad	0xc36d6793	0x66add8ee	0x652c8548
-	0x79dca1a8	0xc2526972	0xd10f03e2	0xdbae6f42
-	0xe223bf69	0x10082495	0x74ba4cf9	0xeb71ef5f
-	0xafae5d4e	0x7b3663e9	0x9339468c	0x31edca72
-	0x65a07876	0xf336fc1a	0xaa505397	0x011d5253
-	0x99b88ade	0xa688f0fa	0xedac589d	0xab4d8f45
-	0x0ff866a1	0x61280e9b	0x65c5a63f	0x8b372073
-	0x7a4c88df	0xc74f7959	0x19597c51	0x97c8a27f
-	0x33eb652a	0xffd40c86	0x57a2ca0c	0xaabc6cc8
-	0x54fd2280	0xd5b59006	0x2e00f009	0x72bd86c4
-	0x24936e04	0x877188de	0x91b60401	0xb949b337
-	0xdab93e69	0xdffeab2e	0xb3aa7c79	0xb8612f31
-	0xf0c53b58	0x8896833f	0xda35944a	0x1867027a
-	0xef6bfce9	0x8213f320	0xac477eb2	0x92368362
-	0x606cfdc4	0x27c98907	0x50673ac5	0xec48f5f4
-	0x39e879f8	0x80d050c8	0x9febddbe	0x5d797725
-	0x06d8b755	0x0319d93d	0x7eae3ce5	0x8963ed64
-	0xc91772c9	0x4e031095	0x2fd03d3e	0xe774ea89
-	0x7dbc97ab	0xe8d8f361	0x6e167fa1	0xd1520c5a
-	0xb3278325	0x8acaf913	0x6ea81dd4	0x9e3b2a97
-	0x0a5b8a09	0x84000db1	0x59a30fa9	0xf0b6868d
-	0xfb62b0ed	0x8953057f	0xdbbca3c0	0xc103b876
-	0x47420e14	0x1eb22bed	0x58c8f65e	0x3a689da6
-	0x8ed1a99c	0x869ddc49	0x60015d09	0x2264c797
-	0xdc10c6ac	0x7275327e	0x8d47d2ab	0x87a75624
-	0x3dd8fcb6	0x40e67a31	0x98114b1f	0x7e3a5976
-	0x1d9e62a6	0x988c0398	0x0c7c0d8d	0x0aad4954
-	0x3c40a234	0x7b752b7b	0x79f94813	0xa0b86dec
-	0xe3f646ac	0xa993f76a	0x6f9d1f99	0xe883dabf
-	0xb8ab1b2d	0x6766ac8d	0x6b9a793a	0x02f55fa5
-	0x351a96ad	0xd190f768	0x35667fe0	0x6a85c938
-	0x72444e33	0x5140a848	0xd3062250	0xe4ce902a
-	0x44e7d9d3	0x7c8d48fe	0x4d26a61d	0xbd013c4b
-	0x540d32bb	0x9152cafd	0x09840a30	0xd7a8663a
-	0xd5a3ca17	0xfd5dbe65	0x655b226f	0x7cb9debc
-	0x59d300dd	0x13737132	0xdf0d004f	0xe98bbd9e
-	0x5626fb54	0xb6d66fbd	0x273087a8	0x032969ea
-	0xbd69c191	0x010cdfff	0xb2a9cea5	0xb8778e4c
-	0x8f0dd084	0xc75b4ce6	0x9c027c6f	0x36c58105
-	0xac424eb8	0xa15d2883	0x9e73b7b8	0x54e9aade
-	0xb9500a5a	0x97505e35	0x4c59b36c	0xb3ad1302
-	0x31e21ed1	0x78bcd74e	0x2d9fc122	0x49bae35e
-	0x5c8f01c0	0x8d29829c	0x0c672566	0x37938db5
-	0x4959e71f	0x0d2365bf	0xaab666b9	0x52b2cffc
-	0x200ee1f5	0x5dbb262b	0x9aae28df	0x3223780a
-	0xb65218cd	0x633b797d	0x93f42423	0x3268b3ae
-	0x141e506e	0xb1ed94b2	0x497b7973	0x9f2db9f6
-	0x5260bf9d	0xb30e4310	0x4a3539ec	0x275d2ae2
-	0xff43e500	0x645e30e5	0xf1527598	0xb76ec4cf
-	0x88fc44e9	0xde68932c	0xe61aff6b	0x19d042b6
-	0x11981ff8	0xb0d595d9	0x52764f82	0x7e0ca214
-	0x8cc51237	0x581f2a1a	0x482420b3	0xd47ff971
-	0xcff78344	0xc019eca7	0x3146ab02	0x107a3ee4
-	0x16dc120d	0x33a239ec	0x0ea84236	0xebc7a1f4
-	0xd1f2fa2a	0x9464c008	0x2b76a4fd	0x9b4acb99
-	0x00f6a92a	0xd68b8d15	0x25e1e58d	0xe1fe3cd1
-	0x6fbce2cd	0xf78be2dd	0x09b9c08d	0x6b32d210
-	0xd06e7c95	0xd62f47f4	0x92c717ca	0x44fe3d2d
-	0xaa13cc08	0x3d411f94	0xc2eba262	0x7521c9e4
-	0x77d6cdc7	0x22d76158	0xca2efacf	0x3e51004c
-	0xef9a82d6	0x1508d20c	0x923f18ff	0x3eaa88e6
-	0xf2f32bc7	0xe74b8483	0x82529884	0x58b38ad8
-	0xdd9f2a5f	0xdf54adc3	0xd4497667	0x789c000b
-	0x935d1743	0xa52d5f1a	0x4e27adf6	0x5c3334af
-	0x6cf71ba0	0x501f8353	0x031fd6cd	0x4831ec4f
-	0x08c847db	0x6a6e0657	0x0bd803d4	0xd7c48cfe
-	0x94b7e25f	0xc6516ebe	0x1001c08a	0x0e165da9
-	0x4e39605f	0xe3f3637a	0x013daae9	0x217168b0
-	0x6013ab5f	0xd5b7eb97	0x8ce6b6ef	0xc4259f29
-	0x470e90a9	0x7a254ff5	0x8dcbf841	0xa2541a7f
-	0x4880c5ea	0x28c750ea	0x043a0200	0xbeb9653c
-	0x46e354d1	0x64f7104e	0x05a64bf3	0x7db42752
-	0xbbd38c7b	0xca7da1d9	0x916c7ebf	0x1df5e3e1
-	0xef0897f5	0xd0456a5c	0x629b50a3	0x8caefdc3
-	0xddbf8b94	0xf6e6b341	0xd8ce3e02	0x27c96419
-	0xb2659ab5	0xe8d576df	0x9f136353	0x6f5230f5
-	0x68417adc	0x39b65378	0x4b742f21	0x96d071b1
-	0xeb046da9	0x245ecb46	0xc17eeec3	0xd7c56615
-	0x07df9b8c	0x647ee4f4	0xf15f7e7b	0x825b87eb
-	0xdc67dd20	0x43c38867	0x977868ca	0x3a299ef2
-	0xa75073f7	0x2dcd59e6	0xc6c78c75	0x63a00767
-	0x74dfba2d	0x7880c7da	0x83f72bc6	0xa9750166
-	0x716b3abe	0xc949a1ea	0x7e5fc036	0x574ee475
-	0x39c3cae9	0x8c1dacdb	0x640fcc41	0xc69437e8
-	0x5d33a950	0xa28e483a	0x4031cf9b	0x0007e3be
-	0x6e3f277f	0xe25d3025	0xdcbc4a0a	0x7451a537
-	0xb372169f	0x21ff0e91	0x1978aa74	0x6471624e
-	0x01a03f20	0xeb391a3c	0x70d18ad5	0x47c9ddcf
-	0xd9415b2f	0xd9ea29ce	0xffa0677e	0xeff7a04d
-	0x1d384ff4	0x66195704	0x22736810	0xad754f27
-	0x782ae9bb	0xffed05b6	0x5ae3f21d	0x5eb2c577
-	0x0101cf91	0xed0322ad	0x56ac50c8	0xc513b1c6
-	0x4f62ba8b	0xbaffd6b6	0x6649baa2	0x8702464e
-	0x78947007	0xd6e97d6e	0xde7c6abf	0x2bdee498
-	0xcee1db1a	0xb98149de	0x47f32f5c	0xc6c354fc
-	0x6e148fad	0xb343cf2f	0xeac6a9f0	0x33dd1560
-	0x923403bb	0x87d6e292	0x0b1cf653	0xe8b76402
-	0x5f21a955	0x236dec28	0x214663fd	0x1917539e
-	0x3f11ce80	0x1bb35a2c	0x38a358f1	0x15f67224
-	0xc65394f9	0x63cd4887	0xe8e73d2b	0x51b6204a
-	0x8eeae8f5	0x6e071c8f	0x55c23dca	0x4862eaee
-	0x0afa0037	0xc98446f3	0x09181a1c	0x41e46e02
-	0xcf13d6b9	0x85907776	0x30116b18	0x27b8c7b1
-	0xd153a5ce	0xc95c90b2	0x34392718	0x8103dbe4
-	0xe012a7be	0x6aeb8c6a	0x5bbaddbe	0x221eab21
-	0xaf769239	0x2621a689	0xe8c41061	0x5890f76b
-	0x2c4dadd4	0x2ad2e669	0x394209b5	0xb272b2ef
-	0x560031cb	0x4ab7be9c	0xcc5e92e4	0xc0de0667
-	0x7a39cf63	0x03482c6e	0xd653de11	0xe14466e1
-	0xf2dbaf25	0xc34d1c0c	0x03eeb3e3	0x8260874f
-	0xf6e2ef37	0x13626fba	0x15b7efe4	0x069cd153
-	0xbf631788	0x797668a9	0x724d831a	0x0ceeb589
-	0x9559cd31	0xb995d2d2	0x7564c4ef	0xfc45a3dc
-	0x1cd999e3	0xbe090229	0xab4f9383	0x879156a0
-	0x06e1d37b	0x3796487a	0xaf1e3884	0x1f9a59ef
-	0x6c2d8a7b	0x0a8a5ffc	0x4cd60f03	0xa60bfc63
-	0xf67c6872	0xf19b75cf	0x041cc864	0xc563566f
-	0x58ae88a0	0x3747b0c1	0x64cd86fa	0xed185c5a
-	0xb71533c9	0xf15672fa	0x2722d209	0xb71ec7d7
-	0x3143a8a5	0x61c18934	0x3a899ec5	0x4274f336
-	0xea7c52a9	0x9193cd11	0x44c471e7	0x57fff360
-	0x53923783	0x76d57ce6	0xbff32513	0x4dbe0d39
-	0xb9f80483	0x62ce4d25	0x5941e9fb	0x7dfedfe1
-	0xa33f9130	0x336e6539	0x1de31e79	0xb6855a41
-	0x4db2db67	0x02a9f1ed	0x019bcf20	0x53ad0ce3
-	0x4d049f95	0xa9de2c6f	0xa26f6997	0x28eafacb
-	0xa5220548	0xb4675e1b	0xe776ee88	0xc93e6c37
-	0x7868630d	0x1690625e	0x6eba0fd4	0x78f598ff
-	0x113fa1b7	0xcb025590	0x2ee34123	0x92241df5
-	0x6edbf0b2	0x3bc2e0a7	0x710ce59f	0x656f0eb7
-	0xa598424e	0xeca53268	0xb6a44542	0x5bf6674f
-	0xad483960	0x35290b93	0xfba74c81	0x78141ea2
-	0xd6baf9e7	0x8e5a08e6	0x4910c5b0	0x7b140d21
-	0x1958c79e	0x0dbed125	0xcfbe41dc	0x089fc4ab
-	0xbf014fa7	0xff961610	0x7a2ae6c3	0x560d3a9c
-	0x2cd77620	0x3a7c15cb	0x9464d8f1	0x249a93ff
-	0x96fe6c56	0x7231a31c	0x4bcdadd7	0x62edd9f4
-	0x8ad1916c	0x3a5fbc8d	0x2a2ccd7a	0x558980b1
-	0xb0137cfa	0x3cae6929	0x587c349c	0xbcfee701
-	0xbddd49df	0xa0da6dbe	0x4cb03dac	0x5f84ba2d
-	0x7fb3063c	0x66de2150	0xbf7dbcf2	0x1c0892aa
-	0x4be8b0ae	0x5d9845ab	0xa21455af	0xc42f2e68
-	0x9b6f438f	0x5eaf4941	0xabbf9079	0x94984a47
-	0x542bdea4	0x34cf3d67	0x854010a4	0xf39a9b19
-	0xd25ffb6a	0x04364e75	0x0af97ef8	0xe10e3620
-	0x2184d002	0x0c0ca683	0xc19963c6	0x4c428d15
-	0x47ae4151	0xd11ea57c	0x437a9ed6	0x50a6b8a2
-	0x141b16e9	0xeb4ae873	0xb51180fa	0xe3dc318d
-	0x7744a06f	0x64d297d2	0x845fac66	0x5854d172
-	0xc14dbe9d	0xccba053f	0x4620a715	0x405d728f
-	0x28b86cec	0xcba09cdc	0x92823f94	0xeae2664c
-	0x48eda6ae	0x4b60f5f6	0x1772f309	0x8af285bf
-	0x9c3ae474	0x13149ebf	0x2bc835c2	0xafcaa560
-	0xc11b6f91	0x94861d9a	0x089c0d82	0x1e04d66d
-	0xf0e497fb	0x6b2d8b6a	0x9d7f0cae	0x4a93ba71
-	0x1c006123	0xed4b5f75	0x76e7826d	0x4f884ba9
-	0xbba28011	0x1e275278	0xfa72461d	0x7e70e215
-	0x1427ba3c	0x467e4f3c	0x781c5f92	0x357b7951
-	0x9de2cce4	0x524a0de6	0x12e15f95	0x7b64fae0
-	0xf27e93cf	0xc6f48158	0x9b71dbd6	0x081dc1b3
-	0x47c9c2c8	0xf110add7	0x7881b556	0x0404bf1c
-	0x58e7d936	0x04442173	0xe1e7f0cc	0x128ce897
-	0x169c0a11	0xf30b5575	0xf2ac0bab	0x91515620
-	0xe8b809b0	0x2a73d5a0	0x9ed32dae	0xcf943a47
-	0xfc157bf9	0x1a53054d	0xf0657e2f	0xf39f6ea7
-	0x92a5834a	0xcdca0c13	0x40a7b40e	0xba0e0cdd
-	0x72f595c3	0x6b7eeaf3	0x4d0fd8ed	0x9a856082
-	0xd75402c8	0xe0f8d3b9	0xee57a2a5	0xe1ccf4a7
-	0xa4fc4fa6	0x9f2407c7	0x75f94c0e	0xbf2361de
-	0x2d3b4782	0x72c35e50	0xb97f7d4e	0xbc880223
-	0xb0b24073	0x08931201	0x40e0d18b	0x559db40c
-	0x6216a921	0x031a379c	0x29bff1ac	0x1c522c12
-	0x583bfe94	0x2519ba2a	0xd691d08e	0x905dc62f
-	0x43b421b0	0xd45caaa0	0x5f099da2	0x012fc4a5
-	0x509712b3	0x67e5d441	0xc843de50	0x7e1c756f
-	0x91368900	0xc6ec0dd4	0xa41e838f	0x58eabda5
-	0xd6ad78a9	0xa037b655	0x8af4e767	0xa9b95900
-	0xdcf1780e	0x64e28d82	0x215ad981	0x292dfcc3
-	0x708d8557	0x0a507562	0x486022ad	0x8165bc7e
-	0xabffce1d	0x78fbe480	0x77b916f6	0x88f8167d
-	0xae8b8edb	0x62698ab6	0xdbc6bbbd	0x001819a6
-	0x8c096fb3	0x40a121e9	0x7b96a718	0xf6d256ed
-	0xe5c0a484	0xa09bd764	0x6552b5a2	0x1847ae3f
-	0x0669a650	0xccabc209	0x85246d20	0x61158f3c
-	0x379d8086	0x02135988	0x1eccc6db	0xf8f38c67
-	0x8e1b0f3d	0x0f6e87e5	0x936bbb84	0xe04839eb
-	0xe26b3e5c	0x3f35ffda	0x4920e752	0x014c876a
-	0x25189061	0xbe2bc4ec	0xbb2ca0f2	0xe2c1c9b0
-	0x747df643	0x26da8dbd	0xdacc3c8a	0x7d93b22a
-	0x922d9a0a	0xf82d65b6	0xd56e5f35	0x7aea7534
-	0xf1808648	0xdfa7ec9a	0xff00f8c6	0x69091da7
-	0xbb478c83	0x64e24ae6	0xf2371faf	0xcff5732a
-	0x4da88e73	0x9c8494df	0x4c0da767	0x3e22bd67
-	0x059298eb	0x9d7611ce	0x74b4a198	0xbcbe440c
-	0xe2bb1a9f	0x0ba3e5f7	0x65a5cf9c	0x8b24b6f4
-	0x7784ca5c	0x24ffc234	0xece71bbd	0x36f8e876
-	0x1b55d68b	0x2b9163a5	0xaf8be424	0x958eeaef
-	0x5d711c41	0x66d11cbe	0xfce42868	0x4a3c819c
-	0xf66d295c	0x629402f7	0x64b2ee3d	0xc0b74538
-	0xe93a735d	0x3b9e807f	0xd1d0d7c8	0x69588f34
-	0xae92b6fe	0xf5508d03	0x45b6ccd6	0xf85a18c6
-	0xe1a28a53	0x438f9a35	0xf4fe84dd	0xe3f95791
-	0x16860340	0xefe72aee	0xb13575c6	0x3d730481
-	0x3cf2a43e	0xa6ed239e	0xd7529176	0x8ad63f3f
-	0x5efe8f4d	0xe9cad7df	0x44fefef4	0xc7198f50
-	0x85aabf5c	0x15c175c2	0x26f7a0cf	0xf06782f0
-	0x4dfadfa7	0xbc57a087	0x21406f0b	0x692a8f18
-	0xd17a358b	0x19d1b2a6	0x6c35022e	0x87d8c987
-	0xe7f2d06c	0x91c4daa6	0x4a132822	0x1e864671
-	0x5cbf0c4d	0x6a34f073	0x1c87a8e5	0xb38f1717
-	0x1cac430b	0xf733ee6e	0xdf73201f	0x71026328
-	0xee976531	0x661c9d28	0xdeefcd7f	0xdefb4607
-	0xfca9ef3a	0x3e1b9b38	0xd204c892	0x6b059f5f
-	0xd5b8665f	0x4eec24fd	0x09b21b40	0x364c708c
-	0xebe0d543	0xc3d64eed	0x8facb895	0x8f415f31
-	0x3dd25b0b	0x95f4072e	0x85e6f4c1	0x3345e2a5
-	0xa56e8dcf	0x3ed8df67	0xa8194a81	0xafe613c7
-	0x384b25b9	0xe7661836	0x5ad6476d	0xeb0ae982
-	0x19afdf2f	0x4efb8658	0xff07e358	0x96c469d2
-	0xf3030add	0xf5bf5b51	0xba03b24c	0xcb77143f
-	0x134fba20	0xa126558a	0x193cd220	0x48f43727
-	0x156f2b18	0x4e599917	0xc3ac4eac	0xcc460648
-	0x67974a2a	0xe2917a7a	0x02998a74	0x470c60d1
-	0xbacbc868	0xfef38d84	0x3e4597a9	0xa1723ab7
-	0x8ffed7b2	0xe489b151	0x34b982fa	0xf67bf8ce
-	0x043cbb33	0xe3927c98	0x3c8fb221	0xbff0644a
-	0x886d333c	0x1f4cd6b7	0xe9b744f0	0x443ef364
-	0x04847d65	0xf3c2ba04	0x60a8e656	0xab4dca06
-	0x620dbf22	0x5b0221e5	0x877973ab	0x128b5a6a
-	0x4696b5d7	0x8f034e85	0x18796215	0x8579ec7c
-	0xf8917eae	0xa98bffce	0xfc67e9de	0xa897445e
-	0x2f115777	0x990bfb90	0x1de53f71	0xfa2e5c1f
-	0x24a5b882	0x0f871a5b	0xe7fc33a0	0x6927a106
-	0xb210bc90	0x2ef851de	0x09629147	0x2553882d
-	0x77393353	0xeacf977e	0x470198f7	0xb7564a05
-	0x4d575fb4	0x1d980371	0x0feeebba	0x26ba3c12
-	0x17b21567	0xfb664d1d	0xcee1a603	0xa8881580
-	0x8a47e853	0x6511027f	0x734f6fd7	0x2977b345
-	0x7465e47c	0x0e3c4c8c	0x3185ac04	0x2450ea5d
-	0xa6e97dba	0xf52b2f4b	0x328ac24f	0x5a507ad2
-	0xac05d4f7	0xca332e1e	0x44b6cdd5	0xe22b049b
-	0x55b885d1	0x71144ba1	0xf57284d9	0x76cb0900
-	0x8266cfae	0x82bb0271	0xfe547080	0x53e4dac9
-	0x0546dcb9	0xa09a8de0	0xd55d15a9	0x7a3a96ad
-	0xd23c33ed	0x7a8fa769	0xa0542b10	0xdaf92f2c
-	0xd6433b0e	0xad7cf7b9	0x72c54814	0x38ff5c07
-	0xddee72d7	0x6c29582d	0xa1574da8	0x418272ea
-	0x0a9e21f3	0xa34bb5ea	0x1e78630b	0x9238d5d2
-	0x7cfa682f	0x6e8e841b	0xa4b3d17d	0x70b6d075
-	0x704db3f8	0x76aa7d19	0x1cd3e85b	0x2ae7fa63
-	0x5ff0dad0	0xdd92c129	0xce7d884a	0xa7ba03ab
-	0x3b366560	0xfeaf75c5	0xd08856c3	0x01ffbced
-	0x089aa8a3	0x2e4b36f1	0x03955648	0x882468ba
-	0x534abc87	0x28c08402	0xa7512f6a	0x1fab044e
-	0x6595e159	0x92fdef27	0xa0b6093a	0x5fdb5f3e
-	0xd0facb7d	0x512a8b83	0xd7f31adc	0x82166318
-	0xf9ad7f02	0x9120b349	0xab744947	0x2787d6bf
-	0x489e3546	0x02a7ce3b	0xd3812409	0x819a092d
-	0x94a48db8	0x49d8dff3	0xdd4e9b5f	0x330d32d0
-	0x203cad0d	0xace20075	0xfd019f42	0x1cc56871
-	0xe53e452b	0x51e7c9e6	0x1d6732c7	0x03694ca7
-	0x900ecdb4	0x3251d119	0x2c4a0669	0x3243bb5e
-	0xb434326f	0xd6eb26b8	0x8ceb7328	0xff30d7e3
-	0x861fa43d	0x15386557	0x3fa11d24	0x86590299
-	0xc3cbd319	0x8d1031a5	0x80db9f63	0x9d957321
-	0xdec927f4	0x1468a2a1	0xff1b8842	0x4c403eed
-	0x62140459	0x912ddd25	0x36252404	0x49052d26
-	0x22205558	0x53773ca0	0x3428d400	0x51002834
-	0x6b5baa18	0x838bcf14	0x30d09ce0	0xf1c456bd
-	0xb1fc90c1	0x525dbb0f	0x64a9105e	0xe0a5cc89
-	0x293f2441	0x335b1c7d	0x55842eff	0x6c7f60dc
-	0x903fd793	0x868589ef	0x50a596a6	0x337c6988
-	0xb7a670a9	0xa46b1a8d	0xdf8c013c	0x3dcdfd02
-	0x01075847	0x06c3a7e6	0xc8f22594	0xfcd94f04
-	0x8b6ddbbb	0x5a138f6a	0xf43d2cca	0xcf4df232
-	0x088cddf4	0x9adce26d	0xee803f2c	0xedf042d5
-	0x7d738c39	0x8f02cc34	0x3f964043	0xbfae17d7
-	0x5f2dd670	0x177a9f36	0xf0e1dc28	0x07082ed9
-	0x90534419	0xf03db66a	0xb8ccbbbf	0x739d2ae4
-	0x3509b32d	0xf0105125	0x2d603572	0xbd1a6b64
-	0x50959fe9	0x26100668	0x758e250c	0x9b372d1b
-	0x0f1e1bde	0xd53edd46	0x0187d6e6	0xd0158da6
-	0x05dd0922	0x3fc0a182	0xd7f70ebd	0xeeda22e1
-	0x1c7f99ad	0x9b39bee9	0xf101d67c	0x1ffea21d
-	0x5494b799	0x787a77ca	0xe8908c34	0xdd00d1db
-	0x25e21bcc	0x30bf0b70	0xd8cd0350	0x96f2d414
-	0xa9a4cb6d	0xa3f3c207	0x2db5c7bf	0x88e8837b
-	0xb157189a	0xb9fb869e	0x48c2a7b3	0xf5e0c692
-	0xf9103c12	0x6c590e9a	0x7e0aac34	0x97392b87
-	0x8e6c201b	0xc6d68ddb	0xb5fbaf0a	0x1f8e411f
-	0x6355e9d9	0x05fcca55	0x9b0250dc	0xec9c5d7d
-	0x668075bd	0xb93078f1	0xcefa1755	0x216c5e0c
-	0xa83ae6b5	0x748bff79	0xfee9e797	0xc6acb230
-	0x1243bc06	0xfee350e0	0x3ee5f8e0	0x0508fb60
-	0x87d9d24d	0x0b54ac94	0xfc37c8fc	0xe9958f2f
-	0x3a927f73	0x04933b6a	0xa195a6dd	0xda96dca3
-	0x9c1799c4	0xd055fc63	0x05deebbd	0x2b5400fb
-	0xf157f110	0x80b1e79a	0xd7f1e4b7	0x5a1fab0d
-	0xbaaa81c3	0xa42489e8	0x594a791a	0x29f18382
-	0xe86f0358	0x5aa5f4b0	0xa682993b	0xedbfc5b7
-	0xf1eac55d	0x9b1716bc	0x907d9d1e	0xb2205254
-	0x4fbba0f3	0xacea63a4	0xc518d83b	0x8449fef8
-	0x80b4f69b	0x95dc7429	0x16c22c9b	0x6e116239
-	0x4c4bfd11	0x56f159fa	0x60cbb0a5	0xa2f4721f
-	0xa829cf9b	0x5ddbb3af	0x2db824cf	0xe82f3fd1
-	0xe5dcb2db	0x185fe7af	0x0775003d	0x38669aba
-	0x7b540eea	0x94ce3d10	0xba77f357	0x63507853
-	0xb50ebb0c	0xb614739b	0xea3a3c47	0xf2b6176a
-	0xf805b28d	0xdd0819b7	0x9f4b2799	0x18bdadb8
-	0x7d58d588	0xc4f0994a	0xef834870	0xef2d6ce4
-	0x97a36a52	0xb6e581e6	0xddd9aa9b	0x6437d4e8
-	0x43f74dc5	0x8cbbd744	0xf394a2a0	0x4a1e7f75
-	0x395bd36f	0x27a8f9e9	0xed62f4a5	0x7c2f0484
-	0xf394f837	0x5f69d50e	0x86ef57af	0x7af052f0
-	0x85dee180	0x125f56fa	0x87291494	0x141931ac
-	0xabca9ae0	0xbc1e4e4d	0x541e2edf	0xa3551bb4
-	0xed2766fd	0xf6e778c2	0x3a82644f	0x67c47659
-	0xb81b826c	0xb11603ee	0xba6cc507	0x691fdb74
-	0x06507f6e	0x64ef2a0f	0xebd9b51d	0xee620487
-	0x82991d7c	0x1493fed5	0x08af819e	0x7066de45
-	0xdeee1600	0xde12b903	0xe572ced5	0x81b897be
-	0x458d0db8	0xc9970232	0x7402dd05	0x44e1c70c
-	0x1619441f	0x9ea0c392	0x1d13c3dc	0x34737cbb
-	0xe1d726e1	0xbe7d749d	0x304892a5	0x71c7bb33
-	0x608bb696	0xd334cfd7	0x862e360e	0x868757ad
-	0xb7d8aa70	0x81031f5e	0xdb64b80c	0x954ff4c1
-	0x5c66d432	0x08c77a67	0xd5e298af	0xb6074be1
-	0xd687a163	0xac2fd525	0x14e6ab5a	0x6ca4232d
-	0x8a921092	0x0a19e936	0xd4464ee4	0x0da28777
-	0x6b6d4131	0x975111bc	0x3f26afae	0x5a6faf38
-	0x867d7956	0x554aa8be	0xf9898211	0x3afcde65
-	0x493dac6c	0x61d901b2	0xbaf3e9fe	0x2a3758fa
-	0xc2ad3ee4	0x97d13dad	0xe84b02f9	0xaaf5ca63
-	0x41a94864	0x6d7b71be	0xd843e866	0x83c3193b
-	0x972d4bbf	0x55c3a234	0x0d03b540	0x53396a64
-	0x98b5c0f3	0x36708484	0x38363c7a	0x0076dbf8
-	0x5edbd01a	0xf6e835d6	0xccb95e4f	0x2bd2907e
-	0x210f9312	0xf4ec9221	0x343697d6	0x3913cd41
-	0xb02ced20	0xba991ee5	0x09c7893c	0x749da3c0
-	0x46e5ad3b	0x871b685d	0x02358659	0xca76706d
-	0xe61524a2	0xf46ac4a9	0x4f6c9e19	0x68a86d0c
-	0x9d16bc4f	0xa9157a1f	0x830993b8	0x3738896c
-	0x7c821db5	0x02de8542	0xb17e3767	0x455a0b40
-	0x19b707eb	0xed81e63d	0x568e1e36	0xbf5cee00
-	0xaa12957f	0x67f65ecd	0xb940789c	0x0ab3bab8
-	0xd7e3a789	0x777b64ba	0x4e00d3be	0x46887a34
-	0x08f0127f	0xf5027e8f	0x9cdb4671	0xb7a7eac4
-	0x9be5cfb5	0xb1f57dbd	0xbce97b11	0x41525f56
-	0x5e847d16	0xf71585b3	0x1ce5047b	0x1bc2fa00
-	0x860aa4ca	0xf97ee77d	0xe7843ee6	0xf07bd865
-	0xfa059452	0x58a59ce9	0x24f03b1b	0xd18a52c2
-	0x180426ab	0x2ced0003	0x399234cd	0xe43f91e9
-	0xa0516a92	0x8088d598	0xc3a41365	0xd1f044ef
-	0xfb3808f9	0x1770e594	0xf96c4185	0xc6b67b9f
-	0x5c01c703	0x65c6ef8d	0xd49310f3	0x0f962bd1
-	0xfb3c96f1	0x4d501516	0xa09beeb5	0xce9df639
-	0xf792c71f	0x392b420d	0xc03c9099	0xcab5dc42
-	0xbdfea308	0x84c80c32	0xcd66ec3f	0x68932191
-	0x62b69b08	0xcacb4a8b	0x0415feff	0x84673edf
-	0xe61b5ff3	0x6107a18e	0x6a7a206b	0xed64aa34
-	0x1bbaef36	0x22a3f0fa	0xb0945c72	0xd1a7f7f8
-	0x65fd1b29	0xa34d99a9	0xb6f2ea53	0x055ab055
-	0x433c3eb2	0xe591d68b	0xcabb8a71	0xfb055c2e
-	0x37e1efec	0x558fd45e	0xa5358766	0xe0c450f3
-	0x78ed3061	0x8713e084	0x4b0d2ec4	0x24feb10e
-	0x6689fc4e	0x0c83f1c9	0x7490df57	0x00d618bc
-	0x2c510caa	0xc5e2838a	0xcfae6669	0xdc2fa4b0
-	0xa4569e3e	0xcee095c4	0xcb5f42ee	0xdc11393f
-	0x69f1c5aa	0xa495fae6	0x64c53ea4	0x4477aeb8
-	0x2ff43cef	0x660aa186	0x5dec9e67	0xa59f6aab
-	0x51504061	0x28279b5a	0x4e245278	0xdbf53c73
-	0x01a77ff9	0x7d771730	0xa8d19fc6	0xce3697dd
-	0xecc405d8	0x22f1872a	0x683afa3f	0x725f7e03
-	0x14c7acb2	0x845efb20	0xf3e03095	0x8c9a7d04
-	0xa9f115d3	0xb93fa8ef	0xd2e78a32	0x91e3cc61
-	0x805d48de	0xc9fcc672	0x225d36f0	0xb32e7627
-	0x11b7a585	0xa7321798	0x9b40640f	0x0c3a6b7f
-	0x3337c762	0xbbe54bb3	0xc8316a84	0x0d487a67
-	0xa6d6b86b	0xd1fb2b92	0x15805dfe	0x5cd49b21
-	0x9855f2c2	0x74e2a195	0xbdc0729f	0x29f680a9
-	0x092f47ad	0x0e7091d1	0x6e7d2020	0x0a7b5d47
-	0xc9c4065b	0xc4cacd97	0xcd7b4071	0x7986cc7a
-	0xb1c29ef5	0x47ced57d	0xc08a8b40	0x12102685
-	0x685caae1	0x1ebf3635	0xdfe6af15	0x8a0496f4
-	0xb9c07f19	0x1f62a68f	0x0133de0a	0x993017d9
-	0xd0553b5c	0x0c8f1311	0x7d979028	0x6001db26
-	0x1caf7ffd	0x76ced0cf	0xc33d3f23	0x9fc27423
-	0x235fc137	0xf85a079b	0x78174474	0x1d15b725
-	0x20162abf	0x62e0712d	0xa03f9cf0	0x0f4ff140
-	0xaa389d0d	0xd58e1171	0x8f5d21f4	0x3ad5b3c4
-	0x03003b51	0x49b29d4f	0xa3d82796	0x9c7f3391
-	0xe34de3a8	0xab75e6f4	0x3f06b52d	0xb8092f83
-	0x01f14341	0x929a3b8a	0xa630aa03	0x4b7e055e
-	0x90b06e58	0xeaf2ad79	0xe8c5b756	0xf46f44e3
-	0x6693ff09	0x499d2790	0xd0d81c69	0x72d7a2bd
-	0x794d242b	0x9be19084	0xddd51a72	0xf4f60698
-	0xd1747d6a	0x24dc87dd	0x78ba7af6	0x548b43d0
-	0xa2b03ee8	0x100ef53b	0xe836488a	0xf4b9a443
-	0x41d61bdc	0xee4bedb1	0x8f0ec0b0	0xc0125983
-	0xaa919a7f	0x6677db37	0x78e7d366	0xc7bef834
-	0x967a54e7	0x5f78951a	0xc0fddf1f	0xbd5cf29a
-	0x3fa13be8	0xca67a695	0xc13e8c23	0xaff54342
-	0x94f4bc22	0x85512c06	0x1439cd71	0x7d13b7b5
-	0x76f8bd59	0xffe02871	0xbd88ccb1	0x2597d721
-	0x80a52e2e	0x1f696120	0x689e73aa	0x7d085fa0
-	0x0e183650	0xe041d3fb	0x5a340dd0	0x26a6c10c
-	0xe6fef6d0	0xdb18b3b8	0x2fc6df63	0xfa695c57
-	0xfb3e6a3a	0x64fb412f	0xc1cf1e32	0x6edd945f
-	0xcee44d66	0xdfb2ec8c	0x5eb84515	0x177f031b
-	0x56a9db8a	0x0e247577	0x99004862	0xa5805854
-	0x04b1afc9	0x9c649998	0x908a1424	0xb595099b
-	0xb91fb0ce	0x8c4bdd8a	0x78de806e	0x65ff3cba
-	0xb66aeda0	0xe22d3592	0x7c0cdebf	0xc15c0853
-	0x80f31d27	0x84dfc7ed	0xc96a5992	0x939b3d6c
-	0xf0ffac53	0xe4be269e	0x4d56d528	0xb0477318
-	0x40a4b528	0xd938f1bb	0x2b25a6c2	0xc93b3c9f
-	0x179c9571	0x999c2e91	0xe7280616	0xee6e0481
-	0xc30eae2a	0x7d6f0458	0x0b7a52ff	0xd44e0a23
-	0x81d661ee	0x9d0f857b	0xe7fa9d18	0xd499cb85
-	0x4e27e30a	0xd51d1f9a	0x14195d32	0xccca7d6e
-	0xc1703a6e	0x15664170	0x7f51c821	0xf1363619
-	0x37dc27f5	0x6aea6223	0xd574e44c	0x4b683223
-	0x4135ad1a	0x7694390a	0x0bf4bddf	0x9522f11b
-	0xc20797be	0x45fb151e	0x96f2a952	0xedfd5f2c
-	0xdfbcac7f	0x58f5dba6	0x68204d0d	0x52eeb34a
-	0x8313fd8b	0xda2f1243	0x195a1479	0x19bb2970
-	0x1c2131e5	0x6841c28c	0x1ec33cfd	0xd3e489de
-	0xd9b70b18	0x81503d32	0x9642a53e	0x02470015
-	0xb8d1087f	0x4b629e77	0xd7ec9ee0	0x795ffd91
-	0xcfa71aeb	0x4bae649a	0x7f768123	0x69f501d5
-	0x56c19a0c	0x4bfaac57	0x90ea664a	0x4d428e1a
-	0xaee71c90	0x198fc316	0x549f5572	0x07a22e58
-	0xe8f444e3	0xedc7fc23	0xe96c1595	0xc4bdad06
-	0x751a3df5	0x3bc4fba4	0x58cd19b3	0x3665000a
-	0xe4371d96	0x6c50d4e6	0x5d1d6a57	0xf130eabf
-	0x48fd82ad	0x42a8bee8	0x71f89c32	0x95fba6dc
-	0x9150b601	0x72c361b0	0x71a3c317	0x149614f9
-	0x224e67fa	0xf6a3fea9	0x5461cefa	0x367bc566
-	0x2226ee83	0xaa13e83f	0x8d7dc705	0x417c7afd
-	0x8a0f2e17	0xbb4003df	0xd1c27124	0xaaaede8d
-	0xd4ed5bcd	0xd0102aa8	0x3b519bfa	0xb82d6932
-	0x50b8f966	0xec685a1d	0xffb18b64	0x538955b2
-	0xac4b6cf1	0x0a86d32f	0x34e4cc05	0x02adcf17
-	0x7c80379f	0xcfb5bcb5	0x842190e7	0x8348cd1f
-	0xabf77742	0x3332866f	0xa56fb2e6	0x6c1fec47
-	0xf2fbb22c	0x7230d805	0xed17d8f5	0x3426e157
-	0x1d045cb2	0x6c1e349f	0x3a6116ca	0x4baf0bdb
-	0xab68daad	0xc4867466	0x7bb15fd9	0x707a6a1a
-	0x83157678	0x277cffd1	0x8d48e5d2	0xf829bd6d
-	0x1fd2750e	0xb6bb8854	0x66d0a20a	0x38f47b92
-	0xa3568b90	0x0d091e16	0x65a8245b	0x238e4299
-	0xd0bc6bbe	0x8ef67730	0xf976b632	0x326d9d24
-	0x96833335	0x1d475e95	0x1f8f41b6	0x65c9dabe
-	0x2133b931	0x43be592d	0xb887160c	0xf21fbfce
-	0xd83ca306	0xa0fb3fe7	0x7da09bf9	0x3f464aa6
-	0x37a7e40a	0xbb0c85bc	0xb172ff01	0xee62de6f
-	0x59d2d646	0x4262e938	0xcd96f5e3	0x0c1862cc
-	0x438388c7	0x9f45d4b2	0xc65ab0b0	0xd24a381c
-	0x1d6c6767	0xedaa1ae2	0xa93eaec0	0x662d776b
-	0x192a88c9	0x6c9d860d	0x61106181	0x30027db0
-	0xa5ae7b76	0x73fc43da	0xd77472b0	0xf4ceba3d
-	0x7cd642c6	0x903dd266	0xe33f58e9	0xbd088621
-	0x8e4c2c12	0xd8c4288e	0x24fdbb22	0xf72ee1f9
-	0xf291bd7e	0x94e68382	0xbbdd9240	0xb59602de
-	0x1b59afd0	0xe5417cf5	0x20bbb538	0xe28fdee3
-	0x0bb16920	0x77d6712a	0x1a0ae5f6	0x0156c43e
-	0x976b53c4	0xef856d7b	0x5a974cfe	0xec53404b
-	0xc627c557	0x3318542a	0x8fd883e6	0x508562b3
-	0xe0ab7501	0x9ae57262	0x95611b5e	0x50c699fd
-	0x984bb8ab	0x5983ed68	0x9947a7c5	0xc0d2374a
-	0xe0845ab6	0x9ffec0fe	0x41873bf5	0xc85c1a4c
-	0x7ef2b12d	0x9e1a3857	0x444da53d	0xb8947919
-	0x84c8588c	0x268f34e3	0x1974cf3d	0xfa67e03f
-	0xc4478570	0xc1896f5c	0xf86de14a	0x9d27ddb7
-	0x5da1c695	0x73c74ab7	0x9123a47b	0x1c9d9563
-	0x7b96bb9f	0x98d20464	0x1f46fd8d	0x4bc35857
-	0xc221a75f	0x04b24c86	0xbe1c7271	0x21a7b19a
-	0x9e050b54	0x8d93d0fb	0x98d7b55b	0xe5fe9502
-	0x9471bff8	0xb3825934	0x5f22d5b2	0x47f4ae9c
-	0x62d7623f	0xfdeef9b6	0x38c64ff3	0x9268fd7b
-	0xa7cfd22e	0x80eeed4c	0xf80a4a3e	0xc9a7e4f4
-	0x6f334b52	0x48e932a5	0xef8720eb	0xb9e86512
-	0xc4183682	0x08142405	0x0a32902d	0x34503fb5
-	0x4c7f132b	0x8db9be38	0x82c20236	0x80a79fa5
-	0x9a31e682	0xca61dd2c	0x2e354b63	0x8d5a4750
-	0x7a838960	0x24dffeb5	0xc7d19837	0xebfbc508
-	0x82e8dbdb	0xe732eaf4	0x109470c1	0xb012af6e
-	0xe2ce17be	0x79db33be	0x281184f3	0xc813df9d
-	0x9e6a771f	0x4a81882c	0xda5baf2c	0xfecbbb6b
-	0x4621a151	0xf4cece92	0xfc230416	0x8d4e758e
-	0xf69c296c	0x9fa2490a	0xeaa56785	0x3075ed95
-	0x4c2ffe06	0x817caf32	0x5a72f33a	0xc6d99da3
-	0x2bbc3dde	0xade463f7	0xb74af1a3	0x738d809d
-	0xd244aeaa	0x7302a2db	0xcb6e9b1d	0xe297c027
-	0x15dbaff6	0xce99c273	0x2810eb0e	0xafbe1f09
-	0xd316d8ba	0x27b8af19	0xb66bdf45	0x3e3b5fbe
-	0x318a4f05	0x2ea7807b	0xed6d40a0	0x58ba8267
-	0x1d1c9d15	0x29af51cd	0x04a46683	0x4b759694
-	0x20ce21e6	0x19ef8036	0x141a8064	0xca36f583
-	0x6d47da5f	0x3a8f6b9a	0x70a99a79	0x03677150
-	0x0feb8c70	0xf3509842	0xf33b5dde	0xbef320a3
-	0x932f9512	0x87497bf0	0xf521a0c8	0xa813483b
-	0xcd6fae43	0xbb7e4dce	0xc7d039b3	0x2d1e6f8b
-	0x1b19cb9e	0x8341c193	0xeffde49d	0x4c40621b
-	0x19d60210	0x8846c540	0xea735ec0	0x0c995dbd
-	0x9aefe2f3	0xbd46f954	0x9b315f98	0x2819307e
-	0xebe2c1f5	0x05919533	0xa52921ee	0xa0bd6746
-	0xd754f5d1	0x39eb2ce6	0x8442d51e	0xb1f75159
-	0x1b617cd1	0x046fc90a	0x6452daca	0xe8d3e3e1
-	0x77406387	0xe3ffbfca	0x89387e91	0x7e348a53
-	0xa5bd3b60	0xc113e95f	0x2ad5a7c4	0x45c1f445
-	0x2a683930	0x3428246c	0x4b89cf6b	0x05e66b1a
-	0x571737eb	0x6e55a8e1	0xbc96ce28	0x24d501f3
-	0x242c8191	0xde8c9472	0xbff946e4	0x551b5759
-	0x411e3420	0x0f0b9299	0x44aaaf70	0xacf2f3df
-	0xe9c44a27	0x781ffdce	0xa39651a5	0xdb7b44a5
-	0xed0ec4d9	0xec17fca2	0xd3ccb15f	0x2b9bd010
-	0x0446a9ef	0x18df586c	0xe227ae08	0xbbaff527
-	0x7958fb15	0x03bfc823	0xc09b7b6b	0xce07b0b3
-	0x0161a359	0x8e21f733	0x8f8168bf	0xc1e2207e
-	0xf9f65e93	0x831b4ba8	0x4b3677f9	0xf8342d03
-	0x03c10268	0xd07233c1	0x0df67d97	0x72434732
-	0x059c7679	0x96526a88	0xb54f9440	0x19e7327f
-	0x6f7f52c1	0xb4b8d069	0xcc4681eb	0x26ea581b
-	0xc26fe16e	0x4073cc56	0x6d252a42	0x689fd0fd
-	0x5d93f1b3	0x070ad283	0xa07cb95b	0x6effe0d1
-	0xe303ed01	0xb8e9b3f4	0x0721647a	0x31f877c6
-	0x134518e5	0x08694d5a	0xb0e6ef3b	0xc7fdc67e
-	0x6111276e	0x45185e0a	0xe13cb5c7	0x7c6ec9e9
-	0xfdee9721	0xc1fb8bcc	0xe25a2bc1	0x075f717e
-	0xd37b7698	0xa9cbfeae	0x6b7d0a28	0x1f1c8bdf
-	0x35d0e6b2	0x8b988b79	0x54f02ea3	0x3426ae01
-	0x5e402b08	0x840d3b8e	0x221527ff	0x906a86f8
-	0x411ce6dc	0xe4b3056e	0x26c9ed04	0xf3d8bc97
-	0x3b02cf67	0x11309c45	0x06ea08bd	0x1c698922
-	0x04e1e492	0x06e0c39d	0xed2937ab	0x83f1911b
-	0x25a94599	0x75d365f0	0x98f191e9	0x845f5e0f
-	0x49547aa4	0x42a0ae2e	0xb7e77fb7	0xe132bfb9
-	0x1cc087a2	0xb0435a85	0x4818ee36	0x4cd90b16
-	0xf56d5e22	0xdc49137b	0xb5f16e70	0x8f8ac784
-	0x84b020c7	0x83c26ace	0x090b3489	0xde14f529
-	0x6ee716ba	0x9deabba1	0x2c230ded	0xd6a68037
-	0xe626043f	0x33431885	0xd26423e7	0xcf259f47
-	0x335dfa6d	0xf052f836	0xcadf2fa5	0x6f2125d9
-	0xafbb23bf	0x19ec69ba	0x84d10bad	0x8cd3ebd5
-	0x36f0fbb1	0xbc1cbfbe	0x96c56812	0x0b05c939
-	0xbd79989d	0xffe74b98	0x6f99405a	0x9f10b14c
-	0x9d8efef4	0x299d21b5	0x9dd2df5a	0xc7ea511b
-	0xbdde106f	0xe5dc7d17	0xee136bc7	0xc4521b6b
-	0x823d31d0	0xcc3c32eb	0xb35ffb33	0x84dd8acd
-	0xe8ddf3d6	0x4611888c	0xfe469f52	0xf8e18215
-	0x768747f0	0x86379e46	0xd3cf9eb7	0x86f1e47d
-	0x30e68652	0x740203fe	0x1031b14e	0x96ce6827
-	0x45f57455	0xe41b7656	0xaa8496d3	0xb99701d0
-	0x485f88ed	0x1d064ef7	0xc7e3348e	0x110d938f
-	0x0c3c9604	0x786b0b35	0x2b2aa6ad	0xdcc45e0b
-	0xe9b29146	0xdbb00ed2	0x0527d574	0xc8029ff1
-	0x5699dfd0	0xd627ff70	0x285fb3d8	0xcf2e6b75
-	0xefad87da	0x4fa21893	0xa391388c	0x5760b28e
-	0x41a95b55	0x82001638	0x6f0e2d45	0xd30f70aa
-	0x5eca612f	0x946317f4	0x24c44ef7	0x470d26f2
-	0xf7e65ef4	0x3a831857	0x53c5699e	0x1af6ff3f
-	0x675b46c3	0x1bd5cfbb	0x03ab61be	0xa67a2b7b
-	0xbae16286	0xe1522d53	0x076d8ec2	0x3a603daa
-	0x0dbacfd9	0xd32acae8	0xe8a23399	0xdf3330bf
-	0xe990c05d	0xfe56bcc3	0x165f868a	0xdf42a220
-	0x6587e194	0x0a31eb94	0xa72a98fb	0x5512801d
-	0xc5fd9c69	0xf7210367	0xcc80f30c	0xc08755bc
-	0x3afe8202	0xc47d603e	0xd17d2990	0xa4addd73
-	0xce89fcc5	0x55726cbd	0xeeb77a64	0x628b3d1c
-	0x2297e332	0x6ecab8e4	0x9739c0d1	0xd53d619c
-	0xbf1a3371	0xe29ea297	0x140436d5	0xfa4802f8
-	0x1b277664	0x4f101407	0xde441685	0x1d36bbf4
-	0x057d9f25	0x7949dbc2	0x57686ffc	0x12984cb7
-	0x0721d76b	0x81ac7aac	0xeb40577c	0x43aaa8d4
-	0xb4e06e63	0x7054a526	0x18bced57	0xa37d26a0
-	0xac039a34	0x156e6d9f	0x07ae4487	0x0e59f4db
-	0x28aeb416	0xc1c4dafd	0xe0357fef	0x683adca7
-	0x93f2d62b	0x8f1f6ec6	0xd42fcbd8	0xfc4e3fad
-	0x082e4bbe	0x578bdbee	0x42dcda04	0x7684e947
-	0x20853da1	0x207dd044	0x56e372bb	0x5ef4c033
-	0x83353865	0xb3b42465	0xb80c9c79	0xffedbed0
-	0x09e45d5b	0x794fe5c7	0x498d4fbd	0xb1cd7a48
-	0xfc89b057	0xc1d19df8	0x9654d056	0xc94cd085
-	0xd7cb03b5	0x13a52c5b	0x52471fd3	0x990aaebe
-	0xe8bed6a7	0xa6960d01	0x68011da1	0x021bf151
-	0xaaa196f2	0x9e3b6188	0xbb28f2c5	0x559d3dd2
-	0xc38861b2	0xfd7242b1	0x716c29e2	0x270236a9
-	0xaaf33479	0x610a7d76	0xc0d564fc	0xf0bb1bd8
-	0x31fb232b	0xf19ebb3f	0xd62acd99	0x5e45578e
-	0x467c587f	0x0ac00140	0x9c7c1705	0x61a8a1ea
-	0x4c5e4e5d	0x0e0d846c	0xd199939c	0xb4c615ae
-	0x4cfe60cd	0x6b4e5cf4	0xe97ad9ec	0xf325a456
-	0x6ca45a64	0xb88b4506	0x9f751f49	0x1d66e330
-	0x59b40444	0x00f530b0	0x9242124d	0xac6de2f9
-	0x7b7e7a67	0x64962ed3	0xfd0825bc	0xbdbcc113
-	0x38d8d589	0x3cedb53e	0x17d95495	0x020b8ac2
-	0xe9aa9bdf	0x0a5a2820	0x64670635	0x91a2a89e
-	0x91bec6be	0xe9b4f902	0x1ef88ee7	0xec6e1208
-	0x149e39ca	0xb140ce3b	0x3210a2a7	0x8e489c45
-	0x59d3ebad	0x30275658	0xc20708d2	0xffdc3e00
-	0x96c700b8	0x3d03aea6	0xf0ce7ad3	0x232a5585
-	0xb0dc6620	0x1c1357b3	0xfb4c6d29	0xe5c5b7b7
-	0xc4bfe2aa	0x37f7ce13	0x433eb884	0x3dde220f
-	0xc1c34602	0xea700f6f	0x37b79490	0xad5761a3
-	0xfc5917b1	0x22f7e1be	0xa90566d8	0x89e9db15
-	0xf91bfa1f	0xdad2260c	0x93eba86f	0x2d94c130
-	0x777290f1	0x2e656559	0x9be4a490	0x377a6ea0
-	0x1b4523e4	0xdca0c8a5	0xb00eed31	0x6baeb803
-	0x9601ee69	0x13d53e86	0xba8d6d8f	0xed6203ce
-	0xc844f9c7	0x91e8a556	0x39974676	0x3b81329b
-	0xdd7f10e1	0xbccb6558	0xb20de25c	0x448c44ee
-	0x8932398a	0x76717b57	0xb20a667a	0x14e2df4a
-	0xa57107f6	0x701b6c36	0x4b83a1ac	0xb39a1c9e
-	0x2cc7e9fe	0xf5ae4a62	0x620687b6	0x2d6aef9d
-	0x6672612c	0x168cdc7e	0x8b09abea	0x522692da
-	0x6461676d	0x34ab3a9c	0x0d61a2ba	0x0590fef1
-	0xe9b4b475	0x2dfb6081	0xbcdafb25	0xdae642aa
-	0x9a9230fd	0xfd67f346	0xdb9d66e1	0x5b307b61
-	0x9d4f1869	0x21133d6f	0x5157502f	0xcc8ccbc5
-	0xb6631100	0xa33f48db	0xc0172774	0x5cb276ac
-	0xe6e5c560	0x07e126dd	0x42bcf23a	0x8064fd70
-	0x567ece78	0xbbc2fe32	0x9d5ee1bb	0x175b24be
-	0xf0feac7a	0x57322618	0xfe9e893f	0xa9b2d67b
-	0x36d03f5a	0xdf178831	0x4da346c5	0x843b1b10
-	0x0d688dca	0x41a475c6	0x4b7adf33	0x145a00dc
-	0xcd226a4d	0x4c40cf2c	0xd4972929	0xbad5ea65
-	0xa96987fa	0xbe247d1c	0x49f2ce89	0xe09bbe72
-	0xee48486e	0x34b41435	0xb41dbb86	0xe58866c9
-	0xe848e228	0x18880947	0xd03cd275	0xca285915
-	0x53dd0097	0xff9069f9	0xaff6a8cd	0xbfe16ac5
-	0x5e88e076	0xac629a26	0x5a99bee9	0xea892a43
-	0x8d1d5ce8	0x806a38e3	0xc4d99fcd	0x331a4a01
-	0x0e586310	0xdd2dfabb	0xe7e6ad37	0x31d67fb1
-	0xbb985560	0xc969ce24	0x3a424634	0x20a2080e
-	0xeb1b587c	0x5cf7da4b	0xdaec0133	0xc99abb17
-	0x63ab9c8f	0xef7e4042	0xca513c8a	0x4e15f5d9
-	0x7cf8fc96	0x464cea5a	0x2363577d	0xd21bb7db
-	0x1d977a0f	0xb02f4878	0x4fd1a03b	0x435b9149
-	0xdfba062e	0xa2f7fc23	0x5ebde93c	0x28e9ed7a
-	0x4023b147	0x9cac0cf9	0x7c5d5ca1	0xb7453148
-	0xa52197d9	0xb85dd94b	0x72ee7e51	0xb81f4f5c
-	0x97a4b485	0x13d8858a	0xa0aabd28	0x9d381125
-	0x4960d2a7	0xa62787b2	0x865231c2	0xd637cc90
-	0x6d58f3b7	0xe2759f6e	0xa28af8da	0x5a005f20
-	0xc11c495b	0x85ecc413	0x657e7b91	0x10b39f7e
-	0x3fcc394a	0x94b3fc3a	0xb359d60e	0x2e6c1555
-	0x67d6d21d	0xb0457bc4	0x004f329a	0x2e131d8b
-	0xfbfbff2a	0x2c1bcbef	0x181f26b6	0x32ebda60
-	0xa0839e5a	0x241097df	0xb3f070a7	0xefbbd9f0
-	0x7c3669c7	0x265f2dbc	0x0bd00e42	0x80d6c4c2
-	0x44874336	0x0b6e7e0a	0xec590889	0xef865c09
-	0x1a02ac8a	0xfbf78784	0xaaf89d75	0xa86c9caa
-	0xc626528d	0xfbcec50f	0x2955f18e	0xb5e9a833
-	0xae60f6bb	0xb3f4c51e	0x21bd6a6e	0x092a6861
-	0x162d73dd	0xacfa4f0e	0x4efed2bd	0x88980089
-	0xa2cee6d9	0xdf0953b8	0x6bf5208d	0x4364ed53
-	0x1a5f19ad	0x2ec7711e	0x7d18832b	0x0f1b28a6
-	0x0e127845	0x278a6a61	0x9e236436	0xf4646e82
-	0x07fff0f3	0x34ae92f9	0xec3e71af	0xf7ec7c67
-	0xdb9ddd62	0xe664e712	0xbb48a158	0x30a14ae6
-	0x0d93b021	0x83082cc8	0x68952311	0x001b0003
-	0xf0688e25	0x6c3b5161	0xfff18a53	0xbd1fb0c9
-	0xe3cc9013	0x1d1e553e	0xa85cdfb0	0x358afc14
-	0x61749007	0x6fad59bd	0xe85f4500	0x26a5ffa1
-	0xedd69e21	0x4c1db8ce	0xaf3be18f	0xcd75c259
-	0xd05f62ee	0x2f0ff1b7	0x717d9bd3	0x62e13392
-	0x159ce5ce	0xcd9e9bff	0x8964600e	0x57d85abb
-	0x3f5ead09	0x2d5d4a55	0x87da8369	0xc7944933
-	0xcde9a717	0x55fa318d	0x112e1607	0x2ca832cb
-	0xb1181bd5	0x7541a7d4	0xac1a1e20	0x6ad024c8
-	0x119378ec	0x60b6cbfb	0x068e2f24	0x83acecb1
-	0x87fd0df3	0x94c9552f	0x08c3d8dc	0x56f1b514
-	0x717d50e9	0x9680fc39	0xa1bdb28a	0x3dfa1c7c
-	0x8fc84774	0xb72e06d7	0x42b7ad1e	0x93646393
-	0xd3632e4a	0x368d78f2	0x36a5ac5b	0x6576a4d8
-	0x8bc6856c	0xd447936a	0xbec6fb22	0xab285e59
-	0x3db2c781	0x72eda32a	0x9d654f18	0xdbd78e99
-	0xbba310ad	0x938ecfc6	0x72d5079a	0x49e2fad4
-	0x4b44dc75	0x81e82165	0xbe269c9c	0x2558ae80
-	0xa3bb693e	0x107d10fd	0x8e4fd977	0x22926b4f
-	0x68c9a7f8	0x6b7439e0	0x5c71c127	0xff5d88b3
-	0x9d8cce8e	0x02982a71	0xf8fe1ceb	0x3ed3996b
-	0x1e4f9957	0x63aca642	0xcc9db51b	0xbcb5af80
-	0x7b2bf393	0x2915079f	0x87f531c5	0xfb06b13a
-	0x550b261c	0xf01fa342	0xcdf4dd86	0x76718f50
-	0x717c6bde	0xf460ef23	0x7f912022	0x54fe5b9b
-	0xc7a5261b	0x073ea6e7	0x71504d55	0x91dd9b8e
-	0x6d259452	0x2dc96e43	0x289959ca	0x128176a5
-	0x8d004371	0x835c494e	0x0efa1879	0xddc02e95
-	0xf0f4618e	0xc67656e2	0xd2bde6b1	0xccaa5e84
-	0xc6592f19	0x91d01db8	0x2b697d22	0x8adfa55f
-	0x5a49e4e7	0x897d5c43	0xd326d94f	0xf5ff0c5b
-	0x57976ca6	0xeff0db4e	0x6d49d466	0x7c054970
-	0xd3eb0f9f	0x0cbdce79	0x1beaf714	0xfe2df967
-	0x6a50895e	0x013167bf	0x6139e59c	0x0662ecee
-	0x9a8d6b53	0xfffb8649	0xce0e685f	0xea5b2a7a
-	0x8819a629	0x5f96afb4	0x8891acfe	0x545f1097
-	0x9f314e1b	0x248a5272	0xa40b8424	0xe42af07a
-	0xa180f331	0x904f3c05	0x98455bc5	0x46198ed7
-	0x03e208e5	0xcf670099	0x7a85b08c	0xba921ae2
-	0x1e6947d0	0xddffa6ec	0xea6330d3	0xcda6957e
-	0x19525cd3	0x311fb407	0x796c1ff4	0x3a2760fb
-	0xde4bdd71	0xdb289b69	0x9811773c	0xa72cd839
-	0x03da90de	0xd42912e8	0x8da1fb0a	0x985d4132
-	0x5890ae40	0x1f7724d0	0xa336824f	0xca19df32
-	0xf8ac73d1	0x61c370a9	0xe152b073	0xdafc6461
-	0x23672042	0x9e6982b6	0x1256c6b4	0xe6bf2c9c
-	0x9dae123e	0x30896b8f	0x99acf3a3	0xaa05d384
-	0xea3b7bb7	0xe711d473	0xa9053351	0x71a85cb4
-	0x3a0f5d25	0x2db3cb48	0x86314a6e	0xf7a2265b
-	0xf7dc1cc3	0x548f56cf	0x4028a1ee	0x7d2e25d5
-	0x68c87e37	0xbced6b8c	0x536cc252	0x68bab5ca
-	0x1158c6c5	0xae0e9509	0x66fa6885	0x22bf2b9a
-	0xa7a60a97	0x18f4f609	0x348623eb	0x773e705f
-	0xb3d6622f	0x8f348186	0x81cb9856	0x64bf21ba
-	0x47e1f96d	0xc95a5843	0xeff6cfce	0x08cb092c
-	0xf214e48d	0xce272fec	0x57bf90df	0x3c425ea8
-	0x856e1f5e	0x5c21d1b6	0x105488a3	0x553971eb
-	0xde614ee5	0xdfa3ac81	0xc5eca5b1	0x69d02d23
-	0x2a0fefb7	0xf9a01854	0xdd99f277	0x75014d7d
-	0x3830e3dd	0x7dd8f1e7	0xdac5ac92	0xbf57c03a
-	0xa5e6a6c7	0xb7c1b7a9	0xc8c8405e	0xfd1977da
-	0x1e6a7ca4	0x299e1025	0x651a0e55	0x53d624a7
-	0xccc9e861	0x901bce45	0x1de5a1ab	0x6140dcef
-	0x3e09eafb	0x20c63cd0	0xff642faa	0xbc91a0a7
-	0xe373e111	0x857236e7	0xe3e61037	0x0b6cc497
-	0xca1da7e6	0x60e53803	0xb68663db	0x42e9956a
-	0xbf4a1650	0xb43f25ec	0xc1232a3a	0x283c2ff3
-	0xcd233183	0x17ccdfc0	0x03ac3e6d	0xa68ced48
-	0xe38217d5	0x03c6472d	0x6a623afc	0xfce0d117
-	0x448ee829	0x0909efd4	0x843a3b4a	0x9ad07683
-	0x2250af2a	0x01ecc053	0x29684919	0x4ee0c62e
-	0xa326a904	0x3ec83943	0xc42b0663	0x966379b2
-	0xc672ece4	0x39391ad3	0x689a10f9	0xd3e9cbd6
-	0x4bfa8446	0xd1ef6375	0xfe01b6a9	0xbda7d01a
-	0x1e6879bf	0x05bdf46e	0x14ccab04	0xb02ae668
-	0x58b51752	0x5eb8e83c	0x753d99de	0x87e4235b
-	0x80b2afe7	0x127439fe	0x127a98a4	0xe5934c92
-	0x86044bc0	0xa9664abb	0x91365b53	0x35b14bda
-	0x67755842	0x7239651a	0x49e0b2e6	0xbb1d25fe
-	0x51ca7213	0xaff2fd82	0xc1223aba	0x02941bcf
-	0xb6ec2cfe	0xaa817dc0	0xe0475250	0x78098112
-	0x750ae102	0x0b3135fa	0x23b648d4	0xbc9d78bd
-	0xc5d7e046	0xe90ef47c	0x7f21eb75	0xdb304b0b
-	0xa2c12ee2	0xb45e62ed	0x9f50feb6	0xe036ff55
-	0x422f410b	0x2385de45	0xb37df6a5	0x4c2abf10
-	0x6a2c7370	0xf35197ac	0x381face9	0x694761c6
-	0xb2275097	0x208824c7	0x945300a0	0x4ad3f83d
-	0x38a7aa12	0x00daaf41	0xcd4b2c19	0x25b2e8f7
-	0x60d3e39b	0xb3dd8220	0x152f86ab	0xd1ec4233
-	0x1c3df78a	0x5aeac74e	0xdeea2fe3	0xcfcf9b2e
-	0x6efc8b2a	0x12a8c5c3	0xb56384e4	0x1b1fe549
-	0xc55acb4d	0x78e7306a	0x733b0f70	0xf4afe6be
-	0x6d904b03	0x7ddd7862	0x4da02602	0xfce1e904
-	0x78773a4b	0x9083e908	0xda8a7593	0xafd8776e
-	0x9e5ae37a	0xd6e7c557	0xad27adaa	0xd0f1a995
-	0x1c84e046	0x3319b21a	0xd24c0d03	0x1789df77
-	0x0f02b9ff	0xdb911f76	0xb2df7654	0x2e75a7bd
-	0x8acc6fd3	0x3c16ec0b	0xe0d7ac22	0x3ddd1ce1
-	0xfa9ec67a	0x48f2c409	0xf8099606	0xd73a459d
-	0x9b2b3fa5	0x8e3c3e9c	0x8b99286a	0x006c0e07
-	0xc299ded3	0x8a2bd400	0x74508dd4	0x609b4afc
-	0x1a532838	0xb352a629	0xd390d8af	0x440a5798
-	0xd31f6ad5	0x161aa48e	0x24a4359f	0xf39f49f7
-	0xff160d2a	0x27a24637	0x84c46d40	0x988d026a
-	0x5697a68f	0xeae970a0	0x42689e3d	0xc84ee62f
-	0x764aabd5	0xb6d74ba5	0x8efc05a6	0xf2d0eccb
-	0x2b4fa41c	0xad24799f	0xf73b8353	0x76bcd448
-	0x08172d5e	0x5c6be301	0x926ffdd6	0xfa31009f
-	0x8339c5f9	0x9dde2840	0x00c2d730	0x6402335f
-	0xf6f84eda	0x5b0e628a	0x140dbafb	0x0533ee67
-	0xa7523e60	0x20ca14b3	0x1145d280	0xb0c0ba41
-	0x81f174d1	0xb80fc64e	0xe8321cfe	0x5762e501
-	0x9e266b75	0x2695a738	0xe3104779	0x1d1ea19e
-	0x15fd1d53	0xf0fbd4ee	0xc82f4552	0x4ea98e23
-	0xec892d69	0x66ccadeb	0x2fdf99b4	0xafffec15
-	0x2de5ee13	0x5e6ead7f	0x20b111cd	0x752254d1
-	0xc0126f43	0xe2695fd8	0x38651d40	0x15b708ce
-	0xf2c2ffdc	0xec24c68c	0x04351ddc	0xceac029b
-	0x0525fc89	0x90e28526	0x0a23a4c2	0xbb33a5c4
-	0x13f1fc38	0x66d79cd9	0x0acabe80	0x8d4ef5d8
-	0x4091808e	0x02f7150b	0xf550597e	0x52703c3f
-	0xfc954b68	0xe9ebaccb	0xd4f35b2a	0x93793446
-	0xc40799e6	0xa963fc0c	0x92c8d8f1	0xbc8218dc
-	0x9ec5c30a	0x8a6a2217	0x63d13dfe	0xea664e1e
-	0x487192a7	0x1c8f8610	0x88e20f93	0xc54a6de3
-	0x0111ae79	0x1335f02e	0xa2e2d37d	0xc2563697
-	0x5fffcdec	0x233919ab	0x3bab1329	0x61943e99
-	0xea7940f7	0x3cc62cf4	0xaedc5bc4	0x41b63f2c
-	0x6dbf285f	0xb4793534	0x0e1013f2	0xc54d8c2d
-	0x23c587f7	0x75df0092	0xc055254a	0x55db2c71
-	0x518eaa5b	0x55c810d6	0x9c44ca37	0x034287ea
-	0xe06a0567	0x221a0d8c	0x037a9164	0x36693ef9
-	0xb7d270a6	0xa8d84a63	0xe8862970	0x484077b7
-	0xab426cb7	0x37db7c9e	0xb34e1752	0x35444958
-	0x00d48e90	0x8142602d	0x8ca28e2c	0x714598c9
-	0xb1cce1be	0xbb98db74	0x400e1029	0x330cb2b6
-	0x1fd3f8ce	0x2abf7516	0xc2d07e5c	0x2b1d2b80
-	0xf06bd895	0x2fa7bc09	0xbdbdf893	0xd8466f85
-	0x61e551b0	0x5b99bfb8	0x86ea5ee7	0xfd82ff9a
-	0xd7c6344a	0x1fa144d8	0x650f0f02	0x71bd73cf
-	0x2825177d	0x56c76399	0x2e0b873e	0xc3bf939d
-	0xf8bc3c1b	0x468482e7	0x33cb98a7	0xa679eaf4
-	0x32ba9b49	0xde86d50c	0x9eeeeee5	0x94a306e5
-	0x432e1c9c	0x37997d0c	0xa84d981f	0xbe07b56d
-	0x4ab6d465	0xa3cd92c4	0x5dea82ab	0xf771249d
-	0x78f87ba5	0x8105df1c	0x3d74e1c1	0xf48cd4c1
-	0x8ad010e1	0x9e9a2758	0x509c8953	0xeaaed79a
-	0x97a4ecb7	0x23ffceb0	0xb3e42e61	0x5f41b4eb
-	0x14d2804c	0x2d635ad3	0xe1314781	0x3921ec18
-	0x3dbebec3	0x94e0df22	0xb0b4724e	0x0e7f986b
-	0x83dd7694	0x7041a22e	0x3c942757	0xd6ff5cbb
-	0x048b0426	0xa5d6c4cb	0x1f4e3bbd	0x78d5924e
-	0x6a857d77	0x1d115ecc	0x73c6a888	0xefb934ee
-	0xa7d1702b	0x6794a668	0x03715b90	0xfbab19f9
-	0xd5a433df	0x12f4d421	0x40519650	0x636a093e
-	0x1601be15	0xe0fbef6f	0x79d775bc	0x789c3a30
-	0x4d9fa618	0xedf8fa70	0xb0fa402d	0x692ee91b
-	0x5a593e5c	0x0fa3667f	0x3f51a636	0x935e28c7
-	0x230b725a	0x4929bc83	0x76de40ad	0x2d9a5f7f
-	0x8799e033	0xbf2700b0	0x5220159d	0x1ed71ca5
-	0xcc66f114	0x15fd868d	0x4236645a	0xded2558e
-	0xa561cc0d	0x02822e5b	0xd0177f80	0xf09badd9
-	0xd5380ae3	0xcfc11a46	0x36713416	0x7f3d60cc
-	0x4018797e	0xc6b23941	0xcb5a4861	0x614ce6df
-	0xabfc0629	0xa519bcfc	0x911f04f0	0xe509b546
-	0xbb411eb9	0x9e6b921c	0xbf0b1c70	0x80c2901c
-	0x85786713	0xad2aafec	0x62711ba7	0x6edb4971
-	0x214eb137	0x45b1b313	0x6742d5e9	0x7daf37a6
-	0x21d6a27a	0x059424f7	0x2c8c3dfb	0xe7a06c77
-	0x10815625	0xb4dc69e8	0x52767f66	0x44d48738
-	0x84d26c93	0x09008893	0xfc21394a	0x82155a72
-	0xc4fd7512	0x6d43cd2f	0xcae99e08	0x453175ae
-	0xc6ee93a3	0x2fed0eac	0xe48fb73d	0x0afe2d2a
-	0x5966735e	0xdc7e5fb6	0xed1ef13d	0x7e08a106
-	0xd3ca0e6b	0x4ce5ca02	0xa0beebed	0xe982c609
-	0x1ee9e5a2	0x24ae26cb	0xfd4c08d4	0x5e85e850
-	0x11b54b3b	0x87209692	0x4a5b0c35	0xcd25dd6f
-	0xd9570253	0xaad0b9fe	0xaf984fee	0x6cf7ae2d
-	0x45d9926c	0x07a66ac6	0x8e7aacdc	0xaf587d66
-	0x53972a4e	0x8da4a6c9	0x2bc311e5	0x36938ae8
-	0x179b965d	0x515743f7	0xb5bbbdcd	0xd8602715
-	0x9e43049f	0x4e78a080	0xba3f1750	0x68635cf0
-	0x85823047	0xbb03b5fd	0xb0d747c8	0x58d214af
-	0x94b1ba85	0x6d2cf8ac	0x2bc1faeb	0x6bd7c1e3
-	0x127658e9	0x8b499020	0xab8f0f62	0xee665a6a
-	0x89240e4d	0x8a95342b	0x00b38ccc	0xe6b14d9d
-	0x32a2af71	0x4c9ecb69	0xc8de2685	0xd7385184
-	0x8e943872	0x809b2c79	0x108511da	0x08b4f54d
-	0x95f52442	0x26fe296f	0xf7e037c0	0xa1aecdd3
-	0x89774a91	0xde67c55f	0x1f9816dc	0x1469a4c2
-	0x28240be2	0x5fd0ad14	0x0949db3a	0x451b94d3
-	0x637e6d49	0x8a4771c8	0xf65104b7	0xc3058c40
-	0x592fe4d0	0xe26129f0	0xe66e6ce9	0x26ab39b8
-	0x308da532	0x205afe77	0x6dc78664	0x84d4890f
-	0x9d49fcb0	0xcac8f2ed	0xe713d798	0xfed7c75b
-	0xe441a0d4	0xdf60df37	0xc2eed2f5	0x2d68b20e
-	0x7827c89a	0x9d4cb9f2	0xb8912cce	0x07516335
-	0x976ffbb6	0x5cd0de48	0xed716f54	0x6f3c9f7f
-	0x34cf42d1	0xc1027cbb	0xde67c065	0xe0a229af
-	0xfc8bd2e8	0xd62ca176	0x8bfb76b2	0x54a1388f
-	0xe0650bb6	0x6d60682b	0xe16cf130	0xbd7c3ca2
-	0xea642814	0xa25f4d44	0x27013786	0x7316aa38
-	0x571511c8	0xf1b6b789	0xb7bfe72b	0x8fd2652c
-	0xbfc7771a	0x51a2e551	0x3bd738c2	0x2698b495
-	0xec69a196	0xd5ecb5c4	0x9bd3224c	0x6d9ab4cf
-	0x326c9942	0x4d711191	0xde9be50a	0xa980ca0b
-	0xe8e59dd0	0x4439e4ae	0x35de914d	0xee499a84
-	0xd1ca0c9d	0xfe6ee96d	0x5b1f4fd0	0xabf0621a
-	0x0c8220c7	0xcb6dbb1e	0xa5116036	0xe858d3c3
-	0x728e3a56	0x3b33e818	0xbe2643c1	0x497bbcc7
-	0xeb369828	0x9a4a01be	0x8c7e72a6	0xaf052f25
-	0x8d3ca85b	0x4703e55e	0x45647d4c	0x86d1e3e8
-	0x40ab59f9	0x3259b195	0xf979a147	0xb8961870
-	0x88b024f9	0x366e26bc	0xd6811525	0x252910c2
-	0x4223a20e	0x7fc971a3	0x4a639bf3	0xb6550c3b
-	0xfe05e552	0xbdc98897	0x509923ff	0xf51a5abc
-	0xc6cc0891	0x61cdac05	0x03a68664	0x1b80cc76
-	0xe18d8ee1	0x798bb4d2	0xd7769bf9	0x9ab4c02d
-	0x7484774b	0xa9ee2c8b	0x87d34c85	0x15697682
-	0x9f6a4a55	0x9d7a731c	0x10014d6a	0xb9798070
-	0xd42f79cb	0x89db59b3	0xd5b0a0b6	0xf60864a5
-	0x2d6fb084	0x1cb607b2	0x48232701	0x9310cbc6
-	0x5bc81c98	0x6b25016c	0x2014b99d	0x0836e60b
-	0x0addbc4c	0x3b8bac7c	0x8d95ac77	0x1d56c3c7
-	0x58333104	0x3d6eb719	0x676eb951	0xd5c2d1a3
-	0x239dae86	0x92181ab8	0xbdde9741	0x7995d452
-	0xe0020661	0x2f80c8b7	0xeedcd4fc	0xe4bde175
-	0xb98fdf78	0x84b9228f	0x78ecb4f3	0xe99e5d46
-	0xa33b9b96	0xe2cbc71c	0xc19e2146	0xdc0ee758
-	0x2d8f8767	0x2036685b	0x149df155	0x2e7ab376
-	0xb13b4266	0xf5c8a3b0	0x02ca1e19	0x1badd81b
-	0xb9c1832a	0x73b31f75	0x69979b55	0x567070a2
-	0x2edeb3dc	0x26b55921	0x461df49f	0xc1aba883
-	0x25d6faec	0x5260e9bf	0xa8ccdd4c	0x04291961
-	0xfaf7a1b8	0xbc2d36e3	0xd6c86385	0x2757fbb9
-	0x62c7107c	0x87dac461	0x0c006454	0x0e971e49
-	0x4749afca	0x7f1fb389	0xdc0b69d3	0xc69fab09
-	0x12c372c9	0x78480a51	0x8ab03a94	0xb37022ca
-	0x1d00e893	0x0989de45	0x8c819503	0x8e0e1c06
-	0x11cfef86	0x3c2386a6	0x66c0e6c8	0x1befa478
-	0xd2e7a4a7	0x9a8b5917	0x2cfa1816	0xaf7e6c7a
-	0xd6c9f0ff	0x1aada3e0	0xbe36a471	0x5a91f3c7
-	0x6c61ea95	0x5246ef7c	0x20bc86c4	0xcfd87abd
-	0xdc61f595	0x8310a684	0x0477e35c	0xe59e776f
-	0xfa403863	0xdaf7bcb1	0xd6084825	0xb90bb047
-	0xeb9ff684	0x7223fbca	0x6b4af987	0x6b2553f8
-	0xdaabc6d2	0x82e2ebc3	0xa7c1c054	0x667eb0a7
-	0x53a0c7d4	0x3fcba743	0x38170187	0x2a2e5830
-	0xee134608	0xcd6e0112	0xac0831f9	0x9537d532
-	0x1e176b9c	0xe3fcb69f	0x17a2eee9	0xa9e6467f
-	0xbf6b0246	0x6a08c0fb	0x7fb943b6	0xb8f67c0e
-	0x2b3b4ffc	0xb155d20c	0x4eb5de53	0xf078715b
-	>;
diff --git a/arch/x86/dts/microcode/m0130673325.dtsi b/arch/x86/dts/microcode/m0130673325.dtsi
new file mode 100644
index 0000000000..8063a752c9
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130673325.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x325>;
+intel,date-code = <0x11192014>;
+intel,processor-signature = <0x30673>;
+intel,checksum = <0x5edcd570>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x25030000	0x14201911	0x73060300
+	0x70d5dc5e	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x25030000
+	0x00000000	0x00000000	0x19111420	0x11320000
+	0x01000000	0x73060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0xfff634fa	0x937ca2ab	0xb28d19b6	0xdefc54a7
+	0xd8df0b32	0x13e9a2a8	0x7b7cb24d	0xd588d3a7
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x1f504653	0xe21b5652	0xe97686b4
+	0x5f67c59f	0xa9b26fd4	0x9dc84f1a	0x0f02451e
+	0x0a821675	0x12547714	0xefe1084e	0x91260f23
+	0x17e46cf5	0x3dad6dd8	0x4e16210b	0x0472bd56
+	0xd3fca8a6	0xfa3f5184	0x87d91976	0xa7b008eb
+	0x17bad553	0x89835b41	0x32e7d87c	0xdfcf298a
+	0x6a740196	0x0405a296	0x4f830df5	0xfcf047f1
+	0xca0e7a10	0x8d0afa7b	0x08facdae	0xcf7bbe22
+	0x8e08e283	0x6b51333b	0x452cf734	0x03da5390
+	0x7075365b	0x402e71ba	0x4a8d4547	0x0da62d39
+	0x3fcae342	0xe8cb1437	0x6ddc21bd	0xe22b5edb
+	0x319decc1	0x6c558ad3	0x3b44648a	0x8cdf8642
+	0x5a3a8cdf	0x6aae06b2	0x7360d1a5	0x774351c9
+	0x88681d42	0x466d3573	0x6d8538cb	0xa3350f1e
+	0x7b431d3c	0x21074f32	0x6955a68f	0xa3988611
+	0xad1c79d3	0xe00884c6	0x12e5baa8	0x7dad4109
+	0x61d16a48	0xd2074a23	0x58611da6	0xad7b774e
+	0x90a80987	0x05aca95d	0x482b51ca	0xbb8fe27d
+	0x2abe5e48	0x590c8b98	0xef745dbf	0xce17a591
+	0x6607216b	0xbefec476	0x7a8b08a9	0xb281bfc4
+	0x76f7dc81	0xaacd78a8	0x38cd6888	0x9636aa2e
+	0x7035053d	0x069305f5	0x0da92823	0x46d344df
+	0xce46f308	0x1fcca5d0	0xf4b0daa0	0xed8ecd8e
+	0xdae9e33d	0x69be5bef	0xc545c95b	0xadeaeeb8
+	0xdd903783	0x5a2f3287	0x73865fd0	0x865d709d
+	0x1ed58537	0xe44c821a	0xc9ad0d97	0xe81b9851
+	0x552cf1e7	0x03a3b2dc	0x219194a0	0xd8875c82
+	0xe39b25b7	0x61149b84	0x79a99812	0x287eada3
+	0x057cc940	0x0ed85405	0xf4cbb20d	0x8d87a099
+	0x2018b6ae	0xd14f3646	0x35bf5bd8	0x82931be1
+	0x52234bd1	0x9143a967	0xd9d1a3d4	0x869c266c
+	0xcaff55f0	0x64ad39c2	0x02435da4	0x32e2907c
+	0xbc2682a9	0x60863cea	0x163028c0	0x007fc9fd
+	0x6553eb56	0xab00c11c	0x3aa77e22	0x87f722d4
+	0x004850a6	0x5460e040	0x9e91042c	0x46dd43c7
+	0x3b05c92f	0x060ce074	0x62730a12	0xc6d47872
+	0x03d26f06	0xf7b3d04f	0x92adc672	0xc31d8130
+	0xd40eab22	0x616b7f8f	0x56b2c742	0xde6015c3
+	0xc10c0d02	0x3ab28f97	0xa091494f	0x1fa0c28b
+	0xc76c5661	0x27effd8f	0x3de80c1e	0x5713a42c
+	0xd9114db2	0x17ab3314	0x0e3aea42	0x60712f1f
+	0x4a7d4389	0x9db1857c	0x1103baa8	0x579462a6
+	0x82ac5a7e	0xda8d9f67	0x835bed5a	0x08705479
+	0xbf4bd494	0x082d8b22	0x408878b0	0xa698e9d8
+	0x27fba6da	0x2308fb71	0xcc1b9c9c	0x5200bd18
+	0xf1baf601	0xe67b1d1b	0xf3c95153	0xf8fb4f22
+	0x2859e330	0x3e7bc864	0x02c88201	0xf835c5f7
+	0xcefd31e1	0x4c430b43	0xce13d99c	0xf9aa01ab
+	0x9f5c0d3a	0xbf06696f	0xc834c22c	0x145cf026
+	0xb45e1f1b	0x97302dd5	0x5b5d108a	0xffde5401
+	0xffbd2caf	0x8eb5c823	0x3f113711	0x144ec354
+	0xab3864a7	0xeee70354	0x208ea79c	0x1b2c7364
+	0xc3cb82d0	0x21d9b3bc	0x27846121	0x50bd8910
+	0x43a2616a	0xface9686	0xe12195b9	0xde4639d9
+	0x0b88b493	0x32b1685e	0xbd782bea	0xc674188e
+	0x23425d26	0x9d2d3c81	0x33b3a260	0x4ebebf2f
+	0x6a634d1f	0xb977b1c1	0x476223c5	0x654c5461
+	0xbeaa9c98	0x75242b30	0x26061148	0x69889154
+	0x910a2132	0x07df3136	0x372a7cf0	0x58541d8f
+	0x65ce78aa	0x0c6e4ff7	0xab8c31b6	0xbe39960d
+	0x63bc072d	0x53872b7c	0x959f3049	0xc13ba7a0
+	0xd7111cd7	0x5e68763f	0x923dc674	0xdb2e8a4d
+	0x5c2cd5e0	0xd93be0e2	0x1bccff32	0xbbdffc8a
+	0x1641ff1b	0xeab24fc7	0x70aff37e	0xc87fe4f8
+	0x32afd630	0x060dbdf9	0x6e119a8c	0x987e51c5
+	0x57abb8f6	0x15b3755b	0x938f709a	0x7c4b5522
+	0xfd376691	0xd909457d	0x58656778	0x3bdee518
+	0xaf65afd2	0xe1cd74ec	0xd2bc8a3a	0x9aa30f8b
+	0x6e1f183f	0xc2fa7bf8	0xa60385fd	0xe0320d46
+	0x2e5bc0df	0xf95b8c37	0xfa760bc7	0xc8960509
+	0xdebed2f2	0x560ac9de	0xb3ac0e62	0xefe328dc
+	0x358d5330	0x72c31526	0x5932780a	0xb3b824b4
+	0xda37daae	0x69dd74c1	0x41c91b5c	0x8180b956
+	0xc69574b5	0x1830993b	0x0d5ef14b	0xa8dec45f
+	0x5c4019ed	0x559e7b51	0xd07a3c14	0x49208a2b
+	0x5265dad8	0x1b9826c0	0xb8cc3edf	0x63ccaf33
+	0xdfdfb78b	0x3292f976	0x9f1ddbc1	0x2e3bfa8f
+	0xc4b5a941	0xd8b1fcea	0x68764a2c	0xbec828e1
+	0x07db4118	0x2022cfd1	0x6be82389	0x7ecb046a
+	0xd31a639f	0xa0f50a18	0xbb4dc035	0x765a6e5f
+	0x59fe51c8	0xd2138643	0xccfeebae	0x234c0440
+	0x49bcdabd	0x88e86cb6	0x48760e88	0xcc34f20c
+	0x0977dead	0xf3f0d324	0x736f4df6	0x0a94f658
+	0x0bbb01cb	0xe962549c	0x6a1c39c6	0xbec25a26
+	0x4cb71dd7	0xf1043105	0xba0f3726	0xc97645e3
+	0x23d4b508	0x7c0827ae	0x097f96f0	0x0a054e0a
+	0x79e7a543	0xbedbd7d1	0x52d2b51f	0xebabfee4
+	0x1f0e76e2	0xa07922a8	0x3a630243	0x41b8b460
+	0x11f8e1be	0x97ab45cf	0xd952588f	0x70461a90
+	0xdf62afd8	0x169cd499	0xc9a38028	0xe2d36ebf
+	0xa86477c5	0x1890d4fb	0xb78c189e	0x6002b07d
+	0x346599a1	0x998b8687	0xa073f3ff	0x561c2a62
+	0xc4904bcd	0x59a5194c	0x6b2d285d	0x3c7208dd
+	0x1a2e9b5e	0x7a7732a8	0x2c803c45	0xb307e8fe
+	0x9a402093	0x521740de	0xb25a372e	0x1abeec65
+	0xd9f84a17	0xed465fd4	0xfcc2e034	0xdc9bc727
+	0x9607ab7b	0xe0bd62d8	0x8630873a	0x361b3b75
+	0x603255fa	0xd815876b	0x32d0e705	0x5f99a520
+	0xf15a63b3	0x83f3009f	0x7ad4b916	0x1ba9093c
+	0x824dc86d	0xcd792af9	0x8d1e623d	0xad4877c1
+	0x2c09f508	0xab062540	0x242c5f5e	0xb46796bd
+	0x0bbc1a5d	0x02be8545	0x4ad68f23	0x370b4b1b
+	0xc16c7ebf	0x8b65ef74	0x11b64ded	0xc00f5586
+	0x41d6033a	0x0f79c8e9	0x356094c0	0xff3ec289
+	0x11a0d26f	0x347ebbef	0x23f2b11a	0xb6b15aca
+	0xe6856320	0xacecde47	0x513fbdea	0x7d7ac026
+	0xb72b0011	0x7d8cac25	0x222704f3	0xabc6b166
+	0x60995d26	0x95ccf438	0xce21d44f	0x27e15e98
+	0x9e229da5	0x929009b0	0xe79afdb0	0xf91bcab4
+	0xe5894312	0xe98d7607	0xb2bd2408	0x5abc5003
+	0x532b2c0a	0xb41dbdf7	0x248d6b00	0x7b811187
+	0xff7afcb3	0x818c2c38	0xacc7a704	0xaa14713a
+	0xeed076d3	0xcca8d4aa	0xd90177c0	0x9fcc01ae
+	0x8edd4189	0x1c896cfe	0xc4856a25	0xbeeb2217
+	0x52249b24	0xad45ff42	0xb43ae3a7	0x4bf0df57
+	0x91e369cf	0xcfafc488	0x6c218f44	0x0aab7b09
+	0x5f9c2410	0x87cdac03	0x986e83cd	0x56a7bba7
+	0xc7d2270b	0x467b995a	0x4b398fc4	0x64f04f87
+	0x30334708	0x8d0c7e49	0x69c792c2	0x725eba77
+	0x6870df0c	0x84d8a30c	0x0c5c6ac2	0xd9bc43cb
+	0xc52ab350	0x64878641	0xef306551	0xcfe54739
+	0x1aa176e8	0x6f1a7e1a	0x965be809	0x21e345f9
+	0x9ad41590	0x5e5de630	0x82cc1207	0x6120734f
+	0x846449fb	0x9d822218	0x2c8e025f	0x747f180c
+	0x90a64365	0xec79c646	0xaf2a29b0	0xb5a4cfa3
+	0x4f5b82de	0x0b7ad494	0x3b02b3e0	0xe5d96463
+	0x241aa4f3	0xefeeed3d	0x6e6d49ff	0x2d45821c
+	0x4598f881	0x7de00efb	0x25509321	0xc64ceb14
+	0x218dde9d	0x59c3cf6b	0xf8f702e6	0x3e0cf0c0
+	0x178f8a4a	0xc8aa3338	0xdcb7989d	0x297f30a0
+	0x270b7ea6	0xceff00a3	0x22ec287d	0x50673360
+	0x1fccbc8f	0x66c3805a	0x8a327234	0x52e1978f
+	0x538b121c	0x1f2fa957	0xeada2b4e	0x29423125
+	0x81d3a179	0x968b4097	0x3522324d	0x5cccf20c
+	0xa6adfc16	0x3d1cb3b9	0xbaefea60	0x57978720
+	0xf5eb4b9c	0x5a8b3acf	0x4f3ac467	0x94a7e4ca
+	0xb4100044	0x54fc2e4c	0x16ec9a22	0x3aecc34a
+	0x6df7f52a	0xe1279f5c	0xaa25ad1a	0x907baa13
+	0x51c19956	0x35987a2e	0x1adbb651	0xaf0a5285
+	0x83ce12f0	0xcbabf9e6	0xfaa1cbff	0x73139922
+	0xc6f5b18a	0x9f91c4fd	0x6583a1bf	0xa144eed0
+	0xc9f2b43b	0x249407d3	0xe3520b2c	0x60dc9aba
+	0x53ff14c4	0x24133ac0	0x4b6a4452	0xe0aea55c
+	0x884302dc	0x24d8ced4	0x3db6976b	0x48aad95a
+	0x7e4defba	0x80215bbf	0x62241272	0x0747edc0
+	0x32206c16	0xffebdcc1	0xdd1662c9	0x1bd3eb01
+	0x785d4a0f	0x4b37087b	0xce5142e8	0x1262ef36
+	0xb04665e5	0x84491927	0x9df53726	0x8d175409
+	0x79fcc87b	0x647f1da3	0x68c89316	0x14926e0b
+	0xf7ca65bb	0x20634f45	0xbd13da4c	0x683991d5
+	0x81cab56c	0xeb840c6a	0x8954031e	0x06deeb42
+	0x92f26c77	0x6b2de0c6	0x80a23d71	0xd11b9d58
+	0x703498a0	0xacade451	0x797bf69b	0x0f6b0db2
+	0x92430faa	0x1756940d	0x99aa9ef0	0xcee8c383
+	0x8bc70735	0x19b263e3	0x36a5345d	0x271c893d
+	0xa32a1999	0x0345759b	0x3f89c616	0x52132086
+	0x10d16c86	0xd7425739	0x961a376a	0x3c4f62a9
+	0x64c0bbe2	0xbf9fcf69	0x3b9055a6	0x88ce084f
+	0x12d088cc	0x2ca9dba5	0x01e2d480	0x7510c47a
+	0x48439c10	0xb82ea353	0xc749c7e4	0x9a768665
+	0xb4233311	0xd62cc354	0x978f7fb4	0x24598a22
+	0x559f80e1	0x18038c96	0xf4a8607a	0x9b45454a
+	0x966c8058	0xbad65e97	0x3247c4c1	0xf402cdb6
+	0x9210a715	0xa4f007f1	0x99154ab2	0x65fbcbfe
+	0x9f80323c	0x34699431	0x01676213	0x30a1e6fa
+	0xd25522c1	0x379c77d4	0x1871da5e	0xce5e5496
+	0x3d6b8be4	0x1dca1d1a	0xa00a2d5c	0x87e10ca3
+	0xe693d866	0x460474d3	0x3f63c391	0xe7ea29d1
+	0x2cec6e1e	0x14d4984b	0xc5d6b60b	0x6d6e0837
+	0x3d4c924c	0x90489257	0xfc8d6a83	0x925c8cb2
+	0xbfe92b1c	0x49242696	0x2e61cd01	0x2257e796
+	0x05a1a9bf	0x3cf1f59c	0x8dbca249	0x224abfe4
+	0xd03b80f2	0x69958e27	0x2ab3a3cd	0x12c385a2
+	0x009f8225	0xfdd732be	0x008ab069	0xf3c83e93
+	0xaeb24747	0xc589db37	0xcde6618d	0x20bd0207
+	0x385e9501	0x0fd9495c	0x5b2e2ed8	0x1078f265
+	0xc90dbe7a	0x1a41d9c9	0x8f9874d3	0xafddd25a
+	0x6c06f499	0x30fbfec6	0xd7c880a7	0x88707b30
+	0xa6dbcb05	0x952fbc2c	0x634e6259	0xe6b40847
+	0x6461bd47	0xae4d5763	0x2b2bba28	0xb80d9555
+	0x2ec5ca1e	0x29d9df5f	0x41cc03d9	0x2235582b
+	0x23835179	0x21d0ccf1	0x804ba9b0	0x57b9b8d7
+	0x1497654c	0xf1e54c96	0x9049e9bf	0xec7a7398
+	0xcfe60cef	0xd8a41f9e	0x924e41e8	0xd4310360
+	0x0bc22c8e	0x8e9949f5	0x1de2e407	0x83cb7e67
+	0x43eadc46	0x428a67b1	0xc3be2567	0x2e64f02d
+	0x416bb222	0xbc70ec3a	0x582bb3ed	0xcda0b133
+	0xb906e982	0xcaa44950	0xf9c503a3	0xe83283a1
+	0x5126b967	0x525d3279	0x0ac69ff9	0xcd705322
+	0x2d8429a9	0x6e76fe2e	0x81794602	0x666ab1bc
+	0x3f31b894	0xcffd21c4	0xf5cd3705	0x114db9a9
+	0x4ab6f993	0xc413712b	0x4d3e7649	0xd167da79
+	0x33c9f1ce	0x1d7c81f4	0x06f9b423	0x747aff7d
+	0x0d52f157	0x839b8075	0x0a853d42	0x6203b11e
+	0x4677d3af	0x38abf342	0x3623c79f	0xbca55b66
+	0x8bc84201	0x4bc018ea	0x03233c7c	0x615f7eb2
+	0x0c60cef9	0xe0308dbf	0x12031915	0xb29fbfb7
+	0x78434066	0x4ee2c89a	0x184f0327	0x47f9d7be
+	0xcce175a6	0x6b3e0b3c	0xdc5b8812	0xc4a0678b
+	0x4023109a	0x152b2c76	0x363fc158	0x8c3e2f21
+	0xa064aed6	0xeb042d45	0x23c24cc2	0x1a8af60b
+	0x07b9b84b	0x29d990b4	0x2609d654	0xddb12106
+	0x23cb29bb	0xfd7be4d6	0x458e378f	0x3435ef60
+	0xf4c5a257	0xfe2b302b	0xa44c6fca	0x9594eb9c
+	0x42562735	0xdcd2ae0f	0x6b121b2b	0x955db8b2
+	0x99324409	0xf9040b5a	0xd4ee06a6	0xe02dde19
+	0x1d689a66	0x01c5034b	0xe16762ff	0x404c08a4
+	0xb797f9f9	0x409e15c8	0x7f8a86d5	0x8c097dc3
+	0x88853010	0x7870d226	0xd9684129	0x5b1f1ff5
+	0xcf0f9327	0x5631fdd0	0x85ad0d39	0x9a7a3da0
+	0x2f196f96	0x98f80f57	0xc2f5bc2b	0xf3c89a99
+	0x5167b4e8	0x38a5b8da	0x31274e92	0x316736b3
+	0x0ba380a6	0x4cdab635	0x55c10afd	0x0aa42f67
+	0x5cb9233d	0xefbea208	0x614caf1e	0xa7b51e52
+	0xbca0669b	0x3e82e113	0x8437d9ea	0xed52af57
+	0x90c58450	0xd58d0939	0x6065bacb	0xa0f03557
+	0x28dacf55	0x95616db9	0xe22c6304	0xf95f1451
+	0x68a017d1	0x744940a8	0x29656d46	0xb462a093
+	0xda67e118	0x9beae14d	0x41295fc2	0xf4832210
+	0xd546e11c	0x9a6fbd36	0x1fa63a12	0x080dd512
+	0x142445a8	0xd7924445	0x7e81a85d	0x0fe2facb
+	0xaea25515	0xdadd52ac	0xd4d4c9d1	0xe53a1391
+	0xf23efc0e	0xae8d8a11	0xe4a18294	0x7897206d
+	0x882f7598	0xcfba1c50	0xd2ab7795	0xabce7dd4
+	0xf953ec47	0xe61d6306	0xd16895b7	0x8754c3fe
+	0x71b45033	0xa13c4375	0x12eeaccb	0x982003cc
+	0x207896e1	0x49d067a4	0x5f302283	0xe4df36fd
+	0xb00cfa4d	0x9ae60753	0xd7bac02a	0x994f4996
+	0xfe146dae	0x97626cf2	0x9e42c940	0x6e337e36
+	0xb6afed1a	0xeb2fd381	0x934baf9a	0xf832addc
+	0x6f979a6f	0x99487a6c	0x57544e74	0x0c66d838
+	0xa061f71b	0x0ddcd233	0x1848e2c7	0xd4c88955
+	0x6c64fe17	0x9bd44131	0xe582e3d4	0xa005bd26
+	0x703b0eea	0x21bd18c1	0x664a9e98	0xe0590718
+	0xd3e4736d	0x0ff91923	0x5dc8871d	0x31699e80
+	0x61a37893	0x1ae82483	0xe45118a2	0xfecea103
+	0xf41828d5	0x4ed049d7	0xdfbade95	0xd238ccf9
+	0x992a8e55	0xa09b38ba	0xcfbd44d9	0x91504f56
+	0xdaa43955	0x1b33f9f3	0xa78246cd	0xa8fd012c
+	0x45af83b9	0xaac19610	0xd89f53b1	0xffd31eeb
+	0x6197b65d	0x7f47d34b	0x6e93fdfb	0x595a289f
+	0x385174bf	0x6f3496b9	0xe49b3f1a	0xfe745cd6
+	0xfdb24e8e	0x6269a7ac	0xa8deb024	0x959a4ca3
+	0xfb164ad5	0x0a74d852	0xc022a450	0x7c46bbb4
+	0xb2cb2e2d	0x1fc8d084	0xd1cd2aa7	0xf301e029
+	0xd0d8bb65	0x89968da9	0x05409da8	0x24134907
+	0x48c6a151	0x390da0bc	0x32816da9	0x6fdda0f8
+	0x7a5e60ca	0xc500eb10	0xdbd2126f	0x22dc1c8c
+	0x165efc8e	0xc52f4553	0xe4488f60	0xbbbd961c
+	0xa965f0db	0x256cafb8	0x35b82b80	0x1b9bbf5d
+	0x69aa3130	0x2f5402f1	0xb7db92c6	0xcdda626d
+	0x9d50e8f8	0xd75b2b43	0x23869cbb	0x18f1fc43
+	0xc4500abc	0x7b22b871	0x93d281b7	0xe72b7f91
+	0xb8a3d2f7	0x40de9703	0xfde8a07c	0xff614acf
+	0x14ba7173	0x4c9d758d	0x67ba546f	0x6edc57de
+	0xe3397593	0x6076ad6f	0x54bbf0fb	0xc7aa004a
+	0x9099bac2	0x43001c2e	0xef39dc79	0xfbf16c39
+	0x43d3b4d9	0x4e1ccb60	0x0a5770ee	0xfeb0bb21
+	0x8f5ef605	0xd69a2259	0x5ae00282	0x81422a35
+	0x537fcf9a	0x740907f9	0x1e980cf1	0xfaf41103
+	0x8554081f	0x9044d4fa	0x9349fecb	0x2e12081a
+	0x9c63d3ad	0xb02fc0e9	0xb9f71ff1	0x7ffc123b
+	0x221be745	0x6b1378b4	0x283d86e2	0x24fbdd88
+	0xecaa1214	0x0e2a05b0	0x49256317	0xe1efbdd1
+	0x2b40232e	0x8a44c71e	0xe5ab10ac	0x55baf697
+	0x57c9cb8c	0xef2cdf39	0x9e28e29c	0x82fa8623
+	0x85090ab9	0x4bf3c17f	0xeb34b5e7	0xbbffc965
+	0x9be897b7	0x7a54a66a	0x0182c5b7	0xfbe04efa
+	0x79a3aedf	0xb04bdde6	0x12396b09	0x7f2eea54
+	0x139fced2	0x2ed4e710	0x8e587a3e	0xc1150171
+	0x3d4475eb	0x3bd4dcbc	0xd15a4ee5	0xf6a03e6d
+	0xd6946d8b	0xc7f12861	0xb46f2665	0x4778aaaa
+	0x90fd4944	0x91b58ad9	0xce88f970	0x6b002000
+	0x3942bf93	0x58560cb2	0x555f27b8	0x51e7e2cb
+	0xe8d32c0a	0x76979f1c	0x0fbbef02	0x784ee6f6
+	0x72e1f85a	0xd2006d22	0xe142e64c	0x0e821726
+	0x0204234c	0x76aff6dd	0x72c02389	0x79674b40
+	0x48c827a4	0xd60a816e	0x4361e2a7	0x20575b11
+	0xc0a15faa	0x1bd24f4f	0xde97121a	0x886610d9
+	0x3c1488dd	0x74331a2c	0xb80b075b	0x1cbaab02
+	0x310e08f5	0xe7e63832	0xf5559bc2	0x5939166c
+	0xfb966138	0x2c192ef1	0x3022c840	0x4760139f
+	0xfc9e25c7	0xa40b3af5	0xf960ef95	0x4bd0fe44
+	0xf951e214	0x320d1105	0x3886b597	0x90be3da2
+	0x16b5e7ee	0x81b43af0	0x4a83b571	0xea294a6f
+	0xe879058d	0xb80d4a36	0x4f3807d6	0xee2a3d4f
+	0x90fd7abf	0x76a13008	0x3a31e37a	0x60cbe826
+	0xfddf43df	0xeb00f98e	0xb22c6cf8	0xc17d7ca7
+	0x82c1b9d2	0xd8408d4c	0x349a8c22	0x55273d19
+	0xc841f4f1	0x6d54d550	0xcc41b69b	0xc7365812
+	0x85f41eea	0x432850c3	0xc27c009d	0xe397479c
+	0x86fe387b	0x578837d7	0xbe61890c	0xdbb0ccd7
+	0x7be07b26	0xeb6f962d	0x02e3e226	0x490c78fa
+	0xba8357ca	0xe0e28646	0x098fdd96	0xaf92d911
+	0xb94371e8	0x2f172a39	0x548d45d0	0x30fad17f
+	0xfb74d606	0x2f5cbfa2	0x25f720a7	0x9bb55ff9
+	0x95af7efd	0xbd078a82	0x67acecf6	0x5890b891
+	0xadb4266b	0x4de99f69	0xa6f5513d	0xc639cde0
+	0xadf8f9db	0xe49c0753	0xf7abf355	0xccbc3ef2
+	0x4da3b1b0	0x6b4930ae	0x0e4dcc32	0x44d27988
+	0xd8a0742a	0x85f9141e	0x4af69334	0x3b02912d
+	0x8d90147b	0xecdeb8e5	0x8c5c76c7	0xf64f4537
+	0x4c2e07c6	0x6caa89b2	0x22fbb640	0x75540372
+	0x07c538a5	0xe3dd71f7	0xd54e1233	0x2bff75b2
+	0x1b65ed38	0x5d5ee6d6	0xf3d99db4	0xe535f17d
+	0xe9b355d0	0xfb27c862	0x2418a7e9	0x83020f9b
+	0x17c850b5	0xc7a49afd	0xfa7cc598	0x4caa65b0
+	0xe35d78ab	0x5fbe5a68	0xb8b23c84	0xdd30c3c7
+	0x166d9c71	0xce9512ca	0x8ff12b46	0xc4f5a4e1
+	0x772f87cb	0x9910eba8	0xd8f966e7	0x1e7a1029
+	0xbdb95937	0xe8745fd3	0x97bd0c23	0xf08d29cb
+	0x3e144fc2	0x4ea5c2d2	0x4dbb3579	0xb2d6d1fb
+	0x59a9499a	0x07de7cf3	0xe5093e74	0x9620e2ba
+	0x98db53bf	0x0088a257	0x81575927	0x1572a999
+	0x85014396	0xf252e4c7	0x935494a7	0xba6777de
+	0xf0cbee95	0x89224156	0x726f5f9c	0xc6a97741
+	0x438936dd	0x02982457	0x69e0b7aa	0x6b2cfa7a
+	0xd920fc79	0x088f473f	0xbdc049ad	0x26fe03eb
+	0x51ce0c14	0xd4ee50da	0xefba7a8d	0x41d48c15
+	0x2fc64c16	0xb910ee77	0x8fd3c6cc	0xf2ea6eae
+	0x799585ed	0x78bb8529	0xf5e8dafe	0xc4d2e7ec
+	0xacb82780	0xc366cc65	0x786dfbe0	0xf6858178
+	0xc0737f16	0xcd7ac719	0xfc1d25f9	0x9bac062a
+	0xf861f2c3	0x534306a2	0xc885076c	0x228b59be
+	0xb5a03917	0xa49ee2e1	0xd7e3f947	0x2993430b
+	0x936b3a69	0xfddd2df8	0x409bcbfc	0x9a49ea67
+	0xda19b129	0x52d00d43	0x594b5373	0xb3ec4e85
+	0x99ba948e	0xd5a139e7	0x0e309bcb	0x824bdac4
+	0xe846138e	0x8e867ec9	0x3b3b3de0	0xb193c1c3
+	0x1d972fb9	0x37e7c572	0x2312fe3f	0x233675c4
+	0xccbe653e	0x7f33fdcf	0x6dbb5b33	0xa1482994
+	0xb053851f	0xa136a22b	0xab83000c	0x8baa7f8c
+	0xf63ce4d1	0x0add4950	0x1e2118a1	0x778b55d9
+	0x11283afb	0xa0ece7a4	0xd5cf4afb	0xaa425954
+	0x735e7cdf	0x915f28bb	0x9f257f4c	0x35f60425
+	0x428317aa	0xde7e7394	0x903cd466	0xd3b76f46
+	0x440cb5c7	0x926ead8a	0x4ad0bc01	0x589d2503
+	0x36c6dbe2	0xae3cb112	0x8af34336	0x98086144
+	0x998764a3	0xf18c15fa	0x4c6b1e80	0xdbea3a77
+	0xdbca504d	0x48e922eb	0xe7d2efd1	0xb2a55650
+	0xd40359eb	0xd669304f	0x3e0d1323	0x8fdbf002
+	0xb8cd2146	0x4f70e597	0xadb80b28	0x6968f1aa
+	0x5785cb7b	0x09d452e1	0x2a24c269	0xeda3c6e0
+	0x3d3c6920	0xb635c806	0xcc205fd1	0xcc273f90
+	0x92f36850	0xc094ef55	0x99e33eee	0x775ea554
+	0xea124752	0x8b006562	0x38bbcb67	0xd2008955
+	0x14ee116b	0x964f634c	0x5bcf34e0	0x58c28331
+	0x01cbb9c6	0x56df247b	0x8fe03e91	0x9646fe0f
+	0x650d96fa	0xe8c99df2	0x7458f4fa	0x76491d87
+	0xaa84a44a	0x48b0ad6a	0xc0d8c6d1	0xd8ad81e9
+	0x65b48f71	0xd254bde2	0x2f34f225	0x4eccf8b9
+	0x25fa9135	0x3662dd06	0x17c9a780	0x1996ed2e
+	0xadfd4c99	0x613f14c0	0xd80c9926	0x2ef5e5f5
+	0xb06ec784	0xf7e430e8	0x19e9ef08	0xe3ac3c51
+	0x78cb1177	0xaf255850	0xcaa6fb41	0x735550b7
+	0x67eb076e	0xf17b3cb4	0xaa8edd18	0x4aa229c7
+	0x74492140	0x11d71f59	0x8c275a99	0xcb217ed7
+	0xa4273190	0x7d9dab3c	0x934381c2	0xdd6176e6
+	0xdece7df1	0x7ab6bea8	0x303bd86b	0xa9170bfd
+	0xc8412491	0x84da3ea1	0xd57e97f7	0xbe0bb91f
+	0x9efc9c8a	0x1c09a4a5	0x83cf52a3	0xd342460d
+	0xd302163d	0xd05c637b	0x1ebb7326	0x79ba20d9
+	0xc944f204	0x18a78657	0x89542294	0xf7bd975d
+	0x5fd7140b	0xbfc96910	0xdc339353	0x952f97d7
+	0x253d4006	0x99fdff85	0x8116afcc	0x328ac2a3
+	0x4410871b	0x2dfe8e51	0xf45c01a6	0x40217a8a
+	0x0c0d19c1	0xd96351fb	0x3bb0b96e	0x287d0ad7
+	0x5a63c6ea	0x037477b9	0x33ead7f1	0x0183222e
+	0xbd1242cf	0xbce09c86	0xa9efc50a	0xe388da86
+	0xabffd93a	0xcadb61fb	0x94320786	0x36731cf5
+	0x4169fb6c	0x60a3e64d	0x22881d97	0x7eed6b34
+	0xe3e6b7cf	0x011047ef	0x514a380d	0x1063defb
+	0xb5c55e9b	0xf548dcfc	0xaa1d300e	0x5aba83f5
+	0xc02e41b6	0x44925671	0xd7d2129f	0x917539db
+	0x9f5d234c	0x6122338f	0x3f8a847c	0x9e65ba6b
+	0xd28e9f70	0x04e78d83	0xad696012	0x471c8f88
+	0xf42ce5db	0x9f0b9849	0x5db38a8a	0x7fd7d4ca
+	0x244ea3e2	0xf352a9d7	0xa670c8c9	0xab7fca55
+	0xec9c1042	0x625ed8e7	0x31f4ff8b	0xa3a8a576
+	0xec645cff	0x3c971f8c	0x527fdc5d	0x77e4d1cd
+	0xa8746a1d	0xc4b9af0c	0x41d2e8fc	0x62456003
+	0x792138ed	0xe672d51b	0x119befb9	0xfd2b4348
+	0x3b14d25d	0xd36edca6	0xd2f74bdb	0x9ec52dfe
+	0x97b55659	0xee80103c	0x12555012	0x6d4a8def
+	0xf1454d26	0xf5c41569	0x4b6e604f	0x92c0851d
+	0x9f4618c7	0x4e5ad7c9	0x41c7cd36	0xe50a1a4c
+	0x74c5b18a	0x721bddb3	0x8d67f6fe	0x7afdca7e
+	0x0a545134	0x137f4344	0x9e5f2d92	0xafc74bda
+	0x0a18eb99	0xb2718bd1	0x1d9b8d07	0x80232c83
+	0xe962d93a	0xabc0f007	0x204f0def	0xb292a3d5
+	0xdfca18f9	0x34fe2939	0xccb61664	0x419dee6d
+	0x4070f1b7	0x334975c6	0x283a9bd6	0x3dc4a721
+	0xea8bd79c	0xa4401e2e	0xa378d378	0xf03ebd34
+	0x5cd39e42	0x0a4ba860	0x34b26a87	0x9979e96f
+	0x8e872a1d	0xaae3cfc2	0x25876b90	0x8bf1b190
+	0x6864856d	0x4965cab9	0x9c49f4a8	0x7d9efd8d
+	0x313413d0	0x52905c5b	0xd43b4f40	0xb3a1cfe8
+	0xb09d2a80	0x6655a633	0xaee4a3b0	0xdbad5f59
+	0xffa56b65	0xa0bec51f	0x10e511f1	0x3091be0e
+	0xb4899296	0xb6640c3e	0x4b0bfd96	0xbb4c2d9f
+	0x7d6ba4ca	0xe0de7fa7	0x3a7c39c2	0x03d52694
+	0x9af37318	0x0f1f28e1	0x629c5821	0xfb78261e
+	0x34c74091	0xab92d7a7	0x226a753c	0xbdb6aafb
+	0x76c9434c	0xfa167b4d	0x640e7dc7	0x1070355b
+	0x2264b655	0x03ded64e	0x100ff664	0x38d25b67
+	0x6715611f	0xef479b2f	0x8f52b055	0x0789f609
+	0xc84baeec	0x16021597	0xc6d924ee	0x32913130
+	0x8e86b7c9	0x8532fc4b	0x27c9b92c	0xfd9c38f2
+	0x63e8c76b	0x9ba845fa	0xad507144	0x7c1eca93
+	0xaec2e059	0xadf30a5b	0xe9133d92	0x7ef687e7
+	0x5c89bfc9	0x58d8f8a1	0xcd70ad24	0x316ea0a7
+	0x5d0957ef	0x8b630a27	0x2c43bd03	0x7925f21e
+	0x42bb7aa2	0x08bc5d8f	0xcdcb9090	0x417ea6c0
+	0xce5c5f86	0x10112aa8	0x19674618	0x3e3809da
+	0x40c7caf6	0xa0753b11	0x7e718c19	0x50bccb67
+	0xd08e448f	0x5f7cf11a	0xc4fa6c6d	0x9aabb2f8
+	0xdda811c3	0x37b24fd5	0x31fbd13b	0x954355ff
+	0x0a3f8036	0x3cc96699	0xc1d0f52d	0x4e976ed4
+	0xe24ee785	0x3ea3647b	0xc2486a7f	0xe24b8488
+	0xa23f433a	0xd0ec2901	0x079da6cc	0x617282e7
+	0xa65c81dd	0x0651acd5	0x14adbf87	0xb62a352b
+	0x33c9a353	0xbb74a62d	0x97fe7ac7	0x2709dd2f
+	0x1bd03373	0x5fdb088a	0x94b8675a	0xdb3edd44
+	0x378021b1	0xafa448c9	0xedad3e93	0x68bc71c1
+	0xe32f7e72	0x28ad6d83	0x97670184	0x2dfbc275
+	0xc238281f	0xd07c0e6a	0xc3b12738	0xd0af1b0d
+	0xfa161509	0x6af28479	0x6350ddcf	0x5de28d1d
+	0xa2504310	0x1fa39c51	0x41c24f45	0x588cc066
+	0xcc1f3a6d	0x6231cbac	0x2b60a3b7	0xfe35561e
+	0xcf92322f	0x412dce5f	0xf7d5628a	0x4eb7aa88
+	0xd832c865	0x6a97e393	0x1ca8f5aa	0x0fb9d833
+	0x52a134d6	0x11ede00d	0x091040d6	0xbcee0e8e
+	0x3065f06e	0xfed5b966	0x5a304bfa	0xecaba5a4
+	0x71142b74	0x44a849d0	0x7334c493	0xdb5ee797
+	0xe537a453	0x849f4cf0	0x435923ac	0xad3a754d
+	0xa78c3e5b	0xdb062ce7	0x874d85ad	0xc80e3955
+	0x3db9ad97	0xbe5ee26c	0x4627c40b	0x095ffa45
+	0xc2affd98	0x5f4d1325	0x7e4e1cd0	0xf87f1a1d
+	0x5ee40ff9	0x87b4a4db	0x32d4d331	0xc75f8a6b
+	0x79cdb281	0xf7b41e82	0x6e38397a	0x9af320c4
+	0x57da9320	0x154f9f49	0x3451d8b8	0xe3520cd1
+	0xd8df7d66	0x15d80b8a	0xfedf9cd0	0xa86675fc
+	0x7fc8e941	0xf7f21238	0x8966e9a8	0x416da7bd
+	0xc44d7d8f	0xecf21ce0	0x801b2813	0x16545fa6
+	0x3c438b30	0x37200a5f	0xeb8ebb3b	0x6d90077b
+	0x123c3d29	0xef11bccb	0x7b107fd9	0xa4fb179d
+	0x7abc5dfb	0xe4817640	0xd3788477	0xd954d092
+	0xa8b16c03	0x694941a7	0xf499fc7d	0x8d65681c
+	0x8c6016b5	0xce3a995f	0x15ce39df	0x9bd26a97
+	0xfa6c7a38	0xa66670e3	0x0932cac5	0x9a4ebbd3
+	0x4c06bc72	0xb0dcb9c0	0x3598f7cd	0x7557e021
+	0xba16f52e	0x32cd1c62	0x12cfc28d	0x544b3d77
+	0xd780755e	0x340fea59	0xefb9b1ae	0xeada06ae
+	0xaafbc431	0x275071ef	0xe8d19426	0x714a2ba3
+	0x81a7c4a5	0xb5599e4c	0x9637445c	0x4af7df96
+	0x5ffb2f87	0xc0aefa6a	0x30a00ede	0xf8ec4413
+	0x2fb53e35	0x1084dd22	0xc04e8437	0x25197744
+	0xb68a5330	0x1fd2f46b	0xda66de26	0xd0db8e5f
+	0xb782db5a	0x34f4a30a	0x9b249d48	0xb0d081fb
+	0xcc18d9bc	0xe7f0f327	0xd651dee6	0xfa7603b6
+	0x3df72308	0xb6e0bbe3	0x0cea0072	0x2895be61
+	0x30e976de	0x3201e40a	0x9e7421c4	0x7df47822
+	0x82a04ba5	0xf9a16c26	0xd76b42ae	0x5b7f7455
+	0xeda1add5	0x60189560	0x875db6fa	0x1315b3cc
+	0x40c629c9	0xf5033d8b	0x10338d35	0x00f5e8c9
+	0xc15acd41	0xe952cb8e	0xfbf03648	0xfab3a0c6
+	0x3c23ac72	0x8206fe5e	0x831da221	0x67d3676e
+	0x4a64ac61	0x98dc0ccd	0x68ffdd6a	0xa2a0edfe
+	0x534d47a3	0xf79b6154	0x3d2bc073	0x50c2b839
+	0x03932319	0x64342c82	0x92d92fd6	0x9a9ba8db
+	0xefb42d33	0x28d07ff0	0x5db4fdfd	0x39225ab4
+	0x37f24ea5	0xa82e9e1a	0x26c4bd1c	0xcb365ab6
+	0x60553456	0x03efa3b9	0xd7b8d40b	0x4858269c
+	0x0eef7011	0x19d7f85b	0x938e59bd	0x24f33de1
+	0x2d466d05	0x3ac7c2b4	0xbb7af230	0x3ec5069c
+	0x2abe2941	0xf5db8b3f	0x902f1251	0x9a6e0bb7
+	0x1d2cc0cf	0xf65d6e88	0x03365f91	0x3a2ecb53
+	0x4a59e1e9	0x0b252007	0xddd6c5b8	0x1c4d54a2
+	0xc1edf67c	0xb066e206	0x6c8c9894	0xe8426c70
+	0xc9f6ec2b	0x425c161a	0xc585a39a	0x064e4452
+	0x5294148a	0x36c0a919	0xc84d33e9	0x1a5fbdb9
+	0xfaec593d	0xd8d248f3	0x2fb18459	0xcbe7a0ce
+	0xd70e9e1c	0x1afed776	0xecd2959a	0x7d8a5f35
+	0xf1c70be6	0x2650b3c7	0xf0c46fa6	0xbf6bb842
+	0xbf279282	0x4120728c	0x7f6b506a	0x87064748
+	0x0bcbd2a6	0x2757fe8a	0x1db17cec	0x7517ef49
+	0xbec921f1	0x804cb1d9	0xb9217e2e	0xb9ec624c
+	0xcdc5e715	0x30bc1f23	0xaca1b3c0	0xf88bf420
+	0xb5a8ac78	0xe93a9e75	0x0d15ac6c	0x12547703
+	0x57a4e428	0xd1404e52	0x03f6e562	0x168cf122
+	0x08da568d	0xdb96b84f	0x533c183c	0xa9dad7f0
+	0xe2cd7e2b	0xc4162c32	0xbff6345e	0x69307759
+	0x98b07a47	0x08f8219d	0x0d604427	0xc4305cac
+	0x294162b6	0xa15a6c1c	0x04f692ad	0xb8da5cb7
+	0x4839cc8a	0x91488ef3	0x08061887	0xebb839ba
+	0x322ad7d6	0x490ac9ad	0x90ce1d35	0x83bf44d1
+	0x1f988e2b	0x7acf6511	0xfc46e340	0xdb66656f
+	0x9fc8938a	0xbe5afc17	0x7349bf91	0x1c36730c
+	0x3b7f643f	0x06a42553	0x6142e212	0x8fb07289
+	0xc9b53580	0xe927620d	0x0e966437	0x60a4867c
+	0xc93e5e14	0xb5d54cac	0xd1c63103	0x30bbcbec
+	0xbd22bce2	0xf48e5a20	0xab393f90	0x0a265db2
+	0xe4805f5a	0x2d0941ba	0x8a877e27	0x141d94bd
+	0x30ef8a0c	0xfd82b15a	0x36c3c125	0x402c1a1a
+	0x0fa86d0e	0xa195b994	0x4c309653	0xbea4fdd4
+	0xfad010e5	0xb7e3cb7e	0xd5bce9ec	0x0e366de0
+	0xc6515a96	0x68ca6f82	0x73720af2	0x5d9a3be5
+	0x16ea24de	0xeac200df	0x7ebb1e44	0x486bba64
+	0xa8c68872	0x53008115	0x968633d8	0x7b9b000c
+	0x0c1aff43	0xd83875a2	0xcc3e1339	0xf1cf9b3f
+	0x5da5f6d7	0xfd5570be	0x649ee5c3	0x0ad7de54
+	0xe4d4c568	0x04d8521d	0x322df607	0x5d0f20df
+	0xf4a8d682	0xed3275eb	0xf8159013	0x3a7ee2d7
+	0x706bb51e	0xac4fa1d1	0xf7245344	0xb5a352f5
+	0xaf84a731	0x073beb18	0x05679002	0x414a0323
+	0x9eb69396	0x9e57bbb4	0xf5765947	0xcf85bf53
+	0x90cb7bff	0x9aca4c64	0xd87c65dd	0x717cb65a
+	0x6598389e	0x75938c29	0x3a73f234	0x265cb77a
+	0x9fdf49f2	0xf6c60084	0x175963d1	0x27f213af
+	0x0d5a9f2d	0x22593c74	0xce596562	0xb41196c7
+	0x707d6606	0x8d953238	0x61481d28	0x2fe1e9c1
+	0x5dd2d437	0x65f8fa05	0x56732403	0xb989d4f7
+	0x917ea769	0xd4bebdbc	0x13d39d92	0xfecf7388
+	0x6f3597d2	0x76147a5d	0x01c51f65	0x0ad769e0
+	0xd96c281d	0x9983cce8	0x4d2bde45	0x151ea741
+	0x99d61b62	0x0d603ea8	0xfc85937d	0x427d7b10
+	0xe8d15c97	0x13ef1e0b	0xf4f79fef	0x62b76eb7
+	0x21d65b86	0x6a72263c	0x166b02b1	0x36b13710
+	0x2ff6fbac	0x1b853cad	0xbdc93294	0x6f5f6b9d
+	0x06ce7ded	0x49120f04	0xc9e09c7b	0x3d049a07
+	0xb606d45b	0x12dcecb4	0xb50b3b8a	0x7c198d4d
+	0xfa0f1618	0xac7968b2	0x33eb7dcb	0x07dee874
+	0xcb4d9d96	0x66eeb30b	0xef1ebf3a	0x06c281b9
+	0x44bfdd0b	0xbe4936c8	0xff238c39	0xc87beaf2
+	0x7b3b032b	0x87e37014	0x09a4a1c5	0x2a60e1c8
+	0x1bd67945	0xbec8a12e	0xf1837ea6	0x7a9a4aff
+	0x7b0a9211	0x00e8551a	0x1f2b699d	0x9b38fdea
+	0x43c58686	0x1d98737d	0x0f772a4d	0x7660c66c
+	0x3bbda6b4	0x42df1fb1	0xc1c5aeec	0xe5f13157
+	0x2926d26c	0x57ab1234	0x47626eb8	0x8b55b251
+	0xf0a4dccd	0x6dc4e449	0x1573d97f	0x26f463c7
+	0x9a87f877	0x19b07943	0xeafc72a2	0x9723ada4
+	0xab30aacc	0x1d6df35c	0xd1c891ba	0xe93769c8
+	0xa58ba86a	0x5d13eca7	0x29d0280e	0x1fb8c99e
+	0x5caaff2c	0x7cbcbdc9	0x64d2cfe7	0x7586ca1b
+	0xdb371ead	0xc5c037b8	0x80bf52bf	0x3d3c3ad2
+	0x6b7e425c	0x113409d4	0xa5e1aa77	0x521317f1
+	0xcc3b148e	0x7b99be8e	0x8362b991	0xc7bf1ee7
+	0xdfbb5ddd	0x94edb425	0xf0ae4ea6	0x846a026b
+	0xeb8befdc	0x54090284	0xdbb22f07	0x8aa40ce0
+	0x23fe1e1c	0x47f383c6	0x3e7e8fce	0x0e533a25
+	0x8a31b356	0x6dfc7274	0x2de64ecf	0x941161f9
+	0x85e6296d	0x25d0f616	0x0a818f46	0x8ba2e331
+	0x3193d742	0x4aad0883	0xa97e4d89	0x6c380aa3
+	0x7cf9f824	0xf4b0880d	0x2105a500	0x4b21aa24
+	0x85a37c7a	0x8b6e6ee0	0xc6907e75	0xd289dd04
+	0x97859658	0x056e5df8	0xbc67be96	0xaf5b7d8d
+	0x70426841	0xe8910781	0x3a2a84cc	0x029a8b16
+	0x4a01f9fc	0x56fc8172	0xa406a272	0x86c6995e
+	0x902a269c	0x3e2f46c8	0xdf628cad	0xe9c917ca
+	0xb2fc0fcb	0x1433c09f	0x720db1ee	0x66372abc
+	0x29e7b946	0xa8f8ae57	0x94a75fb4	0xc5b89188
+	0x46aff2c6	0xcaef0590	0x5c3c8f11	0x1f89b174
+	0x1536e302	0x456b8947	0xc7449e60	0xabbf6bbd
+	0xd7dfa543	0x243a10c0	0x58f4ec8b	0x0bd3f346
+	0x6a7f8d3d	0x9615e391	0x63810f52	0x4679abe7
+	0x35060bdb	0x90518f32	0xef673aec	0x3b119149
+	0xe61749bf	0x105aae24	0x134e5f31	0x7773bf1e
+	0xa317a8d3	0x136a9ed5	0x18d9b8c5	0x2d9ef922
+	0xc09d3a82	0x2fd65aec	0x3c9c867c	0xe13d79f4
+	0xe8f10d6d	0x367416b9	0x08cad24c	0x634ded9c
+	0xff5e5041	0xb95a0220	0x90941112	0xad6a6fae
+	0xabbd6a68	0xda8df1bf	0x64ecab3e	0xad163a7a
+	0x4bbf0be2	0x92dd3c4d	0x14e405c7	0x7259c058
+	0xa925a2f9	0xbe6343c3	0xde477a54	0xbe622353
+	0x68e87028	0xa0e7bef2	0x907c2d70	0x0717cb56
+	0x60162a22	0x9279454f	0xb4bc4db0	0x1444a062
+	0x46ff359c	0x7ef881b2	0x882bc1b5	0x5a5547f9
+	0x9d288801	0xe5e9be86	0x8c22d3fe	0x2c9cfd0a
+	0x1fad5fda	0x23ba1388	0xd0af08a0	0x4f218b5d
+	0x372a023f	0x498a3301	0x37d89270	0xc7f3f2d0
+	0x5bcd1b11	0x3cae2643	0xdb8a3acf	0x760b973d
+	0xea3476ac	0x09795d63	0x3a926c84	0xf668f08f
+	0x962aa19b	0x4a9d8ba5	0x852ec947	0xe742453a
+	0x86436cda	0x12632bd6	0xffd300d7	0xce3e66c0
+	0x1d8fbfa7	0x74dabeee	0x629376c8	0x8dde3458
+	0xbe7f9e18	0x1eef9cec	0x7f026424	0x919e5361
+	0x009daea3	0x66d9ac59	0xbfa09c85	0x86f78426
+	0xd82a9ca9	0x94cec335	0xdbef6b65	0x0507c651
+	0xbb34d330	0x17bc84e0	0xaee42b53	0xcb41b21a
+	0x25b45399	0xea54d11c	0x57e7b13a	0xaec71577
+	0x18fa957c	0xda47937a	0x7d0c72a6	0x2ce6856f
+	0x5d513cd1	0x48560d4b	0xd0505c7e	0x75060791
+	0x8ad85f16	0x8ee29517	0x029144f3	0xe811ce82
+	0x49790987	0x890a38a8	0x4959350d	0x85120232
+	0xc40d93f6	0x8419b3f7	0x3d1938d1	0xa0fb7571
+	0xf2a22104	0xa8eb4259	0xe6b69491	0x6367059c
+	0xc5f4d067	0xfbb99b36	0xe22a7fac	0x1aa67168
+	0x4e352bcd	0xc02b9339	0x4dcbef0e	0xe72cb674
+	0xe91e6e6a	0x6ded5223	0xe8520b54	0x842d4e80
+	0x4caf72dd	0x40eeb737	0x7c213234	0xa169be4b
+	0x6a88b02a	0xce540994	0x280cb749	0xa5c13190
+	0x0067bae1	0x26254839	0xcab1fc69	0x630b961c
+	0x8275487d	0xbb8b20f3	0x757de8f1	0xb652de6e
+	0xfa845694	0x4aeb9f77	0xf477f13b	0x18f42a8c
+	0xfd6a12f9	0xa97f9a78	0x8b56105c	0x765f4381
+	0x1ac648d9	0xea0b5b90	0x526bf787	0xe975c883
+	0x8cf8c115	0xa9d20628	0x3f663ddc	0x6e1bb3f6
+	0xf3852873	0xb8296270	0x7e3c9e91	0x45e48c69
+	0xb1a875b1	0xe4a210ed	0xe2552d56	0xa78fad94
+	0x970ff726	0x95a4beea	0xf9d5505d	0xfc87ac3c
+	0x179da815	0xee295504	0xecccdf4e	0xfe9786a2
+	0x9536ae1a	0xc130fc4e	0x10e2738e	0x27aa298e
+	0x96613a99	0xcd92fe53	0x8e7b1cb7	0xd708df30
+	0xd45c95eb	0x34d09a74	0xa746f62d	0xbfcbceb3
+	0x925da8da	0x0da0aa75	0xe44f0e36	0x06982962
+	0xe5471959	0x56a37f36	0x7a5c58f5	0x82386903
+	0xa7e18350	0x3c00ad76	0x33affdea	0xa179837a
+	0xfcafe757	0xd0b14701	0x7f9ec58a	0x878407f0
+	0x229afe49	0x2d6345bf	0xe3399a6f	0xf01376fe
+	0x689f49eb	0x816b6543	0x4c6735cc	0xe596f327
+	0xca2604df	0xf089bd37	0x2b554507	0xb830a463
+	0x2fef8d6c	0x9b70f1dd	0xae54c418	0x899e40a5
+	0x85ecfe99	0x8016eb0a	0xefd1150b	0x2e3b2e2b
+	0x8d9a2ce2	0x94af20ef	0x96d16f0e	0xa1644c8f
+	0x7181fca0	0x79eab0b8	0x10c0e6ff	0xfef780c8
+	0x54202790	0x470e8daa	0x2e63a9b4	0xd3e91716
+	0xd435d270	0xe63f7af3	0x2eb78830	0xf4c6f669
+	0x27240ae4	0xe6206d76	0xae9639c5	0x9299d54b
+	0xb8bcbf88	0xa2b90455	0xc94aeb91	0x5b23387a
+	0x18434a0d	0xcd8562b4	0x787d88c1	0xa00161e5
+	0xc5a526e2	0xa4ac9832	0x377cdd34	0x7bd3e6b5
+	0x9b19c204	0x208d76d4	0xc22dba4d	0x7c72c839
+	0x4aa16eba	0x1dfbcdfd	0x824f3395	0x560b6ffb
+	0x9cdce848	0x925b6be9	0x37649256	0xe1e06b14
+	0x34ba53b1	0xa81b7478	0x9ae2578a	0xab07c5ef
+	0x496f97f1	0x40ba5c08	0xd34fb442	0xdbccf108
+	0x24211f41	0x9a3c6829	0x1ea2c1c3	0xb3545a48
+	0x967a5e54	0xaf506484	0x6cec3593	0xc1bc8d22
+	0x35142a18	0x8352db87	0x18a9c31d	0x900c54e3
+	0x0e07f4e7	0x8fa7248f	0x80c2af22	0x115c188d
+	0x14d68800	0xcfac8e36	0x777cb6a5	0xc1f2879d
+	0x23fc81b6	0x2c864c6c	0x0e8dfe68	0x451fd26a
+	0x4b65b016	0xe3a5141f	0x8323b451	0x62e5cdba
+	0xec14db6f	0xc8de546a	0xe29e8674	0x187681a4
+	0x31d91dd6	0xbf21549f	0xb670f1f9	0x2accef94
+	0xd9255c53	0x1ff2b607	0x69dcef61	0x5806864f
+	0x736d774f	0x44701bb2	0x6007ce5f	0xcbcc4c13
+	0xfb7ef6bb	0x6f2ea43d	0x791bad8d	0x6c0e4c02
+	0x600853e7	0x95258757	0x4aaf3143	0x4ffbee3a
+	0x166847a5	0x1b5b21e8	0x3d56cf37	0xc11e2fa8
+	0x7df56f7d	0x4f193858	0x36da7870	0xe29ae1ab
+	0x2571f278	0x7d81f452	0x37ed737d	0xe4d109d5
+	0x8b0d7bf5	0xdd8fae7c	0x1691cb26	0x94bf321f
+	0x8aad839c	0xafe85792	0x694eb2c8	0x8a256274
+	0x48dd295a	0xd07e2d18	0x031b5e4c	0xe9059897
+	0xf98cfd9a	0xe46dd735	0x1185fea1	0xa4123e79
+	0x5f123825	0x54b6b92c	0x32cf6a3e	0x3ab5bb75
+	0x18cb657c	0x0971a1bd	0x70aefd2b	0xfa48beae
+	0xd6a57c5b	0x289ffd4f	0x9feb0a93	0x3e19add2
+	0xe99862e3	0xf0db195a	0xa28af96f	0x9a22b6d1
+	0x077800de	0x74687d2f	0x77bf648b	0xb0e6b32b
+	0xfc91951c	0x0b30916f	0x6bb88661	0x7e99e24e
+	0xb35ab07f	0xdcb43d79	0x578ff682	0x5d8e242b
+	0xe5643628	0x3b84abc9	0xeac7cd6d	0xe811eb8b
+	0xae728ed5	0x0235b55f	0xa0b6d2e5	0xca735341
+	0x4bb6eed1	0x3a0336f5	0xdc365965	0xe159015d
+	0x89e52c09	0xc3d9429e	0x4638e951	0xdfad21b8
+	0x0650f1cb	0x61b2df08	0x0bca3a7b	0x58def8bf
+	0xf9be3645	0x475c2308	0x4f3808f9	0x472a95d5
+	0x9f557c1e	0xb6427b22	0xa5edbb0a	0x8a0787b1
+	0xda40c48d	0x445e50ac	0x8c01527b	0x21dc6254
+	0x14bfaee0	0xeca3a219	0x0e2dbdf6	0x6ab66c33
+	0xbd20d715	0xb65e8e67	0xec888c3e	0x5023fbeb
+	0xad4c82c4	0x5f793ba6	0x28d79a02	0x23948e5b
+	0x6f1503e1	0x37604f55	0xa6bcdbd2	0x998bc834
+	0x8f372c52	0xdfe4110f	0xad098b4d	0x3d49720e
+	0xa229229e	0xc2c0cf38	0xbe32eafe	0xe992cae8
+	0xe19c55ff	0xfb38fc31	0xcaf2c5be	0x3a61f1aa
+	0xea316472	0x3973d416	0xd047814d	0x5f86de99
+	0x09f5d09c	0x220c0773	0x93c04b91	0x99f3099f
+	0x5fd0948c	0x8abc9565	0x70818172	0x7dab758a
+	0x50415032	0x77bb8a97	0x527c0cfe	0xb9c3b837
+	0x105822e9	0xe286154b	0x1c00f912	0xfe7825c8
+	0x9b76bd3c	0x0af6a65b	0x23215707	0x8836d3c4
+	0xf44ce91d	0x417b6212	0x8f28ec23	0x3f0f597f
+	0x2caaa865	0xd7ff95c7	0x4d4d4458	0x732a75b7
+	0x1d3031c4	0xf8ad5064	0xda73dc99	0x431864af
+	0x38d7bbd5	0x332a2d0c	0x347e68ea	0xbfe2ecf2
+	0x74f6ee17	0x7cdf983a	0xef7dd066	0x1262bdc0
+	0xa7efbccd	0xf3ba76b8	0x3815f62f	0xa1fe8170
+	0x52897deb	0x20f8dc2e	0x5a8953f4	0x8fcc182b
+	0xf6d4dad0	0xfe7fa13a	0x1778ee2f	0x2f289b50
+	0xd9f69db2	0x32d125b0	0xa3ca42a3	0x3075c1d2
+	0x59e7b61c	0xa734845b	0xf183a080	0x9530fa32
+	0x6c59a39e	0x420410e1	0x9f76df13	0xdda0a047
+	0x0073a389	0xe55e57bf	0x926c3ba1	0xa9a94122
+	0xa1283d02	0x74f1e874	0x332b8e81	0x812f3e9e
+	0x81577778	0x30d86799	0xec4960ff	0xd446557a
+	0x49f05905	0xb9fef70a	0x30d403dc	0x6a4498d4
+	0xdc1a7e15	0x445bb9a5	0x1455ba4c	0x9d4a37a4
+	0xeec57bb1	0x34ac00e0	0x7127c2f7	0x44b5a260
+	0x9c71f1f8	0xada2be3d	0xe1cec205	0xc163f099
+	0xe0dca849	0x86ab7f72	0x5c6f4c92	0x93b0eb07
+	0x7ec203f2	0xcc399989	0x75bb2533	0x89ec7a1c
+	0x118371b3	0x7497d553	0x03f2d03b	0x7e7b4d81
+	0x478b1cb4	0xe4801e36	0x808d7527	0xbc1d3ea0
+	0xb297b06f	0xa579d810	0xf07aea4f	0x9e6dd0ef
+	0xad0240bb	0xfd5b94d1	0x0f8037fa	0x944d3fff
+	0xc6fc7d3b	0x4c9761f3	0x68440387	0xc0496074
+	0x32cd1609	0xd67b2de6	0x700adfc9	0x2d284f80
+	0xcc5393b6	0x32d83e64	0x2ac02cc4	0xb759a6bd
+	0x9d8a2f64	0x2ef1b8d8	0x0f574410	0x4cb81db6
+	0x922af2e1	0x56231889	0xf4353d11	0x6d6e9050
+	0x4523c317	0x229d9291	0xbc16016d	0xf1381dff
+	0x84f6e1b7	0xc7378275	0x7045561c	0xd4736ef9
+	0xb863b8bf	0x902bfe68	0xb0811fda	0x9df8d9b8
+	0x6ad9c691	0x4cdf381d	0x68be4e7d	0xd03f2cec
+	0x8166ecf6	0xdcf45f29	0xfbbc6dd0	0x791cf886
+	0x3639c902	0x1f1dab00	0x1abb48ce	0x9f2f4d79
+	0x992b2df2	0x44e8ae22	0x7fa777d4	0x62f1a754
+	0x57448154	0x662948e3	0xe50c5f0f	0x83adfbc2
+	0x669f3fd4	0xf4bf4a87	0x0a1b01ce	0xef6471b2
+	0x49778a6e	0xe470e785	0x5fb3cb5a	0x9767dad7
+	0x04c4f262	0x9cc1944a	0x8bf5062a	0xd316b454
+	0xbed231df	0x9f9e1984	0x915c06ce	0xbfee9689
+	0x6d1b7d27	0xeadc62e0	0x85fe6b06	0x97a92ce4
+	0x879344a7	0x8ce19261	0x48508a42	0x7f63ec53
+	0x05de4fea	0xef725c06	0x23c17065	0xa8c4ab97
+	0x8e304029	0xf25c4857	0x3ddbaa04	0xfd325479
+	0xd6eb3fd0	0x25f8ed38	0x67e70d61	0xe894d72a
+	0x5fc7779a	0xa862b7e4	0x27a93aee	0xa3c8807f
+	0x1dcd0622	0xb90b336c	0x7b89617c	0x300bea80
+	0xbbfb1898	0xd61dee74	0x80ce1142	0x4829c4e9
+	0xbe50282b	0x41a5ed8e	0x27150e7e	0x86f18198
+	0xa9bf6e31	0xe4f36079	0xa5c241ab	0x61ab2326
+	0xbf7be24b	0x4c87e8a8	0x170a4d05	0x05941c41
+	0xd0ea7712	0x505b8ad5	0x33ab4e89	0x334ea7de
+	0x32119057	0xfbaeb5e7	0xd00a75b6	0x8e467276
+	0x8260a778	0xbf2d6a39	0x139ef440	0xa7b44a0b
+	0xca0a2442	0xbfd7790e	0x353f6026	0xa418156a
+	0xabc15fad	0x365ca72a	0xb9c5f379	0xeeb91216
+	0xae8a7e67	0xff621bc6	0x5f6767b4	0x703e08f5
+	0xa91b4d87	0xcbbeed4d	0x0f7aeb4f	0x7d7b88a8
+	0x3144ff32	0xbbde4be4	0x1a9af3b1	0x218b80f4
+	0x000342ef	0x0752f7e6	0x98ccb7bc	0x58fb806f
+	0x32b3a302	0x67435abd	0x7462e773	0x3cbbb910
+	0x391c6346	0x939e79b3	0x28cde352	0xbfa8866b
+	0x8a4dba83	0x14dcb04c	0xf2f9f462	0x5fdf6d07
+	0xf0a8de85	0x63046ef4	0xbc007be0	0xa5014d97
+	0xb966e6e8	0x31308a90	0xd5fc5756	0xdd21483d
+	0x4ab980b8	0x48b8708b	0xdcdb9363	0x9188fcc3
+	0x790c58d6	0x2c1e2cc3	0xcc621f2a	0x4c36fbc2
+	0x739f934e	0xf666cf77	0x5082421a	0xbe98a7d6
+	0x722fb2d0	0xb8bd4af7	0x371c6eb4	0x13141930
+	0x73320cd1	0x2085f28f	0x49dafcb8	0xe5627dce
+	0xcf40e9f5	0x279fb8b1	0x61775564	0xf9751e18
+	0xc9a50230	0x54aead9c	0xf295e9c1	0x5edfcc4a
+	0x965eee7d	0xd4a0fb0f	0xbc1c32bc	0xd63bb4aa
+	0x9f5e3cfd	0xf0f1f047	0x1a1bb313	0x762a6e08
+	0xd1e112fc	0xd07737cc	0xeb85de60	0xa81adb27
+	0xf56a8804	0x927e4a07	0xa03f4c55	0xa75c038c
+	0x4aa72639	0x856b7a63	0x8e0b5b09	0x0b650c8e
+	0xdce67a0a	0xb093aaa4	0xee9c495a	0x397c9b72
+	0x00201e9a	0x0f3654d1	0x44303f3e	0xdc708b39
+	0xab8bd5d9	0x1ed28dbb	0x1e91ab78	0x9357e946
+	0x0591f394	0x3f174806	0x7e5363e2	0x10d73f05
+	0xb18094b7	0x5c0cd26b	0xffa4c529	0x914ded6b
+	0x247a68f8	0xec8a2133	0xe368fe87	0xf18c26fb
+	0x8e442fff	0x39ea6ecc	0x9743be65	0xcac5d694
+	0x24c4bcbe	0x2edee596	0xbd052bd1	0x70adaca0
+	0x30c241a2	0x62b3f644	0x061f6b48	0x2fb91a6f
+	0xc92df68d	0x73d41f19	0x3c18cae5	0xa04fbf36
+	0x0ee5c645	0xee7973d9	0x7eee5dec	0xf11a3fc3
+	0x06acd8c5	0x8ea5b050	0x652b3270	0x0f1e47fd
+	0x82ba02c9	0xba7622be	0x9031734e	0x29e08f94
+	0xe204f41c	0x95d57dde	0xc178791d	0xb4af2e68
+	0xaf7e788a	0x17925d4b	0xdf417ecf	0x9193b6b0
+	0x1ca32a5a	0x767d122a	0x0718eea6	0x1da6aaa8
+	0x30497c08	0x32a6b264	0x7e0d781c	0x040010c3
+	0xda2d6754	0xa3f9bb71	0x40ca8c26	0xea70e76a
+	0xc90365e0	0xe6102f4b	0x728b93fa	0x8c9b288e
+	0x9acf17a7	0xe1164350	0xf0103d84	0x3201abfd
+	0x28e96191	0xa85a975f	0xfd89e4c5	0x33b397e3
+	0x688bf58e	0x69d4bfc9	0x38d9d38d	0x395c61c4
+	0x46b33a28	0x59d8b30d	0x5fcd406a	0x36dcf494
+	0x3e6e1d45	0xdad47f30	0xe23d6c85	0x05c0f5da
+	0xb2eb2523	0x617f5209	0xc4bd50ef	0x9a40d446
+	0xf6706e43	0x8a41211b	0x141e5cdd	0xe5f4763d
+	0xaadf5d59	0x34ecff99	0x4ebc45d5	0xdb4b1578
+	0x33ec85da	0x67ee6b0f	0xc5789628	0xf67e6663
+	0x1b19bab3	0x58620745	0x3e1929b3	0xa3ef35c1
+	0x6233b038	0x928c9bde	0xfc1a74d9	0xe290e8e8
+	0x2dc2b3ce	0x13533357	0x865397bf	0x551b56cb
+	0xce7a7ef5	0xa3788428	0x7eeb6f73	0x7537f3ea
+	0xfdd77af1	0x35343358	0xca248bee	0xf3726d8b
+	0xbd027aff	0x43cbbd5d	0x4627b904	0xdcaed70a
+	0x3f17a9df	0xbf2158fa	0x6953f389	0xb2bb4bcc
+	0xfd56ff25	0x482cb729	0xa7c7d9cf	0x029c2e69
+	0x4f3605c6	0x4f148ef9	0x29b6c0a4	0x2f556532
+	0x6a298f9e	0x25945e4b	0x0a464d76	0x1fabd60a
+	0x7f4c7d56	0x3b138677	0xa4d89ab4	0x5ccd85fb
+	0x8c39f4e2	0xe77261b0	0xc3f3e6e5	0xdbf298ac
+	0xe18fa767	0x89b19fed	0x65f32b00	0x042d50cf
+	0x769900d8	0xf2c8dcdc	0xcddd6fa8	0x125af4db
+	0xff808661	0xfd607112	0xcd9b7d51	0x65189811
+	0x125c6011	0xec46f0b4	0xabbaa61a	0x35e5ab40
+	0x0b66213e	0x8f0b1471	0x54a54816	0xfd70f393
+	0x8efe0bcd	0x9727c46b	0x3f91f2b7	0x60d13926
+	0xbf074154	0x5ff54e1b	0x9b7aace3	0x5507beb8
+	0xb54dd8b3	0x4bd21318	0xc16e8f89	0x75aef7e7
+	0x42520647	0x71cc3319	0xe9bcb41a	0xd0b016fd
+	0x98fbdf6d	0xb124aff6	0x81b21f00	0xf5025987
+	0x629e381b	0x3d971a74	0x2d20c3e7	0x1f990330
+	0x9798ef1a	0xab4c06cd	0x9bcdbde3	0xf58187f1
+	0x5349ee2d	0x9befe269	0x92512cb4	0x7a90a7fa
+	0xc8bcb803	0x7213b43d	0xc54b82ec	0x57395c83
+	0x80483b13	0x9d9e3384	0xfe9e19f5	0xbd75b346
+	0x445ecce5	0xf549df86	0x43abdfdb	0x579c16ea
+	0x2d838513	0xd8c030a2	0x0f26f21f	0x86dd65c7
+	0xa56f5587	0xaae5e6eb	0xff6cae9a	0x2b6a5082
+	0xe8cfea92	0x426e5b12	0xeb6b5e11	0xef748b88
+	0xa7c52873	0x884b93ae	0xeec07e07	0x7f822b08
+	0xc88c1c51	0x2fdfbfcb	0xde46bd4f	0xc0f72284
+	0xe5afdd1e	0xc831d473	0xf3b02b32	0x610530cb
+	0xdc57ebbe	0x0789b8b2	0xb1e004fb	0x98954e9f
+	0x56e27413	0x840b2e16	0x53af5141	0x05cc609c
+	0xa5652e91	0x982ae5ed	0x757c75a6	0xd31d253f
+	0xbff9ff00	0xf7dedf5d	0xb7a15617	0x514aff52
+	0x4c04184b	0x9e7a31e9	0x31485a41	0xead3407e
+	0x50e1cecf	0x601f296f	0x85d903dd	0x54308603
+	0x877a8cb0	0xa0f0949a	0x3cd9dc5e	0xa62b3ca1
+	0x79db50f1	0xa49b5ffc	0x7afa975c	0x1007d484
+	0x7700bc31	0x2b8431ed	0x8f1c2ccb	0xd26b396d
+	0xe6a2abb7	0x64f78fa3	0xace8788a	0x8ba6f357
+	0x01cb3b57	0x60ea304f	0x44bc28f1	0x2e16fa08
+	0x4e9a2b65	0x89c2a14c	0xc521051c	0x2bee04b1
+	0x10c0bb27	0x1ab75887	0xd819df0d	0x0b21368b
+	0xe924da32	0x628af541	0x6d6eb08c	0x0a418b53
+	0xac19e5cc	0xb2704fba	0x759df88a	0x76df6bdd
+	0xb2ed3a34	0xf52af31a	0x44f6fb45	0x8885764b
+	0x6397d609	0xa5803b66	0xbd3c3ee9	0xfd91fc62
+	0xa92ad0e7	0x4075feea	0x1b73b846	0x1840a431
+	0xc23ea4d5	0xf4be4c2e	0xe45fb99d	0xbc96c887
+	0xa707bacf	0x40adabb9	0x2b1a8d08	0x05d5f8e2
+	0x94578102	0xd032c431	0xe633de5d	0x9fa46925
+	0xe4f78f93	0x09b5a508	0x68797087	0x75a4cf41
+	0x68f34d2c	0xbc9d676a	0x939c00ec	0xdba51b90
+	0x9bdab841	0x96c079a3	0x4c926224	0x046417a3
+	0xa3090fe1	0xe2395840	0xff85d732	0x16eb0672
+	0x1f2b4c36	0x10432695	0xea175319	0xac6b4fec
+	0x22abeca3	0xaf42dfef	0xed67fef5	0x556b9185
+	0x79318868	0x013082bf	0x882b4c74	0x17232518
+	0x5ab0b8a9	0x565064e0	0x61bde558	0xc2f9f27d
+	0x08d57cec	0xe02dd914	0x7e9a5972	0x856d0859
+	0xe5488341	0xa0dd98de	0xa3c88a46	0x22c7bbce
+	0x5924efc2	0xd15e2a36	0xfbabdd34	0x19e4838e
+	0x1510c1f3	0x70f94986	0xde0505a6	0xe34df2cd
+	0x39bc87ba	0xb0b6a36a	0x35bfd415	0x8b71c8e8
+	0x074bf788	0xc7322d81	0xdfe4c9d3	0x14e4a913
+	0x1d559696	0xc539cac3	0x91b6dd2b	0xc198e564
+	0xc762ea2b	0x8b7f7f5e	0x3928468f	0xbf5e5a5a
+	0xe5151ed4	0xf7abecf6	0x379c3bde	0x81ca5b6f
+	0x6da09c5a	0x361d2f8e	0x7b38f326	0x0906a7ab
+	0x1afafd4d	0x24fbcb5f	0xf02ed4a9	0xad2f8a2c
+	0xccac956a	0x9a906a0d	0x55742842	0x08a7d782
+	0x250e3581	0xd2328a15	0xcf943410	0x0c90aabb
+	0x158fb11b	0xfb4c7ec3	0x51784a26	0x00b63b38
+	0xfa9d20fe	0x6c3f5841	0x91204efe	0x70471fcb
+	0xd7158a2c	0x09dc4685	0xefa8ef7e	0xd9e5c6b1
+	0xfcc7c7f8	0x8f6fc8c1	0x4217f7a4	0x41e6d387
+	0x26b12c91	0xe547e92f	0xe0a03d8d	0xe37b6003
+	0xccd60f64	0x43a58a44	0x83ab597a	0x084b5c9a
+	0x73f053c8	0x7590140d	0xad7d7fb7	0x9f1c8d60
+	0x2f96ec1e	0xd73ceb36	0x18c9db5a	0xb144c70f
+	0x745ca3d3	0x4b6a2615	0x09b7a09e	0x5c9e6f60
+	0x60431f35	0x13fb02c4	0x6a6a2aee	0x0052d8e0
+	0x3f120080	0xef5b3906	0xaf071511	0x981b4584
+	0x7e21a2a6	0xe6fd2e96	0x67f460e0	0xc2f8f323
+	0x22538f24	0x042f44e3	0xf271ed0e	0xa6fd7882
+	0x0a469528	0xd1997489	0xa005e740	0x1b37ed35
+	0xc546aa6b	0x5defa5e7	0x0df0e3b1	0x20de0573
+	0xafdaf222	0x4efa11c4	0x129e4d10	0xa5b36477
+	0x3cfd82fa	0x143f99ce	0x6277d132	0x41bc6588
+	0xa96832b8	0x8e448a33	0x64d475b3	0x0d03dde7
+	0xb9b7274a	0x7c43c3bd	0xcd7dea08	0x64f213a9
+	0x4e5e3b17	0x59f0ccf5	0x149d6092	0xb3da7ff0
+	0xe4bc1141	0xd6e3ad13	0x309b6d3f	0xa8bc2b2f
+	0xfe8c49c8	0xfcb93795	0xa21e6218	0xfa789db6
+	0xeda40d1b	0x8a571368	0xb20288ba	0x8f590d4b
+	0xe2d350ee	0x55de37b7	0xa6b1545e	0xd34397bf
+	0x2ca3cb72	0xc858a6e2	0xf18eb4f0	0x13162f7c
+	0x3c73d583	0xf42f4f2d	0x2190c996	0x5842aeb4
+	0x0fb8fac9	0x91835b21	0x768e94b3	0x0ee40fa7
+	0x0bb4abf4	0x5d634b0a	0xf05614d1	0x8421bf96
+	0xadc9bc41	0xc3c25730	0xead6783d	0x6b26a26e
+	0xa5654315	0xddfdbd76	0x0e9efb4b	0x2523aeec
+	0x0ded6345	0x9e745201	0xd74941e6	0xde1a8779
+	0x8369587e	0xfe9e7ff8	0x7361da63	0x3b392b9d
+	0x294fda91	0xd2bb0865	0x2584a967	0x2eaa63af
+	0xf24d9e7e	0x02f0b739	0xe78adfad	0x803d1b65
+	0x4fe08993	0xbbb8b6fd	0xee720db4	0xb9bc4da7
+	0x05d068c8	0x3e76a5a6	0x7ff1a6ca	0x2370982e
+	0xeea006ab	0x39482f79	0x9887af2c	0xdba4de83
+	0x9ecd4cfc	0x6978eaaf	0x1c910836	0x90abaf2f
+	0x66fbbb3b	0xdba1eb1b	0x7c5d8640	0x10e2b54a
+	0xbc9bae3b	0x4ab513c1	0xc3916328	0x923f610d
+	0x8a55ff24	0x3efba683	0x25f2c4be	0x58e5374c
+	0xd307e907	0x48ea462a	0x2dd7509e	0x870a5dcf
+	0x08012046	0x3cd12b1d	0x6a47b79b	0x4113492b
+	0x652e973c	0x9249d11d	0xcd2703e1	0x2fbe5959
+	0xbe07c47e	0x441a0496	0xe7a6c7e5	0xf7cbd2ac
+	0x44fca640	0xb264be8a	0x87b3042a	0xd347d1fd
+	0x8dbb5347	0x60a9b650	0xa5fa99b3	0x6745855a
+	0xea6324e2	0x380882cc	0x7d220119	0x344e1982
+	0x906ade50	0x24e90f8c	0x490d112f	0xf111aa2e
+	0xb08f13b7	0x8e1d7590	0xe9370ed1	0x62eb39e0
+	0x35927fb1	0x829a40cb	0x0806336a	0xbaa04062
+	0x9939850a	0x0869ac12	0x54b03562	0xa4f5c614
+	0x392c62cd	0x7c23d63c	0x85fd1195	0xb7ed5546
+	0x686e1f4f	0x55edcc7f	0x3094818f	0x2537a964
+	0x664d5c0a	0xe80e1cbf	0x7948cae1	0x23c64375
+	0xd418e137	0x78c3642e	0xecc9da92	0x79aa46e8
+	0x59be9660	0x88058e58	0xc3c31420	0x378a39d2
+	0xad44e929	0xb3131130	0x11a55e4e	0xf34bec26
+	0xdb1bdb5b	0x0e9c986c	0x21472aad	0xd10cb0ad
+	0xcfa7f425	0x8cc73d4c	0x935ad802	0x8a8252a8
+	0x4ef3c4af	0xa9ea8d4d	0x8b8d2327	0x49221fa4
+	0xb7a9a150	0xe635f856	0x37df5260	0x8d47a600
+	0x736ff5bc	0xfe702551	0x622bb56c	0xafdf67b9
+	0x394d0c63	0x1895e424	0x788eedd0	0xb8e7f6f6
+	0x57a690b6	0x7f37de59	0x5f4cf3e0	0x1211b1b4
+	0x9fd82e02	0x5c21f2af	0xdc016937	0x5c3a60f6
+	0xf7729837	0x77758003	0xc470bc58	0xed2622e4
+	0x88ba5184	0x18418beb	0x75659944	0x790ee40c
+	0xd7db7e2e	0xb263b2ed	0xae90b658	0xe31faa45
+	0x084b7b2b	0xe2817433	0x5fb477b6	0x05b99337
+	0x20897d5a	0xdd5349f3	0xb6de2ced	0x0ad02021
+	0x667a11e2	0x45fa8d58	0x7d9f7b52	0x982be1bd
+	0x80d9b10f	0x1311fdbe	0xfd0c3612	0x77d03036
+	0x9fc16296	0x60e450a5	0x329af69a	0x2fcd48be
+	0x9c61579a	0x398ee2e5	0x18d52ae0	0x2e6d52bb
+	0x0b1d391e	0x17d677a3	0xa56308dd	0xca961ae8
+	0xaa08b85d	0x230a894e	0xfd1bb53c	0x40f070c6
+	0xe536f86d	0xace6b686	0xb2ee8045	0x3ca0ca1c
+	0xdc14297a	0x016e04bd	0xd298babf	0x1775685c
+	0x25eeee81	0xeabf3996	0xdbac64c0	0xb644a8b1
+	0x1d034410	0xee2f26f5	0x646f8804	0x0a219178
+	0x88b774f5	0xb7757133	0x3ed44b66	0xbafb3535
+	0x7f28dad2	0xd9be6e16	0xc1ee44aa	0x6473e8c3
+	0xce6a8d51	0x58996952	0x74d779f5	0x7a332ec1
+	0x93b1ae48	0x072f4696	0x91a59962	0xd1b4650d
+	0xdf7bc203	0x5a1e01e1	0x0cc1c256	0x5f038178
+	0x316dfbd6	0x6b6066c8	0x88d3c99d	0xf4593234
+	0x7744e3e1	0xb986b226	0x122c5c78	0x98c304b6
+	0x8d8e5248	0x258ad65d	0x887d2b33	0xddbcf246
+	0x1079b709	0x69e5336c	0xaebbc436	0x021f40cd
+	0x1c5c888f	0xadf4031e	0x773c6a1f	0xca6a4b54
+	0x678a48b0	0xa83766e2	0xb51fc797	0x9378d2ff
+	0x24617e89	0x63b6f24b	0xdff10c7e	0xd7899313
+	0xa117de13	0x9ce9fe62	0x93568bd0	0x79525643
+	0xe73d74ca	0x6fa05775	0x16532ef4	0xf158297c
+	0x43d5b180	0xb3713768	0x42f5c74c	0x360674db
+	0xd503b365	0x85f2e190	0xe02701bd	0xc4f72047
+	0x9f0e8c3b	0xcb74c0d9	0x26a763f3	0xf052587f
+	0x1e6382a6	0x98957c55	0xf84848a6	0xc899e8a1
+	0x8baf0ead	0x04efc2de	0xfe51e034	0x31838b1b
+	0xfc488265	0x54c21df4	0x3a1a09df	0xc3197a60
+	0xf82505eb	0x01b09802	0xde6c5986	0xfa64e8e7
+	0xd46b602b	0xd4b8abae	0xfd712f8c	0x374a2d31
+	0x10bdfd5d	0x8b2c581c	0x11b999ce	0x93cb6b25
+	0x03f83c15	0x5e2ca149	0x3cf835ac	0x8952786d
+	0xde9aa5f2	0xc64c816f	0xcd56d134	0x6341ba5d
+	0x48f8b46d	0xa6465fc8	0xf17c3199	0xf8945500
+	0x52591640	0x126a5e9b	0xe4ef95ce	0x092ce906
+	0x60feea4d	0x3ed8d81b	0xe13b4585	0x3699ea3f
+	0x3c99d800	0xfb45a4c6	0x80b9af7b	0xdc1a8f13
+	0x42793d11	0xf5b680b5	0x17443c44	0x339178cf
+	0xe9122d87	0x60c79f06	0x2516b5c1	0x5225d594
+	0xeb2dcf80	0xcfe02eda	0x7719eab8	0xf4beaf16
+	0xce7d36ad	0x49a95435	0xacee9deb	0xc79cd246
+	0x8ed659c5	0x66894b11	0xaedd26b6	0x9ce7d941
+	0x294b5830	0x105962ad	0xeb5b34e6	0x31917645
+	0x122c34fa	0xc7c82bd1	0x6ee4ea9a	0xe2fe7f27
+	0xb1fd4c3d	0x702e9bff	0x7788ddba	0xbd3d942a
+	0x75159d12	0x6aaec1ca	0xc3b4abcd	0x37a69572
+	0x1fce87c2	0x01fbc543	0xacdd6775	0x2c7890d1
+	0xbc1563c1	0x413dd754	0x5b7970d0	0xfef5b1ca
+	0x8079af11	0xd551824a	0x5409896f	0x54e0be68
+	0x8bcd30ff	0xc8375f42	0x30c06a2f	0x779c737d
+	0x32d3e66b	0x7bd05d0f	0xb9c67b23	0xf273695e
+	0x13528262	0xe4a790e9	0x0805aaea	0x3907f7c9
+	0xd7abc54a	0xa4cc51a4	0xf49493f0	0x472aa285
+	0x4dbed2c4	0x4864edaf	0xa46700a8	0xd7542f0c
+	0x7c0ae286	0x951dd824	0x3c73e333	0x52eb49b3
+	0x70516de8	0x7efae010	0xfe0bb650	0x786eb317
+	0x43fb3ab7	0x4c86f7b0	0xab0c578a	0x59787f35
+	0x719e2575	0xe5c919b4	0x26076c48	0xf4c5cee0
+	0xa832e1c0	0xe0e719e9	0xeb978049	0xfde5093b
+	0xe1c5a86f	0xc0ca654b	0x07140b4e	0xcee94a0c
+	0x684f8c9c	0x0dc722ef	0x3f81b654	0x24f6b59e
+	0xc9366802	0x07317ae5	0xb07bc322	0xa68d61a8
+	0xfba88f10	0xdb077c88	0x2e2d4cae	0xf950f615
+	0x0eb4b1d4	0xcc43df94	0x7f76068d	0x9998b11a
+	0xd8c4c734	0x2444116b	0x6f387abf	0x402ba3a7
+	0xb343b091	0xbf1ed457	0x0325a66e	0xac685f81
+	0x3b13da49	0x71bfeadc	0xb706c3cf	0xc18367a7
+	0x74e05a7b	0xf15ce88f	0xb7effab8	0x8e79599b
+	0x758e0fd3	0xec60aff7	0xa36b3584	0x978555f1
+	0xf03e26ce	0x05b7f39f	0x0f44d1e7	0xdb301d27
+	0x2734c001	0x1ba4bb02	0xbed0c57b	0xbbb082d7
+	0xa0f5c163	0x7b081aff	0x8f6020f0	0xb2363b33
+	0x50fba5d4	0x8f862718	0xcfd4080e	0x31881dec
+	0xcea35f4d	0x0ce550bc	0x968bcd16	0x701e96b4
+	0x70104a77	0xd1381316	0xfa0b6bf6	0xd0800a1f
+	0x30dd27e3	0x53396989	0x58066430	0x6fe20758
+	0xe4776597	0x85bc8231	0x6f013aa1	0x8b0f1a6c
+	0x1d41e906	0xd476acb1	0x1f50f428	0x61ebc0b6
+	0x78c6389b	0xc70b922e	0x4d4c6fc5	0x97931134
+	0x9d157c3c	0x053d63fa	0x4ee4dbe3	0x351ccb06
+	0xdabfd086	0x6759fab0	0x277549b8	0x7a265b93
+	0x35d1a141	0x972395a4	0xffd773c2	0x9ba52eb4
+	0x41574c66	0xd4195554	0x49ccaa22	0xfe228bd6
+	0x6977e1af	0x100a9948	0xb6c9667a	0x276c9a27
+	0x169ba199	0x395986bc	0xa7079788	0x40b6deb8
+	0xe74c106a	0x620f202d	0x32b4ee73	0xe7916e7a
+	0xc949eba9	0xbf56f13f	0xa76139d6	0xfdca38ac
+	0x7a295c2f	0xebdb2f5f	0x452694f2	0x6183f044
+	0x0f29f26c	0x41760fa1	0xbf1fd689	0xd3055c3b
+	0x1edb2239	0x5e9aa007	0x193c6ca9	0xa5f75684
+	0x281732f2	0x99308898	0x78c4f631	0x6673d2bf
+	0x62b8251d	0x4a466036	0x9641449d	0x138ce807
+	0x3d637a7f	0x7d09bdf2	0x433bad7c	0x71bad217
+	0xfb587029	0xa9a436f5	0x0e24623e	0x0aa852a8
+	0xe86564a8	0xcdb686e4	0x65c48b10	0x2973caa6
+	0x62d4e121	0x4b0835ae	0xa17bd769	0xac4a2db1
+	0xf185166c	0x50f2fdfc	0xc39f14a0	0x5ef9dace
+	0x0e70ecb6	0xfa577352	0xf944271a	0x4219017f
+	0x4023cd16	0xcb999031	0x3435d9a3	0x376a38d8
+	0xf9c5020b	0xf607d1b3	0x20899f9c	0xd4a0c8ba
+	0xbb8afd18	0x4171935c	0xd949dd4c	0x2e33f6fb
+	0x02af555a	0x0c2cbed6	0xba680cc6	0x07f0e58a
+	0x88750bfa	0xdad6ce37	0x90e0e1be	0xfde50439
+	0x714c6da7	0x52d79397	0x73f2dd50	0x0ec2df57
+	0x38f609ac	0x6978ea5f	0x2b4f2a8e	0x977c5d83
+	0x40f4581e	0x9c862f00	0x0ec9124f	0xcec0f275
+	0x0830a2bc	0x1e620c5e	0x1c99889d	0x88fa02b2
+	0x12cdc5c6	0xd1308d75	0x68c1c312	0x4dfee754
+	0x8c7637a4	0xacd042fd	0xf9fa1e7c	0xa3fe1a74
+	0xbabca0bd	0xf2c4f9cf	0xedb898d7	0xbf68ed2a
+	0x88f88f66	0xba7eb154	0x8b657afb	0x8cdefdac
+	0xa2becf86	0xcdcbe0d7	0x9481c98b	0xb194eca7
+	0x2a0a02d4	0xfb00d895	0xcfae192c	0x304180f0
+	0xa82bcede	0x3f9407eb	0x6f616505	0xf2679357
+	0xc74ff05e	0xa42d33b6	0x6d131a74	0x46837c8f
+	0x618d8b8e	0xae3fdf80	0x5ac56792	0xe8204095
+	0x7fe678de	0x0aabe905	0xe23966fb	0xdfc3ae2f
+	0xbfba369d	0xd362d0ad	0xe4d00bd1	0x36468346
+	0x142ed1df	0xc97cad2c	0xe5c1035d	0xf6c78877
+	0xe00295da	0x3be8b0dc	0xb59cef1a	0xe8ed05c6
+	0x514ea1ef	0xf7633df2	0xb7e10bca	0x44cc343e
+	0xdb5ebaed	0xe10b3589	0x60fd04b2	0xfacbfe1e
+	0x93a1e9b8	0xee694238	0xd693b0b3	0x2812a260
+	0x08db3159	0x59ca9d4b	0x4153cc57	0xf0ecf932
+	0x438d4d1a	0x52c232d7	0xdf6d7a95	0x5b6f5092
+	0x81e98659	0x8f9a196b	0x99acb238	0x19f97546
+	0xba51ca3c	0x6c65e249	0xf45c7ad8	0x05bb02f7
+	0x3ef3a052	0x61ea6df3	0x3d28d168	0x085c370f
+	0xc2da1e98	0x7808a8c7	0x25be8a1b	0x89aaaf9c
+	0xb66b1fa7	0x3f734eef	0xa845dc71	0xf66dc75e
+	0x8a3fd539	0x7b0edfcb	0x93a439f3	0x835fd4cd
+	0xef222958	0x476a8df5	0x41622b4d	0x8bf6f823
+	0xd2c72644	0xb28c401a	0x2e56d5ef	0xb7762140
+	0x6640e607	0x825f8ab6	0xeb42e497	0x8c92adee
+	0xf680d2a1	0xc2f96614	0x014f5191	0x47becd6b
+	0xe2d06126	0xd5e04451	0xa03771d6	0x459e86bf
+	0x72d63346	0x908e8298	0xebc918c1	0x6deecf70
+	0x8bc4f332	0x79a31a01	0x2114b2df	0x0180e3e3
+	0xe2c91e71	0x0811ee5f	0x2c016723	0x069618e4
+	0xb3b08ed9	0x1d9fa7bc	0x657733f2	0x86e610f3
+	0x2621f0b7	0xd9f6651b	0xbefc2f7d	0x76a0b063
+	0x604856fd	0x94a4ec8f	0xd7472d38	0x64b07478
+	0xa4b4d499	0x43235f22	0x5319c88f	0x911e6372
+	0x89ff9bf8	0x54455299	0x7b3e4e02	0x2335f31d
+	0xf10efd89	0x652e4e5e	0x8a9325c3	0x4064cb40
+	0x59ea7010	0x97fbfdcc	0x7836d7cc	0x88d05455
+	0xf6a719e0	0xe6841411	0xd54f36de	0x2cb4c908
+	0xbf87b0f0	0x6b1bfb7f	0x4dd2f56d	0x699aa41f
+	0xb330eb1a	0xe1f021f6	0x65be482a	0xd48dc3cf
+	0xedc98989	0xc38a4452	0xc4d0144a	0x812fab34
+	0xbf112bd0	0xc9d10e16	0x6600a506	0x87955675
+	0xbf65cf7e	0xd0d0e097	0x789c3540	0x1b6c3b27
+	0xa17f9e2a	0x0d47f6c5	0x08ba8430	0x0ea5ab50
+	0xe6875bff	0x745f6e88	0xe91a037b	0x9da767c1
+	0x4673b150	0xbe14d919	0x3164e3d0	0xab5d0c2c
+	0x33a0c5c8	0x67436862	0x0f043a50	0xb48a4fdf
+	0xf2bebb0f	0xfc4df25a	0xd31c6354	0x21b41071
+	0x2f29814c	0x2eb38275	0x7d7b4493	0x3235611e
+	0x65e3106e	0x4fbcf4c7	0xe131e9d3	0x44b7028c
+	0xf424c38a	0x709a1171	0x0bf1900f	0x5228b316
+	0xda000118	0x61d8b278	0x0f4df4b4	0xdf948e72
+	0x289dbff5	0xef421693	0x0e9b89cf	0x809db1a4
+	0xde5468fd	0x937b068d	0xfd94e40f	0x397379be
+	0x9d41a041	0xc01b0889	0xd4fcd1e8	0x0456e57f
+	0xe91261fe	0x32ba801b	0x7edc2183	0xde70ea6b
+	0x3a81dd35	0x4641b2c0	0x016e7025	0x1c164cab
+	0x8430aace	0xa14e3de9	0xbeedfaf4	0xd5416157
+	0x89212bc3	0x8f517277	0x64dc0c28	0x051c353c
+	0x052f38fd	0xb4b9c162	0x087db1bf	0x384e2051
+	0x8012f360	0x31a94aeb	0xfdc99124	0x3cd37d7c
+	0x34067dc0	0xd4a35bfc	0x1fe16dde	0xd1f99248
+	0x5a9cec00	0x25a73f12	0x861daf34	0x956456b0
+	0xf042d8df	0x0b23f39c	0xf3dcf643	0x9ba5ce10
+	0xbac25abc	0xb8c56204	0x10db5a6e	0x8de89772
+	0x1e968309	0x4a478676	0x119afb50	0x988930b9
+	0x6119d759	0x51788bfc	0x1d61e721	0x3d480f67
+	0x66075802	0x45eb1829	0x118b4be5	0x7efeea7c
+	0xba49b891	0x4dd11852	0xf71b4788	0x99c2f05e
+	0xbd28303e	0x5ee62804	0x1b072acc	0x2d017ce9
+	0xc33294a8	0x57312d2c	0xfd67b2b0	0xbb18b0bf
+	0x2ec80198	0x26175f00	0x35255b65	0x516f5a38
+	0x0890895a	0xd965ce68	0xbd651309	0xf4eb8906
+	0x7e07e61d	0x7e9ef0f9	0x42865474	0xfeb2a58a
+	0xd7c2f2c5	0x1641fd75	0xa24be73d	0xca6e52f5
+	0x40cac5d6	0x24fee627	0xe56c185d	0x29cfe810
+	0x871b030f	0x3b139120	0x19f07175	0x230b1346
+	0x46d300da	0x04d6348a	0x9edc107e	0xeefed616
+	0x673a9e51	0x2daa84b6	0xa19fcd37	0xdecc2c69
+	0x3a683f29	0x17770c30	0xb5395aca	0xf8a977ee
+	0xfa920726	0x7ccd7850	0xc259807c	0x46f03a5e
+	0xb5049f0a	0x09a23cad	0x96208471	0xac73f67c
+	0x91555dac	0x2eda61f6	0x11997b88	0xf82227f5
+	0x333f3844	0xbbe6b077	0x9fa39297	0xa9731383
+	0x3a6e781f	0xc0d3f568	0xf97d2c47	0x84831be6
+	0xc4b64556	0xf9a8de4f	0x19eb50d8	0x72e5a15e
+	0x054a8fd2	0xc1c6345e	0xc0f7b580	0x9704a4a4
+	0xc4226ac9	0xc4ea548e	0xd513e3f5	0xd6af08f6
+	0x831ed495	0x01e6c528	0x1a54b048	0x96dd6e66
+	0x47988fff	0x188566a1	0x8e1313e1	0x5a7f71da
+	0xd3967f1d	0x7690d3b6	0x2f8f2fb0	0x6f6251d2
+	0x4c8aad64	0x02e2fa38	0x85287186	0x14a660ac
+	0x76d76c09	0x1cdd99e0	0x9469a4c1	0x2e627afd
+	0xb3c2e2ee	0x96ccf8e9	0x71d2baca	0xbc6e3480
+	0xf2aac857	0x937f744b	0x0aef9370	0x29ab7ff8
+	0x2d7df775	0x89a4880e	0x40b33115	0x1681969b
+	0x38f87c90	0x58d99e75	0xe0bdcf8d	0x0748a43b
+	0x815cc6fd	0xab02e1fb	0xa556d9c4	0x28045ce9
+	0x92cfd9e4	0x53c48e36	0x10e2102b	0x14bdbdad
+	0x072e7bfa	0x05f11cb6	0x647faaed	0x817802b7
+	0x37514080	0x34e1952c	0x2f97aa78	0x67e5480d
+	0x41c23454	0xb674bf64	0xf1059ebd	0x05bf0d65
+	0x8cea89fe	0xe4c80026	0x19c6c2ce	0xc7ba0a80
+	0x72361b09	0x40442dc7	0x0ea61783	0x0ae238b2
+	0xfd189442	0xc777a400	0x407c0ba0	0x0068c8f4
+	0xbdc3758c	0xccd5a384	0x78c17a8a	0xd9cace15
+	0x0b0cc384	0x4def636a	0xc9ac6e70	0x0b47f099
+	0xec8e3fd6	0x56de8792	0x613589e8	0x3625caae
+	0x54c9ba96	0x61af1ee3	0x22c13793	0x2bb28eb7
+	0xda0bf41c	0x37818fdf	0x66d06085	0x6ed9a2ea
+	0xbd2f6197	0xe019fef9	0x58b35249	0xf7c471d2
+	0xe08ee8c3	0xc0e4f4f8	0x2222e0bf	0x939049a3
+	0x0f81527c	0x6e9d9062	0xb98e6ab9	0xe131178f
+	0x9df0684a	0xfe4b3755	0xe29cc274	0xebbb906d
+	0x5c1ff361	0xf6f785ac	0x925c1ffe	0xbe66b7e7
+	0x341ce7cf	0x86b9e13b	0x3cde9717	0x528413e9
+	0x47017637	0x8fbdb425	0x75bade38	0xaaca2a42
+	0xc2cc87fd	0x341d3b6f	0x810374f7	0x539d08ca
+	0x370a9899	0x13c63028	0xf6121e3a	0x1b6b6379
+	0xe54543e7	0xd6c28f9c	0x92cad6e7	0x0c7805df
+	0xa74ec04c	0x0220c53e	0x02bf9983	0x67b30801
+	0xcfac9bdb	0x30ad34b1	0x623e6398	0xf72dff83
+	0x6d6fed19	0xf62750ba	0x3238cd67	0x520b85f3
+	0x814273a7	0x62249749	0x805a6f0f	0xe38b536d
+	0x41e5a937	0xa93cf20e	0xa751645b	0x8b3e9866
+	0x30967b99	0x3601f932	0xe3ff9f11	0xc4f80f52
+	0x79431f0a	0x6231aac1	0xc62affa6	0x460653a1
+	0x76e31119	0x06034ef6	0x1c69c3ee	0x93d7c70b
+	0x72090aa9	0xc6e716b4	0x694be9b7	0xe2824b39
+	0x669ac02d	0x443fbcab	0x1401440c	0x9e39be06
+	0xf0e38a3a	0x01e81eb2	0x2f04f9fc	0xf8b9e3cb
+	0x997f336e	0x276f6a76	0x4ad5de0b	0x4f1d43c9
+	0xa0de062b	0xbedbcc1e	0x490e9ef0	0x3b9c1a9b
+	0x1df97641	0x90a7dece	0x54b793c3	0x0ace3e2c
+	0x06858b88	0x9474b6ef	0xbbc9955d	0xd882fc18
+	0xb2c19d95	0xa2979c3b	0x2b87a2a0	0x25ab6e6b
+	0x9744f6df	0x8a58cd8c	0x299a4009	0xaf51abcd
+	0xf568b3ae	0x5ef83c60	0x491ed983	0xd3b384bf
+	0xfc42e31f	0x908aaedd	0xaaea2da9	0x62f5607a
+	0x3925938c	0x69432bc0	0xb94c3fd1	0xfa6e119c
+	0xf004de98	0xf26dc0f6	0x58ffc4ca	0x1e215ba3
+	0x77f52343	0xd9930eb4	0x84ff5f85	0xe357c135
+	0x7ca48937	0x45acab8b	0xeb8cb3a7	0x79697bd9
+	0x7aa4e063	0xc275dd65	0x9fce5cb8	0xfdea246f
+	0x8bf8ca24	0x8b61b9c4	0x6a000d59	0x383d33f7
+	0x89727da8	0xb6359382	0xf22d9f92	0xba35a48d
+	0xe8b29b52	0xee2ceb3e	0xb2fc82e2	0x8f343501
+	0x86312bd0	0xad483690	0x751629f5	0xb67a2e3c
+	0xd076ad22	0xc01b43d7	0x2f4f9e6a	0x08b72eb6
+	0x8db81d53	0x4e14b531	0x058c3ab5	0x81b3fbbd
+	0x334ebfc6	0xd0c30788	0x9efef6c7	0x9d468836
+	0xcf54f32f	0x18100d0f	0x75d013a9	0x872ca0a6
+	0x48b656df	0x856d0f88	0x726d5762	0xb1b2dc0d
+	0x49c7039f	0x2b9a468c	0x37f2cda8	0x62d964f0
+	0xc50299b2	0xbe5f6cac	0x67899dfc	0x96ee110f
+	0x7a00c5b8	0x9e9cdfcd	0x0b713ae1	0x06835e3c
+	0xd243476d	0x5b140c30	0x65d5bdaa	0xd6bb4f4a
+	0x1fde9ee1	0x12fd8800	0xd7a7c764	0x0fcca914
+	0x8bd85200	0x40957099	0xe27b21a7	0x46a7fd6b
+	0x0c16e600	0x4385aeee	0x157ada11	0xa750f2ae
+	0xcb37c17a	0x1246d3d1	0x0b8cf308	0xa4a006c6
+	0xa8649968	0x1e07eaad	0xe257f62b	0x966e3ab6
+	0x424bd346	0x9a3b57b6	0xc5a443e4	0xb839b41f
+	0x5ff5721d	0x78844fe7	0x210ef7ef	0x408c4278
+	0x1892d6a9	0x9c3f0954	0x8d607ffc	0xc4cf44d7
+	0xe1b650c5	0x4d417fb0	0x90d99753	0xf2fa12c1
+	0x40a80089	0xd8afda76	0x90885dd2	0x1ad599e6
+	0x828bf177	0x9969fafe	0x34232f6d	0x815828c9
+	0xe851cd4f	0x22d909c5	0xd8b4ed0f	0x388ce97d
+	0x651d147b	0x53d51595	0x09dce7cf	0x04a62df5
+	0x10eb3d91	0x634ab2f7	0x707583c8	0x0f1ce97c
+	0x61135a7f	0x14255857	0x17bcef54	0x24591002
+	0x26b42928	0x5bdfcd75	0x04fafa75	0x0b77e81f
+	0x3d149568	0x40074834	0xc9ed3122	0xa00483d1
+	0xd1094f89	0xfc7e9697	0xbdc02fd6	0x5c0dd406
+	0x55b3af34	0x147221f4	0x6a4e4493	0x70b27ba9
+	0xa839c20a	0xb4ca83c6	0x6976e395	0x53823387
+	0x7e7fa8dd	0x62f3eecb	0xe87a5081	0x2d2e5da9
+	0x2dc917a1	0xa840aa15	0x3ae4b7de	0x818020d9
+	0xe27c54d1	0x863b4ea7	0x3d770e0c	0xc913d78b
+	0x22b6ce26	0xa38d471d	0xd86dfbb0	0x43c94bd8
+	0xbb4e34a4	0x737265fb	0x68698195	0x89ec336f
+	0x61e94b6f	0x01661a18	0x3378d7af	0x2abdd82b
+	0xbc68f021	0x010136bc	0x54be683d	0x9600e0f0
+	0x2710a3e4	0x1fc8650a	0xffc41bfc	0x764776e4
+	0xdef736af	0x80a5b3e0	0x6ba97e54	0xdb90b4cf
+	0x33ca5c3a	0x7dffb784	0x82c7bff6	0xb5c67d89
+	0x8b39d097	0x87b0760a	0xe75b7bc8	0x67a40fdc
+	0x2e77c957	0x8e9e397e	0x8c7b8e80	0x8bd64f05
+	0xfc65f423	0x1ee3b99a	0x13d3c9bf	0xb37869d0
+	0x385dda4e	0x03eb3c6a	0xdf1d4a3b	0x0944847f
+	0xdb5d82be	0x6d8954c7	0x8fc3be6e	0x733e2ddf
+	0x561f1d46	0xebf0b439	0x9d1583dc	0x65406edc
+	0xa981414b	0xc57e522e	0xc960f260	0x6b23dc83
+	0x710d10b2	0xab5f0fb0	0x2d724302	0x03acc581
+	0xb7a06490	0xf3e2489e	0xef949571	0xcd054246
+	0x094e6a1f	0x6ed5f8c1	0x7db5c90e	0x2d52f22b
+	0xa0843e2d	0x4c0645df	0xe30eb8b6	0x10701a24
+	0x8adb03e2	0x98d68158	0xc838134b	0x631f2ac7
+	0x6e181502	0x0ebe0e06	0x39baa3e7	0x20d71f40
+	0x212b2283	0x7387444f	0xb6f617a5	0x17b0015e
+	0x390110fc	0x76f888ae	0x94399a20	0x14a05962
+	0x59a68ad8	0x4dec4aa2	0xfed32466	0xac0f4040
+	0xaa67f018	0xabb1afc0	0x96017ce4	0x55c61e4e
+	0xf549b0d4	0x050889f5	0x4d7d29c6	0xa65e7c08
+	0x87cda967	0x8fc571c4	0xac89bcb7	0x84e41f05
+	0x2316e3e4	0xd11c78e0	0xd7519fc5	0x311ae321
+	0x9443b018	0xd2d850b5	0x9df96b70	0x48b39b10
+	0x17afbb5a	0x81a8970e	0xaca67baa	0x76a0b500
+	0x0b9886f2	0x14e5edba	0x5193071e	0x266148b2
+	0x4a91857b	0x97d18119	0xe095541a	0x40f027a4
+	0x42a63a25	0xd47b0a19	0x537ebca4	0x953aac61
+	0xb601a00b	0x93f621bf	0x71ec4f8a	0x9f2a46e5
+	0x11ad282d	0xc2824e65	0x69bd7aab	0xc75c3965
+	0x2d760621	0x66d29d8c	0x669536b3	0x95524faa
+	0x7bbfc249	0xc459d1b6	0xb818eb26	0x14350530
+	0x2c023f4a	0xce54b444	0xc8373dbe	0x187fd195
+	0xb3b898d6	0x4af556e9	0x6b6c5ee5	0xcdd35ec5
+	0x44e2ae62	0x6d57b2b3	0xca4753ec	0x7cbfd888
+	0x9e4dc38e	0xcde55903	0x293d2710	0xd236f84b
+	0x016997aa	0xe415f003	0xf3c9043a	0x3c17d8cf
+	0xab946c5b	0x1492fa88	0xe800dc8c	0x694bf983
+	0x6330ade6	0x73cc7c36	0xb190371a	0x340a333e
+	0xcadb7168	0x46544957	0x161ce821	0xaf5aba0b
+	0x2a483074	0xdc414466	0xff89c2c3	0x6be345e5
+	0xcc6d38ab	0xb7184bee	0x2d3d3014	0xfab468b1
+	0x58769273	0x4cd9b32d	0x9904046a	0x93127753
+	0x6f750d9b	0x1b01b4b7	0xf5a8f0a7	0x06daf1ea
+	0x06688114	0x205f441c	0x807747f3	0xdf29ce48
+	0x9693acd2	0x648c00bd	0xdaf0730e	0xb5705538
+	0x1aef0ba0	0x5a41b185	0xe5ad0226	0x50714598
+	0xa6aaa344	0x849c7e6e	0x3c71f72b	0x4078f3fb
+	0xde8f37c0	0xccfa72b1	0x49606c96	0x49585dea
+	0xad971ab4	0x50208dfe	0xff446e7f	0xfac4de46
+	0x81cd1577	0x3bbf8978	0x5e11789b	0x3e7ce21d
+	0x53f9ecf1	0x22eb632a	0x26b3d386	0x35676803
+	0xa426e362	0x924fabde	0x858f8242	0xa626e03f
+	0x6b265948	0x2f7b1f45	0x1a3757ca	0xd7dfc2f1
+	0xa9324b7b	0x13ffad69	0xeea8f8b4	0xc9acc8b2
+	0xc3913f85	0x74df9857	0xa7743982	0x257c9f59
+	0x87e6f0a6	0x0ad53759	0xdeee3892	0xfc83ab6d
+	0x7f394faa	0xe7000ce0	0x7fdf6667	0xcaea0850
+	0xb51da301	0x2b534d21	0xade4d5d5	0xef584f5d
+	0xe22f4151	0xcc181641	0x7cb60248	0x43c7f754
+	0x0be0cbb0	0x0e1c1ae4	0x9846f0d6	0x5c26632e
+	0xee7f2381	0x37eb79a1	0xf27b2c89	0x45d49782
+	0x7df3e51c	0x838220f1	0x41173453	0x704695e2
+	0x8e697330	0x37860def	0xf5ebc630	0x468095b5
+	0x5222f701	0xebfa262b	0xb8482a3b	0xace9be0c
+	0xb7161f6d	0xc7ad9a9b	0x6e73d814	0x0980ff34
+	0x8efc3ee5	0x470779fa	0xbdd71e46	0x230371cf
+	0x0baad09c	0xcc68ac6e	0x6d2e0c74	0x328c9f08
+	0x6752d432	0xd42288b3	0x1739034f	0x8b80c37e
+	0x6338280a	0xd55a35bd	0x30799d71	0x7af5110b
+	0x17773f78	0x362581f6	0xdfee41dd	0xbfb03d86
+	0xd091d481	0xb6b0af6f	0x2c81daf0	0x049e0706
+	0x317622a7	0xb2b1df89	0xe1cb1376	0x6c9e5e92
+	0x809baf89	0xa6c275be	0xb942a1dd	0x9fe1efce
+	0x5fcf873a	0xfab5e544	0x471617fe	0x00be2ce9
+	0x65f76905	0xd96185d6	0xe7bfed6c	0xb9a24e09
+	0x776d6d5d	0x64ae6e94	0x90da99e5	0x4e12adc7
+	0x2362ce5d	0xa65c09e1	0x7f27fea7	0x8ea78f0d
+	0x7d33fcdd	0x7ece6d71	0xd873c817	0x63df756b
+	0x4215a6f2	0x657d792e	0x9f514868	0x6d19aa19
+	0xf6276b52	0x7a5046d9	0x0e642e24	0xb19ffed9
+	0xefa48aeb	0xd496077a	0x14f6f686	0xb013697f
+	0xbb28a39f	0x0b49c8e9	0x9fa12b7d	0x45ed23c1
+	0x7d5f545b	0x4c5eebc2	0x87457417	0x9912cd28
+	0x16456561	0xdc8bf90a	0x1eb50230	0xc5ca2117
+	0xc76a221e	0x32c46625	0xd718e8cd	0x4f391d4d
+	0x408d6ae1	0x59a1e68d	0xdc2164d0	0x1a27eb34
+	0x1226ab65	0x79b411ad	0x1e288871	0x9f1149b2
+	0x0c291b3b	0x65564605	0xa5577204	0x5d6418a4
+	0x74074f29	0xd475ca11	0xa47167dc	0x1e2a636e
+	0xc667c8ac	0x74ae41dc	0x80b486f9	0xf3e571c9
+	0xf5b58f5f	0x972066f2	0x9ab34e6b	0x36959a1b
+	0xc35b30cb	0x16535e2c	0xf4f343f4	0x3c4ce4c0
+	0x0d23dffb	0x7f5c7ac6	0x4b240af9	0x719656ce
+	0xd13cfc1b	0x5d391014	0x1df24571	0xe60eae06
+	0xe9b8348b	0x84318f32	0xe59b73b9	0xff61511a
+	0xad38aa99	0x9704f905	0xfbc7422f	0x99581ae2
+	0x59d4f702	0x29920e96	0xfd4605e0	0x45d6dd5d
+	0x6a8ae3a3	0x18a754a1	0x162a9f48	0x3d3cadcb
+	0x930114f9	0xc3157003	0x0e69fb18	0x3bef1ddc
+	0x5c75246c	0x7e45b98a	0x4c5d3d8a	0x5c7ba0d2
+	0x576de26f	0xc1717477	0x5289e141	0xed1703cf
+	0x5c541296	0xb4fd3ec2	0x8299b3ff	0x833d1918
+	0xb9c9d6df	0xfb864144	0xc68b2140	0xeef94cb1
+	0x3081ac6d	0x11e679fb	0x28a8d6ee	0x1450fa01
+	0xf2eb7690	0x069f4e2c	0xd82d9e66	0x90d0a134
+	0x94506a6b	0xb156f8e7	0x15d4988e	0x61e838b1
+	0x4050c1c8	0xf5480167	0x6c6b5387	0x882040e1
+	0x1c576822	0x721faf51	0xc62e23f4	0x0a5ce137
+	0x92e71c95	0x03704ca2	0xd4f4ffa7	0x62ce6831
+	0xf75937db	0x6ec41127	0x5a0f6b9d	0x740db083
+	0x17c844ef	0x2ff5f033	0xaa6c4c4b	0x1ba43741
+	0x82d539f3	0x89f8c559	0xe5d7d8b0	0x6cde9f35
+	0xe09dd140	0x752a39c6	0x357ab644	0x6d725123
+	0xd3156805	0x2a667adc	0x8fba9fc0	0x2b95f6a6
+	0x5b445475	0x1b6939dd	0x6d355453	0xd597908e
+	0x1eae67e2	0xbde7e7e4	0xc8b0f418	0xc30b9fd5
+	0x8429be75	0x39fc4443	0x5574e8b3	0x2737caa2
+	0x63f52048	0xd8eba3b2	0xb5d6817d	0x440701e8
+	0x8fa3c203	0x0b14345c	0x0f3de5f2	0x883b0407
+	0xf9a050ac	0x7708b92b	0x3a4e2047	0x6514b530
+	0x316caadf	0xba8f264d	0x2bb4e870	0x5c290444
+	0xb92c8256	0x69e74855	0x3bef0744	0x85074b9b
+	0xcd1cd441	0x65d7aa91	0xa6e6b18e	0x00950ef4
+	0x4b7e155b	0x0f20d1cb	0x66967570	0x4329041c
+	0x2822ef7c	0x5d23d9cd	0x8d9a08eb	0x22ece0fc
+	0xfd70002e	0x6dafb2cc	0x4d6245c5	0x4f922e5e
+	0xae71bfa6	0xd77143b4	0xec36850a	0x1141be49
+	0xeb354327	0xbd2e81c1	0xf1e02b23	0x36e6c56a
+	0x5b00e6ea	0x01523f35	0xdd467c4e	0xe0b68aaf
+	0x5add5b4f	0x8af89711	0xb3a6df1d	0x10d73bbf
+	0x7da50182	0xf7eef4bf	0xac8ab46b	0x9192187f
+	0x9a77b25d	0xa6fb4e3a	0xd974f36b	0x2d5d4287
+	0xfb8c99d5	0x8e09f429	0x87406c64	0x5b568921
+	0xb1f0c18e	0x07127af1	0x2a7e0373	0xfabaaf7f
+	0x0641e396	0x2c13d47b	0x7fc2c3cb	0x9923354b
+	0x0781b144	0x14565ec6	0xeecdcb1c	0x198deed8
+	0x756e2db1	0x9d63f9fa	0x8adad5a9	0xfed7f9a0
+	0x4e7e42a4	0xde606824	0xdd7a7b46	0x5bfdedd5
+	0x9de3bc4f	0x33632d20	0xa46f862a	0x44e7ee86
+	0x7f1dab81	0x04bc42d1	0xcab0836d	0x27a79498
+	0xf0908ee1	0x77bbe9d9	0xd5545f4c	0x96bdf186
+	0x43562be9	0x1aca7e5e	0x10a6afaf	0xe77f4331
+	0xd7a714f9	0x7d69bb8f	0xa6f7c2c6	0x5b47765d
+	0x85cf795d	0xec3bf9f8	0x6120a5a1	0x1221b3dc
+	0xa40eebd7	0x4b1a850f	0xc54b5f45	0x70696a91
+	0x95e4f994	0x68a4e7d7	0xf73610ab	0xbf9a918e
+	0xc296c1b2	0x22c94b51	0x7251446b	0xfa106d69
+	0x3a483b82	0xffbe90a5	0xb5193f29	0x4eab332a
+	0xcb256d5a	0x80a1d4f2	0xd0c82576	0xf206a4b2
+	0xa87c5194	0xeb9794c5	0x1f2de60a	0x03d24a40
+	0x7513f5b8	0x7c9eb6f1	0x310b3fb8	0x44db613b
+	0xe6a87138	0x01c2affb	0x86f7502e	0x4646c069
+	0x760cf456	0xaf1729d5	0x0cda28b0	0x05d25b38
+	0x75775802	0x0aec6066	0x398e862d	0x5cb646f2
+	0x27498e91	0x0d21c41a	0xc28f7d53	0x26b34c20
+	0x0def57d0	0xfbe8f668	0x54aacccf	0x31f671d5
+	0xfeb727ff	0xd1134b18	0x984befab	0xe8018e3f
+	0x5664fca1	0x9b4f89e4	0xa5f9e765	0x1c81abdc
+	0x07c807da	0x3eb61d45	0xd01e03dc	0x81685d21
+	0xa0e0fbce	0x054b75b6	0x7c0d5f19	0xdf75841f
+	0xd30386f4	0x7fbf1c38	0xd335b8ae	0x861b77af
+	0x01c0945b	0x159d55f5	0x658164a7	0x82460382
+	0x3889b1a2	0x69d1df23	0x9db51495	0xab5a40ba
+	0xe8ffb5cc	0x7f97ce27	0x72297780	0x08564c09
+	0x25245263	0xc77ac799	0xf020b6ee	0xa1a43e26
+	0x30a5e09f	0x01f6f829	0x97961644	0x398fb5c0
+	0xff8efc8d	0xaf5973be	0x39d03242	0x1102ccbb
+	0xf41e180f	0xf8b9b39f	0x58827e26	0xc3e85cca
+	0xf117b142	0xb1b72156	0x00fa68d1	0x6bd0cd65
+	0xd7baac93	0x71b6b09a	0xb051efc5	0x1abaca81
+	0xf1ec4198	0xc18d57c2	0xe3f81760	0x446267ea
+	0xd165cd13	0x623770fa	0x46f98309	0x84119b56
+	0x56687c4d	0x9276c444	0x3e1111cf	0x60cc43eb
+	0xca66d039	0x8a721094	0xb78bf506	0x45eadd1f
+	0x6dd24d41	0x4bf63cd0	0x4274755c	0xcb3c9104
+	0x65dd66e6	0xa017ea2b	0x18bcf547	0x54815e68
+	0x5d65b5ab	0xb14f312d	0xf2f888f6	0x367f0867
+	0x7d06617f	0x4cf5660d	0x90331978	0x2358e1b5
+	0xaf55418c	0x9700cb8f	0x04f04ddb	0xad2d66fa
+	0x14ff5f50	0x9ecec2bd	0x9d8e9213	0x3c02ad40
+	0xafad80ba	0x33997a50	0x8c314e5d	0x18485a60
+	0x147cd77d	0xb2e6d561	0xe1d7f391	0x4a774594
+	0xa2b31804	0x1c9573c7	0xade0a878	0x9d325428
+	0xe59a890a	0x4e14d3db	0x98828e72	0x62f061b2
+	0xa34102e0	0xe405b8b7	0xe70eb2b1	0x8305fffa
+	0x15fd4b1b	0x3647130a	0x0fa693fa	0x213bccff
+	0x8be2f93c	0x5fccc005	0x409b798b	0xae31fe47
+	0x7e5a0b87	0xbfaf1412	0xfcba0901	0x2c50e788
+	0xb03c6658	0x5bdc9914	0x461ca4ee	0x7a67fa0d
+	0xe452cdbf	0x3bdaa6f4	0xf05e956b	0xe5af1519
+	0x608afb31	0x04d305f6	0xa7942ddb	0xb42b9fca
+	0xf5377403	0x1a41b1fb	0x729c80aa	0x23b9f813
+	0x5259f61e	0x1dfbc47c	0x49cc1ba4	0x83f36f0a
+	0xa659d988	0x3411d8ba	0x9d283718	0x377cdf0a
+	0x0971775c	0x3301339d	0x15c9e915	0x57961066
+	0xd7a71fc0	0x0e61722d	0x18dde63e	0x88ac866e
+	0xe33c7e5a	0x1e10ee2f	0x1b4ed88f	0x24dab92c
+	0xba3ebd7d	0x045cd9c7	0x38349770	0x19c58bed
+	0xa84e8401	0x005f57e2	0x6c351717	0xdb0bd6f9
+	0xe02a7d13	0xa1c30bfd	0xe820c746	0xbb1b3319
+	0x6ff3592a	0x8d8805f0	0xf7f07017	0x4c445824
+	0x3ab65173	0x31e34226	0x0a64e317	0xea7adb49
+	0xd01b5114	0xe042a694	0xd4659e02	0x5a8a4094
+	0x68c06794	0x7ac9c7f1	0xbb195a3e	0x8c25b1b6
+	0xe61f7da6	0xa7377050	0x800d5805	0x728a3816
+	0x3556e2b1	0x7edad3ad	0x880ccd19	0xf704f716
+	0xa704fdbd	0x6c506715	0xb01c7949	0xe2c853b8
+	0x22d69d3b	0xd979fbce	0x61dbec7d	0x2e24a0f5
+	0xc44c42a1	0xa4371aa7	0x1c921c85	0xe163563f
+	0xdeb9aef6	0xb07a6815	0xc6113b37	0x0977db61
+	0x956a4697	0xd47e14ba	0x3ed9d661	0x2b6b483d
+	0x9ee66746	0xd77dcc87	0xd7b27bed	0xd6fd72c7
+	0x06fdef68	0xb9d02089	0x364995ec	0x201bf111
+	0x8ea2580e	0x831b0b8f	0x879de175	0x6cbff50b
+	0x4905be36	0xe2223f45	0x10c33c9d	0x4819cf52
+	0xfb24288e	0x71bce828	0xdc31a0bc	0x7a1f9638
+	0xe061635f	0x81a3bb35	0x0e7a5f23	0x30ebdea8
+	0xcdb09f35	0xf3a78100	0x014b1c6e	0xe40d0e4f
+	0xb4fd80a3	0xf625ee7d	0x83932d77	0x802a8bf6
+	0xacd62133	0xefa074df	0xfbbc8752	0xd03130c7
+	0x825f6a0d	0x13bc90d0	0x15461b35	0xf65bbcef
+	0x834d860b	0x10b85d8b	0xb0e6a6ba	0x073a2724
+	0x7b36fe04	0x3c5f6c40	0xb7267f96	0x8d41b32c
+	0xd14fa5e5	0xd0f1cefd	0xf16b4378	0x1b30158d
+	0xb8bc4c8a	0xcdd5bcb7	0xf599d6a7	0xae6c497f
+	0xa3295605	0xed018953	0x279e0aca	0xe4130d76
+	0x1346ca12	0x7c99293a	0x6a88d6a7	0x96a8e21b
+	0x4b2dec5d	0xe3a0d997	0x18884dc5	0x16b0c992
+	0xb305cf1c	0x059536a7	0xf9e8dd61	0x35f36076
+	0x411da268	0x0fbd04b7	0xbfc0286b	0x3f43d4a5
+	0x6ff425a7	0x191b9399	0x16955429	0xe7291c9a
+	0x94266d2f	0x0020ea77	0xe97a491b	0x05f3d64b
+	0xe904e7cd	0x1fc996ee	0xb5267321	0x0b045416
+	0xa05b8e9a	0x7e87b890	0x0418e547	0xc7d8381a
+	0xbfe27290	0xf1bf710d	0xf541392c	0x9d731a97
+	0x10d83fd4	0x1142fdd3	0xd45205a3	0x778ff68d
+	0xffe89291	0xef551eee	0x1cd65c9f	0xc0570b59
+	0x9cab6077	0xe382c833	0x2de6e07c	0x4503d1e3
+	0x611d3337	0x0db6912b	0x63e87ba7	0xec4cefef
+	0xc9f68c05	0x5d9f296b	0x668eb313	0x72606184
+	0x5c40431b	0x03883e0f	0x0c5ee3e7	0x9446406b
+	0x74ff15a7	0x2b7b26f3	0xe793f913	0xdbf796eb
+	0x33fb9128	0x5fa6a230	0x57b72dae	0x19a1645f
+	0x758e2f95	0x64bc0874	0xfaad2208	0xb272f8a9
+	0x8a3c1ba2	0x173aa881	0x2eda89f8	0x10be1bbe
+	0x7e6290a6	0xaa5a1c2f	0x2bd0e8c7	0xfd2ab92f
+	0xeb213701	0x643842e7	0x30896c22	0x1d5930c6
+	0x2a63e6ab	0x681be1eb	0x96e99eca	0x16086415
+	0x7adb7562	0xb8162576	0xfaf355f3	0xd62e8194
+	0x7d89824c	0x0d90dc84	0xec6045ed	0x0ec71061
+	0x36bac535	0xe97a4722	0x026e2cc3	0xc2a52ad2
+	0xf0fbdfe0	0x86d47f96	0x38783397	0x13e179ad
+	0x3939cfc6	0xc7a90e66	0xad11c691	0xd310ea0c
+	0x74c6848b	0xedff38b0	0x709e0c0b	0xb7fd3c3e
+	0xa7e61dd6	0x0cf5e31c	0x6c7da0c0	0xbfef7b85
+	0x212613d6	0x619e6170	0x6d664486	0x0aa491f2
+	0xffa6d7d3	0x5c1f2498	0x2909bf7f	0x7dc0d0bf
+	0xae5f6cb7	0x918acaae	0x2da16456	0xc237f9b2
+	0xb550afce	0xc9d12467	0x0e1fb820	0xe9089a77
+	0x7395b303	0xa226ef7a	0xa9763cca	0x16fa1f04
+	0x6ed0a254	0xe79a3e2d	0xbbabcd55	0x40b9f8a9
+	0x4381487f	0x04f4544b	0x492385cc	0x9b30b9f2
+	0xab640975	0xa2dc4c51	0xe11ce677	0x1679489e
+	0xe5d3a517	0x0fed6647	0x2392fae4	0xe658e71b
+	0x273c5243	0x0685982c	0x27c1cf33	0x6275ecd4
+	0xc6ff317e	0x7c4a29a1	0x0b426fcf	0x0991acf1
+	0x9feaa45b	0x1d1ffa07	0xf54687d3	0xb18f5d7e
+	0xdbc422d2	0xf70244c8	0xe5548cea	0x3a0c907f
+	0xdbf45c62	0x59b57e9f	0xa48f5e63	0x5c72e8a6
+	0xb5b47cca	0x8168e20a	0x34b27256	0x9038f6fa
+	0xe0ddd466	0xc2a48c7c	0x960db9c6	0x0f2732cf
+	0x3dcc51d4	0x9391c39e	0x357979a0	0x80e62d2e
+	0xdf3263d6	0x00524093	0xd370fc30	0xce834f90
+	0x7b9186ad	0x0a52f586	0x91f6a338	0xb1c0683d
+	0x19c473a0	0x58175c01	0xe2ddd12b	0x2eff8804
+	0x5edf1891	0x42b13b8a	0xe29cf9cf	0x1a9a57e0
+	0x551ae904	0x611c65d1	0xdfae00a2	0x5709d8a6
+	0xe8e96058	0xaccb2248	0x1329913a	0x3c94a76d
+	0x732eba5b	0xda39f17b	0x3c88c5d5	0x6d07ab0b
+	0xb74969d1	0x75af86cf	0xc8f4e048	0xdaa00f5e
+	0x8702a790	0x674d81bc	0xb4e1ab44	0xc2ea8673
+	0xfbd8ce22	0x14f850e2	0xb580842b	0x7246150c
+	0x3a6dee51	0x0766713a	0x8eed598f	0xa80b43d1
+	0xc2c7917c	0xe2ef5cbd	0x83251950	0xf4079d78
+	0x71f63dc0	0x6da3360f	0x001f8d0a	0x2f135670
+	0xc85d6376	0x6754e59d	0xf53b5205	0xea0b3d07
+	0xad19e39c	0x82408613	0x00c282cf	0x6bdfad45
+	0x62f0ab66	0x770cd75d	0x2ba77a49	0x7233cc6e
+	0xf9c76754	0x36880b84	0xc834c8fc	0xdec5ef03
+	0x968aeb22	0xcffe64df	0x5851070b	0x17f63d5e
+	0x48e7f121	0xc482ec1b	0xabd98aa7	0x5be312a7
+	0x156e01a4	0xd526a4d1	0x8b75c41c	0x441f8ad4
+	0x6ec314c1	0xef1cd01b	0xda6d9713	0x26cac0e4
+	0x836bfd8d	0x433df830	0xe5a42260	0x31422f67
+	0x81a83d78	0x0e3018de	0xad1c722f	0x110471d1
+	0xff047a60	0xf4c77372	0x2e7d944d	0x04ee0afc
+	0x627575af	0x1a3abe82	0x3beff798	0x8f492986
+	0xd20456ca	0x3502f3df	0x3b02e7c3	0x03365dc8
+	0x7705ea0c	0x3633c422	0x65b0b3ec	0x3e9ed973
+	0x750cd309	0xda693bad	0xa890b0fa	0xb40c4dca
+	0xd16afcca	0x49b9b449	0xae166692	0xc79d1384
+	0x9cb9e327	0xa56a7d17	0x3e10ae3a	0x8ec84814
+	0x1f82254a	0x07b889b8	0x7da971f2	0x540ac0cd
+	0xea60e782	0x3bea0849	0xb17dae28	0x50dba88b
+	0xd4df4a4e	0xda155e3f	0x672c95ba	0x1e91da48
+	0xaa6cce17	0x002dbf3c	0x886b0944	0xee556fef
+	0x4937b75f	0x3b5a6976	0xab70332b	0xc6335496
+	0x641b7e15	0x7db46337	0xe7271920	0xc22323c6
+	0x65ad4099	0x7cd99598	0x3ddd7e16	0x6835f314
+	0x145cec8f	0xb2e7a3c3	0x09170052	0x2c34fc34
+	0xabe9c170	0x765f3077	0xdcf265a0	0x95d95aec
+	0xa1485bcc	0xbfb16108	0x01694ecb	0x6bab8f30
+	0xaa4fdcde	0x2844bf83	0x677c7891	0x2b5304e9
+	0x3a2deee5	0x6b8ce685	0xc4adc75d	0xa9698b2b
+	0x7b83712a	0x178eac03	0xa51f95b7	0x1057a7c0
+	0x28fdc9a8	0xbbf9a172	0x6da21335	0x2c0ed8ae
+	0xbb41c417	0x8f2f2f7a	0x2d47a852	0xc5fef121
+	0x07b2f438	0x53ddb4e4	0x297629cc	0x060f4905
+	0x3b4b4b4f	0xcfa9601f	0x29ac502b	0x2ed377f7
+	0xfe6fd814	0x46674670	0x40b07340	0x1594a18d
+	0x3133a783	0x166dcbe4	0x6fdac44a	0x7966e454
+	0xbb31b980	0x64ebaa4b	0x66b8036c	0x6d1a6bc2
+	0xc9943328	0xce5c0b4f	0xc92855e1	0xc988f7b6
+	0x965f1b48	0x88139c7f	0xd7f572a6	0xd8b4ef45
+	0xfc3fb2bd	0x6e7e9728	0x98770466	0xe1ab3558
+	0x9bd99c5a	0xf4a7b8af	0x26961742	0x130a1467
+	0xf67c1237	0xf75ed2fe	0xc8edbf81	0x5d375cc7
+	0x1ca686c5	0x6428a8e6	0xb6a89c96	0x838620b8
+	0xa29ef90e	0xce6cc74d	0xc9a7ba3c	0xb8aaae94
+	0x7e2e7496	0xfe89d0e6	0x886b55d8	0x053559f6
+	0x13788e3f	0x1fe94926	0xe6be2cb0	0xb69bd93d
+	0xe080a734	0xef31884e	0x1b7ee144	0xd3c0e444
+	0x0dbd197c	0xa97c4e40	0x742fb324	0x60777e37
+	0x65a0e07a	0x60e4a524	0xdea92cde	0x9d53a354
+	0x054925d8	0xbed53c15	0x19a56f63	0x8e1d7d0a
+	0x385c0655	0x6127884c	0xd90669c3	0xfd01eb5d
+	0xba5230e8	0x8be4e0af	0x641ac70c	0x9da4bec4
+	0x491b3fdc	0x72088377	0x6fadbb6b	0x1eb3f194
+	0x138f76e6	0x06e5cfa1	0x50e6c02d	0xced3bc9b
+	0x4f3cb822	0xe7c05bef	0xb8939b8c	0x228423bd
+	0x2826da45	0x7c7a4327	0x69ee1772	0x6ce06d42
+	0xdde9f377	0xfd8296f0	0xcacf450b	0xac8a79cc
+	0x2515f4f1	0xb8877606	0xe3c75f15	0x87eefd57
+	0xd5f83e31	0x8ad83ed0	0x645c8379	0xfb2c09b1
+	0x29fa9f1c	0x523070c4	0xbdb3b12c	0x56b5dcde
+	0xf8426a93	0xe4b2c23d	0x3d5b9e33	0x82b25356
+	0xd92445db	0x33022612	0xb8ccdb74	0xa20ca557
+	0x55345b9d	0x8e9c951d	0x97a6866d	0x494c6e01
+	0x70210570	0x5a43c02e	0x6fe89bef	0x2cb5ad9c
+	0xe0ab87e5	0x75adcb6e	0x45405e26	0xa692bf48
+	0x5b609761	0x030a9467	0x40a759b5	0x106bb462
+	0x620a7d75	0xe929da61	0x071bd58e	0xee378d68
+	0x6b08d4d3	0xb8a36917	0x45efd5a4	0x62fa1ee8
+	0x267621c8	0x01fcc95a	0xb313963f	0x881e32d5
+	0xac58d47a	0xe8e98407	0x940144d3	0x9f4fe111
+	0x99c16f87	0xa6f50b4f	0xa9407cbe	0xe1ed1a1f
+	0xf7af2972	0xe3236e66	0x1514a6ef	0xa4838377
+	0xb6b7bb2d	0xe9c12d6f	0xffbc47d4	0x0009e283
+	0xe066bfd9	0x9453acd9	0x3a53516f	0x1565d9e4
+	0x05623966	0x1b1dbdff	0xd1d630e9	0xd0144dfd
+	0xc97ff66f	0x269311de	0x1f9661d8	0xc35a0169
+	0x8b206d41	0xc078f81a	0xe0d268b1	0x612f66ae
+	0xcef1e654	0x9ae0237c	0xa9a6db51	0x2ec4dc13
+	0x31225c9d	0x201ddb16	0xcb8c3092	0x92b5bce7
+	0xa554dd54	0x715c2779	0xaf77d5db	0x0e66d154
+	0x4346695e	0x096b18b3	0x4bfffc37	0xc12f275b
+	0x75be5fa0	0xe0844620	0x8ce45a27	0xbeb23c8a
+	0x038acf17	0xbe750146	0xcb50aa60	0x28b17d7a
+	0xf2c24fae	0xe80da3e4	0x53bda2ba	0x0db14ce5
+	0xd4562d22	0x906e6c6d	0x2228060e	0x7b758425
+	0x5120152e	0x79fab288	0xaa30431e	0xe02aff0d
+	0x11cf0942	0xd6dec434	0xa37c5532	0xdc75fcaa
+	0x6e709ccd	0x0fd6d302	0x9c0cff7b	0xa9ec920c
+	0x4930add6	0x9dc7080b	0xf7e84e66	0xedafc508
+	0xded94db8	0x32848bc3	0xb46e6e41	0xe9aec094
+	0x2c6ed428	0x81998fb9	0xba44962a	0xbd47d39f
+	0x69c5f06a	0x527f64a0	0x3863510e	0xabedb09e
+	0x66ba1af5	0x2f4701a2	0x89619e66	0x2a8213b6
+	0x96b35155	0xe36f9bf1	0x4e4c9831	0x41e29f39
+	0x8a38c10e	0xc6b0b3bc	0xb9a8bbf7	0x1b3feff6
+	0x116cee15	0x7a26aee6	0x8aa5e277	0xe033f839
+	0x03ae9486	0x87feab5c	0x2a76ec0a	0x2c9f5bb7
+	0x979e8365	0xb735d5fd	0xc5b2684c	0x65bec358
+	0x20ed649c	0x6044f3e2	0xe964aaca	0x083c0fc7
+	0x64c6f5ec	0x58c2f1a0	0x7248e733	0xf86633d0
+	0x155e08f1	0xb5105931	0xc3a675f3	0x58beb5c4
+	0xce27bb83	0xc317c8e5	0x08c20bd5	0xb52687ee
+	0xef5115d3	0x4c01fe14	0x031db379	0xcb219aa3
+	0x42ba3a94	0xe51c3809	0xae496040	0xf8a9cd70
+	0xcc5753ae	0x0540afc7	0x2f967c3b	0x7ef7aeac
+	0x4a41f6eb	0x705f7bed	0x556adf2e	0x68b38e05
+	0x86bc6414	0x0dd9c2a7	0x31d0f0bc	0x148062f4
+	0x2ee98f94	0xd62fe807	0x11d37fe3	0x052ecb38
+	0xca75133c	0x2ed8c2c6	0x8e604160	0x392e1fa0
+	0x8544d810	0xbf670aac	0xea63e11f	0x69f8e72e
+	0xe5ea3048	0xf33a1162	0x51def599	0x5aa97dd8
+	0xa7af7df6	0xcf7ac38b	0xfac81bb1	0x5c13e786
+	0xafb6c23b	0xf51f6a22	0xb07484dc	0x476b48a5
+	0x88a4b41a	0xac65199e	0x30206ad2	0xda03b33a
+	0x5c1f02c6	0xc47f63eb	0xf32643e7	0x963d6f51
+	0xa7154c6a	0x927627aa	0xf46ce42a	0x363f40e5
+	0xb4bf67e3	0xe47052d5	0x9e0b47e1	0x6b0fe58b
+	0xa03a9c49	0x5e945cb0	0x6ad3cee7	0x6e5bd7d6
+	0x11acd8c7	0x79545822	0x255b7b5a	0x5f909b17
+	0xafb63f90	0x5a407558	0x47b10cb2	0x510251c2
+	0x7534555e	0x374d4ac8	0xae77ac8d	0x42134d42
+	0x2eadea43	0x3abcc1c0	0xa3281b92	0x7883d25d
+	0x41825437	0x9a5e2c5e	0x805c11b3	0xf2fd6d24
+	0x9e5c2348	0x61cd2c3b	0x4290dcd5	0x906ac92c
+	0x75a98667	0x29a0953f	0xea6f3127	0xcf96cccd
+	0x255aa79f	0x566e1f66	0x6368bf00	0xd54ac5e9
+	0x364a210d	0x68739b18	0xa482d61d	0xbf54b83a
+	0xa572f37a	0xf3cb277b	0xecd0a7b0	0x4dadcf68
+	0xe611e146	0x9cf2a4d4	0x89b685e8	0x72b99e7e
+	0xe2571569	0xc136a3bb	0x7876c300	0xaa37ffbb
+	0x4733aa9a	0x9f5af114	0x288961fe	0xe4435cf7
+	0x7e72625e	0xa2c435bb	0xce8fa422	0xa457a9e8
+	0xfb68cabf	0x74968fa8	0xc3070a6d	0x785da5d2
+	0xf3405cae	0x0fe4988d	0xa0dfc0bd	0xf9e6e423
+	0xf6146969	0xb7aa7f77	0x5a57e757	0x6db990ee
+	0xc49f092e	0xb1dcf93b	0x3b5499ee	0x45551aea
+	0xfda57777	0x114422ef	0x2469c86b	0x50990211
+	0xd8de398b	0x0f1a46f9	0x82aaba33	0x41f2f3e8
+	0x64ad897f	0x6e00f781	0x6cf84715	0x46b63df4
+	0x1ba8220d	0x93f57e2e	0xd884801a	0x2be20427
+	0x98284ea3	0x69a7ab50	0xf92720f6	0x2669b337
+	0x72c26a6a	0xec7f7086	0x1241983e	0xb46cf0e4
+	0x05c303aa	0xf319d17c	0x1675bf24	0xbf3fcb76
+	0xfd40cd25	0x8f4b1a94	0x4c16fada	0x2a315da8
+	0xdf3ea7a2	0x98c05b13	0xd8a0daf7	0xbc0dcc30
+	0x1468a240	0xb52d9ee6	0xcd66c460	0x2a1a4d2c
+	0xf745b0e0	0xb5bc837c	0xeb6b1f38	0x9123504d
+	0xeba7ef5b	0x2b10b0d4	0x5e22dfcd	0x4738c874
+	0xb0f1d3d8	0x7bdd395c	0xd4f6a2b6	0x27fd3105
+	0x18fa05b0	0x19ff0580	0x990ccdb4	0xb81e67e0
+	0xb5bc6686	0x669059f3	0x6977de9d	0x876053bb
+	0x5b50f1b5	0x71c07729	0x7e1305e5	0xc248bd65
+	0x5f3c8c80	0x5b4c883d	0xeaf29302	0x764b7c09
+	0x95f53d63	0xa99544ec	0x04c35881	0x34e0c07c
+	0x2038454f	0xe5b98ad8	0xe076ee6a	0xe708b760
+	0x9420d20c	0x4bfea03a	0xf1588ed4	0x13d9a7de
+	0xe3a56c16	0x5216ae46	0x0bb1d9db	0xe78f9080
+	0x14f9bdb0	0x54382a55	0xfc2bcee9	0xcf678d72
+	0xafe6f3c2	0xe6266a66	0x81d8e14a	0x9df511f5
+	0xb76bbf2b	0xcd27eed7	0xca08842b	0xf982f551
+	0x358d4c7a	0x341eb98e	0x78b3248b	0x2c3ddf2b
+	0xbaa24b24	0xdd1b8ffa	0xbbbba633	0xdb05116b
+	0x124a84ce	0xeb724c87	0x46247d39	0x7373c479
+	0xf9153a17	0x670c54ed	0xa0f9332d	0x251d955b
+	0xf341ea7b	0xf3c7ed67	0xe54f4b60	0x2fb2a89c
+	0x1db5be18	0x6d87706f	0xb35bad8c	0x94f00821
+	0x7f1d5e2e	0xb94d96ab	0xb1bcfb5f	0x77f3e9c1
+	0x22a74758	0x12507b73	0x07454515	0x539ef418
+	0x991f26d3	0xb8a7e4fe	0x88f43bef	0xe5106dec
+	0xf08d35bd	0x37b78b97	0xdef6d486	0x36e9afec
+	0x44256976	0x8fa27327	0x5e4510e1	0x62b1d6ab
+	0x739f6a3a	0xe53b2560	0x0eee61ab	0xce5c2195
+	0x2a11d29a	0xfcc773c2	0x998f0377	0xfd0cfbab
+	0x60531b2d	0x0f163a3e	0x056e4ea3	0xcbf8f075
+	0x8eecb224	0xdb6f6564	0x9994cf11	0xf2da6068
+	0x7edf2d60	0x3484e010	0x3986d352	0x3215d09b
+	0x8acec634	0x88beb778	0x384583be	0xcfa9469d
+	0x3eaa128f	0xd2584846	0x526e16c5	0xe62c56b0
+	0x28878619	0x451a3cc6	0x9d6b3b22	0xbb4595e7
+	0xc41c5702	0x8eaf59af	0x3ec60116	0xcd3fdf25
+	0xf4baa3ee	0x995acf3d	0xfe048b4f	0x34bf9b46
+	0xef80dd5d	0x715270f8	0x7a0c0212	0xdf084b0b
+	0x6823f5b0	0xd63885c6	0x68fa0d06	0x4d4cdbb1
+	0xe3b28319	0x15e287fb	0x7c8a7c24	0xb260381c
+	0x956d8721	0x02e9a6a2	0xc43316e0	0xf8e8f45b
+	0x3b98c8f6	0x5ac45695	0xec28fec3	0xc122e2a9
+	0xd54498ee	0x075854eb	0x24a9c53a	0x88f82fcc
+	0x6a300c63	0xefd1ae69	0x547a9ec3	0xa137e93c
+	0xaaa2242f	0xd84cccfd	0x4b317c9a	0xa73c890f
+	0x53563e89	0x496e871f	0xacb487cd	0xac528731
+	0x979bd60c	0x1644d04b	0xfb25ec8f	0xa13f6ce3
+	0xfc0c1a00	0x13545d49	0x4b7f9ec9	0x4bd41253
+	0xe2b467a7	0xd677887b	0x3e52951d	0x1b16be80
+	0xb335a750	0x0cbe6466	0xd7b20d9a	0x2fc717da
+	0x7b421a32	0x361f1f9b	0x7a690107	0x07418186
+	0xbe912ff0	0x19ab248f	0x45f15951	0x928dc0bd
+	0x34b6d079	0x0e232ff2	0x905d8b2d	0xdfbe8b6e
+	0x9329a93d	0x730f6446	0xfd66b27a	0xfc2ee1e1
+	0xc7843f87	0xfb41abd9	0xe195709a	0xa55268ad
+	0x7fafd370	0x5b3d3940	0xd0499932	0x68b122f4
+	0xb68060a9	0xd8bc5e9c	0x3e97aa65	0x81d088e4
+	0x1f1d516b	0x91025dbd	0xa2bd0027	0xae82f668
+	0xd7b9a631	0x0a498109	0x4ffa40bd	0x82778f22
+	0xe57c458a	0xdfb5fc7b	0xe87374e1	0x8886dcc2
+	0x2cbc6bcc	0xcd024d5b	0x21987f5b	0x5bee50d5
+	0xcfc95d59	0xbfeaecce	0x35e308b2	0x1c431c62
+	0x63834bd5	0x9a93892a	0xdf509f2e	0x7a5ad3da
+	0xe11a9e99	0xc7363cd2	0x84e195f2	0xf18d74ad
+	0x5cd07824	0x5e632fb1	0xabf51bdd	0xbdcdb3b9
+	0xe7f2b97f	0xe0319ac1	0x92515886	0xdc4a11de
+	0xd2a8b48b	0xc713272b	0x1e1250d0	0x59d87385
+	0x7f962a6a	0x07c50bb2	0x935a13aa	0xbbdf216d
+	0x22bfe2cc	0x9c587c77	0x4e3d6997	0xb5b9030a
+	0xfe9131af	0xfafc7485	0x35a53be7	0xdd7a91ef
+	0xb790c7a5	0x5077a502	0x7670eb90	0xa032fe17
+	0x79f1a53c	0x426d12f7	0xda45810e	0x1892e046
+	0x1f11dace	0x1b80983c	0xed8401f4	0xd5813b24
+	0xe1d5665e	0x5d5086bf	0xbd7605cd	0x1ef38e49
+	0x79848055	0x0c537b4a	0x85198fdf	0xc13d9914
+	0x61c2d22c	0xc3a71565	0x80aa108a	0xbc6cee1d
+	0xa01d35d4	0xe1bd82df	0x11867dad	0xd04b476d
+	0x23f6bf14	0x1b326624	0x908504ab	0xbe631bc9
+	0x7bd48d7b	0x715d075e	0xdb00938f	0x295c2109
+	0x555dc4ef	0xfc476f0c	0x704f2970	0x1528a393
+	0xf5a5a3e5	0xb98429e2	0xf00ddc40	0x23df90f6
+	0x31d70e78	0x7ed4eb17	0x078264e7	0x0604a330
+	0x7f1a2a62	0x339ebf28	0xb6a7f8c7	0x459323a4
+	0x5e0da59c	0xe0f45bfe	0xc718dc9a	0x4b1b6237
+	0xe06bbf0e	0x195f6811	0x474d7c3d	0xcca640ae
+	0x77a48b6d	0x96eb434e	0x8a118ca1	0x55a513d8
+	0x2b4c0414	0x2bed5335	0x8feeeaf0	0x1e3ed22c
+	0x887a2db3	0x3e9cd3fa	0xe836764b	0x9833144f
+	0x9be55821	0xc45ca6ed	0x65419d88	0x4f4e8dd6
+	0xe159296d	0x1fe302bb	0xcdfa2bfc	0xf6cd6f1a
+	0x8acdeed0	0x8bcdb4c9	0x36c82e69	0x4ec65b26
+	0x10498082	0x6e267465	0x3b0831ed	0xafae25ca
+	0xf02be37e	0x930c689d	0x44d149c6	0xfcc96fed
+	0x39ea636e	0x02009f40	0x4e1de152	0x8c138829
+	0xa16e6860	0x33a5f206	0x9c97bd93	0x58af75fe
+	0x984e0f23	0x4abfa9f6	0x99693bab	0xa787d2e5
+	0xaff87efe	0xd5078255	0x21d6f10d	0xff7db25e
+	0xc3431f52	0x20918eb7	0x1b8605d0	0x23b92d4d
+	0x4a72f632	0x80c1fd17	0x0c02d9d5	0x1ae9c1c1
+	0x076b6166	0xa7182495	0xbbd4d5b7	0x81aa4b26
+	0x00ef55f9	0x3ee3d821	0x0b84ad77	0x2bcd72cc
+	0xf1787994	0x13422b02	0x9137efd5	0x4da3a99f
+	0x7ffc5321	0x4b2bc219	0xe96631b6	0xaeb03a4c
+	0x0296e305	0xf923b421	0x519becdc	0xf918f411
+	0xaf036986	0x85e8ccb5	0xfa7da8fe	0x50f4919d
+	0x1fb7158c	0x1cc71295	0x87b14315	0x68bf833c
+	0xe0e2f829	0x0899a1bb	0x7d0d6259	0xb3e0d938
+	0x87247548	0xc4b8b45a	0xa1a198bc	0x86553eb2
+	0x07903528	0x3468e45b	0x3f619b4b	0xd76e9f2f
+	0x1fe52ccd	0x1fa7489e	0x1a0944a9	0xa3001f22
+	0x52e29e4a	0xd8583e6e	0xa2f8bf9a	0xbb596023
+	0x78d13b38	0x37722a86	0xad2630f9	0xbe615c28
+	0x8d660703	0xd2c60522	0x93600693	0xb8026ec2
+	0x04d71941	0x0188c650	0x8fde0e25	0x00bb1949
+	0x18cbf921	0x9efafd39	0x61e2c5f8	0xd7e129d6
+	0x1da1c371	0xeebb9552	0x3d89d2fd	0x507ddb33
+	0x59aefa5c	0xa96050c9	0xa89753f6	0x8a6a3724
+	0x249e55af	0xf5d712aa	0x165332e5	0xeb8b8fe6
+	0xdd58d97b	0x696b8de9	0x1aaddbfd	0x5b70ab39
+	0xd3cfae84	0x43d4ed0a	0xc3e62170	0xff5a2f1d
+	0x4dcac28f	0x483e6b75	0x6f499dc7	0xe322ea5d
+	0x435cab14	0x9c83b6e3	0x03b8cd4b	0x4a773061
+	0x8dd12c6a	0xe16e0b85	0x71754c74	0x61da9e61
+	0x6b0a5780	0xec507e7c	0x67d251f3	0xd158d66e
+	0x5d554986	0xf1b869f5	0x3846a89a	0x93203735
+	0x1fee1e40	0xfedb9d4a	0x833f3275	0x4efbb610
+	0x84e139dc	0x391caafe	0x72ded682	0xc4578cc9
+	0x2a97e6a6	0x31ae0a21	0x61b759e8	0x7dba8f29
+	0x9f44920d	0x2a682773	0xe0973858	0x4fe8d93f
+	0x4461e195	0xb4e9d538	0x35244354	0x71e1e076
+	0xe7c9a805	0x9281e7bc	0x9c5866ff	0x8d3fcc6b
+	0x96bf9d94	0x081b5f1f	0x59f1c86f	0xc7624b4a
+	0x642828b5	0x2d1adf14	0xa23027b0	0x203baa5e
+	0x383020e7	0x9270e519	0x5c9db413	0x65de52bb
+	0x427d85ca	0x9be72540	0xcc42320a	0x2a540c30
+	0xb5f05697	0x94deb4f7	0x85931ed3	0xf6985f6d
+	0xcdbefa9b	0x4c3b4518	0x23900cdd	0xb61242cd
+	0x551f4fcd	0xe32114c9	0x1463bf4f	0xb1ab0b15
+	0x9d3bd7d5	0x482ba600	0x2a1905df	0xeca00b13
+	0x4231c992	0xbee51476	0xd53b8a3c	0x84e444b3
+	0xf580de73	0xb77ae962	0xd317f0f7	0x0696e18c
+	0x548cc93a	0xe84e9eaf	0xd3a112ba	0x09203e1e
+	0xe5fcf34f	0x8cbbcad0	0xbd39deba	0x3f3c444c
+	0x9b42960d	0xa7cfd77c	0x6fe061f4	0xa47cde9e
+	0xc6e0d1c0	0x73c66abf	0x5d1e8fbd	0x3623c582
+	0x661501cd	0xf82c02b3	0x1fdddc43	0x41326004
+	0x7e66833c	0x9b87f09e	0x460e9f29	0xaa42d4c7
+	0x9de056bf	0x7a04e294	0x4f45a29e	0x4dc53b68
+	0x35f66dc3	0xe5d61f33	0xdf1c3b74	0x7a800188
+	0xd2d69278	0x51d10dec	0x36ba5a27	0x84710d0f
+	0xdb9d4265	0x0cdb2557	0x2294b43b	0x21fd5276
+	0x8e242a48	0x534b736e	0x517c06fe	0xddae34d2
+	0xc9963646	0x316a2866	0xf78e670a	0x4354b9ad
+	0x6478b461	0x41bc356b	0xadc9d69f	0x86310701
+	0x698b5dd4	0xac1a065b	0x325b19b6	0xdd8c1424
+	0x9782ac36	0xd07f2b25	0x3142d1ef	0x1b65cce6
+	0x45dc809d	0x26b47e8a	0x47ffd190	0xddd23daf
+	0x852c505c	0xc68d8c2b	0x76f71872	0xd62371f2
+	0xa85876ff	0xd67bee5f	0x9c7f08df	0x7cffada6
+	0x1f87b705	0xb7395ce6	0x5f20c731	0x83b83c9f
+	0x39b72eb9	0x33402454	0xfaa4a4f4	0xce09b8a9
+	0x8fc8ec39	0x8282f919	0x18a12d7a	0x669b255e
+	0xe63cf97b	0xe06c98ad	0x9e9c48c4	0x9e1eca60
+	0xade5b5a5	0xe871bbcc	0xf5c4459a	0xd239cca5
+	0xbc690a32	0x8e6a5a36	0xf656c3cd	0x2aea3748
+	0xcd89e82a	0xd727974c	0xc89c15d3	0x2cb3d656
+	0x5ea5697f	0x95351d3f	0x3c51294d	0x19dad085
+	0x9875ff98	0xcbe290c9	0xec1db1d1	0x06dad038
+	0x59676ed1	0xd4ffaa52	0x67b53321	0x406d0405
+	0xb63b27b5	0x02a7acfe	0x0218e862	0x0600e77e
+	0xc5ab4fd1	0x59614324	0x0711ff6b	0x66aadc1f
+	0x03d4783b	0x260efa73	0x595b8ff7	0xcc38a258
+	0xf581cde6	0x54ad0529	0xe7fd85e0	0x865cdb10
+	0xb36829e6	0x292a183f	0x0365b477	0x699539bc
+	0x1bab4354	0xef8fbc6e	0xcd13d0d0	0xae88592d
+	0x1fd2b9ab	0xc73c4087	0xd443f88b	0xd954a62e
+	0x98f330f4	0xec153762	0x79ab5dde	0x576b971d
+	0x32bfeb19	0x8cb0fc53	0x0adf7206	0x1fd5c3dc
+	0xbf2937d0	0xe3a27af7	0x7a5985c4	0xf385bd6a
+	0x4749ff2a	0x2c9dbb25	0xfb5ec7e6	0xd35e3858
+	0x6b02a00f	0x39648c79	0xea16560c	0x7426126c
+	0x2e48ff85	0x7db3751d	0x5caa6cae	0x9d7bf7fb
+	0x7dc3045f	0x11a58714	0xb1c7ec05	0xd861d92e
+	0x3b9335a5	0x369f36de	0x86537f91	0x6df69efe
+	0x097f9eeb	0x21a1c221	0xe705e58c	0x814c6d6c
+	0x3b15231e	0x27348dc5	0x31904ae2	0xe795e0bd
+	0xd66763ea	0xe8d72c3e	0xa98152da	0xe13f01ee
+	0x3f309623	0x4af332ab	0xfa907056	0x55f64e59
+	0xec5b728e	0xffb73bfa	0x01e03bd0	0x78b40ce6
+	0x494800ba	0x391c7b3c	0xb1a5f6bd	0xc08f1e24
+	0x3e463ced	0x365110ba	0x637cb6b0	0x75753237
+	0x8a7eb826	0x10017424	0xece96fac	0x7e1ee939
+	0xa11e1553	0xfca3f88c	0x20937141	0xa10f07ed
+	0x2be3baa4	0x0b1abf6a	0x446bb4ac	0x431fcc86
+	0x4d13befb	0xa1dde1c8	0x956aa819	0xa6a6bb8b
+	0xca2e0a62	0x7ebd0a45	0x1ffbd5b8	0x95c8518a
+	0xa69b829e	0xba2506fa	0x8969eb89	0xb8989e02
+	0x2cc46256	0x52f394ba	0xef94217d	0xc397b570
+	0x029acc3f	0xe4ed9f6e	0x15d2b07b	0xe0e0e7b5
+	0xf0a90eda	0xd2b9c951	0xe7fd0d22	0xa11b524e
+	0x297192fe	0x09494708	0xc3231693	0x23057014
+	0x2347f4f8	0xecb07723	0x78d5387e	0xd950aa5a
+	0xb8b89982	0x3d4eb0fe	0x9a5eac36	0x3c314180
+	0x037ef95a	0xe5a07f1d	0x963d7545	0xda533ac8
+	0x652420c3	0xecba1589	0x69956916	0x7118042a
+	0x010cc872	0xca74ec31	0xb65b0a15	0x24d7076c
+	0x7835e3c4	0xae04ce57	0xb9106c38	0x450147a7
+	0xfcd308a6	0x3780795d	0xf127d659	0xabd3762a
+	0xc33508cf	0xd43c2743	0x13f9c4b7	0xb811ccee
+	0x60ea88e9	0xfeaf11ed	0xa2e4e08a	0x679a8a16
+	0xfe2f179d	0xf9d71588	0x46a5b44d	0xa3739f11
+	0x026aece1	0x27227337	0xa67499e7	0x150941d7
+	0x3acb3852	0x36e4a886	0xb3cdac7e	0xa6cc4731
+	0x3da129f9	0x8945d1d3	0x0ca8e53a	0xefc7a5a8
+	0xde9550b5	0xa2838b96	0x85855f0e	0x5f527d35
+	0x6f7cc825	0x3376c65d	0xe11c296e	0x31b6c238
+	0xaa78ce8f	0xed627ba3	0x8b341b27	0xe5ae270a
+	0xe4def7ab	0x4956ab96	0x8fe3e3e6	0xc38a8264
+	0x4a580ee0	0xa367eff8	0x30cd46a1	0x63bfb7de
+	0x0f077d1a	0x071655c1	0x9cd20ef5	0xbd910426
+	0x5ff8d076	0x780541e2	0xb1b78ae6	0x8d4f3e25
+	0x0d607fbe	0x6553eaa5	0x295663d7	0xad96bd90
+	0x3fb8d299	0xa876e194	0xeff9ad1b	0x8eca7226
+	0xae0822a1	0x2f2665b7	0x8c380d8c	0xdc3dced0
+	0xc5902d53	0x9487cbc7	0xaee8d33b	0x9918bc49
+	0x172b80a4	0x54da0366	0xb0480c4d	0x8505c00c
+	0x95f9d4e8	0x04f6c56c	0x4f1992d7	0xd5be2a99
+	0x9cfd5518	0xae36133b	0x68cfab7a	0x93c5b3c9
+	0x5c3e00de	0xfdba8d1a	0x1950a499	0xf585b68f
+	0xd7877843	0x31f26d1c	0xf6aaff0a	0x8422439b
+	0x34932e6a	0x9fdef126	0x004902f2	0xcfeb933f
+	0x461cde2e	0xbf0c2348	0x6f378884	0xc6f28584
+	0x0e8e1484	0x487df649	0xaa6d7abe	0xabe47e51
+	0x9c037ac3	0xa7d9a917	0x017ce418	0xd3fcfe05
+	0x45d44ef0	0xe2122eda	0x3dd12c7b	0x2b943ac1
+	0xe944001a	0x9ea8c0f5	0x13887de2	0xcdeac67e
+	0x661926c8	0x464d7d92	0x2153bc27	0x28f366b0
+	0x95aaccf9	0xf58e42a6	0xe2b74b95	0xc4e76731
+	0x8bbe0115	0xc13d03b0	0xdfd3c57d	0xa6a6a376
+	0x33054af1	0xf2164000	0xf12d1b3e	0x10aaba39
+	0x8c48e878	0xf62e4034	0x9989fe81	0x3cce7788
+	0x33dedaab	0xecce3579	0x52a1a0f9	0x25f7e0b1
+	0x00024fcc	0x9d315f1a	0xf9243a7f	0x51b5bfcb
+	0x4cf926ca	0x19a4e8f4	0x729db9a8	0xc3f0cda4
+	0x2cd53230	0x1d86dc30	0x7b20b7cb	0x1bdbf1f8
+	0x208a3bed	0x175ce105	0xfd45df17	0xdd3f5fc1
+	0x689efdd6	0x0ab4123b	0x7329b958	0xac90a04e
+	0x32caa96a	0xf7609907	0x862ee458	0xaa328d13
+	0xa839f1ba	0xe7da448a	0xb5f361c0	0x5d5f16c2
+	0xcb3faf23	0x9d6fca62	0x80ed4411	0xfb134416
+	0x39ab14a9	0x305ab74b	0x76312b28	0xea38b1bf
+	0x45dee43e	0x4890904e	0x548bdf7d	0x20ef92c4
+	0x86704c38	0x8366dde4	0xafc9d551	0x01486482
+	0x2a66f042	0x819315ea	0x59aef12f	0x5c4d2f1f
+	0xd1d0fb21	0xa286aa99	0x59fe8c60	0x0fb2275d
+	0x455d95c1	0x665c9783	0x4c6a7fda	0xd78f1536
+	0x2cca3af5	0xe7fc1c83	0x12836c68	0xe40afac4
+	0x04971027	0x15033991	0x1599b526	0x28f271d6
+	0x249e2db4	0x8c87a3cb	0xd8949626	0x467b165a
+	0x9834d5dc	0xaca55a99	0xae403e0e	0x5e44dfe6
+	0xb5cb972f	0x4affd423	0xdfe3a0ba	0xba66ddd3
+	0x8fb8afbf	0xf7d2127d	0xc56b4e4e	0x801ee995
+	0x3af70660	0xe4271646	0xfc9b3f0b	0x0d1b714c
+	0x2899451e	0xc0d2ac1d	0x5376412e	0xf8830b3b
+	0x00730f02	0x2070e1c3	0xaa3ecdf4	0x61c2b089
+	0x43160e14	0x1c909bca	0xb12b3e7d	0x563aa455
+	0xa6c82117	0x2fd25eb2	0xcbf7402d	0x5fd16485
+	0x2a903214	0x10b1e25f	0x20ec92fa	0x03e38321
+	0xe264cf01	0xd0b18d0a	0x529610d3	0x6a862094
+	0x0021652b	0x3e41ec43	0x68753afa	0x578208f8
+	0x63fc6585	0x3c065808	0x15072917	0xe530dbca
+	0x4fd31ab6	0x90ec9f1d	0xd21347c2	0x1aa8057c
+	0x707ac53d	0x3a6f6cff	0xef4f5bfb	0x91f9df78
+	0xd4d8e7b3	0x85b23779	0xd70dfb50	0xfc3eb090
+	0x2afb8f1e	0xd17d1671	0x887adc0d	0xbd01123f
+	0x39584f27	0xe5bdc9fb	0x8c1f74ea	0x4771c3ed
+	0x994f3f8f	0x71f73dfe	0x6d8f1065	0xe639d542
+	0x1a0c1e63	0x87d4f6cc	0x6b7d3f3d	0xf04e1fa7
+	0x83d6c73d	0xd674b74e	0x3c68a8c6	0x018b543f
+	0x3c1e295d	0xece6274d	0x1119b65a	0x74a6967a
+	0x69e31d43	0xed442719	0xb6d4d76c	0x0c634c05
+	0x94ee29e8	0xd780bfe7	0x2bfa6dd0	0xa84c1e0e
+	0xc5a76023	0x8513aaab	0x67104dd1	0x6758d5ef
+	0xb804c65a	0x4b5eae39	0xcdf42fc7	0x0a409263
+	0xd5172df1	0xe06de198	0x221b3d16	0xd389dea9
+	0xdc7ec34a	0x0cdb0c31	0x74aa5423	0x1a3a12f0
+	0x84af11b6	0xed5484a9	0x48a42703	0xf88a5554
+	0x1fb1c3e8	0x14f0139f	0x5bb798d4	0xa44d0a7a
+	0xffe63aaa	0x2623dfb2	0x3dfdf073	0x7c5f64c5
+	0x7fb8e776	0xd6ec4cda	0xbbbcc9c5	0x543d4e67
+	0xe6261cdd	0x5fa93a6b	0xb2f22232	0x46b3bf1d
+	0xc85c492f	0x3e9b59c8	0xc57467e9	0x3ef1cca2
+	0x885c11b4	0x430b945b	0x7e866a53	0x35640ef2
+	0x2bc250d2	0x143e8bcd	0x526e160a	0xaf195f5c
+	0x6b7af12d	0xae86e442	0xa8a7e79b	0x348e2f45
+	0x83464bf9	0x7e9217f2	0x633167d5	0x7f48a7d9
+	0xc0e68db1	0xe20a73d3	0x08631c1e	0x6d1c947c
+	0x09f758fb	0x4e7a91f8	0x6310962f	0x4cb9d435
+	0xc4e0d790	0x516ff75d	0x7d94e8f9	0x5e096081
+	0x54c45793	0x5c4006ad	0x96597e18	0x8288ae51
+	0x80b02790	0x07a93092	0xc3c4f812	0x5370f66d
+	0xb0dbdcf4	0x7b3989b6	0x401ba87c	0xb6583c3d
+	0x172f026b	0x14f6a157	0xf38c63d1	0xdd649ff5
+	0xf3f4e004	0xf35ada45	0xb4ef6088	0xf4dd2f84
+	0x45cfd771	0x87f4aea6	0x258285ab	0xd6cd6526
+	0x6ef11ebc	0xc9fe8974	0x19fa04ad	0x42f2cb41
+	0x1f79e225	0x4a377d25	0x21bfba29	0x344a68e1
+	0xf5ecce49	0xfbb59c84	0xd79e3b7a	0x66abbfbf
+	0xf472eadc	0x96e131d4	0x582cc500	0xd6e66fbc
+	0x89514daf	0xfc33243d	0x03f2ef3c	0xc89b7e63
+	0x81690099	0x3d7b84fa	0x760c3e67	0xd17dc669
+	0x5d224d4c	0xf4ff8750	0x0156afad	0x65d31848
+	0xb90d0084	0x5f8bca59	0x30fe3607	0xf42d02d2
+	0x1a1433d9	0x83e8ac6f	0x580fbfdd	0x621b4f0c
+	0x8a0384c3	0x8f2bb99e	0xcde8d946	0x656c0982
+	0x4e6ba947	0x6111abba	0xd2a533df	0x9d173834
+	0x12ae87b7	0x9c96dcc9	0xcb38017f	0xcfdb1a79
+	0xa812fa65	0x7e94957d	0x448b6e54	0x951db061
+	0x95413429	0xa9b8f2a2	0xed53849d	0x0df306e6
+	0x47ad8eee	0xc89bbc9b	0x2c812451	0x8a8cd47d
+	0x7f6fd5e3	0xac4f541e	0xd0141031	0x1bc101b8
+	0x445eabc8	0x8812e01f	0x1972aad1	0x490e0983
+	0xde196258	0x8a1f4280	0x7d4bbc9f	0xd8828045
+	0x6d0b5f9c	0x99300545	0x2245bb3d	0xa6212403
+	0xa16fedfe	0xd14bf451	0x26146824	0x56fb7edb
+	0xc569ab9c	0x3ee4ca51	0x4769b0c7	0x9702340a
+	0x81477a5c	0x5e5e2b00	0xecdf796e	0x1b71f918
+	0xeb7b0bef	0x4943478f	0x996aa457	0x563df3ea
+	0xc13e9084	0x84a710c6	0x51aae833	0x1286b9b6
+	0x646e93d2	0x27cdb6ae	0x2c5131d4	0x80331468
+	0xa2de5ec3	0xcc2f6702	0x3e395dc6	0x06faa48d
+	0x395bf0b8	0x2ab561f5	0xbf8d67e3	0x8faf4cea
+	0x51e93442	0xcf47cea8	0xbf63b9ee	0xe927b21c
+	0x1a03197c	0xec291d24	0xfb8519d7	0x4d955d6c
+	0x2df0903d	0x5a706cd0	0x61ef0856	0x494d1444
+	0x86699045	0x067b12c0	0xbe0a1b48	0x234b346c
+	0x34cd7efa	0x6a4ae615	0xcd91c638	0x954b84f4
+	0x1a128af5	0xd969cc17	0xf4dc37e1	0xaa5e52d8
+	0xde59f894	0x0f5a917c	0xb4fb57e7	0x0cab7d81
+	0x9aac2151	0x4cdbb7c2	0xacd786a1	0x3a7b62d3
+	0xf240daa6	0xff356dad	0x758d1e15	0x193a13f2
+	0xee61d3e3	0x981a74fa	0x227adbf5	0xce83506e
+	0xa1e3af28	0x5d4885c1	0x6c1f694a	0x96986af4
+	0xe458cbbe	0x91951817	0x854ec652	0x71e35285
+	0x89afd078	0x26170aa3	0xe65e2d7d	0x457ed03f
+	0xc2fc1735	0x026e2185	0x7084e0e7	0x118e91fb
+	0xba85dfc6	0xe658f66a	0x0c19dbe3	0x17dc8f29
+	0xa75cbee5	0x1ad8e022	0xf5458efe	0xbc5c0628
+	0x8bd901d6	0x8a986723	0x492e7376	0x7c35b261
+	0x39d55be9	0x3768fe66	0x7467ae3e	0x2388e33e
+	0x5b91e770	0x55d12deb	0x2c12b96d	0x82664969
+	0x6fddc486	0x790b4248	0x0a1a279d	0xd9b92a2e
+	0xe316f88e	0xf21cc3df	0x51038908	0xb3aecc0b
+	0x9b4048a0	0x21748d61	0xd65d0a32	0x0ba4dd14
+	0x51606dfc	0x23715771	0xce5bd0ca	0x26b7d411
+	0x87029a42	0x3a02968a	0x0b81412a	0x7fbf7638
+	0x6935a48d	0xd29ddd49	0x5e60b89a	0x498efa41
+	0x37756ec5	0x7a07ae76	0x60b6cad3	0x521dbbf6
+	0xa1d46ac0	0x61279e7e	0x28bdb70c	0xdae29099
+	0xb075ba91	0x6096a79d	0x2bee42c2	0xe2632f66
+	0x6f63ee5e	0x3c1635a8	0x9cc893f5	0x74fd1f0c
+	0x0e979de0	0x3cdf28f0	0x5a0f41c5	0xdad09973
+	0xc57f47f6	0xdde7dd76	0xd05965a8	0xdeadd87d
+	0x1d87a754	0x5513a4c6	0xbd5fef6b	0x0d649214
+	0x5b36915c	0x568038c0	0xc775afc7	0x7d32462b
+	0x78ae7ed5	0x132a1ae2	0x248359de	0x2550a259
+	0x7ff08337	0x2dd48301	0x7d11da38	0x4076b6a1
+	0x8d6ac3b8	0x2858fcf5	0x102ba807	0x6508bb1c
+	0xa5aa0335	0x25d56586	0x53b990b0	0x7e4e4c49
+	0x67b37e21	0xd4646417	0xcbf0e82a	0xa2eb08a7
+	0x53761d3b	0x3bc87b03	0x0e8da6ae	0xa867b1b6
+	0x03704bed	0x5460a156	0xdbc7b432	0x861e76c6
+	0xd9a25796	0x746ff2ff	0xea2ded19	0xc0c12f66
+	0xbed173c7	0xcba2a17f	0x073ade3d	0xcd20aa31
+	0xef12f091	0x306a0d01	0x683ffda0	0x6a4d3ced
+	0x2f19e821	0x2f220131	0x59c46a40	0x7370fda6
+	0x6c8268c2	0x82e5ef45	0xd79dee43	0xe7779aec
+	0x94ed3852	0xed0e12c7	0x6ab12986	0x32d1f391
+	0x10d545fa	0x5771a8a2	0x0cc7aac1	0x90352208
+	0xb8f980be	0x39d2c41d	0x60474238	0x54f2ab34
+	0x29cf4e10	0xf29aeabc	0xf1ab8e24	0x167c2b39
+	0x83e05ce0	0x12e6ce1e	0x35afe73e	0xd9095f05
+	0xfb41fec5	0x564488c8	0x94a858b5	0x8e940dea
+	0xf624ae34	0x85efbb1b	0xcbcfb146	0xb9455026
+	0xb4e40bba	0xc3195d35	0x1cfa4bf8	0x2d49eec2
+	0xf6695b41	0xd220af6f	0xfad02fa4	0x8af9362b
+	0x7d1dedcd	0xc5667cff	0x897bc389	0x831fb846
+	0x2442033e	0x41ebff58	0x05502fd4	0x43574914
+	0x58530064	0x11c1e752	0xbbe62845	0xa7618ec6
+	0xf1627ff5	0xafb00250	0xc3824684	0xee3eec52
+	0x337942b2	0x7a3a291e	0x857f05f3	0x15719b81
+	0x66fe3f57	0x88280481	0x5c866ada	0x2c1f07c6
+	0xcef7155b	0xd3a236b7	0x90c96bdb	0xedebecad
+	0xc478b1d3	0x75dc8363	0x340738ac	0x4d15034c
+	0x1cb8e2e7	0x41ab7b1d	0xe798cf70	0x3a33131e
+	0x6a43e6a3	0x386192c6	0x59693949	0xd6b28e16
+	0x22468abb	0x6f23eff8	0x22aaa858	0xcfc1443e
+	0x092215c9	0x894b362a	0x17819cca	0x75eacf86
+	0x9e8edcd7	0x578501fa	0x888b8186	0x7849f9ea
+	0x18a5f279	0x1a0608e0	0x3f79a285	0x5a9cccb7
+	0xc8288846	0x8153e63b	0x06745426	0xfeb7dd82
+	0x37967ee7	0x6501bdc8	0x2b1303ff	0xf105ea53
+	0x1afd9ea4	0xd7f0c26e	0xfc9d98e0	0x3adcfa5b
+	0xb95372a6	0xcf0737ae	0xd6f56c9b	0x3d047e23
+	0x1742e108	0x730cea46	0xd61b5674	0x1d4a0bf5
+	0x9f9a0d2d	0x15751fa5	0xd1f78c6e	0xbcbf0f49
+	0xf02861da	0x75c73284	0x565ac314	0x74f424cd
+	0x2de2c5d0	0x8b81d64d	0x7da7ed9d	0x0dec53d5
+	0x119bcb0c	0xe3280bc2	0xb8876379	0x61d9315e
+	0x76e711d2	0x5f7d25f6	0xe536781e	0x48bb7127
+	0x0241bdb6	0xa3f5c283	0xa4e289e7	0xb0c00a9b
+	0x31437997	0x8360ae3f	0xa89404b6	0xb5049139
+	0xecbe777a	0xd5aae954	0xa7e3497d	0x766e436a
+	0x00311364	0x09c314f6	0x03f4992b	0x57cf2522
+	0x717d0b4b	0x3f0c50a4	0x6f2faa6b	0xfdd19e4d
+	0x136b4811	0x2ec4df6d	0x540e503a	0x4ef99a84
+	0xe190e376	0x4c6a2b6d	0x898e2adf	0x30816632
+	0xb595e258	0xe1b16383	0x9a0dff8f	0xed42f0a8
+	0x12314f07	0x2d51c21c	0xf31c3c3f	0xc112dd94
+	0x052fcfe0	0xa567c821	0x6892dec8	0x07c26300
+	0x1799a9ef	0xf2ef0828	0x30cefea6	0x3f6919cf
+	0x5d3d2396	0xcb2f347e	0xf626b1ef	0x449fbf5b
+	0xffe2da0a	0x33d5d2bd	0x44d7d222	0xb24a94a0
+	0x04503d1b	0xde3efdb1	0xb6a30029	0xac134d4f
+	0xabb57951	0x4f3e6cb8	0xdd738dc0	0x598dd5ef
+	0x80fdf47f	0x756d4968	0x95449696	0x44dd4689
+	0x3781c7ee	0x8b3c7403	0x51b86cce	0x90d40f13
+	0x50296220	0x85637fab	0x11430ba6	0x37b6fe45
+	0x06923d07	0x75119847	0x2b16990a	0x558a824c
+	0x4f7ed662	0x6ff01850	0x73301b84	0xa9f8cacb
+	0xd47591c9	0x239f5de5	0x978dcd1c	0x50c99641
+	0xc4331a17	0x9c42adda	0x33adb88d	0xf278e923
+	0xe4f30829	0xe505a03c	0xd83ee3b1	0x46bf73fa
+	0xcfd0610b	0xe5904ea6	0xf1aef3d8	0x4f38284b
+	0xdc0ae0bb	0xb63412e0	0xd871cbc5	0x95e54457
+	0x4e6b6ee0	0x796e632d	0xb02c54d5	0xff6e3a26
+	0xcf25f241	0xa264f1e9	0x9c4c5a83	0xe8c67201
+	0x8a54d34c	0xefeef65e	0x224eda49	0xb66a6c4a
+	0xb7947d42	0x1b9cc0c4	0x18f24b32	0x265ba45d
+	0xfe433ce5	0xc878de4a	0x66239035	0x3e55f422
+	0xabc11200	0x5b3ceeb2	0x79972610	0x13b5b5ba
+	0xe0ec8eca	0xf5f2a0ee	0x98bf92e3	0x5bd78dbb
+	0xfe01740f	0xc089bd76	0x033dc19b	0x43d76143
+	0x34ce988f	0x57c18ffb	0x73d1ddb2	0x051a4e3d
+	0xc635e701	0x4a0ddefd	0xb10b6cda	0xabcccffd
+	0xbe1055e2	0x5ecae7cf	0x880329ec	0x7590ea81
+	0x967cc129	0x78faa2e6	0x7e0f8e38	0x222bd775
+	0x31943949	0x8c5e77ef	0x9fa68d99	0x5d90ff61
+	0x62b9de80	0x8f42ed5c	0x907a18fc	0x851b4e2b
+	0x46992571	0x0a2b6586	0x938b91c8	0x4475b4f1
+	0xefdd87e5	0x28c7339f	0xadc025bd	0xfe9a46ef
+	0x96b62846	0x9600fd60	0x8d30853c	0x5321f086
+	0x51504b37	0x70f70c0e	0xd3c63718	0x4ee48d14
+	0x0f42ece6	0x4c7788db	0x8d0838d7	0x487d073f
+	0x3c0c9a41	0xb02bd044	0x8509af73	0x6dd6f7a3
+	0xb0fb556f	0x92c15d39	0x35c3dad0	0xcea85451
+	0xc7d26893	0xd59a4be3	0x24c3b5e8	0x20ae4992
+	0x46fdf7ed	0x237c7116	0x6cf591ab	0x069f6538
+	0x0c1b1441	0x3b5be741	0xb410ff01	0x20d511b0
+	0xf2c96bda	0xeed21dc8	0x2a3602ee	0x08f774b9
+	0xf77317f1	0x788a9067	0x70907446	0x16affdee
+	0x999869fa	0x4d164296	0xab34d654	0xf7992cf2
+	0x676ec9ef	0x8e9b8b12	0x33ae21bc	0x1971e43c
+	0x28880c9f	0x1a62e925	0x76dc574f	0x15765e0d
+	0xe41a9f10	0xa7bfa8bc	0xa6a68542	0x5368b186
+	0xe235e3d0	0xc89c2aaf	0x2644f5e8	0x577a3fc5
+	0x0529603c	0x77c89615	0xb89aec94	0x9c8406a1
+	0xa340c976	0x343625f9	0x2e6031ea	0x2202e06e
+	0x97d888d1	0x1902d335	0x86c3b9e9	0xebefbeab
+	0xd0732d32	0x8be1ac34	0x4289df13	0x4f44a9fc
+	0x0871780d	0x413a895d	0x893db7cd	0xb58cabf0
+	0x8a20ff00	0x6529c6d3	0xd6d22f25	0x4cf7c2f8
+	0x427e50d9	0xaec1c707	0x91695339	0x711708d4
+	0xdfdd7fe1	0x5e9df851	0x65722a04	0x05d8da5f
+	0x27c91699	0x1efd60c9	0x940a132b	0x7ea2851a
+	0xd9fd9dff	0x0a541bbe	0xc0d63c35	0xc12929b2
+	0x33610416	0x502b2626	0x5228b15b	0xd94d4b35
+	0x14c0b45f	0x64ed4b0b	0x78af7626	0xc2e9046f
+	0x7a12f190	0x42beb256	0xaea48841	0xf0e790d7
+	0x72973deb	0x11cfeefb	0xba5cd0e5	0x1a1f41a7
+	0x65c06ace	0xac49a1f8	0xbbd82cf8	0x415035e0
+	0x33ebda26	0xc908a605	0x8dcf8b85	0xd4569ab9
+	0x2e5f7de4	0x2d0a3ced	0xe7c29493	0x6fb32111
+	0x71f9535b	0x63cef544	0xc2215455	0xb1574011
+	0x17b0b0af	0x4c9436d5	0xb16fdefb	0xe33c66aa
+	0xcc2e67f6	0x10f09eda	0xd46e0144	0x99dc690a
+	0xdecf7f81	0xc421b916	0x703e1199	0x6e074b90
+	0x259fcebd	0xb4e7dbcb	0x4045f119	0x4034d34f
+	0x0a52aeeb	0x0f8e2b36	0x3ddaede3	0xbd012dd3
+	0x7fdef8b3	0xe0071859	0xfb279d23	0xa8eff030
+	0x30e2b0a6	0x7c50a0c6	0x97dd696c	0xee072f57
+	0xe45d0547	0x3a4a96a7	0xc59bfeb4	0x37e4449b
+	0xb165ce74	0x2939ff17	0x2c16376b	0xacde50da
+	0x3e57b316	0x589a14a2	0x8ed5557e	0xfd6bdf76
+	0x57348636	0x77df0b9d	0x49e6e4ac	0xe9a3ce3f
+	0xc1b06ddd	0xaa5111eb	0x748a53ae	0xbde72bb6
+	0x7b2d7f63	0x7ed5bf06	0x98389845	0x17c8d9a3
+	0x4cace2c0	0x441e3441	0x67eb5256	0x59e7cd3d
+	0x46ffac59	0x8bd74b6b	0x09abf015	0xdedf14a6
+	0x92ed879b	0x116b4a44	0x471ce853	0x9c649ad6
+	0x9f1838c5	0xc4beea8e	0x747900dd	0x48ca9e9e
+	0xaeaf94fa	0x1c03c132	0x44662d4f	0xa537d972
+	0x589a90fa	0x57332041	0x2f8349cf	0x64364c6d
+	0xff5f1aeb	0x681dba1d	0x4eeebbef	0xedade9ef
+	0xcb938dfd	0x0164c6d7	0x13b9bc03	0x18b407e9
+	0xb298e043	0x9b224562	0xb645ffd8	0x5815aa44
+	0x4793d73d	0xb56f0e9f	0x8c9044d7	0xe41109b1
+	0x2710c352	0x4b7dcbac	0x38f754b7	0x3c6cf465
+	0xb54ee7b2	0x856a179e	0xe86338dc	0x1e7e2b53
+	0xe89b7e12	0x15c42976	0xad7a65ae	0x0d8a7cc3
+	0x4bc02b15	0x517a40d9	0x11c81722	0xb2bff7aa
+	0x0ba28f37	0x6c9e84b4	0xa1de9a97	0xdafdc842
+	0x418082c7	0xac99eb05	0x440d81bc	0x0f8281e7
+	0x62386c2a	0xe9772f62	0xdc79a423	0x09b53e98
+	0x84c3c90f	0xca17ba91	0x1c6389ac	0x873c14d9
+	0x2c259be5	0x1cc07fd2	0xfec486d5	0xc24694f4
+	0xdf474401	0x7be2a72b	0xadb66511	0x81209edc
+	0x62da35e7	0xcb368410	0xe80b6818	0x26cf9c82
+	0x321e312f	0x9cc8a82b	0xbf9ebd18	0xc598d6fb
+	0xc21858cb	0x6dc72a46	0xe44aa56a	0x82fbdec9
+	0xbd732010	0x6975adca	0xe5ddf36c	0x72bedc92
+	0xde4c0ccb	0x9e6e20b4	0x6bf5ce44	0x0a6eb5d8
+	0xa439cda7	0x055f776e	0xedf823ad	0x298c0f7d
+	0xdd6c8d9c	0x066e9378	0x86847ddd	0x151bda4c
+	0x61ec7724	0xbf3de534	0x64d80341	0x9c608f22
+	0xde5d94a9	0x7423895b	0xadfe2881	0xc7acfc0c
+	0x7ff035db	0x42c2ae6a	0x0cd9e52e	0x425bf47a
+	0x41cb2f2f	0xb0d034ae	0x1cbc0c50	0x9ae9ee61
+	0x40fd456e	0xcc5ddf76	0x3e5c52d7	0x4f7e55df
+	0xe88c725f	0xa38d12db	0xa63d5340	0x7a65f347
+	0x5d8e6ed0	0xb6140480	0x1d038fd8	0x32041136
+	0x1c45b5ee	0x5100ab0e	0x98473545	0xa92e7dab
+	0xbddefe68	0x6eee94c9	0xcd046fd5	0x9269ca4c
+	0x9244ed01	0x68b9272c	0xa2abf1f9	0x0c5eb602
+	0x3cee855a	0x8d449506	0x968687a8	0x69fc4521
+	0x89fb7d41	0x82d335c1	0xcc7e2c7f	0xdbdc20c1
+	0x5adb4bc7	0x429ea826	0x99c6d2b9	0x8f684704
+	0x53361f81	0xb8c4a550	0xd079cafa	0xe28fb54a
+	0x170c157f	0xe5faa727	0x9d37b6f8	0x7a0f88b6
+	0xdad0aa7d	0xe6eb4a39	0xa8391bbf	0x912bd27d
+	0x7676a2c9	0x67ebb91d	0x4f090fec	0x4148f1c1
+	0xb8456040	0x56befd92	0x9089e3a8	0xc2568a9d
+	0xeb649427	0xd904af9e	0xf99984b8	0x4467144f
+	0x79efc76d	0x75589aec	0x9f168b29	0x4c048855
+	0xc0fd5d25	0x4a58fa2c	0x31b194c1	0x8a801969
+	0xd5e0000f	0xa2f9f4e8	0x8591ac20	0xc0fe5118
+	0x5b7f969f	0x21a9dff2	0xbef3c51d	0x51873dda
+	0x207120cc	0x690d99c9	0xd532b33d	0xab0d4ccc
+	0x7452bd5a	0xa17f7858	0x5289f83c	0x7d0e053a
+	0xd906a982	0x6778d47f	0x005db3a7	0xe88104e2
+	0xc52df471	0x44db6099	0x995d4c1f	0xeca903fb
+	0x3eb38a46	0x3a656171	0x24945ee1	0x35439de7
+	0xbf95525d	0x9b4030a0	0xb518b00a	0x137ebe42
+	0x0997e7a3	0x1f344a83	0x00241146	0x40e74f33
+	0xb1cd34d2	0xfda51a35	0x7cc94789	0x2cc46a7b
+	0xb966a92b	0xdc8f9838	0x2a2fc869	0x846778b0
+	0xc2ded51a	0x88000d7a	0xc6d1a90d	0x2e4c17a2
+	0x112e4409	0x489edcfe	0x5be08376	0xf004d962
+	0xe26e28db	0x4ddb374f	0x6801cce8	0x35826ef1
+	0xeb3b8c3a	0xf209ce2b	0x728ad017	0xac4e76c3
+	0x721ad4c1	0x67da600f	0xeb8fe821	0xdecace00
+	0x0c355770	0x3d28fc3c	0x2eebca24	0x4753b9cd
+	0x0b945832	0xf4120f6d	0x588409fb	0x15a94438
+	0xa727a943	0xa95217fd	0x0ded75a8	0x1a556482
+	0x767d35c3	0x9d96d689	0xe8c6df73	0xbf229244
+	0x12bf8389	0xd5dc4782	0x2b2bba74	0x53a49a14
+	0xffa085b8	0x314087f6	0x3e036542	0xa9517e8c
+	0x6b6da9d0	0x15dd4ae0	0xe7ce03db	0x7abff8e0
+	0x89fdc6ab	0x28ed5196	0x8c79b0d9	0xa80f7919
+	0xf121a584	0x9809d3e9	0x83cc73dc	0xa4e51962
+	0x370d9307	0xda518436	0x5ed4c7e0	0xe024a1ea
+	0x0c524b24	0x3bb0bbc8	0xb4cee95e	0xb2622308
+	0x1fc85d64	0x1e836175	0xd43fdb9a	0x39d05c71
+	0xf8bcc9fc	0xd33a53d7	0x9c4d3858	0x2fa63ff2
+	0x351e8720	0x32419c0c	0x8fe0b68d	0x326a8a91
+	0x44625b27	0x52b2716c	0x22eb5861	0xe1a87187
+	0xf5ff95b5	0x0e9a42c0	0x3700221f	0xda6c81dc
+	0x6ec82ed7	0xebbc013b	0x907b528e	0x71222e15
+	0x17bf4813	0x9d8577e3	0x325ad1bf	0x2f98087e
+	0x6656baa6	0xf5bd91a2	0xe5bf2aba	0xc2e16644
+	0x8fb13479	0x0a19eb78	0x80cab720	0x02889d26
+	0x81d32f06	0x666bed5c	0x58aba47e	0x9f36ec4e
+	0xa6f8a312	0xd50dfc50	0xda6ee1c8	0xbf2dbd1e
+	0x6dbe34cb	0x2ee1459f	0xaf3ba125	0x69453966
+	0x0cf984ef	0xbee72495	0x9e1befb9	0x9785668d
+	0x7861dc74	0x16dd92c3	0x9c39366d	0x376b20bb
+	0xb08d0942	0xd2415614	0xb5eeddaa	0x92f148b3
+	0xc1fdb0ab	0xa64e8a08	0x11e6d898	0x7e345541
+	0xd7d875a5	0xd396f516	0x8cdf8a23	0xb324f279
+	0x07382961	0x35e5b607	0xff378354	0xa61e6e1d
+	0xe7b6830a	0xe4022021	0x7230e616	0xe113b776
+	0x595fc933	0x7052027b	0x02525cc7	0x23637336
+	0xae0dabfb	0x46492daa	0xb57f5cc3	0x7f8ff15a
+	0x70126d10	0x6a6b896e	0x330654c5	0x3680f93b
+	0x04e705e7	0xf89c1eca	0xab401dab	0x7fad939b
+	0xc9d8900b	0x29ca3871	0x2931e4be	0x26d73a89
+	0x74c2602f	0x61920680	0xbf532c23	0xfbe87348
+	0x5ee7efcd	0x8228b6e9	0x404e6492	0xbd577535
+	0x1ae12b2c	0xff26b6cc	0xeac396f4	0x04102950
+	0x28a698a1	0x26ab1d9a	0x06f0e8d1	0x82eba335
+	0xbace28f5	0x7f7efab6	0xc9ef2555	0xc5b33992
+	0x74f481eb	0xcfc2a96b	0xbcabf5cb	0x118a80c5
+	0xf815ac13	0x06da52e5	0xd70f8c6f	0x54af4177
+	0x7890b2ad	0x20c1a59b	0x5d1e3c26	0xb0fdd3aa
+	0x53b8120f	0xfff85542	0xfa402307	0xbc0736ae
+	0x3b05c066	0x9e8794ca	0x075af678	0xc540a9db
+	0x40d0dcf9	0xa9bba474	0xebb1b883	0xff1f4933
+	0x97a47b97	0x321b2d6b	0xf01a64f1	0x7d571e58
+	0x8889079e	0x86077eb3	0xe9f91569	0xdf70fe84
+	0xc6bb5b9a	0xf648ed36	0xb75c1714	0x0438e727
+	0xb30d2344	0x6e972d08	0x45164e18	0x3b325aa6
+	0x5fb60f83	0x8e836a45	0x55a693bf	0x704da46a
+	0x0924a501	0xff86991e	0x55bef546	0x9f8b4aa0
+	0x91574c19	0xa3e712de	0x4f9c39a5	0x227962ec
+	0xaece98a3	0x717c7193	0x8bebd8ee	0x8a63eed6
+	0x8907428b	0xd6293e59	0xc4b12c7e	0xc8deb375
+	0x686f9d67	0x141838c7	0x45e4c565	0x814d20e2
+	0x140103b1	0xf88b55c4	0x8b128c94	0x449cd74c
+	0xe4ea1fff	0x9432845f	0x8e700f5b	0x148a70d1
+	0xd0d20a83	0x5422d311	0x4b2562fc	0x0002e6f0
+	0x624bce41	0xfb72d76e	0xaec8229b	0x8511a0e1
+	0xaf3358be	0x23161922	0x7e4a88d4	0x0792e30e
+	0xc29c52b8	0x0ee24229	0x9ec21326	0xa53a3904
+	0x0a3c0eb2	0x973b1d25	0x02884f03	0xcdac8153
+	0xa8f17003	0x2ab6a386	0x59057b41	0x2bc5d886
+	0x86e91ce5	0x7211383c	0x06e20628	0x09361cd9
+	0x8128d9d9	0xc21195c0	0x43f63562	0x46d05de0
+	0x7ed2ef09	0x65ab5805	0xb6963bee	0xa1873132
+	0xf9998e7e	0x84ff6a0c	0x00fa22b5	0xc84432c6
+	0xae963ba5	0x80660ec9	0x2c25ca27	0x17b0b858
+	0x935459ff	0x6dddbdfb	0x418d3c0f	0xd3c6b5af
+	0x1e19e0a1	0x720d5e50	0x0ec48992	0x577c29ff
+	0x5837580d	0x0a7bd481	0x3f13a685	0x96b9ef69
+	0x977ead5e	0xa3e4ae2b	0x96f97a6f	0xd93d0904
+	0xdd5128c5	0xd2a00577	0xc1e6b315	0x175f49e8
+	0x79a4afad	0xa6d864a3	0x98d68c49	0xc54d1d7f
+	0xa0031e9f	0x82580ab0	0xe8567a5f	0xd853d485
+	0x0704e3ca	0xd8afbd7c	0xfe0ab692	0xa8dcd22e
+	0xeb7f1064	0xe565a37b	0x0f429464	0x94df9a46
+	0xb4a43a3a	0x85e7520a	0x828f17d3	0xe404df1c
+	0x02a24101	0x107347d3	0x64eb1552	0x127f2f6c
+	0x8722ba2d	0xb0e56339	0xf9ea6f68	0x80a535ee
+	0xbbc273e7	0xaf777c05	0x8638b501	0xb855c346
+	0x3c0a200f	0x280d2842	0xf727be3e	0x9d322582
+	0x71cf64f5	0x8ac26843	0xd4e8cba9	0x41b357d3
+	0xbdcbde9e	0x606b63d5	0xc793a0f4	0x729b875a
+	0x6a8f1a7a	0x5e0c326c	0x40780713	0x0ae7bb36
+	0x84184229	0x583b1e87	0x2c931de0	0x34d75344
+	0xd38c92ef	0x6a90cd78	0x4442aa32	0x48ce80eb
+	0x7419f27d	0x1f6971c5	0x94f2a389	0x38c4009b
+	0x3b663629	0x19adf150	0x8874214f	0x08a52607
+	0x946fcf9b	0x27c2cbaf	0x2969f147	0xf8fa352c
+	0x5422ac80	0x732d4b75	0x9c44517c	0xdd5e855e
+	0x24325f35	0xb56ff386	0xf2eac65c	0x09382b69
+	0xd6d63436	0x00b3471d	0x9cc6bb3e	0xd64770bd
+	0x4fee58cd	0x400cecfa	0xc9bbf876	0xaa4becb4
+	0x65d693d3	0x4ebd85fd	0x5274bf54	0xc28419ef
+	0x019bd1ce	0x8828234f	0x2361215c	0x9c996c26
+	0xde0560da	0x3be8a4c3	0x63f1a25b	0x1f3db503
+	0x433fcba7	0x27bdf9db	0x9e75e926	0xfa9a0c86
+	0x93144220	0x7b5c5dfb	0x831b0bba	0xac237612
+	0x9125e97d	0x18bc3d44	0x187e65d6	0xa7f1e29f
+	0x4949a362	0x49490a5b	0x9fd7f5c9	0xd4aa1ed0
+	0xae02d433	0x3c8a1c45	0x74aece0a	0x9281873b
+	0x74d67c84	0x7c3ce8bf	0x42d390b2	0xe1b67960
+	0x924c912b	0x39db2dd8	0x0fc0daae	0xefeb1793
+	0x86933e2a	0x79dc30d5	0xd6093f15	0x69c3e88d
+	0x4b4f4281	0x5aa01736	0xc6d4be3b	0x9e961328
+	0xe7c9d7f3	0x4cf1cfe3	0x2b7d0cb1	0x018e150d
+	0x15780565	0xf076db48	0x63c70787	0xcaa9d201
+	0xfb417ce2	0xba23b25c	0xc54e1651	0x9bf2a3c8
+	0x8bed1da7	0x842a94a0	0xd5a7eb11	0x06913cbd
+	0x4620eb05	0x76076fe6	0xfe87a105	0xcac81f51
+	0x9ddeec05	0x83ae9c88	0x682fb66e	0x71f2eabc
+	0xbab703ff	0xab9d687e	0xcbe35917	0x5976ce5e
+	0x0ef568be	0xdd8a23ab	0xd1b94ce9	0x14d47a65
+	0x0a21b6d5	0xb2cabc60	0xab6fbe1d	0x55ffee0f
+	0x59509606	0xf353d47c	0x83ae774a	0x3666736a
+	0xf5fb86ee	0xa1aeb0da	0x1d826dfd	0x873340a2
+	0xc1ea76d1	0xe05c76af	0x2ee20af9	0x27a1d100
+	0x9c4a42cd	0x0c44fe38	0xeff8de27	0x05ca0de9
+	0xe95f6fa1	0xb7bcff23	0x5c523206	0x4f31cdc5
+	0xbfe4910d	0xb1b1c09b	0x7f947c52	0x5cf70669
+	0x5be2fccc	0xf0f52eba	0xf8891b30	0xdbcd2578
+	0xed18f963	0x6953d3f0	0xdbc69319	0x4ac03f2e
+	0xbb073adf	0xbac8210e	0x3f7454da	0xe250ff05
+	0x53fe6a2c	0x9b096e66	0x0c2b33be	0xc9a66cc8
+	0x25fdfa7a	0x211597d8	0xdac355c6	0x3b0b8086
+	0xe1cb957b	0x34ead4b4	0xaaaace1d	0x45470209
+	0x4afe8bab	0x1f383d95	0xc4eb5e38	0x3a4adec6
+	0x9b68485d	0x0028ac74	0xc892a7ae	0x112963c8
+	0xedfbfd1b	0x9bc2a1e7	0x77e86452	0xf7285e2d
+	0x5165641f	0x0be144bb	0x26f32616	0xa889df07
+	0x8de11d0c	0x1ae8026b	0xa40c0afc	0xf66e6b1b
+	0x2f3a3959	0x0f96159e	0xd383fa2c	0x6d8ac6f1
+	0x77e3e042	0xe9d05a47	0x3483a623	0x0e13671a
+	0x8afb2f74	0xad1ee74c	0x2008e340	0xf5b7fe4d
+	0xbd46ec33	0x4cadba9a	0xc86ee5e5	0x12a441bf
+	0x8700bd26	0x1677d9a5	0xbb5299a4	0xc03f06ff
+	0xc015876d	0xdf3ae9d3	0xebafa8c3	0x7407fc93
+	0xc13c4432	0x5263ee0c	0x85b4cb87	0xe95c88fa
+	0x812ba6fd	0xf117a989	0x82a07176	0x1051b99f
+	0x3998d57d	0xa182e824	0x26d164ad	0x47244eca
+	0x436b2d02	0x5690b951	0xc4a2b7e5	0x9c3f4d63
+	0x9d5771ca	0x74bff8cb	0x3063c36d	0xc6624e63
+	0x93cfbdff	0xa392d1a7	0x8917d687	0x542dca54
+	0xf930db3c	0x530a62e0	0x6c3139ca	0xc733bbf5
+	0xfa22ff43	0xf91198d2	0x27ebc843	0x6fc4a872
+	0xeeba081f	0x71d8a984	0x2cbb615e	0x08f28f4d
+	0x2c242252	0xde7bd041	0x5e337eb6	0xdd6a8653
+	0xbe10c145	0xfb5c313f	0x9c8be692	0x3e9c4715
+	0xd3a028c0	0xd87cf41b	0x2d7ce48a	0x3527909f
+	0x2fe5a866	0xb8d7d44a	0xdeea8a8f	0x7e39ca58
+	0xaac93e0a	0xec7dcb33	0x0ddf07db	0x024c82f9
+	0x4c06c528	0xb1c9bbfd	0xdea798d2	0xc0518d93
+	0xf9309f76	0xe3a80954	0x5f5fc8e7	0xe42ce642
+	0xc13a067b	0xeae08cce	0xbf7a70a0	0xc23e36fc
+	0x57b7e071	0x74b9fd8b	0x49cc2ee7	0x566ae6f2
+	0x1a566458	0x0fba6473	0x207838e2	0xf830c013
+	0x2ad8f7e7	0x4a962bab	0x5656179b	0x50edfc20
+	0xd7eceadd	0x19833983	0x0ac98913	0xc78e1e72
+	0x22626a8f	0x07abac2f	0xbf64e3b9	0xd6e2be8f
+	0xf3bd33f4	0xc1d727dd	0xe6ab80c7	0xe01d5026
+	0x0b9f81b1	0x167d09db	0x168f9fd8	0x270f1384
+	0xeeaf0e65	0x33f0c489	0xd3871743	0xd885ee70
+	0x49157f15	0x4677fd7c	0x06211cc1	0x4dd6cda4
+	0x92f0e059	0x8bd2481d	0xf580ab05	0x74cea2fe
+	0x0972a039	0xe362b4a9	0x18a688a6	0x32eea77a
+	0xb4b28ba8	0x366b59f2	0xfd04f522	0x97cee744
+	0x455e8819	0x2db1da4b	0xb2ac81ad	0x85868d24
+	0x91a9b381	0x2ce1ae15	0xc8261a26	0x3c314755
+	0xf57d98fc	0xcbc1eeaf	0x26a2423d	0x3e4b57c1
+	0xd411d2c7	0xfd70ba8f	0x42940578	0x1fffe7a8
+	0xa34c60b5	0x8fe0d771	0xeae9f523	0x928d2b17
+	0x6174105b	0x42e3ab20	0xfc8477d0	0x0ff054a1
+	0x2896b26c	0x33fc61cf	0x5b8097d5	0xafd8a429
+	0xf18e6b50	0xcdc292e9	0xa2846d37	0x82656479
+	0x05e34533	0x3cc6434f	0x5a132ede	0xb2b47148
+	0x2380b9fc	0x6413dca9	0x3609f82a	0xbcfd5ce8
+	0xa234f6a1	0x70c158c2	0x8d516132	0xf8ffa8b9
+	0x39629663	0x361d3077	0x54d3a1d5	0x5c78770b
+	0x0d12c667	0x200ee0a0	0xb4c5494c	0x417161ad
+	0xd641d326	0x7e6c924e	0xdcb14454	0x52ec57a9
+	0xbdb8a491	0x214411c6	0x0f7aa41a	0x219a4610
+	0x77aa93a6	0x9f260e58	0xab671d2d	0xa738db71
+	0x3b794aba	0xd4d96e58	0xf4234dd4	0x119417e2
+	0xcc18e115	0x28abe734	0x2e3364f8	0x0eafdb5b
+	0x9a917e82	0x6c49a8c8	0x41cd3d33	0xd4d4c8dc
+	0xf2fdd3b7	0x9f033d83	0xc6383f73	0x615ab71f
+	0xd59d74b9	0xfdb24bd3	0x1a2b929e	0x9850abc1
+	0x06ebadb9	0x452d5748	0xd4dbd979	0x319b06e5
+	0x8cda871e	0x4c4d8acf	0xa65d3c10	0xceb80135
+	0x6362f88c	0x588c3cbb	0xc92e07a6	0xdf156666
+	0x5776a8dc	0x24615805	0x78a31c47	0x0a8e2897
+	0x924e21ea	0x3c9e4844	0x8beb8379	0x1a97c923
+	0xa66ce316	0x19b2520f	0x613db392	0xde86323b
+	0x6d986a88	0xcaa79411	0xe5236511	0xdcb10401
+	0x180e3dd3	0xccd3566c	0x34fe6a8c	0xdca4d272
+	0x7dc2d6b7	0x3445be9a	0x60ab92ae	0x973b90de
+	0xa0819660	0x3f3da862	0x7f948121	0xe35d655f
+	0x1f974969	0xd77e51db	0xbcac7e3f	0xc2e5ca0d
+	0x4a0fa8bd	0x3089fa79	0x5038a272	0x1309f923
+	0x2e2615f2	0xb1b51edd	0x6c74acb2	0xdc1348ca
+	0xf72c0596	0x7fc0ff17	0x23d5de89	0xe57f53b2
+	0xc2c3bd15	0xeb38d68a	0x0f5fc1aa	0x048aceb3
+	0xaf834119	0xb87a70cd	0x6f55c303	0xe805dc32
+	0x428f2215	0x8c1fe4a2	0x60f3f83c	0x958b6397
+	0xe1636adb	0x2d664743	0x407145a1	0xb99881f5
+	0xe69cdc72	0xf9ea8ca8	0x10990d7e	0xdce842e9
+	0xf516bbbb	0xa135ecd6	0xadbf1a3e	0x894687d9
+	0xa7f833a2	0x7c28a41f	0xb2bae9e9	0xb601eb62
+	0xd15f1fb0	0x812f61cf	0xe3833aa1	0x9dbeef8f
+	0x44020023	0x8dc8bed3	0x89319828	0xfd2eb018
+	0x00fedd3e	0x484dfa16	0xf7509751	0x5efe134d
+	0x30e92cba	0xd3d915cb	0xe2a6ea2e	0x6980c6f7
+	0xbaa228cf	0x439a0d8c	0xfb7dbfcc	0x482b24f1
+	0xe7de15dd	0x2fbfba0b	0x32ff4379	0x6d3235f5
+	0x643c45ec	0x271b652a	0x89e7ff62	0x0ab8b2be
+	0x09378021	0xce24e1e2	0x6565cf41	0x6f72e9d1
+	0x8767b9b2	0xa07dee1d	0xfecced65	0xf99321f0
+	0x8005ef02	0x842d1c6e	0xcd2c837f	0xe3614a4c
+	0xec977891	0xe632b995	0xbea82e41	0xd31418d5
+	0x96608016	0xa7ceb9fb	0xb02cb3ea	0xb0343ccd
+	0xacc278bd	0x142e4f1b	0x3d233a7f	0x4af4c3db
+	0x85279e02	0xe7b8cf1c	0xfa9bcc8a	0x72b8902f
+	0x7f45fe1d	0xb2726325	0x9c1d71f7	0x83935b50
+	0xa136f758	0x396424e4	0x674c2a3b	0xb8077412
+	0x547677bd	0xc47f916e	0xb4c3357f	0xd1147d60
+	0x228303a1	0x97d7b3e1	0x355d23a5	0x778f2f18
+	0xa20d6acb	0x7062246d	0x04aad4d3	0x4696f496
+	0x1000ac5b	0x5005eea8	0x51a26d3c	0xd782018b
+	0x65eeee7f	0x4a37d244	0x8d5c78f5	0x4276c06f
+	0x7b051c97	0x340f3f54	0xc818f340	0xd5436752
+	0x311d7cee	0x87f1ae54	0x77c99d33	0xcf913f56
+	0x97a1faaa	0xfe3a1719	0xba390f82	0xb715b00b
+	0xddfa1183	0xf3af7c0f	0x8601aa46	0xd18e0cbb
+	0xff036109	0x4985dbbc	0x4ed2596b	0xaa4dc69c
+	0x707e2300	0x51d4ed57	0xceef773d	0x7b70150e
+	0xfe007480	0x000041fb	0xc0fb79a8	0x437f1ab9
+	0x7fb711e5	0x833c06f9	0x064f9291	0xa9c5a76d
+	0x402383f9	0x9a5b6de3	0x5fdd7c09	0x69c57f17
+	0x243a4d39	0x4b91a17a	0xadb16f23	0xa95843ba
+	0x52dc3827	0x5c15f379	0x76f0179a	0x65792a3e
+	0x5becc4c3	0x879159af	0xdc96e7b4	0x81c96a72
+	0x9cc3ef98	0xc9a03721	0xb5e0e950	0xba46151d
+	0x73522da1	0x8e5f8e26	0x0ab8c9a1	0xb9e86fd6
+	0xb133c5fb	0x0605aa96	0xadd00ab0	0x759b6321
+	0x7f9d9ef8	0xdb242bb2	0xa4b339ad	0xe332a5e7
+	0x66d52605	0x3a03f318	0xff0d15ae	0x1db610dd
+	0xf65b1039	0x97be3c69	0x22a104ab	0x4a6c1b6e
+	0xc1bc3435	0xd57c4c33	0xec1a3ca2	0x5161f419
+	0xb2cd0cee	0x71a394dc	0x94c23225	0x42b398ad
+	0x29164e15	0xfaad2b2e	0xca59ad9c	0x360a976a
+	0x0c8d7304	0x8fd6ac30	0x684c3d63	0x564defb6
+	0x265b343e	0x22158f4b	0x354cc488	0xb5059d68
+	0x014520a1	0x6c493ce9	0x221166bd	0xdea1f9e3
+	0x2f69ca64	0x9c3ce396	0x7d1a5f8f	0xfd6a57c4
+	0x8764c0ec	0x41e15814	0x35c1bad6	0x2c539519
+	0x65087c3b	0xf5b3830c	0xc2bc2993	0xa1b3cf19
+	0x576391f6	0x5ce0cc84	0xab879f90	0xced4619d
+	0x19b6bd51	0x355d2c3c	0xa4133356	0x8a0e318d
+	0x535b8cc9	0x35660d4d	0xbca8d6ee	0x32215f13
+	0xde46d9f9	0x982ad7db	0x9f7eec2d	0x5282abc7
+	0xddf348d7	0x43cd6a3d	0xd63c9cca	0x7ca44fa2
+	0x0bc2f640	0x97498df6	0x30501800	0xd61520cf
+	0xbe3f76b1	0xa25a0c07	0xaa57867b	0xc0315c66
+	0xf4310292	0x21811c11	0xebc3482a	0x3a7b6e50
+	0x9cf2d841	0x92f00e94	0xefba5af9	0x25d2d9cd
+	0x737be378	0xdce27210	0xdf16478e	0xd9e45484
+	0xe402d70b	0xd797db64	0x03fe0e77	0xa89c88d9
+	0x09f22ee4	0x729caf19	0x23290678	0xa4bb622a
+	0x8730fe6d	0xb71f3eb2	0xb48452d2	0xe6dee29e
+	0xb91933b9	0x2a4ef477	0x7d5c4791	0x8b35cf57
+	0x3f1a49a4	0x3f585ea9	0x4d3d06a2	0x3531f766
+	0x4e9314ab	0x82e165b1	0x9b0493c3	0x898c6db7
+	0xdb53b9a8	0x266dd07c	0xb2be18e2	0x1ba50fca
+	0x7cf32c0e	0x227afc92	0x52c76fc4	0xe7f17624
+	0x0cf1789e	0xb1adfa4d	0x67773b86	0xcd46a6a1
+	0x3c9ea75d	0x73d3fbe7	0x7b0d0b80	0xe88f3ddf
+	0x20bd2842	0xb67a3c9b	0x0b3db9b2	0x62fbbdfd
+	0x76df2365	0x4b2bff0c	0x9c26c9f8	0x26079266
+	0xfc18b24e	0xc38a4fd6	0xd45ce2e8	0xb30cbcae
+	0x0f80fdcf	0xf2e8adfb	0x11f4bc7c	0x98102829
+	0xe40358f3	0x50d35ad4	0x117432cc	0x4e6fce32
+	0x695d7b3e	0x98d28a2e	0xe570db97	0xc015fd81
+	0x137f73dd	0xab23d5f1	0x7e8c0e6e	0x72a1a57e
+	0xe58cfb67	0x604f84cd	0x43ffacb6	0xae73cc50
+	0xab34f299	0x0b3035d0	0xfe214b74	0xed2a8168
+	0x3da3450f	0x8e51b78e	0x253e72b7	0x8b620f54
+	0x8b63af50	0xce340e10	0xbb419809	0x5ba00635
+	0x42493b0b	0x8ee85bd3	0x49b6a7df	0x808fea2b
+	0x091c809d	0x0cc496db	0xea6642fc	0x601d5000
+	0x3589e04b	0x714096d2	0x4e55569b	0x1c45121a
+	0x04a6050d	0xfd47c074	0x57269ffc	0x3e06836b
+	0xdf8f7d43	0xab671a69	0x0d0df4dd	0x54a67c89
+	0x92d408a0	0xf378abb8	0x214d6425	0xd91d7194
+	0x6dcc9cdd	0x02d27ea9	0xd4d4a4e2	0x7bdf848f
+	0xaa4149c3	0x9df0d2d7	0x8800c904	0x192fd5f5
+	0x10dbb590	0x5b8b1e2c	0xd5b5dad6	0x30ddbf84
+	0x405edb23	0xcb906b8b	0xd9a124c7	0xe7ac7fb1
+	0x2a7a4ba5	0x90fe1e2b	0xbf9323e3	0x50469643
+	0x16c8926c	0x6dff898a	0xd56a03ee	0x29ee3e30
+	0xb1893885	0xdc1e2e0b	0x87cedfd0	0xe458d4b5
+	0xdb878d28	0xd151d52e	0x6e5aad6f	0x0ccc8b2a
+	0x5a1fe08d	0xed61dc74	0xa4649fb0	0x670c43b9
+	0xd7b22c7a	0x4fbfeee6	0x77341a4a	0x28b2f3b8
+	0xd81079dc	0x9a81c4ad	0x1dcebd98	0xcbee2e9c
+	0x746399bf	0xf3383a23	0x5c5468e6	0xefadf365
+	0xc2a7a3db	0x08c1c628	0xf14191fb	0xbbde23aa
+	0x47f7c782	0x357b117a	0x2c2a92a1	0x87ed1511
+	0xa8d709e8	0x7de8749b	0x92199870	0xb8017e07
+	0x481b9913	0xf1a31212	0x5fb4f7df	0x07e246e2
+	0x274c1754	0x14fc9659	0x2513158f	0x4f8639b4
+	0xa602189b	0xbc1e3f31	0x311ff0b7	0x5ca7c9e1
+	0x49747707	0x350cc8ac	0xf6bf896f	0xdc0bc1ac
+	0x1f0d3ddf	0x21a21a62	0x80711ab4	0x60f70fe0
+	0xaa5ade5f	0x914eba42	0x0fed2bc8	0xaf4d97d1
+	0xf294b5ed	0x24ec5df9	0x66db067f	0xfb2b6ce1
+	0xce42c8b3	0xfb027c19	0x79447655	0xf0673adb
+	0x72befbe6	0xb25247a3	0x0813dc37	0xe640e10a
+	0xf45759f6	0x328aee51	0x95d537c2	0xd2de2137
+	0x30327a18	0x9e934258	0x5f0dfd3c	0x34b88261
+	0x5ca0fc63	0xd4ff6e27	0x2f287435	0x38be55d3
+	0x3590bf93	0x6497ddca	0xb48bf82d	0x3aa7c943
+	0xf705e627	0x2ecefc01	0xe85a739b	0xd91d2b1a
+	0x178dcb38	0xded1e432	0xe119864d	0xec965444
+	0xb6866cc7	0x84160d5f	0xa72c6b30	0x78223f8e
+	0x303132db	0x00f10c7a	0x6238a0de	0x9217bb53
+	0xe0313377	0x318ebadc	0xf9854726	0x632b2df3
+	0x16ac7842	0x2c0958df	0x49a879ac	0xc49f1fe9
+	0xa3e7c05a	0x811e01d4	0x9b11ccf2	0xc32eb57f
+	0xefdfc729	0x38fb8cc3	0x6781c78b	0xfab82792
+	0x08da3c82	0xaf0346f6	0x6588d336	0x06ae489a
+	0xb58419ba	0x771f3fd4	0x53f42a79	0x0653504f
+	0x93330a58	0xcddab350	0x2d44eda6	0x7860152c
+	0x63b3e12e	0xaf7dc6f6	0x5cc5ad4f	0x95b9d06e
+	0xddcfc613	0x84f74de5	0x51694312	0x1950051d
+	0x62cc7724	0x06742036	0x92e8805f	0x679a3c64
+	0x87b8f43e	0xce386713	0x5b476587	0x300ca68b
+	0x7d2fa903	0x552489d8	0x25ead402	0x8d0cc96c
+	0xb5c5ee96	0xf0b74e97	0x999b0e56	0x217d326d
+	0x45edc298	0x5d269e37	0xc88487f1	0x27ef568e
+	0x833ff6a2	0xf832552b	0x5a56b672	0x21379d3c
+	0x5de123ed	0x1617159c	0x666699f2	0x165b3fc5
+	0x04a8177e	0x9412ca1e	0x196a603a	0x752d8a13
+	0x46bd8094	0x200d93cd	0xe6f9002a	0xd2444774
+	0x29aee76a	0x13d6cb75	0xc947e68d	0xbfea3352
+	0x2fbbf62d	0x89dad4df	0x0f771fcd	0x2b5c3135
+	0x658aac69	0xe980266e	0xaa657242	0x8440f399
+	0x19ac2617	0xe74b3e55	0x9639c72c	0x25bc2843
+	0xe5428269	0xb06b7e52	0x47e3f96f	0xc3ff329c
+	0x7e428457	0x3b877e30	0x824d6981	0x8d66bccd
+	0x3ef8b239	0xb90ceaa8	0x5323ddd1	0xfd9f9711
+	0x747920e0	0xe64253b6	0x7bd26403	0x1cc2ad5e
+	0x51612252	0x39d671d7	0x5043d9db	0x4c1d9cd3
+	0xf1e48340	0xb68e5148	0x77d7ee51	0xb345cb5a
+	0x639e92e6	0x458cb2b0	0x2cb49fe4	0x01683f64
+	0xbeae5114	0x20d167c3	0x8439bb31	0xaa11d7f3
+	0xdb14315f	0xc474fe90	0x2992dc24	0x8ed70fb4
+	0x73228ecf	0x016c6e08	0x9bf91825	0xa13662f4
+	0x86a759da	0x0cb6d6b7	0x43d67df0	0x2badff1c
+	0xd1769bfa	0x0f5aefd4	0xbe2e49b0	0xa6e91ea4
+	0x046c73fd	0x38b33892	0x37a3ab24	0x30225f43
+	0xb4e9d784	0x0b8d3c79	0x83411221	0x0080586f
+	0x0383f4d7	0xb4733a71	0x4609dc6f	0x149e2be3
+	0x16be8f2a	0x6155a89e	0xdb42ebbc	0x4790004d
+	0x0b84706e	0x24d8e7a7	0x7434cf91	0x4aa01729
+	0xb285bf41	0x894256a9	0xc346c2ca	0xcf83c38d
+	0xd7a9df68	0x61e95cf5	0x05458abb	0x2468d516
+	0x6cfc6f97	0x06792edb	0x0faec9e3	0xcece2cd5
+	0xfcc300d4	0x93b52c8b	0xf9f81fa4	0x8a9d62d0
+	0x94715de5	0xcc4f5ae0	0x724c65ed	0xbc9d2513
+	0x3ff58f0e	0x2571d254	0x1b2f8fb2	0x593ff054
+	0x1542e7fa	0x5e2b8733	0x135f62d2	0xe5b8f1de
+	0xee3852fb	0x9e1bb2ff	0xcfe6ef95	0x85e3d35e
+	0x5fc2f0e4	0x1e391bc0	0x0c282cc5	0xc14e84a3
+	0x4a566eaf	0xac04ab06	0x15e9bb8c	0x74a82932
+	0x615af08f	0x92ca2937	0xa04182e1	0x8964f936
+	0x9c00cfec	0xf8ee661e	0x60c0bfe4	0x9d1c2a39
+	0x164f0f50	0xc1cde961	0x1ec2dbab	0x441312dc
+	0xff8f746b	0x4fd8e2f4	0x7d41bec2	0x610c39b8
+	0xe54eb811	0xed6eb997	0x6aef9b63	0x2ca1fa79
+	0x6a0741bd	0x9b323ed4	0xa9e51346	0x4c7c19dd
+	0x980117a9	0xba0a00c4	0x501e433f	0x3010f10c
+	0xd7cf710d	0xf03ab992	0xa9df2b11	0x2939a708
+	0x90182f87	0x2f5c228a	0x7982d287	0x4cc9aa36
+	0x4db0ac5f	0x2d5eb58f	0x78029b74	0x9e592313
+	0xac57236e	0xf5d3ba18	0x1310184a	0x0291a22f
+	0xa2bcae47	0xd4aafc4d	0x50f97087	0x9f428c85
+	0xe8b1d16b	0xbcf3cc24	0x2febcdef	0x8baaf25d
+	0x4839894d	0x713618c7	0xc6b4119c	0xa72804f7
+	0xf9ed3930	0x947ab473	0x52ba8d8b	0x9d3ef240
+	0x928262f3	0xde8a2e3e	0x0dd1a3bb	0x124cb146
+	0xbff6b771	0x8768185f	0x9dcfc72f	0xec46ce1f
+	0x55eb08e9	0xee110630	0x4f1abbdf	0x790d96fc
+	0x0edeee84	0xf4effcfe	0xf171d08d	0xf0ea076d
+	0xcfc6bcbc	0x2df2d7a3	0xba1a967b	0x1cea509a
+	0x1594c0cc	0x08339c8f	0x8633f7ad	0xcffdc9c1
+	0xb620cf8d	0x3807a89f	0x6b992761	0x222d9a95
+	0x900f8f87	0x0f085c6c	0x5ce2975f	0xfc2d28e0
+	0x1f1e2d6b	0xd2af1514	0xa3cc5dfd	0x301cca91
+	0xb02b1b87	0x070126f0	0xa18820db	0xaeec06dc
+	0x7f12ad58	0x79c8c8ba	0x173b231a	0xd52de2f0
+	0xdb67eb9e	0xd50fd00c	0x1767d59c	0xe83c1fb0
+	0x3d079a0a	0x34aad1b7	0x8e410684	0xd17f51a4
+	0xadadb74a	0xcc20b073	0xce1fc8e2	0xf9faa5e7
+	0xf7b96bfe	0xf1dc7007	0xf2a5df74	0x3036f630
+	0x0fddcd9b	0xd3292ad3	0x2e565365	0xa0bdfdc8
+	0xcea1dfaa	0xb161265e	0x28e1b5e4	0x6b718da8
+	0xab2fd7cd	0x06cf49cc	0x00db7d65	0x6bb855c2
+	0x6c58fb02	0xc34b1948	0xbbb039a9	0x7df185a1
+	0x323d797f	0x1f21b9d4	0xf63332de	0x03d84887
+	0x8dacb69f	0xb33e6158	0xf378a088	0xcdf7408d
+	0x9d54f759	0xc94c5d13	0xdf657953	0x77f8dc3f
+	0x432fb39d	0xedef8db3	0xd8443326	0xa06eab9b
+	0x77029612	0xcd729e14	0x3d1b4677	0x07c424af
+	0xf599ada6	0xb0eb8eee	0xd775afea	0x3013ddbf
+	0xe9d06eef	0x09600082	0xe8cd4c2a	0xd3ff4417
+	0xfe29cad1	0x2173b541	0x33585437	0x769344c8
+	0x02de5ca2	0xf5206b44	0xf3e34d41	0x6deba140
+	0xa79632c6	0xc9ba3a50	0xb3515fa1	0x9eee380c
+	0x4ad5290c	0xcb4739c3	0x71da64eb	0xfb559aef
+	0xa3091f65	0xfdef610a	0xce5412ec	0xcf498deb
+	0x26e1c1b3	0x2a8fb23c	0x0695459d	0x5a4c277a
+	0xdd483fbb	0x1a78ddd3	0x24c0c414	0xaa24b351
+	0x20c848cf	0x94dd1387	0x0fb0016d	0x9e1b83a4
+	0xafe2c58d	0x596d1cc6	0x42376363	0xa6b0a5ac
+	0xa6c30abd	0x067d634f	0xf921e454	0x1e86e083
+	0xb5986bd4	0x3e4e7b76	0xe02427d9	0xf39df942
+	0x77f82cee	0xd7cad721	0xf884ea2f	0x0247e300
+	0x4dcfd3ec	0xcd3595ab	0xca789c58	0xfd6f4b59
+	0xf39a1fb9	0x60d80d9c	0x67dc447d	0xd061e922
+	0x5c4ddc32	0xd87a0e11	0xec53091b	0x88f73838
+	0x4a30fbf4	0x77ddf719	0xec903563	0x1103cc06
+	0x38d36baa	0x6e7822ae	0x7e238d27	0x9f10f184
+	0xdc571ae9	0xbfe5a7be	0x60796471	0xe7193642
+	0x8f4932fb	0x3288ea54	0x880b61bc	0x6f5adeba
+	0x88078ffc	0xf53a7321	0xda5f397b	0x797d53cb
+	0x170023b2	0x2ae674b8	0x41ed6927	0xfc416bac
+	0x9517d112	0x8131bc8b	0x9207340f	0x0860f495
+	0x5ee42625	0x21abd2f4	0x730cc2bf	0xb705d5a7
+	0xb0ceef46	0xa9e1580f	0x04379973	0xbc2de3f3
+	0xbbf47518	0x8135e690	0x7dcaa849	0x2d284fcc
+	0xdb956dc3	0xa01dcee4	0x204879a0	0x25d4ec0a
+	0xab883c9b	0xf4c98ae4	0xd6ff96c8	0x1c44bb4e
+	0xefc0ce75	0xa018f744	0xf3b708b1	0x5219e162
+	0x03c478dc	0x56de45d4	0xd16b9680	0xf3809c02
+	0x3078072b	0xd1b792b0	0x1dc53f6c	0xf39f77ee
+	0x74db19ab	0x2d9772bf	0x1d117036	0x8439e76e
+	0x15550137	0x9378cce1	0xa3007b8d	0x44246b55
+	0xe27a583c	0x93fbb9d2	0x14b875ab	0x58ba4172
+	0xf70336a2	0x1a193fa6	0x6edd7c7a	0xf9d7abad
+	0xce49c41f	0xd59e4f0a	0x87c209a9	0x6c531d65
+	0x5e8b2912	0x4985e164	0xaa30d916	0x04c7a98a
+	0x92ec0a16	0xc81e0c8c	0xaa7fbc60	0x73c9997e
+	0x1080f5ff	0x05824cca	0xa465ca7a	0x4e7aec8e
+	0x5e230d7f	0xbd80153f	0x2f9fc7a6	0xfdc2e4c6
+	0x8447f46f	0x2b98b918	0x934e2131	0x89e96a33
+	0xaafe33c9	0xe821a560	0x3a7c81b7	0x3905eae1
+	0xec902015	0x8b70db58	0xc6e5cfd2	0xfffeeb18
+	0x4b79d360	0xb7d2a21d	0xa6742dd5	0xc38a9ac5
+	0xe4f33f88	0xf7864b38	0xb937ed2b	0x286ea756
+	0xc7b977e8	0x117abf40	0xc52e4e8b	0xd8423c60
+	0x4edaf3de	0xca387d75	0xb9fbe5f7	0xda6f9543
+	0x29684231	0xfdde17b2	0x55d9da3c	0x047472cd
+	0x48aa5670	0xd0fc555c	0xb694d68a	0x225d0c82
+	0x65da3f2a	0xa8da5a72	0xba791eb0	0xf6dda6d0
+	0x6f408fba	0x0f3e53c4	0x42dfdd18	0x83afd9ec
+	0xc0c28641	0xe9aceda4	0x9a57bb91	0x509ae5bc
+	0xfab6364d	0xa965bb80	0xed52b4ce	0xa9637114
+	0x1ba06d2d	0xe2a071a7	0x4f8005f7	0xc01078e5
+	0x6c8c1b40	0x0d785131	0xf89f318a	0x7a859d66
+	0xa54c61ba	0xa1ac3829	0x5846abc4	0xa4bbee21
+	0xc150c513	0xc43e56b0	0x2b9b6c2e	0xbd23ac4b
+	0xd5bb877a	0x26aab6e9	0x3175a360	0xa417779e
+	0xceda5542	0xd6ac1111	0x3631f049	0x822d6fd7
+	0x456b5441	0x14815178	0xf26c6347	0xcb2f0ac9
+	0x2876a89e	0x5d77052c	0x1dd9903e	0x1a243b17
+	0xd32ff417	0xf2ee16cd	0x29c1e28a	0xab23c5a1
+	0x7bf92552	0xb3ff18d6	0x7218138a	0xfc4c7fb0
+	0x8b431515	0xf42dc92e	0x39c27b33	0x5439b8c4
+	0xa044cf7a	0x1904dafc	0x8334b7b5	0x5285f6b1
+	0x64cec961	0x90bca178	0xe3108fb7	0xa0f64d12
+	0xf1bb4b0e	0xff22ca3d	0x455af526	0x45398675
+	0xac6db8a4	0xdd6b3cdd	0xd93e0ade	0x6407f4cb
+	0xe1434f7a	0x5048390b	0x9ecb584c	0xbaabceb3
+	0x592859c7	0x0b6dbd23	0xf5579ec8	0xfd372708
+	0x8d306020	0xafda0c88	0xe93bbcf9	0xeb0f3a50
+	0x8a0e1c30	0xfb926ba9	0xf628b5f4	0xbbef7f64
+	0x59bee520	0x8c95cf83	0xa9ff6a92	0xe8d43591
+	0xca0252b7	0x44311a65	0xa90c0287	0xd6769de5
+	0x647a9d7d	0xb3430eee	0xfc295b9d	0xfaa99965
+	0xfbc57eaf	0xcd1e38dd	0x4173522c	0x815845c3
+	0x2146414c	0x5d5c5b01	0x8a309fe7	0x6aa610e5
+	0xd102780f	0x89e6e565	0xbdac3838	0x32626179
+	0xa2a55556	0xca7a20a0	0x9e746a00	0x02726584
+	0x804f9c1c	0xa1edaa0a	0xe2a2ee7c	0xd1c5657b
+	0xea483c23	0xc6642eae	0x0a85bd37	0xf1f3be44
+	0xf82905bc	0xe412fc3f	0xf6bf0714	0xf91a7e1f
+	0x661f92e0	0x7283395f	0xf014d2a6	0x499044df
+	0xefdc70b2	0xb0f4e6af	0x75ef5398	0x08ecefe1
+	0x8be7f455	0x29b91faa	0xcd1622ee	0x3b4c3bf9
+	0xba7b11c5	0x0e4e91ad	0x29af310a	0x774115fc
+	0x7e6f4914	0x4ba6c995	0x211268e1	0x03b24064
+	0x558cc226	0x40d503c0	0x2af0591e	0x99792856
+	0xc5b667cf	0xd1e2cf31	0xdce9955a	0x061782c1
+	0x82b31a76	0x67bb7082	0xecab8414	0x0b20cf81
+	0xb8a21305	0x2bc2c62e	0xfb6a7ebb	0x598d2036
+	0x9f7f9f79	0xad9d6b51	0xa30bfc49	0xfec190dd
+	0x17fe7e3e	0xd020fbae	0x52ec37c5	0x6d9dfd4f
+	0xb4d1cf48	0x4d91b929	0x1b3e4116	0x81e109c2
+	0xe13316aa	0x8b49b605	0xd5c036d5	0x4feae27e
+	0x452760a0	0x308d5266	0x5af8ac2e	0x519bdab9
+	0xe2c88a12	0xbfe6a961	0x6e54bc3f	0x8143030f
+	0x5d47796a	0xe91fa496	0xd80e7e62	0xc5274d87
+	0xf0f7414f	0xd8a592cc	0x41fbae5c	0xdf848359
+	0x545f2e32	0x8650dbfd	0x116de333	0x5a013231
+	0xa9c16828	0xc103b508	0xc2230535	0x7167b332
+	0x7c0c8804	0x0a4f7a6f	0x3ef1104a	0xfa3401d3
+	0x042ba25c	0x05716cbb	0x88954de8	0x769902f8
+	0x93f8369f	0xdce3dc03	0x0f5bd13b	0x3417fbb1
+	0xe311cf44	0x8b6d116e	0x8a940805	0x53023454
+	0x2b608182	0x67424c31	0x9528932e	0xb4b69459
+	0x75308580	0x0d3097fa	0x4381d82b	0x75d297bf
+	0xda6c7f10	0x6adca79a	0xdd174f45	0x6e237e9a
+	0x5f17578d	0xea2869b6	0xd4ef7d60	0xdcf1e34f
+	0x39c0984e	0xca3cbf68	0x2b846994	0xf3c04152
+	0x58ad6900	0xa27a0473	0xa86814e1	0xb504c81d
+	0x0a263d9c	0xa21f5bfc	0x3634f89c	0xf2698fcf
+	0x0f10789f	0x580923ee	0xdd27aafd	0x49334c8f
+	0x6fc30ea1	0x535b6eec	0x103d548e	0x57681176
+	0x17152c46	0xf67cce7b	0xc6f1f215	0x763ec7d2
+	0x66f46032	0x9c7749b9	0x6ba3832a	0x24d788bc
+	0xcbe6ac21	0x1cc634fa	0x06b8d601	0x68b1c34d
+	0xef7a7f38	0x92c02580	0xfd5be079	0x67ec014a
+	0xda6a5b4c	0x9c884cf2	0x2e0cd606	0x1cb05866
+	0xf333f9be	0xd5585da9	0xedcecefa	0xb0224027
+	0xb2511fcf	0xab2440e6	0x77414c23	0xdc9263a6
+	0x25926b77	0x6083751b	0x825d995a	0x10ce9058
+	0xd91e2b6d	0x76126062	0x5f28b9fe	0x8df86405
+	0xb6e5bb6f	0x8eceac86	0xd08d074e	0xff4ed3d4
+	0x5fa5cf88	0x53c405b4	0xc60e7599	0xc07ef3e0
+	0x4435a7a4	0x28c490fa	0x9140004b	0xdb19895c
+	0x25d05b82	0x53d58535	0x8a2d6446	0x3e87d549
+	0xd961b6fd	0x76f8b718	0x6f0fd68e	0x86a7da31
+	0x4fcac697	0xcb4385aa	0xceca1471	0xc9ea76e9
+	0x18a36661	0x8da1db39	0x02bdd85a	0x56b5f9a5
+	0x39bdf861	0x206004b2	0x7a780b2e	0x9512fc70
+	0x8e128f45	0x964b5d31	0xc60ad183	0x763695fb
+	0x7addd1a6	0x8efae2e7	0x57b23dfd	0x91cdfc82
+	0x203aae3c	0xca53b1ca	0x05388d1c	0x3d5715bc
+	0xba33759d	0x2d3470b5	0x3b36c53c	0xe38fb71f
+	0x4c37e926	0xcba524c6	0x00d65da4	0x9d0dcb37
+	0x3a291c08	0x81ee1ef2	0xce1ecb25	0x6e34393f
+	0x4c7f9478	0x7bfa3437	0x3cf9d845	0x900979e0
+	0x1ae6a7c3	0xd5b64d84	0x467a16e6	0x489a3fee
+	0x73f7a7b3	0x29d2d941	0xbbb6cf3c	0x7478de98
+	0xa4618be0	0xecd3bf7b	0x9ec7a549	0xd762012a
+	0xbfc200db	0x172876e7	0xe3686578	0x74a03861
+	0x499dd970	0xb3600340	0x17a21676	0xe4f76eca
+	0x413c2938	0xa21b445b	0x30e36091	0x095c523a
+	0xf30af4b4	0x236740c6	0xb6a50c97	0xc285f888
+	0x5c45b9f2	0x6d2e28a5	0x561afb4e	0x112576fb
+	0x7740b38e	0xfe3789e5	0x5099bd10	0x8e565b15
+	0x463baaaa	0x8b712085	0x99fbb7fd	0x8b415a46
+	0x517c8de4	0xfcc385fc	0xac9fd9b4	0xdb29a377
+	0x3494419f	0x825386fc	0x6eeaa91d	0x2f48dbba
+	0x4615049f	0x90530f6b	0xfd2ddf08	0x97ee1b44
+	0xeea55310	0x6802e808	0x116d9cd5	0x874699d5
+	0xb9ec222c	0xbbc6e9f1	0x339cda6c	0x32d2c15f
+	0x10f073fe	0x2c544e3c	0x518503a8	0x24b730a0
+	0xf252cc99	0x6518b218	0x771d5ff3	0x841cc2cb
+	0xd3870e5d	0x6b166d5b	0xef10e55a	0xc873d615
+	0x5531c97b	0x6a10a199	0x63158156	0x40740e69
+	0xed060c8d	0x37625a2e	0x939ccd42	0xd225f0c8
+	0x060be21a	0xab542cb2	0x564ebdad	0x6d0e949c
+	0xc162caa1	0x22560483	0x26ed1b27	0xc8fedf98
+	0xd7358719	0x7b219308	0x327139b1	0xfb660fd8
+	0xe2d4e408	0xf9019405	0x38e6c024	0xe6ca02af
+	0xdaedb8e2	0xa81c4fec	0xa163e63a	0x9469e3e3
+	0x8bd652d8	0xd9692460	0x61671766	0x566dd7d7
+	0xd4ea8885	0x9f7c006f	0x963a23f9	0xc2a2abc8
+	0xe3f08b74	0x3411628d	0x0d5d26ea	0x368aebf4
+	0xeb8dcadb	0x3573f8aa	0xd23cd73b	0xa9b3c7d5
+	0x3119a47e	0xa5354659	0x7e375817	0xc7b36bf5
+	0x70c7ba81	0xda84798c	0xecf9aae1	0x52423bc0
+	0xb848058f	0x5dfbc1fe	0x4bd58fc6	0x38dffde2
+	0x8f41473b	0x8f2e8d22	0x5ba888ce	0xe7496da4
+	0x46ec5aa5	0xbb8cf063	0x9effa0b6	0xa487f166
+	0x1ceb3e26	0x468aac4b	0xe006c9c2	0x97b79086
+	0x1e53d58e	0x4ef59d4b	0x4ecfbb2c	0xb6ecbec0
+	0xc82338ae	0x7db1ab21	0x24d1e3e5	0x04c19de5
+	0x376f474b	0x6369bdaa	0xd3220ffd	0xc05ee6a8
+	0x24c3a90b	0x34a6c61a	0x811ce30e	0x4dfe9d6e
+	0x12a85352	0x38014645	0x1c07851e	0xe9beb298
+	0x0ed63abf	0xd5b40ba9	0x7f83d8e7	0x7a53ae4a
+	0x7360dd8f	0x1be62e35	0x5511f901	0xfbb6afc2
+	0xf788d81b	0xecfb7225	0xacb286fc	0x148e9a49
+	0xac3ff738	0xa3f93f2e	0x47f89037	0xc3226d1c
+	0x9d349976	0xcd757aa8	0x2eec4d43	0xdd7e7c19
+	0xbe13b149	0x60b4013d	0x988966e5	0xa41bd486
+	0x2a364043	0xb7a77403	0x60188f16	0xd5a13b2d
+	0xebf92c64	0x8e82daa8	0xa302aa28	0x33bac63b
+	0xbeb1e4bd	0x27bd0430	0xbd8d35ce	0xd14a8967
+	0xa7016b70	0x8a6722c3	0x6ff26f0e	0xfa50fc75
+	0x59e52041	0x339151c0	0x9c4a41ab	0x9edb4197
+	0x08eb539c	0xc13c7254	0x7fcd3f75	0xb3ac16f7
+	0x1b15d8cd	0x0505c2f1	0x076a2636	0x1d3bdeeb
+	0x798f8347	0x70e1fe1f	0xfa8c3373	0x1d26dda4
+	0x8911d6eb	0xc7278a2b	0x7208b02b	0x028e3adc
+	0x18f8ab78	0x68377e63	0xd61901af	0x2c2e46b8
+	0x32b7e434	0x63cdafd4	0x78e918d1	0x0b674143
+	0x8293d0c5	0x0ea5da68	0x4984eefe	0x9b67e25c
+	0xf4aa5f43	0x877688e8	0x2d1c032a	0x55548305
+	0x64ef45d5	0xf73d1301	0x2418537b	0x60c08c65
+	0x24329668	0xc4ef5f1d	0xdfa2aafa	0x8958d85c
+	0x9d5924c6	0xfc1c041c	0xf507ea2c	0xf922715d
+	0x3e895a74	0x1689f90d	0x59da19ec	0xff295078
+	0x423557cd	0x5902762b	0x7e11ad6e	0x52b10c3b
+	0xb5d68631	0xe0278437	0xf9b57e12	0xaf124829
+	0x7e9a1960	0x5f3585f9	0x54dc91e9	0x6d421667
+	0xbecf1cd8	0x00077b85	0x56c0b10f	0xefe280bc
+	0xaf20574c	0xfdee86e1	0xf6404d91	0x90bf47af
+	0xd916e601	0xfb81954f	0xc095cb29	0xf5bec4a5
+	0xfcef97bf	0xb07e37ee	0x82b6b56d	0x04ea42db
+	0x60abe29d	0x8222eab3	0xfbbb230b	0x73d93c02
+	0x40da8a92	0x524ff943	0x78bf83d4	0xe1c37afd
+	0xa35155c2	0x48329b3e	0xc762a668	0x68b6aa7d
+	0x41b5876c	0xbf8a8e45	0x3e1a53b1	0x76e546ab
+	0x79abb608	0x4c0501a0	0x18206179	0x61ef55f3
+	0x8fa514c8	0xbee9cc2c	0xde6def99	0xdd666c88
+	0x0b0a5c54	0x2857ceb5	0xceed57a8	0x62d86d3a
+	0x1bea74c3	0xf35942a6	0x684295f2	0x561a041e
+	0xf305e199	0xcf0c0f81	0xf9ea7e7a	0x3484577b
+	0xb3ee4a37	0x02b7863d	0x9cea59bb	0x847f5fcb
+	0x3903c152	0x05482a5b	0x9ad5099f	0x28dea11b
+	0x47e3968a	0xf6080cea	0x1a63a706	0x8100411c
+	0x0227c6f2	0x52e5a652	0x91e7ac8b	0x989b3811
+	0xe10a5c8c	0x65eac802	0xbebb07db	0x823f8119
+	0x1f25f0ef	0x47e69451	0x9a6794f5	0x9b9fab61
+	0x4244a127	0x556c18e5	0xa94651d0	0xbe8a0554
+	0xedbc5f9c	0x6e8fa53d	0xebe3d4d2	0x91d3194a
+	0x1ab227de	0xcce6da7c	0x300e6080	0x9c8fee09
+	0x21baa932	0x2c807700	0x422d0f10	0x2b318ab9
+	0x45f759c5	0x5f7a961b	0x7e3e7554	0x52651209
+	0x1e3e9181	0x7c583d7b	0x74bc7215	0x397bbca3
+	0xc969c761	0x89692bbb	0xffe3e02c	0xb3cbaf98
+	0xeb9f4218	0x97269337	0x201b4633	0x47bbf0ab
+	0x954f00f0	0xe50597d8	0xfa30bd0e	0x34f97b08
+	0xe70230b8	0x5175d237	0xf6f05156	0xc6ef5b9a
+	0x5d34628f	0x96ae0d57	0xc4a1c34e	0x2883f6b3
+	0x813ae49e	0xb7afbea1	0xb369902c	0x236fcaab
+	0x9bd3e129	0x1167510b	0x935bde08	0x74782cce
+	0x76c4d54c	0x67324fe8	0x20fdf163	0x30edb4ec
+	0x3baf38e0	0x3338e653	0x632f3e83	0x53754073
+	0x87587c1e	0x505229c8	0xd84db10d	0xa011f5de
+	0x89a24ace	0x0ede0052	0x24cb60ce	0xed01cd5f
+	0x1a5dc2a4	0x40a1c78f	0x08c394c9	0x94e53eb7
+	0xc36d5906	0x9c0411c6	0xa47e0212	0xb8a09053
+	0x789bbd30	0x185e99df	0x4e7f5e66	0xea395698
+	0x5b9185a3	0xb12ef72a	0x3bf786da	0xfcfc87e1
+	0x706f7e71	0x1defdb8f	0x6209ff4f	0x0fcf979c
+	0x368d78c3	0x7325607c	0x09cd4106	0xb2b5eacd
+	0xd91e2de6	0x3b208bcd	0x763aaea6	0xd2e67e50
+	0xb42c3b86	0x68442e72	0x607c9e3d	0xe50c8c69
+	0x9b04293b	0xd06db29e	0xd709d11e	0x4d87a088
+	0xf9d5a59c	0x90e387b6	0x1d6d00af	0x959e019a
+	0x3fbab7c2	0xbc2d59a3	0x22b7b925	0x5cc6bf71
+	0x7f4e1225	0x65f80dc5	0x92d6299c	0x464ece21
+	0xf107bdf3	0x93e265bd	0x596b14bb	0xc3ceeef7
+	0x4a821410	0x712ab8b3	0x976e8cd6	0x4ea91f29
+	0x72ce3351	0x4d18420c	0x186fe8f8	0xe1729dd8
+	0xe5ba8e5c	0x565b6c62	0x38727f8a	0x5eb3ca68
+	0x82238397	0x6addab1f	0x10ab1bd9	0x55847072
+	0x2fdf1819	0x48452cc0	0xf52b3405	0x430d0d3c
+	0xde25205c	0xc928a846	0x8a49a600	0x2e0f347d
+	0x68dd5eeb	0xb668738c	0x921c4293	0x28d3220c
+	0xea3a76e8	0x8e56a305	0x6232fe74	0x4002c4b4
+	0x9452e5a7	0x4a7d0781	0x6208ec18	0x1f223625
+	0xe16ed578	0x14d4fdf8	0x04d47966	0xe96a08fd
+	0xd95cb585	0x576321a1	0x00a8c07a	0xf0626b43
+	0x68e468db	0xe7e333b7	0x5145a525	0xb4a393ac
+	0xa7d58ab1	0x57d8ab46	0xd3803314	0xd8fa8397
+	0x73f0b404	0x07af9046	0xd7adc0bd	0x3fa6678c
+	0xebb05a2b	0x577b2e2c	0x52792d07	0x24abf050
+	0xe1046a1a	0xda2cadbd	0x9493d8c2	0x4fb41ba7
+	0x26f3f8b3	0xbfd58a43	0x15f53d77	0x3957de3a
+	0xf055d7dd	0x1056a0c1	0xcac3f7a0	0xd2433645
+	0x518c6d33	0x49b3af19	0x5ec8f961	0xfcca0f3b
+	0x91f9ab7a	0xac41e597	0x8eb537e0	0xc8642907
+	0xe293232d	0x8853aa59	0x8ac14c3a	0xfd6d1609
+	0x7989ba9f	0xecec948a	0x89b9adfa	0x2c1a155f
+	0x717d44ca	0x3b0b4808	0x679e6079	0x7f509dff
+	0xf46b7089	0xb9b93a45	0x973cda23	0xcb5aeecc
+	0x8bfcfcce	0xb3a0326f	0xd72feb16	0x1aa69d84
+	0xd63a720c	0x17917f37	0x6ce5305e	0x1d4be016
+	0xcd461cb6	0xdeb337c2	0x93f3aad9	0xb4392d5f
+	0x3794070d	0xf66b315f	0x773ebbe7	0xb49bca0e
+	0x6399ff52	0x666923d2	0x7da14294	0x62735522
+	0x607a3e72	0x74cfdf97	0x5120de20	0x87efd2a5
+	0x42ace644	0xe6bbe848	0x3c913024	0xcbe9c195
+	0x4cbfab2f	0x283d55c9	0x4124679e	0x9104dd52
+	0x402353b2	0x1d2934c2	0xd078f360	0x1e612c3d
+	0x55d7560b	0xc6fa6c69	0x8f3d701a	0xfe8d0621
+	0xf728b0ad	0x621bc481	0x767c00b2	0x20bd9a33
+	0x43153fb8	0x1dbaf9e9	0x9aacfe31	0x0c13b370
+	0x5207070f	0xcbe94b63	0x16107ec2	0x5948fc06
+	0xac484ba9	0x005295c4	0xdbc6c45d	0x0d0b938d
+	0x2ca516ed	0x0b0affd1	0x100d782d	0x6b13fe4b
+	0xdcf4adf6	0xed2d24f7	0x2528f40a	0xae52c51e
+	0xb4548c92	0x048c762f	0xf4be834d	0x36453c04
+	0x9d2ea546	0x13b9ee9c	0x018a9896	0x0fa6031e
+	0xbef7a3b3	0x4abc8aa5	0x78244a79	0xf77d7b9d
+	0x5ab92df7	0x653ab84b	0xd40e8ad7	0xbfe0f037
+	0xb08c3f61	0x3511b9df	0x71f4ac45	0x18f8feba
+	0x14b6bcb6	0x9f7f0ff2	0x0fbd67d4	0x08662b13
+	0x663606a5	0xcc43f0bc	0x119aba1a	0x6f078180
+	0x2ee00979	0xf9dc663d	0xcfb6e229	0x59e6535a
+	0xb9041219	0x5096ef84	0x5a7058c1	0x80841a9d
+	0x923c2063	0xdce14c17	0x540f2785	0x5789b67b
+	0x370c8d98	0xd1e83ce8	0x936e3988	0xbce0476b
+	0x80d96d9c	0xb40fb347	0x7276d0ef	0x34e41df1
+	0x4dbefc05	0xc0a109ad	0xa8a76647	0x0b324453
+	0x82a88349	0xaa8619a0	0xc90adf91	0x6db31b49
+	0x20b8ea53	0x6971e930	0x5ab45e41	0xac318e8f
+	0xf8440d27	0x6e7b4f5f	0xd641f8cb	0xee4b486f
+	0x376e4d85	0x40f86be5	0xbcf3fd65	0x711296a5
+	0x171dc6de	0xd76bb94b	0x486488ee	0x29869fb1
+	0x0eedf832	0x088222c7	0x79db06c6	0x08093c31
+	0x78e6af7c	0x7e92a84c	0x5b7af1e8	0x9ed1082a
+	0xb2cf6495	0xfe566712	0x810f6623	0x06f5b7f0
+	0x57ef86a2	0xd3d0543e	0x7b272150	0xd4eb6f7f
+	0x802d6331	0x8566d10e	0x07e3e6fe	0x1447cf0e
+	0x60b3e885	0xf89a005b	0x37110b56	0x68ae7dbf
+	0x72f27442	0x3df57b64	0x2fbf6e25	0x7ee42060
+	0x1415c9a2	0xbdcc37ac	0xf31ae0c0	0x172e8e14
+	0x8b5d2cef	0x27fe63eb	0xa9219d96	0x429a6e0a
+	0xdc3f1f05	0xe19d1296	0x36da614d	0x0e9ec19d
+	0xc66d4ce1	0x291d49ca	0x83a3d92f	0x1d9b06bf
+	0x733aaab2	0xacf961e8	0x63e9a69f	0xa7a075e1
+	0x4e23b6f0	0x81cc07f0	0xde10c07e	0xd331c8b5
+	0xfbf18a1a	0xfc755121	0x886c628b	0x79fea666
+	0x7ce1bc5f	0xec5b3ce7	0xebd177cd	0x66400f87
+	0x764b1291	0x5ea94164	0xfc0a0fb7	0x0fa43dd2
+	0x49235d17	0x37926a51	0x8526a177	0x773fc730
+	0xa0f54815	0xed6f01a4	0x5bb24014	0x8539b71c
+	0x132fd915	0x5f000b68	0xc06aff07	0xc8277dc5
+	0x2ddbbbca	0x3ba503ac	0x63b3052e	0x30b5342a
+	0x2af7a786	0x09da5bd6	0xe4bec048	0x133d461a
+	0x795f4916	0x419808e7	0x26261e73	0x56e041cf
+	0x4dabd60e	0x1831430b	0x2e98bb48	0xfd18b5b1
+	0x29b89cdd	0x5970a40d	0x6345a28c	0x12843c53
+	0x2313d471	0xbf22181a	0xeed3b409	0x2b998b70
+	0x6734d4e9	0x4a99f823	0xd29ee17c	0x2bd55ce0
+	0x815732a1	0xdebf0e7d	0xee592700	0x2b0e5cdd
+	0x6d1165f2	0xdd1cb298	0x21d59792	0x29ed1d86
+	0x838769d2	0x9e571c56	0x488df973	0xcdda2fd9
+	0xc2aa23fe	0xec54f33d	0x4071d93d	0xd436a884
+	0xfbacc598	0xec188594	0x2d58f807	0xd77c2f9f
+	0x4cc2ecdc	0x38b99efb	0x9ad5c2cd	0xcf93ac82
+	0x19fd53b4	0xc61c4afd	0x9019c128	0xe642476d
+	0x12975e1b	0x70406aed	0x0bba3c07	0x94944b64
+	0xf26214c7	0xa8504bd9	0x0e5dd9d7	0x0f0e705c
+	0xe1d40427	0xcf6ca05b	0xfad2e372	0xb635f645
+	0xf048ea3b	0x1a39e8cf	0x386a19d2	0x4b495c31
+	0x10ac1cc0	0xc3b65767	0xf36cf20e	0x5ad6c70f
+	0x83512822	0xfc78a6d6	0x63f73285	0xbbc3ebdb
+	0x9fe2c227	0x7b1bae2f	0xae794110	0xe438ab6a
+	0x368b06a3	0x5d98b357	0xaea10310	0x51de113e
+	0xa19bf885	0xa46d4603	0x16a6cd3a	0x87d0cb12
+	0x0b319013	0xed4495c9	0x8710f555	0xe051c6d1
+	0x6c0d2f47	0x1a09af9b	0xbc5da303	0xb3c33c15
+	0xb5ab2df0	0x7b1a02ef	0x0b7558f8	0x99faea0b
+	0x2694715b	0x1e418212	0x28163f30	0x9f842906
+	0x9ee82eb6	0xdf04c95a	0xf7f3e610	0x873f8210
+	0xe514e5b1	0x65426e17	0x1bb7426e	0xfbab6b85
+	0xa08ae8b3	0x854ca95a	0xd0d2d6ff	0x63225f99
+	0xb961fad2	0x2b4cfa45	0x51dda947	0x67405e3e
+	0x9617808f	0x4b49c09b	0x5ead3eb3	0x465177b4
+	0xabea9a4e	0x1e4272b6	0x8e0e4d16	0xfe2174d9
+	0xa604e462	0x02bae16c	0x214aaa79	0x55588fd7
+	0xa06c6534	0x52174dd8	0x1ffde727	0xb5cb4ff3
+	0x58e8e401	0x874ba1fc	0x09f52e68	0xe2ab8893
+	0x49943632	0xbe02e3ed	0xdade2e8b	0xa5da9671
+	0x31f393d2	0xfb4f4e01	0x10c03e2e	0x94fac702
+	0xccdd9c33	0xd51373c5	0x32f67c97	0xf75f6dc5
+	0xf7c56120	0x429a4417	0xee3533ff	0x6395711b
+	0x84c30f8a	0x87e400c9	0xdb34cbb8	0x554373dd
+	0x89c3032d	0xb54a2095	0xbf8ca76f	0x32b9528f
+	0x45a716a0	0xdabd57bc	0x0b5a9419	0x0607f8e7
+	0x97bd8515	0x34fcfa92	0x89914683	0x596ce15d
+	0xa0d16b41	0x0475dcba	0x530d9b55	0xb2f6980d
+	0xeeb49560	0x9ff9f979	0xffb3b3f2	0xf8dc90c2
+	0x7df7ec78	0x663f667a	0xda25d7f1	0x4e5e1a1f
+	0xb8017f9e	0xaaab7404	0x0fbc96a3	0x2e6883da
+	0x70b4ef71	0xe68fd886	0xbf9813e5	0xfbea41ec
+	0x0e9c7205	0x4f4324b3	0xe9f241c0	0x59848c26
+	0xa6c883b0	0x6fed019d	0x3bea1228	0xd636e300
+	0x6950359e	0xcf52052c	0x1b528057	0x06fe6742
+	0x04965c8d	0x9a7b26c5	0xc99230d8	0xb579c7aa
+	0xe24a7255	0xe814e07a	0x76f58992	0xbad495de
+	0x55700746	0xfaf4da35	0xb5536992	0x1008288a
+	0xd867fd0b	0xb1c9720c	0x047d6414	0x561bdcc4
+	0x74e334f1	0xb66a42e7	0xc08e03a2	0x859a375c
+	0x2d6c3b8b	0x0aa6b45f	0xc97b7c6b	0x5765735c
+	0x5367cf95	0xd957151b	0xb6354238	0x7c9dbd21
+	0x97fbcb95	0x110361bb	0x2394edad	0xbf8e18b3
+	0x2d4d9bd2	0x24b42b08	0xace76b11	0x2b8fb939
+	0x04105821	0x79af703d	0x434c240e	0x2a019bf0
+	0x02a38fc2	0x9c640e05	0xdde8995a	0x3b8c0b1d
+	0xb44190f0	0x3c84367d	0xdbb9bb01	0x27c42ea7
+	0x87f24ef1	0xc9abb097	0xe4df5c7b	0x45e04755
+	0xe29ab2aa	0x29be8522	0x4efa4f5f	0x2b4522d2
+	0x67f465fd	0x4171364a	0xd2bed8f0	0x477e8b5c
+	0x982c0339	0x48fcc0aa	0x06206cf1	0x4c132f24
+	0xc2a78b32	0x18a3806e	0x84551ba3	0xbc8dab25
+	0x3cea4ede	0xbe3cb62f	0x7be253ed	0x828e2dca
+	0xae76b847	0xc018fe6f	0x09e3d2ab	0xfd775e4c
+	0x80f2595b	0x1a1d440b	0xc48f9889	0x52d1cadb
+	0x99fd2c1a	0x3d700d86	0x079d1761	0x6811c4eb
+	0xcc2f677b	0xe5422423	0x11a606e9	0x3fd6ea3d
+	0xf9ae700e	0x09aca633	0xa7097790	0x5db8d41b
+	0x34941e1b	0x3fc50d4c	0x2fd2cf3d	0xa60aa40a
+	0xed6381c1	0xb192e754	0x3248af41	0xe0cc843e
+	0xef3c9504	0x3712da7c	0x9fffb613	0xdef40782
+	0x86f9bd62	0xbd8a3260	0xf6dcbb87	0xf9a264e7
+	0x3bb46aee	0x6f92d88e	0x6b0861e4	0x5ab7d4cb
+	0x2f1cf740	0x8213ac78	0xa34f0812	0x4d7db7bb
+	0x20d1abcc	0x9c519247	0xbc708c1a	0x66871981
+	0xc436271e	0x88247723	0x2996c404	0xca9c48f6
+	0xdcea7c3d	0xf6cdd451	0xbab6a23f	0xf064060b
+	0x3c0d3775	0x3a7ccc2d	0x5d056c98	0xa6521199
+	0x7f3b8753	0x3ca8407a	0x3097264f	0x60c75837
+	0x96e43535	0x5d17c5bd	0x89bb2825	0xd35fac11
+	0x1c323feb	0xe8fd05e7	0xcad8184e	0x23456746
+	0x6e4f1d7d	0xfbfada38	0x20faac8d	0xdcedab37
+	0xf094bd0c	0x7d4e750c	0xbd7ef698	0x0125c05a
+	0x17d840cc	0xf44bd1bc	0x236e7f10	0xdd53c6ac
+	0xb0bc6a1e	0x019b1a51	0xfd99d0b1	0xb723b517
+	0x728e0e9f	0x4280e2d0	0x8da35086	0x2e3cb572
+	0x2a53e018	0x6f7a3e41	0x7afe2ee6	0xe4efc53a
+	0xe2ed04c6	0x67112c67	0xe7e43b4a	0x03f680d7
+	0xe3434120	0xe2c12215	0x63ff546e	0x4d87e2b7
+	0x6f95093f	0x7c7a5e18	0xef98c38b	0x8ccf2684
+	0xf4619327	0x148676c5	0x4be2254a	0xcda85631
+	0x00ae4a2c	0x2df961dc	0x85b6fd89	0x1512b1fb
+	0xc17a7547	0xbd062ec9	0x91229a47	0xf6d4b08c
+	0xf7d3c4f1	0x4d951e94	0x62c8a9e9	0xd7df6f2a
+	0xce34f11d	0xc04b655f	0xfcf369b9	0x40eb0ec3
+	0xf7b55c23	0x8edce54f	0xba8ce0db	0x2a5e5a92
+	0x3b243dcc	0xbcc8c5d0	0x906db8bd	0x6a0aee9f
+	0x9e6c3df4	0x16f2252d	0xd389126d	0x5118a5bc
+	0xa75cc327	0x559dde05	0x5bb43b00	0x7fbe942e
+	0xa24e752a	0xabbfe05c	0x916daec7	0x8817b357
+	0x5be9fbfb	0x6e8bc90d	0xcdf7cb49	0x0b28069a
+	0x1922e927	0x24713a66	0xb9c800e5	0x63968dee
+	0x34464be9	0x712fa6d8	0x9f9c814f	0xf6121f78
+	0x12863a08	0x349158d3	0x66556d8b	0x4938c818
+	0x69374151	0x55046a98	0x94c8e4f4	0x48430cff
+	0xb885cdc4	0x762fb5b6	0xee98caee	0x8e582d5c
+	0x808ba575	0x7878cbac	0x1d257ec1	0x85bb9f16
+	0x50adfb99	0x98e3f712	0x532b6bb5	0xd3aa0b14
+	0x07369ec9	0xc6f71890	0x1bb76ff9	0x0e91023e
+	0x7d6e119a	0xe8c5f447	0x49edf0c4	0x8d380eed
+	0x99984929	0xd37dd90b	0xfffb0a41	0x69eb9ab1
+	0x67b2585d	0xe3a5a664	0x7f9d9156	0x0454b9c2
+	0x4b5d28f2	0xfa6d0a33	0x3c9206a7	0x5aa2fb75
+	0x767201c8	0x7db04d90	0xc27e89a0	0x4df1cfb8
+	0x81efb5ad	0x2eeee02b	0x42d5ef5c	0x394fdbd2
+	0x0bcc3166	0x2f43982b	0x832520df	0xdb6fb558
+	0x63fccc0d	0xc42816d3	0x5cf66464	0x2b4b89e7
+	0x2d62dcb5	0x6c4f52fb	0x6c3ac264	0xc92c6977
+	0x1f6cc458	0xd639250c	0x4044e6b0	0xc39df4c4
+	0x65595b2b	0x1c9be044	0x5242d7f4	0xec710e0e
+	0xa991869f	0xacb3cd55	0x4e82d850	0xa7ddd47c
+	0x12c0cc9d	0x8ff166b2	0x89d6bb4a	0x136ef38b
+	0x3875e7df	0x8d59d30b	0x3d22b091	0xc64b065e
+	0x73077e1e	0xcdbbe7db	0x000e842c	0xd5147941
+	0x8fbcd501	0x6d731511	0x1a45fa09	0x1579e7bb
+	0x4dfa5ed6	0x192d360a	0xc36e445d	0x6df0bb79
+	0x9c60d757	0x99067a40	0x286e1450	0x21d95d9d
+	0xbffde5f4	0x5b6e43a1	0x61b62406	0x87e27b1d
+	0x12fbc7cb	0x52332046	0xe2ac85fa	0xe6dc1b49
+	0xb04e0d61	0xf9cd9aa9	0xe56424ff	0xc5b0b353
+	0x7b99dc04	0xf8bf97d2	0x3fc86848	0x396441ff
+	0x92c981c7	0x97a58a03	0x18862056	0xc9849658
+	0x683cec3b	0x3298b913	0x1d381d39	0xbe687457
+	0x1598e8c8	0xb4944287	0x59e42ebd	0xaf631121
+	0x81c6ed2b	0x811cd718	0x9d9ece91	0x6d26ed1c
+	0xca577a45	0xe87b71a4	0xf9d884ed	0x8c88c874
+	0x452020b4	0x9e6ac4b8	0xa99fb35c	0x3d0acc96
+	0x6d0220f5	0xcd4a9041	0x0f7b3489	0x4de2fca5
+	0xd91865bf	0x7ae85bea	0xd0ac675f	0x3643cfd2
+	0x9c9e938a	0xcc24771c	0x04a8d771	0x69ea870c
+	0x536c78b1	0x9c986d53	0x188133ed	0xc2449d1a
+	0x949dcfee	0x657b7cbb	0xbac748a6	0x5469c94f
+	0x58b00d1b	0x4a95f324	0x9e3d996a	0x7d61363b
+	0x95c3b5e5	0xe0c628e5	0x89ba2777	0x92530a59
+	0xa52ed8d8	0x96f64b04	0xd7a09900	0x2b7bdcec
+	0x31ddf392	0x796d19fd	0xdbaac550	0xc1b483dc
+	0x7003a526	0x260f55db	0x2065f6ad	0x97c38ccc
+	0x2a6b7ce5	0xec4e0018	0x990007bd	0x93e4d47f
+	0x04d2536e	0x4bfd17fd	0x173af016	0x26515f4e
+	0x9051893d	0x63333e26	0xe47971be	0xd909f5f9
+	0x2f5be247	0xfade7a04	0x121542b3	0xcd5f8f3b
+	0x416d8352	0xa66d58b6	0x5656d408	0x10ee1bf2
+	0x3c65b26a	0x31dbef80	0xb3badd4d	0x388342da
+	0xc430266f	0x53fa9fe3	0xfecd7bd3	0xac043f73
+	0xc94b4ee6	0x1dd26332	0x993b8b27	0x1d78261e
+	0xbd4a0564	0x170a57fb	0xaaa7be6c	0x9bbde43e
+	0x70d16f35	0x11525ae1	0x00b8c636	0x7088bf37
+	0xed6ea850	0xaa37bc1f	0xe08e79ea	0x7d4ed426
+	0x95f8916a	0xc2fdd49f	0x1fa1bc9a	0xb759624c
+	0xd7159d5d	0x65762aba	0x50c99a62	0x8879a995
+	0x496ad905	0xcf5447b3	0x230a9e21	0xb6d586ac
+	0xccfd911b	0xa4a58d33	0xbef8ff75	0x6381b0c3
+	0x62d0e4ad	0x2f0992a0	0x27d2e923	0xc9d67860
+	0x46f394b2	0x877ea324	0x6ed5c693	0x386dbfd3
+	0x5f5c1f7b	0x1a339481	0x1cd12853	0x4da6425d
+	0xe50aa540	0x2dd400e8	0xd7b37c5f	0x52046ed3
+	0xdb24073b	0xb28cbf56	0x67e62bdb	0x32f6e9bc
+	0x8f2f443b	0xacedd944	0xfa99423f	0x3ae8d636
+	0x613a42fb	0x1a410513	0x4469e127	0x2fdb4b5e
+	0xf86ed877	0x07637d77	0xbb197929	0xa8fa021b
+	0x9a9f4341	0x35e36444	0xc6728094	0x54c438fb
+	0x17b46ef7	0x152d988b	0x42c512fd	0xcc4f36dc
+	0x1ab4ed10	0xd367833b	0x1c08b3d9	0xb5d182e1
+	0x198f9d7a	0xd68ac623	0x964db9a6	0xd6c121f9
+	0xdb56e5d9	0x69e61f26	0x6b9fe5f6	0xc414f7ed
+	0x812a505a	0x7b73b945	0x08000c8a	0x8ed6ff2e
+	0x19b9394d	0xcce2bc3a	0x46d66935	0xf3e5468b
+	0xf345f275	0x5f9bf5c1	0x46ceb342	0x45149107
+	0xc02af675	0xbf3ca371	0x55237036	0x8ae2d3bd
+	0x19b01471	0xa77a83f0	0x6b003b46	0x29a22e11
+	0x89a94839	0xd0c249a3	0xdb36a03a	0xe38f4040
+	0x88f9c8b9	0xef50fad5	0xd69b106c	0x5f314dd3
+	0xde5e9f87	0x91c24944	0x49eee859	0x2aaeaa65
+	0xab45e53c	0xf3a0e4c0	0x200a36e5	0x77e484f5
+	0xcbf8952d	0x64d6ebfc	0x1f832895	0xd835590f
+	0x13f5a770	0x190849af	0x3068c161	0x61a78e84
+	0xd7567c5c	0x4a1ab2db	0x524ae318	0xd488b5be
+	0x1703785a	0x0a1889eb	0xd39c572a	0x4f99ba34
+	0x3015e101	0x99e6ff5d	0x13cee969	0x0d66997b
+	0x8e3dafe4	0x9c0507b7	0x28cebbab	0x2e6cf3d1
+	0xb24b11bc	0xe411de4c	0x64d5f845	0xb0b20f46
+	0xa49b7b52	0x9b65793d	0x8756f69d	0x0e0bfcd9
+	0x6631f0ee	0xfea0c152	0xc54d903a	0xe05159f1
+	0xb2cd54ac	0x039a6d29	0x81cd7e6b	0x58cd335c
+	0xf6e95cc4	0xa6a02bf1	0x62e10eb8	0x0b11d249
+	0x5b52a70a	0xff2eb36e	0x9ce7f597	0xfc4421c4
+	0xba74bbfa	0x4ba989b4	0xce7c369a	0x8c149a5f
+	0x063745c9	0x4a1dc1ba	0x3c798afe	0xa47ef113
+	0x54c6c987	0xa6623430	0xed26b37f	0x0ebac834
+	0x54cb0233	0x92995cf3	0x5412dbfb	0xaf94b295
+	0x80ea9fea	0x6c776fea	0xc638768e	0x3e2cd596
+	0x8c6f6218	0xe5b70298	0xad6cb433	0x0271dd2a
+	0x25c9a276	0x24ee6a85	0xe72e9d3f	0x3bdf3f97
+	0xabf11c1e	0x99937754	0x2bb62c14	0xf3da4c81
+	0xc962c562	0x727c4e26	0x97b1c000	0x0de49161
+	0xdb8d6318	0xc9b83dd7	0x40901e67	0x68ac3dd3
+	0x217fecae	0xfa36644a	0xb9399c9f	0x620ccdbf
+	0x81fa634f	0xdb38edb1	0xf7e11418	0x1f580868
+	0x48b35cae	0x7230c6e3	0xf7cc6a25	0x440c45d7
+	0xb390e675	0x9b78318a	0x0d359239	0x97e078cc
+	0x80e65a34	0xd71dbf0b	0xd112cd54	0x53a3f81e
+	0x098f7be4	0xa11d522e	0xebbb20dd	0x2c4a78c0
+	0xd4e79e2e	0x01c919dd	0x2fa34e3f	0x6a16a7df
+	0xb81c9cf9	0x472fd48e	0xd197dae0	0x94cc62c4
+	0xe052d018	0x1ca9bf15	0xb44ddb70	0x814d856c
+	0x68927beb	0x5622d712	0xfb289586	0xd40ab10c
+	0x4c7f3469	0x357a822a	0x717a3720	0x3f3a99ed
+	0xf13943e4	0x043dbfae	0x6fb72671	0x06bcaf58
+	0x790c1e70	0x3e8e537f	0x5a4fb50e	0xa2fe476d
+	0x9db652cf	0xace6b43f	0xd1273d75	0x88727f3f
+	0xe66f9c36	0x24339816	0x28f8dd6c	0x5a4f8879
+	0x51ebf963	0xd64769b3	0xd9006ec3	0x20bd215b
+	0xce24e7cc	0x61c00c46	0xf9b16868	0x429a54f8
+	0x328834df	0xfcdbb181	0xd782c3e9	0x6b71dbe0
+	0x70dcfe9d	0x95c1a80b	0x5ae919c7	0x7e71afab
+	0x4103d80a	0x955c62d8	0xca197e33	0x4b579a1e
+	0x94521734	0xa9bd1f4d	0x112ef524	0xbfafeec9
+	0x6358d4de	0xe68efe2d	0x93c564db	0xa3e4ac68
+	0xc61833f9	0xef2e5dbb	0x4d3a5a3d	0x30e7a355
+	0x6b1ed181	0x1e6cbb81	0xb6fa389c	0x0c7e7ee9
+	0xc20c8770	0xcb04a3ac	0xa4ba69e0	0x7e87b290
+	0x8c67e8db	0x2c3a40f7	0x366bc618	0xdeaab8e0
+	0x95d11262	0x665c9d87	0x68435cf0	0x924c1e1b
+	0xc8f8c882	0xdff0c036	0xfe411797	0x2bd049c1
+	0xf4def28d	0xd8d01637	0xc7ef2c00	0x6367f83f
+	0xd34fdf44	0xd392e10a	0x6d522ea0	0x16f8e3c6
+	0x4d9b0149	0x6ce5ac26	0x57431d08	0x77f105e2
+	0xe9f6f804	0x92dae4d9	0x63baf9f0	0x17056564
+	0x010e1d9f	0x50231c43	0x5ba79db6	0x8517839f
+	0x18afe138	0x88d3a85e	0x786ed442	0x9cf4a72b
+	0x629ebf65	0x613d8e8e	0x712a0fd8	0xbc88b08b
+	0x81ea88b3	0x3ac5f023	0xb93c236e	0x93a3468c
+	0xd86745c6	0x6df47eb2	0x10e2e256	0x2da86820
+	0x1513101f	0x38128155	0x7fbc9673	0x5e8aca10
+	0xc79677d1	0x8006a420	0x56909452	0xde047cd6
+	0x33256da8	0x63637d54	0xdbb682c2	0x9b00c56d
+	0x9f62d072	0xb7be713a	0xb0e603d8	0x047e37e3
+	0xd51ffb7a	0xeec69890	0x1e72d673	0x6d7f5c0d
+	0xa80c0473	0x12b89507	0xd605abac	0xd4c6899d
+	0x9bb98856	0xa6269a33	0xe08135cc	0x8a69b777
+	0x077837e8	0xd13014ea	0x9ca638ad	0x908e6612
+	0x5bf969fd	0xfd9da209	0x3e72a1a3	0xc7cbec2b
+	0x66cf84a1	0xd67e67eb	0x1684ed54	0x22feca3c
+	0x9c0d00c2	0x6337c641	0x89f65117	0x7fa4c657
+	0xebbd3208	0x89322dfb	0x925f82c7	0xebeef669
+	0x8cf74ade	0x55847368	0x28fd1623	0x5c2e0709
+	0xceb12802	0xbc4de4d3	0xec44bd13	0x33574d46
+	0xe89ce0f8	0xc09d2036	0xf83ce68e	0x0da18b34
+	0x30bd2849	0x252235cd	0xae7b84e6	0xb894640f
+	0x5b84fc6c	0x23f8cca0	0xd5a506ad	0x5605e837
+	>;
diff --git a/arch/x86/dts/microcode/m0130679901.dtsi b/arch/x86/dts/microcode/m0130679901.dtsi
deleted file mode 100644
index 11aaaa025a..0000000000
--- a/arch/x86/dts/microcode/m0130679901.dtsi
+++ /dev/null
@@ -1,3284 +0,0 @@
-/*
- * ---
- * This is a device tree fragment. Use #include to add these properties to a
- * node.
- *
- * Date:
- */
-
-compatible = "intel,microcode";
-intel,header-version = <1>;
-intel,update-revision = <0x901>;
-intel,date-code = <0x4212014>;
-intel,processor-signature = <0x30679>;
-intel,checksum = <0x69c4e6f1>;
-intel,loader-revision = <1>;
-intel,processor-flags = <0x1>;
-
-/* The first 48-bytes are the public header which repeats the above data */
-data = <
-	0x01000000	0x01090000	0x14202104	0x79060300
-	0xf1e6c469	0x01000000	0x01000000	0xd0cb0000
-	0x00cc0000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xa1000000	0x01000200	0x01090000
-	0x00000000	0x00000000	0x18041420	0x01320000
-	0x01000000	0x79060300	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x00000000	0xf4320000	0x00000000	0x00000000
-	0x00000000	0x00000000	0x00000000	0x00000000
-	0x3b6ec6fe	0xc0fda75e	0xb4ea6a9f	0x8fd6ed15
-	0xd537f374	0x669bf3bb	0xebedec72	0xb4cbc889
-	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
-	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
-	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
-	0xc928c400	0x3add156d	0x531946f9	0x92a03216
-	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
-	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
-	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
-	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
-	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
-	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
-	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
-	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
-	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
-	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
-	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
-	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
-	0x11000000	0xf03f27bc	0x3ed2262b	0xe1f8f63d
-	0xc164c68f	0x92e5df39	0x46108645	0x99a9968f
-	0x1dfa58a4	0xd1ebfd99	0xca4dae70	0xe466a06a
-	0x49575333	0xe30f49f0	0x814e5961	0xfa4bb7bd
-	0x2e212282	0x31912456	0x7d722c47	0x9cda0657
-	0x111985e9	0xd28d3b0b	0xec52f0c2	0x956b5b95
-	0x0806f491	0xa8096786	0x1e4c1248	0x42ea1ecf
-	0xea09d662	0xa821f68e	0x4b84d60a	0xa6f61348
-	0xfc95c139	0xebcebc32	0xd68ffe3e	0xa9aefabe
-	0xf653aafc	0x2a9f10e4	0xdaf3d51d	0x5f25aaa5
-	0xdedacabe	0xf2e08b12	0x6fb9f444	0x31b13d4e
-	0x13074cd3	0x68905491	0x08ce3a00	0xb3e5a3dc
-	0x9554ca97	0x5955c3a4	0x2e9951fd	0x5d708c9f
-	0xf3abe824	0xcb9105a1	0x3f51122e	0xd2152f23
-	0x2873cd28	0x463c0ff3	0x7bb81500	0xaa360665
-	0xbe69bdf9	0xa32415d6	0x111af68c	0xd129eaf6
-	0xdd102779	0x098a2b08	0x90363b85	0xdb5d3420
-	0xd1d116e3	0x9e5dd54e	0xb4a93d32	0xb5ee99fe
-	0x409f0bca	0x40302319	0xe175ddaa	0xfd7c8d00
-	0x2c28edb9	0x698d27f4	0x2e7945f1	0xc0150485
-	0xf9c599fc	0x139824cb	0x1571f70e	0x222565e8
-	0x3377eb7a	0x70fdee6f	0xd409f0a6	0xc875d05f
-	0x70d6a86b	0x66201d61	0xf8fcb733	0x14279707
-	0xc204e0e4	0x124c89be	0x8b298d1d	0x79bfe168
-	0xdbf7fe94	0x0358af09	0x8291ef8a	0x3e74a2ea
-	0xb7780782	0x0194d445	0x0bab231d	0xd76f85b2
-	0xc7510861	0x4b9a5c80	0x6c9c8583	0x4e18d7db
-	0x7dfeaea8	0x59be4d17	0x8e96f5b7	0x51bcb2da
-	0x5f3afeed	0xd3f46ecd	0x10da04eb	0x29dd87db
-	0xb7df24c5	0xd58dc2dc	0xede0603f	0xadf00cf7
-	0x50090b9f	0xc9130c82	0x854fc603	0x13b8b4be
-	0x10e2e41f	0x5c1d2246	0x0ee11843	0x6d38356d
-	0xd3bd47ae	0xb419f115	0xb118cac7	0x9c61aa7d
-	0xca22cf8a	0xd41af2f1	0x0b5ebfab	0xc0889746
-	0x078c705f	0x9e5b2b7a	0xb886ff49	0x1ab413e4
-	0x085cebc5	0xe3a44ab5	0x8844df92	0x075a79cf
-	0xb8fdc33b	0x1766265c	0x9340a734	0x4af860c9
-	0xa933586e	0x3e8a9a5c	0xf6419a1b	0xa70a1556
-	0xf930240e	0xe294fb1f	0x9bba35c5	0x4051819b
-	0x6799015f	0x7eb725ad	0x3953fe03	0xb8760679
-	0x54c7978c	0x3dfd36c2	0x631212bb	0xdeaca312
-	0x56d994dc	0x3a1696d1	0x214451fd	0x6dc505f7
-	0x7bbf210f	0xa266b569	0x8fb5eb6f	0xa6b76bf8
-	0xc9e782a1	0x8456765d	0x0a9eb223	0xa67e533f
-	0x211016f4	0xd8783c3e	0xc35574b8	0xd97e9b52
-	0x28ad2911	0xbffc5dad	0xd807d783	0x3050f3d1
-	0xcc33efa8	0xb9cf97c2	0xee5dfc8c	0x2adad5bb
-	0x4011c50b	0xa16f5d93	0x5e2ac188	0x521c977f
-	0x6af1b858	0xcd7e4b4c	0xfc988f66	0xc0e4cee9
-	0x82ac99ea	0x54353832	0x2308e02f	0xd084d198
-	0x03574ad5	0xbe4b698f	0xe1d7d294	0xd772d08d
-	0xb7a4fb2a	0xf7c93bb8	0x42fb2f4b	0x98cb1a11
-	0xf564f28e	0xd6ace35f	0xc43f6639	0x85be741d
-	0x079b8c1f	0xb5b45522	0xfedab918	0xf7fa7494
-	0x32204c16	0x1c8d5434	0xc39e58e4	0x99c7a2c4
-	0x3ccfbc3a	0x3f5ba9ef	0xf919921b	0xcffbeb79
-	0xd2927d86	0x5a50486d	0x62bdb218	0x22731dcd
-	0xbad1db2c	0x2f4af4a5	0x8f7eded6	0xeca3dcca
-	0x0bb5ecf7	0x05e6f3c6	0xa38cddff	0xc7cae177
-	0x1d115485	0x711ea542	0x33729cf9	0x59000680
-	0xcaf26070	0xd2647235	0x4ce354fc	0x76d9bdbe
-	0x53e39ec2	0x2d8acfb3	0x193c03b9	0xb3cef3ba
-	0x1da26bd5	0x8dfeeaa5	0xc199d90d	0xcfc8ee2d
-	0x4cb1bd52	0x521d197c	0x008bf34b	0xb6ff25ca
-	0xf4922b7c	0xa91893a8	0xbd3d7874	0x32865e72
-	0xca72c49d	0x02733201	0x6156051d	0x47464b81
-	0x353a3c14	0xa87475c8	0x9681a015	0x4b58832d
-	0xea65c6a2	0xfefef1fb	0xd5fa7dbf	0x13aeee80
-	0x2915b47b	0xe4a54fca	0x31615326	0xbad80f83
-	0x21eedfcc	0x2a2787da	0x6eaa2c9c	0x9de76356
-	0x8a34d823	0x2e7641b8	0xef16714d	0x8267bad4
-	0xacdfff45	0x09a93862	0xf63863de	0x7eec7d8b
-	0x70b4cf72	0xc7a8118c	0x4ed89774	0xc12a5e0d
-	0xe77cc023	0xcdee8fd8	0x20ffe6d9	0x88bcfaa0
-	0xd945e4fb	0xf496fccc	0xe7587e99	0x42252ec4
-	0xcc47d738	0xcc549ca3	0xd5059657	0xfbf502a5
-	0x2788945d	0x4f8ca4d6	0x41b7c069	0x618ebdf6
-	0x0354452c	0xf7249d75	0xe048dd38	0x4ca484b3
-	0x0347342c	0x23608b20	0x8a76cb28	0xd445886d
-	0xfe0e1e6a	0x46678478	0x230c0ef0	0x3add3053
-	0xa6a158c1	0x22c589d3	0x3b728538	0x5f78bfe8
-	0xab0bb3ab	0xb39e20b7	0xbb913a69	0xdf8bb73c
-	0xc2d5bb32	0xbd3e928c	0x30374965	0x9accaf18
-	0x60bb410e	0xa7786a6d	0xd368444d	0xc5eda57d
-	0x7a835abd	0x9f5f74e9	0x33b14a30	0xc0129833
-	0xc5d2e117	0x5f884f0f	0xae6fd2f7	0x3ef71ba2
-	0x0f0b944c	0x1a8dd932	0x2448f0ed	0xfb8ca949
-	0x9d08756f	0x7914384d	0xdd70f795	0x8cf8daff
-	0x6755785b	0xf4e6a191	0x8c5a9a2e	0xfdc19939
-	0x66f39dc0	0x3da9fcc2	0x2c22797b	0x63f892d3
-	0xdcb75a66	0xa043c021	0xcb0f9292	0x887eb1a2
-	0x9d588452	0x9fdc185f	0xf481d465	0xbfef53b9
-	0x38da9baa	0x9d35c4f4	0xa652c843	0xf80f0007
-	0xb482a32c	0x7ae4df5b	0x74ad41c2	0x15d849b3
-	0xc4235054	0x36d44d98	0xc06ad604	0xdc83d81f
-	0xd4b87511	0xab79b430	0x832a7ce1	0xafe26f16
-	0x9f7d26db	0xd00816cd	0xec6e7b8b	0x0392bd20
-	0xfe4b6e2f	0x87795026	0xf9e4eef8	0x06cd2ec8
-	0x91670e6a	0x17aad6af	0x399050d1	0x043d05f8
-	0x5dd8e105	0xa2938113	0x2c47ea5e	0x64a062f8
-	0x14dd01cf	0x6773f479	0xf2b4a773	0xeefe3b89
-	0x8cf35404	0x0f02b236	0x430023ff	0x04ecae31
-	0x6949cdfb	0x65b63ba6	0x86c5a7c6	0xd53cc1b5
-	0xdc1ee770	0x30ebc654	0x67a95215	0x2e4508a9
-	0x9df37690	0x33baf9e5	0x9a58d5c0	0xe99baa0c
-	0x4b7446eb	0xfc7c8340	0xfa5ee60a	0xd1d873b4
-	0x302f882f	0xcff8ac83	0x56d809d2	0xcab281e6
-	0xadca5551	0x50691975	0x7766b753	0xdb7adecd
-	0x131c83af	0x1b09ee46	0x87fdd3ef	0xfe3037c2
-	0xcd2b5362	0x5f21384b	0xacd78f4e	0x145a4793
-	0x131a6a20	0x0fc1adf5	0x3707f20b	0x5d37ba20
-	0x6c8448e6	0x76f721a4	0x348b0456	0x608453ed
-	0xb1185c8a	0x18bbdaa1	0x7c1c6e05	0x46fa7cdf
-	0x390cf9b7	0xe9c825bf	0xf77554c5	0x7dd5a47c
-	0x49cfca16	0x5fd7e6dd	0xf707ac36	0xdb6f0142
-	0xaabda9b0	0xe7ac02e7	0x0a1eb844	0x225686b2
-	0x7852c1cf	0x3912115d	0x89d65081	0xc3f4faee
-	0xfedeba97	0x073395d9	0x33d20ce3	0x56c6c126
-	0x378f822e	0xf575b487	0x043da151	0x1ccae8c2
-	0x5fa2279b	0x0608f618	0x4c90662b	0x30591d0c
-	0xcf217166	0xacdbf6fe	0x1a653b17	0x6fa76090
-	0xc804480e	0x44c5b06b	0x1ebb8a6d	0x2f6f6f08
-	0x6bbeb75c	0x21c5c48d	0xd4c4cc2d	0xfdeab68f
-	0x25cd39e3	0x62970aa2	0x48aa915f	0xca38c833
-	0x9cfd1d10	0x81dbc61d	0x51702e45	0x8f80e492
-	0x07e89651	0x920e9f7d	0xdfa9f973	0x8cbfa187
-	0xbd3e7a14	0xee191486	0xb0077d2e	0x7345adcf
-	0xce36b2ea	0xc73aec7d	0x9278ac37	0xe07c6d96
-	0xf90f78a5	0x38f5584c	0x4941da80	0x67ff3048
-	0x3c263914	0x49656179	0x22f066a5	0x1f5a5e3e
-	0xce9ce83f	0x8e7446a2	0x85473d62	0xd7622673
-	0x3941bc22	0xf879d494	0x0936a517	0x2bba925e
-	0x516761b3	0xe238a8e3	0x11a0c8bf	0xd53cb861
-	0x60c0f0d5	0x63f7f157	0xb23dd4f9	0x5a4fd86c
-	0x3851d435	0x483b98c7	0x71c55b1d	0x1931d219
-	0x7bd54621	0x108bb4af	0xa72c8b97	0x51d985e2
-	0x598a521e	0x7efcf984	0x69b02671	0x5746157d
-	0x60cfc339	0x629567fe	0x2236a93a	0x520d0094
-	0x61811f40	0x856aeba6	0x4fc0a2b3	0xedcc9fb2
-	0x8fce6123	0x2ba53b1b	0x6fc610d4	0xabb564f4
-	0x957158aa	0x1d2b7989	0xaca5dedc	0x684a7086
-	0x1610e1ef	0x2abdf9b0	0xd9e9d205	0x0119ab86
-	0x6da64982	0x71f274b0	0xf425e61b	0x029dc92f
-	0xb13ff88f	0x064ecf92	0x4070c36d	0x58bd6ebd
-	0x629bcf8a	0x9091566a	0xc947a42e	0xd0475c87
-	0xe7773220	0x7b61f2fc	0xae0c08e3	0x44582521
-	0x557dfbaa	0x92fba0ef	0x529900aa	0x90fef908
-	0x570b0495	0x704125df	0xd8f9448e	0x9a7cf1f3
-	0xd83a747b	0xe27e3d56	0x4da6aaa3	0x55439398
-	0xce0d1c02	0xdebd6473	0x580f141b	0xcd5a5e57
-	0x1c64cc23	0x53f8f9c7	0xcfb5b464	0xa4939b05
-	0xc0bb3066	0x37923d76	0xe5e9b428	0x6f4f2894
-	0xe5144757	0xa9cfdc46	0xe3448b78	0x7e0bac3a
-	0x38066245	0x0d7c86fa	0xb7fd09a6	0x075426bf
-	0x3de7c82a	0x1f8d1b36	0x34144ca2	0x6c03ad9d
-	0x34305ef0	0x0a5269ce	0x82a9eeed	0x3be63f82
-	0x2001cea7	0xbba641a8	0xa4dad9e4	0x92e0fb69
-	0xa166dfad	0xd1ae10ab	0x0372e102	0x88469aeb
-	0xaa11bae9	0xf1006dc9	0xa8648217	0xe171b6e8
-	0x590ba849	0xa593cf1f	0x4cf079d4	0xe451e193
-	0x4355a93f	0x54dfcade	0x1a918a74	0x88eff191
-	0xd5a2bf54	0xb9962550	0x58d478ab	0xc78828a9
-	0xe2cff385	0x9ff810e7	0x9643953f	0x84764dee
-	0xe4950d03	0xdf17e0e5	0x4da892d6	0x48145872
-	0xb7453254	0x41240a2a	0x7ddf94bc	0x898771f1
-	0x61a423be	0xcfb46db4	0x7db27a89	0x2feeaa82
-	0x24d86326	0x043f5b1c	0x8cc6bd73	0x934b7b3e
-	0xac4a1262	0xebc494bd	0x53921696	0x115c4d9a
-	0x1d73de18	0x6417f141	0x9fdce4cd	0x8f72ccdd
-	0x3bb26030	0xdaf43da3	0x1e26758b	0xad1234be
-	0xe5bdf477	0xd2dd9e46	0x1270838f	0x557f3bd2
-	0xaa5a28c1	0x61e0d535	0xdc5aa028	0x9af22a6d
-	0x9b669fbb	0x979b5586	0xabf8264f	0xbcf91b17
-	0xda92e3cf	0xaaa87ae0	0x52336f6d	0x5beef95f
-	0x7c310125	0x8858f708	0x3c6e6d73	0x6720d3c6
-	0xed51b365	0xa9e50de2	0x865a7fc1	0x756b5758
-	0xbe13f4ca	0xf2eb039e	0x187d1641	0xc6e37977
-	0xbc3a2d64	0x6523583c	0x70db0cf9	0xebdba06e
-	0x632e8e5a	0x7b44144b	0x338bf7e2	0xf43dd8e4
-	0x2d91d815	0x9aff02dc	0x700ebe20	0xe9b6ea5f
-	0x776cdc38	0x43324788	0x53458290	0x2e22910d
-	0xed0fdf3b	0x279fc3ca	0x5a01f65c	0xc4ad1598
-	0x7a1fa09f	0xd12f97bf	0x34d99bad	0xfcecf69c
-	0x2b5567af	0x57a93cb3	0xfcf93005	0x3a403789
-	0xecaad383	0xc63fe190	0x5b8de563	0xbd9b876d
-	0xa20b875b	0x79db86f9	0x1917cad6	0xe925d5e9
-	0x8a233ed2	0xda8e6369	0x43028013	0x91b72d39
-	0x6b75eb99	0xc7bb03bb	0xab135e5f	0xb73cbade
-	0xfb7b0cfa	0x62ef94cc	0xdfdaa5ee	0x75c0f3ef
-	0xf020108a	0x6c54535f	0xc9583167	0x68fdd582
-	0xc6c95829	0x7fa6f2b4	0x9c7f494c	0xde5daac7
-	0x10088178	0xc27f2052	0x84714bf4	0xd2eb0ba2
-	0x23fd2e08	0x7c2fceb7	0x119bfd3a	0x029faaba
-	0x41c8cd67	0x2461da7f	0x25acc8ef	0xece252ec
-	0x997d4b00	0x3f19f111	0x68237934	0x518f427d
-	0x6c2a04d9	0x27f61e6d	0x68ebf9c6	0xf3ca994f
-	0x43e5c576	0xc4e1fd3b	0xe2393151	0xbf97bbec
-	0xefd161e9	0x5e3a816b	0x1d8b9bd3	0xecbc57f5
-	0x042c1237	0xcb1c852c	0x546f4d72	0x01b37ce2
-	0x20e30817	0x3fbd20d1	0x2ca11cc3	0x63cf6770
-	0xa65064ac	0x32d2cbab	0x9c1fb334	0x37c097ea
-	0x63ea10fd	0x7db8fc2f	0x8a4425dc	0x752ca318
-	0x9a570211	0x50f90038	0x90abfad1	0xe81169f7
-	0xd804a9b7	0x18b7efa2	0x6daabb80	0xf098566e
-	0xb5df2af6	0x8f23ef8d	0xed7dac93	0x4fbed0de
-	0x929b870e	0x60b5c69b	0x5589cc4d	0x588914af
-	0xfd78c6f8	0xd4018180	0x43d22344	0x873ee413
-	0x0ad0f12a	0x15200a82	0x749bff31	0x6fd4ca58
-	0xeea48890	0xc1507520	0x7a750a56	0x87c85e9b
-	0x2bc19182	0x9e7084d6	0xee8595b0	0x3c35ef78
-	0xaa19db33	0xbc4d7c20	0xa7b2c1ef	0x51ccd346
-	0x72b24c95	0xedf9e250	0x88a582df	0x42a27480
-	0x8fe7bfa3	0xb5f08d25	0x2cfb9e8c	0xcc118d13
-	0x50d9c479	0xf4abe2bd	0x1b22edbf	0x8f525f45
-	0xac39c5d6	0xb35d5c21	0x0e588e14	0x4715d55a
-	0x1b0ecbad	0x16e9e58d	0xcefb1002	0x8a37403e
-	0x70e90356	0x9b7a48f6	0x43bcf700	0x70470d6e
-	0x8e0dd0ea	0x7620f026	0xb4809687	0x8a3d8bef
-	0xdc0261a9	0x3e8d2dbc	0x6d48a5b3	0x4107a6d9
-	0x2dc369b0	0x671d66a3	0x559e6e50	0x4b8098ba
-	0x28209e38	0xf2bd6114	0x0a6f4f54	0x77a82065
-	0x406470a2	0x93cae58d	0xcf774ed5	0x7f4cdd72
-	0xfb869931	0x4ab42cd8	0x8251ded1	0x2c85fccd
-	0x14a8ae06	0x92333b50	0x53f605f9	0x3347f24f
-	0xf190509f	0xf72b525e	0x13a0f3ae	0xc04c7e10
-	0xa735fbf2	0x94df568b	0x71f6306e	0xcad6592e
-	0x1690c07f	0x64dda7ef	0xb03c8822	0x41f58140
-	0xc1953b66	0x2b4bae6a	0x278c23d4	0x0a02a425
-	0x10942d48	0x70557bb5	0x94981643	0x63214c9e
-	0xaa7ea265	0x505bf23b	0xa66c7082	0xf428671e
-	0xd1fdc33d	0x5817c28b	0x2ad4649a	0xb22b1eb1
-	0x17f29535	0x0423d04e	0x8b4d30cb	0xc36089f1
-	0x492dcfa4	0xe7842e60	0x7d4805de	0x02d4f43f
-	0xd3b6933d	0xa763e450	0x4301f667	0x58318b37
-	0x78d9dd14	0x84343bf2	0xf62e93a3	0x76d9d617
-	0x82c37d71	0xc3fa7cda	0x3dffa327	0xa171b148
-	0x4654011a	0x7cbd5689	0xaabe734f	0xb8226cd0
-	0x9d846c68	0xb9233e88	0xfc0b0bcc	0x2138ccfe
-	0xaff53d8f	0x9b0b8b80	0xb2be2912	0xcc871084
-	0x47a380a1	0x593c82ed	0x3cc8424f	0x5e77c12d
-	0x813626a2	0x8021e31e	0xeede3c2c	0xb8fea5ea
-	0x236a7fc6	0x783bdc5b	0x0d67a0ab	0x8987c13f
-	0xb6381e65	0x3b313687	0x52ad7a81	0x759ae49d
-	0x468ab620	0x8b735c2e	0x60937053	0xb3cf5867
-	0xb48525fe	0xd8bc07fa	0xf092e18b	0x6d8ce7a3
-	0xfeec327d	0x752e3f43	0xf106ac62	0xfe3489b7
-	0xa699af8d	0x1c5dcb5a	0x3a931d51	0xc1409944
-	0x843c3667	0xb923eb17	0x67c3d38f	0xd1edd5bb
-	0x4bffe68e	0x8b7acab6	0xe0058382	0x79de2e31
-	0x1e48cc0f	0xc4b8ad1e	0x5a00cf89	0xa4f6b8e4
-	0x29d42e0a	0x3d483f3e	0x746de9bf	0x0ce78994
-	0xcb6df646	0xe287b7f6	0x85907659	0x333127fb
-	0x6aac4a54	0x5ff7c669	0xd42ea2ac	0x92ae55b9
-	0x952f68e5	0x3273a013	0xec6cedbe	0x9ede1ad3
-	0x76d7c595	0x167c73fe	0x7c2572f4	0x8f653319
-	0xa1c726a4	0xf7ba8a71	0x5bc9b17c	0xc0d89104
-	0xc0ba5907	0x0e8c9c27	0xc8205b68	0x74f8aebf
-	0x02acd438	0x28783ffd	0x143ea70d	0x9c82abd6
-	0x9eb156e1	0x5951d075	0x5afb06d9	0xd14bac91
-	0x6ae19745	0x728cd46e	0x775cf71d	0x1126cf7e
-	0x058d4dcb	0x7f5f648d	0x5f37a908	0xd2fd843e
-	0x8dd64fb8	0xcdaa761a	0x105c38c1	0x9b5f440f
-	0x2dad00c4	0xd3c25b11	0xcc07bfb0	0xbc432852
-	0xc2d34e0c	0x0b1978f9	0x95a119ee	0xfc4dbdfd
-	0xae6d3b7a	0xff06ff00	0x30976600	0x9e47e68f
-	0x3308cf27	0x0a2d1580	0xe91ea75e	0xcbf12170
-	0xc7da3143	0xbe0a6ded	0x74d03d5a	0xb0869deb
-	0xbb94dec7	0xec2a053f	0xcb4fd13f	0x04912071
-	0xb1af28a2	0xee094f0f	0xa78a4965	0xcdded4aa
-	0x6d4959cb	0x93ee7709	0x2901d3af	0x6ad494ad
-	0xb95203f0	0x1fa160d4	0x7a06d88f	0x35f89a76
-	0x5e151830	0x27feb3eb	0xa9a9805f	0xc43b9387
-	0x5b6bf76e	0x3372d23a	0xbe2d27f1	0xad9b7282
-	0x5d67323b	0x2e96328d	0x3d90fe8a	0x9e4d4522
-	0xa2eba985	0xe1ed3264	0x28eab708	0x2551ba26
-	0xc143badb	0x3bebdacd	0x4da62bf1	0x875ffcaa
-	0xcc643e34	0x1b75c14d	0x13b84e83	0x8abb6f10
-	0xb82dd0fb	0xf31e4572	0xca8a5f58	0xb98da99f
-	0xec33fc4c	0x952384ca	0xd673c525	0x45f36727
-	0x269b8efb	0xfe5bc4a4	0x90325548	0xb8aefb93
-	0x6a2381c6	0xdc4ecc1e	0x7fc546b2	0x5348ca20
-	0x8eca0f26	0x5a49fa01	0x4b0822fd	0x862e680f
-	0x5abdf88e	0xeb23e8fb	0x2c023eb8	0x092cdb59
-	0xa15e0fbf	0x03f1e5e9	0x2c343bfd	0x8876aa74
-	0x5b80428d	0x4a4fba83	0xeea3da82	0x414a610d
-	0xecb123db	0x0f81b8b2	0xfdd1c970	0x8de71d6f
-	0x0ca553b1	0x57fc98ad	0x47d44eb3	0x17827c70
-	0x2d91f5b1	0xecf63cb7	0xb4fdb928	0xc49c42ed
-	0xeea589bd	0x62cf916b	0x02a553a6	0x50cb4523
-	0x959d3831	0xebfa026e	0xd2483d91	0x140364c2
-	0xa8ddcdd6	0xca343670	0x589a154f	0x6bf369ed
-	0x40eff32d	0xd7b49920	0xf4bff896	0x5a62c192
-	0x0a4cb0bc	0x449533d6	0xace20ca3	0xfae7465b
-	0xb6e0edda	0xda214fa1	0xcc08b6be	0x54c342cb
-	0xc09f8db1	0xead565c0	0xe38b2187	0xd0d0be68
-	0x16748998	0xced5a632	0xa0636b45	0xc71ab63f
-	0xfe161e04	0xe8b66fdb	0x878e2039	0x17af26c2
-	0x6851cb01	0x9484d4a5	0x697e6981	0x9946e0fc
-	0x970cbede	0x87d887f2	0xd987bd44	0x10dcae60
-	0x20239b60	0xe9ef795c	0x536f0f3b	0x2d4de85d
-	0xd50035c9	0x335410a8	0xee350c4f	0xcf94d278
-	0x688c98c6	0x3c0402d5	0xa8b8a81c	0x952c67e6
-	0xdf432d95	0xb74dd56d	0x77316d7c	0x56df9401
-	0xb8aad070	0xf5d1cbb6	0x206f18bd	0x59fdf55d
-	0x5de26069	0x31ab08b6	0x719a4d81	0x8f1c8212
-	0xc792bd91	0xd6f262c9	0xab4bd545	0x36f3c600
-	0x917c135e	0x1aa0455b	0xc1de8100	0x855db3e9
-	0x42d41a24	0x40955a66	0x8475c651	0xc7f44c6a
-	0x4e1f0df2	0x7cc5cd54	0x35a47bec	0xe6ac8550
-	0x8b43af30	0x6fcd1cb0	0xf37de1ef	0x00c70de7
-	0x63913125	0xb33688d5	0x8c296f13	0x93570308
-	0x6d8aafbf	0x67a574e9	0xf297b1a6	0x53600c84
-	0xfdea2e69	0xe75cf59a	0x1b0e3dd0	0x7f7fa8c2
-	0x7e463346	0x97c7069a	0x671ce307	0x2441f370
-	0xbbeb3a08	0xc2e4448b	0x2157fe23	0x70954499
-	0x3038e792	0x4a8a2fb0	0xa1f4541d	0x7c88605a
-	0x6a4edc03	0x689fe83b	0x93835e79	0x19c99c39
-	0x9ea7dfa9	0x36bd28c2	0x64ac057b	0xa2987c35
-	0x9c3f17ad	0x0be5e9f8	0xef63c94d	0xee32f2b1
-	0x3781a3ae	0x9ebe229f	0x77467a2a	0x1dfd79fe
-	0x24ed349a	0x3008c1c8	0xb77520f3	0xbf831d15
-	0x11dc4dee	0x7b5e47fc	0xfefa0f69	0x2a820af8
-	0x8e133d47	0xa021cf99	0x7886d896	0x8edadf3d
-	0x89a10318	0xb048ce73	0xd9843457	0xe000594b
-	0xff3c1ea8	0xd93a7c02	0x8471da9b	0xf24ccfcc
-	0x6f0576b7	0xeb024ef8	0xaf75787b	0x508fca52
-	0x18315250	0x74482410	0x169985c9	0x911c14ef
-	0x96575aa6	0xd4791358	0x1bcd07b0	0xf91ff654
-	0xc3b9c8d0	0x101e8aaa	0x84b8352b	0x16f57154
-	0x843a47f1	0x88269e3d	0xa625bd0d	0x99c91f9c
-	0xfe79c26c	0xd1844839	0xaa59ec6d	0x1e1b9ca5
-	0xb99e4bf7	0xc8c06104	0x29985a13	0x2aa0dea8
-	0xa92de35e	0x8242311d	0x61e0a059	0x09232eac
-	0xc7e8f2b4	0x05fbcfa5	0x41d2cac9	0x5d2026f9
-	0x69b970c0	0x0274700a	0x1f5f23d6	0xb98aea3b
-	0xd879d256	0x69230276	0xbec32596	0x6d4dcd0c
-	0x04efed6b	0xcf5ca09b	0xddd17a77	0x821a0172
-	0xe656d7e6	0x70dd6839	0x75710294	0x59765f6f
-	0xa3174d9b	0x4227c2a1	0x23ddd6c4	0x1d7d8c79
-	0xb2e50bb1	0x98744c39	0x853152f9	0x4d439b89
-	0xf852ac32	0x89ad2fd8	0x613c8c1d	0x47ab4071
-	0xdd62c705	0xe623a5ec	0x93f4bf07	0x5053a3fe
-	0x2545e42c	0x03e4ca84	0xa5dcf9cf	0xc279dd6e
-	0x6e3e2248	0x51c6338b	0x1b79f55d	0x871d7595
-	0x1991ba98	0x697bf68a	0x634bef62	0x415df824
-	0x007523ec	0x595fe4f3	0xd2018516	0xcfa8f6b3
-	0x1e3d33da	0x141858c4	0xa553fa95	0x0ba00794
-	0x923edb17	0x86a18480	0x4aa94d38	0x429814d8
-	0xdd0d853b	0x375808f6	0xcf857aba	0x6f6d5dc9
-	0xdc27fee9	0x7c49718b	0xb3eb09ee	0xf48ba9f7
-	0xa7f8deaa	0xa0afa80f	0x84a0ea27	0x63858132
-	0xa552f06d	0xcce0bc50	0x70a6b770	0xe21c7251
-	0x1fb70601	0x2e93b5f3	0x1f257ad1	0xab09dde3
-	0x176c80a3	0xa1845a72	0xcf68a2e2	0xe3bdd613
-	0xa41d6e7e	0xde870606	0xc292df07	0x7093562d
-	0x692e5e51	0x179dd237	0x01dc96ea	0x3a2efdfc
-	0x6088f181	0x7c3d290f	0xbd38e29c	0x340cead8
-	0xdca8ea9a	0xa43a7899	0xf6541b9c	0xafabfe18
-	0xb5557f4b	0x995bcd2a	0x5355ea0e	0xf3dcdf66
-	0x02216d50	0xaa3a8f23	0x1c63637e	0xb8950554
-	0x7199e726	0x20fed1f2	0x027d67e3	0x7d5a236d
-	0xd1e01da6	0x2db0e750	0xfba1d718	0xa58b42ea
-	0x839b80e9	0xcc55d1aa	0xb1da75e5	0x50789516
-	0x818913cc	0x03facba2	0x6e2bda29	0x1e3c1120
-	0x8fe64712	0x12317a15	0x6e6bb39f	0x7edd5bbb
-	0x900bf72d	0xc6a822c8	0x3353d602	0xd9965f2a
-	0xfc290ed8	0x9c8210e3	0xaa84d5ae	0xdf9f1507
-	0xbd10f9ff	0x50a4d9f4	0x22111607	0xd4043bad
-	0xfb7b42e2	0xe0285329	0x4e76e1a7	0x4188ed50
-	0x88cd2a99	0x4727768e	0xba625d6a	0xf8ad5d67
-	0xcc1595cd	0x36984dda	0x7c9f8fcb	0x4e9ec35e
-	0x37f95b62	0x8e70690a	0x8e43aeec	0xf3434e0c
-	0xa4b3ccee	0x99c0d714	0xee0082c0	0x9d9f002d
-	0x3eab3543	0x829e9098	0xafe4e802	0x5337a928
-	0x9bfd2d3c	0x43b69305	0x2c10167b	0x8b06b92e
-	0x949049c3	0xc98231a3	0xf77c9543	0x9961f18a
-	0x36a63fa0	0x039932f1	0x1179d978	0xb43063e0
-	0x89bc1a9a	0x2a61348d	0x34113ada	0x1866335c
-	0x8b0249ef	0x94c2a8a9	0xd002ae9c	0x029e1f71
-	0x989a3204	0x57b1aaea	0xf2d06793	0x62f17706
-	0x656e06b8	0x022897b3	0x09c381bf	0xafd90766
-	0x8c79df8e	0x665a6727	0x33c2cd0c	0x2e61c4aa
-	0x9dd83f35	0x01b2b241	0x70f5d0e4	0x0e98f63f
-	0x800dc70c	0x8eb5c772	0x7defbb2f	0x763810f0
-	0x7ff959ab	0x07640942	0x7ca07fa5	0xa7bace66
-	0x208a078f	0x2975dd73	0xa4866e67	0x271f5bac
-	0xdca36998	0xe5e1d1fd	0x511f9ffc	0xafac1c08
-	0x827968f9	0x8823df83	0xba2c243c	0x3e2a0d33
-	0x77e0cd0a	0x623d50a3	0x278f115b	0xb79a27e0
-	0x51ab943e	0xdda62a6a	0xb42ea0e4	0x2ae47d5f
-	0x5ceb281f	0x022dfce9	0xe1f879f7	0x6fe70f50
-	0x1d98abe7	0x0828e611	0x8ad0ba15	0x61bbd7be
-	0x5cde8df9	0xd78b7375	0xe1cf9350	0x9faae80b
-	0x5564c0dd	0x3d735e25	0x64985c05	0x20ac585d
-	0x57e9da3d	0x495cf386	0x1889c50e	0xc313efb3
-	0xb3f5e423	0xbb87a9b0	0x3cd06b09	0xdf51b230
-	0xeb2801dd	0x6d5d43cf	0x1fba7400	0x08791e6f
-	0xf90e0873	0xa65df0b8	0x64369b67	0xc22c9200
-	0xd840f9f0	0xcc49d4de	0x9987db7f	0x8fec9974
-	0xc826c852	0x657bd87c	0xcaddde2c	0xeb0dc447
-	0x4a45ffa9	0x035d22b0	0x236eceff	0xa3ba5f8c
-	0xccee0a9a	0xbad5d1dd	0x1cc8b587	0x5f11d469
-	0x99f8c63e	0x64311906	0x43c19b36	0xef9d5e86
-	0x00705473	0x78100dd0	0xedab57b3	0xf3b00610
-	0xfc6e3467	0x6c4bff2f	0x97227c44	0x38ca257b
-	0x4e79fd63	0x0c8b3466	0xa2ae7e62	0xb01fba5c
-	0xdeee261d	0x2a4c6387	0xb9dce78a	0x2f0905c3
-	0xa76a7929	0x5f3fa1f0	0xca4e5260	0xccba772d
-	0x862fec80	0xb8257aa1	0x7c79cfac	0xc75d7230
-	0x387e536a	0xaff486e5	0x3c549063	0xeea5fc5c
-	0xc433a55c	0xbfb619b4	0xf36fb0c5	0x4faab4e4
-	0xbcd75d84	0x6eb5ee8c	0xaa4e29a9	0x551db0d6
-	0x1ccbc659	0x9b5e8c52	0x1e33bab4	0xcfd30d60
-	0x6366c21d	0x3f0d7056	0x7f2247da	0xaba4f322
-	0x7b0ec4fe	0xdd64dd73	0xcd538711	0x67dfcd4b
-	0x02d1b6f0	0xef0b6e60	0x1058738d	0x0c056ad5
-	0xb40abdbc	0xfc2549e2	0x6fb269b6	0x08f7ec08
-	0xea0a76de	0x7e97ee14	0x4eed0856	0x75ba49db
-	0x8145dd79	0x43101098	0xac911399	0xf8aab5ed
-	0x1e9d391b	0xb2a3fbe1	0xa394939f	0x12b8300e
-	0xa5f5200f	0xc350dcc7	0x1b2380d2	0xa599b322
-	0xe219e0d0	0xe4912308	0x0ad305cb	0x2e22d468
-	0x599eacdc	0xcf3b7eba	0x65fe5903	0x44f6cb16
-	0x0ab29b19	0xa74185e6	0x41736bf9	0xeaf231f9
-	0x762d0e7f	0x8b445ce4	0x173d3775	0x138da565
-	0xe4f7f652	0xe62e4ae8	0x91ce0ed8	0x1fc94878
-	0xe44acd84	0xe4402b5c	0x6437aaff	0xe7b0d8d8
-	0x514fbcf5	0x4b3bf5bf	0x0696b5d0	0x89a562ee
-	0x02408e77	0x94cc3287	0x47860ed4	0x42aedc7e
-	0xe9f0f3a2	0x4cf19812	0x3181341b	0xd72803a2
-	0x42f5c8b3	0x5735456a	0xef70c247	0x5943b8e4
-	0x7c62b0e9	0xc507e2e6	0x85a2c82f	0x95c6d92d
-	0xfeefff6e	0x5740c004	0x1958f117	0x44ebaa15
-	0x9f061786	0x732a8720	0x9483f974	0x839d5b20
-	0xeefb728b	0xae2d4b7c	0x49bcb243	0xd86db07b
-	0x73b0542f	0xc5a34fd7	0x5b9401fd	0x7f75e686
-	0xb239ec36	0x41e7943d	0x2bc517f7	0x27057733
-	0xf6c9cbd1	0x2965ef66	0x969b44e6	0x77b66e0f
-	0x68b93916	0x31d581c2	0x8520df18	0x16ce6af1
-	0x70bbf865	0x6d1ea78e	0x989ed713	0xf97c0d1d
-	0x538aef6b	0xf1ac3c76	0xf65f8bf6	0x4f4d3a8d
-	0x639d90ee	0x43079e8c	0xc9d50f0a	0x9b12ec49
-	0xaebe3d8a	0xd1bc3cc6	0x8b92e348	0xd056119c
-	0x7aec25f3	0xb3d2cf65	0x32c03540	0x53287cff
-	0x0bfa781b	0xf8610282	0x18a2d96a	0x541a6f1a
-	0x6052aac0	0x4f79e46a	0x7c868b93	0x6547a94d
-	0x58326c30	0x98e46f02	0x77cdd3c2	0x204ce551
-	0xa5e32028	0x679e3153	0xc7880c16	0xf32743f0
-	0x63c8892b	0x51d8a6ea	0x42bc6417	0xdb8ae71d
-	0x04c71f86	0x1a5bd80b	0x810f3b56	0x049580a6
-	0xd384d2b4	0x92cd10c8	0xaf4e6ce2	0xac955cc4
-	0xf57b42b7	0x1017f2b4	0x3031fafb	0x3d1a8024
-	0x3aca42cb	0x75514d81	0x454b1806	0x5505c3e5
-	0x26d2c642	0x57454f1b	0x5e2d3c9b	0x6535eaf5
-	0x370de383	0x6adfbbe2	0x513a5d0f	0xfc48c333
-	0xa0a70bcd	0x35777e16	0x5ecec516	0xb7879d7b
-	0x08928fd4	0x88c8048f	0x4a0d2896	0x5bdae2f1
-	0x8761b488	0xfae8bb60	0x3c8e8abc	0x13939d3c
-	0xc29493ca	0x585a71c8	0x43205f16	0x06a3be38
-	0x4be88f47	0xd2be8c8e	0x3d721e2a	0x43051f74
-	0x922a9a30	0x6391fc85	0xc4965afc	0x61f082e9
-	0xc2686e37	0x4f77b6a1	0xac47fa16	0x1eb05157
-	0xe6f767a0	0x24177985	0xdf80b368	0xb54d959c
-	0xa5719425	0x656c70de	0xf35dfd40	0x702d5063
-	0x4e7ac001	0xc4bb4fb2	0x4af7b9e5	0xe0eb5c48
-	0xf08b19c0	0x468b1471	0x74af9030	0x51d171e9
-	0x81a59926	0x55b893e4	0x17adeb1e	0x72084962
-	0x7f358bec	0xbd4363b9	0x75a56726	0x3a033a75
-	0xd0fbf874	0xa6bf634f	0xa5e4be7f	0x4cd8338c
-	0xef6838b8	0x1d458215	0xff7698ba	0x4ba19dec
-	0x87f58c07	0x2c7933a6	0x1cd4f99a	0x158bba9f
-	0xffcedb5d	0x256eb5d7	0xcb6dadde	0x980349bc
-	0x6169dcf3	0x94267861	0x168ba5e4	0xd2063474
-	0x156c9738	0xc4bd2c2d	0x31ad709c	0x58cd43e6
-	0x76ba9c33	0x070f490b	0x357c3929	0x103bef50
-	0x82ebacfe	0x5affdca2	0x96d0965d	0x60911a5f
-	0x65d4f52a	0x795b3094	0xf56291dc	0x6e614bb5
-	0xf701246d	0x4953b1b4	0x15e4e5fa	0xb6954973
-	0x43ada767	0x4c0a9f27	0xa47f78da	0x52375c95
-	0x79770885	0x479c5aed	0xca2ac2b8	0xee74cc5d
-	0x752f00d4	0x2b5532d6	0xd3641edd	0x05eb0e05
-	0x5118c9a9	0x47a0e0b5	0x5f12d793	0x92019247
-	0x27d77d98	0x0e413c92	0x76e4aea0	0x9fa8e3f1
-	0x3c57e54d	0xf4a60ba2	0x5bb37f64	0x8b214f1d
-	0x320f3bec	0x1cfd1f0f	0xb0cf5b70	0xf26a138e
-	0x37bb143f	0x993d3fa6	0xde4138c2	0x9fa287ba
-	0x137617ff	0x591624c0	0x1d10f02a	0xf7e350a2
-	0x76bc2933	0x12af6e72	0x1777e320	0x3e161b20
-	0x6c9fd66a	0x0b30f462	0x9cb717cc	0xee2902ba
-	0x466d7b9e	0xe97c26a4	0x7406b88a	0xf15a7209
-	0x3d2815c1	0x3eb961e1	0xe5321371	0x05f60ece
-	0x39168ef2	0x201a9dfc	0x90fdb132	0xe4531401
-	0xbef01e52	0xade4b385	0x6ca0c911	0x7586ff60
-	0xe457457c	0xfbfa3688	0xc826a1e9	0x10360416
-	0x192b51d4	0x18471973	0x3f0dd5ae	0xea2bbfc1
-	0xbe099b58	0x8bd8efda	0xdfc56e40	0x9e50f4e9
-	0xceeaab0a	0xd1eeb5d2	0x840a3cd2	0x6b739449
-	0x4a94e95f	0xe53720e7	0x68c70986	0x1cec3aeb
-	0x2423ad9a	0xe83b9246	0x7ac4b815	0x3796ec1c
-	0x65ec7484	0x79e5b0cb	0xd25f4790	0x55573d75
-	0x0f24c1ae	0x6d5d9b62	0xf3b2788c	0x2c695087
-	0x0980abb0	0x5086c2b1	0x26a247e9	0x72071084
-	0xe76c66a2	0xcc9c0bba	0xc67723b5	0x19a809d9
-	0xddc03879	0x7161b52d	0x24ee285c	0x5a345427
-	0x0626ef30	0xb734a77e	0x8ff087f3	0x80222e05
-	0x91b6c40a	0x4fe76862	0xef66e1df	0xeedb9f06
-	0xb785ea7e	0x0e84aab2	0xd0a669d6	0x7ccc77d0
-	0x264df92e	0xe9d1b14a	0x4b517134	0x05444463
-	0x408e7bb2	0xe7ad2bc4	0x5d8cb4c5	0x61e508ab
-	0x9798953a	0xa6848924	0xf26be53c	0x8940d4f6
-	0x56f11005	0x6d8d60ef	0x03c374a9	0xce0dbc18
-	0x341e634f	0x64e7d2f8	0xeb201eb7	0x2dee184b
-	0x57ecd83f	0xd8f644a9	0xca4493e8	0x66347804
-	0x542e06e8	0x55f607ea	0x7f425fa6	0x362807b4
-	0x731c87c3	0x4b5d6e1f	0x03e70201	0xbc5f4080
-	0x899cfd7b	0xa651d567	0x9c333e24	0x8b0eedc1
-	0x53ff0c74	0x7db69633	0x6637bbda	0x5ce53c7c
-	0xe93bd003	0x91234974	0xe8a626f2	0xc6550418
-	0x1b4157aa	0xc42ff7e4	0x1b9213ae	0x70d84165
-	0xc7cb09cc	0x38bf0221	0x238ff6b7	0x3688fd5b
-	0x5694728f	0x4a8e4cfb	0x3cd7e1d2	0x72a41c1a
-	0x2d098e4c	0x5a0ab21d	0xc8a40160	0xf252b062
-	0xc172763a	0xaedea2e4	0xeedcbcf9	0x4c0d2216
-	0x02b5eba5	0x410139da	0xde4ff14c	0xa53ca456
-	0x8c30792f	0x6af27a7b	0x734b1dab	0xf4f60014
-	0x79fc3cc7	0xfc578e4f	0x20948f41	0xb4fbe4c4
-	0xdbb21292	0xac1aa341	0x7ffb8913	0xa498296d
-	0xae1e8f6a	0x167d82cb	0x094513fd	0x8f0810c7
-	0xd01d348f	0x700d0063	0xeaacbad2	0x23d45e0a
-	0xe3b3a244	0xf2f7100b	0xf680fb9b	0x529efdd1
-	0x01dc5480	0x263328c6	0x686fbe31	0xbf3a1057
-	0x34c763da	0xae45207e	0xcb5abb2b	0x011c0faf
-	0xde2b6f4e	0x3d95034b	0xacec6e7a	0xc792595e
-	0xeb3cd922	0x7894f0d5	0xd9a7e62a	0x1a3c2ea9
-	0xa8f22d99	0x1ffaa636	0x47c6f1ff	0x69feca71
-	0xcf8d73d6	0x1c85d0fd	0xcce984c1	0x993f7a9f
-	0xc095c139	0x1c013486	0x675a753e	0x01030902
-	0xccab4cd7	0x0c14c605	0x5ebc19b1	0x60ad33a1
-	0xe80e1200	0xdf49db31	0x855aee7a	0xbfa37ef2
-	0x135d844f	0xdde541e3	0x0522f180	0xa27312bc
-	0x57046808	0xb96fe1b6	0x77c2806e	0xb90ac06f
-	0xa425864e	0x857ff22f	0x16eca5a6	0xbaa58ca6
-	0xab30772e	0xb20507fc	0xa593f6cb	0x9e7e8409
-	0xac4ecd8d	0xa9c0561b	0x0c462492	0xb3ee5aa1
-	0x83d3d56c	0x5bc20412	0x03365294	0x09758ede
-	0xe9e6968a	0x80ffc576	0xe62ddfd6	0xd5934635
-	0xe07f36e1	0x99c0db4e	0x2dcdb7ed	0x68749a34
-	0x4f718748	0x630b1315	0xe632adbb	0x4c111085
-	0x13bbfaf1	0xb70bd522	0xf22068d1	0x4ed37edb
-	0x7c50ff42	0xa6b61456	0x828deb4d	0xf19dc8ae
-	0x7ed7560e	0xb47a1aed	0xb79beb35	0x720d104f
-	0xff5ecb74	0x1e7d9f8c	0xa69f72fc	0x743e81bc
-	0xa11aacfc	0xab8fdc17	0x263ea36e	0x840bc0ec
-	0xb994aefc	0xcc5922c4	0x08411c01	0x0073895d
-	0x7b661458	0x8bf91a68	0x93112089	0x541e53ed
-	0x37706daf	0xc8733951	0xe74fa74e	0x638cfb72
-	0xe696bdc6	0x87f4b7c7	0x413acce6	0x16642eec
-	0x83b0ecf9	0xcf770d15	0xa4aad143	0x2ecd9f9a
-	0x5bd7a2c0	0x07dca9c3	0xf6ab7c5d	0xaa4a55c2
-	0xd410d6a8	0xdb84dc85	0x6b8e3aa6	0x8f268bb5
-	0x1e9604cd	0xb5fabbcd	0xc8a519d7	0x07fdab7f
-	0xceee08f1	0x08b9566e	0xaa646716	0x4ba7ca9f
-	0xe0166e0d	0xb31e9561	0xbb9315cd	0x42201352
-	0x5eae88f3	0x8b8e8eee	0xd63d0610	0xe64a45bd
-	0xc2e8a084	0x2e421cb3	0xda754ee9	0xcdfe2c8b
-	0x52b5544c	0xe5c0616e	0x387916c6	0x204c7ca3
-	0xdc507264	0xca026018	0xb4dc7a91	0xa9f27453
-	0xfb6995c8	0x349b640d	0xe59e1670	0x53d18974
-	0xa61ee5e8	0xdc8b88d7	0x78d2f8f8	0x72ddf8c1
-	0x7345705a	0x1e6ecb19	0xff0f4f31	0x197ae361
-	0xc2e43f5f	0x80a2bf1e	0x274d46c4	0xbb3ae1ff
-	0xd59798f3	0x5bf16015	0x871d2acc	0x4044c5b1
-	0x9ea15fc0	0x9a735765	0x1683fd6f	0xfeb503d9
-	0xc3de1998	0x14405d5b	0x86b76966	0xb3893dbd
-	0xdb365404	0x6636d465	0x63558798	0x758d5f12
-	0x6e225d18	0xad787cc5	0x775a5c1b	0x68112320
-	0x23e1ea3d	0x8cf63961	0x0596cb9d	0xe9ca89e5
-	0x96cb88a3	0xb7cac802	0x3b38edc2	0xb455d1ae
-	0xfb215ed9	0x9cfe7580	0x0410155a	0xc6b75ca3
-	0x359ef846	0xf96db47a	0x9800cc06	0x9ab0eeac
-	0x1c86094d	0x19537992	0x3cc54b13	0xe877a758
-	0x35c01849	0x396470de	0x8c229cb6	0x2b01a145
-	0x54ae9638	0x33b0bb07	0x5d38fbfa	0x3a08d46b
-	0xab433b4a	0x6be993fa	0xe85fe0e6	0xd4d2b82c
-	0xc35398ca	0x66200602	0x51df5ed3	0xddb67c76
-	0x6a4c2d36	0x9a02eb04	0x8ce871ce	0x66753dbc
-	0x5441d00a	0x3d331728	0x80c55fcc	0xac286e97
-	0x71fad042	0xe99c0cdb	0x3120ef01	0xfabe32e3
-	0x265699eb	0xa73e31be	0xdd44e3fa	0x668531dc
-	0xd4ba1078	0x0f13c8fb	0xa136ed20	0x010f3c83
-	0xb3f8eaa6	0xc6d95837	0x0e09bd46	0xf0ecb760
-	0x8dd905c0	0x02cbe8fd	0xfa898489	0x14ab16b4
-	0x6ae99a74	0x516a171a	0xaa60c4c8	0xc075f0cb
-	0xef530ecc	0xf6fffd33	0xe1d2af99	0x6913b9ec
-	0xc96666c1	0x20743c9d	0xf65cd424	0xa671b903
-	0xcbff34ba	0x60df0c1c	0x0d610133	0x4281a959
-	0x656230ac	0x1693d52a	0xf4d37186	0x203caa5c
-	0xa54cad8d	0xea1c8816	0x5bd54f8c	0x2a3c33c3
-	0x151f72b6	0x63061580	0x0bc7f244	0x882f7656
-	0x243d76fe	0x9b3bf7c6	0x3337a21b	0x8b9e3e63
-	0x106289a1	0x74ae0571	0x8a43a5a9	0x7ad8c804
-	0xb6867d45	0x45732f84	0x0d1773f6	0x9fc01aa7
-	0x7b192c33	0xeeab4a4c	0xc96ae493	0xb5aad8be
-	0x8b32c8cf	0x8ebf63c8	0x5f2a5e17	0x43a2899c
-	0x35ec1fc2	0x7c675072	0x6673d01f	0xc1d85b58
-	0xf73dec41	0xc1c89c18	0xff8fac98	0x434c3c5d
-	0x184ee2bc	0x3469f366	0x2558fbf7	0xa0e5622a
-	0xebb39f69	0xe9020554	0x3cd80512	0x767bcd48
-	0x2e388fca	0x32eaa226	0xeaf4f6a4	0xbf7fb5ce
-	0xdde75b24	0x30365d1b	0x48fd5203	0xca805f98
-	0x82526a04	0x51a8dd82	0x61fdd2d0	0x3ef56891
-	0x6d5d53d0	0xd83646eb	0x1d7a7086	0x7ac52300
-	0x69e4359c	0x7c8058f5	0xf47d703a	0x21b863a1
-	0x608b8362	0xb9a78389	0xa9d2280e	0x16672055
-	0x05501917	0xf2e01be2	0x261a10f7	0xfe455dd0
-	0x902a0cf3	0xbed63a74	0xeb4bfe27	0xab8b091c
-	0x4cd8f22e	0x48dbda13	0xb3d29b0b	0x65bf3d3f
-	0xe9be4080	0xfdbf0a24	0x9181ebdc	0x5faf48d6
-	0xaaf1acb3	0xe2a2aaff	0xe1ae56f7	0xbd475702
-	0xbfbe292a	0xa6133579	0xadfd6723	0x289485b4
-	0x92667c06	0xee16866a	0xfbc71087	0x0cd78050
-	0xfd40dfba	0xc9834441	0x5cfac60c	0x844b44ba
-	0xe1e4d8ac	0xd6775e4f	0xd4f01979	0xab5faf6a
-	0x63e03982	0x7789e272	0xb75dd171	0x39d0666e
-	0xbd90a902	0xa4eebba3	0x2640274b	0xbcedd52b
-	0x87033b15	0x2048812d	0xc13c2230	0xa7d345d9
-	0x84b4fb4d	0xbc0960cc	0x4c7422ec	0x4bff7ea9
-	0x16315057	0x1a9c50ee	0x5441830e	0x61cc7b9d
-	0x2f7cd3eb	0x6ae05c81	0xc264d759	0x4c6dd592
-	0x3d47dbbe	0xf8797367	0x4ae67c6a	0xdb42d373
-	0x0f6a6e9f	0x3d6c6b82	0x16906b77	0x80f7dbbc
-	0x6ee0683a	0x1afb8d53	0x4df1322e	0xc7d489a0
-	0x9d06aab8	0x08c5ebc4	0xd8cf4766	0x0be222da
-	0xd45596ee	0xa8113953	0x1a42b7c0	0xf4de2c73
-	0xe5741505	0xeb9032d7	0x480ab9f4	0x595e824f
-	0xc87c4e6a	0xe636b3c0	0xddb3438a	0x03f6ba20
-	0xd43d9bf5	0x3bbe086f	0x6385fdd6	0x0b9d62ae
-	0x1b9fc458	0xf6d1cffa	0x168ec5f7	0x93c98771
-	0x018c51fc	0x3a6c5880	0xbc4d25c9	0xb90c47db
-	0xccee6371	0x289878aa	0xb63ebf23	0x9fdff591
-	0x863d71c7	0x1301cab8	0xead66f03	0xf8a74303
-	0x91439b31	0xcbfc5008	0xc78a05c7	0x172ddb38
-	0x16254ebb	0xf490cd3e	0x9724bdba	0x915c5eaa
-	0x2d971801	0x672389af	0x25023172	0x69fb7e23
-	0xc5d66742	0xdb578a72	0xbb6fe6ef	0x9ff3920f
-	0x9e04e6bb	0x9bd9079c	0xe70a3479	0x1f423c00
-	0xd3a901dd	0x7fceda2a	0xf1999db6	0xeb73cb34
-	0x891cf0c9	0x55313b9a	0xe74ad3b2	0x98fc0593
-	0x9ec6c756	0x7b84cb06	0xb06c9cf4	0x604b8b04
-	0x112e4063	0xeec6c6a8	0xab9b6bb0	0x33e24999
-	0x14c1cb98	0xac0fdd7f	0x2b9a1d04	0x7fb3667d
-	0xd4375e71	0xe0b840e4	0x1c0789d3	0xe67c6b6e
-	0x00b8439f	0xc0be1ba8	0xfd6bac10	0x3a7e3be0
-	0x3c6a0d2a	0x38eb71ab	0x43711d1e	0xdbce233d
-	0xce91e57b	0x2f386b58	0x88ca7857	0xbe5bf50e
-	0x487a5b5d	0xb6470361	0x91e09471	0x18ee543d
-	0xe1857917	0x60d489ae	0x5d44c618	0xc6f46454
-	0x3cc37b33	0x9f8cf96f	0xd365b8f1	0x721f6448
-	0xdbe1a2e8	0x81651a33	0xcf105b61	0xf4ef4f94
-	0xc4693805	0x801e2a58	0xc932d045	0x6352f5b8
-	0x731cb8aa	0x3b2a6546	0xad87d205	0xa6b41613
-	0x8cc971a6	0x5cb47978	0x86b89ba4	0xb482b4a0
-	0xe326080c	0x821b137c	0x2a154131	0x094b02a8
-	0x56a1868b	0xa8a38181	0x8815878e	0x749bb12a
-	0x8bab2a16	0xfbe0bfd1	0xabef2266	0xd59d9169
-	0x975b6018	0xdb45a39d	0x6e31771d	0xa373d6a0
-	0x214d69c0	0xa4cfc886	0x30a8b314	0x558b670c
-	0x7cb96533	0x9c6c1dbd	0x3bae20a8	0x6a792685
-	0x1a5d6816	0xd085f694	0xcf367101	0x908cc2d7
-	0x9a7eed70	0x1e19978c	0xbf77c25e	0x5098a627
-	0x2129095d	0xcb5c81c7	0xa2888a61	0xc9df4b0f
-	0x0f20511c	0x6a16bb53	0xda26eb80	0x9a0190c2
-	0x372ff753	0xe1ae8ecb	0xe54e1e31	0x967b935a
-	0xd58c26d6	0x7d4a5515	0xa8f41efd	0x737a8b53
-	0xb2a33b65	0x7d04ef67	0xfd491b9c	0xffe6c29c
-	0x54424355	0x50c502e3	0xd8400ac4	0x6f17dffe
-	0x8be39f17	0x6b3055b6	0x20c445f3	0x6cef7ee4
-	0x821cfb2b	0xab19d476	0x540476d6	0xa6d1099c
-	0x223acfda	0xbda49356	0x403d63a5	0x2b83600e
-	0x45e5e0db	0x10323cf9	0x80675f78	0x6acc9d72
-	0xf0d7b6bc	0x122fbbaf	0xafef53d0	0xa606b680
-	0x13e91e0b	0x95a464dd	0x54ae9057	0xf12e1c07
-	0xde806b00	0xce8904ca	0x44ef27a3	0x14f85e0a
-	0xbc1bd0a7	0xa19863a4	0x7bb14eab	0xc3fe7ff3
-	0x1c915fe0	0xfa45a07f	0xab471bb8	0x335918ae
-	0xbc91e280	0xd27ab8c6	0xf79a0fec	0x0d54b501
-	0xf870aaee	0x44c1b504	0x60d2338c	0xe2f01abb
-	0xad4ca3b9	0xe8f97018	0xb3810e3b	0x3f885db3
-	0x6890f6a4	0x8568faf9	0x503d9690	0x709dc422
-	0x11f02c4f	0x57305bce	0xc1e07251	0x3b8b0c3d
-	0x3da8d742	0xe5956aa6	0xf394f116	0x07daa257
-	0xfd5b1b25	0x354b3d77	0xc2587f36	0x6fa8083c
-	0x6b8b8a0a	0x71cebc82	0x799e5566	0xd66e6525
-	0x3d80e29e	0x0a1dd883	0x7886487e	0x5d80604e
-	0xf7533c54	0x53c428c2	0xdb5c0cb9	0x211fbb3a
-	0xc7fd4590	0x409ec2d9	0xce50ff5b	0x142bcc4b
-	0x475f8d75	0xdc4b4f3a	0x1f230600	0x863d868a
-	0x5a8cfd49	0xc761fa43	0xa2ee8f88	0x5e8dbe56
-	0x9a140e41	0xf5c00dcb	0x04786e5f	0x6c2baa7f
-	0x9e4cb1d6	0x4074ee5d	0xbb4f106e	0x9afa4259
-	0xefa345c2	0x806cd3a0	0xf51afbd2	0x653502a7
-	0xcdf6fac2	0xdf756b85	0xb89ef192	0xba0b2652
-	0xea1b3853	0x4edf3f15	0xccaf559c	0x11721dba
-	0x36ab3f38	0x198d218d	0x5bdd7b39	0x3be8d3cf
-	0xea3e6882	0x6ed8fc9d	0xbffeed09	0xe513b75e
-	0xdbb9f2c9	0xf693d870	0x7bed8b14	0xe98cae50
-	0x591d36d1	0xba55333c	0x20048cad	0x7104e6ea
-	0x08a1335a	0x6dc416cf	0x431d8dfb	0x3f4db80e
-	0x3ae3f65d	0xdec93bf5	0xe1773712	0x8b9d6e9e
-	0x7a3599f4	0xa6292450	0xb7b68277	0xe57c20ce
-	0x3cf4eb70	0xf00d3dd3	0x9da300bd	0xa4b25418
-	0x6273314b	0xc5be2c6d	0xf297eb77	0x851334b9
-	0x9eba7308	0x7a015151	0xa3416ae4	0x7c54c0b7
-	0x352083c7	0x5c56ffda	0x1cf4d4e3	0x6ffef4b0
-	0xa8c972d1	0x6db1761c	0x4b2f3400	0xfab16aaa
-	0x437f0125	0x0c3ba2ac	0x89680f6f	0x7e48432a
-	0x0e465f0a	0x943cc778	0x075156f7	0x46249153
-	0xcbc017fb	0x0de6f92e	0xf380bcf4	0x9732a788
-	0x6e01dc94	0x5329275a	0xec971ab8	0xea971178
-	0xc1e3cbee	0xe598c0af	0xc5ca63a9	0x06018d8c
-	0xc55446d0	0x18e04c29	0xd19da94b	0x74536dd4
-	0x9837bbec	0x64bba10b	0xa63810e6	0x2189497c
-	0xfab9e5a0	0xde0267ed	0xbfb94a58	0x377e52fb
-	0xc8f5016f	0xd34b0180	0x2a5e942c	0x2ca6fe08
-	0xfd52fd5e	0xcc2f838b	0x7aeb73c7	0x43832892
-	0x2a44684b	0x0d8a7b22	0x9b84347a	0xacfedd86
-	0x966aed18	0x66eb4a8e	0x890108b1	0xda13caac
-	0x36c0f2c2	0xe2d85d85	0xc51f9f4e	0x9594e1b0
-	0x0707929f	0x63fa9d30	0x2b461080	0x18566f8d
-	0x40e12ea7	0x83e37963	0xa8d0eab6	0xb242700d
-	0xd928ecb1	0x6f5d6d73	0x603f5d48	0x4902cf34
-	0x9a477f4f	0x1b282220	0x3645ae11	0x09acad23
-	0xf772e479	0xd3c5b6b6	0x09abad03	0xdcbffe41
-	0xc971e22a	0x360a0c86	0x102ee956	0x9162221c
-	0x6a59f30b	0x9685277a	0x6dc283ba	0xcffd7ce3
-	0x0e487e66	0xd4dd807b	0x686bd0f2	0xc44a3392
-	0x6422fa86	0x6716d62b	0x2ac73404	0xc88fe77f
-	0xc49b6e01	0x8f011f47	0x5bb1ac5d	0x1d0ba4e8
-	0x7eb0d0c7	0x9db01b4e	0x6cbdaccb	0xd46f1c0d
-	0x96cc24e9	0xdbbaf254	0x9c5c45d6	0x325aadfd
-	0xca9638fb	0x1aeb36f3	0x8be8295b	0x705d0bab
-	0x9ceab5e3	0x5eb5288e	0xd7ec61fc	0x69bb3afa
-	0xad60164b	0xc435c21c	0xeb79ab88	0x145a58f4
-	0xae1e30ea	0x29987183	0x0a2a0432	0x160daa37
-	0x14e295e9	0x978315c9	0xf323f88f	0xe24d5136
-	0xae6ed24d	0x4a812cf8	0xd1e45d3a	0x64894447
-	0xf47d0453	0xb6fb5f02	0x34685ba2	0x8c700222
-	0x4dec7d3b	0xf035a0dc	0x9a802102	0xc3e27d5f
-	0x1928580f	0xeaa68f5c	0x46aad88c	0xfa913719
-	0x4fb0b232	0x3a638afb	0x4cd2068a	0xf26e4c98
-	0xe9da3c5e	0xc7ad41bd	0x3f1cc280	0x1fca9886
-	0xa777ff80	0x1ca76273	0x6a63123f	0x46d87fb4
-	0xd9282597	0xab9e06bf	0x3e244814	0xd9653380
-	0x48ab7d76	0x65d98e81	0x06047ee3	0x29b7ce31
-	0xae94d96c	0x856f9e8f	0x158f1b6b	0x9de1570b
-	0xca4ce67d	0x6f09907f	0xc891e152	0x6867c97c
-	0x02a5b2d4	0xf2e7c715	0x84f6da46	0xd603e51d
-	0xd837b33c	0x70de8d6a	0x598dd9df	0xed29a7a6
-	0x42da0f62	0x893fc276	0x56b43a06	0x949d4f05
-	0x7dde2d34	0x8b3f4c32	0xccc9c0af	0x01fdbdd1
-	0x2a3a3cdf	0xb6763454	0x7377862d	0xb99dd58f
-	0x9ad6cf20	0x2f80a8b8	0xc11b356d	0x4adae4cb
-	0xe808d693	0x3e8605d2	0x005cbfb2	0xfe966e1d
-	0x713b365a	0x4d12fc2f	0x1664286b	0xb5d41f0a
-	0x4420d15f	0x63e106bc	0xc2fe4169	0xe5f440c4
-	0x7fc0ae73	0x35ba3ba1	0x7a228157	0xfc50c107
-	0x2bd1f472	0xa9d03dd6	0x62d1a612	0xf93c55e6
-	0x6677a632	0xcd874d7b	0xa76ba1f1	0x2d82a8a8
-	0xa65e30ef	0xe48eaccf	0x4d7a4adf	0x8c276f69
-	0x0e229210	0x0096b100	0xa039ae73	0xea245d6b
-	0x0ea50d26	0x99b480cf	0x159ea81e	0xfa45f5a4
-	0xafd411d8	0xe1190cd5	0xc9e85cff	0x1e037ea1
-	0xf4be41e6	0x48fd1c6d	0x24d52f02	0x3780b91f
-	0x8e31dd07	0x1d392b15	0xb07e9d5d	0xf05b19bc
-	0x4f52d03d	0x846cf6a0	0x4d51d2e6	0xe4144ab9
-	0xa8f9558a	0xdbea007c	0x770f27bd	0xef95e02f
-	0xc01ba9db	0x8ad80d07	0x039bfc69	0x8f5d2e43
-	0x8640ff02	0x31872f4d	0xb959380e	0x027a8268
-	0xf39dd7d6	0x7c84199f	0x8f977814	0x6830b481
-	0x46495e33	0xd5c68952	0x6f2c3636	0x8de0e29d
-	0xc03f0b39	0xbc54910d	0xfa46af50	0xe81542c8
-	0x462d1ff8	0xb229a9cc	0x6a234b00	0xc96f857d
-	0x0a932f55	0xbd7fcba7	0xf937d965	0xc90cfd53
-	0x2ff150f6	0x0f5a40a8	0x805bfff9	0x92056edd
-	0xf6326626	0xe18371b2	0x9b9ce558	0x252d7e17
-	0xfbb7fdfa	0x3cf275e9	0x8ddc0be6	0x7e83319f
-	0xc61ee1ef	0xee1751d6	0xe267323c	0xd7229015
-	0x4a9cda9c	0x841730a9	0xd924dc44	0x619f2cee
-	0xb5172002	0x210144df	0xf6fda998	0x64f75cb0
-	0x3cd50175	0xdc7d3564	0xad0e94bd	0x18c876d5
-	0x7532124e	0x3b99841f	0x1a2c6219	0xe7d5ffe8
-	0x9f76b0ed	0x63437918	0x2b14f1ce	0x898a1cc3
-	0xfad43f4c	0xde5adcb2	0x8b9d0166	0xb4f2370c
-	0x1d212e4b	0x1f55058f	0x26bc79ad	0x681d1014
-	0xe0ddd0bd	0x4c256b7d	0x7268e89e	0xa422562d
-	0xd7a55326	0x6955e943	0x86ccb09f	0x03133a0e
-	0x2fe2399d	0xd9601d6d	0xdd128b8b	0x182251f6
-	0xa041ce84	0x5b5bc49f	0xbad64d6f	0xa7594fcf
-	0xb6dce9ff	0x69c7e4bc	0x83d16d70	0x41c2593e
-	0x282d55c7	0xcdcdddf9	0xd9855130	0x83fca027
-	0x32379a19	0xf8fa8dfe	0x0720d059	0xcba2a7b7
-	0xeab4e686	0x228601ac	0x660b45f0	0xecde3baa
-	0x4047d983	0x4ced2e8f	0x77aa1d0c	0x7e6cd6a5
-	0x80e06058	0x95d27baf	0x071433d6	0xc7d3d431
-	0x7856634a	0xa1b894d8	0x2faedc1d	0x1e05a846
-	0xa9bc7fa7	0x0ca15e02	0xbcc96351	0xb483c979
-	0x239681be	0x24354ba0	0x5c743a31	0x7ed77958
-	0x20a4d718	0x7b37986f	0x43a9e233	0x02091eb0
-	0xebdbf21c	0xffd2069b	0x6f191684	0x111e2666
-	0x8adb42dd	0xf26db866	0xff83d42a	0xc7d28a0e
-	0xec1bf909	0x10434bd9	0x6404e8c0	0xae30d43f
-	0xf415a59e	0x3daeca66	0xe1be615b	0x04db2d3f
-	0xa53b33b3	0x5fd6479c	0xab5ffe67	0x2cdaaaef
-	0x61087f2e	0xd805a00c	0x11d85656	0xc1ae3754
-	0x1fe38c7d	0x108e2ccd	0x3c6e1773	0x512eb70d
-	0x86142b5f	0x826ec294	0x956a3025	0x8b04e083
-	0xd69cd3bf	0x04f39016	0xf362b172	0x960466d0
-	0x230a3139	0x19378fba	0x335f3518	0x206a29a3
-	0x82465579	0xc1e4684b	0x9ac06746	0x1f0138e1
-	0x875a9aae	0x35ed8dfa	0x030c59c3	0xb3ed8018
-	0x2e91fa18	0x93739c48	0x172ed0d3	0x13722907
-	0x8e4e0426	0x47f72379	0x8bc54eb7	0x8657e9b7
-	0x0472cf9c	0x1424f3da	0xdf83007f	0x87aa810c
-	0x0e14e6e1	0x9d0dcfdf	0x9e7696b0	0xe019c6aa
-	0xa866fc9d	0xc19a1ff2	0xb187dffa	0x220adae1
-	0x16deb6d0	0x57bb035e	0x8084703f	0xabca8b49
-	0x577af6a8	0x520ff09f	0x3d87711f	0x1d2254a2
-	0xe161d5be	0x23287038	0x11722e48	0xdc7c6153
-	0x7e953ad9	0x1797ca90	0xd56bdecd	0xf7973432
-	0x5804968f	0xb688ad25	0xfda5e113	0x584d2c84
-	0xc5c02d74	0x7b6235b9	0x6c1712cf	0xb8ef7795
-	0x26d414d0	0x4b705388	0xa5725233	0x4e29eb6a
-	0x4e2f32b6	0x4996ed96	0x45b98f88	0x67ed828c
-	0x34e7af7b	0x5640103f	0x6aacf602	0x354d85f7
-	0xf6e8983e	0x1468e2dd	0xacae2dcb	0xd3bcf29a
-	0xa176799f	0x57a1bd66	0x7971495d	0x44dfac4c
-	0x32c643f6	0x57cc7b19	0xfee17e6e	0x1505f974
-	0xbaef1420	0x3b930cd2	0x65fd2cad	0x92ce1aa5
-	0x734f0807	0x65a5a815	0xa7124d4c	0x1ad9684b
-	0x32eb33c0	0x761f49ca	0x10b49a88	0xf0af198e
-	0xd7173b32	0x640b00ce	0xd3ffd60b	0x3a92cb20
-	0x71eccf6b	0x7c1c49e4	0xc7401cfc	0xf3f52441
-	0x736776c9	0xe8609667	0x8cbb06c9	0xc821f68e
-	0x827c67ac	0x0a98a704	0xd71e62bc	0x349fe1e0
-	0xac56ba89	0xd36baf48	0x54af6806	0xaeb2f143
-	0x0247d79b	0xfd27b357	0xec131b3d	0xd9fecc41
-	0xfdcb3993	0xec61c159	0x911a6bb6	0x849e85d1
-	0x5e4794d1	0x3c771cb5	0xdbc45603	0x76ef6090
-	0x4bfa505e	0x592b3fd9	0x05509bbf	0x2766b252
-	0xd9b66afd	0xe80fb26a	0x1ea90db3	0x61b1e2e9
-	0x5899953a	0x08c3bdea	0xe6393951	0xd2db7170
-	0xaa7031f2	0x5afce44e	0xed13e406	0x2af7388f
-	0xc6254e8c	0x3a846e5a	0x49de8429	0x56792361
-	0xa9fa85eb	0x4d97a05d	0xbd804c72	0x9e3f10be
-	0x94c6cb39	0x38a2729c	0xf71833f6	0xb9b36d59
-	0x8d7a74cc	0x4d9d5b59	0xaa9a735a	0x4ebac1ef
-	0xf073c9ee	0x38d2ea0f	0x87247f61	0x2e110dfd
-	0xca47846c	0xbcfd03d4	0xea058e96	0x40cb9628
-	0xaea31bc5	0xf39d05d9	0x246bec2d	0xb514efa1
-	0x5861299d	0x148ef9d0	0x1f5e33bc	0x444e79ef
-	0x52d62130	0xf391282b	0x93fcd860	0x6c3065e6
-	0x8a739db1	0x51f6cd7f	0x2da05ac4	0xe8f8b6e0
-	0x48adb62a	0x8c0c687a	0x2dc37ce7	0x993b198b
-	0x31008c46	0x3e509467	0x514a6614	0xca7c1511
-	0x5d3bca38	0x3a8188ee	0xedc7da67	0x3d243fe7
-	0x209f9238	0x03b4bc67	0xbefb5ed1	0x644e60ef
-	0x708021de	0xe7a8f948	0x8ec69a79	0xdde65d7f
-	0x2304f3f8	0x616643fb	0x7343b800	0x102f165a
-	0x848f5616	0xa85d42ef	0xc725fcf8	0x63207a50
-	0xa10f827c	0xd23d11c4	0x9832e62f	0xe7e99da8
-	0x492e1355	0x63882a0d	0xbeb2e2e6	0x02fdc22d
-	0x1a696e02	0x9821f6db	0xadf34cb4	0x2b274251
-	0xc40e4a88	0x7b22d05a	0x42574be2	0x004de66d
-	0xccd4a41c	0xd19863df	0x2f1965ae	0x868d7221
-	0x07cf8546	0x3fba2d34	0xb39e65cd	0x425bf20e
-	0xa61be150	0x191d3530	0x4f975298	0x37e1f881
-	0xd45df57f	0xbaba406d	0x06385459	0x4b105297
-	0x1669f5df	0x0ff8db41	0x258d3667	0x8592fb19
-	0x20f3da88	0x8bc12e8c	0x4247ed36	0x9d6ad7ec
-	0x26128a8b	0xbfd08579	0x084e2fcb	0x9279b5dc
-	0x3a33654d	0x1e40c91c	0x8f0a953d	0xdfd96c06
-	0x8703d737	0xca1f3200	0x60ec2e4a	0xa8814a20
-	0x6d9950a8	0x4b2438ea	0xc6ca6580	0x99f2f4ad
-	0x42dc5043	0x1bec10b7	0xce44a349	0xa6b35911
-	0x3583a4ec	0x65bcf9c1	0xd25c3af5	0xcb72222f
-	0x97cb8371	0x85f75c9b	0x03b1d637	0x6f80294c
-	0x3bdb3942	0x91126cd9	0xd3fbb35c	0x752a7251
-	0x5ed886d2	0x19c91d06	0x7a883d41	0x550a9331
-	0x371f617e	0x61543776	0xaf4b02a2	0xa390ca74
-	0x99d106c5	0x3f8c2d8d	0x01ca467e	0x20e50f07
-	0xa40edcb3	0xdd2b0317	0xf96342e4	0x94a6e3ae
-	0x17431448	0x789ea7b0	0x7bb4fbf6	0x03839d5f
-	0x13f86c23	0xc6efbe86	0x9f891cd2	0x3e3af545
-	0x0b1d0457	0x481e80cf	0x406bd13a	0xb277b63b
-	0xfb5d99bd	0x6fea0963	0x5b48c16e	0x0ac10b3d
-	0xcfd388d4	0xe07a502b	0x4466cac6	0xaa21c31d
-	0x806ba060	0xf175bac7	0xfee9f170	0x38d1af9e
-	0xae1f0f7a	0x6252edb4	0xb23c56c1	0xede12e73
-	0x5747e22d	0xc3b58928	0xaf586774	0x9b6e8b87
-	0xeaf2016e	0xd1fa9a90	0x986a5882	0xdfe68064
-	0x5657ea69	0x237bbb3e	0x01e22722	0xb7bd28e1
-	0xb75d98c8	0x31ecee6a	0x861d60e1	0xebe8bebb
-	0xdc35606a	0x447f0a45	0x9f50d631	0xcaab3492
-	0x76035cd3	0x9d84a371	0x51b55a55	0x263fabd4
-	0x62ff9ab5	0x8b1ee33a	0xdc85e9eb	0x0471df10
-	0x29cabc6f	0x47467a07	0x6ee73133	0x536f5c8f
-	0x15f2a4bd	0x2ad7e8af	0x631a9bb4	0x9ce75522
-	0x228d008e	0x86fc05c2	0x5526b054	0x8db9d95c
-	0xdea2c7d4	0x1336add2	0x901543ce	0x2a855d2a
-	0x4c7e054d	0x967eab4f	0xca5c932d	0xec109941
-	0xf1752baa	0xd4b3a39d	0xd999886a	0x1a6cd856
-	0xb11f6348	0x60a21b64	0xea4467ca	0x51db6925
-	0xf8ee33a9	0xc674ce6c	0x5fa834a4	0x17f2b8ad
-	0x2eab9ce0	0x0ad42708	0xd8a6740d	0x164c4fe6
-	0x1f9d12c5	0x3efb12ee	0xedf0e724	0x7e8880ba
-	0xe9c55084	0xd9d6e9f0	0x8f4ec3ae	0x2d6aaa11
-	0x480e0081	0x28b6c152	0xee01619c	0x79ddd62c
-	0x4b17ea62	0xeda6fb70	0xd3673924	0x02e84486
-	0x4c0d66ec	0x9ab8cd5c	0x340fa6eb	0xf8db9df6
-	0xc72b2937	0xc09cdf2c	0x7ba60229	0x5318612b
-	0x08a07717	0x81cfe5ca	0x32a3b0e9	0x03cc518e
-	0x1085bd98	0x16069e72	0x6aa01ff2	0x0b512345
-	0x5ce6b51a	0xb58b347d	0x0dad3da5	0x7bc5aae3
-	0x81a88658	0xd9857a74	0x4fb95187	0xe03045db
-	0xbe4ddc3a	0x68be74f7	0x9663e4ac	0x4d31a7d2
-	0x7a2a70fd	0x03dde6ec	0x827e2f9a	0x17cf679d
-	0xb34aefe8	0x085aaebe	0xcff354e3	0x18754a97
-	0x10c4a4f6	0xb21d4e04	0x8e93af63	0x226ea564
-	0x6c3608a8	0x9fa96865	0x24f420b6	0x7d4a31e3
-	0xb7852762	0xd1c752f5	0xbcfe1a9f	0xe3cd44ba
-	0x800d6669	0x08455dfc	0x2bbdab4b	0xcc8cb0a5
-	0x268cd5d3	0x2b0cbe1b	0x40cd57e0	0x939c0f22
-	0xb85a1372	0x6c06319b	0x2be94501	0x9e13089d
-	0x2df0027a	0x47bb8a84	0x660234b0	0x6a05c46c
-	0xde9eb668	0x2fbef0ec	0x8e7391db	0x875bd721
-	0xa1e55bf5	0x31dc45aa	0xeb0fa893	0x36f0fbf8
-	0x8edacf6d	0x61c11564	0x9fe655fc	0x34378418
-	0xe032bb0a	0x5e996c49	0xaa576bb3	0x88f1f99d
-	0x08562a6b	0xa4d7900e	0x3d124350	0xf10984ba
-	0x65af441f	0x8329eb45	0xfa1c3069	0xd9c18941
-	0x6bf28004	0x32d89f25	0x107ae0eb	0xf23bea70
-	0x709b7c6f	0x7f6bc1b7	0x6829a1cb	0x770fec21
-	0x6dc4d64e	0xa37d7219	0xe5551a04	0xcd470067
-	0x81d6207e	0x81bc2a06	0x5330dc76	0xbe8b6aa2
-	0x5080f90e	0x7f393edf	0x37194036	0x1b19bf9e
-	0x4ff560fc	0xeb207634	0x2fa526e9	0x9c48acd4
-	0x9b9be6b0	0xfa749280	0x715fb587	0x50287f59
-	0x04bd42c6	0xf8674fd2	0x614fde7e	0xf0482894
-	0xa402a285	0x54813092	0xf50e474a	0xfa420315
-	0xfe7f82a9	0x835dbfdd	0x08540acd	0xabba517d
-	0x197c438e	0x3f69c2c6	0xdf1b60b0	0xbcc4b1c5
-	0xbb967e53	0x8a2e2be3	0xb78406f4	0x6cca685b
-	0x2877516c	0x3159fdb2	0x3f48f0a2	0x88c2ed5a
-	0xe8731530	0x227413ef	0x50b5610e	0xd0e7d76d
-	0x68b8a8e9	0x2f251606	0x0ba3ca68	0x3f470646
-	0xa473b7e8	0xa36ec586	0x0f41792e	0x4ef380fe
-	0x938d7626	0xbdf5914a	0xde6b5c26	0x26306e15
-	0xfbb123bc	0x9cd3a83f	0x5d621b36	0x9c391ee7
-	0x0921d18e	0x261a36c2	0x28cf5843	0x1b65db1b
-	0x28cf152a	0xd1308452	0x6aa9803c	0x8f11c7bf
-	0x42797ebc	0xd02410f3	0x56b4c779	0x22e788d9
-	0xc3fee627	0xa1673ded	0xa389d31d	0x47563835
-	0x4e963ba3	0x2acbc139	0x70da7525	0x39b3ada3
-	0xdf20f92b	0x1ff80e87	0xf847db4c	0xefae0a2b
-	0x42139d4f	0xd311a9d8	0xc54ccfcb	0x3b7c939c
-	0xb2eefc73	0x4908680b	0x30f160ab	0xa15abe60
-	0x31cdcc4b	0x2b5d457e	0xa264ccd5	0x73dfc993
-	0xa75c34aa	0x1b302cce	0xd5c93553	0x6982ca4f
-	0xf83cfac6	0xb1235d67	0x25780fb9	0x78af4f8c
-	0x76b1412e	0x139afea7	0x291cebe3	0xbd275519
-	0x18c300d8	0x33502f82	0x86f1d060	0xc83323f7
-	0xc8d57b77	0x928a2c82	0x9ba9d389	0x4942f49c
-	0x04c5abcd	0xc5fa8ab3	0x3e4936d5	0x6c5a6c16
-	0x69f97f82	0x277e2c29	0x4f5a84b1	0xcc546d60
-	0x887d8de1	0xbe980c48	0x6fb583bb	0x8f0dda22
-	0x64ed4be5	0xd3be3a6d	0x615532b2	0x260b87f7
-	0xb54915d9	0x9222464c	0xd447b5fb	0x08ef3c9d
-	0x1e68ebaa	0x16d60b49	0x67b5c5af	0xef5d90fa
-	0xf2fd3185	0xdb03838d	0x17ffffae	0x43304284
-	0xabdcf858	0xfa019d66	0x80a891f8	0x4b2898ac
-	0x676c113d	0x711d2b3c	0x59323717	0x912dbb50
-	0x55afd393	0xde134c0e	0xaaf1d1b7	0x97975a07
-	0xb66e6cab	0xfb0f54c1	0x6dae6384	0x04405a5b
-	0x95df053f	0x125f371c	0x6656c332	0x5801265f
-	0xcf365f00	0x31c300a5	0x2a7617ca	0x65ce79bb
-	0x4cc96bed	0x1af82f49	0xfefea103	0x49054f1e
-	0xb9341875	0xb37952dc	0x1db40d2e	0xe23154e5
-	0x5a4e8bcd	0xed67b774	0x6639eb56	0xa4b3a6f9
-	0xc0918496	0x295261ff	0x08b0f294	0x54573333
-	0xff925b65	0x7872e916	0xbd5552d8	0x5d72050d
-	0x1cf126d7	0x9dfc6d65	0x3b107698	0x0b9f2951
-	0xeba14913	0x5c065af1	0xb5dd50ea	0xbe47408c
-	0x3c9da76d	0xbafbaad6	0xef2b0118	0xa97bf92a
-	0xf2d0b2d6	0x39c8bf7d	0x3017810f	0x35583abd
-	0x2f430d70	0x7d08a9a6	0x4304c566	0x295fbed9
-	0x07412bc8	0x833dd8bc	0xf086a3c8	0xf0836418
-	0x85985a3a	0xd620dec9	0x3c81fc7a	0x08fbadb5
-	0x55d56912	0x6e63f48a	0x3e178cb9	0xaf43c5d2
-	0xce83c97e	0x0b59010c	0x7806f1e8	0x5ceda01b
-	0x0cbfd565	0x1234bea9	0xadf6ad5b	0x68c5c83f
-	0x7b5ceb7d	0x55bcd3f5	0x1e1fe06e	0xe6c9bce5
-	0x95b5563d	0x0318973d	0xc2c4b750	0x8297ff40
-	0x1223837b	0x8264fea3	0x1e9a70df	0x69ed57ff
-	0x9598bb0d	0x1647c7a6	0xc2f1e9ea	0xc47f77d7
-	0x5e088380	0x31b7cf46	0x7aca1985	0xea1bcad7
-	0x058afbcb	0x05929ff9	0x2d5c85fa	0x19b2eded
-	0xfb6bd501	0xa0ea0987	0x4b8dae5a	0xc9bc0d84
-	0x2d1841ff	0x58b4bbb3	0x5f3494c1	0xce489fcf
-	0xf048eee3	0x8a146cfb	0xcb5d2fce	0xf24dc8ab
-	0xac9a22f4	0x1c0e8be0	0x8f1982e2	0x979abeb6
-	0x2e61de90	0x7096ecd1	0xe6326066	0xf6b2c331
-	0xc8035863	0x23ac48f7	0xcc6a8a96	0x6d2a847c
-	0xe3cd2dfc	0xcb224f09	0x5274254d	0x1052513b
-	0xdd244a04	0x2b583887	0x24b623f9	0x1cde29e4
-	0xf86fdcab	0xf3fbee4a	0x34804cb5	0xe4d2d1be
-	0xe3ee0459	0xba8e1428	0xd0d61467	0x493d74a8
-	0xda33b30c	0xef080476	0x6c4f86a2	0x3917c5f6
-	0x14052bd1	0xc5d10f70	0x3eb72eb5	0x2939b07d
-	0xcf722a48	0x330615a8	0x797bfb7e	0x9c604abd
-	0x612ca005	0x716bdbee	0x8098f5f9	0x4a591363
-	0xbd89a21f	0x5e3787ea	0x2acbffa1	0xff907f14
-	0x42ca9221	0x4d15a235	0x76d4e9bc	0x2080e33b
-	0x6437bd3d	0x3d5b4267	0x9ac9655b	0x857b5a56
-	0x8db93b3d	0xe1c45c90	0x0872b3e1	0x4935532b
-	0x314c8628	0xa43c7d03	0xba6468b3	0x93056b1d
-	0x60e61ab4	0xb6995957	0xcd37b047	0xc50cd92b
-	0x259a8690	0xc78684a3	0x96384186	0xd9bcb24d
-	0x31b39f0a	0x0fbbae5f	0x869a70da	0x80f0714f
-	0x50070cea	0x2643b25c	0x164c01e3	0xc77d8624
-	0x48f047b4	0x0cbd2c71	0x4c0b13b2	0x667fc4a4
-	0x848c28cf	0x05443953	0xfdbd5329	0x3aeae7b7
-	0xeaa0de2d	0x498be6e8	0x9663391f	0x8d55c785
-	0x20c68ab6	0xfc7591cc	0x5f757324	0xa30d684f
-	0x6ccb9c33	0xe90c74ae	0x488bc0dd	0x08231a14
-	0xe253a7fd	0x9196b1cc	0x25a54296	0x0f70ba47
-	0x9ee0a233	0x43c2e7bf	0x2d927857	0x1fde792e
-	0xc0598134	0x7aac6123	0x39da69f7	0x99233284
-	0x5894e482	0x396fb16c	0xcc554518	0x61784cde
-	0xf12b0d7d	0xf1e7ee64	0x53a93eaf	0x142d292c
-	0x52c36ba0	0xd9037d20	0x9eba60f0	0x4a041620
-	0x5462a0d2	0x9ae6663b	0x0a5dfe17	0x9307f8f7
-	0xc3532fd2	0xd20b3393	0x82d40f2d	0x3b139fca
-	0x6ec0948f	0x1434629e	0xa529a79f	0x3a607eee
-	0x07ee780e	0xa407a5ac	0xbad8d686	0x888401a7
-	0xf221e944	0xe8ba61c6	0xc3caabc4	0xd610be89
-	0x0e5432fe	0xb38b44a2	0x65a48b8d	0xcc044491
-	0x253a116a	0x96c20a3a	0x13bf416e	0xbd80a231
-	0xc94420a6	0x8ffee6ea	0x35bd2c90	0x39bbc314
-	0x762981a5	0x7217db3b	0x8ace0761	0x31e2506a
-	0xf1d679eb	0xab0b8a9b	0xaaff2f04	0xf40502fd
-	0xe56aa165	0x418522a3	0x2fb1212e	0xc25102c4
-	0xae39da06	0xe708d400	0xfedfc55d	0xcf13fc39
-	0x77cc3ff3	0xb70b7ee5	0x57e2732e	0x54eafd32
-	0xee513833	0x2f2f685e	0x17c8b664	0x4b22ab02
-	0x684951ca	0x67844071	0x27c3c09e	0x36f129d3
-	0xf5d71bbc	0x251d6129	0x6cd71b6a	0x975e1d42
-	0x89142f16	0x6c250a42	0x9058209b	0x7f713bc6
-	0x7bfa7c2c	0xe6a5a5cc	0x90a74d5f	0x79902546
-	0xd43e0042	0xc3b12519	0x2afa12af	0xf11aadc6
-	0x5ee59722	0x802b403c	0xa282210c	0x7658c843
-	0x88a81f68	0x25b8fcd9	0x967d3058	0x1ecbeac8
-	0x9b1f0dc3	0x16dd19ac	0x3c279aa7	0xed5c8077
-	0x2c03b915	0x3b0cd605	0x3677eef0	0xddddb73e
-	0x407a5512	0xb8cbb129	0x7d6f0f97	0x96e41ef0
-	0x7d1bbca8	0x7fa26a3b	0x025ed42a	0xceea965b
-	0x4a10020b	0xc3c47832	0x171644f2	0x75baa013
-	0x436abd20	0xc7000fa8	0x03123e13	0x3b80f711
-	0xee4401b5	0x34bb57b4	0xb7fd072c	0xfb5cb343
-	0xf6ed3bc1	0xd83b2953	0x9285bbb6	0xb9e9afb3
-	0x23ef8322	0x46111ee3	0x1b5ee880	0x994b4698
-	0x11348ba1	0x358ca0d0	0xf9e1e517	0x58150115
-	0x31b69c9c	0xb59d1a14	0x736d1af4	0xa2b6fb4f
-	0x6df398ad	0x5f5ee1c6	0x499e00ab	0x65024633
-	0x32af0af6	0x61aecdc3	0x19dc2376	0x061c1132
-	0x09eb3e31	0x53edd271	0x280ad517	0x167d6297
-	0x11da637a	0xfee5d512	0x86ba451b	0x9ac4dd03
-	0xae09fe4a	0x011fb154	0x5dde9f8d	0x66b77ebc
-	0x348f5dc4	0x89d838c5	0xd1076c44	0xb7207c6b
-	0x288ef144	0x4ddbbc30	0x8ab3181a	0xb3a9cd9c
-	0xe8da4c2f	0x5f51ea25	0x25698b3c	0xe5d8be42
-	0x9033461a	0x08ab6b56	0xd3ef4e5e	0x22fef14c
-	0x40e6cbd2	0x8023d0d9	0xd3624fa1	0x05058ed6
-	0x7f9e29d4	0x2d679020	0xbd8a9438	0xfc2c7ae1
-	0x43ff62ce	0xa5c960de	0xca118741	0x1d3ff652
-	0x7aad82fa	0x7e05c2b1	0xaa60d6b5	0x1b44c011
-	0x3d8ed489	0x33e5569f	0x954c9df9	0x6a3f3eec
-	0x185e0868	0x0b261932	0x4abcec9d	0xe91a01b5
-	0x2dcb391b	0x2623c791	0x4054eeb7	0x39f859cf
-	0x838a2034	0x89b408d4	0x58976dd9	0x130dc93c
-	0xd7c36f4c	0x65a57934	0x87364549	0x5e9e1b78
-	0x598c3e00	0x1267d53c	0x12655bdc	0x757ba8ec
-	0x20897226	0x121f8469	0x4db11ce8	0x6c4457ce
-	0x408c5799	0x0dafde84	0x34e803f9	0xe6c40be2
-	0x76601d29	0x6f382889	0x60a7602d	0x0e9f8f86
-	0xd02bde01	0x6bbe40f2	0xcfc7e18d	0x18bb288d
-	0x7693588d	0x93b5bf2c	0x257a886d	0xa444942b
-	0xddc30b6d	0x0c733fc6	0x59c7fb0c	0x1e7428e1
-	0x00e95317	0x8bb2b789	0xd1e8d918	0xe79d96be
-	0xcdaecf72	0x1f10292f	0x8550150c	0x3ac030fb
-	0xa740ed6f	0x86ca944b	0x1cb36602	0xb7a210bd
-	0xe3943a61	0x3a6eee17	0x26e3c293	0x48587d54
-	0x2e3c250a	0x9f5139ca	0x4ba8e861	0x310f187d
-	0xf30ef633	0x96708592	0x2c8219ed	0xba807709
-	0xb84d2c21	0x683d5e31	0x7c73d54f	0x20a9f6bb
-	0x8c571bfc	0x18f513b3	0x983064fd	0xfbc61cd8
-	0x34d473d7	0xe0c16341	0x3a51b21a	0x3f7ffd24
-	0x33d20d89	0x92ed2b84	0x711d3f75	0x4437d1d2
-	0x19ffb997	0x03fc59d2	0xd73c4ce0	0x1c048be1
-	0x3e1c70e6	0x2132c8dd	0x96883172	0x9e7ceb89
-	0x03c9bd60	0x6a288f88	0x9b69b2e3	0x21de2320
-	0x7ec42f80	0xfa9c1431	0x421447e9	0x82b422b8
-	0x691d53b6	0xe5adfacd	0x58d1fd02	0x5e66ac2d
-	0x1020615a	0xf1a5aa71	0x9ae9f314	0x61a8780f
-	0xfd35d0c2	0x6d0acb7f	0x8665a3cc	0x638dfdae
-	0xf77cd507	0x9e896caa	0xf023fe26	0x138ad408
-	0xd4a3d2a9	0x20392108	0x4e259b7a	0x294084a2
-	0x353ddca7	0x6b4e0d0b	0x2ecb3b7f	0x2e72b5f6
-	0xbd09b0dd	0x4de2ddab	0x27bbaf57	0x93c0044b
-	0x0c9ff149	0x5e06496d	0xae665015	0x422e1608
-	0xfb06c77c	0x7f49815c	0x74b36569	0x97c6b34d
-	0xb2171d9d	0xd85c83a7	0xd95e5cd4	0x474b6faf
-	0x4276a8cc	0x3eebf9da	0x373c9404	0x0fe5b125
-	0x2140e5d1	0x99fd5df9	0x1b624b9a	0xd277f04d
-	0x57d365a0	0x49fef587	0x1e8c3af0	0x4d827485
-	0x075a70d4	0x75569578	0x9d03ee73	0x2956bfcf
-	0xc45c3dff	0xe15ef324	0x4389e20b	0xb2b6a465
-	0x863fbaf3	0x7503fb46	0x41d8f4c8	0x871f04e5
-	0xb677456b	0xc806932d	0x99d586ce	0x94ad33e6
-	0x996a43b8	0x4c7ff253	0x441e68ea	0x3f2454f6
-	0x7b33925a	0xed5a56d7	0xfa40f2f5	0x3e7a60f0
-	0x45bae53b	0xc3237b7d	0x3d6fe60a	0x7ef17115
-	0x6df8dbb2	0x26d1240a	0x7372d23d	0x5767532e
-	0xa72e2c58	0x2a0d2f14	0x74d029c2	0x1bcf8b01
-	0x513dd7e4	0x800a6440	0xe0f3a8be	0xf951cd2a
-	0x5795eb8e	0x3384450b	0x46e7970e	0xb4434ac3
-	0x468194b1	0xc562555b	0x76d9cb19	0xdf109cad
-	0x57f1ac2f	0x1207af15	0x19d7cfda	0xfb4c069b
-	0x306802c4	0xe8aedc76	0x0170ab97	0xd19b99d6
-	0x7fe69394	0x60b6dd20	0x184caddf	0xd4c81b0d
-	0x008ebffd	0xfd615c94	0x813a5a30	0xb3386934
-	0x5c54130d	0xbe0a6b6f	0x91b127cb	0x7207bbff
-	0x176cac26	0x450be167	0x53563516	0xd6f5ed1b
-	0x90ce178b	0x80e28eba	0x4ddf538c	0xb8037a72
-	0xceaaa6ff	0x3e0eabdc	0x2af375b6	0xfafdf3bf
-	0x24bb3630	0xbcd6da54	0xc59375ce	0x4e9d08c9
-	0x7953057e	0x81ef3d8b	0xcb641721	0x8fb73300
-	0x07f1dd2f	0xda12a374	0xae008fff	0xd106aaac
-	0x5a4f59a3	0xe01bd4ef	0xe1ff2c4e	0xd58c4500
-	0x283e8041	0xb2c7ec64	0x81077f24	0x304fd646
-	0xb5554330	0x098fe673	0x9e5976ba	0x2e24c1c4
-	0x3dfad07f	0x3d64fa0b	0x78a9c65f	0x282c343f
-	0x755810ff	0x363e7150	0x692be96c	0x62cc0559
-	0xb7b9e8c1	0xe35abebf	0xf28d706e	0xea9b31da
-	0xd4762701	0xce0654fd	0xc10a087e	0x0ee813cc
-	0xc66364cf	0x56a8143a	0xb8eafc6c	0x085125a4
-	0x758752b3	0xfd8df76e	0x483c550a	0xc155fb38
-	0x20188374	0x118c9519	0x2e1dad79	0x45b648e2
-	0x32eea6a4	0x73373bbd	0xce78e1b1	0x49b6150b
-	0x826f31d7	0xf5b27772	0x76467cdb	0xab248975
-	0xc98c52c2	0x331e7992	0xb7ca3cb9	0x65fba8de
-	0x8d9df126	0xafb34641	0x83627ecf	0x4f6f5711
-	0x0a18b1bd	0xbf9f7e56	0x5b532a14	0x2c1c7f27
-	0xaaba76a3	0x0019b4c1	0xad0dec08	0x0a090710
-	0x9d092403	0x4b7f63f4	0xdda21492	0x5ac79d8a
-	0x53636303	0x8baacf07	0xd0e54e2a	0x06af65bc
-	0x1776250d	0xe3b7a745	0x3ed99c2e	0xcdfa72f1
-	0x28e2c19c	0x972ed696	0xc40238be	0x2eae4108
-	0x16dbeec2	0xe5aab504	0xb752b0ec	0x908c027a
-	0x5d6706f5	0x5dc64b1f	0xda6012bb	0xd823ba00
-	0x21227a10	0x99c8a5f7	0xe13e863c	0x7271ad65
-	0x37341fc0	0xed4f202f	0xe9394896	0x8c51a222
-	0xc730618d	0x61f38ac7	0x077bbea0	0xf7068ed0
-	0x9fe0eff4	0x09f20a63	0x692cb600	0x965b334c
-	0xe4d16d0a	0xabfd76d4	0xcebb865d	0x52ae79e3
-	0x54be2cc4	0xcada0fcf	0xdc531eda	0x0f6f5a07
-	0x45c26e9b	0x1b65c5da	0x747e35ce	0x28e8f353
-	0x8b14a4dc	0x70fec472	0x386766f5	0x452ec69d
-	0xea3d1060	0x4ad0a84b	0x74947e04	0x241d736e
-	0x67087154	0xa8429f6c	0x93f6fa81	0xc8ae48e8
-	0x8bc37b91	0x3c412b3c	0x5a9b6ea0	0x77b1267c
-	0x4e654c9e	0x3af8be15	0x0c1fcc1a	0xdd53e911
-	0x4133f74d	0x19b478ea	0x935059e6	0x602d1c43
-	0xef2f0dc5	0x606c328e	0x3bcb34f9	0xd3e43917
-	0xa4b13432	0xe32ca0b7	0xe72cf4f7	0x89e64046
-	0xf7665787	0x0e2ceb68	0xad0326bf	0x0df255df
-	0xfbe35bd7	0x452ad738	0x151ded08	0x4977f8b4
-	0xfb0d8ce6	0x55ba4d5e	0xacc482b6	0x685f74cc
-	0x483dcc86	0x09346c6c	0x1bfb0413	0xc8454c50
-	0xed0ab7fb	0xbd60dc85	0x2d4ce7f7	0x7e374d17
-	0x97c4de4b	0x8e241f8e	0x0c63ba83	0xfe2b6605
-	0x0d16e6b6	0xd2b65dc7	0x574904d1	0x57013653
-	0x02bbbb72	0xa1a951e7	0x2e06e4c8	0xaf8a0ce2
-	0xe45132d5	0xc335004b	0x7a80a191	0x70abfb32
-	0x0e6dae78	0x47ae882d	0x2ffb0f2c	0xfbfb1549
-	0x3f5d2a7b	0x9df9be34	0xb69b7919	0x051a54d4
-	0x3e7822d9	0x83f3988b	0xf4f6a380	0x382ec90d
-	0x19ec37e6	0x41da0b90	0x63edbfe6	0xb53fca2b
-	0x4117bab8	0xe711495d	0x93b066cf	0xfa436ab7
-	0xafeb2443	0x842a6a7e	0x92dbfd01	0x5536c8ab
-	0x87706182	0x95b19ae4	0x20a5243b	0xd17d6e3a
-	0xacc705bc	0x02124f77	0xcdd25a60	0x27f2cfd0
-	0xab63270b	0x5d0d50c7	0x626b463b	0x8d1c6c67
-	0xcd8faed9	0xdec15e02	0xeead3ca7	0x35e6b1b6
-	0xa3404975	0xa40c4d99	0xba2aafa7	0x9fd543c8
-	0x737fca65	0xf825b862	0xed028145	0xa19ab5c0
-	0x7a5cf4c9	0x29275a49	0x4e70bfae	0xa68d7af7
-	0x4027d4ad	0xc0f1f772	0xb1857bf2	0xeff36b41
-	0x1cefd1be	0x609569f1	0x5e4a45ba	0x3982f52e
-	0x2662da23	0x9995e160	0xa5236c1a	0xfc3dbe22
-	0xe2cf629e	0x1927e9bb	0x890c2c5d	0x9b1a74a5
-	0xd98da36d	0xd6394f24	0xea08f3ef	0xd7543732
-	0x2c08cff2	0xb338420e	0x954ebee4	0x8f62faf8
-	0x30001084	0x6209f495	0x4bf3151d	0x549fe524
-	0xf0a233cc	0x3d9520f6	0xc3bb7564	0x724bf6b8
-	0xf0364758	0x8c780cc2	0x85041d68	0x004c18d6
-	0x7e1b0aed	0xe515764b	0x3f646ea8	0xfa14a4d7
-	0x1d197044	0xf3eddc81	0x8aa91a1e	0x16256c4f
-	0x8199c0df	0xbf9a50ac	0x568a0f09	0x2cb00264
-	0xd72fd139	0x2705356f	0xcbca00f3	0xd1d48350
-	0xd9ea820e	0x8cef5c8f	0x208f4413	0xa8cc4af4
-	0xd3925d45	0xcacb25be	0xf5c478f0	0x2d98856a
-	0x9b2ca15c	0xa866f9c0	0xd11e9a8c	0xecf63535
-	0x26afb8e5	0x07582187	0x68e92d2c	0x701732d1
-	0xcfa17e9d	0xcb923dcc	0xc6fd0935	0x2949f3f7
-	0x2f819c1e	0xea483296	0xb234a335	0xe3e174f1
-	0x2e79e24c	0xcebb3426	0xc7b11c2e	0x09c50c12
-	0x1a776bec	0x9eb75be2	0x906fc75b	0xa951a0bc
-	0x067984cb	0xeef41487	0x592d71bb	0x6d830d75
-	0x9315da53	0xfc4a745d	0xf55687dc	0x41d554e7
-	0xd9f4873c	0x51680147	0x70a32832	0x514a6b9b
-	0xdb221d0c	0x5d8a04f2	0x56d0d2e7	0xea241411
-	0x2fddf98e	0x4f114da4	0x5b08dece	0x4a1deb72
-	0x8a05c6d7	0x5412556f	0xb34099d8	0x769a94dd
-	0xa5e5f79d	0x2aeed8ec	0xb2c36124	0x4049a237
-	0x14984601	0x1a595742	0x64490292	0x630c8cd2
-	0x55e6bb46	0x6a0d06ab	0x2b0b11b4	0x7c616e40
-	0x88ad3ace	0xd51e4e32	0x09b91afd	0xe7e15aeb
-	0x0050ef89	0x4330509d	0x12cb2d58	0x8aa65df5
-	0x6a3a7bfe	0x13110a63	0x6e0321e3	0xe00dafca
-	0x71e02a28	0xbb179946	0xa46ec287	0xec8a407f
-	0x71e4ecb1	0x9aa3eaf1	0xccc68628	0xc593d002
-	0xadc7003a	0x4266b50b	0x3c1883ee	0x6dccb885
-	0x417c946d	0xbed06b8c	0x333c5aae	0xb05e54ee
-	0x16d7a8d5	0x2c4711e4	0x77f99748	0xea4f1ce3
-	0x99077ba5	0x3efe0258	0xd6df1959	0xa68402c4
-	0x17fb46f9	0x84dd7f43	0x2743ad55	0x4c3618ab
-	0x066e70fb	0xa7ae2740	0xabfa9383	0x3550f323
-	0x12df0416	0xf1453568	0xa72e19a3	0x858f6f03
-	0xf17cc616	0x4ae587bd	0x18a72aff	0x3a7e96e0
-	0x742fcbfa	0xf2978c0c	0x1c9b4647	0xead5df7c
-	0xa4006862	0x4ff1f7ad	0xad9ef88a	0xf2e10660
-	0x408e1435	0x54fce4ac	0x3b362a56	0x31215f74
-	0xaa3c9bda	0x9e20dbdf	0x0d5fce6a	0x282c976f
-	0x0edc8226	0x373f111f	0x3e98c061	0xf268555d
-	0x2bc94957	0xaea989d8	0x509c71ba	0x12314a4c
-	0xf763fd18	0x756c083a	0x210052bf	0xc8a587ec
-	0xad316f0b	0x8bdc25ef	0x97d826c2	0x2b2274e0
-	0xb2d83dc0	0x758a648c	0x98f048ed	0xc049ee18
-	0x86a7ae90	0xb2cd2e74	0xbf05a5fa	0x99569e00
-	0x91ef2ef3	0x0fa73191	0x8fbe0377	0xd833195b
-	0xa8f92c91	0xd5180d87	0x78e66404	0xa6932c29
-	0x63767065	0x212597be	0x71443fa5	0xc7f0f7e7
-	0xee005d0f	0x3f554ee1	0x0ce921c3	0x11f7aa65
-	0xab833603	0x226583ac	0xdc02270f	0x582acced
-	0xe4873a4e	0x4789f1b5	0xe4556ae0	0x2db116e3
-	0x4dcf008e	0x94848eef	0x33dd4850	0x763ee311
-	0x8d129dec	0x37584ab5	0x2a72a7f1	0xc3812cba
-	0x8b28d2f2	0x0adb3ef1	0x77c139ed	0xa024d006
-	0x77b56ff4	0x237a0ef1	0x70c06866	0x3f678b49
-	0x758b3ce4	0xac6fba3c	0x425f5226	0x736cb61c
-	0x6d33908e	0x2db271b8	0x57a0b9e2	0xafa0c8eb
-	0xe16670ac	0x01358d54	0x291458e7	0x20dbb518
-	0x750ebeed	0x3b7ce363	0xab142fda	0x2f827c5c
-	0xe4b63c2f	0x25b21550	0xd9a7d8a4	0x9a0d0235
-	0x6ccbe996	0xbd16a832	0x408c6b6e	0x264e7057
-	0xf76251cc	0x10b292aa	0x44e35c08	0xe10072a1
-	0x8496f9f9	0xf3f14db0	0x903e0d04	0x437cbdab
-	0x94bba5f6	0xd93cb547	0x6c8c5b9c	0xdaef1d7c
-	0xc9245303	0xb8327055	0x17b4f91f	0x9609ed57
-	0x276a2fef	0xd6547d96	0xd845e2a3	0xdb17e11c
-	0xe06b1865	0x91ac2801	0x7499b2bf	0xfcc13e08
-	0x4d2c3ad7	0x33f551e1	0x7d9409c7	0xafc9eb56
-	0xd1b99328	0xfb86b03f	0x386621b1	0xc937917d
-	0xd049796a	0xb61b9848	0x6e6c850d	0x9acceebb
-	0x2335fff6	0xba4cc878	0x71410231	0xe2f8c5ab
-	0x9af0d19d	0x28ec5cf5	0x756ac8b7	0xbef10a49
-	0x0845244c	0x1d73e741	0x9062b8e2	0xda4ff7ed
-	0x02b84967	0x1dfa2bce	0xa39fde98	0xb9754114
-	0xf1d1128c	0xfe4a89f5	0x7f752ab4	0xc079051f
-	0x9d280392	0x8e4405b6	0x9a78116b	0x93ccc928
-	0x9423c484	0xd9d02b55	0x8b293206	0x4e1ba855
-	0x8b163dac	0x86097281	0x5fed4e15	0xa3a9986f
-	0x6aceb1fd	0x9840a4a6	0xb9159ba5	0x43a6a036
-	0x48c6b148	0x741b03e3	0x2034fa35	0xa2238e26
-	0xcbd2d186	0x543a2254	0x52bee0c4	0x3d86f09b
-	0x91b2c0f1	0xbcc3b745	0x2f74849a	0x0330c741
-	0xbe83b31b	0x2be0b1e3	0xb5289590	0xd70e1559
-	0x575ed5ef	0x26095dad	0x243db065	0x7deef6bb
-	0x65d12981	0xed493443	0x8bbb1d52	0xad9cceeb
-	0x9d2347e0	0x6cca137f	0x17470bbb	0x7e3c2e70
-	0xf8f031e4	0x089ffd36	0x54188a4b	0x0da3ca59
-	0x89502f42	0x118865a6	0x188d2f03	0xbab32122
-	0x8b7dce7e	0xd560dcf2	0x3b664c1f	0xc75878ec
-	0x24483e82	0x5f98c3ad	0x30f8edb6	0x750517a4
-	0x26b74663	0x4a92cf2c	0x34142eea	0x74434b26
-	0xef952153	0x499bb195	0x0eef898b	0xc87096df
-	0xebb06a79	0x6f85e09d	0x61582c0d	0xf067fa23
-	0xe800ddac	0x5d94560b	0x7b3c3438	0xf8656d92
-	0xbb2e740f	0x3919d1e9	0x4ae59719	0x9884c38e
-	0xab33c8f3	0x2b6fe11e	0xbb918fe1	0x78b89ddf
-	0x28ff265a	0x8d1be42f	0xc7ae521f	0x59021a63
-	0xc8feb2b0	0xf4adb84d	0x1627d0ad	0xdf2f54b9
-	0x6c34378c	0x19905a68	0x751ab74a	0x4ac834b3
-	0x0482a8a0	0x3fa5727e	0xc67e56e6	0xe9a7fa62
-	0x138c624b	0x8cfa9421	0x777be58a	0xa77e4a9c
-	0x317880c6	0x784adbec	0xf24af624	0xca7b14cf
-	0x0733ca3a	0x4df8fa2b	0xe737de97	0x8221ad28
-	0x12318567	0x1143d1b5	0x6d785e96	0x96b4706f
-	0x62b54a94	0x2cc3c8f4	0xf4509cba	0x013b1838
-	0xeb30c28f	0xafdce478	0xb079b9e2	0xf7fde255
-	0x369de668	0x51eaacb3	0x1a4857b1	0xdc155799
-	0x14312bb5	0x88e95615	0x3baea03c	0xda51f1b7
-	0x2ba9c897	0x02acb260	0x45d16629	0x69f4125c
-	0xb814d67f	0xd9371fdb	0x2abe9516	0xcb4347a5
-	0x8499fa6d	0x548d5caf	0xeaaea9a8	0xd2050d3e
-	0xe7ffd097	0x1343ddc5	0x2c063604	0xd4860459
-	0xe97d7e58	0x2b039549	0x7f9abb32	0xce9ae49e
-	0x6a9f2bc8	0xf42c6e74	0xa2cc44a3	0xa586ee59
-	0x9468aff1	0x9baa9f44	0xc672fa47	0x81af898d
-	0xbe2e0747	0x2568ec6c	0x5a297908	0xa3a45a84
-	0x86e7b0c8	0x25d653d0	0x2e1dd924	0xb8b8401d
-	0xb6132a11	0x63380a89	0x70457a9c	0x5599343c
-	0xdfe56efc	0x7347c609	0xd2a0254b	0xddb9eff8
-	0x2ff89812	0xc3fb0b4c	0xaabcb56d	0x8ea167d7
-	0x3058af81	0x90c13947	0xd2d066bc	0x9187a7c2
-	0xea3f4bc7	0xde558f0c	0x553387c2	0xfe52ae90
-	0x55e9dfc9	0x280c76a9	0x22029fbb	0x695decb6
-	0x37e156cb	0x636cd8d0	0x314735a1	0x6b97c31e
-	0x5990da35	0xa36210e3	0x731aa846	0x3e9f4591
-	0x1c311983	0x1b05ca14	0xd26366ce	0x35108fc6
-	0x6ec7c06a	0xe5479ece	0xabda431a	0xe876a3b9
-	0x7306ec54	0x8ac2dbd7	0xb6025692	0x60e08291
-	0xbd2d5771	0xae63c08b	0xb57f59d0	0xa0b7a4d2
-	0xa1975545	0xd4246fff	0xb541c3e7	0x80579f75
-	0x350f9ba5	0xc167fd9c	0xa4753b37	0x614432a2
-	0x8c2a5225	0xcacb408d	0xc692b149	0x44eb19e3
-	0x9e36674a	0x4221e3a5	0xc8847980	0x22188be7
-	0x9f3b54db	0xca30b3a9	0x4f23026c	0x1ac563dd
-	0x0cef9dbe	0xde1759e4	0x88a1ac44	0xdb249ed0
-	0xcccf2728	0xc54995cd	0x1410f555	0xe68a533c
-	0xbf63c4b7	0x53890c13	0x501696a3	0x09695674
-	0x49675e62	0xd5859fac	0x62dfaa74	0xc2837e8f
-	0x5693d6bd	0x6c4b7df7	0x19673414	0x436523f6
-	0xd7476fa4	0x1c123daa	0xf160418d	0xb022c7e0
-	0xa0798def	0x908aaeed	0xab420cd0	0xb42b83a2
-	0x779b9257	0x8bd0dafd	0x17088cc8	0xe5707f57
-	0x7e95cb37	0x2f0975fe	0xf6c69671	0x9adb2ac8
-	0x9744adf6	0x534f59b4	0x70126a4c	0x094dc52f
-	0xeb1bca01	0x8439872b	0xa9eb2393	0x93466ee6
-	0xfaefa751	0x407578bc	0xf96695f3	0xece8916c
-	0x90555ebe	0xd4bbb5e8	0x521e0328	0x733e7a44
-	0x6b38d125	0xaf78c4f6	0x02a68e77	0xf0b3de08
-	0x6b7055a7	0xe173c89d	0xf8d502e8	0x0af8722a
-	0x0cb5d7c7	0x67fd3443	0xc3ece1f6	0xd1e3476a
-	0x6c51b69e	0x1e4d6701	0xd30b9ed8	0xcae0b2cf
-	0x107a07cf	0x9e995fe8	0x96be9a9e	0x9679a48c
-	0x56e943fd	0x5840eba2	0x903172e8	0x030e7848
-	0x01aa0b3c	0x3430ee93	0xd9074e67	0xba76da7c
-	0xac651f8a	0x4776630f	0x335cc3e6	0xf196a501
-	0x3946d5ab	0x9521219b	0xd5c1b923	0xea8a860d
-	0xb68cd8e3	0x422fe195	0xee228116	0x7935c07c
-	0xf9a777a8	0x5ebb5f11	0xca9af85c	0x2ced106a
-	0x839746e2	0xb278a109	0xd80ac684	0xad50dc92
-	0xcb1306fc	0x03b5953b	0xa1739037	0xb3d2eca5
-	0xa2177c85	0x331d941e	0x07d760f1	0xaf91e655
-	0x37859c68	0xa93f3fe7	0xfd8c0c27	0xfbaa7226
-	0xf9ebb691	0x378f97ba	0xbff7118a	0xe2dcdddd
-	0xbbcb31c6	0x690c39d0	0xa87db784	0x71e8f7e3
-	0x6030ca21	0x4a0e52fd	0xfbfb507d	0x162bf88c
-	0xaa2641c4	0x8df9c9b8	0x23266298	0xc3c49ddd
-	0xd285aff8	0x3b867dd6	0x0be83ba1	0x0f4a797c
-	0x1c934d37	0x0e0fcb24	0xa0a4d4bb	0xa4c9e180
-	0x1f151322	0x44b9bce0	0x047feb93	0x3e05cf8a
-	0xa9b3e489	0x43f0da55	0x6fcddbe2	0xa402623a
-	0x5c8ad2f4	0xf7ea52fb	0x3da14b50	0xbf8849bd
-	0xb45ca440	0x2893d691	0xf6d8ee21	0x9dc0cf25
-	0xfa6be75a	0xeb27219e	0x9b160b84	0x1867d384
-	0x5b536f15	0xdac9e97e	0x1d290193	0x683d4a93
-	0x4c449e2d	0x493edc1b	0x8ae3a3aa	0x3a49ca51
-	0xd6751c65	0x174ef916	0x94118e1d	0x0bc6adeb
-	0x49c4b0cd	0x04668564	0xc9e39f39	0x19907555
-	0x0320cb0e	0x32a643db	0x4ba9edc5	0xce11afee
-	0xce71c45c	0xebe0c707	0x48d1d23f	0xb2704cfb
-	0x94b97cba	0xaa934cb4	0x7e375bf3	0x7c9f87b7
-	0xb34ebd26	0xb1ed5855	0xdd458d3f	0xcf071bd0
-	0x3204188c	0x744959b0	0x20eb0748	0x1b863237
-	0xc36fad4a	0xde026857	0x74c278b2	0x7be0749e
-	0xd61895dc	0x509355a2	0xab890c09	0x210ef412
-	0xae4678f3	0x3605af3b	0xc111b378	0x81f0173e
-	0x4ac61ae9	0x2efebbd3	0xec8a55b0	0x5c60addb
-	0x19ab7fa7	0xbf5bb0ab	0x7b55db2b	0xa246b5b0
-	0x70739cad	0x20bcca0c	0x152a98a3	0xb1ada872
-	0xf3a401eb	0xb169b481	0x1024e632	0xb285ec8a
-	0x42f7bc38	0xe6ce9265	0x05ce19a1	0xf89e52ec
-	0x2dd6f337	0x81b30e86	0x459ac80d	0xfa83fd49
-	0xc0ba36eb	0xaeaf8c90	0xab621eec	0xe94ee998
-	0x0f693a97	0x5d9a589e	0x439e79a6	0x565ea22d
-	0x60d8e090	0xa021284f	0x4dd58eab	0x35cbe80c
-	0x386c67b8	0xb260ff41	0x9b2685c2	0x37c33d86
-	0x2b922b27	0x1aeb19d2	0x9d503c43	0x0fff6ce2
-	0xf400393b	0x70be801b	0x8cfb132e	0xbb1781c6
-	0xbeaf80e2	0x2a5a64c7	0xc02c7ebb	0x8f870c7b
-	0x6bfecce5	0x8d885183	0x4f2c1b6a	0x0a3e6c0a
-	0xb7d17ad8	0x7d593bb0	0xb1e00ea2	0x8d553de0
-	0x07ecf8c5	0xde0c3afd	0x40f193a0	0x77030199
-	0x458046a0	0x21b67cd9	0x836ef83b	0x53563580
-	0x4edacbc3	0x1263d410	0x2b217042	0x4e3ad860
-	0xd51576cc	0x714ba8f7	0xe02e102c	0xb38770fc
-	0x34270f26	0xe7aa59c0	0x17a3461c	0xe6667980
-	0x9d5ed074	0x4168f2da	0xdefefcf8	0xc6b3031c
-	0x27c4d4f0	0x5e51e5be	0xf90cb81c	0x26ff3f7c
-	0xabc25d19	0xd65e5687	0xa5ee2995	0xc4e545b1
-	0x0184fab9	0xa44f4395	0x2aaef6da	0x33a682a0
-	0x5f878a4d	0x0b808a4e	0xb95490e1	0x4e4b3902
-	0xa1815407	0x3769d4f8	0x81943938	0x0d8b44d2
-	0x89c90314	0xb779e2b3	0x1acfa29a	0x3ee54de2
-	0x203c8450	0xfdbf24da	0x8b9bc91b	0x41a25706
-	0xab9b74a3	0x6feaa6a3	0xed50c416	0x5dca2489
-	0xf9d58d01	0x57682903	0xd951335c	0x55a323f2
-	0xe6c10c4b	0x0983a265	0x50df7efa	0xc550b079
-	0x1e670ce5	0xca74138e	0xa7e01118	0x4d1cd2e3
-	0xcd3b73d7	0xc5c0d501	0xdd56b269	0xbc6bf217
-	0xa3094ee9	0x794e6e21	0xc097fddf	0x191a1b70
-	0xe6a45c45	0x47a1899e	0x29fe5a55	0xaf88ab14
-	0x0a05bec0	0x05c97061	0x0b7654a3	0xfcb357b7
-	0x31657eec	0xb5aeed41	0xc70ea45e	0x096075af
-	0xf5236b88	0x6329310c	0xe1bdaf51	0x569053d0
-	0x7679fcd0	0x04c70d46	0xcce2d566	0x0316e8c7
-	0x391cdf9c	0x47045b03	0xac63bff0	0x1a7bdde9
-	0xa5a725bf	0x6dc151e9	0xf02a3df4	0xfb01c649
-	0xa6690e2f	0xd561a5df	0xbe0efc39	0xd35f7dd6
-	0xddbe2e12	0x8f403837	0x1c92e116	0x1b47ecde
-	0xabd75d5d	0x3b39c5a3	0xbc8a81e2	0x5beaaeef
-	0x1206f28d	0x7aa1852e	0x96eb9ef2	0x30911a7b
-	0xc1ed82f9	0x0940dcef	0x07c62124	0x1ec437a5
-	0x688e0a9e	0xc26852a2	0x01bb985a	0x55429a26
-	0xc90b329d	0xf618584f	0x1ed4fb9d	0xfe605231
-	0xc20810d3	0x7cf66bbc	0xadf11084	0x80697ce9
-	0x473457b6	0xd162e619	0x4e452b78	0xd39ddbdd
-	0x8591db3a	0xb225b8e7	0x208855e9	0xefa860f0
-	0xdd96e987	0x074a8ff1	0x1cf505b1	0x78d7b7d5
-	0x8cd1cc29	0xae25f5c3	0x4fdb0160	0xc4cef03e
-	0x9a9c5704	0x47032d85	0x3486b65f	0xd3ecb515
-	0x58bd87e4	0xa408f421	0xca577e46	0xa5e921df
-	0x5a295aa1	0xe53f571f	0xc03f9dd4	0xf1d6a0c4
-	0x711016e1	0x300d5999	0xc321eef2	0x96669e94
-	0x2925f8c6	0xf7096453	0x65d21402	0x6f7462ab
-	0x826ee986	0xfd04606c	0x5554d246	0xb3d98bcf
-	0x237e9d62	0x82224172	0x35ea607d	0x8142bbeb
-	0xcb0edddd	0xc0a9233b	0x64be095a	0xf8b39e85
-	0xde2d0b29	0x69e2d7a1	0x6737f156	0xf85e0d4f
-	0xc194effb	0xed018c03	0x873a1908	0xa4fa5da8
-	0xf6eb812f	0x04e4819c	0xd189a19b	0x94694499
-	0xd0545215	0x371f62e8	0x2208dede	0xcb49f3ad
-	0x192654ac	0xf36c1f49	0xeb3af0c4	0x54bfd20a
-	0xb86f85aa	0x3d94435d	0x31a9a1ed	0xd02b0620
-	0x0b44bc44	0xb4861a1f	0xb4605284	0x1c83e472
-	0x055d7e70	0x717bb954	0x44d8e8bd	0xbd9af75d
-	0x068d8de3	0xe25b73ad	0x8df23c60	0x4050ca9b
-	0x86c000d7	0x67a9e98d	0x437bb833	0xe26ca015
-	0xcc53371b	0xa0ce2a4c	0x83bfc220	0xc392520e
-	0x38d7f316	0x4801955c	0xcebd086e	0x6a3b8eeb
-	0x83d63b2a	0xcf516140	0x3f0d648a	0x58b62c57
-	0x7ef3bffa	0xa6976628	0x8f3a5c55	0x42a3baa3
-	0xedeb9c23	0xb477c88c	0x63d7c7bc	0x2bdd0e26
-	0xfe7b9821	0x31fe5981	0xdb5425a8	0xc716b3c4
-	0x0a6f1597	0x34a8a007	0x36b0614f	0x8362c856
-	0x5e0f52b9	0x9398b4d7	0xc5c5590f	0x4af55ddb
-	0x1ec59258	0xaf0222f6	0xcc2c7b6c	0xf0413081
-	0x1ac15bcd	0xf0bf09a8	0xbdd23bc0	0xd75ed77f
-	0x551c6a1e	0x5380ca48	0xf5f30a44	0x88ecff13
-	0xa5f8130c	0x7cb60dc0	0x9eb26ba1	0x3f883068
-	0xd954b9a3	0x95c87a30	0xefcc0c68	0xf7337080
-	0x1eb12337	0x125c5a7f	0x25a0fee6	0x439a4a47
-	0x02ac17fa	0x5d581e53	0xafb9d7be	0x914f9ebe
-	0x82f5c4e8	0x7d29838a	0xe8d6c3ac	0x1192f816
-	0xdbfa1251	0x239defaf	0x8d4a48d0	0xa48bf5a7
-	0xae7149d2	0x9c349068	0xe7e1f6c3	0x8c28773a
-	0xd441626e	0x81fbd796	0x3597d8c0	0xb8f39eef
-	0xbafa40c7	0xe4e53aa9	0xb678c826	0x1ac82ff4
-	0x9e7fa0bb	0xe8bb2559	0x064e4e96	0xb0e6f10f
-	0x9ae0ee3d	0x7d9b0b42	0xadd1c5df	0xf095f8a0
-	0x30f172ae	0x61caddf6	0x4ce89732	0x06099b54
-	0x011266e7	0xbec76cea	0xf7f8d2f2	0xdfbb7f1b
-	0xbb003bf7	0x425d3677	0xfdef38c8	0xadbe4b40
-	0x634753c2	0xe53ae88c	0x1714dc8c	0xb788dd35
-	0xcbaffa0e	0xffbda6ca	0xe1f91cc6	0xf92d121a
-	0x9a260275	0x45b2c1ca	0x707a08b6	0x2a8db106
-	0xa7df6894	0xe7189751	0x206259b0	0xde37dfea
-	0xe468cebe	0x2476d774	0x1687f09f	0x2c06af20
-	0x60fa742d	0x81aca355	0xef888aa1	0xc1847c88
-	0x32036160	0x29a779b5	0x47d9e830	0xb9f83d5f
-	0x3fa4e61b	0x038f4901	0xda804b60	0x231c9fff
-	0x8070517b	0x2a4e6c70	0x9485f89a	0x7b57f832
-	0x0d92d4cd	0x04aa0eba	0xdcf5c49a	0x3b3a772e
-	0xe9df2e03	0xde378b39	0x3bdfbf09	0xa60790df
-	0xdd8826c0	0x3de3b41d	0x68c3f5bc	0xd6f093d4
-	0x41bd42c0	0xc68291ba	0x12f94625	0xae5ca753
-	0x0abd919d	0xf48b4d3c	0x57c0c82a	0x5ba454cb
-	0xce5a94ff	0xae3cab47	0x4aa33823	0x1afaffe8
-	0x7d4136c6	0x2be28394	0xfb7602ee	0x39eb1300
-	0xd12bae68	0xe4b7a0c0	0x94f94c06	0x048abf82
-	0x4eb3e435	0x6fd07abf	0xd471636c	0x5c6c299f
-	0x702a9e43	0xf239358f	0x82dc3598	0xc76a572b
-	0x48b47811	0x1de592d8	0x258a64a6	0x9b61d81c
-	0xf44f9c0f	0x737b3537	0xc6e0eef8	0x169efe91
-	0x834cc9a3	0x67d42617	0xa3df949c	0x2e4601f3
-	0x21630729	0x7bb68a4c	0x7e489647	0xfa9179b3
-	0xf2588707	0x4fddeedb	0x7a1f612d	0xb55787d0
-	0xafee1501	0xb3e7b9c6	0xba804c9e	0xd4ae95e0
-	0xac524f6d	0x58cf914f	0xe057bd9d	0xf3ac907f
-	0xb03a6d32	0x2260788c	0x4caaa555	0x984ca3f0
-	0x2129f747	0xc8d68e34	0xa87c8179	0xa480412b
-	0x63e15d82	0x41cbe3df	0xdf1a76d2	0xc60c1cde
-	0x7648f22c	0xacd4fc11	0x06b9d04f	0x991c16ed
-	0xcb417c7f	0x479c604b	0x5582e2c5	0x40f9c0e7
-	0xc2d613be	0x136c76be	0x91e780bb	0x2063d01b
-	0xc4e5d68c	0x6862f436	0xa56544a2	0x5d022a83
-	0xf72335d0	0x85e89050	0x89306316	0x1f0514bb
-	0xa5080fbb	0x2a7369e4	0xeac3af3d	0xca7607a5
-	0x5c743d9a	0x7ffe728c	0x9e8fb02f	0xa0c5eab4
-	0x0fab7728	0x4cb95891	0x2e79d596	0x018ccc65
-	0x0b58f60f	0x2ca2b629	0x046ea589	0x3b30acb7
-	0x8ba03fbc	0xf22519b6	0x8cb72f21	0x202dee89
-	0xf9d00d21	0x2ec96d07	0x4b83c51b	0xa9fe32cc
-	0x1d8f9267	0x1a432a84	0x6d823868	0xc7911f1d
-	0xcb21bb51	0x3c2456f1	0x1a03390d	0x25052957
-	0x20616d36	0x4fb85138	0xcdd69e20	0x42b7854b
-	0x158e4668	0x6303770e	0x96e26c4d	0x71b527a5
-	0x11319d1d	0x6d75f287	0x1dba9eaf	0xccd4fce8
-	0xf5d9cfa1	0xe9fd8f1d	0xb6f43134	0x2d4cbbab
-	0x1304d4a3	0x7a05977a	0xe773bf6f	0x30baa540
-	0x61f204da	0xc5a5aaba	0xb9957e48	0x3262daf3
-	0x78511464	0x2ab04e32	0xc89d96b6	0x14246913
-	0x4b836fc9	0xf50f4f05	0xff2d221c	0xc14a1bbf
-	0xe05e4591	0xf4c57aa1	0x935d6b79	0x0878ec6d
-	0xdf4537d9	0x8a82fb47	0x6510da09	0x37a2a471
-	0x216f3f32	0x40bac353	0xbd273df0	0x92a53e79
-	0x54e1c315	0x494f9ef0	0xf206a246	0xb536ed59
-	0xbd90d8ac	0xe7cd65db	0x1528ae70	0xa999b3ea
-	0xfc3616b9	0xf26b0fb8	0x0d26f2e9	0xbf44ebf3
-	0x690d86fd	0xbfa22568	0x760c8270	0xb51e0a14
-	0x3f9d311e	0xac848312	0xfc101499	0x553fe2a4
-	0x6a6b0f3e	0x6f970879	0x2be81e35	0x6144ac40
-	0x501451ea	0x268aa441	0xc6cf124f	0x6bf90440
-	0x08fa587c	0xc04bf04e	0x25bfb03a	0x3741f6db
-	0x26242832	0x5bf071f0	0x8d6463b9	0x500e503c
-	0x1a9468ce	0x5d23d18f	0xf2f8163c	0x0d7e519f
-	0x98f0edd1	0xdd12a97d	0xba39e22d	0xc91cace2
-	0xb2204698	0x87eaa42d	0x7968cfdc	0xe32a8876
-	0x6799323a	0x5df22ef3	0xa674dfd7	0xb46117cb
-	0x8294a996	0xac7d3b17	0x30c06dd6	0x3b827594
-	0x1cd8770a	0x026d3220	0xb9efe807	0xb3d73bad
-	0x68c78f8f	0x8f8a13ea	0x1ffb9590	0xe99cef6f
-	0x03cd123d	0xfb1bb840	0xaff37d51	0x199b5161
-	0x842c3d56	0xf31e3aa0	0x218ed36e	0x16bbd3f8
-	0x733a6088	0xed5c4240	0x29ac4df9	0x65765620
-	0x1645afd8	0xb9af1aa2	0xdad3a6b0	0xa1007b56
-	0xe709a529	0x51a7d880	0xe58a2cd7	0x79c1915a
-	0xf63df885	0x83e87bf9	0x33e3818e	0x3e3c0136
-	0x59b684da	0xc03628d4	0xfc3e229f	0x67fdb30e
-	0xe965e7c5	0xcd262320	0x171c70a9	0x85d68571
-	0x1da4d76a	0x59e854d3	0x138428bd	0x0804e776
-	0x948e121e	0x410cd3d9	0xdc4834a3	0xecaa7f10
-	0x6d2993a3	0xfe17843d	0x518ec623	0x70c3f7f1
-	0x418d09b8	0x04272bf6	0xbb6f5ac6	0x86993bb5
-	0xae28afb6	0x1afa1ba2	0xf1231937	0x599c8856
-	0x47eb85af	0x6cdf0c60	0xc08098ee	0xa26eaa47
-	0xabcead3c	0x72e567a9	0x54196049	0x502ed324
-	0x2c8773c1	0xb109a085	0xe8a25547	0xe13f68a0
-	0x08ceb631	0x024c1b3f	0xb1701b83	0xe3602a0a
-	0x2d9d092b	0x55f9960b	0x1eaeb777	0xcb422b9d
-	0x15484e5b	0x3b040ae5	0x6851c37d	0xbe99e012
-	0xdf731c32	0xf2a4ddc2	0x4f18a7b1	0xf244d571
-	0x20a13803	0xcff77b0e	0x6a32c0ba	0x6db996c1
-	0x83b3dba1	0x0287b69e	0xc8132123	0x1cf51166
-	0xeae54e68	0x64c974a8	0x4d6add7b	0x58a87bc3
-	0xa70799a9	0xd6575ef6	0x9c67be5f	0xe565e7f2
-	0x6c602d11	0x47a2332b	0x58e3a7c0	0x4bb04592
-	0xb899331e	0x28691b63	0x35a5b304	0x590e8684
-	0x398bce23	0xa6e5d1a7	0xbe941045	0x8248a1c7
-	0xe2f0f0b3	0x8fedacf9	0xe9412fa0	0xfcdd0389
-	0x0aadca9a	0x592efaa5	0x5b32f7ca	0x59331bb2
-	0x8c3edeb1	0x327d14ad	0xaf6ee0de	0xba015362
-	0x331e2a77	0xd0759b70	0xd80e1d52	0x8f24b791
-	0xa77b5abf	0x0dc0bb13	0x22d28613	0xf579ac0e
-	0xfb8f0252	0x7073e4df	0x28a4aa05	0x7e665e37
-	0x8459682e	0x17ce0744	0x55c15497	0xf0d506ed
-	0xe4402e0f	0xeb964b36	0xadf8cdfa	0x51e408b2
-	0xac8f1f75	0x21da7eab	0xd8be84a6	0xb889de7f
-	0xa3b7ccba	0x2e92096f	0x51dea741	0x4bc8b6b7
-	0x509d1e16	0xa51680d2	0x94570667	0xac5f5203
-	0x916845a5	0x1e2b4162	0x39f55bf1	0x903c4c15
-	0x0953148e	0xe0ebd00e	0xcb659fdf	0xd3574623
-	0x4d97e3cf	0x49f4b61e	0x44007063	0x20a32437
-	0x7c5dde33	0x8c7145df	0x9db86b04	0x19b6dc0c
-	0x18ae6d06	0xa7e11c47	0xbf60d44b	0xf8670b5b
-	0xe9e8e361	0x6bea92d7	0xddb5fbf3	0xfe493a6a
-	0xe0010eca	0x472558e9	0xd3438288	0x67dff800
-	0xdcf99ebc	0x8550e460	0xd4f74bf2	0x9cd801bf
-	0x69a5fcc4	0x70ca0a39	0x8ca2156b	0x7c3d451f
-	0x688ccdc8	0xcf6fe525	0xc39776e6	0x2d71269f
-	0x9bac002d	0xdb4bd577	0xaaff71ad	0x99a880ee
-	0xc4e77913	0x4f58dea4	0xb0d35b3c	0xb7dd5cd6
-	0x368f88e0	0x1a153497	0xa61a686a	0xb4b29fc0
-	0xa2605188	0xf1bc0648	0xb2ad7cbd	0xac582f14
-	0xdfb3bac0	0x079fd5f3	0xfb336ee5	0xdbd17aac
-	0x5c5da53d	0x89d5d69e	0x07451fc0	0x53f3ee4c
-	0xfd1e08cc	0xcf46a702	0xe9b4e436	0x25e13d98
-	0x809a73ab	0x07b25e94	0xd5845739	0x7eb131f1
-	0xd3e5d83c	0x5fa46a68	0x178d2b05	0x94ee2f16
-	0x75c6be0b	0x01716271	0x359790a8	0x754a16c4
-	0xa26be7f5	0xd998b02e	0x25497107	0xb842f73a
-	0x34f680a0	0xae8c305d	0x5b9b239c	0x0f2b009d
-	0xfe440280	0x145d1126	0x6d102c8b	0x402b89b6
-	0x9a580c40	0x91aa00a9	0xa03d8974	0x4d2a26a1
-	0xb75b8202	0x16600764	0x211ebb2e	0x28bd93d9
-	0x6518d2cf	0x6d5bd308	0x382c5ed7	0xa29e0aa3
-	0xf89cf93a	0x74a0b016	0x3ca612f5	0x24064cf1
-	0x47747a5d	0xd22975dc	0x3c696e1b	0x0e4d0a5a
-	0x3718d1a4	0x1fcc5ea4	0xab35093b	0xb50603ea
-	0x3650c65f	0x32858ec5	0xa87dd504	0x687c5833
-	0x2a36de42	0x9cb6868a	0xe78d1072	0x675eb362
-	0x64e67cfc	0xcdab05b7	0x72e23276	0xc7dd5753
-	0x409f3b09	0xfa93587d	0x99eb8cff	0xb6c5fc09
-	0xca99a2a2	0x7f5583e9	0x2fd55cd2	0x38a65dd0
-	0xa16d92a2	0x286f021f	0xd71619c3	0x7d1c61f3
-	0xf7507ce9	0x6c2a3eee	0x1053a2ae	0xb63e258e
-	0x86f335a4	0xb5b07b32	0x0d156a38	0x53755412
-	0x76a542d2	0x26f25a85	0xfc038aab	0xa9d96a0c
-	0x8575d08a	0x24805c0c	0x39ea0650	0xb2edc539
-	0x1df34734	0xf7728395	0xe17c0196	0x54079a46
-	0x5c52fc37	0x09d2d435	0x19f28d5d	0x92dc3611
-	0x4f7fa756	0x19a128f0	0x3e273d1d	0xff6309c9
-	0x2c34216c	0xba4cc184	0x8873b38c	0xcd84fcdb
-	0x3ede1e50	0x286cfb74	0xef17d548	0x01e12784
-	0x5365dfce	0xe808116d	0x619f6117	0xaaa322f5
-	0xc81e268a	0x8303df05	0xe251ffa3	0x86b43181
-	0x1f6ab10b	0x60c48f73	0xf0a299df	0x311f1a35
-	0xcf1b31d1	0x67bbee54	0x4be22f23	0xe1cbb341
-	0xce778173	0x495c5dd4	0x2597b567	0xda1bda27
-	0x45409289	0x5f8290bf	0x9b3d5714	0x5a732f3e
-	0x9ec75a75	0xa062a5ae	0x1d9b6d09	0xa983c663
-	0x0fc1863b	0xef46c113	0xaf6517a2	0x3a90caa4
-	0xc1c36909	0x16a68595	0xd83751da	0xf965e105
-	0xf0a2c08f	0xaf5a83cb	0xb1ef85a2	0xb994a331
-	0xd0dc78d2	0xeb278a2a	0xe22a165d	0x3f1f999c
-	0x5b7c2d89	0xa0a9afbd	0xc42db24e	0x061c9ef4
-	0xbf09c71b	0x2e14198c	0x8765e181	0x6eb6884d
-	0xa91be755	0x8d203fe3	0x80e25674	0x0b39ba38
-	0x12cb68bc	0xf0dbdc5d	0xb95f1bab	0x7ce7663c
-	0x227dc658	0xcd46afb7	0xaf9127c3	0x0ba73835
-	0x613b23f0	0x599e6f37	0xb5e6463b	0x49557c88
-	0xb104b402	0xd5276a66	0xa68ce0da	0x5d229e9f
-	0x59292206	0xe71d18a5	0x3627be43	0xa1931f4d
-	0x9b282f64	0xa429e37d	0x2954801c	0x78f8ff7d
-	0x72d0997e	0xb6333f10	0x9db0ae49	0x849d6972
-	0xf3105f52	0x42413f96	0xddb2c652	0x99802d95
-	0xeeedf598	0xfd785866	0xd13a7b1a	0x225a59fd
-	0x19722276	0x9a016c80	0xf4d22f4e	0x5a739fb9
-	0xbaa3488e	0xcf913c7a	0x7ff05f65	0x0b5ecfe3
-	0x86a7dbde	0x2de1255b	0xbadc1a92	0xe8be38c4
-	0xf13fa2fb	0xd46894cd	0xc48b9503	0x8e715854
-	0x3a03fe9a	0x013e5b08	0x4f46f488	0x7e27181d
-	0xec159b58	0xc4977b80	0xcd454784	0xbbaa3742
-	0x124eaaa3	0x66414ef9	0x1e514b4e	0xe978d0e6
-	0x46d8c643	0xd316c855	0xb84dd9b7	0x5122465d
-	0x34c59dac	0xa6f10643	0xd80b3949	0x07536f2d
-	0x4fbcc30a	0x8aa8a4b6	0xdc2be5ef	0xbc3e1c78
-	0xc25d1ebd	0x96919bed	0xdb37931b	0x6e077871
-	0xfb2bf61b	0x9a659648	0xeccda7dc	0x79e86b23
-	0xf1c18329	0x59830510	0xf1dcfedb	0xdc7d2b84
-	0x41e7afd1	0xeca8021d	0x7312d4fb	0x7a45eeb5
-	0xbffc8a1e	0x494d7c24	0xc2a84a95	0x460a0ddd
-	0x7e44dbd5	0x2109fdbf	0x556374c2	0x616bf76c
-	0x8b3ae7b6	0x0e2cfcd1	0x65370b6c	0xf1fbb913
-	0x81c57609	0x4c2cadad	0xfc74a3cc	0xc9556305
-	0x16464838	0x5ef7fb12	0xc90eb9f4	0x72353a20
-	0x46bc1ec8	0xd3b12916	0x51c45e0e	0x061b53b2
-	0x1a203faa	0x4e5e3054	0xbaff1858	0xb65398a0
-	0xd5b4eca8	0x5649844c	0x2e1c6f6c	0xf828c53c
-	0x689565ba	0x76f11b18	0x5dfd40ae	0x1d98abf6
-	0xc9322c46	0xa22604ad	0x2740ba5b	0x99eb85be
-	0xb52a3340	0x3fde5fb7	0x5e0e3a01	0x60f69345
-	0x37f6fd3d	0xd084006d	0x26c3a62b	0x161b206a
-	0x2a224c7e	0x93a45c60	0xfacdce07	0x2e7b4058
-	0x3c79d10a	0xd7939bc8	0xbca2e30f	0xf22b6c21
-	0xbb03c5e1	0xf30b3651	0x2fbb40f4	0x8050c8d8
-	0x8683e045	0xe6024d08	0x81dc0b0c	0x8cd923e3
-	0xdf8df717	0xb1f8d6f6	0xb0469246	0x79ea7958
-	0xe3743d7d	0x83e1cad3	0xeaa7fd02	0x4d3aebc0
-	0xba63ef51	0xd5cde1ca	0x1bdf1383	0xbb462d70
-	0xb777376c	0x5a382db2	0xaed44fff	0x130fdd93
-	0x1ed8bc23	0x1f3c7297	0xf3e79215	0xaabc0139
-	0x50005a1e	0x55ca82c7	0x58778cb8	0x2e58a478
-	0x4c4cff0b	0x3c44a21f	0x8f108d67	0x58211b23
-	0xd233181a	0x9e46b169	0x37533a95	0x33bddfef
-	0x777df938	0xda8a8239	0x45af2beb	0x3613b03e
-	0xe6ae05f4	0xe33730a2	0x1e65dff3	0x7a64a0d2
-	0x79273ca5	0x580a16b5	0xc51b39b5	0xccea7be3
-	0x29d9caff	0xf7377acf	0x0bc27444	0xb68b6ba4
-	0xa75ccbbb	0xdbf69f05	0xe8be0152	0x569bdc28
-	0xb8ebe746	0x43398e79	0xa7def566	0xc99e1f1c
-	0x3be29c87	0x6e4c4b68	0xb8a37b2e	0x84970f9c
-	0x178d4e72	0xac72ec6f	0x0862e04d	0x85cdb66d
-	0xd6f2feb9	0x10d299c2	0xd91a74a1	0x831697bc
-	0xd0038240	0xbe9aed06	0xe808bb08	0x49462fac
-	0x7efb2fbe	0x1e276eb9	0xf83b97b5	0x3754f4bb
-	0x4449cb0c	0xcf2a2866	0x04840e6d	0x9d9b6551
-	0x3b50f722	0xd8f7f14c	0x9ba685f6	0xcf6bed00
-	0x41012924	0x82b27e98	0x7541d6e5	0xfa5b81cc
-	0x91d44937	0x46d27cdd	0x91570abf	0x959e1e97
-	0x7ee9da66	0xf82883a5	0x87afb380	0x761c818a
-	0x180811ad	0x095d4970	0x751dee19	0x9f438246
-	0x32a3c642	0xb3b34b98	0xab450f56	0x539a6ffd
-	0xb339563e	0xe8808c93	0xc7ad9eef	0x0dc36b70
-	0x1278e749	0xe83d046b	0x987de721	0x2115e00d
-	0x7a09efd3	0x8e56c4f1	0xd5de351b	0x98eb73c2
-	0x9becebb9	0xb18998d9	0x3ee01945	0x20eea116
-	0x846bb55c	0xb7f624c5	0x6f7b7463	0xcbb986ad
-	0x545c3c41	0xd754bfbd	0xfc4148ec	0x312f89dc
-	0xe2894337	0x7867e25b	0xeb11c6df	0x9fb721ac
-	0xa843962b	0xef242fd4	0x6fcf4b6c	0xea208951
-	0xd521c86f	0x08f67a28	0x07209b9c	0x6ee42989
-	0x9fdc0e42	0x3794b7db	0x038a398a	0xb339b4b8
-	0x6d621319	0x6b9d713f	0x3537ff34	0x3fff0baf
-	0xa5c0e302	0x8fdfa8da	0x50dede4b	0x448ed0b2
-	0x2178bf5d	0xf7dc834b	0x9762f1aa	0x087a9b65
-	0x7f3cc965	0xcd1c011a	0x4c630727	0x755908c4
-	0xe33580fd	0xca010764	0x677b59b5	0xb3d182d3
-	0x55c2d739	0x8c6f67df	0x10f6b558	0xf034ee76
-	0x540009e2	0xe6343edf	0x95f2508e	0x2a9c22c9
-	0x5d42e77e	0x82216d23	0x10ad67da	0x8ec77e6e
-	0xa88a3bb0	0x4e10dc6d	0xf3fa2dcf	0x59be53e7
-	0x25f758c1	0x2c42fef5	0xba575ddc	0x0435bf50
-	0xd390d087	0x6e230259	0xf7e3c764	0x52c16ff4
-	0xf2a6105a	0x31f0188f	0x83f2582c	0x2b73521d
-	0x6b320332	0xcb7f3899	0x17f23cd3	0xab7d47d2
-	0x535f1340	0x700ea217	0xbcf4f83b	0x16ea4470
-	0x76a618f7	0x30216e93	0x6e80cfd7	0xcf706ae5
-	0xd766457d	0x0ebc1377	0xdcb10949	0x2f679120
-	0x5cc6abdf	0x65754d61	0x1a3dab69	0x8f349b8e
-	0x95bb833b	0x5588b280	0x0f0fa923	0x21250ef5
-	0x73bc2547	0xcd7dabe5	0x4795737a	0x82b92e90
-	0x896f9de5	0xa18ae6d7	0xfeeffde3	0x346b0557
-	0xdc7c068a	0x4e6eed51	0x4ff07c63	0xdd15b445
-	0x97808676	0x304a0912	0x7fe07453	0xb9e64599
-	0xd7a57b8d	0x7f4fd506	0x226719e4	0xe6c251e1
-	0x7ea1ee5d	0x6051b787	0xb00b6e40	0x6babdb06
-	0x725fc094	0xf35fc6d2	0x4e7d6c3e	0xa5a718f4
-	0x17f63fb4	0xc39bf11c	0x808332f9	0xd2c07986
-	0x57bf130e	0xe1f5656d	0xb52a43b6	0x9a105745
-	0xafc22c4c	0xeb5b8a45	0x39153d0c	0x55f1b477
-	0x4a947d5d	0x83dee3b3	0xc3d1e1c1	0xc6dc4d47
-	0xfb93a531	0xea002909	0x95e58a9e	0xf14453ee
-	0xe7fe7f8a	0x6eb7bf4e	0xfd74da03	0xe2a994cf
-	0x4ec6321a	0x27c4a2d8	0xfaecde76	0xd4ba53bc
-	0x22b291c3	0x32dad786	0xedc8172b	0x98f6cbe5
-	0x0407f9c5	0x0e3e7894	0x68c4562a	0x2264dbe4
-	0x938a45c1	0xb02c5428	0x31df8b31	0xefb49223
-	0xad0abeb3	0x9ce02ca2	0x7906e6d5	0x2fbe9f55
-	0x3dfed450	0x9a9f5854	0xa99171aa	0xdedd910f
-	0x3e7727bd	0xbf49e35f	0xfb435c59	0x872ca461
-	0x9693c2e5	0x4d9f7917	0xbf9b494b	0x4cb695ce
-	0xc21c2629	0xaceab2b2	0x30a8686c	0xc09e85e3
-	0xe3cf9904	0x39d0db4d	0x73e0c451	0x64b5d63f
-	0xc27777a3	0x91272d8e	0x511db1dc	0x9d1a6175
-	0x9c7e83c0	0x60037169	0xe9d248c6	0x54d04f10
-	0x99787291	0xc3ee42f5	0xbbd26f8d	0x7fa0ab4c
-	0x1e1e7f10	0x170b04bd	0xdf46d792	0xb17864a5
-	0x832c1074	0x17783980	0x174f75ea	0x92980341
-	0x7aca43ef	0x851a6e2d	0xa25dfbd7	0xf84cff03
-	0x8a3d6563	0x8fff04c8	0x9ac359da	0x58a7b145
-	0x57c1e741	0xbc735a98	0x171bc199	0x9f704237
-	0x1efbde72	0x79b48991	0xa7d67d95	0xe9869769
-	0xf6324dbe	0x17360a53	0x2131f704	0x5cf7b840
-	0x53101e35	0xe71c8bb6	0x1c10fa64	0x28aa5883
-	0xc41d3377	0xe6c3556a	0xa5140cf0	0x1e0224b6
-	0xaabe86f5	0x00b520f4	0x346aa560	0x7de8aef9
-	0x2a19e4a0	0xbe2a2772	0x93653c17	0x2ec53d8c
-	0xd0a5ea33	0x985e6fd7	0xd300651c	0x72ce1567
-	0x16559001	0x6e459145	0x2dafc413	0x28f514cc
-	0x2d1b9e94	0x798b5770	0x3bd27af8	0xd5437be9
-	0x0bc1de32	0x83f58c43	0x4a968323	0x873cf533
-	0x44b8f501	0x8caa31dc	0x90961244	0x257e5811
-	0xfb1c4c4d	0x7203f540	0x9d2294eb	0x533e9896
-	0x670bf234	0xefde4d0a	0xace846e0	0x16a1421f
-	0xe6a40e79	0x8b0f861c	0x63b8416a	0x80bc7963
-	0x035bcc06	0x2f3a8636	0x4adeb4a8	0x527a1f98
-	0x6d0ae365	0xd430ee93	0xa54d6e88	0x9e492859
-	0x6d435e2a	0xf3f336df	0x8789fe48	0x04683847
-	0xeb35012c	0x793f787f	0x1649fc98	0x4daae27a
-	0xa899ef37	0x0aa874e3	0xe877985f	0x3877168e
-	0xbcd9af49	0x925bd4a0	0xd7653ea4	0x1a7356c1
-	0x53cf5cbb	0x5b3e660a	0xce923831	0x42ea11b2
-	0xcb85c607	0xcb4fef4b	0x33ac8e92	0xc68e0ee8
-	0xda28f304	0x34466a58	0x4e3ed659	0x433c37d5
-	0x6e5d8f11	0x2306c1d7	0xb8562926	0x857280be
-	0x7f6978c9	0xb6127ef8	0x848ff180	0x3f175d08
-	0xc9ea3682	0xa7f8401b	0x073a04ee	0x75d43c6e
-	0x193e70e8	0x9e6ee78f	0x5eda1df9	0x53e54ed1
-	0x94a57a5c	0xd66dc923	0x121c0f87	0x637f93d0
-	0x52b5658f	0x34ca3432	0xed262d4d	0xe7c3c8bf
-	0x05519bb1	0xa27335b6	0x8aeba357	0xa9edeef9
-	0x06dad515	0xcc0258ca	0x0db85a3d	0x4edbeee7
-	0x8efdc1fa	0x53f1f91c	0x367b73bd	0xc9785288
-	0x8046ec91	0x1270cb82	0x6a5cc22b	0x7c56f6c4
-	0x09140a7f	0xa362df46	0x794ba791	0xc280f317
-	0x0a8c218e	0x8fd18bc7	0x9d112770	0x4a94c675
-	0xd08f6e86	0x200978a2	0x08bb8824	0xeda38a74
-	0x396364ed	0x4cf3fae5	0xd1bbcc8a	0x38e68b54
-	0x49fe9e89	0x0f372a6f	0xcb8206ec	0x686c51df
-	0x3d21fba2	0xeed5addc	0x8cb09804	0x7b144b6c
-	0xc31b72c5	0xb2e1fc8a	0x699440df	0xa1484706
-	0xbfd64898	0x87c7d89f	0xdd1f06e2	0x9048531b
-	0x3fb97a6f	0xec79fb12	0x1a81577f	0xf6fe7c86
-	0xfa572435	0x0ed1607e	0x85823de4	0x2688f491
-	0xcd6f5341	0x55c944e2	0xd94a5421	0x43b0eb08
-	0xabc52c65	0x3f624e64	0xaaec22a7	0x0b6fc108
-	0x0b5e8a54	0xb9f36d25	0xf531e230	0x18405343
-	0xadf99cb1	0x779851bb	0x93aec541	0x8364b884
-	0x9e14f66a	0x389f6625	0x94d43b9a	0xd9f3b002
-	0x34b23621	0x80599e02	0x7ab4a0f0	0xb0428b5c
-	0x8510def7	0x2871743f	0x350d0bc3	0xdbe61d9a
-	0x787b3c6c	0x80272431	0x2ed6efd3	0xcf77c8b4
-	0xa21f406c	0xcb82aafc	0x451b3a49	0x4bfd9ae6
-	0x4bb86748	0x03fbd542	0x329ad4fd	0x0761e756
-	0x07f31e88	0xe6aa2f44	0xc209345b	0x250eab3a
-	0x2710b3b1	0x710bb403	0x921c083c	0x94e25ccb
-	0x6b344255	0xda1501d3	0x3e0dc98c	0x2c09adda
-	0xefbf0286	0xdec41f1c	0x3865e02d	0x211215e6
-	0xbd3e4351	0xa3b9abc0	0x9ab908b2	0x5c345108
-	0x0175a871	0x3611d15b	0x54733b2a	0xe57bfda6
-	0x3b507ed3	0xcdcd1007	0x5314fc0d	0x3ef57680
-	0x181ffd9e	0x27a7e64f	0x7a780684	0xc8fadf11
-	0x13415b31	0xce53dcd9	0x55488687	0x858b70cc
-	0x14067837	0x0f3f012f	0x41f0636b	0x1c8d2f52
-	0x9dacc300	0x63b27876	0xe1c23617	0x02c57956
-	0x85a91d2c	0x0740e7a4	0x619eab0c	0x10f254ca
-	0x9ec8ca01	0xdfd090f4	0xbac084ac	0xa1f8168e
-	0x7fa0e114	0x282b1cac	0x8e1283be	0x9e108b3b
-	0xc6eb7a09	0xf8d643a3	0x3b4afa67	0x3e7f307c
-	0xa5fb1937	0x0b00178b	0x017369f8	0xafe1fcff
-	0x29987f54	0x965cfcd5	0x0e362047	0xd03dfc30
-	0x9540bd32	0x2c688ee6	0x6c32d9c1	0x5935278a
-	0x11b6c4c9	0x69202bd5	0xce48e114	0x9c5bc22e
-	0x3e92fc71	0xb77657e2	0x9232fd3f	0x76dbd637
-	0x1d672fbf	0x4dcb0727	0xe719838c	0x3db49bc3
-	0x77d94683	0x6d82214f	0xdd3d51cb	0x3c23f486
-	0x46253c8d	0x347089d1	0x7fef2912	0xee1d3cb4
-	0x10da8cbd	0x7172b3ac	0x95c24117	0x60d1bd52
-	0x1b2b9552	0x20ac6729	0x3614535b	0x830844db
-	0xd9310617	0x3480f0ae	0x8e2e14df	0x4a02c210
-	0xf5944144	0x680b5216	0x5b5ff941	0x921f8c17
-	0x798012fa	0x43dd9855	0x725e40e7	0xb3bbac37
-	0x44ef21ec	0x7fcbcfe0	0x0630ce23	0x3f39b5dd
-	0xf0b3f7dc	0x51bdefd5	0xf5e0b7ec	0x3a2c2398
-	0x00e4ad5c	0x4017fa32	0x205c567e	0x70c646e9
-	0x81c0291b	0x33c5050c	0xeda458a6	0xa6c868fd
-	0x1b70f270	0xb661cd4e	0x322b97a9	0x1572f522
-	0x004792fd	0x01d23270	0x667b335f	0x5da3142d
-	0xb7de831d	0x9736e866	0x0a70d898	0x16d1b373
-	0x70bd1a6b	0x75170aff	0xe98d71af	0xb9829684
-	0xedaa0924	0xbc67c151	0x155b4797	0x63c8d08c
-	0x7811c5b5	0x84a348e8	0x6d841a8a	0xdc0e3707
-	0x3defd447	0xac78f3ba	0x44ac7616	0x68147936
-	0xc3f6fe4f	0xe3550b13	0x1dbb593e	0xeede24e0
-	0x3935ec43	0xe0a30569	0x66a0223f	0x32b741c6
-	0xd9e35135	0x77793169	0x8479a087	0xcf7433a2
-	0x91d6967a	0x34aee2fd	0xfd68c051	0x6375cafa
-	0xe5d7a0bf	0x1a3cdf26	0x4f0765b6	0x89dd8de2
-	0x0ebfa813	0x8a5b91c0	0xd698549a	0x4ee2cfb4
-	0xc2dbd4a5	0xd0e2ab9b	0x9765a4e8	0x880f32ac
-	0xf0f30fcd	0x74021c54	0xa1d6944f	0x25270ba8
-	0x75dd0748	0x770e7b69	0xd6dafdd2	0x0254ea84
-	0x427eb60e	0xf5a422b1	0x53fbc0e3	0xb470027c
-	0x3ff09ede	0xbecc9100	0xba2d3ea8	0x86295a6c
-	0xf3a8690e	0x503f198e	0x7498daba	0x4c04fd03
-	0xcebcfdcb	0xec671b62	0xeb98f36e	0xcf3d095d
-	0xfc627be1	0x7a6aa482	0x4961f814	0x82a9df39
-	0xeab68128	0xe618105e	0x603e4e80	0xd42305a1
-	0x2ab596b0	0x66ef4bf8	0xbe2d8a31	0x7571fd10
-	0x6ad34e73	0x77c92e69	0xf70829d0	0x243bca33
-	0xa41899b2	0xad3847d1	0x326085c9	0x1e32f76a
-	0xe5939032	0x2ef87117	0xedd0598b	0x0f5b0ab6
-	0x843d972e	0xbdedfd02	0xf6f281d2	0x806f8619
-	0xc0d4e6f7	0xc7c752e2	0x4cb18e8c	0xa3109bc7
-	0xb3c9d39f	0x5fed1b89	0xf56bf4a6	0x1ef9ad37
-	0xb6d27d00	0xd62e0e2f	0x427c1f76	0x64b708e3
-	0xe61b8094	0x58c140cf	0xc9ed8bfd	0x549d8321
-	0x887f495a	0x9b92965e	0x19dd4f23	0x48faa916
-	0x536988d2	0x5c41f555	0x78dd7a98	0x52c98af1
-	0xaf1aa0a7	0x472d9c18	0x5072ec30	0xcb8d8c2a
-	0x20ca2831	0x54741df0	0xde485e64	0xde719ed4
-	0xd0e4fa14	0xdbe68e08	0xc4b52f6b	0x7c478181
-	0x5ce15685	0x20bf9757	0x01ccdc90	0x3f59a540
-	0x09dfd538	0x96d5313a	0x11b8a5b5	0xb185b4a6
-	0x80b8ebac	0xdcbf7885	0x1f78d8ed	0x3f845528
-	0x8f10047b	0x31048ec4	0x08b16c82	0xef8212ce
-	0xba7e12b6	0xbb27b4dd	0x880c366b	0xbb9013e9
-	0x680e9afc	0x639c8dd4	0x67a899a9	0x95d99658
-	0xcdcd0ef6	0xd35bf9ae	0x73dc39ff	0x1159cdd6
-	0x820e821a	0x233b30ac	0xa5355178	0x508a060b
-	0x70f8eb69	0x7dd6cd6a	0xc9babdac	0x952886c9
-	0x20a4d780	0xcafe7a7d	0x4a564d22	0x23c88386
-	0x95dcd3ba	0x57e703c6	0xbafaa61d	0xd515f701
-	0x1634dc08	0xaf721b5c	0xdb4b52e4	0xcb54c7f2
-	0x1bdf64d1	0x7e798a76	0x20066741	0x1ecacec1
-	0x2d5be224	0x8eec039c	0xa2adcff2	0x6abe342a
-	0x15929ccb	0xde4a5a29	0xb0ef2733	0x51e6e38e
-	0x88f7ded5	0x9a7c3d12	0x0102cd55	0x1e5fa60d
-	0x43e10b70	0x17c67005	0x6d60158b	0x03ebc351
-	0xc1877454	0x99486475	0x68e31d63	0x4ef41164
-	0x1250792d	0xe2dbb2b7	0x3f041adf	0xc00f1ca1
-	0x0bf6b065	0x581d1496	0x6babf291	0x0cab401a
-	0x37305a02	0xd8b025f0	0xd9aad863	0x33378c27
-	0xfce64bab	0xb944fc9a	0x421cb71a	0xeaaf1a0e
-	0x08c62ae4	0x4be73168	0x95907070	0x7b40f3dd
-	0xa0273b1e	0xe4995d27	0xb6aa456f	0xbbefad85
-	0xdf650ed9	0xcdfde8ec	0x8f3ba9b3	0x6c8aaa45
-	0xbb938c57	0x2d26fcf3	0x1fc85e00	0x30338e08
-	0xe3502aad	0xfe0528ba	0x25c888e4	0x136224fd
-	0xe3fb8d06	0x8b521420	0x8d4849b0	0x128a5579
-	0x485bd52d	0x46ced7d5	0xe922bb2d	0x76d52253
-	0x976436c0	0xc3fa64e6	0xf900fa97	0x1ef8db2d
-	0x79a8b6e9	0x1ff2b058	0x61dd59cb	0x76eaffd9
-	0xdaad829b	0xaf929bc6	0x7f1461f0	0x28541e57
-	0xdb2223ca	0xb5a41af3	0x963dfe3c	0xf332afee
-	0xf01270c1	0x37fff0d5	0xa8db736d	0xbf6b8ace
-	0x060b9827	0xe04fa359	0x8483405b	0x526756af
-	0xf93bd116	0xaaf82ddc	0x3d800e46	0xa462a35c
-	0xb62236e3	0xab42ba34	0xb662603a	0xe8a24ea0
-	0x4b13879b	0x0271f215	0xb7227ebc	0x1c85b75a
-	0x06a7f989	0x5a58a071	0xf027ba62	0x3940d149
-	0x174c162e	0x1710f899	0xe50684e0	0xe58982ee
-	0xcb3b9fa5	0x545dd73d	0x42a33d21	0x14ce3ed8
-	0x151fc3e7	0x6fa96a65	0x60131642	0x20115648
-	0xe2fe3663	0x618bb9ab	0x9b2fe08c	0xce906711
-	0xb9fbe11b	0xce79c0a2	0x76320db5	0xd2b8956d
-	0x3c8fba1b	0xda7d5cfd	0x79930fde	0x7b1eaab3
-	0xe4190098	0xe46cc648	0x796557fa	0xe61f5c5d
-	0x85341adf	0xa01cc486	0x1460f8f8	0x0de8488c
-	0xc3575498	0xdaba60b1	0x6e00e9de	0x8de1e277
-	0xd7ef67e0	0x6f209a77	0x582ec810	0x4636f6cc
-	0x6bd9e60d	0x64ea05fc	0x580f9f7a	0x0f18218c
-	0x240f624a	0x0afc252f	0xb025c839	0xe6a5afc3
-	0xd5e32234	0xf30ced0c	0x90f032cf	0xb6fd59b8
-	0x2ef1aeb8	0xdd5d3fe6	0xa18a909d	0x65c3e9e1
-	0xe821d2f9	0x957146ce	0x86ea8c2e	0xea79a59c
-	0x91bbff8c	0x50efab7f	0x4a8c0919	0x11faafd8
-	0x3f3463b9	0x80e0e50a	0xdbcc8485	0x3f7c058b
-	0x4cfa4e1f	0xff8867ed	0x6bf2f6e9	0xa61daaaf
-	0xb718eeec	0xefe4f834	0xd0c4727d	0xec787df0
-	0x85bfe1f5	0x7329affc	0xf4c0ed95	0xa6a8b495
-	0xb3bd1c06	0xd38e0a09	0x26e3f747	0x6bd5ceb3
-	0x5eef12c8	0xd1011d66	0xb1dd692a	0xba1294c7
-	0xf7ddcb0f	0x4dbd2861	0xb29db408	0x051fb421
-	0xa4fd5f8c	0x1ad5a3d0	0xd95aee42	0xd52203b8
-	0xc4e76978	0x5780ee25	0xc38f6280	0x0e4bdb05
-	0xdeaf0dc3	0xcada9dc0	0xf7dd201b	0xffe07b67
-	0xe486f4d5	0x72a0b32a	0x518c1122	0xc240db35
-	0x1d7b5a09	0xa26636f5	0xe1b716fb	0x9158d0d9
-	0xfbe3b60e	0xd37c00dc	0x551615da	0xc7fde3ed
-	0xac94b6ae	0xcc87d6a7	0x0d010d6c	0xe1bc4072
-	0x8d8a4caf	0xf4381342	0xe3efc8dd	0x64be88ba
-	0x0eac9658	0xd10e87c6	0x8dc223f5	0xbbadd543
-	0x3ad28376	0xba68d553	0xbce5620d	0x1adc3d5e
-	0xa64d27fe	0x65086819	0x80b82c62	0xff91b5cd
-	0x97cadf1a	0x2cb0d45c	0xa73587ca	0xdaffecee
-	0x299e3888	0xb4c116f2	0xd7aee299	0x9c33d177
-	0x8af686c9	0xba6b45b6	0x47fe7688	0x1e49d908
-	0x721370a8	0x1220ffc9	0xeb62dcbd	0x4255a463
-	0x13ef302e	0x619bc137	0xce369fdf	0x3a1ded2d
-	0x88dc709e	0x4b10b186	0x582eba1a	0xb508101b
-	0x6e827983	0xb25e5755	0x9f29bac5	0xdd946461
-	0xa6b87255	0x92471f76	0xac61af93	0x670e9ae7
-	0xb3cc278f	0xb674f114	0x5616b751	0x527869b2
-	0xb6847ec3	0x7c94f508	0xdedd2e51	0xe322e023
-	0x3ef45d78	0xc95848ce	0xd53c243c	0x645d8456
-	0x1c510cde	0x243ad2e5	0xfafac2e4	0xc23ad8fc
-	0x481fe577	0x1f73fdc8	0x4cf5388c	0x8afb0c47
-	0xe39a7e0e	0x439e32a0	0x1a3af126	0xdd0ddbcf
-	0x56efe7bb	0xa4526c50	0x1f1e8d7c	0x6fff2758
-	0xa9cfc7c8	0x9aed3088	0x1419791f	0xc41006c6
-	0xe665ffb4	0xe0cfc001	0x5ac279f7	0x8dda44e8
-	0x6ba63b5d	0x11cd5e85	0x87b35603	0xfcb57486
-	0x64df1bbe	0x1df9ceb9	0xc2565187	0xbb6b4730
-	0xa60ba743	0xb50ca534	0x224eecf0	0x8acbd1e3
-	0xff2a22f6	0x00b94b20	0xb2bb1824	0xe3af6f67
-	0x78db1d5c	0xa3dfaa5e	0xb23a1a59	0x234628d1
-	0x46a0b6b1	0x6d7b354d	0xd7f14b18	0x492cdb7a
-	0x4b0e5fb1	0x3b210deb	0x82ba85b1	0xe5af7727
-	0xde5e2892	0xf4ba96b6	0x1011fde0	0xb96e65b0
-	0xb3f72d55	0x4388cb56	0x09f8801d	0x534eecde
-	0xa30f33cf	0x2454f5c5	0x5f32f1a1	0xd1d008eb
-	0xadb25f06	0xea32375f	0x71734ccd	0xc989e49c
-	0xb45f560d	0x49ed0d08	0x5ccf1394	0x5115dd15
-	0x46876215	0x20e6e84f	0xd5deaeea	0xe559d4f2
-	0x1e1c44d0	0x9f582603	0xad90b17d	0xf16c26c9
-	0x7f0708f0	0xfeb0b9e1	0xb853f20e	0x16f3ff5c
-	0x1789f6ba	0x236bb3aa	0x906f2ccb	0x255c8814
-	0x9d762cb2	0x2846e2b6	0xa34f8522	0x2502c2fe
-	0x698ad3e5	0x09c88175	0xdbee86b6	0x264167d1
-	0xcce5d399	0x78a3f959	0xa0a515c8	0x36c2db5c
-	0x5dec037f	0x56a558ad	0xa17a21b5	0xca0296a3
-	0x963a70b4	0x2733e44e	0x4f979549	0xf3738ba0
-	0x60aff2d1	0xf66ed176	0x8f658d9b	0x1e83fc2b
-	0x28a3d57c	0x1d50c6d7	0x434f286e	0xbbd6f950
-	0x5bfebf75	0xe366392a	0xbd328d7b	0xf10a2ad9
-	0x59504439	0xac3f2cb8	0x28cd3fd9	0x3776a6d9
-	0x5ac2b26e	0x25171f43	0xfb20e0e7	0xda4565f0
-	0xcf0cd438	0xf54f1ff9	0x33322457	0xaa368462
-	0x540acfd9	0x331fff32	0x8b66b3b4	0x19a74ca7
-	0xe3037b68	0xa4ddcf1a	0x48dfd4e6	0xe0302745
-	0x21522f0a	0x3b9f1cf8	0x2f7da1d2	0xd1e02b1a
-	0x89d834ef	0xc03b327c	0xa32b106f	0x2bfb3409
-	0x7f001db1	0x9ad9a334	0x0f2e5ed3	0x1063a583
-	0x6cb009d2	0xe9670521	0xdfcab184	0xd02add2b
-	0xfa7721f2	0x6e772878	0x11c5f0cd	0x1d228ded
-	0x54d84a8b	0xffbb136f	0x489a4619	0xf51cd9d7
-	0x6618cdff	0x76685892	0xfebcf111	0x02ee0a86
-	0x77ffdd9e	0xd36303bf	0xed4a8619	0x0160eb27
-	0x0b7ae017	0x7e3919a8	0x1b0c65ca	0xc8c7ef9a
-	0xdd593e48	0x48091b98	0x5ad15379	0xf9f54186
-	0x8c064d3f	0x09f23b45	0xb1bf1f50	0xdefe3c11
-	0x3d9c3506	0x328acb8a	0xc0efd1cc	0x7f3e472c
-	0xbd0855c8	0xc32d33ea	0xb2aedfad	0x5f9c5e3f
-	0x39fab7b6	0x3d58511c	0x74dce606	0xca5975f2
-	0x7adc328c	0xa7f2cf36	0x9084c11d	0xa25fccfd
-	0x0f5591e9	0x7c912a6d	0x6bcd5638	0x74174d51
-	0xe4f38864	0x545a4f72	0xad79bce7	0x68f23ea3
-	0x2c29455e	0xb2dce3e7	0xf75922bd	0x62d9d813
-	0x2ea9daf9	0x9544ba17	0x1036f50d	0x003d0734
-	0x6de2f91d	0x12de6d4e	0xbe6f77c9	0xcdc6f7e0
-	0xb7bc6908	0x8102989a	0x81b1ecc4	0xbec4c06b
-	0x57ae207e	0x0d9bf8ed	0xf82fd233	0x626e99b4
-	0x775ba43d	0xfdbe57b3	0x9e13e0ae	0x8f9e71cb
-	0x22e5b181	0x879a9646	0xa59f02b6	0x315bea64
-	0xfc2d998e	0xf3ee358a	0x465f0469	0xae5e30d1
-	0x8667c5ea	0x4d3797f1	0xdd9119c1	0x8a5c7526
-	0xefdbe49b	0xcba8bf75	0x31c56598	0xb089371a
-	0x50b88730	0x8b04e9ea	0xbe766234	0xb589b311
-	0xac86a2dd	0xf3cab9d4	0x8392e86e	0x459f4c2d
-	0xdc6e9e42	0x38fc7db6	0xbe1c3f55	0x87827bb1
-	0xd3fb2dae	0x29f65cb9	0x288ee868	0x44ef835c
-	0x5412f96d	0x8db90a63	0x619eb896	0x819145d0
-	0x4c334fcc	0xb28d29d1	0x71198c8e	0xcb7a1ec7
-	0x67d911c8	0x83e5b451	0x18dc1483	0x74d2d7fc
-	0xfebe405b	0x1b1865d7	0x552adee0	0x62e24345
-	0x4c772a36	0x047bfaa5	0x848961c3	0x86f2f24c
-	0x3f5db1e9	0x48c4d9c7	0xd7902c02	0xa0dfb8c6
-	0xb16ca129	0x7df0a350	0x58e2570b	0x6c0aefa5
-	0x2c8a35be	0xd155ab73	0x0801d1ad	0x913ac469
-	0xc6398211	0xa44aabec	0x74f991fd	0x122423d0
-	0xd1d7f77d	0xeccf8eff	0x59ecfdbb	0xb85cd73f
-	0xbd10ba8d	0x0c9880b2	0xcabcba47	0xc11e71ef
-	0xcb57870b	0x3a29030f	0x0bff4c01	0xf2629315
-	0x6686b1e9	0xd2b50835	0xec24eb6c	0xb23c7e88
-	0x045a35c1	0x5fb62127	0x2dcc31f7	0x5c47cd7b
-	0x1059b75c	0xe2d6d12d	0x6bc8f0da	0x30ade89c
-	0x35b06222	0xd13a1347	0xacbb2f8a	0xb7fc8acb
-	0x2edd849b	0x8d74157a	0x562d8d4d	0xa393948b
-	0xb89b904c	0x418eee39	0xd42898ae	0x630e1cda
-	0x96c56104	0xdd16c830	0x89ae9ec2	0x1e1cadb2
-	0xb8ea73b8	0xabaa7ad5	0x654ab956	0x17b2bb13
-	0xb064652a	0xbf9897cf	0xaabb9b9e	0x38a0654f
-	0x8bc378bf	0x11559864	0xd193ee51	0x3883fef8
-	0x461d458b	0xc35b1b22	0x570015df	0x2b18a043
-	0xab4aee83	0x4e0bff9e	0x323dafd6	0x8bec69ed
-	0x1846d886	0x0ed944bd	0x9a2b4a60	0x132616d5
-	0x86f3c871	0x76ee6765	0xe971f2cc	0xabaac761
-	0x59bf478b	0x0d83ee79	0x0883a1e1	0xbb4660cd
-	0x24c77bd5	0xed55f531	0xfaea8dbc	0xdfecc13d
-	0x285e5bef	0x7b14cc12	0x68cb6d5c	0x07b7a0a8
-	0xaf3d6e45	0xbceb6223	0x1eeaa87b	0xbf0f9998
-	0xf7582f97	0xce1d2f25	0xd8509595	0x1f6729ba
-	0xe3fccc36	0x7ca2d51b	0xa92c327c	0xe1b49064
-	0xe3cc87e9	0x82c05001	0x9d855812	0x0a7cda02
-	0x65017632	0x1b226e96	0xd4ffaa0a	0xc5a5e42e
-	0x04ba35e1	0x39f6606d	0x23668a62	0x9f670515
-	0x4fa60d9a	0xc8bd3911	0xd95d20c8	0xfe483aa8
-	0xbad0ea2f	0x3a443ce8	0x3857d9f0	0x4516097c
-	0x98d96ee3	0x11529725	0x85c93890	0x47461181
-	0xf6fbe21d	0xda939a92	0x1bf3d3d2	0xf5385362
-	0x31937784	0xa7b86d9e	0x42bbf80b	0xaa3c390a
-	0xf4b7d5bf	0xb1c43ae7	0x59efcce8	0xb69885db
-	0x2a6ff378	0x20f6ecb3	0x5cd55e2b	0xcb345f54
-	0x6ff1d8c8	0xa6766f2a	0x80b3f21e	0xb69aa081
-	0x7b685d4b	0x2b84356d	0xc8f7c968	0xdd9582cb
-	0x2ae3329d	0x2884e0a1	0xcfba6d58	0xe80ffa06
-	0x1d9e8104	0xb1cb5fdd	0xdff34ce8	0xa3d46b2d
-	0x229a693e	0x02c1ffad	0xb52810d7	0x94a5f91f
-	0xb2410f87	0xb827abdf	0xd608ca6f	0xb1091e4d
-	0x75b7eb78	0xc40d51ea	0xe8c64259	0xa2b38060
-	0xd3284d20	0xc7bcf1f7	0x380b300b	0x469fd0aa
-	0x39f0e4a8	0x58b56c61	0xe42a3c3e	0x95afbad6
-	0xd989f15c	0x12f9d899	0xaa41188b	0x5ef0a7dd
-	0xe50d22a6	0xceda0b9e	0x53e0fd62	0x4f974e41
-	0x78684102	0x743bc6aa	0x973a47ff	0x48a09dfd
-	0x815546e1	0x346ef0a9	0xd8b9f0d9	0x1f990a29
-	0x1cb7cda3	0x93b243b5	0x081298b4	0x8b1c0520
-	0x6740563f	0xad1275bb	0x82aeb54c	0xcedb023e
-	0xfa9275e3	0xac1918df	0x395ffc44	0xe52017e0
-	0x9b88236b	0x47229fe7	0xafe00678	0x1b506855
-	0x6cd90e68	0xee6332a0	0x806910a8	0xf42b4856
-	0x99ba5340	0x8a0f68d6	0x7a7442e0	0x01f543b9
-	0xd3ae2a29	0x82006e7f	0x84f3c581	0x945c25c6
-	0x08ebe7a0	0xa544b292	0xa828419b	0x17363dec
-	0xf772131d	0x59edff26	0xd05d94c9	0x86f00bb9
-	0x45ce081c	0x25916c63	0xbc881029	0xa52c11da
-	0x846b2a91	0x5802a2cf	0x4a8de481	0x2b418464
-	0xfc6c04ee	0xf23c0f6c	0xc470aa16	0x5f168faa
-	0x544e44ed	0x66e02d1d	0xe4316d32	0x5faa049a
-	0xa3b599c1	0x1712d5c0	0x22c049f6	0x0dcf6498
-	0x59d976ff	0x5729d27b	0x20667d36	0x5e94eb1b
-	0xfe9f912a	0x5b31c8d7	0x96754466	0xb5b7387f
-	0xe6557f48	0xc095086b	0x1876dd38	0xbe3bd213
-	0x2a956ef8	0x59cde6dc	0x79ef6f14	0xd479ac9c
-	0x4fb12aa6	0x1773ac27	0xc99a79b7	0x88319c2e
-	0x017171b0	0xe9322144	0x89ad5ffa	0x66bce095
-	0xe7feea4a	0x67457e06	0x4c85a956	0x91eeaf30
-	0x8e9a3fb3	0x04029d73	0x831daebb	0x15105d48
-	0x855d539b	0xe041b09a	0x64d2d1bb	0x3c3249f1
-	0x9e601a46	0xf6c06195	0x9304a550	0x07ba1e54
-	0xe0e41cbc	0x686ba561	0x92a1174e	0x8dae719e
-	0x7363732a	0xe31c5716	0x75ea27ac	0x20dce24b
-	0xcdd0cb3a	0x7510e7dc	0x6b438775	0x7dc88707
-	0x097883a8	0x9a0653ba	0xa5b58b39	0xb4dffe70
-	0x3dbf5354	0x1296bec8	0x6afea6f7	0x5a396962
-	0x44c59723	0x00197649	0x88476700	0xcebb0206
-	0xc6cb5364	0x01ab08a9	0xefc19a10	0x98b3dbb7
-	0x79290d1f	0xeeb1cee1	0x155d3eb0	0x0d1ad333
-	0xbecbaf44	0xcb494c9e	0xfaba7d92	0x8f0a38d2
-	0xd71aadd7	0x96898e98	0xfae22e00	0x5cdf8ce9
-	0xec12989e	0xc0e235d6	0x35ffad3b	0x0607e758
-	0x146c87c7	0xd441c093	0x94ba23ed	0xf9029146
-	0xb2a55678	0xd9575a72	0xc8d977ea	0x3e4ee1e9
-	0x929514f0	0x947b0b81	0x7659a020	0x1e889477
-	0x47fc8fc3	0xba26006b	0x11ba9b5a	0x296ee7c0
-	0xb9625907	0xce20ae26	0xab5c4ffd	0xc8fb7bdb
-	0x09b94a92	0x96955d13	0xcc165a1c	0x59774853
-	0xd033d21c	0xfcb748fe	0xcca14a49	0xf7c3bddb
-	0x1699d641	0x5a7df26f	0x800db96f	0x3f06e996
-	0x32cb5eec	0xcfed09a3	0x590f6e50	0xe0de426a
-	0x8818035d	0x3e864da1	0x9915f5a5	0x0c9f0e01
-	0xc039e81e	0xbd41702e	0xedeb91f3	0x58bb813e
-	0x58d88d4f	0xcc9aebb9	0x1f16b1f6	0x20289a23
-	0xfc74f52d	0xf76141fe	0xefeea38e	0xb264ab37
-	0x5761d199	0xa615c301	0x854a2586	0xece5890d
-	0x25687347	0xdd5b00cf	0xdc380b09	0x3679f957
-	0x8d28f162	0x8d192079	0xc5018575	0x84e7dc2b
-	0x6801ba12	0x0ff46ee9	0x05977f7a	0x2804d141
-	0x2d66aef1	0x12b96d1e	0xbd0fee36	0xeb61eb3e
-	0x3bfadea6	0xecc451ad	0x6a7c496d	0xa9df4093
-	0xba53eb3b	0x6fc140f0	0xa10e0b45	0x7177ac62
-	0xcf5fb075	0xf15384d3	0xe76956d2	0x6bfe3cd0
-	0xd4c176b1	0x7b83caa4	0x6fcb1c28	0x7013d243
-	0x8303b45f	0x77217eec	0x5f04b4cf	0xed77af47
-	0x4ee8c05b	0x84d50949	0x4af30115	0x6536adfa
-	0xe3460043	0x42d089f5	0x6e7b3b0a	0xa33f554f
-	0xb2f9a7f4	0x8b1ee0d4	0x75b77494	0x5084f874
-	0xd12a5561	0xe22cc792	0xc5b37ca4	0xd3325f7f
-	0x941da42e	0x5f3faf13	0x4d328409	0x2efe01d3
-	0x54742b4e	0xd07c956a	0x57f65956	0x6c1af66e
-	0xe0a2f710	0xe90fc5fb	0xaabb9038	0xb1b78f53
-	0x2235d7ef	0x5421ca3d	0xc2d423e7	0x0d44fe4f
-	0xcb104bc7	0xc68e796d	0xc9f45636	0xd019c30a
-	0x14bdaf28	0x8c1a1651	0x90ab3551	0x9f19da7d
-	0x9b987a22	0x8d49388b	0x89c83ae3	0xafa42208
-	0xf29b54a3	0x83bc5cbe	0xe250c960	0x2c902a21
-	0x057042d0	0x6cfce181	0xca9a5abc	0x43739c7b
-	0xdcaa30b7	0x658f0a5f	0xfc3a3524	0xf1d40104
-	0x611b0e9b	0xf50e2887	0x0fd173f1	0xa0e9597e
-	0xd70ca0e4	0x66657238	0x4c6b155d	0x46021c60
-	0xf6abb98a	0x8b8eca83	0x63a6b1c6	0x000761db
-	0xb9280399	0x68593f55	0x7515caff	0x2c50e58e
-	0x512cab6d	0xebe2dd7d	0xe627fe0f	0x1c85dc4b
-	0x867a14e9	0x5052f8d0	0x8c4bfb3b	0x77047e84
-	0x650c4f5a	0x8f28e68f	0xe50223bb	0xd38f07d5
-	0x1924055d	0x0a89a801	0x9ebb9896	0xd4c7c7e0
-	0x6edea478	0x74ec0a2a	0x4d70ace1	0x1f57c098
-	0x9acae446	0x2d695902	0x0b7b67bb	0xf2c1cd8d
-	0x9d999240	0x02916fc1	0x9eb6f334	0xe7b45cc4
-	0x1155b93b	0x8a101032	0x71a1014b	0xf01bb4e8
-	0x04a38871	0x57d7d947	0xa7b9d28b	0x3f7969d0
-	0x3aca24a4	0xf9d4c499	0x2220fe8b	0x94b1f831
-	0x42f919fa	0x68bed324	0x15a50bdc	0xe29db9d4
-	0x7fb44468	0x3d82d179	0x4736a849	0xc04dbc09
-	0x797c4eba	0x7a6e09e6	0x3704f556	0xe0200cd1
-	0xc52dd55a	0xc80971f0	0xe6c01cfb	0x8057e7bb
-	0xd36b505e	0x85d81001	0x569f284b	0xf44d32cd
-	0x8b6860e5	0xa65bcde5	0xe55c743a	0x9a8a1caa
-	0xd3f91d2b	0xb27506e9	0x82316358	0xbe864575
-	0x809bb916	0xc978bc53	0x4725378d	0x30e50762
-	0x67586f24	0x01a9fcb6	0xe9f6c5b9	0x19719844
-	0x9fb9fad4	0x08c4b450	0x4a45b9ac	0x3048f27b
-	0x077c4a30	0x4aea9304	0x3b2a2216	0x3cf58019
-	0x84f1cf20	0xca0eb68e	0x50775bc5	0xd1f7aea7
-	0x8ae46127	0x54edb313	0xf845afb0	0x61f398d3
-	0xf536b987	0x0b9e6912	0xdb2f264e	0x78e46fdb
-	0x41fbda89	0xf03fe81f	0x187c1ef1	0x17bc721b
-	0x41cf8c8b	0x9b011fb1	0x1aeb5155	0xd0a0fefa
-	0x6751ef85	0xd5d88dc7	0x10825111	0xfc087529
-	0xe33dffad	0x6e82678f	0x50cb45b1	0xd5cc582b
-	0x5df4b1f5	0x6f4f0276	0xcd6aecb6	0x80c6602b
-	0xaf862a20	0x882518ae	0x69fbcf16	0xf3e38188
-	0xa7b35576	0xe40eb7b7	0x879a2088	0x55944f95
-	0xcf7672f2	0xc4541a5c	0x6e09ad3a	0x38075dfd
-	0x2ed6c693	0xc4fa0139	0x671c3821	0x038d5dc5
-	0x09793c52	0xb6a931be	0x453d79e9	0xecd6cd11
-	0x960f0fae	0x7649359f	0x19766e8f	0x4a7fb57d
-	0xb18746cb	0x8c3f492e	0xb91a220a	0xaa889e36
-	0x246cb452	0xa7f61e5f	0xf9fb9e07	0xef7c0d56
-	0x4f8d0024	0x082dd2a2	0xa8c091f1	0xd7466121
-	0x10c79d8a	0x3300740b	0x6d1f3780	0xf60f731c
-	0xf2d58803	0x6a80b882	0xd5d9c4fa	0x3dfc9be7
-	0x9dfe48fb	0xed7e7e88	0xcdd5dbdc	0x485b67d4
-	0xd19f715f	0xce7d6a99	0xed483597	0x2f0eb52b
-	0x7546c358	0x54f1cbcc	0x5df93879	0x79693708
-	0x8eba40f1	0x8f705e5c	0xd1154fc1	0x9f99ac65
-	0xb92d1d22	0x07c98e9a	0x21a14255	0x78c68738
-	0x7cd994da	0xbad78e73	0x463d5997	0x83a71109
-	0x53bb8986	0x15bd8dc5	0x7e1f1998	0xa8c5391b
-	0xc5abc962	0xd9a0bd54	0x48f64292	0x77410557
-	0x09db7193	0xf835577c	0xfd0f32fd	0x578d5fe4
-	0x198232a3	0x5e332aa4	0xce6b2647	0xeabc740e
-	0xf8e545ba	0xcd7d6c42	0x2776f043	0x3f0486c9
-	0xeea7d9b9	0x6773671d	0x08043447	0x290896a7
-	0xe5d05e2d	0x1701dd00	0xe2ac31a2	0xc7a96166
-	0xaff6d0c2	0xfd73837f	0x0bd95906	0xdbbbd03e
-	0x93406214	0x8e4827ef	0x67c7af4b	0x2e83eefb
-	0xac7857ea	0x6a3705ba	0x0e6694ad	0x5b7cf57b
-	0x12b302ab	0xe302c65a	0xb86a70e4	0x558c3c3b
-	0x516b9e0e	0x14a404ac	0xc2125bf6	0x7b004a59
-	0x65781699	0xb455f1c2	0x1f1f7b0c	0x800225a8
-	0x382ec77a	0x31f3d8ee	0xeedbcabd	0x6b95ea73
-	0x7a3a3f50	0x49b810d1	0xb682073c	0x36971f10
-	0x10eec5e1	0x9b9354cf	0x220dc62a	0x0f901007
-	0x204baa07	0x8b028c1e	0x7e4fff42	0x19123ff4
-	0x0219d4f0	0xfd355ae0	0x82e8c025	0x04daa19d
-	0x1d65eb84	0x282aa6ae	0x40dbee56	0x906b6b46
-	0xe1112280	0x031a9dcb	0x61dd8e8c	0x42504f64
-	0x1cb256d9	0x569448f3	0x9ed09cc2	0x52cffe5d
-	0xa0d21264	0xad756a66	0x42743067	0xbc6a7470
-	0x3950b8e6	0x62a4ec00	0x1743a299	0x659adbca
-	0x7206b852	0x156b6cf0	0xa54cca90	0xd4f789b8
-	0x177e7e86	0x6b19f13e	0xd7fadfd1	0x68ef1abc
-	0xbad802eb	0x3802a623	0x43b08974	0x23bc8939
-	0x8ee2bb67	0xbdc11c8e	0x2efbf4e3	0xc550bd4f
-	0xfb7e6923	0x9fd78d20	0x0238fc36	0xa733dd00
-	0x1ae532d2	0x83f4e497	0xca0f4cdd	0x3b204df2
-	0x0d5084f2	0x15da2f6a	0x904b1dc3	0x7418ce5e
-	0x28258fee	0xbc0292b7	0xf2002944	0x73720375
-	0x2486734c	0x1883172b	0xe1dda0b6	0x8e1ead82
-	0x18e47d65	0x9b8178a1	0x0251a0af	0x5a8577c3
-	0x1c5ce32f	0x0220633e	0xc90c9de8	0xe63cc5b7
-	0x7f334c91	0xfe0e70da	0x0af05ce6	0x8506f70d
-	0x52ee885c	0x1c723bd5	0xc547fa0b	0xeaf183de
-	0x5bf6e086	0x436d2b8e	0x3d7ad97e	0x9b766a06
-	0x021e0e79	0xdd17bae6	0x04607ea8	0xb8d174a6
-	0xc3b99816	0x9f2bf1fd	0x6521b1c9	0xc6373e8f
-	0x9c472d66	0xa71f624a	0x14af923d	0x52266735
-	0xa0a0bb3e	0xba8d52d2	0x54c78a14	0x4dd0708f
-	0x190c6c33	0xbfcc1963	0x3ed502c8	0x0766a192
-	0xe1724557	0x32271339	0x6078e163	0x8de0c570
-	0xd8e8dd17	0xce6b4b31	0xb341a175	0x8b8da109
-	0x557dbde6	0x4863ddc1	0xd345fd2d	0xbe39b49f
-	0x0b46caa9	0x572a2334	0x67d7e89e	0x658e947b
-	0x6afe994a	0x17bd769e	0x054b5949	0x850db30c
-	0x20ac6bb6	0x50480eb7	0xe06ebba0	0xacb7497f
-	0x1dadb5c5	0x4d33366e	0x8559d54a	0x7cce6ef5
-	0xfffed33f	0x7695b9c7	0xbec2d062	0x92a1c084
-	0xe0220148	0xfef08bee	0xc3ee1787	0xbe7151b6
-	0x86c8e888	0x4cae3d51	0xbeb8686a	0xa4b252b9
-	0x54d8cfd3	0x8d38b0a7	0x2f8051f8	0xeb3e0808
-	0x7bd6ef4a	0x6d3850d0	0x718b796e	0x20aa1cda
-	0x0a2ae34a	0x1f786b4d	0x1ef65ce3	0x5a710df0
-	0x618056a7	0x1863794c	0xb98ee235	0x9627fafe
-	0x48c9dc0d	0x33a09717	0xc985c1e1	0x0dcd0297
-	0xd8559f14	0x0925fff7	0x1ec6e43b	0xeabd0343
-	0xdf224c30	0x1560e2d0	0x11072a5e	0x5439abec
-	0x68539ad2	0x7e220044	0x8a1285a6	0x1728d4a5
-	0xf9d7cce1	0x6797757d	0x65c9101e	0x6e40134a
-	0x2a3bf252	0x5859d1c3	0xd42d7037	0xe519f182
-	0xa52ca09f	0xa4b8a207	0x3e2c5afa	0xa2dd1581
-	0xfc43c1a6	0xc10737bf	0xc3196027	0xdbae602c
-	0xa8b8bb9d	0xd092e4ae	0xd08b558f	0x41b0c1e1
-	0x6523934c	0x2c339d81	0x903f234e	0xb24cdff6
-	0x98e056ff	0x7f3d915a	0x87d1fa96	0xfbf87d09
-	0x9543241e	0x5d7df767	0x81082a30	0x206e5ca0
-	0x3c78dd55	0x3c4ef16f	0x0cdcda86	0x41b65308
-	0x04001fd9	0x51647a1b	0xd0eba6a6	0xea5b6d04
-	0xe6040387	0x0d8bb27e	0x68cf3432	0xd05a4c2d
-	0x23c1f2b6	0x17241b34	0xebb1ca9a	0xf37a448d
-	0xece67298	0x0487a8e5	0xfcb0bcef	0x31be2771
-	0x82bce53c	0x85b84892	0xdabc1c6e	0xfa2abcdd
-	0xd1df67c0	0x16f1ede8	0xff1a16b7	0x0d8c5570
-	0x51fbe82b	0x8bbb72cc	0x2329bada	0x3085b33c
-	0xb57804b1	0xb0e794b0	0x15c12782	0x607ef889
-	0x0f812dee	0xf4cd98ef	0xb952b6f0	0x5a58331d
-	0x5ec46323	0x125057ea	0x622c0ff6	0x883106d2
-	0xfb3dffea	0xdc3e0223	0xa97ab5da	0x654600ad
-	0x933167a6	0x374ed2a9	0x937eb718	0xd9501125
-	0x1ab096d8	0x7c9e0cbc	0xe4977ce0	0xc5f10f9d
-	0x34d150bb	0x964e8a96	0x45ca9ad2	0x4682d4cc
-	0x1a547f3f	0x48fca7f6	0xd7bcc4a6	0xd97d99ae
-	0xd8f0abc1	0x66cc1dc0	0x97db316e	0x8a382cab
-	0xbfbd6c74	0xa48d1b1c	0x2699542e	0xfd497691
-	0xface9d1f	0xb9efda89	0x4bbd1fc2	0x92f8afc1
-	0x43b37edd	0x6dde4632	0x3919ef3b	0x895378e1
-	0x87bef27b	0xf411bf33	0x656ba5fe	0x8b265339
-	0x50901749	0x3bde1f64	0xd6ca273f	0x896cbaf0
-	0x94122826	0x34ea9bf5	0x15d3043b	0xf332ff70
-	0x2b95d76e	0x57a79ba3	0x71c1f063	0xe71fc35b
-	0x8f07ee43	0x048ac612	0x65aac513	0x68ea6eb7
-	0xf730ded5	0x4402fb34	0x70ac795c	0x69800516
-	0xb1b869f3	0x6f4bbd00	0xe7447778	0xa36497f4
-	0x1c59ed09	0xb2992d4a	0x93c6a1d3	0x11d3ce10
-	0xdef0a673	0xe86e3d99	0xf1468e25	0xb272fd13
-	0xd407426f	0x95497062	0xcad1dae1	0x5a483a78
-	0x0bdb41a5	0x2899f32b	0xbb8bac96	0x5003c23b
-	0xf88ffbad	0xf4155bd2	0x4dea88df	0x5507bfac
-	0x86bd066f	0x7c993d88	0x89ad6efa	0x2dc99462
-	0x8d634a1d	0xebd312d7	0xfc8a8549	0x26f6cc24
-	0xdfc6c501	0x9615c1c4	0xa48293ef	0x52aa4e4d
-	0x7c1126b1	0xed10ce8f	0x39d15759	0xf6dd7f71
-	0x2f4d86f5	0x151da4d4	0xd9175dd4	0xb2d20142
-	0x20fe7518	0xf35752a8	0x37ae7efc	0xc210d83a
-	0x5d9ff559	0x33e91d21	0xd1c7714d	0xa98c7599
-	0x8ee50ccd	0xc747a3b1	0x9dbc5317	0xc25ae129
-	0x51b3647e	0x25aa4406	0x6e123b35	0xcc8fe12f
-	0xdf9c6d92	0xff1e6b44	0xc294d3cf	0x458dbe77
-	0x8176b64a	0x4daa895b	0x5ecc9d75	0x1b570965
-	0xd563bbb7	0x297b9784	0x4129fd5b	0x77beeb2d
-	0x82bab257	0xca55d798	0x4d413dfa	0x27214528
-	0x918d94a4	0xe9dc1881	0x17a00e62	0xff38fe70
-	0xf0578886	0x99fc567e	0x89728e9e	0x267a192e
-	0x5e16982a	0x5da1f959	0x3c407435	0x9c5cfe85
-	0xa7626913	0xb1145c57	0x174daaa8	0x0487ef1a
-	0x11d7b896	0xcd48cce8	0x464ceff1	0xbdc0f36b
-	0xffdc957b	0xb94233f9	0x61dd9f4b	0xfbc1fe7c
-	0x45f0195e	0xd7c92251	0x6c4ba5b1	0xc780a5a0
-	0xe8fc9220	0xa7ca21ed	0xa82eab05	0xd6050a60
-	0x68bf3f0e	0x50214ae8	0xb83e6b76	0xa435330c
-	0xefe62d27	0xd3b40484	0xe96a563c	0xc93296b2
-	0xd1531895	0x5db76e04	0x491b827a	0xf160fcf4
-	0x4b82737c	0x3c72de73	0x1996e649	0xd2d79c59
-	0xb1263519	0xb8660e24	0x4b07996d	0x71df252d
-	0x58f95a70	0x8618a823	0x94239726	0xd6d92a80
-	0xd8142a6b	0xc98c3175	0xfaa52b59	0xe91fdee1
-	0xd9a1fbff	0x8d63a59a	0xe0bd9077	0xbb1cddda
-	0xad57fea1	0x32af0614	0xea652e8d	0xa02ef7b3
-	0x07440720	0xbac50654	0x5e32309d	0x444a9d5b
-	0x9c5d9ff4	0x6b0ef745	0x248f1f75	0x7d87e2e8
-	0x27490681	0xfc2a7b49	0xd81d2e73	0x76b09294
-	0x4512b27e	0xcd72c2f1	0x41d3ba4f	0xc752688d
-	0xc22a2077	0x45a01ca2	0x82b5ba56	0x9f12c039
-	0x44cc1b0f	0xe8b8353d	0x0c26d80b	0xe54b917e
-	0x62df727e	0xfce091be	0x79ca5f3c	0xec222126
-	0x4df04d01	0xcd7566d0	0x839eb434	0x9b6d3415
-	0x61fda637	0x3549727b	0x44117109	0x9d1c3ed2
-	0x2c3cfce8	0x2e2acd9d	0x4ba9129d	0xbe14efef
-	0x5d07e000	0x2081f339	0x1daf0bc2	0x74d098c3
-	0x301e59a7	0xfd696b42	0xfc4d3387	0xa5c09d3c
-	0xf8b0e4d8	0xadd63e51	0x5815b319	0xec7e8516
-	0xc8d93178	0xdf1b9e1d	0x22107d46	0xa3a99acb
-	0xfffc3859	0xd00561d4	0xb383323f	0xf6b7033a
-	0x90f781a0	0xf5f2ce72	0x6eb3fdf3	0x8cc20a5b
-	0xc97c9c66	0x95135ade	0x24880471	0x9bb65b03
-	0x81b19c7f	0x700d0f5d	0xd13737b5	0x6607133b
-	0xfbe4e7d6	0x3c4f45fe	0xfd6782c1	0x93aa0e29
-	0x5e80ece2	0x16609c87	0x238ba834	0x1ddda4b4
-	0x6d07bef6	0x23422da6	0x034a0e64	0x9fbd2d4d
-	0x29f9bf71	0x009ca5a7	0xf483d433	0xcc5b600b
-	0x6bc292eb	0xbbec5d01	0x3e45ed47	0x1f19013c
-	0x9beb22ac	0xab5e821e	0xa1430d82	0xd88d6684
-	0xf8e70a20	0x4e267714	0x32740299	0xc87b9d0d
-	0x61e7c75a	0x967f007c	0xe1f93f4c	0x11a1c3a5
-	0xbbee7b5f	0xd1ef645f	0x141aba51	0x70694200
-	0x71945636	0xc9dde72f	0xc5955db8	0xdbef5230
-	0xbd17479b	0x53159bd5	0x0878bdc2	0x9fdd9d07
-	0xaf67a519	0xadca8377	0x13841851	0x97f464f6
-	0xea749381	0x47018b36	0x42cfffdb	0x2366f112
-	0xe280757d	0x7426dc87	0xcd5252bc	0xe5bdda7d
-	0xc9728a8e	0x8e08cd82	0x66797c08	0xe1600e06
-	0x149121b9	0xf9ea0e1b	0xc3da0d90	0xde18b684
-	0x0c568801	0x58e83138	0xfe3fe553	0xc52b4e60
-	0xb6afb01c	0x9154fba6	0xddabb2f2	0x018eaeac
-	0x7c9640d4	0x9c7c86dc	0x41b8d514	0x8bd27333
-	0xf07f842e	0xb75e7858	0x990187d3	0x316ef3a6
-	0xfaf22ada	0x95356100	0xd0ed3ad6	0x3d9951bd
-	0xd4aa1b22	0xf3a6ad11	0x797f6e48	0xb2428538
-	0x91466c20	0xf17569d0	0x62d5d1b3	0x5a3d69e4
-	0x6d869d97	0x82a84e5d	0xf6a45cdd	0x8781c19a
-	0x0dac70b8	0xe79a4712	0x4617b8c0	0x3167f846
-	0x9c6e7b77	0xc60b0e08	0xd85879c1	0x2be3a597
-	0x06a6daf1	0x80915697	0xa3452bde	0x9cfd11d6
-	0x69be41f8	0xebcadb24	0x315dcb53	0xc35f3e59
-	0xd5b2edf3	0x443859d5	0x7d54f6a5	0xdcdac118
-	0xe767ecbd	0xd017fb76	0xd0e7b4eb	0x8d9bb8f4
-	0xce7b7d9a	0x92c0b4a2	0xcd5d8e1b	0x6f83d592
-	0xc17f2b68	0x2cdab9c7	0xb6e70484	0xe5fe74c6
-	0xe87747d2	0x228d5a4e	0x9dde03e2	0x9a14ba34
-	0x471229ca	0x69be2353	0x74450c0a	0xd1eb650d
-	0x78501400	0x1c4f2372	0x1fa1b6fb	0xaae57238
-	0xd724663b	0x05f5c43f	0x402bc254	0x68877f3a
-	0x57e6c691	0x0a51ef53	0xb65a2733	0x57431f71
-	0xceb73088	0x03c761af	0xb4542581	0x23933fee
-	0x4d726fc8	0xe6474d89	0x4816a760	0x97f68d6e
-	0xb892a46f	0x1fffcbc0	0x63f9c6a2	0x19ec45f7
-	0xad0f5d1a	0xe1436104	0x02db0bbf	0xa88a4df2
-	0xca060341	0x7bef4581	0xbbfae170	0xedf98d3a
-	0xc3972d10	0xce08a7a5	0xf2554832	0xb22c4280
-	0xf51295a7	0xaafe76f2	0x0503afd6	0xadc0191f
-	0xf788a6a8	0x32dde44d	0x2e148322	0xe4f4dd86
-	0xa8012f5f	0x68950d8e	0x40ba9fb7	0xeff278cb
-	0xf1f29ebb	0x5f273270	0x54db6ab6	0x032c76d6
-	0x28b7a8ba	0xe06ee4ec	0x95b4c36f	0xf895a4bd
-	0x6e886a7b	0x29ca6362	0x5ab44a12	0x122b4b0b
-	0x77542b75	0x4254355b	0x8ba85616	0x78f02722
-	0xad2c32f4	0x7a8b56be	0xda66fe2b	0x1018c515
-	0x8e963b24	0x492cd4fa	0x8e8daa8b	0xbbf9a920
-	0x5e1c170b	0x5b55acbc	0x96a08ca9	0x87628e01
-	0x7daf9cde	0x402b7363	0x704db5b5	0x4ed3e581
-	0x0b76bc99	0xee629701	0x976cfef1	0x222eb820
-	0x1eae4155	0xce2c39a0	0xfc80e3ff	0x46604921
-	0xa6411e39	0xc64f34d4	0xc2506d0d	0x9175c98e
-	0x2b41e939	0x9f612788	0xe84717b2	0xdd5f3d18
-	0x011ccf8c	0xd47c6dbc	0xc42724e4	0x4ecdb867
-	0x88c2fc65	0x7146f321	0x426ce2d0	0x21874594
-	0x94752082	0xac96eef9	0xbfaa8f43	0x4b599929
-	0xc40c67df	0xc2f88319	0x6c13b780	0x0331ddf3
-	0x03141f93	0xc8792b1d	0xa5cbe506	0x68424a36
-	0x35fe7a9b	0xc42db001	0xa2c5e600	0x2e9f8f21
-	0x7733f912	0x24b163b0	0x71003270	0xe5a5c52a
-	0xf08c8455	0x9f6b0203	0xfa048b10	0xfb2ef899
-	0xe9b81eef	0xc5d91db3	0x604bdb10	0x30a2bab3
-	0xbf75341a	0x1609bb55	0xfe4d07ec	0x0ffabee5
-	0xbfb339e1	0xb3f43c0e	0x66cd4d8e	0x752b5a86
-	0x9908cfea	0x237d4b88	0x1e4c78d1	0x41914cb7
-	0xe2d72121	0x815cc67e	0xfbf32db4	0xd4ab50c3
-	0x5b8f8ca4	0xd7f0225d	0x75662558	0xe1586c50
-	0xb9add021	0x1475644f	0x7d4d1e0f	0xb078549d
-	0x64edd4ae	0xe9aa17b1	0xe03324aa	0xad30bdda
-	0x2f27b674	0xf65879fa	0x5b5d7360	0x75905386
-	0xc2ecd3f8	0x373566df	0xb7de23e1	0x91805774
-	0x86162380	0x449b798d	0xaaaa35b5	0x0c72c757
-	0xda4f445f	0xa83096b7	0x86002daf	0x7749832b
-	0xf3a61bab	0x5feb28a1	0x26ee7610	0x5a5c40b6
-	0x42c9ee14	0xc4dbb8b6	0x1f67936a	0xe1b56bbe
-	0xe027f6b9	0xe63fb059	0xc88bc732	0x3111de49
-	0x35c2305a	0xcbf91704	0xbd792b65	0x36de53d2
-	0xe2de429e	0xb90aad73	0xa9f473a4	0xca054a43
-	0xa984faa3	0xe8ddfb62	0xc36104c8	0x95e7e647
-	0x17437e84	0xa20c074f	0xb5609b79	0x468c3b7b
-	0xc0bc3e20	0x368c94fa	0x04ff3519	0x60b01b2e
-	0x4a3ad0b2	0x4d8b4633	0xb1dc5e67	0x7e14c0be
-	0x58a6cde6	0xc88980d9	0xb4ca1c86	0xe17c13bc
-	0x3efb7728	0xadecba18	0x369ab25f	0xcda74fec
-	0xe9c4c6aa	0x55590211	0xbe191ec5	0xed8ffbcd
-	0xea3bd84f	0xe1fde7c5	0x5c788a9f	0x31a7b858
-	0xd65315a8	0x62be6ed6	0x04b8be91	0x73548a2f
-	0x93f9cbe6	0xcae8695c	0xea678c66	0x618251bf
-	0xbe8920fc	0xf4f76833	0x15ad8be7	0x5ccf9cb0
-	0x8d6a4fb9	0xe1a946c0	0x00fe7631	0x6abf0c2a
-	0x72fbb39d	0x72bd5bac	0x7d679c95	0xaa5ccef7
-	0x6df60938	0x9f08de64	0xb13afd73	0x61e2cc19
-	0x31485e10	0x2e125f53	0x74021ab6	0x43fd53f4
-	0xe506757a	0x454bd201	0x84947916	0xc89e453b
-	0xa92324cd	0x3667608a	0x28e2645f	0x17e1f1ad
-	0xa300d261	0xc9662fd3	0x987795f5	0xad6c0302
-	0x55d47cc3	0xe96259cd	0x0d67ce7d	0x07bccb37
-	0xf43d61a5	0xbd7131a5	0x686bdc7f	0xd570d5e4
-	0x9ff9331a	0xac9d1d6e	0xa1702a68	0x4a5775b9
-	0xa5624641	0xf65bd241	0x2ac16f90	0xe3413b5a
-	0x17ffa019	0x9d46dc7a	0x2a3081b6	0x857ce29e
-	0xe6640ac4	0x6445b538	0xad3d7e1c	0x9b79c366
-	0xf462361f	0xd1097ef6	0xca1c68f6	0xb5f30167
-	0xc14a23d8	0xc10dcd22	0x2a2fc332	0xfb253533
-	0x65fdf0b5	0x404b7ad8	0xa9ba6f4d	0xaba569c0
-	0xbaa52473	0x0e4627a8	0xc5f59463	0x362e6c4e
-	0x4b2a486d	0x0259c34b	0x28c473f1	0x503bb776
-	0xc5c0c537	0xa8b225c1	0xeea3c262	0x576dd495
-	0x571ada41	0x9f7cd0c7	0xd7496acd	0x05feea00
-	0x41201b9e	0xc77a94fc	0xe9bbcdcb	0x57b23f11
-	0x0804834e	0xd03b6bc7	0x01010b7e	0x1398ab11
-	0x16c14655	0x3c6e5e32	0x420bcbd9	0x8047a032
-	0xf70c4e5e	0x2a3e76ac	0xedd3223c	0xbbba8d71
-	0xba2a9916	0x1b83f930	0x4c93f25b	0x79731cc9
-	0x77925eaa	0xb2fee6dd	0x01f12a1b	0xd797d09f
-	0x1d63619b	0x2b04daaf	0xcaa55fcd	0xc4628c52
-	0x930f5701	0x0293b2d8	0x00e82920	0x3c4f3f60
-	0x6c0990ea	0xec07864f	0xfd650432	0x5bdb68df
-	0x9d138863	0x2a06928c	0xe0f69d3e	0x5310dae5
-	0x5bd2c0a7	0x775d764f	0xd8aadd14	0x20ba7850
-	0x358aabd2	0x192ce2f0	0xfe029fcb	0x9a787089
-	0x032bd81a	0x2033745b	0x11b36de7	0x38e63443
-	0x26a6a138	0xfe1b4cf0	0x8e8c2e54	0xd8d68982
-	0x1f8bfd73	0x11132e4d	0x217497b3	0xa882ae2a
-	0x895350e6	0x58042447	0x027e3513	0x9b23ecfd
-	0x0368bfc8	0x1f2bb5be	0xe81d1738	0x69176a5d
-	0xb4e0531d	0xc899b145	0x9fd09aef	0xabf6b854
-	0x2f1856dc	0x4186e028	0x02aab53b	0x0231c01f
-	0x543d0d94	0xbc207922	0xef61da69	0xe1056724
-	0x67fd8072	0xc98426e2	0xc7635142	0xff184885
-	0x653f91f3	0x1ab5cd1d	0x133df7d9	0x67b35000
-	0xb5880c56	0x21e4c4b3	0x6773270c	0x1c30a75d
-	0x360b8cbd	0x0efa143e	0x025c298e	0x8bea4b71
-	0x903465e9	0x99521cf4	0x2e1857e7	0x13266774
-	0x72f6d2f6	0x36a1a4fc	0xf0e38e70	0xc9d613d7
-	0x765b045c	0x28ea90e7	0x99766fb3	0xcdb93ca8
-	0x4ef82ae9	0xfa083dbb	0x280d6bc6	0x5fa6f9f4
-	0x8232c95e	0xe899ae64	0x9757bcb7	0x7b9a3fbf
-	0x7ee59763	0x707c1e8f	0xb09b26cf	0x39b130f4
-	0x57b13cca	0x9431c3bc	0x03074f78	0x77108240
-	0x2243cf2e	0x79f1c09b	0x2d7051d7	0x1e896e0e
-	0xfca3c98a	0x033f9d17	0x8a84fa5f	0x54ef6d59
-	0xea4f038d	0x37de0f3a	0x290fdf6d	0x87a99d3f
-	0x03539027	0x423a6a72	0x1751d4ef	0x3307e618
-	0xff81f836	0xeff8f63b	0x5fd7f014	0x5d2a7e84
-	0x9bb1c22a	0xd90f6902	0x53594d40	0x2a06777c
-	0xbfb045d9	0x3a994642	0x5d3bb1c9	0x92ebe0c2
-	0x1351d163	0x1d164e51	0x646facf6	0x5a09577c
-	0x1d67f8e2	0x5857aedf	0x4325f877	0x40b104d9
-	0x417b2244	0x944a7154	0x46887db2	0x8e5c72f6
-	0xb1e4105d	0xe23955a6	0x32c458f7	0xc5b0adfc
-	0x45b48308	0xccde9154	0xa84cfc72	0xc4f67710
-	0x19a5d6c9	0x18feea83	0xf731b3f5	0xd26e63c9
-	0x3869ef48	0x70b962d6	0x5f2b4ba3	0x5dd5a9c3
-	0x1efc97a6	0x09be830d	0x791d72d3	0x53f2948a
-	0xf5bdc706	0xa5b6aeb0	0x6c35db0e	0xc312c33b
-	0x6dca7a95	0x9f890aae	0x75308dfd	0x7de2239b
-	0xf530420c	0xe085f9b7	0x2d48c359	0xa8d1fcef
-	0xcb3f9669	0xdf491f38	0xc59ffdd0	0x995cda92
-	0xdef37f3b	0xe056b574	0x676eafd4	0xd4bd9336
-	0xda3ada02	0x290cf756	0x991efdaf	0x2f70baa2
-	0x515ced1a	0xaa0fa199	0x77f09ee0	0xafc3d840
-	0x79e5ada0	0x7900a254	0x4ca65cb7	0xb3eaba8f
-	0x98cd17e0	0xe179d477	0xe80d2f39	0xd89f3b4c
-	0x8d3ca0dd	0xd1d87ab1	0xf9368d54	0xe885ded8
-	0xd500c7f7	0x04910374	0x7c6467be	0x5ad058ce
-	0x5f8885b8	0x08a4a3c9	0x90583a94	0x369f4c36
-	0xafbd90a9	0x6eec8300	0x1fd17777	0xaa8ba562
-	0x24531969	0x64eae352	0x6f7e72c5	0xca5e2247
-	0xee11333d	0x4e96b233	0xcc9c45db	0x377d9b3b
-	0xac17897f	0x8d4f2cf7	0x03786608	0x2ed70cb9
-	0xabb521fc	0x27ae8324	0x99fedf05	0xfa60f2f4
-	0x60fe2470	0xd9994193	0xce4a1f0c	0xdf803250
-	0x7773e538	0xe3461726	0x8f1fb31a	0xe20b4ba0
-	0x247a6bd0	0x33f33c29	0x0534675d	0x9df47ebd
-	0xcb86d416	0xfca6bde0	0xc2113e28	0xac64d376
-	0xd34923e0	0x128f937c	0xc74b76b6	0xb653872c
-	0x05c78e23	0x482ece1a	0x17cd4da8	0x460f5a20
-	0xa9a3676e	0x0776830a	0x9c5764a5	0x7c0bf0f2
-	0xe193d4be	0x31b71120	0x4beed8fe	0x8426bc77
-	0x9f665f9d	0x4e2b00be	0x2dd365af	0x015f5889
-	0x92bd288b	0x4bda3b7a	0xeb2b0605	0xaadc6a84
-	0xf715172f	0x1b0fdedf	0x17ccd242	0xd511eab2
-	0x75829b1c	0x0f5861b7	0x229338cb	0xcad5ac0d
-	0x95ed8bb9	0xe719c62b	0x2e50c781	0x40492cc9
-	0x7ac3e8c2	0x4881bef1	0x8359b0a8	0xd0a8713e
-	0x3808db04	0x847e12f9	0xd28ee5b2	0xc77f7a81
-	0x2e89e5ae	0x95296641	0x55f44a6a	0x22c16d11
-	0x1fa9d5ec	0x3b131a56	0x6b113976	0x057616a9
-	0xf4813132	0x003fbe23	0x082a9ff4	0xd0db4d18
-	0x84be1702	0xc9c51278	0x9f5bc62e	0x5691be5d
-	0xc12f7c79	0xa84f8dc9	0xa9b2b8db	0x0ab996e3
-	0xd25a2195	0x91584ae2	0x11e0a407	0x9faf14ef
-	0x7ecf8b2d	0x64d1b392	0x8292b54e	0xaec7c7d8
-	0xedf1eec6	0x9164a0a8	0x16132244	0x07077758
-	0x32f53095	0x8036d28b	0x5534fa23	0x66869c3f
-	0x3a503595	0x87706388	0x315540f8	0x5348f0c9
-	0xfbe7451a	0x491d7c96	0xa70ad473	0x5d7975c1
-	0xa51c99b0	0xdc0320d8	0x259a0935	0xf15dee76
-	0xb080d4bc	0x1d8611f7	0x64b6c12d	0x115bb158
-	0x1ae6f885	0x9b7bddbb	0x74107ba0	0x5ec2433f
-	0xc05198b8	0x4e3921cc	0xf866e4ee	0xdf4e5b52
-	0x93dc0bfc	0x9f5957eb	0xffebb962	0xb2845803
-	0xf16acbdf	0xda0923e7	0x2b7d8663	0xeef7ea5e
-	0x5c468035	0x1bf5eeb4	0xcf04aad0	0xa898340b
-	0x58f32310	0x6502901b	0x151e45a6	0x4e0a8176
-	0x312d5e40	0xb0a82dd9	0x7461f194	0x5d955cc7
-	0xbc26c368	0x26cc45a5	0xfff346fb	0xcdbdad82
-	0x1f0da6e7	0x6800be4d	0x931a3413	0xd471a14a
-	0x773ade46	0x525f8a29	0x416f7b22	0x75c2b0cd
-	0x5abe1934	0xbb87502d	0xb1568281	0x95c1abf6
-	0x491971cc	0xbac11423	0x0daf5cfb	0xb5e37509
-	0x2eb36341	0x1784cff3	0xdcebc5df	0xdb10122f
-	0xbbed7029	0xb7b66506	0x2b732807	0xb5524662
-	0x37c211d4	0x0730df05	0xe09e9822	0xd6910951
-	0xc6ed46f2	0xfc7d7cd6	0x8d6af74d	0x4697b13d
-	0x7959b678	0x9c67c19e	0x96686e89	0x7f973e98
-	0xe5759786	0x42ba4801	0x05416f70	0x87a85c5e
-	0x8f21af39	0xc64ce827	0xf658f857	0x3b75a282
-	0xf6813344	0x0e9adb2c	0x46ca59b3	0x2f2c4fd5
-	0x1a7ee3ef	0x1e3202ce	0xc4135b57	0x22792d11
-	0xe399a044	0x9453c580	0x639da579	0x80239655
-	0xb1b68953	0xbd677cce	0x9163a0fd	0x766c5b7e
-	0x46ed281d	0x99ec91f2	0x7db3499c	0xbf2b9793
-	0xb111887d	0x3906e075	0x9e211f1c	0x16f15768
-	0xd27474c3	0x8813b27a	0x3393ce5a	0xe73aeee6
-	0xfe056806	0xfe4bf0fa	0xe106529b	0x317d9099
-	0xd2ad43c4	0xbd618f1f	0x77d8e13f	0xd4c10bc0
-	0x30a335fe	0xd7a4b251	0x84c67582	0x1bc0723e
-	0x7a1cded2	0xf6664fce	0x2bd8c844	0x967cc741
-	0x8cb6bf8e	0xb8c49dd9	0xc167221d	0x5c65b9b7
-	0x1f32b243	0x5729b02f	0x76f22a55	0x22ef22f7
-	0xabcde168	0x273b0513	0xb8cc1b47	0xf0e378e7
-	0xc3e189b3	0x344090c4	0x3cac2fc3	0x2a06749a
-	0xb026617d	0x26bbe774	0xb15d08d3	0x6b29e7ed
-	0x34b5145f	0x740f6f69	0x7edb95a3	0xf55df95f
-	0x25061c1e	0x45192d2e	0xdef6bb9a	0x5538188a
-	0x2f7ff744	0x6592e57e	0xdfc302eb	0x8564f70a
-	0x81f22fc6	0x1ed3f7b7	0x3eb74e98	0x84ff649b
-	0x40535223	0xa81996a5	0xb30b0b97	0x9ca701de
-	0x45bd91f2	0x07e94e32	0xb2f60f7f	0xc3d68aec
-	0x2296450f	0x31567179	0x5fa15060	0x6ade7193
-	0x7ca6e320	0xb231f34c	0x1e392751	0x3fb50014
-	0xff632467	0xff33f75b	0x65f2dcdf	0xfa464ff7
-	0x1ffd17ab	0x34c38154	0x72906efc	0x2f649bd5
-	0x5349c835	0x6c83e7da	0x9e0ff921	0xf2ad6dd4
-	0x5afa8581	0x2d6deedc	0xf582ce84	0xda7ddfa8
-	0x6485db26	0x874585e9	0x13bbb0a1	0x4283bb8d
-	0x1648cc58	0x69fae5da	0xa5d7bc2c	0xd7fce256
-	0xc2e25ab7	0x7ec604af	0x1efde306	0x36422ec5
-	0x78e9bd5d	0xbfa63459	0x052efdbd	0xfbc9d2eb
-	0xd8b729ee	0x888dfd1b	0xb64a687f	0x9ebd05b2
-	0x622c28ed	0x3801fff8	0x476285e1	0x262e5f3d
-	0xd6ba77c4	0x8d5663fe	0x4b9bb3c5	0x1909dfb2
-	0x40db7079	0x2799a10d	0x1e2e55a7	0xe597551f
-	0x4d38f913	0x972b1b35	0x92f77eb6	0xb2dcdb5e
-	0xe275428e	0x0f136b53	0x321b55ba	0x70f7edf1
-	0xc41fe047	0x332e9ff5	0x3c372115	0x2ea1c88d
-	0x3ea09444	0xe93066a0	0x666670f5	0xee9553d0
-	0xa817ee82	0xde3fd981	0xf6c5b2b7	0xe88e3857
-	0xec60b610	0x4b0e1af7	0xceaa144f	0x0a8f8703
-	0xd7969cd7	0x0a946a3a	0xc6f77ae4	0x3805f71d
-	0xd5d56360	0xbee37cf5	0xfa524a3b	0x68ba0662
-	0xdf153cee	0x5954f21a	0x05aedb31	0x340e4963
-	0x129115db	0x271db9a2	0x70984fa6	0x7daf0407
-	0x5fcd11d1	0x750f56c1	0xf1a93401	0x3a3aca1a
-	0x8a6d152e	0x9c65e58d	0xf0afd845	0x3abef6ea
-	0xe6e1ff7e	0xf8407d49	0x45dea271	0x545631ca
-	0x73fad7df	0x21e60e47	0x3bd83fd5	0x12b4394e
-	0xba4731b1	0x786279a0	0x97c6d6ab	0x2591deb2
-	0x4b33bf75	0x772fb5bf	0xe9060fd5	0x6a752986
-	0xdf3090d4	0x9de70555	0x471c2e4d	0x5305f077
-	0xf2bdabad	0x2a4ed093	0x36e029a8	0x17b7a5b1
-	0xce75a688	0x8377b839	0x731fa872	0x63f45ed1
-	0x010bdd8c	0x4366cba1	0xd899b1b2	0x839a8a34
-	0x4914176e	0x58fec42f	0xb3ecd171	0xa88b5247
-	0xbfecbafb	0x65962301	0x7b5a7822	0x08b1056f
-	0x6f0cf6b5	0x5dbe0084	0x3280b172	0xc77913e4
-	0xa298f67e	0x2131f5c2	0xb9b9b501	0x7f30b7ef
-	0x55d8cdb6	0x3b0c0dde	0xbf9a5cb6	0x50ba39ab
-	0x0741872a	0x69217ea4	0xad4b12ca	0x14dd5da0
-	0x5d220b6b	0x9d0356b5	0x9608d36a	0xdef765ca
-	0x7d55819c	0xb57ca102	0x9f2a2c76	0x5efc9c7d
-	0x42952b33	0xc8e2749b	0x2eff7d6b	0x211caa64
-	0xec846e0c	0xf3119325	0x31bf7f1d	0x984fadb5
-	0x36670140	0x6419ae9a	0x1c206656	0x86cb7d35
-	0xbd323508	0x5f970165	0x21777792	0xc8808541
-	0xecba85e0	0x0b4b3240	0xa70d8609	0xc68913f2
-	0x67415bba	0x26af0069	0x81974b27	0x92066952
-	0x5f6aa2e7	0x0dfa50b9	0xc1e65cad	0xb93b9d66
-	0xad6c8ff8	0x8e885310	0x5f77e1eb	0x2dccb750
-	0x8f18f33a	0x6ad45207	0x921285f5	0xf3d2d3ab
-	0x1be2996f	0x9bc30897	0xc7c85614	0xce88b0ca
-	0x55a5fec7	0x0570e871	0x50cd5f3b	0xb723a9a4
-	0x8c2f6fd8	0x3a0bfcc5	0x0b75181c	0xe595e483
-	0x063a7f01	0x16984414	0x9c74253c	0xd9627dee
-	0x0b8aa93f	0xef9f3c7e	0x186719dd	0xb0311955
-	0x4ffcf417	0x519b631c	0x295cb456	0x58494234
-	0x81ebafc8	0x02002fdc	0xb28044e7	0x2682e878
-	0xb86f281b	0x108f9c77	0x99368ca5	0x24887533
-	0x37676f0e	0x71230faf	0x8e689144	0x81bbe972
-	0xc8dbab68	0xca5a3ed9	0x878d622c	0x05217a5b
-	0x7ce7e849	0x0416578f	0xc43b026a	0x86abc8bd
-	0xf0fdc5dd	0x1684665c	0xf167d783	0x00d58f21
-	0xb4929559	0x70572ce4	0xbfe6985c	0x051bdcce
-	0xa9307ffe	0x2fa9902c	0xd8f76dbc	0x6dcd4744
-	0xecb46877	0x18ac0a40	0x6f8a8064	0x66dff5e2
-	0xa55d991a	0xfcd7e70b	0xad9c7fd7	0xb77415a6
-	0x761134a9	0xa76e4079	0xe9ca8a5f	0xdb627ec1
-	0x328cd5a8	0xc3f378c6	0x7f5ae9a2	0x5a144e26
-	0xc4b778f8	0x1910215f	0x1d29a078	0x728c7575
-	0xc2017bc9	0x201a0601	0xea1e939b	0x7ed85f43
-	0x92893ace	0xb97613d5	0xa3e47eb1	0xaea2a6b7
-	0x45b4de8e	0x864e3d12	0x300eb84b	0x57246fa1
-	0xf9e50600	0xc5fb68af	0xff700271	0x4ecfe6df
-	0x195f3f4e	0x9bdcfa8b	0x1bcca506	0x0ee96e1e
-	0x4d722003	0xe6ffe15a	0xc3a392d5	0xedc4ea2f
-	0x1cc2bc4e	0xf133ded3	0x584bcee5	0x63e54048
-	0x34f57fa2	0xe606b846	0x82dece0c	0x7bc24217
-	0xf45b9ac3	0xd9949991	0xbc262aef	0x7949bbec
-	0xf37e0563	0x716bdca0	0xef533f5b	0xfa53b4e0
-	0x97365a61	0xbf4cd291	0xc69c9c3f	0xb5ddd420
-	0x92a65067	0x4a63f3ce	0xf53104a3	0x0053fca8
-	0xb8f972b1	0x7eb74704	0x2bc2ef35	0x491b520f
-	0x80f67bbe	0xd36fc91a	0x8babbc98	0xdd3aa4a7
-	0x1005ace4	0xafe0a165	0x921ee005	0x9d05e888
-	0x4e7913ee	0x43690cb8	0x634c75a1	0xf2ca1d08
-	0x6f453485	0x1a62b5f4	0x692608a8	0x76837c9a
-	0x222f6cb2	0xbc883372	0xc785ebf7	0x21b16a27
-	0x5ad7860b	0xd5fec2ec	0xa573aead	0x9c0bd90b
-	0xec3b5d8d	0x393a1263	0xd0cddd05	0x08477829
-	0xd4bb3080	0xd1580e80	0x614e8dae	0x7e789a32
-	0x273b2589	0xe5368d97	0x8db1b602	0xbd06492d
-	0x6760aca0	0xee176a78	0xce44021c	0x4d35c720
-	0xcc3d8185	0x752005a2	0xffdb4703	0xf01771b1
-	0xfccc8abf	0xadca3bbc	0x2c2a4739	0x970d0fb8
-	0xa829ca54	0xc4301da7	0xa56d3181	0x24a95701
-	0xb760d1ee	0xea87f071	0xfabc32df	0x465f142e
-	0xe0998f0c	0x6923edf6	0x3a1debda	0x3e88908d
-	0x7069f55a	0x0cd61367	0x1218e044	0x99713258
-	0xbb60c477	0xe3997857	0xc4e9ca48	0x4be6b283
-	0x1bde70e0	0xb0f3e15d	0x40cfb11c	0xbb9e0879
-	0xc4c732e7	0x2aa169d3	0xa2bff233	0xaa50e35c
-	0x2d0989e3	0x6f39a59d	0x7a7b69c5	0xe66152bb
-	0x69c74ec0	0x46ea7bc3	0x59c93af6	0x0a036f99
-	0x95698244	0xe0ca1af8	0x3565483c	0x8abcce28
-	0x6b322770	0x188e97b6	0x77874604	0x93298d36
-	0xbc4a0f5e	0xbf367940	0xf69906ef	0xf2b5975b
-	0x5968ec40	0xd0e75276	0xdf02b089	0x60b72248
-	0x32de1e9a	0xe52bb0f9	0xf4b33702	0x87b4cd47
-	0x31c86ac5	0x77106507	0x20ec46fd	0x5086dc0a
-	0xadce33fc	0x898ee47a	0x3c6f8af9	0xb4a26000
-	0x8f11d65b	0xf83d2284	0xe512bf22	0x24a7d8af
-	0x12b194cd	0xa530f50a	0x1f64f621	0x6160f047
-	0x8f223c99	0xc7e0809f	0x99312a95	0x5c729b2b
-	0x4af6e5b7	0x8c6e5da4	0x93a07403	0x89fb2a5d
-	0xeb347cfb	0x0d127850	0xc3278db5	0x456e3472
-	0x731c2b96	0x841ed8d1	0x5ed8671a	0x16814226
-	0x4cc3932a	0x556b1403	0xc8547260	0x52340a36
-	0x78b8243c	0x9ce3ac1e	0x997c64d4	0x25812f0d
-	0x5cd3b82f	0xaefcd02b	0xda85628a	0x3b9e3e2d
-	0x4780e91b	0xbb265ae9	0x4667a62e	0x7fde4743
-	0xae2d2c8a	0xbdf272d6	0x490e5bf1	0x8f764531
-	0x59a8ca61	0xc39751a0	0x9777eddb	0xc89da92e
-	0xfd46b968	0xd5383421	0x916ced6c	0x9fc14c5e
-	0x91ff992e	0xd59cd577	0xf5cdda19	0x99ed4f29
-	0xea30d84d	0x868bb72d	0xcd3e19d8	0xefba277e
-	0x9b895f2b	0xb67570ae	0x7b963bfb	0xb7f59d33
-	0xc82c0da2	0x713c0ebc	0xd2e19b6d	0xfdd7cb4f
-	0x0442a88d	0x58e2e7e8	0x7b179f2b	0x12013442
-	0xbbd1c2d1	0xc4e7d279	0xddb4cd95	0x18a254ad
-	0xb2876346	0x4bdca7ab	0x94dc9778	0xb648e703
-	0xeed00eb6	0xab02dd6b	0x3e25115d	0x45cedb33
-	0x906c2403	0x457849ca	0xfea6f2d9	0x252fb56e
-	0x2bbe39b4	0xa35c94e8	0x04952551	0xad733a12
-	0x40bf3982	0x30cb3742	0xd6c149da	0xb6d29f20
-	0x9df8b8eb	0x706065f5	0xfa915b7f	0xd2bdc0ca
-	0x0a4c462a	0x288ef8ee	0x2fa27cdb	0xea11b73f
-	0x5e909f42	0x06d764f5	0x1e2deaaa	0xfae5dbe8
-	0x0ec720a8	0x8fd675b6	0x58ee95de	0x19fd1ca4
-	0x4308d173	0x1884c251	0x56ffe45e	0x961c6bdc
-	0x44582512	0xb76a958a	0x12cdc33f	0xdee5c784
-	0x8dbbe9fb	0xe327f532	0xefb271ca	0xedecdca5
-	0x798e60f3	0xcf2d194a	0xee275fd0	0xd8fe6f12
-	0x30ce7bd8	0x3e17e29e	0x351ec4bf	0xe23692ac
-	0x0bb60ab1	0x60818dc2	0xdfaea801	0x1afe161f
-	0x72fbcb53	0x9382e661	0x56054fdf	0xe6261b4b
-	0x97e746c7	0x6257411b	0xf0bbac9d	0x8fd6478e
-	0x203e690f	0x9758da43	0xef6ede77	0xe85fc9e5
-	0x8e5315ed	0x479c6f9a	0xeceaa8b8	0x4f626f85
-	0xe79c2ead	0x14e97f8c	0x2bb51ff0	0x6b733645
-	0x9e578a09	0xcf424ddc	0xb315bb19	0xc4833717
-	0x3890ca82	0xf00aa52d	0x9e652f98	0x87ea3177
-	0x7acc6baa	0x531c5eb4	0x6a85b1f5	0x7b1c0192
-	0x0b32c8d7	0x735c5791	0x86c1ebc4	0xa4361511
-	0x0c7bce26	0x1357809c	0xa382b877	0xa4f9a0ed
-	0xca30e907	0x277d3c65	0xec0bba64	0xf5169aa9
-	0xb8a1305b	0xbb4059a3	0xa44d32ca	0x76b0141b
-	0x7bacc1c2	0x51273c1c	0xf8f4d7af	0x0278678d
-	0x04d36367	0x38ed7b1e	0x8a45327a	0xdd19324f
-	0x36a5952f	0x97661f43	0xe2671856	0x1eb34493
-	0x8708de21	0x080f9e7d	0x070d13a0	0x2c54a64f
-	0x86ef2751	0xf83a87e8	0xf61841fa	0x0ade1426
-	0xe1cca086	0x96a9a439	0x648f53e0	0x378a6cf4
-	0x894a3c7d	0x9bf1031a	0x2f0affd0	0x4688048d
-	0xec159b64	0x28b103ac	0x462767a5	0x278ac30f
-	0x3e5bf100	0xdd860ac2	0x384e9dea	0x55abe65b
-	0xbc95d098	0x905277bd	0x8b47e264	0xf4cc82c5
-	0x8f06e7ef	0xf2fb2364	0x13f70c45	0xc5eb083c
-	0x6c4ee92e	0xb2f7719c	0x19883212	0x611f22c8
-	0x8c742ec0	0x1550089f	0xc6c5933d	0x1a6aab8a
-	0x27ac73c0	0x4b8be65d	0x25c17a0f	0xd1ee7238
-	0x54a47bdf	0x9bf2d8e7	0x223873f1	0xb0825f98
-	0x6263a6a5	0x6e732bde	0xcb2460bc	0x195b6758
-	0x74eab2c0	0x10509c33	0xad5153c2	0xa9c77d09
-	0x5581bc9e	0xe85a2906	0x19ecd606	0x22d04481
-	0x2acc285c	0x4b01bec7	0x7946efc4	0x3fcc4f9b
-	0x7711e2ba	0x769501b9	0x565ed3a5	0xa6a2e0c2
-	0x2fc9f212	0x1da1dc7f	0x1e354a51	0x42f070bf
-	0x96f603fe	0xa11ea899	0xefa65c44	0x309f3b3d
-	0xa4e7de23	0x0fc0ecf0	0xed135d01	0x11526284
-	0xe1535798	0x46236948	0xbbf375f3	0x33d03953
-	0x057340ac	0x1f8d08bd	0xd3e19b4a	0xd1a074e8
-	0xe8f7b3c1	0x81f4e7cc	0x7efb3ce4	0x2d7b8dfe
-	0xc35c1b7d	0xa981b243	0x56dc3df2	0x7b0cdd73
-	0xba20923b	0xe4469620	0x9999a05a	0xd558e6c9
-	0x1b2a6e34	0x1a03ad40	0xead427a9	0xdfbdf1ea
-	0xe9b9c758	0xe1ce3e74	0x2ee3013c	0x37fde647
-	0x7528f451	0xdb169663	0xc1595963	0x487703e0
-	0x649824fc	0xf4e557c4	0x26ff0cfb	0xa6c61495
-	0xbf6ff8a8	0x1e936c2f	0x28170318	0x16623623
-	0x7cf43aa9	0xcf44b9bd	0xee05bbe9	0xbc364396
-	0xfac9c35a	0x70664227	0x4200bc74	0xc847c1f3
-	0x393b52cf	0x67df2a37	0x24828663	0x85c64437
-	0x0ca91fc4	0xbbab8588	0x170d40ec	0x6a5270d7
-	0xd873cb99	0xc461e41e	0x68fb5dcb	0x175808d3
-	0xb3c75d6c	0x5f8659a3	0x164af2cd	0x491ed225
-	0x21b774d4	0xfc5f44e0	0x5a761165	0x8394b784
-	0xa3625993	0x23db8229	0x18adfc19	0x7a86dcaa
-	0x3759a419	0x8236b6a0	0x866eb76b	0x40e3936d
-	0xa327f573	0x0793a949	0x5511fbac	0x7aa8017a
-	0x869d2433	0x9fb80368	0xd9b8d14a	0x725f0a17
-	0x50ec0c4d	0xeb8bd3bb	0x6785d7c0	0x9882836f
-	0x0c164e65	0xa7ff708a	0x3f4b7ded	0x160237e4
-	0xfa551105	0x7dfeb41d	0xf60157d5	0xf863bb00
-	0x23d96b49	0xc8b80eea	0xd395a7bb	0xa6cb0b99
-	0xdae2d53e	0x374d5699	0xede8a731	0x64e2eb82
-	0x3aaffc9a	0x03da3d18	0x775890e8	0x3842a94c
-	0x863c3914	0x4cf8cc03	0xc40d3d2c	0xb5514333
-	0x1254c457	0xae791759	0x7eebf7c4	0xcaac9331
-	0xb3f9a144	0xf9430aa4	0xc241038c	0x7b481099
-	0x6ffaf560	0x504946d2	0x5ad1fb41	0x4c4ed169
-	0x1331c934	0xfc02efaa	0x519b65e5	0xa2eb152b
-	0xe3b78626	0xf6cc1ce2	0xaba6d9c6	0x6c117767
-	0x3ba1a970	0xab320fb2	0xa17ae6c9	0x07f8b830
-	0x1752f87c	0xcadd1616	0x81229b18	0xb8f1c91b
-	0xf62e10f9	0x40fb1a82	0x6feed0ca	0x375b3f31
-	0xcc951ee2	0xdbbc0a84	0xc3caf9d9	0x51e4f7e2
-	0x6c2cc2da	0x86994a97	0x58516036	0xa680e1ff
-	0x83255438	0xe304daf0	0xabf95c4b	0xeeecb868
-	0xf258ca56	0xc63b1f45	0xe4637c07	0x4bd8052a
-	0x01515dbd	0xa3d3dca6	0x79565fed	0x0427abda
-	0xeb640f00	0x4f34d441	0x135af3a0	0xad86ce4d
-	0x83daca30	0xd9ae59ab	0xad9edd9a	0xbb18a84d
-	0x9163b7ae	0x68c45613	0x4eeb7297	0x12c0aa50
-	0x0003968c	0xb872a623	0xa39b33c0	0x4c934155
-	0x658bcce4	0xfa7c8c07	0x062681c6	0xd091dce3
-	0x6b421cf0	0x726aae92	0x623e4f88	0xd74b50b4
-	0x0a6410e7	0xe6158980	0x2956f74c	0x5e18c87c
-	0x6fd6e24d	0x8afdf654	0x928a859a	0x55edce30
-	0x63a859ef	0x4b82ee8c	0x6eda25a4	0xf8b32d44
-	0xdc47b7f0	0x5ff1c6d3	0x8ec85752	0xfbcddc99
-	0x86b90e33	0xe9fe679e	0xf6933cee	0x7054cf99
-	0x7fca8ff3	0x06bbad7c	0x1a5a6f2f	0x1effefd9
-	0x1aae25a8	0xc594864f	0x8df29cf4	0x373b22ee
-	0xfd7cc798	0x2d3018a5	0x31806f07	0xaeadce1e
-	0x9eb56db2	0x997e6a02	0x3f6ad090	0x8d13dedf
-	0x6fb3b150	0xbd15fe3c	0x35b6e654	0xfd9cda44
-	0x77864119	0x7ab48f53	0xf0cf2f91	0x16c955fe
-	0x06ae6500	0x11969961	0xcf4c27cc	0xe0500cae
-	0x361b4f0a	0x95eafe71	0x9ec8e2a0	0xafd6afe8
-	0x424b6b80	0x4b2e1810	0x3b474219	0x142aea44
-	0xf3654186	0x3ba86c0b	0x833f65c2	0x6d47eb79
-	0x62dd2140	0xd94a70fb	0x8ca1614f	0xaf4b2f5a
-	0x49a94d86	0xd1bcf8ff	0x75758118	0x4d249643
-	0x1998d0e3	0x9138a5d2	0x25c3285d	0x94aff0c3
-	0xa3b5228a	0xd19437b7	0xef21e585	0x1b7e4f3c
-	0xd641981d	0xb402e718	0x864429c0	0xdea501be
-	0x106824bd	0xfa029c7e	0x24d7c5b1	0x392faf14
-	0xc6d34b80	0xcdae7248	0x8fcda2d8	0x4ea47d55
-	0x6159a07e	0x7321230e	0x898acb28	0x1ee768ef
-	0x18d5b5ce	0xad651352	0xcdb1b265	0x51344650
-	0xac50b615	0xe63a8384	0x80662716	0x82a18a79
-	0xa5a7efaa	0x7a145b9c	0x849e7f01	0x6798d58b
-	0x040590b7	0xc5ea38e3	0xc801c79c	0xbb195537
-	0x928bbb0c	0x38dbcc6c	0x78392d00	0x7a1ab99a
-	0x7ab11689	0x5da16626	0x01fc4fc1	0x73aaf369
-	0x4ae39f8f	0x5615a7a3	0x973313fa	0xc7ad9ba8
-	0xd58a9805	0xf600d196	0x2acf7e8a	0xa9781219
-	0x2f60bfd1	0x73dd49ed	0x08e92462	0x7c088af6
-	0xc0ec767b	0x813d1a47	0xc854915f	0x38c19883
-	0x3d68948b	0x37013904	0x7d673d86	0x9a347e46
-	0x89b64816	0xe2eea157	0x9c9e7b43	0x88894832
-	0x4e420ce2	0xff8ca9a2	0xc152fd87	0xfb407682
-	0xe2808404	0x4c386f6e	0x053cd949	0x08f55f48
-	0xf89b7624	0x37e43a08	0xf9bc62ae	0xa6d76f51
-	0x4e400425	0xda181f10	0xad190c86	0x6952cd23
-	0x1c1fc245	0x44d3449b	0x2383b865	0xfe9bb854
-	0x745990c5	0x34be0541	0x3ec0104d	0xda80eb99
-	0xf0b3f266	0x29caf9a7	0xf4ff713b	0xebd3c95c
-	0x1b2223d9	0x14809a4b	0xde8ecf29	0x2140f249
-	0x9da938f4	0x5376618d	0x45e1c6b9	0xcde4cb9b
-	0x1dad65a2	0x47567cc3	0x285f8145	0x080df22d
-	0x61f570bd	0x54c91058	0x597a3472	0x4e2199a7
-	0x54bc0b43	0xbbe1df4b	0xdf0843a0	0x007ffa70
-	0x44a969ce	0x2b10aaad	0x337ffb08	0xd176496c
-	0xe89a0d63	0x953fb0c5	0xc3cfcb1c	0x92a96ea5
-	0xbde759f4	0x497e8adf	0xad8b516c	0xfb6967f2
-	0xdc9031a4	0x6a200ab4	0xd93f8951	0x28e22ade
-	0xf54c1c4d	0x8b6325f0	0xa7946fbb	0x76ed4a4d
-	0x6b808dd2	0x86634406	0xa5044ca5	0xe0d0591a
-	0xd817455d	0xc00d1daa	0xc7c40850	0xe2e025fd
-	0x74ba9bad	0x550c236d	0x29b44966	0xdcbd8276
-	0xc4b6586d	0xb1702e0f	0xaebf15a6	0x7d2f1cd7
-	0x9ccc8b24	0xd2fe8842	0x1fe70488	0xffe89b22
-	0x7600ef41	0x75569ee5	0x89f065c0	0xda8d0c8b
-	0x27296329	0x99241565	0x611cc8c9	0xc67415f1
-	0xf0cf41fb	0x38f066ea	0xc13dff67	0xbc04723e
-	0x8f6f8db7	0x94821abe	0x45a5c57a	0x0c3c2474
-	0xd80aa358	0xf95e1874	0xaf4258aa	0x325f2c1d
-	0xcb15342c	0x40d77acf	0xefad72fd	0xb154345e
-	0x9584df00	0xd0712387	0x6d7d329b	0x8c8ff2eb
-	0xebd94378	0x8b0bae9d	0xeecd6bc3	0x529a6a69
-	0x797edc8f	0x4845ef9f	0xa0d083f8	0x14cd8c0b
-	0x775ef704	0x1f83b4f0	0x0047afdf	0xebf6dd6f
-	0xad0a5557	0x9a9beed1	0x9784c839	0xc5fb7640
-	0xe0b3993c	0xaaf9fee0	0x59976746	0x79e0674a
-	0x82b5ffca	0x608e4a56	0xdb81df21	0x3a558382
-	0x17a7c643	0xd9112bd2	0x2e2a3121	0x852a0836
-	0x5625abd8	0x57f8621c	0x7d64dd40	0x2a8d920f
-	0x5fe3e399	0x4486edd8	0xd36655a2	0x23851557
-	0xa096b610	0x06d36c37	0x05d1fb87	0x953aea36
-	0x168daec1	0xbb219585	0x5f17aa7c	0x35d378ae
-	0x76e183ff	0xd6ec5f10	0x4bda67c1	0x96859188
-	0xb328559f	0x834f3e93	0xab87eb5b	0xa8bdb45c
-	0x6e81579f	0x07fee7e4	0x426aa06f	0x7380dc40
-	0x27cb618e	0x05d41994	0x98876595	0x4e6ecda7
-	0xd0549783	0x21b62d1c	0x85058d66	0xbeb36620
-	0x3457564f	0xc29012ee	0x40f30d02	0xa19964e0
-	0xe6f4e733	0x629df93f	0x958abe90	0xab4c3d2a
-	0x55c626d3	0x63cd0ce5	0x832f8ae1	0x8dc5bc20
-	0xcd0b0550	0xfeee65eb	0x0b8309a7	0xdaa9623c
-	0xb5e51b5a	0xf00c9323	0x6b897c27	0x0bd12d37
-	0xf42f8ae6	0x48b81705	0x155e9392	0xb40ca230
-	0x798cd836	0x58e7eb07	0xca2eb2d6	0x238429bc
-	0xdb60b26c	0xca555fd8	0xac907a1c	0x2307f54a
-	0x74b44142	0x44d620aa	0xabf0208d	0x8904f028
-	0x264f31eb	0x5096576e	0x470ccc88	0xed1d68c2
-	0x03ddf124	0x507bec18	0x262b5988	0xb9b530e2
-	0xd1ac6728	0x3a407a87	0x92308c30	0x7394af8f
-	0x4273dd50	0x1abd7a7d	0x28374e74	0x87404b18
-	0xcf9b2454	0x2da15860	0xfb151dad	0xd7c5e552
-	0x58a49994	0x7daa7fb6	0xf5c7032d	0x199c156c
-	0xe42c6748	0x7ab9b557	0x547802b8	0xc606a059
-	0x3d89ff21	0x4fcdec22	0xb1087ad2	0x5521be5a
-	0x5bd9618f	0x93aabce7	0x28be0c32	0xcae8c149
-	0xe98236c3	0xe4be458c	0x805a0a38	0xb300ceb7
-	0x1dcb3642	0x33d87e03	0x81c17b3a	0xf8b59cd4
-	0x9ed300eb	0x5e99acb6	0xab24565e	0xa7e9d72a
-	0x92f97cf2	0xb61fa917	0xbc4167ea	0x5c37d1f6
-	0xcd5200f3	0xc48dcdf1	0x3ba93fe4	0xf5045cec
-	0xc09adede	0xdeef5953	0x1d7c6b08	0x77f2cd7c
-	0x025d30ab	0x206b53a8	0x8140335f	0xed1751b1
-	0x9fc265b6	0xdc56b2ba	0x6f60ddda	0xf92d7837
-	0x3560dc91	0xed0140fd	0x12071a5e	0x397e7dba
-	0x8d9c89b8	0x5f79e3f3	0x41add538	0xafce559e
-	0x8956bcaa	0x76854169	0xac9d211d	0x1d9d2f47
-	0xa4c8cf2f	0x0bdfa060	0x35ca5f3b	0x1ec524c5
-	0x859b6ead	0xb3bd5250	0x1616fbf5	0xd18e5d38
-	0x8b1b06a7	0x9b6e1a2b	0x128e9c72	0xbb672bb7
-	0xd50b0234	0xfe1f75c3	0x40062da3	0x7b875ae3
-	0xca401a1c	0x1668185e	0x25002654	0x314eb038
-	0xd03a8be3	0x86717b8c	0x1bd58524	0xe17ba392
-	0xaf90d12d	0x7b3afe6e	0xcad2b963	0xb91245fe
-	0xe0c7c9f6	0xf98b3bd5	0x305bd207	0x713515d1
-	0x4677d009	0x20e34228	0x6128d849	0x5fb620df
-	0xe3274241	0xd3814ecd	0x223303a7	0xcba4f054
-	0x73a34ab0	0x874fb4ce	0x390efd43	0x490a7a12
-	0xa45a9d66	0xde80cd80	0x9a36beaa	0x2cfca0fc
-	0x231f4d1d	0x04c1fad2	0x5ad83a8d	0xc2931f83
-	0x97f63f61	0x38a6029c	0xe34de276	0x699fa28b
-	0x458d2e15	0x67b57701	0x49385ab4	0x09417b0c
-	0x18897b93	0x516f5749	0x4578a8ff	0x52fbda3e
-	0x2da1dd8a	0xf22e616a	0x7806ab6e	0x92886668
-	0xaf7e056f	0xd9a35959	0xf6ae0b16	0xa42d213d
-	0x928ba1be	0xb61f8e2a	0x6635e3c8	0xbaf76f05
-	0x693d4eb0	0x69546031	0x00427e2b	0x97e563bd
-	0x2857d47f	0x28aaa688	0xf91ec5a8	0xd119289f
-	0x721dc1df	0xdc40c94e	0x67e3d987	0xd2141380
-	0x1bdb7023	0xa84158f3	0x5637a2a8	0x34f80708
-	0x7d452316	0x7cdd1f84	0xe1d1633a	0x82d9f886
-	0xad779cc7	0xd2ae85f9	0x0c467ac9	0x27c1d5f5
-	0x1b28be66	0x34d759d5	0xbcb56ec9	0x171c3020
-	0xac4319ce	0x68c1e8c2	0x3cb463cd	0x78a065bb
-	0x5188b314	0xc8566dfa	0xc93094fc	0x28a21400
-	0x9151a62d	0x678940c6	0x5023ed27	0x089290aa
-	0x327f3b1d	0x7e3d9bc8	0x2c664ff5	0x32e58da7
-	0xe998fd47	0x480411d0	0x9297db4c	0x182058ef
-	0xe21c0a93	0xa32d2771	0x91199466	0xdb8694df
-	0x6261f08c	0x3aff7da0	0x1e24865e	0xde2f7ebf
-	0x1f570473	0x3ec320a3	0x3a8461b6	0x3e1c1e73
-	0x862aa78e	0x74c9a73f	0x090973ab	0x248fb1fd
-	0xebb1b73c	0xab8cc3d0	0xa80d3a86	0xb81c4992
-	0x9f14bb10	0xef283b13	0x060ac416	0x03768c78
-	0xab1a3b35	0xa8f7cf27	0x947beee4	0xdb6d4731
-	0xbc6cebd4	0x39e3cd02	0x9ced359a	0x3358a905
-	0xa4f31baf	0x56bb572c	0x0a8ccbde	0xe701126f
-	0xad241a42	0xd66bafdf	0x5be07a77	0x4fa8a2ee
-	0xff2a829e	0xbe7aa422	0x8ba9b94c	0x20fce978
-	0x8086487b	0x66bf1d28	0x0e9a4b37	0xdf5836b6
-	0xa6eb018c	0xf6a5ef16	0xcfb3b85f	0xa8bc1ecc
-	0x3c5925ab	0x1c926d4a	0x60e2747c	0x629eb075
-	0xbdcfea23	0x10443caa	0x5d005a9a	0x4a6235b1
-	0x56b70ab3	0xff8cb97f	0x42828a8b	0x33692058
-	0x4ce783ad	0x08d1c099	0xb14379df	0xd65d24dd
-	0x14450585	0xbb0450d7	0xc8776287	0xea2eb9b6
-	0xc44d73e2	0xcb386daf	0x9d3686a1	0xb58c318b
-	0x287fbe53	0xe8d84535	0xbf17ef8f	0x98332fff
-	0x5e098cbb	0x9ecc14a7	0x08366dbc	0x55028860
-	0xc09e869f	0xa29a43e7	0x9be9daac	0xa1750a10
-	0xb2fd8da5	0xf380c1cf	0x6087ff3c	0xd69bd21c
-	0x7e14ede5	0xc0ed409f	0x12f25810	0x3f44d63e
-	0x9e7b0cab	0xcb9cc71b	0x18b66ea5	0x80843c35
-	0xf140a7ed	0x89fb323d	0x0a326c40	0xe3f9af29
-	0xf6c59365	0xad3a2017	0x906d1ce2	0xd3360e1f
-	0x046307dd	0x290ff1e8	0x910a9632	0x5cf471a7
-	0x54321c10	0x12924fa3	0xff3d87e6	0xb1687618
-	0xa2a68555	0x1a21d3bd	0x1095d6f9	0x349b25d0
-	0x8166c94a	0x006c839e	0x0094b4e4	0xdd11f901
-	0x1c40e7f0	0x50946c87	0x52bcea55	0x20b86a9c
-	0x7b386df2	0xddd48f3d	0x421d417a	0x7052e089
-	0x8ec43a4e	0x6174ca83	0x6b712d8e	0x566ae151
-	0xc38d68a1	0xf7d64e87	0x9f53d487	0x5e985461
-	0x21d27e2b	0xdbb9bf40	0x2826a5cc	0x6ca4d786
-	0x381508b8	0xd8ffd839	0xa85f5b86	0xb37fa53d
-	0xe4906f8f	0xc7329e0a	0xe56272aa	0xe7b97be8
-	0xbd6a48dc	0x935e9f91	0x02313e13	0x026b8e36
-	0x939a5293	0xe125a1a5	0x6b27d136	0x3d520ae7
-	0x7abc1309	0x183f50f6	0x08575ed5	0x1d2c4c72
-	0x0e682129	0x655ceb36	0x1a508349	0x3be034d9
-	0x4bf83c5f	0x592520d0	0x5f65a0c2	0xcad74a35
-	0x5c4e605a	0x973b60a3	0x309fc15b	0x3ea3781f
-	0xb56c3172	0x269f8d75	0xebfa9293	0x9ff8bf36
-	0x27bc0472	0x4a1888d1	0x598b47c1	0xba2d3073
-	0xf71b310a	0xb9db5309	0x065ffaf8	0xeb21604b
-	0x60875644	0x6f76cd48	0x47746357	0xbf2e90b5
-	0x7d40e67d	0xe87f11ec	0xc5409f18	0x9904fefe
-	0x9745644f	0xe1089f12	0xdc49f755	0xf0cd3596
-	0xe9e69302	0x419b9a3b	0x3f0a6315	0x8b715e28
-	0x363ede54	0xcd41a72f	0x0bafa9fe	0xd00225c7
-	0x6e8d0407	0xd1f100b9	0x0cd02e9c	0x760a2ffd
-	0x6ac6f01e	0xd2226e57	0xe7a7bd75	0x0bec05af
-	0x72b4d6c9	0x54df0f5b	0xbcb2bb34	0x20364bf2
-	0x9fc24cdf	0x83452f28	0x734248b7	0xc698bf34
-	0xee328cdc	0x8e4bff33	0xa1addacd	0x07af68c8
-	0xc34b5d25	0x8e611a0d	0xcbb8ff85	0x077c6d43
-	0x95feb2a3	0xb435fffc	0xef5eca7a	0x0ff6045a
-	0x449647ba	0x75795c99	0x9c514436	0xabbe74d9
-	0xd180f18d	0xdcdeee76	0xa9550f7b	0xb4c8e109
-	0x80b21662	0x8a407a0c	0xa6245b13	0xa16f44ac
-	0xb3db67d3	0x0b335cfe	0xd878e875	0x81d6df28
-	0x44871141	0x6a6dada5	0x7f97fcd0	0x7ee87f79
-	0xddc5bcfa	0xfc2763db	0xb11a9212	0x94ba7acc
-	0x49428749	0xd219071f	0xd91bc4c2	0x4ad5c326
-	0x54ea2297	0xdb16bca5	0x33327f3f	0xc487b8c7
-	0x54ca8d94	0x4c6f5655	0xf51c3911	0x37931433
-	0xf6506856	0x6b5a93f8	0x388950b9	0xdf5263b5
-	0xd4cf56ea	0x8da347e2	0xf20a9a39	0x1a6b8e4c
-	0x2ce3df55	0x38269e78	0xdc7a9762	0x9e73a3dc
-	0x57de6fa7	0x9c2573f5	0x3491629e	0x009452fe
-	0x8a34ddd1	0x701df9ab	0x4035380c	0x6f25e16d
-	0x0ca914de	0xf9277a06	0xca1f1fe3	0x95aec5b6
-	0x7a613e97	0x52e77607	0xd7229ff0	0x5f301016
-	0xd4e142c1	0x29a939cb	0xe96dd1ca	0xc953aec0
-	0xbf02c31e	0x02135076	0x4f931dcb	0x4b280cd3
-	0xe0cda493	0x70831c04	0x8192143c	0xc9f94a3b
-	0x13eda1d1	0xc62c39ad	0x754a5411	0xe43ce416
-	0x95ac1b10	0x871261dd	0x79f33a8a	0x77383224
-	0x98b2480f	0x2df139d4	0xd753e53b	0xbad87b53
-	0x977cc17f	0xacc4bb71	0xbde6b5f2	0x206562ae
-	0xe0319086	0xcf903501	0x56ed1506	0x64f4556c
-	0xb90bbe0f	0x2def02e5	0x9b625a9b	0x96086cce
-	0x39d1d0ab	0x8c85c5d6	0xa8199040	0x23c770e2
-	0xf5303bd0	0x51a83607	0x5afa1989	0x8a81b4ff
-	0x1b24e6a4	0x4cb58014	0xbbee7d31	0x758271fd
-	0x259bc3f5	0xb3f9c6eb	0xbd8c4f86	0x66c27a35
-	0xa41c2904	0xc9848ce3	0x9ba21676	0x18f65508
-	0xe5637556	0x031e21c0	0xc09e3c77	0x5f10856f
-	0x9b3ea697	0xd8afe20b	0x447f5be1	0x5c4b1668
-	0x71f44cc1	0x8637d0c6	0xbd182081	0x1e4221b4
-	0xd312a403	0xf49d2c96	0x686ff9e1	0xa3f9b746
-	0x3caeae90	0xf2bfb131	0x5823eb37	0xcd4edc6d
-	0x3a7f65d8	0xbb4be9d3	0xd7939b2e	0x71d03a37
-	0xa30ff63a	0xde7ccb57	0x8ea031ba	0xbcb3994d
-	0x8018d6fb	0x1c7a3610	0xac900573	0x9ad05089
-	0xe2d17d5e	0x7816b9a7	0xffcca5c1	0x9faa9a0c
-	0xadbe99e6	0x06de7ee1	0xe4ac8981	0x29ef423c
-	0x32219ad2	0x806642b8	0x412ab076	0xfe4c5196
-	0x82c2507c	0xd58c7b7c	0xfe9edc9a	0x89e4c6e9
-	0x4f122269	0xf0aeb2f1	0x77f4fbc0	0xe6692464
-	0x6e64c198	0xaf79a455	0x01e2ed98	0x897ec1b0
-	0xf7a0dd35	0x92baec5e	0x93f17b7e	0xfbf82b90
-	0x168d32c5	0x741b61c0	0xb0f5b9b5	0x0557fb71
-	0xca937e89	0xad652a2b	0x9a2121c8	0x34d189ca
-	0x037dd1a3	0x3e650192	0x4defbaa7	0x06763750
-	0x48d4d1b4	0xda2af400	0x7df71d63	0x3e0b4c46
-	0x28c645bc	0x29b15428	0x34e10558	0x1166cdd6
-	0xc259a364	0xdc7e0f21	0xb02cee35	0x3055f39b
-	0xb77a50d2	0x2c143c84	0x7903e30c	0x018e20a8
-	0xf95b4a26	0x38c84311	0x1f0c3098	0x535a95e7
-	0x730214dd	0xb0f90f53	0x625fc5d1	0x2c1f2d76
-	0x7c9b5351	0x5cc285f4	0x0f63b5f4	0x90d59d57
-	0x140213fc	0xd21a74b7	0xf85fd83b	0xd9f21e94
-	0xbbefcd30	0x5091f90f	0x8d5c47fc	0x9455364a
-	0xef89f274	0x901af041	0x782cd03a	0x086f1f81
-	0xe09eb4db	0xf7a8146c	0x41898271	0xe8be480c
-	0xdfbac329	0x5fb899cd	0xfdca25e8	0xe994b3d8
-	0x2299ede3	0xc0341512	0x0128eb87	0xd5cff619
-	0x779bba38	0x1e986657	0xc22ac15c	0x919af309
-	0xd3cd1df4	0xb4b22d9a	0x210c0617	0x5723f9e0
-	0xb7b79328	0x613e738d	0x39057942	0x48d48958
-	0xf9d80cc0	0x16f69a5c	0x6d517734	0x012f07fa
-	0x7a8329e1	0x586b22c3	0xdd0d96b9	0x0c56d5f9
-	0x60410aa3	0xd1975446	0xd2c142fa	0xb13ba75b
-	0x0b046c21	0x03afb4e0	0x346f5dce	0xd108fa96
-	0xd1ca963c	0x73f5838a	0x4b4f734f	0xa1d430a7
-	0xd0cda381	0x64fecfee	0xc5048480	0xd3bfb251
-	0x088982f9	0x2383aaee	0x9b9c8f48	0x623f2132
-	0x0f5ae663	0x3c32959a	0xa1fd9ecc	0xf62d0e4c
-	0xe690d930	0x6be7a286	0x825d0066	0xe51094ca
-	0xc99affb8	0x832222ea	0xe7296513	0x2c040c86
-	0x35f62e4f	0x6f46ba84	0x25cdb0a3	0xe8b6ec22
-	0x5b6cf8d0	0xcfd85f8a	0xf0181633	0x5362c0b7
-	0x58955c60	0xc5a36973	0x874d04eb	0xa42a42df
-	0x4bd5d994	0xee6114f3	0x671ccecb	0xf0ae2422
-	0x70c98042	0xf9ed2a1a	0x6b60f0c9	0x04b13374
-	0x96fba002	0x8b481645	0x315198a2	0x65c80b9a
-	0x31475dd9	0xe95c5c3a	0xe3c22d43	0x12659565
-	0xabec6f96	0x9446e315	0xa6552f83	0x295e2596
-	0x8b6a2d9f	0x71efb10e	0x2d309912	0xe3dd2879
-	0xabd39f50	0xcfa94a90	0x61d282b7	0x062b246f
-	0x617b7162	0x3628fffd	0x93c8c8a5	0xaa44c72a
-	0x11b78bff	0x8259874a	0x186bbcfd	0x37bf7395
-	0x6f8582a7	0x65fdd21b	0x53106cb5	0xbfbe1e4a
-	0x1ed99eac	0x670b3763	0x245db7b2	0x7584d9be
-	0xc3472009	0x572bddab	0x17e7406c	0x79e0ea4e
-	0x74779fd3	0x92d0c51a	0x1808d006	0x46c1e76b
-	0x40e48bf4	0x61e17325	0x1d437ab2	0xacf51c38
-	0xc19eab2c	0x02957308	0x0bcc40bb	0xf603815f
-	0x9c666571	0x6a7d539f	0x57f3941b	0x7af81d5c
-	0xad1427b0	0xc188d623	0xac010003	0x1ff4cdf6
-	0xfa504446	0x6425ba6c	0x27ff69fa	0x26da5613
-	0xb6fc0a69	0x1155853e	0xbab81c6e	0x3dc17909
-	0x07b209d9	0x8b269554	0x73fc8781	0xfc1c2c82
-	0x572df087	0xb71bb5e5	0x55f9d202	0x6f525daf
-	0x117755f9	0x52cce1bb	0xa789ed0e	0x1313ca47
-	0xe8bdd878	0xc37e8dcb	0x53b971fc	0x43540a80
-	0x3d2384a7	0x25ac992d	0x7aef31c8	0xb1294afd
-	0xb0a34878	0x96e9ca1d	0x82a19bcd	0x08cd2bdf
-	0xd2681e35	0x2d32fa5f	0xc7c0c8b2	0xeecd089d
-	0x97404355	0x0b34539d	0x37ce4df3	0x599352dc
-	0x06734f29	0xf47ab5d8	0xb15ea9a4	0xfd92ed2f
-	0x9510bdbd	0xb740d34b	0xbac3e94a	0x52efbc03
-	0x40bd7acb	0x1bf83a4f	0x3d76c698	0x7e691383
-	0xec85e4ae	0x55e9a446	0x1fc3ab3b	0x6aea12fe
-	0x8fab4a84	0x69cd7328	0x935a7236	0xc3f59437
-	0xb73a7d8b	0xba0f54e0	0xe8e7aafc	0x6f82ade6
-	0xed6ccaf0	0xdfddc46c	0x0763fc3e	0x778e488f
-	0x0bcc4dce	0x8f919858	0xa7bc7d1a	0xd4954eea
-	0x517b5458	0x6c3f5835	0xd960f76d	0xf5be65a7
-	0x133666d9	0x4431f94f	0xccedf47d	0x6eb21ff8
-	0xb858dfef	0x15beefef	0x9a1b6b6a	0x64890eda
-	0x2a381329	0x660302bb	0xc65c001c	0x049a4be4
-	0xfca1b112	0xb081a099	0x3a2217f8	0xeea9a2ef
-	0x7719129c	0x7c915047	0xb3fe3e16	0xf1c31548
-	0xfa84a76b	0xd7af5b51	0x0de24c14	0x89a7263d
-	0x5a9dbffe	0x7ea90ae3	0xc21a2a1d	0x65ef3a3e
-	0x90fd1fa0	0x69aa0d9b	0xb44a5778	0x5ded34b3
-	0xa0d78617	0x91817661	0xf9541869	0xa0960273
-	0x024d891a	0xbc9f6d7a	0x630bac04	0xd186ffe5
-	0x0d60d640	0xc05e4701	0xba72d775	0xacec7c0c
-	0x1680e76d	0x6b153d69	0xbcbd60c1	0x3e1ed6c6
-	0x9705975b	0xaa3cc082	0xbdd723d0	0x7c0bbdd9
-	0x2bcf8414	0x787b2dea	0xaf923561	0xe4ad94a2
-	0xa85f83a1	0x1de0ddcf	0xd96f918b	0x617b1461
-	0xb1d3e386	0xe8d80b5d	0x40dad53e	0xcd8fb285
-	0x46fb4bae	0x2845c456	0x8b261251	0xf4923055
-	0x99d0db1e	0x0d7cc781	0x9bb20af6	0x7116d81c
-	0xd7f54821	0xba4eb2d0	0xaef6b275	0x3ca796cf
-	0x8807360c	0xd887484b	0x7066ec38	0xf7262152
-	0x5ede9cc5	0x6b8eb00c	0x5564b7af	0x4726dfd1
-	0x9421fe95	0xcc0ff9e5	0x10ca7e89	0xb76760e6
-	0x3da3a50a	0xf9cd3f82	0x1eb01d3c	0x13ae6371
-	0x129747e6	0xab223504	0x9978c7e9	0x1f7ce259
-	0xb17fb162	0xd1ac0e80	0xe04bfd17	0x197d9eac
-	0x59586a32	0x7436e8ef	0xc28b1ec5	0x83af0dc7
-	0x8382692e	0x17f04148	0x31ee5ad3	0xfe89b973
-	0x0148467a	0x1a6a16ef	0xb6400bcd	0x53ae7036
-	0x6b258693	0xb6edbeca	0x2ff0b686	0xe6f0c346
-	0x0e0ff99c	0x8d369a6e	0x7d10411d	0x2ebccabc
-	0xa67435d3	0xf9901563	0x363f164f	0xf01a1b15
-	0x93b6a10f	0x81f0c068	0x89b8423d	0x60eb711a
-	0x4e45bf98	0x24845e1e	0xda91d7f7	0x561e7ab1
-	0x51a183de	0x73bf29a6	0xcdb20f84	0x46d5ab3d
-	0xce01efbc	0x8d09be04	0xbf4aee2e	0xadf03a7b
-	0xbc454c61	0x83647148	0xec9e834a	0x11527826
-	0x2c7eb009	0xc6d7e3f4	0xbe8befd2	0xd3cc42a8
-	0x0442b41e	0x89643506	0xfd1dc572	0x74b340bc
-	0x686f6f6c	0x48b92189	0xe8f88be6	0xfc591dbf
-	0x8b453678	0xea1fd8cc	0x659d57d9	0xb501f90c
-	0xa6d6b031	0x182d8378	0xd6a8d690	0x6419c2b6
-	0x523d3089	0xc23c971c	0x43994015	0xa4b23066
-	0x831e6ca5	0x03c18610	0xd6d1f4b5	0x28978a3d
-	0xdc620eba	0xc1f86faa	0xf6c4d906	0xf06f85f3
-	0x232fa1bf	0xcf80cc2a	0x6599a5b2	0xc2d4cdad
-	0x0287eb92	0x5cdc4dd6	0x34a9b6d4	0x6d4b1324
-	0x6d21a837	0x00026037	0x80a225a8	0xad75b226
-	0x414a3741	0xb74d0962	0x363b24b5	0xb5044295
-	0x0a01c1a1	0x90a110c8	0x53bdeee5	0xad31aa53
-	0xfb85cc5f	0xdf80b0f3	0x7ad3cb0f	0xb5c68bd6
-	0x89185ff8	0x41544629	0xad5adfe7	0x39061752
-	0x2e9c106c	0xbf52a0df	0x9d2cef79	0x99eba49d
-	0x4459b32c	0xdc98fd7b	0xd81f2f74	0x8aa59f53
-	0x1817857f	0x5f79e3bf	0xc4b7c810	0x9e3a9ddc
-	0x724af115	0x121239e3	0x3c33c849	0xd8abb44d
-	0x600d67b7	0xeaa06b4c	0x20fe7ba6	0x502c684b
-	0xf212d37d	0x413d883a	0x5abc83ec	0x3112bb6e
-	0x27e1b3e0	0xf6dc8508	0xfe602c4f	0xa5b34bce
-	0x4d03d689	0xdacb23c2	0xa00fb513	0x78606ea8
-	0x8fd43ecf	0x90072d2a	0xfcc7b1b9	0x7ffec951
-	0x684bbc25	0xc21a0374	0x8f06a016	0x0e28dfea
-	0x40da3a00	0x8c73a059	0xc0d565ef	0x13bb6c81
-	0x6e27c2ec	0x2f4c9a43	0xae1b4513	0x9738b38a
-	0x5557c3e1	0xa292c6ab	0xd0f78cea	0xb96402f7
-	0x6c281a04	0x948787f9	0xe59f0714	0x6f130446
-	0x4b12e263	0xcae5e073	0x00f0e279	0x9b03c647
-	0x2a141b72	0x19d1e112	0x97b3b6df	0x3c2b6c82
-	0x5b119136	0x57e2084c	0xe954bc0d	0xcdfbfa78
-	0xadc6b571	0x010b9122	0x236676d6	0x2458c822
-	0xcbb8384a	0x662cfd01	0x096c50d2	0x4959676b
-	0xf8b59f31	0xad912a4d	0x2e87fa6e	0x30182092
-	0xc0bf2c01	0x02b4bfa7	0xdd208dac	0x4c174da2
-	>;
diff --git a/arch/x86/dts/microcode/m0130679907.dtsi b/arch/x86/dts/microcode/m0130679907.dtsi
new file mode 100644
index 0000000000..30e2f9e527
--- /dev/null
+++ b/arch/x86/dts/microcode/m0130679907.dtsi
@@ -0,0 +1,3284 @@
+/*
+ * ---
+ * This is a device tree fragment. Use #include to add these properties to a
+ * node.
+ *
+ * Date:
+ */
+
+compatible = "intel,microcode";
+intel,header-version = <1>;
+intel,update-revision = <0x907>;
+intel,date-code = <0x11142015>;
+intel,processor-signature = <0x30679>;
+intel,checksum = <0x1bb67b21>;
+intel,loader-revision = <1>;
+intel,processor-flags = <0x1>;
+
+/* The first 48-bytes are the public header which repeats the above data */
+data = <
+	0x01000000	0x07090000	0x15201411	0x79060300
+	0x217bb61b	0x01000000	0x01000000	0xd0cb0000
+	0x00cc0000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xa1000000	0x01000200	0x07090000
+	0x00000000	0x00000000	0x13111520	0x01320000
+	0x01000000	0x79060300	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x00000000	0xf4320000	0x00000000	0x00000000
+	0x00000000	0x00000000	0x00000000	0x00000000
+	0x9703f29f	0x1c68d65c	0x1f15f858	0x114237f4
+	0xfef8d172	0x363b5a9d	0x4c3d9e71	0x13ff68a0
+	0xdb666815	0x5a17bfc4	0x4fca009d	0x099ae8b3
+	0x198e2c7d	0x7c665bbf	0xc07a1a7a	0x7dbcee26
+	0x867296b2	0xc885b6ce	0xe602baff	0x68544b14
+	0xc928c400	0x3add156d	0x531946f9	0x92a03216
+	0xda352322	0xd967ee1f	0x3c5170a7	0xf6de834e
+	0x5a2ed8b3	0x9fb8f050	0x450de17f	0xfd5ef070
+	0x4954575f	0xa3a071ab	0xb56e2afb	0xe2b48302
+	0x6655a958	0x57c9a438	0x1b2f688a	0x09309bc4
+	0x0be95612	0x529c1633	0xc48515d9	0x29eb78df
+	0x9933409f	0xda58dea9	0x58c805fd	0xbc110f5a
+	0x40780ec0	0x6ad59bb3	0xc7387fb8	0x591c1490
+	0xf9335932	0x32130e0b	0xef4b3c96	0xacd903f2
+	0x5b362539	0xe7f85529	0xcb17c41f	0xe7e440d8
+	0xfaf7e925	0x969b76fb	0x5edab8c7	0xf00012e8
+	0x121c2971	0xe5b18959	0xadfd07c0	0x1f09c9d7
+	0x9781006a	0x39550073	0x6c438b6d	0x436f60bc
+	0x11000000	0x46e87267	0x7c9db265	0x4ac824e5
+	0x94ed53c5	0x4b1bbf81	0x241a4da8	0xc3c5d866
+	0x186d6eed	0xba1e5092	0x3d19677c	0x82b56f7d
+	0x95d4d506	0xdccbbfb2	0xdc6be978	0x416dbe64
+	0xe591ce22	0x02987636	0x44858276	0xfbe3729a
+	0xee42767f	0xb415639f	0xbc959b72	0xa6919bec
+	0xb9e2d0c5	0x2fb1e39c	0x1ebae20a	0x9a3ce21a
+	0xebf72206	0x4020d73c	0x92674cff	0xbc607b8d
+	0x488d8dc0	0xd1d6f435	0x39e3ee1c	0x1ed65078
+	0x967d7a88	0xaa1b9f3b	0x38248bfe	0xb8a0aeb2
+	0x3b8e34fb	0x86dd48e5	0x887d7432	0x3a3a3faf
+	0xec556202	0x50ebe457	0x7676b9bf	0xe84604b0
+	0xcb26a17e	0x52c94055	0x6b39d618	0xa82d63dc
+	0xf583cafd	0x32107d4e	0x71d5aee8	0xad5956f2
+	0xad58e817	0xb6da62b3	0x66d63e32	0x00a13bc7
+	0x71233e63	0x326ef79d	0x2e3cf966	0x92b08830
+	0x42be3b3e	0xd49905d5	0x638b6a72	0xbeaa8cbf
+	0x5f28a0f8	0xff10578d	0x59a2d213	0x2919bc00
+	0x61398c7c	0x2a0865e3	0xf1a42982	0xa1e24984
+	0x2234d6c6	0xd6a9a013	0x79740c47	0x56cd5120
+	0xc4bb279e	0x707d1519	0x33b0445d	0xae3be614
+	0x3c3d5c9c	0x6eb115a9	0x4a2d5cbd	0x58718272
+	0xea01ac92	0x8a6e8d3e	0xadc4315a	0xc6ba0145
+	0x52363aac	0x4960bc5e	0x56a66f82	0xdb06eae9
+	0xbcf5c135	0xd59539a8	0x7b68c56f	0xe298be9c
+	0x8ac3c19a	0x3928fbea	0x4a72f2ab	0xbe32ec72
+	0x5928b934	0x6b56ff28	0xc8f2c78e	0x97d168ee
+	0x43381910	0xa592424e	0xb14ae0a8	0x46f724a8
+	0xded8973b	0x9f9100a2	0xd7cbb2b6	0x2db57173
+	0x217fd7ff	0xa85f3087	0x9e23192e	0xff8a0f31
+	0x86f1ddbf	0xcae0ea2d	0xcd0591a1	0x10733827
+	0x1758f010	0x38bfb48d	0xc0ec80d4	0x3a497694
+	0xe82c7b4a	0xf21a8a2a	0xc4ba866f	0xc88fbed8
+	0xe0e9a0f8	0x60ba6708	0x73fe95cf	0x46fab51f
+	0xab34c80f	0xcd06bd33	0xdee23ab5	0xbb405653
+	0x7948d7e8	0x88713e19	0xf3507645	0xc6cf938e
+	0xa690f2ed	0xa1603eaf	0x71688d1a	0x2fc9a057
+	0x3488d635	0x5f8eaa82	0x5c3ac4be	0xe15a8f69
+	0x0421729e	0xfe7dbfb0	0x5fb6c672	0x99c59c6d
+	0x2feb9ab8	0x0e831a04	0x1c8a41eb	0xe3bda963
+	0xcac53147	0xe6a154bb	0x1dd48215	0xe0fed62e
+	0xd0bc2263	0x820d5f12	0xc3df9df4	0x5c978a68
+	0xd4a6d275	0xaa7525d6	0x9e7c91a5	0xad05611f
+	0x8fa896ec	0x9d002d2c	0x06f50042	0xb05c73cc
+	0x2362a6f3	0xb1db87ad	0x2e08390c	0xb827d183
+	0xba59fc97	0x9c7f5996	0x5a6645b9	0x7ff51fb2
+	0x5f8b2b55	0xbdd03e7d	0x0d7ed8c6	0x0468dd35
+	0x4a32332c	0xfc2af9d6	0x33a14776	0x5a0b8da7
+	0xd278a1c3	0xd3f4df32	0xf06ece96	0x08bf7444
+	0xeb1076fc	0x7ac6604c	0x8810a1a9	0x64920094
+	0x0e68356b	0xef753730	0x9e5a90c3	0xd050c0cf
+	0x80c11368	0x37334deb	0x9a758bcb	0x6a50677f
+	0xe091cba5	0x5e574d20	0xce0786da	0xe8ac8ca7
+	0xb08cc364	0x599dec0d	0x755090c1	0xdeb882a1
+	0xdb41e3b9	0x5bea550a	0x588fcfe6	0x2f47fda6
+	0x3c535740	0xb01ef7a1	0x41318391	0x9573deaa
+	0x3b049cbe	0xba4a8bca	0xc70f0a90	0xe353d011
+	0x79493cae	0xb41bd61d	0xbb73d556	0x08fe7bac
+	0xd8214968	0xa6fd5c58	0xb90f3e26	0x7374f308
+	0xd9d66fb7	0x23db8822	0x1b1f7701	0xbb557c36
+	0xd8573d73	0xaccfafa7	0x245cdb75	0xd633e6a4
+	0x623cce13	0xff1b1379	0x068eb371	0x634b1fda
+	0x88d187f5	0xc7524ccd	0x4f907ff9	0x65ed9ec6
+	0x90f9f995	0xffe5e671	0xee78e6ff	0x48aa5768
+	0x1d5401d4	0x76125937	0xda829f6b	0x7066f6ab
+	0x35659966	0x59bf2950	0xfe3194c3	0x93e928ec
+	0x94ea826a	0x252f240e	0xf8293138	0xbd9c56a1
+	0x6d976d69	0x00c2bb0b	0xefe2fa50	0x718391d2
+	0xc2856548	0xba3785dc	0x594f8bb7	0x32a3e0a0
+	0xd4ac9cdf	0xbdee3ec4	0x0c1ed6c5	0x5cd2b1dd
+	0x9bd8afe8	0x5598b8fa	0x8899700f	0xe5b11279
+	0x6bc1eff5	0x81488bcd	0x0066bd0f	0x81a041c2
+	0xb8e1db32	0xd6f00d10	0x53c9f929	0xbf537406
+	0xe90e75b9	0x2846542a	0xf8111284	0x6f448d25
+	0xb9303c44	0x73ce77be	0x319187f6	0x2fa38401
+	0x6ce1515c	0x880a819b	0xf18f7bd9	0x4975e304
+	0x7f530a68	0xa15309fe	0x5d2ccf5f	0xfa1388b2
+	0x5abc2e7c	0xd7508296	0x90ab027f	0x1ed00025
+	0x67ad3919	0x040191cb	0x6f2750ca	0x371e23da
+	0x219ce1f2	0x2a94685f	0xf431a11a	0x8f3a916c
+	0x83add01d	0x15b7c162	0xc5fba638	0xc9231626
+	0xc44141eb	0xeb761838	0xf56010d3	0xed370b64
+	0x3d5c291f	0x369d136d	0x64eb568f	0xf0c2fb04
+	0x1ac908fc	0x5267daec	0x72b77c0b	0x9bd72098
+	0x90505914	0x0ab130e0	0xe9d4cc65	0x3841a119
+	0x49107805	0x104d8a9b	0x948432b4	0xa4d9acb4
+	0x01708bdb	0x33867b75	0x77ed63f4	0x6c59d6df
+	0x6ff89016	0xe140d51f	0xfd55b64d	0x2f260ed2
+	0xf5b97bd0	0x4a278b70	0xfebc3552	0x402ab7c7
+	0x1c563e33	0xde063184	0x32e862b1	0x56fd9e7d
+	0x8cc320a3	0x381ad628	0x736053ae	0x8a4d3500
+	0x9af58234	0x9a4f381c	0x2449cda8	0x8bdc08ab
+	0xe02865f1	0xe5384199	0xbc8d798d	0x6e7539be
+	0xbc3d0476	0x7e0d35ee	0x8bf8be24	0xfea1f124
+	0xc93600bf	0x055e1524	0x4d2e695c	0x8ca4be1d
+	0xf56549d1	0xb610a66e	0xf9644f1d	0x72c21fc7
+	0x325c68f4	0x7e46995d	0x98e494b4	0xb80f3796
+	0x63a58bb0	0xc0918dcc	0x90e1ec3d	0x02da69bc
+	0x48d03c2c	0x50f010d7	0x4e33c8ef	0x3868bafc
+	0xa1bbb203	0x6998fad0	0x69c1e854	0xdd61c5a8
+	0x1eae5c43	0x325a24f6	0xcccd1c27	0x286c1720
+	0xe4b90b87	0xae9d5754	0x35d85c1b	0x6dea7c71
+	0x528f612d	0x7bc8e019	0x4554a520	0x06f224b1
+	0x8f956a0e	0x3446bddb	0x05e3665b	0xf78be26d
+	0xfc87322b	0xed1809f8	0xb00b4c9e	0xad731b02
+	0x36cc1bb0	0x3e56e274	0xe1ef883a	0x07c6c2cf
+	0x86055da9	0xb43d2b6d	0x5e4030d1	0xb4a60919
+	0xbc12554c	0x0c1f4dd2	0x1cfeeebe	0x1c21eb21
+	0x32712e65	0x4791d232	0xe35d3bcb	0xe09629b5
+	0x34a07f0c	0x4220cfc1	0xf6b5e353	0x1ddba77b
+	0x1f9ceb98	0x78f1db33	0x9644dcd5	0xaf097bb9
+	0x066a83bd	0xdebaec77	0xf2c82254	0x29dc7087
+	0xbe788ad0	0x6379772c	0x10f39ff0	0x223458b5
+	0x28d5301a	0xd74cce3f	0xdd5a6fe3	0x8407e1fc
+	0x3a7d4db8	0x02e0f87d	0xc3c1330b	0x2c4990f2
+	0x50735cca	0xb9e45d2f	0x63c8c276	0xfe0b5168
+	0x7c54350d	0x0cb05c93	0xee247fb1	0x40a2c610
+	0x22a00f5a	0xdb4d1da6	0x2086a88f	0xd9fa3196
+	0x9d4cb1c7	0x59d40f0a	0xf52294be	0xbc8d5d0f
+	0xead98b7e	0xd31ff3dc	0x4e32632c	0xb9836653
+	0xeae227e3	0x1e334cf7	0xe5ee9187	0x479d5dd8
+	0xadf733a8	0x12c0a7ef	0xe8307249	0x8d72f210
+	0x3336e271	0xbcc12da0	0xb8d52e29	0xe94a46ae
+	0x5926aab4	0x7a929d80	0x60acdcd9	0x9031695e
+	0x76244706	0x48c3995b	0x17f9966c	0x3c1a30f0
+	0x50c0a42d	0x4ae56578	0x1a81d4ab	0x1395c82e
+	0xdf92c366	0x90a188ac	0xe2f83649	0x5696676d
+	0x7a507ba9	0x45f0e0ab	0x2d68a9bb	0x65d50b4e
+	0xa684fa7c	0x63a04a35	0x0f73e4ed	0x1859da4c
+	0x242dfeaa	0xffa2815f	0x04e5ffa2	0x30d55d0c
+	0x559bbc55	0xe68b716a	0x7dcb07a5	0xb1d3c43e
+	0x5b1bc142	0x77656508	0x5f03d2a7	0x13c21c86
+	0x008bf74a	0xe2f5bbf1	0xaee8a9be	0x9bd33d42
+	0x435aa8bd	0x9e8f958d	0x4a7a566d	0x5b2356b4
+	0x4be34fc7	0xac3f87f7	0x7520fbfe	0x351f4afe
+	0x67476a0d	0x64d18e88	0x71bd9d70	0x9da2e4b6
+	0xe7c611c0	0xf009f13c	0x8eb98619	0x74c22cbf
+	0xfe9f40ce	0x23864c9c	0xa0d7777b	0xff87bcf8
+	0xe42e3b0b	0x9c7fe855	0xfb365cf3	0x0ae87000
+	0x39558461	0x5a7fe922	0x52fb616c	0x1dee6ae8
+	0x430c550c	0x0a30532a	0x87403149	0xb708a4c5
+	0xcc1ff466	0xcfca59a9	0xd743b0bd	0xa7e0f484
+	0x6e7ee3dd	0xd5f919e4	0x9015fc59	0x39b566fd
+	0xdd3f25ca	0x8dfc6741	0x9179d918	0xcf08d388
+	0xe523b058	0x0c4407e9	0x25ae6238	0xafe9cf0b
+	0x9fc29e7a	0x236c823d	0x607add38	0x8833fd32
+	0x21c60d26	0x362de265	0xb6bfa503	0xbd27e44e
+	0x5b6bf836	0xe0d35274	0xebe7908f	0x7e076c9c
+	0xa34aeb4e	0x642898f0	0xc87e1a07	0x9bda87b1
+	0x3721f746	0x65c1ec7f	0x3d0ae8a8	0x3115b008
+	0xcb1a56a6	0xd1a76d04	0xfacd1b7f	0xe553744a
+	0x057f2c33	0x13caeeff	0x209c5884	0xc3211b8d
+	0x5a8c81d2	0x1e59cc0c	0xe7b42f60	0x510fc068
+	0xd200fa5d	0x23193201	0x1e534fe0	0xcf2037b8
+	0x6b6bd4fc	0x3e8e94c3	0xdbe1d38a	0x597d5871
+	0xec0129e1	0xb3be9453	0xa400f9f2	0x6ce19ff9
+	0x259187f9	0x24ec708b	0x5fc5f413	0x847c8969
+	0x9fcf3fec	0x0cff18ab	0x4cefa78d	0x35266a04
+	0xbee81833	0x32634f58	0xc9a7c8dc	0x614f28e7
+	0x4dd5ace1	0x15fc0226	0x3f8b4aa5	0x05606056
+	0xbdb5a3f1	0x851e10b9	0x2a6053e5	0x6df96185
+	0x2cd9cf8c	0xe28d1444	0x08d79dea	0x18da1e61
+	0xb59950fc	0xbbc8c699	0xae43972e	0x920023dd
+	0x13008ca7	0x54b36917	0xa35abb2c	0xd4984b2b
+	0x606083d6	0x4e49dabb	0x372ba59d	0x380f7bb4
+	0xeb861260	0x7f0538b5	0xef69498e	0x83bac8b8
+	0x2344d697	0x4f789a8b	0x2d98b057	0x4e94ee3c
+	0x983d7fee	0xaee49b46	0x00de7dcc	0x94c52878
+	0x6f9e3754	0xaef4b9b9	0x6b46ee19	0xddb10fe4
+	0x0dd24290	0x08f708af	0x3fb2e39b	0x3dace909
+	0x84838754	0x94149bb0	0x2359b874	0x4e09221f
+	0xa56ef81d	0x086f9c79	0x0d338c01	0xb2a91bf7
+	0xaa4d6c89	0xf49969e7	0x6a509eb8	0x809ec124
+	0x71563d2a	0x2b7dffbc	0x5bb334bf	0x18ebce8d
+	0x3e434c67	0x4904d4c8	0xd233d209	0xca3cd2ba
+	0x7c618885	0xf68cce7b	0x35adbff5	0xf61e3d48
+	0x4cb3ae04	0xaa20201a	0x6f491596	0x0b934538
+	0x16a605f1	0x57dfc39c	0x7aceebdf	0xb6082f67
+	0xc36b7e2b	0x592f3f53	0xee3cf851	0x76ec175f
+	0xabc73b4d	0x8d6dd974	0xca41dde5	0x74ab505e
+	0x8c15f4c1	0x9d41aa44	0xcc8fa5d2	0xa570465e
+	0xbbb630c6	0xfc977e06	0xa8b1775e	0x1f4dc519
+	0xbabada41	0x91b2fad7	0x1135566b	0x567652f9
+	0x1d0f955e	0x57c4c2dc	0x660bd5a4	0x59c92987
+	0x9d695aff	0x88aac7a2	0x20308598	0x8e12997e
+	0x29c5181b	0x53ae2439	0x7862d015	0x1626cc32
+	0x10f95eb0	0xbb25f25e	0x03b241ba	0x9bdc7bd5
+	0xf6106050	0xf5154783	0xe080521f	0x061e86cc
+	0xb2ca16e9	0x915f0a4b	0x8f4325c9	0x1a5f2ac5
+	0xc976520b	0xe0717cca	0x5ac6e76b	0x1f62f48d
+	0xf31e76e4	0x8c3a146b	0xc87d8c2d	0x8ddee751
+	0x8bf4db09	0xd2a686d8	0xf216b59c	0x911ecfcb
+	0x65842c11	0x630e6a6b	0x48985e2e	0x9e94bce5
+	0x5cb2afaf	0xe31d5ef6	0x7806074c	0x7744bf55
+	0x1355a6bf	0x388865be	0xb9d900b3	0xea2bce11
+	0xd0228c4d	0x816dd5f1	0xb3654090	0x6c296240
+	0x5956a149	0x402672c4	0x42830ea7	0x8099a3ef
+	0x1b0d2d24	0xc4180b6b	0x2228bf23	0x6ad12711
+	0xb41611de	0x34c8b9e6	0xe301bdbb	0x495e50df
+	0x809d2864	0xb3424c33	0x7399f498	0xc91b39d2
+	0xfec47b00	0x2a2230d3	0x61341d6c	0xe7a75efb
+	0x8aede4d7	0xb20cf7f4	0xfbef0902	0x4459ef58
+	0x197445ab	0xa03e71a0	0x25f67b4e	0xddfcd1c9
+	0x52f4388a	0x5af77420	0x8ffe5b18	0xa29fce69
+	0xbb0a60e6	0x373b3ad9	0xa00e19a6	0x2db7e515
+	0x1a77ced9	0xbd039c17	0x374d5460	0x9ec3a1e5
+	0x77434c84	0x0c22e7d9	0x5fb76173	0x8646c434
+	0xda49e7b0	0x03f47da2	0xc4e5ab4b	0xd3555a92
+	0x9765dab9	0x4848b517	0x05c2b154	0x6e2b996c
+	0x44964009	0x76fe7858	0xe9e8467e	0x1de54367
+	0xd124abd0	0x41ae9672	0x521ae70a	0x5f7430a3
+	0x44695344	0x576beff4	0x50ae299d	0x616c731f
+	0x6144c083	0xf032bf4d	0x3e3cb949	0x7ead292f
+	0x2151c92b	0xce4708c6	0x93bb3ef6	0x5795f4ff
+	0xbc3ad2e9	0x5a65010d	0x0b96c64f	0xcc0cea06
+	0x50e8a9ac	0x502fdfb9	0x03de0aa8	0x696fc1bc
+	0xd8c23367	0xe966ac13	0xcdac2cea	0xb1103122
+	0x902a809d	0xd876e570	0x197ca73c	0x6be80342
+	0xe20bc0af	0x13558f40	0xff1b5f43	0x6c4968f9
+	0xf707bb0b	0x2bda4cfc	0x51de4ccf	0xd9361c61
+	0x2bfc555f	0xdbbd4b0a	0x4b9d588f	0x9a744c02
+	0xd909ddcd	0x91a05ffa	0x2d8d4949	0x35aa9505
+	0x9c6364fa	0x95515e59	0xace63492	0x9e33a345
+	0x724cc057	0xb9d449f5	0xa20f8526	0xe2ed31b8
+	0xa0e9d2e8	0xcaf765ee	0x247314b6	0xd91fad82
+	0xab9236cf	0xea5ee132	0x10c8ed58	0x71faf9e0
+	0x7dee7eaa	0x2470519b	0xd4c9d2e3	0xc56cc95c
+	0xbf1a9b60	0xc170f2e7	0xa8505838	0x863fcb43
+	0x1208ca84	0x07781d9e	0xbd944838	0x460a62d5
+	0x0fef3252	0xca1964ce	0xfaecaa6e	0x5312a7c3
+	0x7ec09ecd	0x0e4a64c1	0x0e4379be	0x6b1c1bc0
+	0x47170f9e	0x12615e56	0x97d30146	0x6cdd0cd5
+	0xb012c33e	0xd1d11658	0x11609a29	0x064562b4
+	0x869c8b99	0xf4e59989	0x84fdc9ba	0xddd6bcf6
+	0x5496a219	0xdb079dd5	0x244e6776	0xb0d8afe5
+	0xf14dba52	0xceec92d9	0x73d66ca5	0x55a79142
+	0x844cd92d	0xf79ced97	0x1857b9dc	0x9addd16b
+	0xcb87c2d4	0xcc47c5c8	0xf6216778	0x047364f6
+	0xa3f057e5	0xc47f4b92	0x49b65696	0xc8476f0b
+	0x6150cae4	0x83e956ee	0x84952a17	0x32c001f4
+	0x12e6c124	0x8733ed63	0xa96622de	0x2b97d312
+	0x3c93d154	0x4a43719f	0x5c94d4a8	0x89138d7d
+	0x59287d4d	0xb6be0aa5	0xe38463da	0x0ad5cb61
+	0x10c3dcc2	0xa649403f	0x763dad43	0x15e8796e
+	0x23fed728	0xc65881e2	0xcae78b38	0xecbfa6a4
+	0xe9f4d662	0xb49b7fae	0xbfe36a20	0x9e1034dc
+	0x816472f9	0xb3cf5e3c	0xfd9ceb35	0x64985d38
+	0x28e5462d	0xe617f874	0x9d1cc79a	0x14987e3d
+	0x48847394	0xe396e54d	0x2a9d37e2	0x90d2c038
+	0x4680ae11	0x8ab15c2d	0x12e5372e	0x18b67728
+	0xffd655a8	0x8c0aeba6	0x42c3e703	0x996c63e2
+	0x0a5ff71a	0x242c4779	0x33068ece	0x59abc18b
+	0xea60c431	0x5992a226	0x5041dccf	0xfec6e22c
+	0x11146c09	0x77be906c	0x82879c44	0x51129cc2
+	0x77a9a0dd	0x3c68d1ca	0x02049622	0x10cb7324
+	0x9309b245	0x42bfb895	0xe011f9c4	0x0a907dc1
+	0xc3351de0	0x2385f003	0xf2d22a22	0xaa760f2d
+	0x38d628bd	0x71ef5bd7	0x37127450	0x446928a8
+	0xbb88d4d1	0xf46e188e	0x224cd2a4	0x4f56954b
+	0x70674ab6	0x9be90549	0xafd18245	0x4689e00c
+	0x07d8e74b	0xfe6a2759	0xa6847004	0x7025494a
+	0x2ef97b21	0x8aabbf03	0x46cdad16	0x2b300203
+	0xa22dcb97	0x2c643664	0xb721cff5	0xbfaa532b
+	0x9173a582	0x0a7c7658	0xbcaa4bd2	0x3c4c82ea
+	0xc1b1ebe2	0x1000d5db	0x178850da	0x2276213d
+	0x1cde5666	0xecdb0d8e	0xfef90d48	0xecd4d1f1
+	0xa96103b3	0x935c5a02	0x8e6fe155	0xd047165d
+	0x3002cf6e	0x9ae52c60	0x62cc7175	0xcafeeb88
+	0x826c0adf	0x4ea5baa1	0x085a2723	0xaaf5f994
+	0xbd599d45	0x8c7084ab	0xff2acaf1	0x96fe0230
+	0x4a22f285	0x710eb741	0x3f941922	0x0b2ca014
+	0x6b6619ec	0x1ac478f2	0x7d74461f	0x89668c79
+	0x3b9edd59	0xf51c425e	0xff6e246c	0x915b68ee
+	0xa1142d51	0x62409991	0x543f5f49	0x8579d5f8
+	0xf97989e0	0x98d23c87	0x393a9364	0xe56329cb
+	0xf62cd0a4	0xaa01e22a	0x5bc6c70e	0x1db499e2
+	0x2e35dc25	0x88d5fda4	0xb9204812	0xe282e4e8
+	0xee44d3f9	0x7c2374ca	0x9558fbe2	0x0df70c02
+	0xe78efdfb	0x4caf264e	0x757e955c	0xa06a145d
+	0xcdb5abc6	0x10633804	0x381ef262	0xee9d22fd
+	0x1922ed89	0x17c41f08	0x78db4265	0x47353c26
+	0xd741f54b	0x98f1e3c0	0x2843a6e1	0xb9fc4eff
+	0x30ba0638	0xf1e2fb9d	0x8c8f03c3	0xe300fa41
+	0x2a0b4a8f	0xaa66ca88	0x0372d9c2	0xbf1b3283
+	0x6d7bb883	0x073b7f90	0x90ea76ab	0x7adf3d37
+	0x94b412d4	0x2b788f5e	0xb76fa8cf	0x2ee0492d
+	0x2d30b5cc	0x097cb48c	0x26147e08	0xea57884c
+	0xe1bb97d9	0xd671b4d6	0xb9f45ee6	0x709ed07b
+	0x89e791f7	0x50a0abab	0x59bba13b	0x4c95ba8d
+	0xf06faf1a	0x9eba91ea	0x203a0896	0xe9180d97
+	0x2c747ad1	0x2bd9fdc3	0x9b66ccaa	0x511e730c
+	0x4d4afe59	0x261d4191	0x431f33e2	0xa537e847
+	0x07f3db81	0x0c553226	0x8fb5e7f5	0xdf27bec5
+	0xa91bf277	0xafb9ea61	0xc0c18350	0x96ecd71e
+	0x65713a84	0x913d77e0	0x740d13b7	0xb7524399
+	0x96d50b1f	0x3c33cc3b	0x1ffd3ccc	0x220fe9cd
+	0x13ff2a0a	0x7737d122	0x282709bd	0x66aae30b
+	0x2578d841	0x73c6ae19	0x77d5a00e	0x54705866
+	0x702c38d0	0x642437ab	0x97888628	0xc92ef39e
+	0x05ff9fc3	0xeee7a2e0	0x08c849c4	0x842988c7
+	0xff8e3d16	0xfa73e115	0x7a152edf	0xb4191cac
+	0x0c9eea26	0x5dbb6b97	0x922fc1e2	0x3c727b29
+	0xe447a6d9	0xe6428089	0xa1c2a174	0xa4b85d60
+	0x5f08cbdf	0x2015182f	0x754c5beb	0xa06453e0
+	0x20493816	0xdf17b930	0xf55bbe8d	0xdc28116b
+	0x7c8b4c37	0x87ea1da1	0x8268b17e	0xd4c4fe34
+	0xe2df10c2	0x240aa809	0xb0916d20	0xe96f934c
+	0x8cc175b4	0x478cf279	0xae91f6ac	0xe09c1b44
+	0xdab45144	0x6fd51ca0	0xda83d37f	0x37bf81df
+	0x52fe608c	0xb3f37371	0x156d69d5	0x12b9c82b
+	0xe7bb0089	0x01ae780d	0xe3f7be6c	0x32989ddb
+	0x971fc124	0xd9048910	0x7166fe08	0xd2724c31
+	0xbd2596e0	0xf7b5d8f9	0xcbb76a30	0xdbbbe890
+	0xe506ffa8	0x5932d8c4	0xea064da2	0x881c72ee
+	0xae1ea9f6	0x50a5c29d	0x5388f42f	0x213b990b
+	0xeb38f978	0xfb81832a	0x702338ae	0x9264d6c0
+	0x9640aeea	0x4f01ee0f	0xd99fe781	0xd9e8b556
+	0x35653091	0x0e2287a2	0x90b7f886	0xd4bcded0
+	0x4b964aeb	0x95271c62	0x12c8860d	0x196c92ca
+	0x8e4edf59	0x4907f388	0x9d275902	0xb9009a4a
+	0x30ecdf04	0xfbf86b10	0x94b946bc	0x5757c752
+	0x916f5c3d	0xd4a080ea	0x7dceecff	0x42dccf57
+	0x97ae2be6	0x4052d8f2	0xfb5cff0e	0xacb3972f
+	0x2fdbea67	0x44fd0087	0x2c8dd356	0x702872f7
+	0x5bdf98ba	0xcd436c1d	0x4cf42708	0xbb9b848c
+	0xafc7e684	0xe0ae15e5	0xbe77beb7	0x5465f78d
+	0xa1a5c3de	0xd7d1bf37	0x293dabee	0xd83985ff
+	0xb966b1e3	0x77908298	0xc814783b	0xf43be773
+	0xc7704e0c	0x7f6d46b0	0x1e9eae7b	0x2e110f7b
+	0x2c3e8cd4	0x198263e4	0xf49bbfe0	0x1ddf332b
+	0x2619d305	0x1c4f083e	0x218695b2	0xf6e9eb91
+	0x2bd46f27	0x8c903e19	0x77c69dc8	0x49ad5596
+	0x9b1e4064	0x33af259e	0xae57d885	0x0f89d69a
+	0x1a3c21c4	0xfa8d3523	0x33e1e79c	0x466a8b05
+	0x5318e75a	0xa64c31a2	0x9e8b489c	0xfa3dd512
+	0x19b504fe	0x087795ee	0x1a1119d7	0x92fd5dc4
+	0x161db69e	0x9b8246ca	0xa4f164c7	0xfa1310b4
+	0x7c761994	0x07a9bfd9	0xd76cda4e	0xd220fd89
+	0xfac3a0ab	0xa35fd4bb	0x103319e7	0x113cecac
+	0x8a0b2dcd	0x39001a5b	0x803e3006	0xbe2e8a0c
+	0x256961a0	0x40cf27e4	0x4229799d	0x14a30f23
+	0x23d80ad7	0xbb1082b6	0x1325fdc2	0x41082eb9
+	0x2c531bcb	0xd1c2c909	0x6b68d5ad	0xc7cec053
+	0x95119d6d	0x8cc85ae1	0xfd204466	0x0dd7b4e7
+	0x930de6b2	0xf0386cb7	0x09867321	0xea6aed3e
+	0x0bc79d5a	0xb2d88c9e	0x387fc5be	0x264b3e24
+	0xa962b5d4	0x6f6fc6d9	0xa1b8a9d4	0x65b61263
+	0x91383a61	0x6b1e8571	0xbc902055	0xbc53cf50
+	0x4fe8e29a	0x048ff6ea	0x9a7d949c	0xa83ceee6
+	0x25b5c85a	0xa10a7511	0xf606a949	0x57b41656
+	0x230afe7f	0x73d65619	0x9819c9cb	0xea609f2c
+	0x4bf6fe21	0x4de72091	0xc439faca	0x58ac932d
+	0x36944d39	0xd046acde	0x8495bc22	0xdb20e8e7
+	0x537d1619	0x8c96eb24	0x8f0dbb8c	0x2461b9b8
+	0x1f9e9c0e	0x0e58f1cd	0x196ecb76	0x7ce9198c
+	0xfbea063b	0x06d810ac	0xa5acf2e2	0x2742822f
+	0x17aa581c	0xb214addc	0x6b8da387	0x3a66dd9b
+	0xa28ae955	0x347f5607	0x755e2679	0xd76cc2e3
+	0x80a38077	0x2a85effc	0xc42f63c5	0xba4f0c04
+	0x2df3075f	0xe119e31b	0x74c09c92	0x8f0de61e
+	0xfd1c0d09	0x0e03f74b	0x3730c527	0x8913961a
+	0xda9a8573	0x0d060655	0x41e91539	0x2f145441
+	0xac24e688	0x71df76c3	0xdd88e778	0xd082154d
+	0xcc87a1cc	0xca1d5469	0x55a9d11e	0xa1496402
+	0x5328879d	0x01130306	0x0fb6e89c	0x6a88d6f5
+	0x2c35d644	0x64787df8	0x0cda642c	0x050d559f
+	0x34d986cc	0x4d46a0c6	0x16958610	0xb095b7f0
+	0x42344d4a	0xaebcc04d	0x38cd1303	0xf55ef5fd
+	0xa2229e10	0x1c84dd21	0xc751cdca	0xe70e4d92
+	0x7cfbc446	0xc346c504	0xd1d0c3d0	0x1a11f80f
+	0x4c3d3092	0x860608e8	0xc629974d	0x36b7ba9b
+	0xa6954e66	0xcddd2377	0x2484d0e3	0x16364b7d
+	0x9f5cff4f	0x510b68a4	0x3f66ffc0	0x3fd56799
+	0xe0e9ee0d	0x2733808f	0x91e062f9	0x0194bacd
+	0x7d0758d6	0xe5c3b76e	0x877cca91	0xb1c6caa6
+	0x6d8390c1	0xdbef1e02	0x4900b2c5	0xb9d48fd0
+	0xb86444ca	0x4b32cf44	0x9d52f809	0x5e465a79
+	0xa654d13f	0x5005bc4a	0x2ff38509	0x90a06923
+	0x567912ad	0xca101885	0x9d2362e7	0xf5dcd206
+	0xd8b2de97	0xc9cfbff2	0x850b73b9	0xa9cce812
+	0x1c89f5c1	0x0e93ca25	0x26977294	0x00651015
+	0x3b6ac439	0x2454a988	0xff2cdd4e	0x0d90452a
+	0xbc9f8a09	0x93f1c4dd	0x650c020a	0xfb9b37df
+	0x2f7211bd	0x9cfce13d	0xb02cb359	0xe149b294
+	0xe6c478d6	0x0ba8d9e3	0x3e8d6b1c	0x28549a36
+	0x5b389e02	0x92d73111	0x33053a24	0xfb4295e8
+	0xc31f642c	0xcce6d7b1	0x19256f9b	0x05af3c0d
+	0x46c876d7	0xf3cb570a	0x5b3419c1	0xeeaf101a
+	0x2415133a	0xa5e5d7ff	0xdfbfa790	0x5fb1acc9
+	0x4b411267	0xfb5f01ae	0x44c85d60	0xf574f2be
+	0xed6951a3	0xc72b9616	0x7a400d1f	0xafb1f5fd
+	0x036d3f4d	0x00426a64	0x10152052	0x16fbc209
+	0x5eb41a25	0xbdd91d58	0x23a593da	0xe99994ed
+	0xe1dfc74c	0x2ace293f	0xcffca29e	0x3f9eb981
+	0x46b74da1	0xa08addc5	0x2e4db3cb	0xbb35bd91
+	0xcf047df0	0x9f000bc2	0x095cd891	0x0e8b0afd
+	0xdc862db2	0x381de055	0xfe5b209e	0x98a6ce93
+	0xe07ec88a	0xed2dace1	0xb5f6ed90	0xa59a3995
+	0x3987443d	0x56650b10	0x0a8c01f1	0x28599c21
+	0x51817fe4	0x88ac9845	0x8a5d7b55	0x89a15b17
+	0x0457e30a	0x9ecfdfff	0x03c7290e	0xf14c569e
+	0x88963e60	0x7bc5e18d	0x595ac0c1	0x29f34d31
+	0xd0870bde	0x58fb1622	0x2736799a	0x20c6ab00
+	0xfd606ac9	0x5931c90f	0xe93eb3aa	0x78f4fdb1
+	0xe3c0b354	0xb02dcb2e	0x028635b1	0x6084413c
+	0xbd262370	0xdd84b981	0x50f4cc00	0xc2a13e6a
+	0xf195d7d0	0xa568ace4	0x3506ccda	0x1a7b1e49
+	0x6b623dd4	0xd5b43db2	0xbd2db225	0x5fc0873c
+	0x07b0e0e0	0x8a7c7240	0x51d21461	0xe39acfe0
+	0xe8b1d0dc	0x319cc88c	0xdbb0501c	0x2d530ef9
+	0x6796f013	0x8d7c42e6	0x64840fc6	0x95f18131
+	0x14128fee	0x06ed7694	0x053701e1	0xa113706b
+	0x7efa1437	0xd988408b	0x15a55f2f	0xdf2da6de
+	0xe1637888	0xa6eb0132	0xe5a49f75	0x13421229
+	0x76b358d6	0xfd430ce4	0xe4b54719	0x4d373720
+	0x2363e083	0xc7c3365e	0xd2c691a7	0x337ba782
+	0x85f0e27b	0x6f270f7b	0xda2e7bd6	0x86aa4e8c
+	0xfccea641	0x4ccffdd1	0xfba17e58	0x48f98550
+	0x7fa85f31	0xabf971fc	0xd24dd6a5	0x2a360f9b
+	0x955234ec	0xe75f238d	0x76ce3dd7	0x9dcf7973
+	0xd90c8737	0x23aa80b6	0x9e4f45a2	0xc8e22d59
+	0x9e74d525	0x2cdeb43e	0xeddedd26	0x14b8ca5f
+	0xd42f6bee	0x4ea5803f	0x772d0ebb	0xe7990ff2
+	0x02e47c5b	0x1c88d149	0xef43755f	0x6482ddcc
+	0x1aa8c862	0x169fd30b	0xfe19600c	0x79253784
+	0x61d94629	0x078a3859	0xfed2680b	0x8bb14474
+	0x9fe0981b	0x0e4cb157	0xbaaedde2	0xff3711ec
+	0x1c03dfb4	0xdb4f9346	0x67faa4c0	0xa9fda842
+	0xd1a08a3b	0xb675f6e9	0x2eed32af	0x54169c1d
+	0x2ab8047e	0x0fa33847	0x69c4eda5	0x4f47713c
+	0x8186f17c	0xc68e0d8e	0x1e512fa9	0xb200eabd
+	0xefe05879	0xec521f72	0xc3b7670f	0x06d96a0e
+	0x830dd6f9	0x293926e7	0x49355c40	0x4bfa924b
+	0xb19404fb	0x4cfcf114	0x39f09bee	0xc5959edf
+	0x17e43b2f	0x36b8cb37	0x48d36720	0x87142d1d
+	0x4dcac00b	0x346a77e0	0x833ec251	0x180a0eb8
+	0xec827f6f	0xd389e5b4	0x193666a3	0x40deb1ef
+	0xeb287db0	0x59d72fdd	0x16c01b8a	0xb2f21a23
+	0x78fae723	0x96704b79	0x1cfa8eb2	0x3174d946
+	0xeceb41a1	0x8af02dd6	0x19b3cc91	0xfb452b01
+	0x185564bf	0xadca8abe	0x5dc86f8d	0x6f8752d0
+	0xef5c4281	0x57053d43	0x84ea5d02	0xb4d2053f
+	0xd5f4c35b	0x907f2a8a	0x782ec949	0x773fd7bf
+	0xb71de809	0x6ad67473	0xfc0f2916	0x7e011263
+	0x8388249f	0xc222cf7d	0x1b8123e0	0x2315de70
+	0xd8cdcf39	0x0181feda	0x6e39af97	0x0b77654e
+	0xaa0c9e17	0x863fc367	0x0615d44c	0xe29b86e6
+	0xa1948dff	0x6d4e1893	0x40db2923	0x4d9b1c95
+	0x4803e7f5	0xfaff923f	0xc1031c3b	0x8ee8b451
+	0x31288c50	0xab825d13	0x1c1473b6	0x08b41dee
+	0xb714574e	0x574040da	0x583db761	0xd3d2139a
+	0x9fb3f39f	0xa0cf0027	0x315521b8	0x4c1f5cc9
+	0xdd80b461	0xf1460806	0x0f0ae57b	0x2b8258c6
+	0x4578a951	0xc16a1b9e	0x147faa8e	0xc96ec7a2
+	0xd03de9cb	0x8df8317e	0x0a619904	0xa65850b3
+	0xff6b05f3	0x5f645c92	0xce69f994	0xa1846ae9
+	0xaf8789ca	0x08dba3da	0x08dda80c	0xe8e396d0
+	0xd9478844	0xc47706bc	0x2f56c392	0x0032ce69
+	0x1e25b40c	0x07d67e34	0x2148bd55	0x9b196864
+	0x7955790a	0xeed52b37	0x6e7bb914	0x3ffe3c36
+	0xe65f8946	0xac51ada6	0xae9b3001	0x5bfd4896
+	0x5d04baaa	0x744c6bd8	0xd8d6c510	0x25d25740
+	0x1f97ac5b	0xc37f23a2	0x17fa1b4d	0xed300b12
+	0xea71b408	0xceeed65e	0x96db804d	0x709d79ae
+	0x20546660	0xbab82134	0x51d74293	0xc02a65c9
+	0x0b1ec776	0xf2b31fc7	0xcba74077	0x4f0c1ae0
+	0xc07f66ea	0x170f1224	0x4acb1ec3	0xfc7b9cde
+	0x07e006ab	0x9da5ed04	0x8370e78b	0xc39691c9
+	0xed854623	0xcfca7c05	0x3d2e700b	0xfc52eccb
+	0xf5c71a7e	0xe4cc4143	0x9164e2b9	0xfa7fabd6
+	0x505ff063	0x2859ed81	0x776b50ed	0x3b15d21a
+	0xd2f03b4e	0x8315f3af	0x5269b9d8	0x31bd7c3f
+	0xf99d8e31	0x7df70284	0x568956ef	0xbe3d74b8
+	0x8fbed915	0xc4e227a4	0x689efb23	0x3d323ff1
+	0xe225e3a6	0xe1fc3a94	0xf988514d	0x161b6ebd
+	0x712dc25e	0x21aa2ce2	0x6c630ed8	0x789c1bbf
+	0x7eddd464	0x2a79f889	0xc7c0f496	0xda39e80c
+	0x6fc17a39	0xed41038e	0x42491e77	0x0097fdfc
+	0x25083426	0x0ed5da03	0xa867753b	0xf2629247
+	0x6bf18213	0xd33549e6	0xd127896c	0xbd2440ba
+	0xba184a7d	0x5f534e5c	0x12fe02ae	0xe5234798
+	0xb3e47348	0xad96a97a	0x177e5fe4	0x62a0ebc4
+	0xf74d4d2e	0x2667eb23	0xca156680	0xc2d6ef24
+	0x8b03cd6c	0x65cdd0a7	0x02a17a02	0x1e5d73df
+	0x8d3d1985	0x634424bc	0x6e332211	0x8f619bb5
+	0x2e57902f	0xfc18e1ea	0x5327dfc5	0x249904e0
+	0x6c7e15d6	0x4c93e017	0x72b72678	0x47e3a4c5
+	0xf925b0ab	0x861b9efe	0x2110a250	0x02d111cc
+	0x01db264b	0xc78ffd32	0xd35b62ef	0xc5e26509
+	0xaddc32b8	0x7384adb3	0x14dd80ed	0x6ea3c9a4
+	0x8846201e	0x43f496e8	0x18dbde7a	0x9382de97
+	0x2571ea26	0x73e1c559	0xbf0328fb	0xf54e01b2
+	0x787b9baa	0xcda5ae3d	0xa7f7c5dc	0x794063e0
+	0x6050f2e3	0x3d067abc	0xcd348208	0xcb7c206a
+	0xdb0f590b	0x0556823d	0x9daafb23	0x68de4801
+	0xdd3d5c14	0x153ae055	0x379ae503	0x05a4d468
+	0x35a3809d	0xb41a49b6	0xbabb51f2	0xa9ade96b
+	0x2eed4a4e	0x682e04cf	0x3fb8a3b0	0x71a6e838
+	0x6b1924f9	0x2325ba72	0x4bc9513c	0xb95807c3
+	0xc7e5c617	0xe0eb5303	0x22e25ed0	0xd86c0256
+	0xbc03456a	0x985b81ce	0x9c2ecf75	0xcbe1292d
+	0x12aee1a9	0x6f83c685	0x20e348a3	0x9576eb55
+	0xad06f6fa	0x36293aea	0xf587b498	0x73e5eb09
+	0xd47e5cfa	0x9379d70b	0xb87fa431	0xa4791f08
+	0x003dd242	0xe64437bc	0xae50505a	0xc5a337ad
+	0x9a63bf9c	0x9fb46dd8	0x06d6d6b6	0x1d557c65
+	0xe19a751f	0x8851e1ef	0x88474420	0xbda6a5ca
+	0xe5c570d1	0xbd520d15	0x9c991349	0x774847fb
+	0x09062314	0x74ffcd56	0xf244496a	0xbc822fe7
+	0x6619f249	0x19ecf3d9	0x0356ec07	0xc754b087
+	0x0c2cc5b2	0x0a928559	0xa63defac	0x2a1016a5
+	0x59f9579a	0xa32ac751	0x880156e7	0xfa98f785
+	0x561f9243	0xf8ad3b44	0x88d09686	0xb7656804
+	0x1d733be5	0xf835036c	0xd9854eb6	0xe3d3e252
+	0xa335451d	0x6cef2f72	0xed2d8bad	0x40ccdac7
+	0x026ccf2b	0xd8907e8e	0x6b9dcb88	0x6db1b016
+	0x88b67853	0xf169c4f5	0x71d030fd	0xe3d0e64d
+	0x331b875e	0x14156d9b	0x8e34aaf6	0x735eb827
+	0x7d96125e	0x757b15ad	0xa501ab24	0xc155f8b0
+	0x9c49cd8e	0x5a8e7118	0x74af8bb1	0x9e8de93b
+	0x07687721	0x5ac42b56	0x3042d915	0xe30e20e2
+	0x94a1e376	0x73d34595	0xce30d8f5	0xefafdcd4
+	0x67a242b1	0x27dc9594	0xf8fae52f	0xc4f6ceff
+	0xd0ffedf7	0x493359e6	0x1deda1da	0xb944d24d
+	0xf483b532	0x40396343	0x312c13a9	0xfa616fdc
+	0x5e318d6b	0x57bb126a	0x79433a17	0xfdae5d08
+	0x24350f44	0x42b9819c	0x8c3e4914	0xb8fd955f
+	0xb66519f3	0x03376aa7	0xc7b35448	0xec75d467
+	0xf861dde6	0x75d9ebec	0xcbc3e8ca	0x5e6d47e1
+	0xe7e499fc	0x6123c26e	0x19fe2cc3	0xde86af73
+	0xf0de8655	0x230a6313	0xe484cae8	0xf160e445
+	0x7c3ad8e2	0x29a2347d	0xcab560e0	0x737c2d14
+	0xb60d784e	0xe34dc241	0x39124427	0x632bb7af
+	0x150080d6	0x2988d6b3	0x435e4222	0xbc26852f
+	0x2cd7e704	0x0e2a05b2	0x1c41169f	0x07c41b03
+	0x0346f767	0xe96b6733	0x54dec6b6	0x8f2d3c90
+	0x1fe618fa	0x75dddb13	0xc9ba2a28	0xe9cc9369
+	0x2c8e53d7	0x3f781a20	0x5791014c	0xadebd041
+	0x855aee45	0x996d5acf	0x9f7219fe	0x94a426a2
+	0x779c04fe	0xd8a5f141	0x9ae3cc2e	0xce57a8ee
+	0x4865de61	0xe14d8d5c	0x98389084	0x81bdf77f
+	0x72aaab47	0xb11b1e31	0xb23c943d	0x65b0e428
+	0x9d2fde62	0xd64cfc1a	0x9ded7094	0x1446e84f
+	0x7b660a21	0xc26c252f	0x5ea92407	0xcc2dd193
+	0xb18d6c04	0xe08faa12	0x84366ee1	0x53dd342b
+	0x88f99d7a	0x97754233	0x54777ee2	0x72103530
+	0xffb77bdd	0x67c3f3f9	0xd1e9396f	0xf7e91a5f
+	0x1ca09c1d	0x148dcedd	0x4812f994	0x734bb2a8
+	0x4c616674	0x79e0669c	0xcc3695a0	0x965c6b99
+	0x54b4bfe6	0x24ff8fe7	0xf227fa4d	0xaeee1502
+	0x2207334b	0x444d4768	0xd1c3e5ac	0xc635e962
+	0xa5fdc383	0xd642360c	0x0bb1d6bf	0x40eb05b2
+	0x563d58c3	0x37ef1c49	0xdbdef02a	0x5c954622
+	0x249cd7d2	0xbc00f7b7	0xb9d311b0	0x84ebdfc0
+	0xb777296b	0x8f922505	0xe3007f02	0x45369d3d
+	0x1b1ef9ca	0x9434faf1	0x955491fd	0x918dae49
+	0x2c55e53d	0x2bb5e664	0xe306a3da	0xe9a4b542
+	0x74fecfe8	0x315d2566	0x42ce0ebd	0xfc8b2c09
+	0x4503579c	0x0194db62	0xaae82e99	0x638cc58a
+	0x6253580a	0xa9e134a9	0x7cf09364	0x2a0f2762
+	0x555e0f4b	0xcaf84599	0x88ff57dc	0x760f71b6
+	0x5f3b52b0	0xf8762c98	0x37d45f0d	0xcefbb54f
+	0xc99699c0	0x54638fd8	0x5d116ae9	0x0b125847
+	0x88aa62a0	0x8ac7b007	0xa97c115d	0x128e72e1
+	0x035d5aa7	0x5d16a915	0x9f1ef842	0x8e23b89c
+	0xb52d59c8	0xc048bbf4	0xca42c82d	0xdc85185d
+	0x0011465f	0xbb025e83	0x9ea0ffe0	0xda4c0e4f
+	0x89401781	0x7a3074d7	0x878b8546	0x9370c686
+	0x5ca6f5ec	0x96808035	0xddb4682f	0x5a616b12
+	0x57618954	0x0e3f255f	0xd3072641	0x8eed8068
+	0xb8fdf1c9	0xb417e2ba	0x9c613492	0x75c3a921
+	0x2e7e0223	0xa9a68825	0xef180ab9	0xe2550aff
+	0xf743b61a	0x92b02868	0x2e4d4a92	0x094055f0
+	0x5b901d5c	0x6512ecc1	0x1d6d35f0	0x114f6a1d
+	0x40bf1f43	0x8e7ba25d	0x8cee3d80	0x5df565ca
+	0x29403904	0x27cd7367	0xad48535d	0xa6e54d45
+	0x24b9e3aa	0xe301871c	0x53e21f70	0x514fb2e2
+	0x937c0248	0x82624d35	0xbbf2a9f7	0xd7b6e482
+	0x21c76f4d	0x430c1bea	0x445ba31b	0x7732e9d2
+	0x19175315	0x712cce54	0x56d653ba	0xe55361a9
+	0x7543f198	0xa8f9e517	0xe8ec0529	0x4681a1aa
+	0x3edd8dbb	0x8cec11b7	0x6b6f0bc1	0x8b9256a7
+	0xb5e86885	0x1a2d632d	0x59dd488e	0x4d529b15
+	0x87d3b0dd	0x3e334eb0	0x8ecc38cc	0xbcd42c7d
+	0xee7b85ad	0xf8db1ebc	0xf7242be1	0x936c4ad5
+	0xf0d3e133	0x15b21e10	0xe13ccd7a	0xafd28ab2
+	0x86f873d4	0xe75498df	0x1cdcacc7	0xa0952f4d
+	0x9c1aef8d	0x4c45d667	0x1ce18e2b	0x95e753ae
+	0xd3cc14c1	0xbc9d6c08	0xb9bb31cd	0xc38cfc3d
+	0xa0f90015	0xe71ec516	0x89996ee4	0x3ca7b1bb
+	0x5cb81d2f	0xf83eba1a	0xd4c7f0ba	0x0fa3724f
+	0xf70fc314	0x6bddc2b5	0x6b5b73ca	0x7fbeb86c
+	0xdc04567c	0xbdee5488	0xa5e84cf9	0x2d923cd3
+	0x10affb44	0x7072a096	0x569c6186	0x73b955ee
+	0x5f51325b	0xdbe6d601	0x80a09027	0xdce073bd
+	0xc4a57e68	0x8e36feb7	0xe95f03c6	0x24536972
+	0x7e9d0914	0xae891f9f	0x71b00cfd	0x4ad1d3cf
+	0xb0c12a1c	0xe6ae12ac	0xe55fae1d	0x41fa24e1
+	0x26ac1069	0x07f63225	0xdc6af020	0x736be557
+	0xbd81cca4	0x0d970e26	0x00aeee65	0x5a95aa6d
+	0xe11d862b	0x73445f3e	0x9debc7c6	0xb9fb9316
+	0x70c80f6b	0xdc3b462e	0x98e55897	0xe3c038bc
+	0x1e6be1e2	0x6b73a471	0x6b08dee9	0xc11316c9
+	0xa03ccd1f	0x9850a735	0xf6f69d7f	0x5f84661a
+	0x35124e9c	0x580021ad	0x83f5cc8f	0xbf6299b3
+	0x87a9300f	0xbfdeac53	0x3e71aa0f	0xef0f924e
+	0xa05ccefc	0xdde79132	0xd37fab59	0xf09bd0f0
+	0xe3d45f0b	0xd800d032	0x23b74559	0xccbaf882
+	0xd7482f3e	0x19b61427	0x8812072d	0xc7b547d5
+	0x3d77bbad	0x16a7a565	0x613512b0	0x1f5941d8
+	0x15c469c5	0x6b594868	0xea78dc23	0xb7edca03
+	0xec75b400	0x85960837	0xe295e802	0x442d5aa7
+	0x1a505b0a	0xb7100575	0x126ab9c6	0x30fc8981
+	0x33d1c5e6	0xe7b36f3e	0x2529f025	0xf7de09a4
+	0x9a237b73	0x4199b6e5	0xcd0ca5cc	0x483c7496
+	0x18a082e1	0x49d36b6a	0x29194f20	0x256236fc
+	0x7ea67a7c	0xf9902240	0x29abc52c	0x58178309
+	0x8d87c634	0xaddfa3ac	0x26a7582e	0x22a46c59
+	0x30275956	0x823d736c	0xc3fd5992	0x49151051
+	0x6f7e26a6	0x69f61e26	0x151611e6	0x0c0603d3
+	0xd472a6d9	0x3b41cc64	0xb2cc8f30	0x361a119b
+	0x2a6325f8	0x6068c424	0x770c3284	0x72ec88bc
+	0x833bbba5	0xa70802ca	0x32a5545e	0x5c22e9d0
+	0x5ab3d9f5	0x9007e5b7	0x24e39b69	0xd33bd9cf
+	0xdc9d6e9c	0x2b7836d5	0x757c6cc8	0xcae907cf
+	0x9e46c6d8	0x3bccb4b9	0xc66ab681	0xab9b12de
+	0x366df0b5	0x7f785550	0x258959f3	0x3a72720d
+	0xb4044294	0x11e76388	0x78006943	0x94321f26
+	0x09e5d3f9	0x2f82cd05	0xdee1653d	0x39b9ec91
+	0xc9012ee1	0xf885bae5	0x79493693	0x2b13808a
+	0x5376c547	0xc997b444	0xc581c3d3	0xbad42d8a
+	0x4901b3b5	0x968eee21	0x77455af2	0x10b0fa5b
+	0x20d71f73	0x575412ef	0xf205f541	0xc551b8f8
+	0x12773d9e	0x7561b494	0x8e5a2137	0xfa842331
+	0xf4a22b14	0xfceb868d	0xc3f356af	0x99c600de
+	0x9803462e	0x35bed02a	0x45f52576	0x3b87c4fe
+	0x92846fbc	0xfe85457b	0x5c17ab10	0x06ce7af4
+	0xced24e04	0xc0e6ae3b	0xb125d859	0x92364ba9
+	0x3a0042a4	0x910bbb65	0xf23b6521	0x5c0fab3d
+	0x3a3d8051	0xd213a5e6	0x16553ef2	0x3413123f
+	0xf7bb2e3c	0x174d8805	0xcc640b23	0xc4713fdc
+	0x9636237c	0xd71729a3	0xc301f9f2	0x63189fdf
+	0x88e96526	0x71b83d67	0x5e819dee	0x03b95fd1
+	0x50d95d14	0x6a3f8a67	0x23c337ae	0xe1863d6f
+	0x6c4b54ee	0x2d361ae5	0x7fe534f4	0x95c737b8
+	0xc9e50fe0	0x97c348cc	0xf007d43b	0xc6f9f79f
+	0x23d80edb	0x921ba7d4	0xae2ae8e1	0x67a7d17e
+	0x6773c41a	0x538aeedf	0xaae06e55	0x21150c78
+	0x2e80e133	0x99361ca3	0x717ea509	0x039822dc
+	0x18792613	0x55ddf173	0xc9c048be	0xd5e49d71
+	0x8adbc8a8	0x81200c61	0x6ae354ed	0x1a708d48
+	0xb349a77d	0x074143d8	0x2d0eac87	0xedacdf08
+	0xa964c6e8	0x3848583d	0x7916be91	0x7be53a63
+	0xe924661f	0x4fd00b9b	0xbfd03db2	0xb65d4052
+	0xd33500dc	0x73a5a54f	0x93c2a984	0xe114df2a
+	0x170408d5	0xecd50a31	0x9f20a1b1	0x34267201
+	0xbdfce32a	0xd8006ace	0x9732c7a5	0x3334c162
+	0x6ef73bfc	0xbfb4ae2f	0x68eddc82	0x2421d413
+	0xa75f7db0	0xb68d99ae	0x3b77b2c4	0x2e5f5aa2
+	0x18a02c7d	0xaecfaf69	0xa798a7a1	0x1710b58d
+	0xdda63c42	0xc0b9f0c1	0x6e98ac03	0x0a6ec04c
+	0x65b6d31f	0xbb420c7b	0x2d0ae4cd	0x073969fa
+	0x075ab187	0x37ebf9a4	0x75b32e70	0xf4e3b50f
+	0x072c13c7	0x629d6d10	0x692a9f39	0x9d424951
+	0x7ccc6e4e	0x0df85aa1	0xaae96b53	0xf0fbe227
+	0x79f4cba3	0x3a4cfe17	0x31005c06	0x2ee79ed9
+	0x175662a2	0xea67d5f8	0x6a585206	0x74ff608d
+	0x8d0e43da	0x46e465a6	0x8b3a1789	0xf58de200
+	0x7470ee83	0xf4b3081f	0xcab7b26c	0x679c03c9
+	0xb2f3e0b7	0x7b0ce5f0	0x54458cc9	0x10adf9d1
+	0xc6418621	0xda7db924	0x42c87af6	0xca18ee03
+	0xbbe316ad	0xffad751d	0xa90e2f31	0xa4f1b741
+	0x79b692b2	0x51c015f8	0x1ec279e5	0x0b66f53a
+	0xd873b167	0x86bb7c09	0x6250d31d	0xfc276aaf
+	0x1b912c09	0x033c336b	0x5e23abfd	0x4f5c8997
+	0xc674dd92	0xfa1817df	0xa56ca16e	0xec6b2cfd
+	0x2feac778	0xc468211e	0x8b60ac67	0x712cc8fa
+	0x4380f941	0xccc528dc	0xc71b2dfd	0xfb08d4c6
+	0xd493c636	0xa7783d6c	0xc7df0669	0x716e9db7
+	0xaf231a4e	0xda22d68f	0xe33184b5	0x3c207ff9
+	0x0318cb6a	0x42e7c8d7	0x4397e1fd	0x6b178ba7
+	0xf979d8e9	0xa968800b	0x3ef4c2f7	0x35386ad6
+	0x1c02b942	0x7a320432	0x2b210df5	0xd2dcfeb3
+	0x8151e49e	0x3fa01660	0x20b2c744	0x56869e1c
+	0x536b6037	0xac6a3c1c	0x7da9b889	0x510a284d
+	0x25e3a895	0x0dae3e72	0x54680194	0x5c8bac35
+	0x95037fd5	0x0dc924a1	0x06eb65b6	0x7e094b2b
+	0x34283775	0x5dd176d9	0xe30c266f	0x70249a10
+	0x2652882d	0x07b82677	0x6f200cbd	0x7cfbde35
+	0x7fb2004e	0x2c01c9cf	0x559cc8e0	0x61a1a572
+	0xfe7ae6a6	0x3658fd46	0x1f72b09c	0x716562d3
+	0xc3fd2552	0x4a7faf26	0xd1b88210	0xfcc8a888
+	0x9352ada2	0xc9649b3b	0x864ef2f8	0x40c3cc52
+	0x38c11046	0xf4b7b9e5	0xd3507c37	0xe0341177
+	0x8b02f6de	0x61e57507	0x7dec5942	0x20e67c7a
+	0x49c8d38a	0x6374e513	0xc4859401	0x3d83138f
+	0x90721624	0xcc979f52	0x43770516	0x4ce44048
+	0xfdcbbbba	0x195318d0	0xd4d67bbd	0xc3e3ca42
+	0xa9a993ef	0x04cf3ccf	0xdd53b6fa	0x670788bc
+	0x928dc8e3	0x459976f6	0x30afc373	0xaaa0421c
+	0x25014ae7	0xf15ea02c	0xa745d8e6	0xf1e8fc13
+	0x6e5d5330	0x2c6d628a	0x7a70b26c	0xe431d5c8
+	0x688f05f9	0x13af38cd	0xcead3e97	0x739092de
+	0xf947216b	0x9a7babcb	0x0ffb6763	0xa5aa9ae8
+	0xf555aec2	0x9524406e	0xe3c1aa92	0xddaeab00
+	0x9a8ed819	0x723cf554	0x510b9a8b	0xb0230e50
+	0x84e77af3	0x5ad3fbe9	0xda99502a	0xd87fad7c
+	0x90d91966	0x47afd789	0xc714548e	0x1bd44ae8
+	0xb6bbffb1	0xe212610f	0xa7be9aa5	0x2d7a51a7
+	0x58ad5cff	0xa69a29f2	0x56650abe	0x60ef1148
+	0x41c878ad	0x99e7cdd0	0xf942c629	0xda11df04
+	0x68a8d833	0x837dc701	0x21c1c80f	0xac3611c4
+	0x9fffc67a	0x46b75e05	0xa297896f	0x5b461329
+	0x72c55e08	0x9069d0f7	0x12e2bc4d	0x0087d348
+	0xcbf33420	0xb4daf92d	0x852a7cd8	0x640647eb
+	0xb08e6b2c	0x7f3b928d	0x4c01bc4d	0xfca759ea
+	0x7106955c	0xcf4a3778	0x6f55efab	0x07447abf
+	0x0cff9f74	0xd42ff16a	0xa03f4bbe	0x7dc27f82
+	0x752e070f	0x573515a9	0xe666b080	0x993fc9b3
+	0x0538fda9	0x5e4a60be	0x5cd19062	0x54dd5d8a
+	0x534e1037	0x75fb6cdd	0xa1e2e1cb	0xa5697b97
+	0x71e3eaac	0x78ebda0a	0x9909eff0	0xc8c9917c
+	0xe52fdd67	0x99f087cd	0x25fc8e89	0x901c2ec5
+	0xd35c94dd	0x2df236f6	0x1373f129	0xfa2de0f5
+	0x9243449b	0x665b513c	0xace1a572	0x9058a604
+	0xab37ecf8	0x22e84435	0x76a79cbe	0xd95909d8
+	0x1b517a23	0x3105603d	0xf6a11df5	0x137c2f63
+	0x444603cb	0x1d763abf	0xb71c6817	0x46b6a93d
+	0x46a43774	0x96db6af2	0xa14bac62	0x695d653e
+	0x99897538	0x6a5780ff	0x58415eb4	0xb907ecf9
+	0x3cb7d6ae	0x4541d829	0x482562ac	0xc4de34a8
+	0xbc2114e7	0xf54eacfb	0xc5b65bf6	0x7c7b3db6
+	0x6c885294	0x5193ac1a	0x7e80e8a8	0x255e7372
+	0x71935b44	0x70599b03	0x7240a62d	0xcc8ab48c
+	0x4eda8111	0x554286db	0x54166dc5	0x7c8029d1
+	0xf79fc09e	0x418c4256	0x045c82b8	0x2de3c54e
+	0x32dac6ec	0x2a5ddc75	0x69be6373	0x22bf468e
+	0xda52d5d1	0xb123f760	0x3c4d7690	0x5e00046a
+	0xd3102e82	0x15e20bce	0x3425b5ec	0x4b28fe48
+	0x6a942095	0x79199aec	0x566369e7	0x27821292
+	0x3dba6081	0xf72378e2	0x8e06822c	0x59669bcb
+	0xbc891709	0xc6af2d1b	0x909e57de	0x7ed2b997
+	0xa06ce64a	0x0b09c561	0x00a1a65f	0xa11faa7a
+	0xe7d1e118	0xfaeeb687	0xd05b4158	0x3b4c1135
+	0x18c1016f	0x556841af	0x09d960f5	0x88a98a6a
+	0x841d61e1	0x54c4a616	0x2ef515db	0xaa6f8670
+	0xa1f4b97d	0x54bd1997	0x95ded232	0x82257303
+	0x3f1565cc	0x65d285a2	0x2828f910	0x7a2290dd
+	0x7f0a8e0f	0x96470c2d	0x8efdb971	0x790fa536
+	0x90b9d2f4	0x615c9b2a	0x5ec4f5ce	0xc7489b5c
+	0x2ab45d94	0xf7bb05cb	0xec8e149f	0x94bb8b1c
+	0x1a6fb3ba	0x77d22379	0x82a8e9d2	0xce732d90
+	0x7108cffd	0x03ded7da	0x06e86199	0x8e2c02b0
+	0xcb2c0281	0x4c49ee4f	0x4b00e705	0xf828ee69
+	0xaab31af5	0x275ee2c0	0xec247123	0xfded371e
+	0x440d3f1d	0x201bd35b	0x76e6b8c1	0x7cccc245
+	0xdc0403c8	0x2c539a1b	0x80db718d	0xb738778f
+	0x489698c2	0x78928e8d	0x7f241403	0x83b5aa04
+	0x99d19efe	0xc52c6981	0xee504664	0xab09e1a3
+	0xf1d99af9	0x3987f801	0x6f666ccd	0x41ebab71
+	0x954645a2	0x7d037670	0x2dae35fa	0x82b60622
+	0x761d5e16	0x0a2aad58	0x9706d97b	0x1347e659
+	0x274d4c0a	0x74e8f15b	0x63129b5b	0x901ad757
+	0x8777b117	0x44e63d79	0x8bd3b480	0x07108a1d
+	0x02e03a7c	0x923e9811	0xaab4b369	0x51fe2c08
+	0xdc8456e3	0xfe49f3c4	0x2954e5eb	0xc54dee8d
+	0x0f80df98	0x63aaba57	0xe45d04bd	0xb15d4d92
+	0x2c8d9557	0xa04d0109	0x309ea608	0xcb0738c6
+	0xe9dacd06	0xee68f11d	0x693a4dbc	0xb11287d6
+	0x1a2e0e76	0x10fdf2aa	0x9c7ea896	0xfd6d6a64
+	0xb45df9bf	0xb55eb016	0xec82d40b	0x8d1ed23b
+	0xff38e0b7	0x9e330c13	0x7d537ac1	0x12cf35ac
+	0x6e6c90ee	0x2941504e	0x783385a9	0xb311af56
+	0xc08a6072	0xcd4f0ef2	0x3e076723	0xff3d56f9
+	0x161acea2	0x2eff759f	0xa506452c	0xa5a71901
+	0x658eaa33	0x6ff385d3	0x57b6eb6b	0x6d66aeff
+	0xacf53aed	0x74eb0676	0xb47ca784	0xfde6497a
+	0xaba4fe9b	0x29f52e2f	0xe785df06	0x1a21f65d
+	0xe339fc97	0xbff4f394	0x635c50a9	0xe7993eac
+	0x169f7568	0x9afbd085	0x3790fd86	0x89708c40
+	0xaf08378f	0x8cddfe3f	0x512e5e7b	0x2ccac57e
+	0x432d49a7	0x922fe1ac	0xd0f7416c	0x2cf9ea13
+	0x0fbad9e2	0xb9282867	0x1bcdd5f8	0xd50eb8c4
+	0x6ee9c0af	0x1a109a02	0xa233e0c1	0x77cd4e43
+	0xfd9876e7	0x81c98fd0	0x226a35bb	0xfb975e44
+	0xc5e290a9	0xd2f46341	0xcfb8d819	0x66a7274a
+	0x94e02e2b	0xdf3ca2bc	0x2f1dd3af	0x78462257
+	0x490f62c1	0x5ea11bd1	0x23d01a6c	0xffb348fa
+	0xda323bb3	0x17fce38d	0x8924bbc8	0x37c696ae
+	0xc35e964b	0x696ecb76	0x63e8f910	0xe1ba966a
+	0xb3b00602	0xf47e8114	0x2615a30b	0xbfaeabe2
+	0xf8d5020f	0x12781ee1	0xc0ab16d5	0x90020b18
+	0x66845dd4	0x6e66a277	0x8572a535	0xf7797d8c
+	0x348de75e	0x86f89a83	0x64848b5b	0xd7dca20e
+	0x57d60248	0xd8e4fe98	0x3a17c717	0x176435b5
+	0x52ab4735	0x6f9f35f5	0x615f63aa	0x48cc2329
+	0x5aa3897d	0xee9999bb	0x92a2bb36	0x8d40208f
+	0xc76f48e7	0xe648c445	0x782c5ae6	0xf83280d7
+	0x47f0d558	0x8deffa11	0x6524c319	0x9f60b5f2
+	0x9a6b7d9d	0x200e1d14	0x88d0c8a2	0x38506369
+	0xfd64aa87	0xecf06513	0x8a26932b	0x8b27c57f
+	0xcfbff561	0x4ee1d390	0xcb61a62a	0x490d373f
+	0xdc60f0ee	0x457fa88e	0x804c0d6c	0x71b52b54
+	0x9174b1a3	0xd63cc831	0xb65bbb2a	0xe47078b0
+	0xf526f67a	0xa722a8d7	0xb3f347ac	0x443ad7af
+	0xedb9147a	0x4393902a	0xbab30f17	0x2ac69afe
+	0x41fa55ff	0x88d1b1aa	0xa3dc36e3	0x9cbb4707
+	0xedff1826	0xfa80b980	0xd15aa9ba	0xcc5565df
+	0x71d1097a	0x1ded7d44	0x515af4f4	0x91f132a2
+	0x3833086b	0x0778bb7d	0xb50b443b	0xc42bbf30
+	0x0de19bda	0x7a2278d9	0x98452188	0x7f5e566c
+	0x428c699a	0xdd3082e5	0x57ffe68f	0x51faa68f
+	0x6e57e480	0x709147bc	0xdc526111	0x1d01f1fb
+	0x199410a3	0x75a82d1e	0x35e77131	0xbfb66d4d
+	0xd20cf839	0x17a00050	0x13020cd7	0x07738d81
+	0xc03ce801	0xa4336caf	0xc86ffe7a	0x5bcbc12e
+	0x9b7efdf4	0xa7b61193	0xe029ff62	0x29a61ff1
+	0x80b9e172	0xaa3e57bf	0xad1d11d2	0xce16c606
+	0xa92322da	0x16b79015	0xc4c6e8c0	0x27ece292
+	0x830bbab2	0x941a8f76	0x9d765045	0x9cd9aad9
+	0x5bdf199a	0x388659b8	0xc21a9647	0x3ca3e970
+	0xea948455	0x7e962f48	0x05aea56f	0x50933a6e
+	0x32f844ea	0x00925b86	0xe1e520b0	0xddff7542
+	0x9670ee54	0xe9ccf36d	0xfdcc295f	0xe328ac55
+	0x5b9a5638	0xf2caf15a	0x4f369aac	0x15d9eb8e
+	0xb57ba439	0x141f2467	0x02691964	0x4a27215e
+	0x049827da	0x1c06854e	0x9a1a7f56	0x227d90ad
+	0x585d7d0f	0x02120773	0xb76a4d3f	0xee4fd64f
+	0x7f94945a	0x0ec9beb0	0xfec85f9a	0x01d52eea
+	0x11269008	0x417decde	0xb66ff3c2	0x6ec6d1de
+	0x180cd9da	0x733ecaa1	0x9cd6385d	0xd9caa54c
+	0x4d8d26ff	0x85f4fdf7	0x48196b4f	0xcd1ceda8
+	0xb6c7c863	0x5c3671f0	0x10784425	0x0311bcb0
+	0x5e3f100d	0xd88aaa51	0x12e0eb23	0xc29a35ca
+	0xa1790cbf	0x3d9e3ca6	0x8b773d4a	0x0c8b4f02
+	0x79a0dd34	0xc8780264	0xadf4a473	0x9eb41db7
+	0x89f3aa34	0x10c7c008	0x08279d39	0xccbbffe6
+	0x306be328	0x52d44c5c	0x73cfae89	0xb5c82711
+	0x5d15bed7	0x3a4e311e	0xd9d7046c	0x9254b741
+	0x42018289	0x5fa67a0d	0x85b9a2ea	0x419b7b3c
+	0xe8821339	0x36f5a2e8	0xb447d566	0x553340e3
+	0x3132df32	0x48d0deab	0x0bb49158	0x75355135
+	0x3aa4c569	0x3cb9ac54	0xa73a9867	0x5e4899e4
+	0x2615816b	0x0604b573	0x9c070767	0xd26356e8
+	0x53933261	0xa6175afb	0x1632f9c3	0x2bcab1e7
+	0x37c57c51	0xe97811e3	0xb719360b	0x51ab2348
+	0x39aca372	0x5f0451f8	0x1068d924	0xf622d0d8
+	0x723b6015	0xd08141b6	0xc12c5c86	0x5d9c54c9
+	0xdc5f75de	0xbf48170a	0x5bf2c552	0x67c44ec1
+	0xe3cbe281	0xac7d823c	0xa0d9ed54	0x8d5e7191
+	0x119b69d1	0x81bc5077	0x70ab7567	0xe64e4de6
+	0xe8dad08f	0xb0885ce4	0x5d4df047	0x6a505a49
+	0xc90979d5	0xba8bcbb6	0x86357aaf	0xa35de476
+	0xcc238d23	0xee718054	0x95422094	0x92f40612
+	0xbce5dfc3	0xbfda5955	0xc1110667	0x33832607
+	0x923d8479	0x0819e80f	0x6ecb452c	0xaa408266
+	0x859e7e19	0xbf885a99	0x8ed80943	0x5717a581
+	0xc3f68967	0x72443b1b	0x4116229a	0xaa61a840
+	0x18f78912	0x032c14e5	0x5f3b85eb	0x28662050
+	0x0b10d6c9	0x3435eba6	0xc620a491	0x40ace7d3
+	0xa960f987	0xf17de397	0xcc385654	0x1c5ab258
+	0xd855b9a4	0x1a431ddb	0x39842fa4	0xfc639afe
+	0xf3ff2d7c	0x0bfd7666	0xdb189c2c	0x8c529267
+	0x8a4e8b6d	0x28b9c6e9	0xbe497951	0xcec75e71
+	0x96f3c1c2	0x72f16e15	0x946a9fed	0x12b84763
+	0xdf5a28c5	0xb5964d08	0x6135ecda	0xbe070220
+	0x3fcb729c	0xd29323d4	0x7759247b	0x5e5492a5
+	0xeac7b650	0x4c34a70c	0x5a97eedd	0x26bb2fed
+	0x7cc4b125	0xb89cd8da	0x6cf8e4b2	0xafefad13
+	0xc39a73d7	0xca78640c	0xe866bc2e	0x06e9ffe8
+	0xbeae327e	0x48be3d47	0x9b795815	0xb8f41c1c
+	0x26562469	0x26840fb6	0xe1b315b0	0x72c869b3
+	0x199c61cf	0xdb0be36f	0xe748b500	0x1580d2b9
+	0x6dfd3b43	0x5c02e6a7	0xf9720399	0x2c686d4f
+	0xabda5878	0x1652d37c	0x202fc972	0xae9dd35e
+	0xe805bc3f	0x24352d9e	0x1dfea6de	0xf7d81750
+	0x48b2ed34	0x8ac388e6	0x5283720d	0x09b4fb5a
+	0x1b94cb22	0x3bf2261c	0xa829a09f	0xa95e2122
+	0x16361e5a	0xd7554d4b	0xfc0d42ac	0x2e24554d
+	0xff51fb78	0x26ebfea0	0x58395138	0x143c8a55
+	0xc2293b7f	0xe9aa4b72	0xd1424a85	0xff9b8181
+	0xbb3eebaf	0x266de1fd	0x90db257e	0x7d35beb4
+	0xeaffac02	0xf79c88ff	0x3e14f387	0x0bc083b5
+	0xcbd395ab	0x1041b3b3	0x08ea7750	0x8728fc11
+	0xf61bd8b3	0x1f88ef7b	0x78b7e9b4	0x17b5c1f5
+	0x025e6c82	0x57f8d81e	0xde5866a8	0x7b7cba80
+	0x28221a45	0x96f83ebd	0x77c715ed	0xd3a4e160
+	0xd4be9d72	0xed659f39	0x7af0b3f6	0xb1d83c34
+	0x2876540e	0x0aa244e8	0x6af45032	0x52cc08ef
+	0x69b51eef	0x94367800	0x80adf5d4	0xcdf9cfc5
+	0x367d995e	0xa22aefd9	0x2faa28ea	0xf15648a2
+	0x8e397577	0x5e449c5a	0xb046cedb	0x17072ee4
+	0x9499b958	0xb230dbc1	0xffbdbc91	0xd8d60c85
+	0x0a139cb8	0x36e99cdf	0x4bdc3842	0x320fa3e6
+	0x075cfaa3	0x43240bd7	0xc8c6a0e3	0x43a14f16
+	0xd7d5d7fe	0xba846e6a	0x0579ab86	0xbf084d77
+	0xe8c4765d	0x8bd7ee60	0x8c4e7a16	0x2cad2f9c
+	0xd5bd8a08	0x63eefdd7	0x7528a1ef	0xb7512102
+	0xda25ea2c	0x4654e6ab	0x4cfc6989	0x84539f52
+	0x00f79862	0x65074163	0x45e2c2ee	0x28731aa6
+	0x7e9f6395	0xf8555873	0xd33bc4a7	0x8ecdbea6
+	0x49f0e7e1	0xa26ef54d	0xfb3e6779	0x35292faa
+	0x4ba9d214	0xead84a75	0x02cfdafa	0xbd1b47e7
+	0x36e2b9a0	0x98779f87	0xfc4ec502	0x71854294
+	0x5826c064	0xbfbbfaaf	0xa00db5c6	0xdea7f68e
+	0xa2d32e0f	0x46954ffd	0xeb66d2f9	0x35fb88c7
+	0xa2465311	0xf989f526	0xbdfa214d	0x95f0afd5
+	0x43a1041e	0x7740e027	0x9bb117fb	0xa63c0645
+	0x9db93447	0x5f250441	0x6537eac1	0x29f787fb
+	0x60f5a17c	0xec8f80e3	0x83c9165e	0x1d9ff136
+	0x8f43938d	0xf040a1d8	0x9e938a3a	0x48606674
+	0x932d15d5	0x383fcd65	0x4d7db303	0x5f633834
+	0x8a17761e	0x19528112	0x371b0358	0x1e34cfba
+	0x7046c689	0x438c7afa	0xad1bc6b0	0x9bb9e775
+	0x4d703091	0x04d9fc0d	0x494ebf77	0x610c1855
+	0x4b88816e	0x6c591a81	0x15597954	0x0fe13112
+	0xa949a9e5	0x4022dfd1	0x8eaf10e2	0xc436ad18
+	0x337254bf	0x0c44812d	0xc759ce3d	0x1da78e29
+	0xdba82250	0xe355c8df	0x6e614615	0x791713b6
+	0x247baf0c	0x9636e6b3	0x092382bc	0x196a100b
+	0xa0478de9	0xfd4f26b0	0xa5a1c49b	0x70d1ca23
+	0x6c54086c	0x47286307	0xa185c373	0xaec65e82
+	0x6ce77213	0x463b07d7	0x5420939d	0x3ee4fc03
+	0xc4cd11de	0x65d521b8	0x5304e894	0x8c707b4a
+	0x455ec718	0x10d082cf	0x20535bc1	0x0c3b1016
+	0x90cf26d0	0x25919378	0x671c24f7	0xeaa83d6c
+	0x9cbb1c64	0x42f1bbfd	0x43b5fba4	0xf4f6ef30
+	0xd2034c56	0x6f7d60a1	0xeeadc1f3	0x319af4d6
+	0x0c7e9098	0x0655d994	0x340a3544	0xb37d57bb
+	0x78d086b8	0x350297da	0xc8540081	0x7918666e
+	0x422de0b9	0xbed54d9b	0x03e32a80	0xf0d0c693
+	0x2fe80f16	0x5941f0db	0xa824c1e8	0xe46e7a57
+	0xfcfa4b53	0xb7d8ff24	0x3ab82e1e	0x0332c4fd
+	0x669fd568	0x64adabf1	0xd9c372b3	0x5ce6c28f
+	0xaa8a0e64	0xd4ced1ba	0xfa74c3f8	0x8a59e9fe
+	0x009f47ea	0xe7c2505e	0xad0470b9	0x92abdb75
+	0x9215812b	0x1fb86f54	0x57268f45	0xe91fc794
+	0x9bb1be94	0xc40daab9	0xb75cecd5	0x293c40c8
+	0xe507f284	0xb79f199a	0xa6a0cbdb	0x505cd140
+	0x04a6d213	0x84812279	0x09e5720e	0xf42e2fde
+	0x112178ca	0x1bfcbf80	0xf42738a3	0xd4e205fe
+	0x204c92ad	0xb916f4c3	0x0d7ce99a	0x90eef87f
+	0x924a4183	0x48d1978d	0xe6e16abd	0x5d9eb6aa
+	0xa7a0ee24	0x5aa5ab50	0x563ba4b3	0x7f2b08ce
+	0x641ec0be	0x955af0f3	0x4689d1ab	0x8625ae9a
+	0x11eda5e0	0xe5cbdb1e	0x010591c2	0x632b37eb
+	0xbc20a998	0x33b69747	0x414334ae	0x92b82687
+	0xdba623c3	0xb0d2d852	0xddf1511f	0xeca97e4f
+	0x8ebf5668	0xee509e06	0x8a9ceca2	0x7391233e
+	0x19e71554	0x02315bfd	0xa3fe5260	0x6e6b8370
+	0x1cfab468	0xf3cec4bc	0x11a6a066	0x129d2ead
+	0x79d0f2c1	0x6aab68d0	0xa243135c	0x5be05f22
+	0xba353845	0x7b96f7d8	0x2ba7c6c8	0x67b38557
+	0xedf2c1a9	0x9bc7531e	0xf72fbdda	0xcef2d3a8
+	0xa471a9d9	0x33a35e80	0xffe32136	0x974bf4e7
+	0x70c2d3be	0x95ab3510	0xd878a265	0x16548746
+	0xca45cfd5	0x2b22b0ae	0xf4f855b7	0x3f44b872
+	0xb66db844	0x680417dd	0x72188a88	0x27f830d0
+	0x09d64419	0x35989f77	0x33b7c1c1	0xf6e14634
+	0x3a0d712e	0x42b02a73	0x37592d52	0x34a2bf38
+	0x4434fa60	0xf1fa3c09	0x91ab7747	0x429124cf
+	0xa6b8eebf	0x5d2bbd8e	0x3dfd42c4	0xcd9ada39
+	0xbc3ecf68	0xf5b00eac	0x6e81fc62	0xf58437d7
+	0x09b3139f	0x27fc4f88	0x2d76418a	0xba8deabc
+	0x79557497	0xd322c58e	0x6669c5c0	0x97939ba1
+	0xe96972fa	0xe69d1ec9	0x816a4730	0x693cf703
+	0x1c350d84	0x328e1953	0xd29e402e	0xd4b68664
+	0x3070a143	0xf332f24a	0xf8f3519d	0x4829f694
+	0x15c92ec2	0x4c09709e	0xacad6a79	0x706821ed
+	0xffb8343f	0xa51a014b	0xec3bae13	0x2691fa26
+	0x50af71aa	0x9ccbbecb	0x25cacfab	0x4ff30e8b
+	0x827c619f	0x912c486a	0x8bddf9cb	0x1ca329c6
+	0x3c2494d4	0x4e3c0761	0x231246b5	0x1bd705f9
+	0x9b15013d	0x78fcda4d	0x42e62ef5	0xb7dcdac0
+	0xb27efdb9	0x09dfc5c3	0x5e6286f2	0xaeea106a
+	0x7869f2cd	0xe41b3015	0x8046e217	0xd2145f6a
+	0x45c88a59	0x892b2ea4	0xc8525432	0x1036d246
+	0x8e6045a6	0xf4f56dd2	0xb7bf140a	0x28cf6014
+	0x142b6c0d	0x27e31fe7	0x52ced865	0x4fdafb4a
+	0x68177bcf	0x2bdd5bdb	0x2b0fa0a6	0x0fcafe58
+	0xddbf88c7	0xde93d5b3	0x49e297a9	0x771049ab
+	0x3c2c3287	0x09134d1b	0x3764389a	0x3781cba4
+	0xed665fe8	0x9b055946	0xdc3ded39	0x6576e100
+	0x6826150c	0x68151773	0x9d1bee18	0x777ea1b7
+	0x4b09a72b	0x973120f9	0x92cc1baa	0xe610b576
+	0x7f08cb8b	0x12f9788f	0xa8387cab	0x38bfd391
+	0x6cb0b1b0	0x0b76d93d	0x73ebec97	0xf152a945
+	0xbd3d40c5	0x54362aa7	0x90e626af	0xa92dca8c
+	0x7865aa83	0x7defce09	0x2a173231	0xf1f322a3
+	0x6dcbe003	0xa82ec53f	0x609d2fba	0x7ed0daf8
+	0x21d72068	0xe50202d5	0x99324a58	0x5cd587b1
+	0x22de1ca5	0x8bbfc6f3	0xb4ef3242	0xb73aea5b
+	0x200b456c	0xa14a0da9	0x7ca58ac5	0x1a187705
+	0xd58896e9	0xa5bc10cd	0x3470d7ad	0x1247dc26
+	0x877172d9	0x3b1dc34b	0xb88494e1	0x39db9c8a
+	0xb802b911	0x20701030	0xea20b1c6	0xd28d8a3e
+	0xbd9d9f75	0xe371ca39	0xfe361a6f	0xedd62fb0
+	0xe76daec9	0xd600efb1	0x5f90ed95	0x5d6fb5bd
+	0xdb0ac4f4	0x8008a84e	0x845d50aa	0xe19c4754
+	0xe68847eb	0x8e5b5c61	0x994239fe	0x9834f61d
+	0x024a2077	0xc3fc21ab	0x6a45af08	0x35258359
+	0xf16b1eba	0xb3bc5423	0xc92d6b29	0x54e02b89
+	0xe6aa9df1	0x8a38aec0	0x031a68f9	0x1107d939
+	0xd7e0a74f	0x976c7d59	0x3fc7896b	0xa247b93c
+	0x58d2e8c5	0x6168e2ca	0x65ce7a4d	0x07eecbe9
+	0x064c67b2	0x06f57d98	0x2fb63ba1	0x7632e204
+	0xa6c9de98	0x8c382895	0xe74fc689	0x2a1def5e
+	0x31002493	0xc185e709	0xd18edc2d	0x7137deb8
+	0xabe21a4b	0xd17d019f	0x95274457	0x737b6860
+	0x9e0f6c6c	0x3fb11486	0xdf8897f2	0xf0d628ab
+	0xb290a618	0x3aab7d23	0x05677cf1	0x5056127c
+	0x14cfd11e	0xeb24053f	0x9654344e	0x6b1d8c8c
+	0x68cc5f04	0xbf17e79c	0x54cfe8d8	0x107f0a52
+	0x9bca389f	0x24252885	0xd758eef5	0xd898d717
+	0xeadf045e	0x165e25d7	0xa685595d	0xf637d696
+	0xebca236c	0x368079c3	0xfdafe821	0x89715066
+	0x6cd7aa80	0x31775690	0x0de0b4d8	0xae9fde9b
+	0xb425dead	0x41471330	0xcd4e58bd	0xf484f0b9
+	0xcbfbf813	0x1a25e5ee	0xe6456cea	0xc956ef7f
+	0x8ac948a2	0x775b1bfc	0x9739ab03	0x4f0b6411
+	0xb6b76e6b	0x9ec9343e	0x4f84c648	0xe1e66557
+	0x94f9fdec	0x386e4616	0x05c69bdb	0x93b0d440
+	0x9e5a3f61	0x635a80dd	0xdb6c23ba	0xc8d5f680
+	0x53767271	0xc0df8ca0	0x117efc6f	0x78758796
+	0xb3c77572	0x40e23c4e	0x82d7a503	0xaec195a8
+	0x53c1fe03	0xa131e6c9	0x2abdf9e1	0xa586fef5
+	0xb6d68103	0x34de4b9b	0xd4c02e0b	0xe5cda9cc
+	0x1a7e7917	0xb9b2f0f0	0xcabd1b03	0x18c17e71
+	0x07a37b1e	0xa83d6960	0x4dd66c28	0x32cc6b02
+	0x6eaca18d	0x7b166b05	0x095d85fb	0x938ec035
+	0x1a7e82ff	0x54bfb69e	0x6fbb6339	0xbeeaf829
+	0x8802a09c	0x604bdd0a	0x8191f84d	0x7da1e89c
+	0x64b9b0a5	0x6a5b6428	0x93eea3b9	0x21c433e8
+	0x8043427f	0x605e743a	0x9c81808f	0x7c976479
+	0xd7ef98c6	0x8b39cbee	0x89be6e39	0xd01dc72f
+	0xe6c09227	0xc8ecb3f2	0x399d3a41	0x4a91d1a8
+	0xf83eeda9	0xe1d4fe01	0x518ca766	0x0c3b1ce3
+	0x828f30cd	0xd3edf647	0xac126894	0xdd3f996c
+	0x601e5d4d	0xdd7856cd	0xce16a70a	0x99212df2
+	0x5e2b3d89	0xdb8d2ef6	0x70b79dd9	0x361a3a38
+	0xf6ec33e6	0x4ec9a451	0x1a280939	0x2d9d6d7f
+	0xfd4e1f43	0xfd5ffd39	0x83921d68	0x37db0d24
+	0x77c94204	0xf11165db	0x5cc1103a	0xab1d0669
+	0xd12ee8b4	0xa9ff0fdb	0xa494ff37	0x694f46c7
+	0xf64b5f33	0x520f1325	0x141eb18b	0xd29adbb7
+	0xa68fe24f	0x3d430328	0xedd40f99	0xdb5725f5
+	0xd3b0249b	0xf430037e	0xd105a0b1	0x95fe82ab
+	0x72dc63c8	0x8c1b45fc	0x96355d54	0x76e40b98
+	0x5f7baeed	0xba9b2590	0xbd64bbb4	0xf1541f6c
+	0x7ca49b5a	0x111f2640	0x4b86cb63	0xfe71a409
+	0x3ec03f6b	0xae4aa450	0x525163aa	0x1123ab5f
+	0xb385fc44	0x6901f207	0x2ff5773c	0xd55b0a75
+	0x6732e0e1	0x773f7dee	0xfe70aee9	0xd856780d
+	0xdee051e7	0xd950ffd9	0x4da637f7	0x13b4c650
+	0x2eff422d	0x0871c35c	0xb3e61664	0x1fb1abad
+	0x78e2ad46	0x44f63fe4	0x1e9e1d36	0xacf791a1
+	0x4fb51853	0xd0d5b2c3	0xf9728625	0x7160dab7
+	0xafe5d4b3	0x8bf7b7f0	0xd49a6ea5	0xab1694a1
+	0x1bc22cb3	0x3fcf2c26	0xf3237c26	0x442367ba
+	0x5dda5917	0x20031a86	0x1f1b8a1a	0x1477325a
+	0x546ee877	0xd347d71d	0xba45204b	0x750c5e9a
+	0xde39e049	0x4a544c72	0x627d76c3	0x13b7f044
+	0xe173e94a	0x64337a88	0x8e0548bd	0xfd0f0271
+	0x45721e1e	0xaecb5a8e	0xfb1f7bec	0x42449a14
+	0x620a6043	0x6310cdf1	0xb49eaae5	0x2bbf380c
+	0x26b7090b	0x4dc2da7e	0x3218693c	0xa6866d0f
+	0xcc998a27	0x57fa9a65	0x38a55c26	0x2d110f40
+	0x75fd7072	0xe147d675	0xb40adfba	0x3ea3896d
+	0xf289c62b	0xfad4fc7d	0xe5e10d26	0x1bd5f851
+	0x96f5e841	0x36a4e81e	0x670ba3f9	0x67aa030e
+	0x5577f4be	0x953b0bf3	0x307d00c6	0xbb9eabe1
+	0x871966cf	0xeb40c08d	0x74fd7e0c	0x49d4864e
+	0xf908f80f	0x1ea32c4a	0xd69e9ad0	0xaad2ad31
+	0xccf27a60	0x41ee5ebd	0xfe1dafcc	0x71cef55c
+	0x784168de	0xc4a0c447	0x315d99b3	0x0c2470f3
+	0x9002b535	0x29b95878	0x7a8a2ce4	0xb49967d5
+	0x37814d76	0x333b15fe	0x8a964085	0x3cd76bbb
+	0xfd1d1834	0xba0c3dfc	0x61d29379	0x8764238f
+	0x5aaf4d00	0x24c3bf1c	0x9c3c7488	0x94dd60f6
+	0xc844a0a1	0xef8b2bfc	0x0e8d1c17	0xd6d4d2d4
+	0xeb15153b	0x4f1233f6	0x8ed307ac	0x749fa7f8
+	0x387d4e80	0x80904eb7	0x53385377	0xf77ca9fc
+	0xbb037920	0x3cd8ef96	0x05ea8e91	0xdd0e0501
+	0x29779eac	0x55de6e6f	0x89874da9	0x56ad3af4
+	0xd8228766	0x9887bc22	0x213a0648	0x4db466af
+	0x550f82e4	0x964ab9e9	0x0cbcb32f	0xad872a85
+	0x97ef2fdd	0x8e78bb79	0x95be67ea	0x44c2d180
+	0x236b246a	0x3b253079	0x15c0dd93	0xef4b0368
+	0x30f36d65	0x506737dd	0xcc93b5e0	0xaf00bfff
+	0x1a79a0e6	0x4dad4900	0xe59a76c8	0xe1533fb5
+	0x75a4d69d	0x80744617	0xdc92e0f6	0x18e53a7d
+	0x9c1190f4	0x6411a55a	0x24137a70	0x3fad9fde
+	0xdfb6e346	0x7221d85c	0x6f6e2aa4	0x3ade33c8
+	0x9410407a	0x953aab54	0x8dde9999	0x7afd3ca3
+	0x1a92d29b	0xa78e9ace	0x95d15c64	0x95e9314a
+	0x0cf548cf	0x31bf5f8c	0x5cbae6b2	0x883b14a2
+	0xe21a9715	0xba500b0f	0x34ec849c	0x2ee98b5a
+	0xa3bdccfb	0x1022fa85	0xbf97abdc	0xf5bd1fe1
+	0x542d7143	0x896ed934	0xd3c42da1	0x13d90044
+	0x0573619d	0x305067bf	0x6f02b13f	0x0c516dc8
+	0x378699d9	0x838166f7	0x380ddd16	0x4c0e8bdb
+	0x61ba5a38	0xd5cf4a2b	0x0733d359	0x39468b9d
+	0x0d9e90c5	0xe8717681	0xe2d0a06a	0x8a436126
+	0xa5a31cea	0x03e217c7	0xe00398c3	0x1e36ee68
+	0x6bec78cb	0xd2de6eab	0x7d252266	0xbb4e8fb2
+	0x96c7fa6b	0x5758c3a7	0xe81f9a51	0x0337916f
+	0x4f31084b	0xa0dd1f6d	0x7da31b5d	0xbfbd5092
+	0x7d9f1e22	0xced1d5d3	0x8c397f51	0x68488587
+	0x2c89b78b	0x5c95b114	0x03a124b7	0xa9c22961
+	0xd05b4125	0x7987a218	0x9b33b81a	0x8dbece84
+	0xcd44692f	0xc2f7e2bc	0xee62478b	0x19a72768
+	0xf89a81c2	0xde94f042	0xe786cc87	0x1cf6dfe8
+	0x97357227	0x5d0b8ccd	0x210ded20	0xa3415b63
+	0x5a44c511	0xe00d553f	0x9106e41b	0xbb90e29c
+	0x4278fb00	0x13c4d245	0x0da5d28a	0x33bcd03f
+	0x622f99a2	0x5403b878	0xb755e5bf	0x93260477
+	0x57163c58	0xd5ad8ede	0x38597763	0x843ee2e7
+	0xf6bbfd8c	0xa80486d1	0x0aa9d04a	0xc3a21001
+	0x0988ea5f	0xa599060f	0x35ed1e4c	0x6861fb9d
+	0xdb49e460	0xeea1563c	0x630322fa	0x1db98607
+	0x061ce758	0x0ac92a43	0xb86273fa	0xc74cff34
+	0xf754e2f4	0x1d2a92f5	0x7345cab9	0x684f75ff
+	0xd68ac78d	0x7ac26120	0x2849d90a	0x9b9e68f1
+	0x61f0cf5c	0xa8ca277c	0x59b364c2	0x0c697e32
+	0x299f1644	0x390cc831	0x52f8fcc7	0x324a355a
+	0x245255d6	0x66571e06	0xff7cfc9f	0x9a1d968a
+	0x77d5b3bd	0x02118c12	0x886cb817	0x86863d76
+	0x6e9e8f89	0x16b32373	0x548c53ea	0x366dd932
+	0xc8bc0ed7	0xc55d2cb3	0x382a1401	0x0c343f0a
+	0xbb7022cd	0x775c425a	0xc942868c	0x491c03f1
+	0xe4e8bc37	0x57eb119b	0x161f1c40	0x78813d90
+	0x64ba5ad4	0x8c1a3687	0x6cc54f9c	0xe838a982
+	0xcb582447	0x946585f3	0x513fb0ca	0x1207f8f3
+	0x2c317225	0xd3144a73	0x937db9b9	0x1512f0fa
+	0x0144c46f	0x617ee635	0x6abb13d1	0xa5735cbf
+	0x28c41d41	0x4bf3cc5b	0xef15db89	0x93fd1b38
+	0x9429d27d	0xbe2c2385	0x8ad8bf36	0x47b18f4b
+	0x439baf8b	0x9f7b5c0c	0x403263e8	0x85a4a0ed
+	0x2ab72c87	0xe5962ae7	0xb2eb376e	0x023c83ea
+	0xe14729a5	0xef1f1f07	0xe8ad7262	0x4577adfe
+	0xb27407ff	0x299d5afd	0x2def24cf	0xb0fb321a
+	0x91a3ca39	0x549ffb9b	0x00c11c2f	0xd52620d2
+	0x483c3576	0x21b03393	0x6c19a634	0x60949c8e
+	0x2eb2bcb0	0x77b950fb	0xe5762d8e	0x491bfad9
+	0x6ecbc8ca	0x8f6665f1	0x1d76f0fa	0xe07c8ed7
+	0x93c70313	0xe3846992	0x84364566	0x642caf16
+	0x5ac66840	0xa8e4829c	0x1503a3f0	0xf0b7d2eb
+	0xac163682	0x4da9a902	0xcb03ab68	0x95395ba3
+	0x9c33a7cb	0xdeed8413	0x9d6b8d5c	0xb802340b
+	0x1ea7fd81	0x99313f3b	0x6b85ad1b	0xeb6ebef3
+	0x6e59a06b	0xfdc0fd57	0x0062b9e8	0xbf16842a
+	0x6cbd26a9	0x83444a69	0xa6f6c1f1	0x2cf5a079
+	0x1c3f8b9b	0x5c95aa6e	0xcdae53bd	0xdfce79db
+	0x3908fced	0x5e5d8e6d	0xbb15c722	0x1aaf5bd0
+	0xd978d536	0x91f112d0	0x3dde83fc	0x1abfd9dc
+	0xc42b4d93	0xb91530fd	0xe782c8b7	0xa78637ae
+	0x87827a53	0x332a694d	0x2fe77c47	0x4310fb1e
+	0xd9ce00ed	0x41458131	0x2db53f24	0x58e70ac0
+	0x48ae6ac7	0xf99f1548	0xb4547cf4	0x5d87e704
+	0x5f6481e6	0x4cc4b6d8	0x38e87cd7	0x9dc7790c
+	0x1a2458d3	0x1cb3d6dd	0x6b42515c	0xe4ad86f6
+	0x3854471f	0xe599520f	0x0499246e	0x9d76565c
+	0x75019717	0x5607a929	0xfcbae54a	0xc98593da
+	0x5d9c3101	0x80dd77cf	0xe8c8d2b7	0x40ce61b9
+	0x2090ba2c	0x487bd52e	0x2e4ed94c	0x3f2f0d11
+	0x7b66d583	0xd91b93db	0x7bb06fc3	0x80c38aa9
+	0xff6d96de	0x47806328	0x255fef60	0xefa54a24
+	0x74dc5c69	0x4b4db032	0xe15621c1	0x11c6b1c5
+	0x30e4067a	0x07d4b9a6	0xc466c81a	0x3d1baac3
+	0x9ccfb9d7	0x13d170e2	0x43ce03b0	0x6a010f61
+	0x53fca3f5	0x2c25ab82	0x09f729fc	0x9f706241
+	0x6a53b88a	0xec3b1246	0x6977fa94	0x02cfcfd4
+	0xe4a7c27d	0xe8e8ea3d	0xe845b11c	0x19862507
+	0x8acf6cd7	0x978be162	0xf01ded4d	0x7ff7e81e
+	0xe6f36ca6	0x22a0a9f6	0xcb178f7f	0xe2e15339
+	0x2f71a56f	0x75fd3f09	0x03c93002	0x26784382
+	0xf21aff81	0xe23413b4	0xdd1330df	0x2ecd91d4
+	0x7fd8d558	0x76878bfe	0x8b1dbba7	0x4383885d
+	0x003baaf5	0x299b274a	0x69e5c88b	0x55b2b499
+	0x522f83f3	0xa46c9774	0xb0212460	0x3085a0b4
+	0xdb229bc9	0x963f7774	0x47267dcb	0x1fa9ce5f
+	0x9433ccb5	0x2848a201	0x93019d81	0x421e703e
+	0xb121c267	0xcc2ad207	0x7f17e83a	0x596a8994
+	0x96f27104	0x89b2eae1	0xa544803e	0x5cb08340
+	0x2f720974	0x1350dcba	0x78ce7ae4	0x7d320399
+	0x3735c25a	0x0545b42e	0x3e4c7d54	0x6ed68501
+	0xc9b2f3f8	0x4e949c93	0x389f0e89	0x43ee36f3
+	0xb3c459f1	0x17513779	0x8229f712	0x215bde53
+	0x4b4b07a0	0x90ad9983	0xaeb3494f	0xf6f727ca
+	0xc28fabb6	0xddabcdab	0x01febf71	0xb244b8c2
+	0x0a455225	0x2901729a	0x0a7b35ca	0xf1b23e0c
+	0xa5f7c517	0x92f8e547	0x233ec55b	0x2bb537f0
+	0xeaf1b875	0x289e0104	0xda51c3d3	0xdfabadde
+	0x06a41866	0x4bf82f47	0x12060655	0x153525e2
+	0xb8cfef42	0xc307b295	0x778b6b82	0x036e40c8
+	0x6a4cdec0	0x750e09f6	0x0806ab28	0xf8dee912
+	0x45b906e8	0x08fb675d	0xae22c34a	0x2f54dc88
+	0xe98c7993	0xb76b6518	0xc70d5d8f	0x5987130a
+	0xd89d1cec	0x1744e957	0x22db0f57	0xc7501e9b
+	0xe9c9dc0b	0x1a8553a7	0xc15a4e4c	0x9e1840d5
+	0xeac1888a	0xba4c0a4b	0xdad84202	0x2d1b2d75
+	0xef06c127	0xd319a36c	0xd60b9d92	0xded20da2
+	0x00d23bdf	0x96b431fe	0x636914b8	0x494e02a4
+	0xc8c4ad31	0xe56bf0b2	0x28f07451	0xd86917f1
+	0xf7299383	0x977635a5	0x9026dc33	0x3e3b3b57
+	0x767118a5	0x04182a61	0xab5ee0ea	0x34f4cc0c
+	0xce072097	0x78d15c95	0x6735d38b	0xc23bab3a
+	0x7633847c	0xdd6d33fe	0xa1df1bc2	0x864ebeed
+	0xda785538	0xe87d3586	0x1b22b9ff	0x13160899
+	0x63bf5870	0x3e2955dd	0xf0ef68c7	0x51265578
+	0x63b70533	0xcfd7b598	0xeef8ed8d	0x760fa884
+	0x6375b455	0xa9c173e5	0xbee01756	0x6dd2f4a6
+	0x47ed59f1	0x7720dc3e	0x629c2a41	0x782040c2
+	0x7b86f562	0x7d5ff40b	0x17fb5fb0	0x26c157bf
+	0xbf0060e2	0xd9688952	0x98374c22	0x59ea8e69
+	0x252e4b81	0x123bf2e0	0x3d56230a	0x5188164e
+	0x93261c35	0xa564aa88	0x121bd9cd	0x5c16aec8
+	0x2fa246a9	0x15789e4d	0xa4bb3b72	0x5bafbec9
+	0xcd1b93fd	0xe2d0427b	0x56f5694e	0xf48953b2
+	0xc50fc819	0xe0af3ffa	0xc3e48bda	0xb80b874a
+	0xf9258e7f	0xad9f4362	0xfca90c4b	0x4884b4bf
+	0x4dee8a41	0x5c4d0196	0xc249d85c	0xbb5b9632
+	0x8b5635c4	0x2b637b4f	0xb840896a	0x4ca8646d
+	0x4696be9c	0x6630a968	0x5c5b4533	0x29eb7b7c
+	0x55f67376	0xa8dc36cd	0xb4f4474d	0xef64a1fb
+	0x1418534d	0xa76530c5	0xdcb4641b	0x8dfc7ae5
+	0x9afc17a6	0x44dab843	0x80f1f874	0x23b8762f
+	0x6cb7650f	0xf30d05cc	0x1f1fe1c0	0xba28476d
+	0x066fbc0d	0x97d7e010	0xb2d29434	0x4a42af7e
+	0xe0292aa5	0xfb450fe3	0x670c292c	0xdb35b707
+	0x8a981c83	0x30e2c3ac	0xe0e9c1b1	0xa8331796
+	0xcf5af247	0xc01b2f47	0xd25679ff	0xd5388c03
+	0x94227b44	0x95b55fa5	0x72fae874	0x4c760f50
+	0x3279c236	0x4b0e3026	0xf0ef3721	0x30ed3945
+	0x99f7e6e1	0xb985557e	0x6f5599cb	0x5c4d76d8
+	0x559f7096	0x183f53c7	0x7ddaabff	0x92ec2b04
+	0x5935371b	0xd968d5aa	0x4818a8f0	0x76d10b5b
+	0xcc0eddb8	0x86a730b6	0xaa95c741	0xdd404554
+	0xcc529f43	0x28567f77	0xe9dcde95	0xcfbfbf96
+	0x1f1253fe	0x60822fd3	0x2b0ed852	0x80e06c9b
+	0x5e8d23cf	0x577c0905	0x96069c6d	0x99c241c8
+	0xe5ae5dda	0x99539ee1	0x56abf146	0x917dfb3c
+	0xe84801fa	0x3d9b7e26	0x404c8082	0x3d704cfe
+	0xb6f7453d	0x1f509b7b	0x846b280d	0x8d20fa61
+	0x1990f9da	0x6dd00698	0xd0b108e0	0xfd767fe1
+	0xa6270bb9	0x1aeff8d4	0x7621ae8f	0x37f5f2a4
+	0x95bc6d03	0xf98e99fe	0x2b03c0d9	0x928b4e3b
+	0x3493fbbf	0xe5833647	0x42a92ec1	0x3ae9f16d
+	0x39089d52	0x8ebfa3e7	0xc05c7627	0x0b42a1ad
+	0x2773bd44	0x10f95843	0x53994b3b	0x0d3f8f05
+	0x4745c534	0x073c3264	0xe7d88425	0x12ce91fc
+	0xc45eed99	0xacda7b87	0x34819b15	0x44cbba73
+	0xd939e0cc	0xd02b4d35	0x2c2174ae	0xd8d25155
+	0x8af4ec1d	0xcbf70b9b	0x647e75a3	0xb5db7051
+	0x978b8f7a	0xb74404d2	0x1635f61b	0x8c1db8cc
+	0xd1414536	0x4caa27ad	0x58aec877	0x625683ae
+	0x076d11fd	0xe2bbbc48	0x75c3d352	0x25dc3bf9
+	0xbc0097b4	0xd8fa1b96	0xc9f01dbe	0x449393d2
+	0xda1893be	0x741f6c84	0x71538d10	0x38d42ac3
+	0x20f9e95f	0x3b6d6511	0x3547488d	0x9ec4e3a0
+	0xaa096298	0x7738626a	0x56a4a9c0	0x79a865c1
+	0x8a590afa	0x8d60b288	0xdb1e68ac	0xd4d1b724
+	0xdc734e47	0x167bbde8	0x43e2fdf9	0x847cd1c0
+	0x49034f8c	0xe9aff87e	0x8b743e83	0xb811b6cd
+	0x3546ec3e	0x856eb97c	0x41d4c579	0xad60d402
+	0x4f0ff4d6	0x9afbee57	0xe678e2e1	0x53a1d97d
+	0x22f885dc	0x642856fd	0x4a81b1a9	0x265dd2ba
+	0xef16b9ec	0x8eb61d21	0x4f484265	0xa668418b
+	0x5c28fe6a	0x895c076f	0x22294668	0xae1d0869
+	0x103b8f52	0x348edc9d	0x8094074f	0x00635bed
+	0x0e48d8b3	0x85a44cf4	0xc06e8cd2	0x96b3bb35
+	0xf80f6829	0x72070e75	0x45f139d0	0xae3c90ba
+	0x72eab68d	0x6dbaf724	0x7b1bb04d	0xeccdd042
+	0x6c55b042	0x5c2d3da9	0xe6883282	0x43085add
+	0xfed4e6d4	0xf6a4e8fa	0xd2609bb6	0xda70dfba
+	0x9e9d1d8d	0x4c4928c8	0x74ef7983	0x76c471e6
+	0x0a84f86b	0xc90a6f35	0xa6a3d84a	0x534312a3
+	0x021377f9	0x3e38177b	0xb7411fdf	0x47d09e78
+	0xbeedc504	0xc69f3e45	0xb9ad6ddf	0x67305b87
+	0x0eee93ad	0xeb42ec4a	0x2d792e40	0x36b38150
+	0x70553e78	0xc9faca6b	0x109523e8	0x92907948
+	0xb1bcea74	0xe949a024	0xa8416c81	0x535456c0
+	0x338ce49f	0x0fe855b3	0xcfe9d839	0x4a71671b
+	0x3b39dca4	0xe7f2f3b0	0x9670c765	0xd0b5582e
+	0x8af482af	0x4de8e13d	0xfc229249	0xa44568d7
+	0x9af47a09	0x56d992f5	0x6359b7aa	0x26179b95
+	0x681fcbc8	0xfa67fff3	0x253b2406	0x900be39e
+	0x1b918c3c	0x184cd65b	0x86dbb9a1	0x406555c0
+	0x9e71c8ce	0x08aafc7e	0xcf7bcca8	0xdbfee8b9
+	0xf6690e2f	0x67dc077c	0x971b0e18	0x93eabd5c
+	0x995e6579	0xe02aef8a	0x1dd8edf8	0x21e5a297
+	0xd8fbd7d1	0x6b778ea7	0x73818f7e	0xec9c60c5
+	0xbda7ec46	0x290f2b1b	0x9b9c1ff5	0xdbc720e0
+	0x4057d01c	0x583aaca8	0x42157273	0xd04cc9e7
+	0x17f006dc	0x7a0061c7	0x5092ebc6	0xaf39abc4
+	0xc83234b4	0x95766854	0x26beaf6b	0x7707852f
+	0x26b81ab3	0xf32e8f16	0x0fb218d3	0x92128d4e
+	0xa1c881e4	0xd99b97b9	0x32ddfdc4	0x788499e7
+	0xbd4da7e6	0x2134a49b	0x768f16f1	0x651e8ca4
+	0xde95ac3b	0xd63d22ce	0x2f7d34de	0x1f44aec0
+	0x22cf59ef	0xe845473d	0x249699b8	0xee698261
+	0xafdf6327	0x4b6c1eed	0xd55259f0	0xac3c90d3
+	0x4a5691b9	0xc2056b30	0x46726519	0x99097fe0
+	0x36204d12	0xae5f9c05	0x6146df29	0x2e3777e1
+	0xd96ff159	0xd6a25f3c	0xc39cf188	0xce8035c3
+	0x18915c69	0x6336aed8	0xba4ee698	0x14160c9c
+	0x5b3f9df0	0x76bae97e	0x42e4feaa	0x3977a8d0
+	0x37dc468f	0x04b24cc9	0x0bba0dcf	0xbfa6e345
+	0x44bdd1e8	0xc92547c6	0x6788da17	0x59e796b1
+	0xe2770fb4	0xd92b9ad4	0xd03d1b8b	0xd07b8c2e
+	0x8a543f84	0x05b0d456	0xfaed7eed	0x52d3fd0f
+	0xf9591f25	0xa00b2f73	0xf0107935	0x91e5b227
+	0x18850204	0x8dcfc51b	0xb6db0c07	0xf7116316
+	0x6a5dbd17	0x0d76e281	0x6005fac7	0x16d79045
+	0x31895a18	0x399371cf	0x536e420c	0xc49323af
+	0xd2b27dc7	0xe9a2c450	0xd1aacbd0	0x8e899397
+	0x67aa7c54	0x235619ff	0xec87a0b5	0x71be4483
+	0x06657d96	0x884020df	0xb8f2a975	0x12e2440e
+	0xd1966cb0	0xa7bfde0f	0xbb51bf79	0x8604d7ad
+	0x4f09e7a3	0x32e6bdf9	0xc964da28	0xa751b31a
+	0xdb35eee7	0x8c27e01a	0x26b538d4	0x0dd36be9
+	0x706170af	0x3b18f53b	0x9c7992d9	0x5ed9eaa4
+	0x47347d24	0x1ba8eb3a	0xa510b5b2	0x033d7153
+	0x7e91532d	0x4a81361c	0x288d3cdb	0x563dd47c
+	0xe7cd0eb7	0xfed9fb6c	0x4d4967a8	0x78f79653
+	0xf1325f1d	0xc165b27e	0x3b92daf4	0x3796065a
+	0x86eda8ed	0x8ac83880	0x4292f50f	0xd9afc9c1
+	0x9fb0b6c8	0x14eb0c0c	0x26cf5e56	0xcd98b055
+	0x1e40d460	0x872376a9	0xb5f0201e	0x90eb25f8
+	0xb4239ea3	0x146369b3	0x778889ae	0xc64a629e
+	0xd687e1e0	0x02663180	0xd37cfdf4	0xc3a99b90
+	0x936df670	0x343064b5	0x65faa530	0xfd161930
+	0x5d89793a	0x7cda7663	0x2a0078c3	0x9caff427
+	0x7c7eb5bf	0xa738ac55	0xa3ec5238	0x50d6b47e
+	0x6006e6be	0x9ce735cc	0x6f0b9435	0xefcd8529
+	0x5e49fa2d	0x3c56e74a	0xe5953695	0xe9435485
+	0x03350f9b	0x94fc5471	0xf8034f8e	0x1bfaf4cb
+	0xd99c75e1	0x8509d572	0x1d7e45a9	0x932770e9
+	0x5c830a84	0xdfb3fe3d	0x7e9d70e1	0x2780e800
+	0xe8408a90	0x704f3051	0x0f0756a5	0x10c5504f
+	0xa6c1ef11	0xeaddf020	0x7978f3a7	0xf6d772e1
+	0x0282f5fb	0x3da228bf	0x93f3edd3	0x1a3c0f7d
+	0x51845545	0xbae91b97	0xbae42cdd	0x497addad
+	0x7e7d072c	0xff1bcd9a	0x3329bf18	0x215c3451
+	0x5a1be9c0	0xc3db81f9	0x0583c1a0	0x134e3d8f
+	0x979b3eea	0x90f6eee1	0x84ce4681	0x573c40ea
+	0x5b93038d	0xa6a8548d	0xc6fa2186	0x5445b29d
+	0xecb121a0	0x0d1526da	0x43c6a7a2	0x5263513f
+	0x5d8cc589	0xef87c7a9	0x352c9ce3	0x7ee7e3dc
+	0x29d35302	0xebcc2816	0xa73da8db	0x8d6ad8b5
+	0xae2dd2ee	0xe3b008c9	0x560f1552	0xa049ef2e
+	0x86bd5c68	0xd28c5e3e	0x8589bc6c	0x19d2bbe1
+	0x94e340eb	0x8b1eebe3	0x4b57554d	0x0781be17
+	0x916fa9f5	0x603c886a	0x3762bb9d	0x6a88e776
+	0x070b02b2	0x02b511dc	0xcb0e2fd0	0x9f610d94
+	0x205c39b4	0x030e84bc	0x105d5847	0xd59ee0c2
+	0x4c000cdc	0x0414fef9	0xe7e5dba0	0x311b623a
+	0x9f8c96c8	0x61af8dcd	0x8d669491	0xb00d611a
+	0xd7fa1cc0	0x0c14260a	0x21e3145b	0x2575cab7
+	0x4c21c29c	0x5d35eaf4	0x888c262d	0xa370d1a2
+	0x81cc8ab6	0x09448c73	0xbcf40a87	0x76283841
+	0x9a2fac29	0x0b4c4aff	0x109cff31	0x289fee1f
+	0x942dfa79	0x221584e5	0x8918480a	0x3a3cf8c8
+	0x8870c5bf	0x79d8e3cc	0x7a5127c5	0xf50ef1ff
+	0xce14b7a4	0x815fdff0	0x984e925d	0x4e079d76
+	0xc48dc46f	0xffc63e16	0x3b72b70a	0x3d65ac7d
+	0x2d09b538	0xcdd74489	0x957827d7	0xbd28802a
+	0x7bd3a4c8	0x0323f7a4	0xd2e0fded	0x1180fffd
+	0x943e9101	0x39771bbd	0x3c9f2cfa	0xd43fc1be
+	0x159378e7	0x23dfd475	0x7366b82f	0xf70424ca
+	0x39252769	0x92e4e18d	0xbf985620	0xf0304d71
+	0x840aee3a	0x26396736	0xfa14e721	0x8496038f
+	0x3f75d64d	0x1a555d68	0x23fe7107	0xf91d6676
+	0x3e26d6d3	0x000d3b87	0x175a5caf	0x234c6cd2
+	0x1bc3abb1	0xeab04320	0x8654115d	0x7d3cd3b3
+	0x5156a35e	0x98e39a23	0x1c35f79c	0x516f34ae
+	0x455293e2	0xf44f7c95	0x61e01820	0x7d3edd82
+	0x9213352f	0x08966bce	0x473cbff7	0x9d139979
+	0x50b7f69f	0xf4264832	0x6e7fcd24	0x26756e8f
+	0xe62b221b	0xa2609ebe	0x9e88ba86	0x5505ae8b
+	0x7a096006	0x8a4811f3	0x103db4fe	0x40a48e38
+	0x8635607c	0xd2f38d22	0x297e3b49	0x6c90a21f
+	0x517de294	0x5295cd01	0x5077705e	0x8a21897b
+	0xa0ac1da0	0x221cddbc	0xa1e9653d	0x8caa99cc
+	0x1c8246ba	0xa50aeffc	0x3d5c71be	0xe2278aae
+	0xefca9113	0x214ecfb2	0x3e46acd0	0xcd029c62
+	0xccc5f799	0x13ba4d53	0x01a857b6	0xce918062
+	0xcc023172	0x70d9c96f	0xceac54cf	0xe39ea79e
+	0x411d6d63	0x0bd9756a	0x1ca60d69	0x1d09c516
+	0xddd3d36b	0x7fdd11a8	0x62a744ed	0x1c47b291
+	0xe1306284	0x3dffbdd0	0xf3243232	0xf1088297
+	0xa6f0d267	0xc1508ef1	0x1df5a29b	0xddc37fd2
+	0x1cf8ccfc	0xcffcaeea	0xc81be18f	0x2ccad7be
+	0xe95737e2	0xc67b0667	0x7382caa8	0x4a4a58cd
+	0x4247ddee	0xfaba56d3	0xde82cf7a	0x5301df88
+	0x6c57cdea	0xadd20675	0x23c86330	0x1e16d63c
+	0x02431073	0x23630e7e	0xb0e0e940	0x099ec0d1
+	0x6e7e854d	0x5e0bae04	0x7c650f85	0x190c0f6e
+	0x6d55b46c	0x97c0e70b	0xbab62ddf	0x8c52867c
+	0x5063c950	0xa38ff7af	0xbff35da2	0x4ed590fe
+	0x42b180db	0xe31c3a64	0xee1d74dd	0xff383c52
+	0xd3e7252e	0xcc1d120f	0x02a7cbae	0xcfefc2bd
+	0xa1abd1f8	0xbe007fd6	0xb1c208c7	0xae640518
+	0xc903dbc3	0xfe049c73	0x9c10ab77	0x00fb4dbf
+	0xba1fab03	0x94472765	0xfa6b1de0	0x45c382ba
+	0xf9e82dd1	0x6c97ffc1	0x05558b82	0xe3c461e5
+	0xfd0f4056	0x58b131b4	0xe0a1c278	0xe7b06c07
+	0x4aeebbdf	0xd304f26a	0x841897e3	0xab607818
+	0xf33dafb1	0xdcc5025b	0xaef62c8d	0x7c190674
+	0x5ccf46b9	0xac4d8f10	0x55aa5bfb	0xc4808316
+	0xf7bc5b55	0xe67fc285	0x91d33eee	0xe5e3b446
+	0xcf268c0c	0x00715de3	0x562415b9	0x75e45b2c
+	0x78cec40a	0xb6b452d8	0xe7d6c7e8	0x4d957481
+	0xd2d3ee79	0x3e31ba54	0x6045c572	0xb77d5c0c
+	0x92bdcfd2	0x0002d033	0xb866a4c5	0x95ee6deb
+	0x9934a3df	0xdc53496f	0x5bcff76b	0xa17ae9ef
+	0xa420b1ea	0x7cbef81c	0xca7cc86d	0xfad89413
+	0xf2e1fc25	0xccd1d762	0x43a52cc3	0xb8f96294
+	0xd05db9c9	0x760aed71	0x8b0d07c6	0x12e32551
+	0x04a17e2c	0x5559875d	0x145a9f9f	0xe8dd21cf
+	0xc81b8d9b	0x885bb782	0x93df24ed	0xdedbd4d5
+	0x8385507e	0x0e2e03a4	0x8b61a48f	0x452ca6c4
+	0x800c4bc5	0x3634577a	0x8a88f244	0x7c6952e6
+	0xba284820	0x55849ccf	0xfc706545	0x59aaf00c
+	0xe3554b17	0x4d56a632	0xb7d06485	0x8bdd62f5
+	0xe5f4ef61	0x16d2e19c	0xf851bea2	0x32322892
+	0xffb592b3	0xed4e8eaf	0x92974b49	0xb24d4db8
+	0x615c7f1a	0xfdc82a12	0x42364455	0xfc550c10
+	0xc8af5c1a	0x1ebede22	0x3a7c3fbc	0x5e573dc7
+	0x0382b39f	0x1f05874f	0xc03e404f	0x31fd13fb
+	0x2b11c5a3	0x162b8ae0	0xa6861122	0xe1b824d3
+	0x8bcfddbb	0x4dbecd7f	0xfdc25b5a	0xd16e15b1
+	0x55b5112f	0xf11217c2	0xd8139a4a	0x79d20da5
+	0x2c34b064	0x7cfe7771	0xd311f0aa	0x8dddcf75
+	0x3f493817	0x9b9b193e	0x2d5dfe6f	0x10f6042c
+	0xe7b2f72d	0xece22f9d	0xdf4fa708	0x533574f8
+	0x3341a9d4	0xd009d35f	0xc92922c1	0xeb24b1b1
+	0x26a9e0ab	0x288da2ec	0xc2ca2a7a	0xdad44c15
+	0x678390bb	0x306f8dcc	0xf3cc8f58	0x1f897400
+	0x0b08ebb6	0xc6999962	0x2d25cdb9	0xdb05ed8e
+	0x85e94793	0xde6cd4c1	0x70c01373	0x7e329df7
+	0x65a75cd9	0x700b19e1	0xf481c94d	0xa3946dda
+	0x32200c19	0x92baa53b	0x4fa53b3f	0xe71b63b7
+	0x8a74a1b0	0x490e4942	0xd256b661	0x7ceca619
+	0x181eee74	0x151effb6	0xaaa8753f	0xe9807163
+	0xd3ffdd84	0x9957bf49	0xe664e8a2	0xc25011a3
+	0x2d659ad7	0xf4b1414a	0xc4cca358	0x4d91d8b9
+	0x7530beda	0xb52bd177	0xaf8e90d2	0xd4ecbabb
+	0xfc9fef6a	0x1344e0bb	0x39bbb6c1	0x9f4c25b2
+	0x27c6efdb	0xb9b35e6f	0xae97797a	0xdd85fe41
+	0xa32fb35e	0x063e2404	0xdea1a837	0xafde0fab
+	0x55882c4e	0x38b4e391	0x437e49aa	0x2d46d297
+	0xb2bd8e6e	0xae36a3e6	0x1977f2da	0x46ba42ee
+	0x3f048c68	0x5f96ef92	0xea6eddd0	0x38539fde
+	0x3cad4c53	0xda123f1b	0x7c08143f	0x995b4425
+	0x91e7f202	0x13b3ffa2	0x6122c76d	0x27338748
+	0xbbf19aa8	0xab13342b	0x1df4d24d	0x95d8e41f
+	0xa85f001b	0x8b6617c5	0x8387c326	0xc63a9172
+	0x13d34c19	0x17d87d92	0xa9865c60	0xbae3f512
+	0x601f9f72	0x6dba49ef	0x4d62cd06	0x2cf42dc2
+	0x5ae11fd1	0x50a35fd7	0xd7795dc7	0x40310897
+	0x1a4bb21f	0x8c8113f5	0x55bcde16	0x2fa12370
+	0x5c6a1c19	0xc13b2571	0xd54d67c3	0x5d9674d2
+	0x5b28b05e	0x5dde9781	0x06a4e4fc	0x30b40878
+	0x171a86c8	0x641386e5	0x8e04cd61	0x632b95ba
+	0x9e802e0f	0x2b7a5305	0xeec8ea33	0xdde05bdc
+	0x454500a5	0xc279403d	0x1bfafe51	0x8032d0ea
+	0xa398b329	0xd6db01f5	0x1e4d454f	0x2f8c8fea
+	0x1bf7f3d9	0xead8f047	0x8b192c4c	0xc6939f19
+	0xe16366e7	0x107216b1	0xabd7780e	0xa24beece
+	0x4a04cfd4	0xe633886b	0x6acf4b15	0x85d74b92
+	0xde3358fe	0x765dfd80	0x3a14896d	0x9cc0fe2d
+	0x7550516a	0x05f7ae59	0xfe0b042b	0xe1d7c935
+	0x7a2e68b6	0x27d84d32	0x86f9f688	0xfc79d99c
+	0x9f18fa11	0x0eba09e1	0x5446dac1	0xc19da943
+	0xfd7aed7d	0xaca9b65d	0xc93f6976	0xbfeec780
+	0xb76d13b4	0xf872fd7c	0x31a67785	0x8f1869d1
+	0x5d95d16f	0x0eb43e3d	0x5ecccdba	0x39852805
+	0x92c43fbd	0x1c36738d	0xa08b382a	0x5da59286
+	0x059315ee	0xf3186365	0x5515e98a	0x23ef39aa
+	0x1dbd4089	0xbd7f88bc	0x1123394c	0x967440ae
+	0x97bec31e	0x4d7ad282	0xd6d8c9b1	0xa06c9673
+	0x96c73bf8	0xd58c200a	0xbabba6b4	0x1bef7dc8
+	0xba26cf24	0x92cb0af1	0x592f13fa	0xef4cdc58
+	0xd65e4cb7	0x48c4106d	0x1bdb7acb	0x65a4887b
+	0x1eb6f79b	0x7af8d180	0xfdc90059	0xefec18be
+	0x4203d88c	0xbf756ca8	0x6b11faaf	0x507607ff
+	0xb2af9e23	0xc74f2d6f	0x568e33ec	0x33bdb129
+	0x63748473	0x0a1bafe2	0xdd82c263	0x93e2fcba
+	0xe196494e	0x52005967	0x2be26f02	0x591332d0
+	0xc8ac5d46	0x17088f44	0xeca12983	0x3799c4fd
+	0x47f62095	0xeda06c65	0xf2cb3455	0x117e0c68
+	0x74fec213	0xc8a652ff	0x338e4840	0xf590dddc
+	0x0a3ee9fd	0x60e23d83	0xb44d23a6	0xe1920037
+	0xdce96701	0xfa34277b	0x9f9ab88b	0x8cfb722c
+	0x66431f59	0x4c37f1a4	0xfbfab598	0x95ee3437
+	0xd338f436	0x4cd9d0be	0xffad23d9	0xa3dd4d6f
+	0xfd4b53dd	0xdb5bc57a	0xddf2baa0	0xfdceccb1
+	0x12025458	0x2f29cfeb	0xebfc2d0a	0xb8d6509a
+	0xe7ce0731	0x0d8c538e	0x6454c057	0x8911157a
+	0xe99ae359	0xb7c960c9	0x1eab1fd6	0xda058037
+	0xa08e7b63	0x45870d45	0x0fb167a3	0xad25fed6
+	0x0844c4d8	0xfee41e4c	0xdd53b488	0x096c6c8f
+	0x5e6a34b7	0x5c24aafa	0x39df9116	0x101795ae
+	0x020add80	0xd644cd6d	0xfd1d7c12	0xc59116ed
+	0xe0b15366	0x90f56459	0xe035796f	0x698a88ed
+	0x78700bca	0x0d9fa980	0x6368b93f	0x61feac15
+	0xfd82b21f	0x8c694a54	0xc317fcf5	0xc2a18c95
+	0x2a3013ad	0xf83fef17	0x44467b9c	0x4047b2c4
+	0xdd920d54	0xd487e3f8	0xf0f92f79	0x13e48f43
+	0x9705bf94	0xfcbc9e3b	0x6d12d9b2	0x985ee1b9
+	0x2e24fa3c	0x46dd8662	0x1cc299dc	0xd21b40b2
+	0xeaeda8dd	0xbfbd1a40	0x8e1a0a8c	0x56a40b91
+	0xf95cece6	0x3a287e01	0x9e0907b9	0x3309b654
+	0x9a5079bb	0x36dbb78b	0xf87c0669	0x775ae8f6
+	0xd4332970	0x2a2a5975	0x28b0767a	0xc110195c
+	0xbf8f47a5	0xb7b9ec93	0x209d3c7d	0x553d8613
+	0x63559ade	0xf692bf89	0x4da236db	0x8d5d69c6
+	0x0991cefa	0x8461b5a7	0xf1d154b4	0xfdaab3bb
+	0x2959c2fd	0x1d5f7b82	0xe730df15	0x11011c88
+	0x016c4062	0xf8d7b303	0xa8ec06f1	0xdc49a98a
+	0xab73e277	0x6566e521	0x566feb86	0x29bb70ed
+	0xa163cef9	0x5e927c40	0x5acffef7	0xefec277d
+	0x07d1c031	0x63efda30	0x52aa8e08	0x3826c55f
+	0xf09909aa	0xdabc930a	0x8266463e	0x3b83fcf8
+	0xcc37dfb9	0x21d64edb	0x9c3b4dfa	0x39fce836
+	0xbf169f0a	0x034979bd	0xcfb36d81	0x381c7551
+	0x28e54be1	0xa8101c44	0x0179404e	0x0ea377f3
+	0x33b8f2e9	0xb7169617	0x9cd2eb38	0x767db03d
+	0xaf40bf7e	0x0ea102a9	0x7a5efc59	0xf2c4b32c
+	0x1547d8bf	0x996d0646	0x77aa0e71	0x3955d7bb
+	0xdd2b7fa2	0x08d5f569	0xda2425f2	0xd87cb778
+	0xa846b6ce	0x047c29d1	0x038a55a5	0x3dfac25b
+	0x3edb60ee	0xbbecb7d1	0x45095acd	0x3f135521
+	0x2f01df8d	0xc1e41e56	0x454d7265	0x85a2d14d
+	0xa233c32d	0x18413260	0xda873753	0x3084d995
+	0x3bde0b3a	0x96523ec2	0xdf924ff3	0xb00ec764
+	0xda13676d	0x58bc42bf	0x2829a06f	0x2efba826
+	0x00ffe1ad	0xd6b5cc2a	0xf53ff94d	0xcd685cb6
+	0xf9bed7db	0x0b4ddd1a	0xe8a448de	0xc495727c
+	0x68cf6052	0x11cf0218	0xb63d6908	0x24c1b0e2
+	0x75eaf5c5	0x7114c81d	0xd596913c	0xf8310f81
+	0xa1dac3da	0x50c235a5	0xd535df89	0x835ccdf1
+	0x2f0a0505	0xd6d76b3b	0x3a203ed4	0xded4a58f
+	0x7b7dadea	0x9103eae9	0x4ee7f33b	0xe785e1ce
+	0x5e0633f6	0x70beb9c8	0x145d7ea5	0x9e7891a8
+	0x2845916e	0x1a61b6fc	0xd90c9265	0xf915e61d
+	0xfcd5c8ce	0xa0f12501	0x6e2dccb1	0x388ecc82
+	0x9519ce00	0xbdefe148	0x1392dec2	0x58e97609
+	0x5bae1b18	0x69929d43	0xc2346b30	0xfa4a2e99
+	0x9ab7eb3e	0x3eb11055	0xd16d2ddf	0x7b70f2c5
+	0x55187d91	0x7d2c7520	0x0e69f3ab	0x5e2509c5
+	0x728e44a2	0xd7a612be	0xbabc885b	0x93016436
+	0x60258064	0x4bc489ff	0xff9de32a	0x98dbc15e
+	0x48eac41f	0xf753d2c6	0x3661eeb3	0xdaab4d1c
+	0x5d81d91a	0x8662b646	0x5952bdc3	0xe38c69e0
+	0xc8537ec1	0x6a9492b9	0x02452afe	0x8f06dd3c
+	0x565a0d06	0x67da4191	0xdc48099e	0xb777bb54
+	0x5d857773	0xfd4ad163	0xd49a6672	0xb2ef80f1
+	0xc6a96c41	0xa6e8db1c	0x6700f1a3	0x683d6730
+	0xa4580400	0x5feb5d8c	0x72dc9b68	0xf40dfab9
+	0x750400de	0x7cc468b3	0xa3e36eb6	0x5e029d98
+	0xd4632a18	0x527a7d4c	0x62bf1ab9	0x7c3a71b1
+	0xefe9c651	0x5e812162	0xaf0bf476	0xb11b216e
+	0xcac9f3db	0x9f068787	0xa4230a9b	0xc4ee7735
+	0x091099b9	0xe0c89a2e	0x844b5e78	0x9a208c07
+	0x86f48fe6	0x1f2b8bac	0xc8873d41	0x7380cce6
+	0x1f80f956	0xe9ca8d9e	0x4baddaf9	0x2687537f
+	0x9d4e2f19	0x8a634fdc	0xa5c1c324	0x258f1e18
+	0x4399e859	0xe43a7e7c	0xd572faca	0x914bcf39
+	0xf2dd53f1	0xde126168	0xa4940acb	0xc8edb772
+	0x4a089deb	0xe9308ae3	0xad97a55f	0x8853ae8c
+	0x976d4337	0x919b885a	0x155ac377	0x5ffcdb2c
+	0xec335ab0	0x4118c00d	0x10f6d291	0x89adb1bb
+	0xf514c024	0x2d6513dc	0x8b8743e2	0xff2fa127
+	0xf4be8a38	0xb54de614	0xaf2688c9	0xd50dc4ac
+	0xdf71a920	0x7556deb6	0x2b0a08f4	0xeb47487d
+	0xae9244df	0xf81216e3	0x42699e0b	0x953ce6a5
+	0xa3fcb558	0x76547905	0x95086ca7	0xf29f303e
+	0x027975ae	0x313b5bbd	0xa8f8d662	0xf32c6538
+	0xa4c44558	0xe626d8aa	0xe7b73b5e	0x21957cb2
+	0x4f830a34	0x713f6e71	0x52241020	0x4f152bfa
+	0x1efe2a53	0xf45c268c	0x569e09f3	0x4878ef31
+	0x77198eae	0x0057bfe0	0x71541c01	0x1eff510d
+	0x34d84a6d	0x43787da0	0xdc4bbc4c	0x9c5656a5
+	0x067a0908	0x806d8a21	0xff3cf1eb	0xbeb9435d
+	0x5dd154a3	0xd4cf6735	0x376e86cb	0x114cbc28
+	0x4e26f648	0x9e15b6a0	0x57e5ce4c	0xb9a084f1
+	0xd9a0385e	0x4cd29cd6	0x80287ea5	0x12609d95
+	0xc705541c	0x0b9cd2a2	0x98af1097	0x0e0ccec3
+	0xdbfb6216	0x370549c6	0xe36cd94b	0x7a71d4b0
+	0x09e51ffc	0xd83c2c6d	0x32e63037	0x87b7c18c
+	0xfa74b115	0x3045a93c	0x146ecc07	0x329bf17f
+	0xcc50fa94	0x6ae5027a	0x9ec70396	0x9b8f3ecc
+	0x565335b9	0xce0a5dfa	0x2b41d3cc	0x6f20e5d8
+	0xd1ab9ee0	0xd5f04207	0x4296927a	0xe5c629e0
+	0xf7b776cd	0xdec98eae	0xff1fe0ff	0x2fe2e3f0
+	0x9ffe3481	0x3f649922	0xfd960e99	0x88ffd8e4
+	0x417db733	0xb233f1e7	0x9dbb56ae	0x271646bd
+	0x8f6a6a2d	0xdf70cbff	0x64ec8381	0xfe97aca2
+	0x48a8099f	0xbe96d90e	0xd32416b6	0x0136efca
+	0x71676cca	0x9d6ba000	0x5c040306	0x0ea08882
+	0xd41a8ef9	0x30dbe3f9	0x73e822db	0xd791f185
+	0xacbe39d6	0x4ea7b8b2	0xde3092f1	0xa1b98671
+	0x83507aeb	0x3be451ba	0x57c7c672	0x773399f7
+	0x9cef2b76	0xaba00924	0x4a333a0d	0x59bef9b7
+	0x77b7ae3f	0x7cbc022b	0x99825bdc	0x6b434156
+	0xbe86d9d7	0xdfd89b81	0x615301f0	0x645c2004
+	0x81a0d706	0xfa5fc5b3	0x3ddea2ac	0xf8b77c77
+	0xdbb9afbf	0xb2966f32	0xa9ef0668	0xf80a9fd0
+	0x46b678fc	0xa5e4783a	0x585cd0cf	0x8dd017a3
+	0x5df45495	0x0f96a151	0xfbcc6c28	0xbbb01982
+	0xc60b9014	0x0da33bd7	0x3f8c9e48	0x4bcad7ee
+	0x8f29bea0	0x434bd06d	0x2d40ee8b	0xf674fefb
+	0x7d13c2dc	0x8b102d90	0x25ee47b1	0xee42f973
+	0x6abff5c0	0x90337ecd	0x650b75fe	0x57592038
+	0x9b8172de	0xa818a53a	0xc9ba76c0	0x84f6302c
+	0xbc2dacbc	0xa33c4350	0x05ffcbf9	0x46178e9a
+	0xb8802aa7	0xb77cca54	0xc4acf832	0x6329da72
+	0x9e0bc1d4	0x4dbad7cc	0xcc1435a6	0xf62df35d
+	0x23bf4f9d	0x5655c820	0x8f362a62	0xbe3c7c4a
+	0x7db11ca2	0x3a5c8fd5	0x04b9598a	0x67a21cf5
+	0xfddeb57a	0xcba92e27	0x85dd2a2e	0x410c03f2
+	0x37d01792	0x52fea426	0x6bfdf31e	0x63cb798c
+	0x6fd48d31	0xac08449f	0x76fd6be5	0x59b6f6fa
+	0x7d7bb61c	0x8a921346	0x5fa14930	0xd00ef222
+	0xbb5d6d04	0x7e4542be	0x56532853	0x6074a287
+	0x21f8b4fe	0xb91b2398	0x72287a1a	0x4edce9fb
+	0x5418c044	0x3b90ef86	0x38620751	0x9fed1072
+	0xc8d64b1d	0x397a4379	0xc0534beb	0x806c80e5
+	0x309b7d0b	0x0ffe292c	0xefb53f50	0x3cd38191
+	0xcc5a6cd9	0x1dca92dd	0x3f7af05f	0x796e20ab
+	0x1715da6e	0x5bb48b9d	0x8a06a2fe	0xe06fd98b
+	0xd7a429ed	0xea2c8ec4	0xb365f13f	0xa803131c
+	0x1ebc16db	0x1e85595e	0xa370b578	0xd3036dba
+	0x0d97668f	0x6ebf2e28	0xde53e48c	0xef8d9c9c
+	0x1697a020	0x65362f2f	0xab0b2447	0xf06ac16b
+	0x68cd2cc6	0x8dee764e	0x41c7f21b	0x89a7d310
+	0x171bfbeb	0x93233fc8	0x4b72e18b	0xef38bda3
+	0xe5a9b23b	0x1f4f7ea1	0xeed90665	0x2f8899ad
+	0xcf933790	0x878ec306	0x59c63347	0x73da1ec8
+	0xcd703bfb	0xdba0f460	0x412023f7	0xf5ac4823
+	0xfd3d5203	0x34b71f30	0x280e7077	0xfab4283f
+	0xb666f47f	0xd5410131	0x79f36bff	0xa94a4d26
+	0x100c5a04	0x4f588fd2	0x6630ad71	0x26a5946e
+	0x7f690901	0x82d8e4e4	0x99bfeafd	0x687f3ab0
+	0x6c99abba	0x988bc7a7	0x23c19c3a	0xae9a5d40
+	0xd0545a03	0x4b9eda6b	0xfc01747e	0x6c02950c
+	0x099d4e73	0x32bc7385	0x299c25a6	0xe8a3095c
+	0x3acaea23	0x893b3b01	0x7ce8a326	0xa4ebeb1a
+	0x64509259	0xd9eebbb8	0xa88fd8b4	0x7b92ed79
+	0xb41eb189	0x50bebf8c	0x9763eca9	0x861359cf
+	0xeb0716f4	0x34d23cee	0xdb7a4372	0x193cb7cc
+	0x7ea76d3e	0xd26c0d17	0x080753fe	0xdacb9dde
+	0xbcda60b5	0x64f756ae	0xf19ded12	0x69775827
+	0x9d581039	0x444e92ea	0xaf3fe40f	0x49c17460
+	0x62b3f21e	0x2e20a0dc	0x9d1e7d46	0x66a6a703
+	0x45c8ada5	0x6ad9e74e	0xa0ab96c8	0xa0c1ddfb
+	0x9ed0fd66	0x659c874a	0xf3ece1d8	0x1b0302d5
+	0xa4ab0a5b	0x78e4ad92	0xef11406b	0x3a02e6ec
+	0xf733a593	0xea7a3997	0x0f4930b3	0x18ca72cd
+	0x8e312e70	0x345fc898	0xb38aedd0	0xbc7adf8e
+	0x580b9f57	0x7dd53eb6	0x1f0e7300	0x5524f2fb
+	0x25280378	0x45dddae7	0x2f1b38fd	0xd9c448f0
+	0x4c561bcc	0x72d2320e	0x23de442b	0x7f5b9046
+	0xfdd80059	0xe9ca2598	0x5527ef4e	0xc834b9bd
+	0x1dbc357d	0x2656f81d	0xa9549423	0x338e5639
+	0xc19706ac	0x0ca6028d	0x86ef336d	0x6c822807
+	0xe40fb194	0x4de2320b	0xb9eef8be	0x33655612
+	0xa2cd1803	0x480ce7cd	0x51c19215	0x68f2c282
+	0xdb097679	0x0f694612	0x03d9bf77	0x3f1e04d9
+	0x3e613825	0xe5833060	0x729a811a	0x2a4ae763
+	0x05cd1497	0x8fbe47ba	0x04e83aa2	0x505717f0
+	0xbf0b978e	0xd378cc7b	0xeee38551	0x5092a751
+	0x52dd9f6e	0xd59ee759	0x4528f839	0x2003c88b
+	0x10b9afa8	0x0bb880c6	0x5bbdc70d	0xe9b5e179
+	0x0941507e	0xee252bf9	0xea772da9	0xf099310f
+	0xf6fabcb0	0xf038e392	0xac061a3f	0xd51656f1
+	0x514935bc	0x3fd22f7d	0x254b06a8	0xff2877f5
+	0xd848996d	0xef66e1a9	0xf79ed46c	0x2196e979
+	0x522b472d	0xcfedf066	0x9a768bda	0xd48632f4
+	0x4773ccbf	0xec4435f4	0x46f7be05	0x2bc5d794
+	0x03f31d81	0xfb7103cf	0x3dedb78b	0x9fc36042
+	0x2280e88e	0x4d250150	0x8fa7e54d	0x5cdaa33f
+	0x4b52bf85	0xb32a714f	0xce7a9013	0xed0fcb60
+	0x8718e79b	0x74e26a9e	0x1fb725a0	0x6e8a63af
+	0x332eb12a	0x36c32a05	0xcc456676	0x95dc04d1
+	0x77f85170	0x304a6906	0x8612e7d3	0xde994cd9
+	0x0b285e4a	0xe60b523c	0xabbfd040	0x374c76b0
+	0x5e40f411	0xe93f8f9d	0xd55059cd	0x2c40bb2c
+	0x1d0bc87b	0xf258dca2	0xb66c26da	0xead5a854
+	0xedf1ab2c	0x2392bf2f	0x3480ebc9	0xf5f1dfab
+	0x4336fc17	0x89bc6f5e	0xf794b812	0x12300220
+	0x8cf10ef0	0x55d78885	0x5c0cbf25	0x1915799b
+	0x52b6d7e1	0x310bdab5	0x07edfb80	0x243abead
+	0xdcf99a9b	0xa9c5148a	0x12d2c0c2	0xc1478005
+	0xd27224d0	0x3bceb6d7	0x9e033549	0xe132349b
+	0xdf5a4ccf	0x3e777127	0x8a2233fa	0x3758bb10
+	0x85ccb13e	0x7b8155b7	0x85bf5cb4	0x26a7a7b0
+	0xcc84ba7a	0xcc0285d7	0xf416da1f	0xffac6701
+	0x95ac6f58	0x3cb13304	0x407406d7	0x14d99a71
+	0x1cc0fdba	0x298468d1	0xbea241a6	0x126fdf79
+	0x8875ee25	0x9f6226ba	0x64678e21	0x2509f53c
+	0xffaf9851	0xe812f808	0x8ba956e0	0xf457db00
+	0x518fe465	0xf160a88c	0xe448bdce	0x930c070c
+	0x3c5c081e	0xca3ae614	0xa831d664	0xf7c4368c
+	0x08fe2afe	0x1adf7b81	0x17f6d3f3	0xb2fee3ec
+	0x9c28bbc0	0x79542475	0x286ef63f	0x4359beff
+	0x7e883a76	0x197d355f	0x63b49b54	0x863a746a
+	0xbb27e270	0xd341236d	0x12f44393	0xb466e0a4
+	0x1d76fb92	0xfa41d1b2	0x1d8c4a73	0xb2d9dd7d
+	0x86b63425	0x425d7223	0x15de6bf6	0x925a9489
+	0x2bb11f48	0xf6dbba84	0xb7a7d5ef	0x20962b37
+	0x02d0d4ef	0x8cdb97c2	0xdca7fee5	0x149444e0
+	0xec103a29	0x7f51f8bd	0x4d5c6758	0x9eb4446d
+	0x6ebaf66c	0x02325a25	0x8bdb761a	0x650dd77a
+	0x1c8e75bd	0x0837afc5	0x6472dfe2	0x3830220c
+	0xf317f6a3	0x8554a846	0x342a150c	0xe4ace9d1
+	0x4ff2e1b2	0xa4d50080	0x95d1c85b	0xc5dfc5a6
+	0x0766a97a	0x71b2cec1	0x8043996e	0x620fb5ac
+	0x35cc0e1e	0x9e0be88b	0x1bd723fb	0xdbe05966
+	0x8d7928b2	0x97561525	0x857d12a9	0xa84475bd
+	0x94a6acd0	0xda298885	0x9a039423	0xae6cac16
+	0x7a76851f	0x70277277	0x50a53b6e	0xa9100daa
+	0x4090b164	0xc5dd2129	0x02475e30	0x1cc65bae
+	0x85790253	0x5eea73b3	0x1b4343a3	0x13ece90f
+	0x470ac2b9	0xf61841e3	0xef6655d7	0x1992dfdc
+	0x5f5112ab	0xb4dd51a3	0xc5e87b31	0xb65f3d2d
+	0x070e9bbf	0x05ffd055	0xf609c346	0x65fbba75
+	0xc9108013	0x7bfaa5db	0x49dd3066	0xcd8c524a
+	0x99d8fcbe	0xfecb842e	0x739feb70	0x79c75772
+	0xe4cd3f68	0x1b062319	0xd3360038	0x7658335a
+	0xabee5b58	0x466809ce	0xde21f2cc	0xa197a1f5
+	0x92287d5a	0x21a75ff8	0x095e0058	0xa38bf1a9
+	0x57ba37ab	0x4747ff64	0x4a12b779	0xc12ddd5f
+	0xe7a19a45	0x1b927ca7	0x88144955	0xd35ef843
+	0xd068337d	0x5632330b	0x65a34c89	0x775e9caf
+	0x78c20a0f	0xff1c2f5c	0xdbdd9887	0x7f48e40d
+	0x54ee1f8b	0x65d42710	0x5fc0d0e7	0x15fce5dc
+	0x318b5abe	0x7860c719	0x6f63f527	0x95bc6f90
+	0x58c37cc6	0x4334f068	0x3f51dc09	0x851a2b85
+	0xe82b9da0	0x7d265c4c	0xfd8ebab1	0x83d54210
+	0x3f74b74a	0x7ee0c3ca	0x61a3a8db	0xb0b704ef
+	0x477cd2cd	0x2a796236	0xfc383efa	0xa6ed3b51
+	0x24791edf	0x80562e6f	0x1273a1f5	0xc74e5921
+	0x3779b3e6	0x7a3f32f0	0x49e60afd	0xa5d0fe64
+	0x8ef054f6	0xef5be639	0xf692e588	0x54044e06
+	0x3f27c315	0x55bb8f4a	0x96554540	0x550e1a56
+	0xace36033	0xff19182f	0x86a5bd4c	0x85da4168
+	0x986a002c	0xd7857384	0x76af389e	0x68ad939e
+	0x2b70c6f2	0x449ee188	0x92c907ea	0xbf2764e4
+	0x3bb587fe	0x783d282c	0x45534e20	0x10658cc2
+	0x4de7c28b	0x0a1c55a5	0x2bacd66b	0xf0a46ce6
+	0xb7ec3bbd	0x1f5e80a8	0xdd058c42	0x7332d51d
+	0x3cef2355	0xa3b65cb8	0x1ee63aca	0x9f957ac5
+	0x0281c9dd	0xd26aeb78	0x58cbb21d	0xac33a189
+	0x7ee718e5	0xee82aae0	0x02a7047d	0x97ab6b72
+	0x525cedb4	0xe2349594	0xd5ae4bf8	0xa339d3c8
+	0x067f1b36	0xf64bdbf3	0xe9a3ddc6	0xa4c5c24c
+	0x6e353ab5	0x0738144f	0x47a2447f	0x9e68b3ce
+	0x78e80afa	0xf940582b	0xb89ec8c9	0x2c6d309d
+	0xd61b1cfe	0x9636289a	0x6117fba6	0xc79f8986
+	0xaf1541bb	0x9c0ac0e6	0x8387473d	0xb9fafa5f
+	0x6a579a20	0xd3f7bde5	0x5cafa55c	0xc4b019eb
+	0xd5898c2e	0x773a5c0c	0xb0094e24	0x8911c4e3
+	0x5c1617aa	0xea4d1e5a	0x4ca917bb	0x616d3d63
+	0xe78a22a2	0xdf438e2f	0x2a95a02f	0x7bab22b1
+	0x7e10fe4b	0x419950b2	0x416176a3	0x87eb366c
+	0xdab47c2c	0xf1ca38ed	0xf3e0a547	0x7a17a658
+	0x302b56f9	0x49c64bd4	0x73411255	0xeced949e
+	0x7b34d21a	0xfb29e71d	0x73833d01	0x03394245
+	0x29976efb	0x43283d82	0xe99524fe	0x86cd9b90
+	0x53908651	0x4bc2181d	0x9e5edd8b	0xa422354c
+	0xc027e7e2	0x8ce2db84	0xc58d19ce	0x355c8b91
+	0x25018861	0x1c72bb1f	0x751abe69	0x203350d5
+	0x7a483fa4	0xb2c3f20e	0x1f0a5ba0	0x01b7e2eb
+	0x1a043812	0x7103279b	0x96216501	0xce39d080
+	0x637f4509	0x2dc69eea	0xa4efc113	0xa5d30a2b
+	0x58340b23	0x028a5b36	0x55f38544	0x6a1446f7
+	0xd1414b79	0x2911a443	0x0db0caff	0x5da8e7ae
+	0xba030f57	0xe3aae6c2	0x0b058245	0x87da158f
+	0x37e8eead	0x321192c6	0xa450f2b1	0xf1a7353c
+	0x2a704f83	0xce0feef0	0x7d817a79	0x26831535
+	0x365a1cd9	0xe9e2d8ee	0xe8d0f555	0xb4293ebe
+	0x2795664b	0xecf43916	0x1a2489e4	0xfb7a2f91
+	0x524f46eb	0xc580b7d4	0xfb48ec9f	0xe9edac5d
+	0x687e2734	0xd4d78bfb	0x1c6693a8	0x9204e278
+	0x2b030f0a	0x1c1e5dde	0x1233cafa	0xb28f23fd
+	0x3e9ec6d9	0x340daf97	0xeca43ed2	0x7580c01b
+	0x98bc3331	0x81df920f	0x66fa4723	0xb5576074
+	0x560b0b7b	0x2b330f51	0x11d4383e	0x2403d863
+	0x2ea9ef88	0x0a4f364c	0xff826ec8	0x1a2b598d
+	0x27336491	0x3ed50c05	0x7fa670e9	0x117c4928
+	0x4f7cb2e1	0x0246bfb8	0x0299dfb8	0x25da1033
+	0xc943c492	0x0c928512	0x88231d4b	0xfa8cd638
+	0x648b0dd2	0x8dad6a9e	0xa6fee246	0x48c260f4
+	0x89f51cd7	0x45d87837	0x7dbc8e53	0x43ae16d4
+	0xb6537ed6	0x5623ab3f	0xa9067ff4	0xe7357501
+	0xb74554de	0x8db2a8ee	0xb1e92a76	0x6e8970ad
+	0x5266a3f0	0x90df4e6e	0x8d646d19	0x4cedc27e
+	0x2bf8d9b2	0xf525778d	0xbdd502ab	0x51bab600
+	0x4eb5b0fd	0x7fe503f6	0xb93e599e	0x2e7d6071
+	0xdde8884b	0xc91c3510	0xa8e14896	0x1880e079
+	0xa4c89f7d	0xadf62f1b	0x6ff233d7	0x3be5bfb6
+	0x6d105d93	0x120397d9	0xfed419c5	0x205a6631
+	0x4d0ccb3d	0xae0e1f09	0x86b9112e	0xcdf2228c
+	0xa0e388cf	0x7456f52f	0xed2d99fe	0x6914f63b
+	0x00feaad2	0x8733d05f	0x2c466ea4	0x7fcff031
+	0xa529f5f0	0x729f8fa1	0x7df47b76	0x1f711f4a
+	0x81e6e406	0x5eb25e9f	0xf762231c	0x26420e88
+	0xae513342	0x6b1ad7f3	0xa5a6a7c8	0xa1ddb22c
+	0xb838a4c3	0xb227f5ff	0x6b86a07c	0x99414531
+	0xde3a3511	0xc284c098	0x3946172d	0x8797e956
+	0x5287bf4d	0xdc668157	0x514f837a	0x0898e1b2
+	0x923d59d4	0x9bd5b501	0x24ab0c95	0xd9a6b20a
+	0x938f61e6	0x14ff757f	0x285003aa	0xdaa7c43c
+	0xd1831a8c	0xe3ee3682	0xf1840914	0x3925fe7d
+	0xf0837c25	0x10228862	0x17fa9af4	0xe7dcc72a
+	0x1849b0f5	0x51320d1f	0x0333beea	0xc35685e7
+	0x0160dbe9	0xca507680	0xd6f2f43b	0x4c9a31d0
+	0xdf6460dd	0xaec8cba3	0x52c8bdaa	0x2664c6ee
+	0x4b3288c4	0x53cea59b	0xfb6ace34	0x41dc20e1
+	0x6a5f4706	0xbbedb5f3	0x9f37322e	0x44a09752
+	0x2ab91444	0x57b4ada9	0x6afe576e	0xaeb73b50
+	0x97d3de4b	0xfec4d616	0x29896080	0x43fe8c34
+	0x83842eec	0xb08f170d	0x03c432a7	0xfefc7b82
+	0x51f66600	0xed503541	0x03b6608d	0x8e3ad843
+	0x4bf99ad2	0x614c069f	0xce7641b6	0xd27a6f9a
+	0xd40eaa7d	0x110c143e	0x352d0651	0x4473dffc
+	0x5d40252f	0xa25db878	0x7df32c3d	0xf4ef6edf
+	0xeaf881a4	0xe88b9a18	0x7df554b9	0x1891b621
+	0x55af4ac3	0x8c39df79	0xc4c205db	0x4b34c0c1
+	0x8c0ff68f	0x72bc50d3	0x5f99c8b5	0x7ba6188e
+	0x798c3d10	0x26870c75	0x90a64bc3	0x6979b922
+	0xbd185fdc	0x6b661e71	0x0beab544	0xbe84004a
+	0x3aa803bb	0xb1e808f0	0xaf7e7b83	0xb12a39d7
+	0x616490f4	0x920b37c9	0x857eea29	0x6d6ca978
+	0xa8388103	0xf4218257	0xfc9a0717	0x4c739240
+	0x3e79ce00	0x3dfd18eb	0x37138fa4	0x9894c467
+	0x507d7d56	0x26c1bc89	0xe787e45c	0xdf554cc5
+	0xd2279a50	0x5b172582	0xcc5d24a4	0x7dafb34c
+	0xd4b16c6a	0x21b79147	0x89e1024e	0x04094b5e
+	0x850c0a4b	0x0c7cf33c	0xe4da26f7	0xa1a62536
+	0x920afaa2	0xba63c038	0x16591450	0xcb6c34ae
+	0x29464a83	0x1cc673d5	0xa530ea51	0x265ec529
+	0xe30bb676	0xbf18606c	0x3f12df0f	0x1ab669d7
+	0xeee0c289	0x33106be3	0x00e39909	0x5a312123
+	0xcbda8bb2	0x0d3ec086	0xdd7c0f83	0xb7ecd1e6
+	0x1b3002ad	0x737b819b	0xa5dd3b45	0x632f9c32
+	0x0ab37cb8	0xad7eb92e	0x6e2d114c	0x586e0994
+	0x2af40df2	0x5501217c	0x0ab62f0c	0x3b7100b8
+	0x0dc35d9d	0x3937491e	0x04f37faa	0x6933c2af
+	0xf1e2c593	0x8c66b14e	0x7d542e43	0x970d2632
+	0xd49e3d2f	0xaf9d7d2a	0x327e5488	0x871a50fd
+	0x3f1158fa	0x2f3838ec	0x9617a31c	0x16e2c967
+	0x09710826	0x077a1657	0x95a1abe9	0xea49bab3
+	0x32ee12a9	0x2d49626e	0x9b95c7dd	0x4846b0a7
+	0x9cfae6bf	0xa9f862b6	0x3e3d167d	0xa544a3e3
+	0x94cccf7c	0x8b97f7c6	0x022b9624	0x5b60bf75
+	0xbd533ed1	0x133cc7d5	0x3853ff82	0xca2bd76b
+	0xed552e3d	0xf133d2d5	0x652c0f02	0xdec8249c
+	0xf61921ad	0x09a9e3a3	0x2229e133	0x01afa009
+	0xc843783f	0xba96a153	0x3d80b2bb	0xbf5398c3
+	0xb66ed306	0xd48fdf1d	0x39040227	0x1f1980fb
+	0x51e740a3	0x6603060c	0x9ce34405	0x9abc2a4b
+	0x7ece5908	0x457998a7	0x45443d10	0x20f2a0d1
+	0x9cac676e	0xb8e66c6f	0x4cbaa744	0xecdc6c5f
+	0x5be9ad3e	0x1a7af08b	0x94375052	0x9547a526
+	0x3f3d7a29	0xfa571d4f	0x00324a11	0x003ed568
+	0x92224138	0x0bc6fa9c	0xd4dcb738	0x81932d66
+	0x27525a40	0xee39a4b5	0x4ad66faa	0x59c5ca88
+	0x578921a5	0xb493d0f3	0x005d131f	0x49bf227b
+	0xa8ea547d	0x2e5c9a48	0x16afbca7	0x34e8a7d1
+	0x5aea0b5b	0x82c3e281	0xc537c374	0xefe8922e
+	0x4ed6aa04	0xc957d8d8	0x54887681	0x61da5bff
+	0x7d116291	0xf2046fc6	0xb71da398	0xf9ddcc7f
+	0x7a884d46	0xf0bdbbe2	0x5fd74815	0xf86cf766
+	0xf588e4ba	0x88d910f0	0xa246d4b2	0x5b2e87cf
+	0xef07a06c	0xefbb295a	0x6be0b60b	0xa0684b8d
+	0x2e4ba4a7	0x32aea4e6	0xde8df602	0x9754eee3
+	0xb79c1df3	0x92819bcf	0x6e2212c1	0xff2ec504
+	0x970e83e3	0xe44c1588	0x25ef7a1d	0x78439e8a
+	0x49befb02	0x30dcc732	0x2abf9573	0x8fb2d451
+	0xb708f582	0xba802a07	0x5a4b4d7c	0xac3d8fc6
+	0xda0c8cdd	0x616ed6ef	0x371d43ac	0xd7e81188
+	0x197b6cce	0x598b7855	0x81091bc4	0x73115e41
+	0xaff509b5	0x62ec8b9c	0x070f53f9	0x65e9acfa
+	0x46b936b1	0x5a97edab	0xbd9093c3	0x7e56e0be
+	0xceb08216	0x523f649c	0x73565919	0xd5a478da
+	0x5e49884e	0xeed780b7	0x670f342d	0xcbec0af2
+	0x60193aa2	0xb9b836f5	0x88142d75	0xb6ef20ec
+	0x45ecc95a	0x86fa7d20	0xbed3332b	0xd72235ef
+	0xf3dc1ee6	0xdee60153	0x17c288ee	0x1598ee3a
+	0xad8be82b	0xbed18162	0xe741e3ff	0x7b2ceebf
+	0x0c023ffd	0x228d9357	0x2519b917	0xb21337c5
+	0xf7ef1ec9	0x1e38a02c	0x2aaca8aa	0x91ad2397
+	0x39b94e45	0x9c16a80a	0xab4f0207	0x9fdd96e8
+	0x4c7e82b0	0xe58e52dd	0xb35c5152	0xf72c7988
+	0xe15b2b53	0x37b3ca5a	0x382cf820	0xe9a5b10d
+	0xfdac3128	0xd613d631	0x0bfa05b4	0x8ed858c9
+	0x48fa9bf3	0x6b0a24b3	0xaea3ded7	0xfe944124
+	0xbfa01ac8	0x90c4b032	0xd506ef49	0xf3c2a52f
+	0x1e717e29	0x9d032123	0x4eff6847	0x87fe7932
+	0xf91e0251	0x7291c0e9	0x04c8865e	0xe26812d8
+	0xd7af6deb	0xab8b239f	0x0d357507	0xc3f23049
+	0x0fcefb47	0x7c1ebbbc	0xda0ff8d8	0xa2e91757
+	0x2cdd7611	0x51b85a13	0x1a658155	0x97ba5866
+	0x7b02d127	0x9a65f8dd	0xcea44087	0x3c44fedf
+	0x6cba4b83	0xb30c9c48	0x5f33e368	0x46309d1b
+	0x5e97e1a1	0xd4dfca3c	0x03762329	0xf499e182
+	0xa8b3de50	0xd6a940c5	0x420b4200	0xebfae5a8
+	0xfff42408	0xd034dab6	0x0fbfc9f8	0x618c48aa
+	0x3258a668	0x040eb946	0xa3e0adf7	0xc5374611
+	0x640a6581	0x57444570	0x4249f689	0x44f6314b
+	0x7461455b	0x13066c2d	0x0d3d29c8	0x58e15f8a
+	0x454ef231	0x9185d050	0xe99a20a0	0x7a06d75e
+	0xd7449ae9	0x93e6bbd3	0x872176d4	0x333d8cd5
+	0xcb511dda	0x3c1ccbee	0xe36c2ec0	0xe9344c87
+	0xf54d7abf	0x531dfea3	0x7272fa0c	0x4c3dc858
+	0x3d13b763	0xb2996ab8	0xa0a21103	0x95e9b6c8
+	0x240dd708	0x92e0ca36	0x3945b765	0x436cc495
+	0x333ef58c	0x463a6f85	0x793e9df9	0x9fe86bdb
+	0xfbf0cbd5	0xdac52990	0x4c3afe5b	0x267ad809
+	0x662c4ebd	0x6b4ac1be	0x89e7bcc0	0xfe4a7721
+	0x48b4de81	0x4c81164c	0x1131ab47	0xc661f7e9
+	0xe1d1bb65	0x7b57048d	0xdc99c55e	0x215a3641
+	0xafd86760	0x1b2d56d1	0xe76d8f74	0x559c649f
+	0x97219fc9	0xd5333043	0xf846c8fa	0x8cb63ba0
+	0x1b320870	0x884e95cc	0x1655b161	0x4ee1ffd1
+	0x376ce49d	0x028cc7f3	0xcc13e8db	0x9712f287
+	0x753196b9	0x4227cf42	0xa5c3c359	0x37b5733f
+	0x8e2920b7	0xe0e6198e	0xc9cc7de5	0x8b8d8fb0
+	0x93807f0e	0xc476c872	0xda4d5c5a	0x4ead8398
+	0xe5da2718	0x253611b6	0x54273437	0x435528ed
+	0x37fe8557	0x3f31ac9c	0x4ce87c33	0x83f19d78
+	0x5b7974d6	0xe62a980d	0x0d35445f	0x6823eeff
+	0xfb23d49c	0xac42eaef	0x7cf3f7db	0x4703e364
+	0x2fbad2c7	0x6ad6c9ca	0xdeac6634	0x9aa4e069
+	0x16375fed	0x5a37affa	0x3ab2c7f4	0x576377ba
+	0x9ca8949d	0x9eab830a	0x2eac9f46	0x20140d74
+	0x49e169a4	0x29c8228b	0xb10c113b	0x97486ddf
+	0xb268ccbd	0xee145285	0xf6db444e	0x2971a507
+	0xe20506c1	0xaed3b844	0xa7d3a71f	0x0ec8a80f
+	0x3964b61e	0x664c06c3	0x8aa6f07d	0x190bd9a4
+	0xa713711e	0xc149601a	0x0e33b930	0x92d924b0
+	0x3a3e6055	0x891417db	0x9da57235	0x7a5c95cd
+	0xb220a13a	0x61486a53	0x84e823ae	0x3a525213
+	0x8f83fed2	0x97a20f72	0x01d40e7a	0x51a8696f
+	0xf78ee740	0xcbe3f17d	0xa03fec72	0xa3c10477
+	0xeee0cc71	0xa4275070	0x71a4858a	0x3e6c10c5
+	0x157f1c48	0xe761a235	0x7ebd0044	0x0587573a
+	0x504bace1	0x18b0e30c	0x87da65c8	0xb09e218f
+	0x394ddcbc	0x30850b35	0x870144df	0x308786b3
+	0x3b5e72c7	0xae824b41	0x08dcbadd	0x4205606c
+	0x0dba1b98	0xea8b026a	0x0ff80267	0x4d345dde
+	0x3e9fe94b	0x2e5150ee	0xe690ebe4	0x7e15f05b
+	0x6fd516be	0x113d1f78	0x8e460364	0x0a18c989
+	0xc858ba5e	0x65229038	0x7103dd07	0x9cd5dfd4
+	0x1d90fe4b	0xe020ff30	0xcd525bd1	0x9b44f15e
+	0x535137e9	0x06e76f27	0x7fef31ba	0xaf21d659
+	0x9f96533b	0xee3b980f	0xf88f1efa	0x47e69092
+	0x7384ba38	0x76c06863	0xcdea308a	0xf05dfad0
+	0x954345cd	0xa0c58d59	0x82cdc2ff	0x5501bae6
+	0x1ca051d2	0xb992dc65	0x98d2f849	0x759e5af7
+	0x3f6ba599	0xbd2b801a	0xf24cf7e1	0x523f4bc9
+	0x280bbd9f	0xaa28b183	0x8b41afce	0xa4ffac7c
+	0xd7555ff9	0x15e6d70a	0xf7d9ecf0	0xf647181e
+	0xcae10548	0x7bf3059a	0x5f53e585	0xf168d5de
+	0x78041850	0x3f3c1c0f	0xbb820ed8	0xe84de7fd
+	0xe0f8e79c	0x06b59d3c	0x42cde450	0x40068ecd
+	0x239241fd	0xef3e69fc	0xe54ca169	0x026d86ef
+	0x790f5960	0xeaac92da	0xdb1ea331	0x34b1795c
+	0x975382e6	0x383576d4	0x9846ba3e	0x7d666cfa
+	0x63c9f2c0	0xcb0b0e51	0x15de13af	0x5b50543d
+	0xf3088ada	0xb0a0eea1	0xa16789ae	0x023687e5
+	0x3fe5a0a8	0x2d087c46	0x1a9f7dfa	0xc111594f
+	0x22f0c9e5	0x23519d74	0x063af453	0x3dded0c4
+	0x2fbec97e	0x94c3a2ed	0x712515d9	0x4e23c2bf
+	0x47ffab6d	0xcc975cde	0xb2cba5ae	0x4f64f77d
+	0x1170d2e3	0xc8ec9fcf	0x548eb6b2	0x28c636df
+	0x7b85e66f	0xc3ae89e0	0xa769b4eb	0x3f7b60d3
+	0x99ae9021	0x32951125	0x38d1f0f7	0x635b3981
+	0x784cab8e	0xb9ac2ae0	0xd9c8e406	0x849e2f3e
+	0xbd46e71f	0x31cc9145	0xcd817b28	0x5d234af9
+	0x5682e8f0	0x6963b396	0xbf42c2b3	0xa6b17649
+	0xb083630e	0xe2bbb3f9	0xe2812105	0x524c7c1a
+	0x3587ab3a	0xe5a43843	0x9013db3e	0x1c7202b0
+	0x059b7c45	0xa79ad1f8	0x578dcda8	0x286f7a7d
+	0x29b82899	0x17e9a470	0x292e9656	0x4ffecb5d
+	0xdf7d989c	0x33d2f0f6	0x1ad9a38f	0x7192ebcb
+	0x63c0924c	0x87adf98d	0x003433bf	0x1f9dbd42
+	0x38811388	0x032c6dbd	0x7216bfaa	0xb8405caa
+	0x358ef886	0x0d8de625	0xda26a3cd	0x02e02bed
+	0xbfee97ad	0x9bd94b51	0xa3e0d47d	0x07afc5ce
+	0xf1846ab8	0x9c56da77	0xdaf48909	0x980d0cf4
+	0x201ff73a	0xecd7d225	0x2f8b88f5	0x6afda416
+	0x1c230e24	0x6e71c111	0xd056e64e	0x8b02a960
+	0x7b3e5cee	0x9369c16f	0x8cc648d2	0x5b1044a3
+	0xec7ad383	0xafdc087e	0xb7331119	0xe2b73df2
+	0xe5aa2679	0xb68a0024	0xbf417687	0x39f8f49c
+	0x4dc6f396	0x394c364b	0x84b262e6	0xfd08738b
+	0xef799352	0x99f6ce19	0xf0deea77	0xff7b2b32
+	0x9f0047ec	0x93328447	0xa68daaeb	0xa15c49d9
+	0x9c2ee179	0xd880098c	0x591333e1	0xf95bbf1a
+	0x99b94163	0x6775a129	0x58312bae	0xb05a0204
+	0xb369ee9d	0xe33139c8	0x228ddb00	0xa90eb06e
+	0x9d740ac2	0x7fe877d0	0x49e80e67	0xae0a1b4c
+	0xe0762721	0xa8aa010c	0xe1b1c70e	0xc4cb1331
+	0x98e2a2b1	0x95eb5adb	0x27ce7e8d	0x0c4c9fb0
+	0xa5600d3e	0x0b1b01f7	0xf5d073ff	0x618c31f9
+	0x09ca0170	0x6f40bf4a	0x778c6e4c	0x82a5d345
+	0x89739b55	0x9a8055b3	0x882713f8	0x6127132b
+	0x7dcd4b1d	0x693bcd45	0xd37be4c7	0x5cfcc650
+	0x108ba25c	0xe514be8d	0x0e6acbe4	0x53164bbe
+	0x04f80fc7	0x3d62e170	0xdc0977c1	0xe4e696a2
+	0x2951e0ab	0xe7df7bb8	0xed0452f0	0xa052451e
+	0xef71dffa	0xe7e1a83b	0xf44f3edb	0xdc8909d6
+	0xd106ca58	0x65a50c30	0x629bbd64	0x8aa53b1c
+	0x281d476d	0x9d8ebab9	0x7618cdd0	0x8726df1d
+	0x873d200d	0x3f0dfd8a	0xac699c41	0x6c5fd299
+	0x1a4ec8da	0x02849d77	0xfb9a17b8	0x97353330
+	0xf58f4ca3	0x8cfd3379	0x560c085f	0x0b0f4412
+	0x93abd1f6	0xa4610fe6	0xb2093ea3	0x2132e754
+	0xa27f6dab	0x1dfdea78	0xa453f3fe	0x84952158
+	0x40cc656e	0x6bc83102	0xbc64b5d9	0xebd58830
+	0xae5d5041	0xcb2518e4	0xfbecfd7d	0xd35df3d3
+	0xb1f3c02f	0x672b45c8	0xf1ec9063	0x7e1af731
+	0x9591a4e5	0x8f6cba68	0x47961590	0x46ab9cdc
+	0xafcc329f	0x89527de5	0x848b9e15	0x12a76f30
+	0x8dd22cb2	0x111febb4	0x9f2b87bc	0x4d1124d0
+	0x82885b16	0x9800ccac	0x8ab228d2	0x4edb46a8
+	0xe3a7867d	0x6a0f0f31	0x0ba359e5	0x238c560d
+	0x6f2e9960	0x714940fe	0x2c8b115c	0xb367636a
+	0x5ef73955	0x1fbd0ed4	0xea769618	0x22879b8e
+	0x19c54520	0x1d60b769	0x8f9c9206	0xe12e6178
+	0x6f7d4e60	0x87a42234	0xbf426187	0x136d1b3b
+	0x096388ec	0x12cf7c8d	0x4f9dc462	0xc4132bc1
+	0xbb83ec7e	0x8a26142e	0xb2b10d85	0x0a22ac57
+	0x587d0f8c	0xfc6566a1	0xf9a313a3	0xdf5b8e38
+	0x3ba410d0	0xcaedcf98	0x623da0d4	0x48a77151
+	0x9fbc8986	0x75d69451	0xdd8db5ca	0x3d143e41
+	0x23c6ef92	0xd4e8c17f	0x50fcf1cd	0x65202d54
+	0x7f465e5a	0xfc9487e9	0x21302b5e	0x22cf616c
+	0x09b9278a	0x24807c5a	0x5347363a	0xa0d43079
+	0x243222c2	0xf31afc3c	0x299615c7	0xbc9862a7
+	0xd9fa9ffc	0xe0da4c33	0x4086d085	0xcd9fef47
+	0xaca1ebf8	0xe9054295	0x0202a632	0x2a566a47
+	0xde6072e0	0x12ab6f47	0x1e961f96	0x79b78cea
+	0x178d0054	0x3a6db40d	0x1c1fa4a7	0x04aeca16
+	0xacfc3b3d	0xa95d26ef	0x7fc56d9b	0x8cd04862
+	0xf05ca31a	0x2f1a8451	0x1fa55f63	0x038c689c
+	0xd275082d	0x6ce3bbb4	0xa5787d5c	0x284ad4fd
+	0xdb456159	0x72fc2b88	0x4e8846f8	0x3652ccd5
+	0xdb67b32f	0xea7afaf8	0x31981989	0x7479b85d
+	0x8cd4965a	0xab410e17	0x3b6000fe	0xefe70084
+	0x4d903c3f	0xad10aa48	0xdf7d8f3f	0x06eb3088
+	0xf80c6c8c	0x1f45157e	0xc81017fd	0xfa4b5d19
+	0x183d9f3d	0xa6552ca8	0x940914f7	0x0dece704
+	0x5183a544	0x2ca83fd1	0x0d39644e	0x689020e9
+	0x8fc6451b	0x6fd1271b	0xaa27e129	0x7c96848b
+	0x51efc70f	0x8fc41606	0xf5d42b17	0x80694280
+	0x1f774b0c	0xaad194cd	0xcdcb3bbd	0xa30226c9
+	0xe94699f7	0xe7e0ad1f	0x4e0e7887	0x4a8eef8a
+	0xd7b8d9b5	0xad81550e	0xd8a47d80	0x3b31cc2a
+	0x283b170a	0x954184bb	0xcb4d6ef4	0xc53a8ef4
+	0x1b9eba45	0x0df70c46	0x9ca62404	0x1960596c
+	0xe447c659	0xbbdf89a3	0x11d5399c	0xf70d6c7e
+	0x2f5f411b	0x55d83f23	0x49d3a5ee	0xa30d42ce
+	0x9d7b5dab	0x798ac7a0	0x54427d51	0xb93539d9
+	0xeab10ab0	0x9baeca42	0x5db291e4	0x6a572088
+	0x1996c3b5	0xc49e4528	0xe5d91c6d	0xace9b18a
+	0xdc00ef96	0xabb2be9e	0x9c8c3dce	0x5575fef9
+	0x55ee1588	0x54fd1f04	0xb51f8054	0xa79f2970
+	0x2b944de3	0x258bb2a9	0x6d795400	0xd8e37086
+	0xe28e13f8	0xac866668	0xee61e623	0x74822294
+	0xb8e40564	0xed674c7a	0x41649345	0x18f67675
+	0xccf6dae5	0x2f771905	0x41617a0d	0x89892452
+	0xebe9c54e	0x15c0047a	0x1360fe11	0x97e9968e
+	0x969ba1ec	0xa8d87a94	0x89c42871	0xa3b7600b
+	0x1eb2da3a	0x51ad206b	0x0ffa1e92	0x6b54cc4b
+	0x551038b9	0x56d3134a	0xc604c359	0x921df194
+	0xdd0e8901	0x0aa069b2	0x63cdd252	0x7f0eb051
+	0x6eb669a5	0x9e4744aa	0xbbdb786a	0xade2eff8
+	0x01735f2f	0x59b21311	0x2a9b3c19	0xfef63adc
+	0x7f935ed5	0x4107ae2c	0x7e87a339	0x169cff65
+	0x9c405742	0x714007c1	0xb7c3a785	0xc4c48389
+	0x31f92159	0x0dc32968	0x52ffa3ea	0x97148ffe
+	0x24e05234	0xaa26f639	0xfcc1d939	0x88657f96
+	0x8f50c4f9	0xf1889d95	0x0ced35a1	0x436cecef
+	0xeca9a15f	0xf48e7adf	0x457a7fcc	0x7a6c1239
+	0x5034af95	0xa718db0d	0x148c7f75	0xe71321af
+	0x6ca91aec	0xd8e3f28e	0xf1792028	0x6cd6de0b
+	0x08a5b4f8	0x6c423f4a	0xabc9fd13	0xd9b32cb5
+	0xa11cf2e9	0x1cf2a8d1	0x5399808b	0x41c4342f
+	0xfc8cc322	0x886c8a1f	0xda930d22	0xcb065a7d
+	0xac2af243	0xde40d5c4	0xbfc31749	0x1648efb2
+	0xd7a7c284	0x66354919	0x0ae2ebfc	0xe9467716
+	0x31bc8fa5	0xee8b06a8	0xd225ddf4	0x1abb30a5
+	0xbab806d6	0x4089c5c5	0xda27fce1	0x049b6de3
+	0xc750ba15	0x8a46ce66	0x036144aa	0xfe034871
+	0x1abebc7b	0x493f7de8	0xb2159be7	0x6fa331cb
+	0xb96cabc6	0x38c0604e	0xfc029108	0x5e60b9d0
+	0x4659e613	0x03acd4cc	0x199fdfec	0x378d55eb
+	0x769412a0	0x15e6347b	0x92c90797	0xc9074949
+	0xf8122bd8	0xf412bc92	0xb78b97da	0x0b57c329
+	0xe53305ea	0x8df0ab76	0x8306e3dd	0xd0d7318f
+	0x36adcee8	0x874d40a3	0x01013be2	0x22ea83d6
+	0x103a41eb	0xb0597649	0x3da90abb	0xe329568a
+	0x197f2854	0x0bcf6548	0x9a8cadf8	0xdbcad384
+	0xdbd146a4	0x47614216	0x20ae929d	0x700c45dc
+	0x2957fadb	0x2ccecc42	0x59dade3a	0xbd4ba21d
+	0xa54cbdfe	0x2168aeac	0xf3fc977e	0xb8a43acb
+	0xb673e386	0x8374b99e	0x1c9b8514	0xb27755b5
+	0x76a14bad	0x7f9e80f7	0x7827aad7	0xa38aace7
+	0x09bfb029	0xd8744c16	0x60e27d36	0xf0bb9c68
+	0x6c6ea1ba	0x1920dde0	0xfd949296	0xbdd246ba
+	0x71b9255b	0x443eb00a	0x484b5641	0x6cf54003
+	0x719a7b75	0x5fd6ceee	0x94379976	0x610d0ec5
+	0x2e601eb8	0xd5b31116	0x351833bd	0x71e20a77
+	0x1bdf31dd	0xf2b71f50	0x643e7b0f	0x14966e60
+	0x2ea94458	0x18fd7a19	0xc2042ba8	0xa6b2a8a7
+	0x5591ab4d	0xd62a7fb3	0x478b9fc9	0xfb0faa9c
+	0x840848c4	0x51d8e887	0x0982b486	0xf5a7a82d
+	0x651cd99f	0xc429c680	0xfae0f0a4	0x341f4588
+	0x358b09c5	0xeab81b53	0x4107619a	0xfd8686a0
+	0x23438c74	0x03e44685	0x7acd2f1e	0x0324c896
+	0x0c4fb764	0xa859e8ce	0xc041d07b	0x1ddea0d0
+	0x0c7d3a05	0x1a9552b9	0x791ac20b	0x135c3573
+	0x3315a1b0	0x20f6b0ba	0x9301b576	0x5f9396fc
+	0xd2b55a44	0x1ccf9ebd	0x8cf0350d	0xa58f9151
+	0x251be7f3	0xce2201a3	0xdf354713	0xe1c1bb1b
+	0x6821a792	0x8b1a47e4	0x681b765a	0x6b857d78
+	0x4b453e66	0xecbeea8f	0x7d4aa02f	0x138ad3ce
+	0xa2e27fdb	0x9f47ceb9	0xdb849664	0xd89748fd
+	0x3245bf9d	0x16bdbedc	0x386f037d	0x9cc949f5
+	0xbeda4924	0x357c0a52	0x9f6e807c	0x547bd479
+	0x51495240	0xd1883e61	0x04869ce6	0x47f09ac8
+	0x2e5cf223	0xc34ef901	0x15b69b18	0x052b45c3
+	0xa045628f	0x7fdf706f	0xaa943b26	0x52a91e2a
+	0xed73757f	0x6ddb9171	0xae2e6289	0xed44ad05
+	0xd9ba87ac	0x5225b7f3	0xd227abe1	0xf95c862c
+	0xf22fb4e4	0x34376d96	0x121f979b	0xb65b7535
+	0x3bca35ab	0x579ef994	0x72659829	0xc0094673
+	0xdea78eef	0x51248fb0	0x4a883536	0x9c69810c
+	0x6f9e2a2d	0x33a54fa3	0xbf04ea97	0x081092e0
+	0xe783b995	0x47f781c4	0xfe77defd	0xd0b42d36
+	0xbe387b86	0xe3072ad9	0xa3b6908f	0xe2141964
+	0x77d70045	0xa86ad40a	0xc3c457c5	0x3e7b7126
+	0xbef763ea	0x0d6fc62d	0x5915bf32	0x2aff83b7
+	0x21cb6fed	0x52903bf0	0xe020e340	0x0b3f355c
+	0xee7c6bc1	0x060fb2a8	0xc0323dfd	0xe1dcfb29
+	0x668647ce	0x3e46e584	0xae4baffa	0x6a77a8f6
+	0x20d34fcb	0xd9ec900e	0x778a2afc	0x1a59fb8f
+	0x43e94780	0xd4e333ad	0x97f82259	0x141571cd
+	0x73aa7c5c	0x18fcf18a	0xd48a4fb8	0xc109eac0
+	0xe8de4f47	0xfd509a7b	0x90707861	0xfb8c77cd
+	0x3b7122fc	0x4ca78b8c	0xa35f59d0	0x45ae991c
+	0x8e70498c	0xb9202519	0x65c96b4b	0x78a4fc95
+	0xdcf1b9a5	0x1031417a	0x9ff8793e	0xa2030f94
+	0x8c733cfc	0x1c91d955	0xf6a68ffb	0xedd6944b
+	0x2aa354d3	0x6ac7af45	0xf1f3cd2a	0x4c62c093
+	0x03480c9b	0x0f246eb1	0x2a4b1c9f	0x839b624c
+	0x29a74da9	0x34ae761d	0xaffd7053	0x136c170c
+	0x62d45905	0x6707d6b3	0x7c828933	0xc8df0f9a
+	0x16917824	0xa446ec27	0xc0ebdeb3	0x78183042
+	0xf55d10b0	0x7ac4cae7	0x1e03a86d	0x5b0469f6
+	0xaaa1c0d0	0xe1ec5485	0xbd92cc52	0xe57b7def
+	0x371cdae6	0x5a344a02	0x4fe6202d	0x550f73f7
+	0x0379ceb7	0xd8136303	0xdc4359cb	0xe38ee67a
+	0x2aa895da	0xe6cd6cdc	0xa50300f1	0xdaecc9bf
+	0xde559d55	0xec988d8d	0x2daf3e0b	0xcae251fb
+	0xd26d26e9	0x130ce5fe	0x86d2361c	0x3108822b
+	0x842528a2	0x23b91b1b	0x48fb92e7	0x013305da
+	0xb9382453	0x8e338247	0x1cee69df	0x28dda889
+	0x3098b87d	0x2fb8a4f2	0x12cbca62	0x0050c443
+	0xa9640f44	0x56926695	0x84f1af0f	0xe7612db4
+	0x7ca148a4	0xde5a4740	0x04fc09c8	0x1168eacd
+	0x3afcb851	0x481d093a	0xdab01eb3	0xad7d6f56
+	0x0311d8e9	0x4094dbf9	0x264b6da5	0x3a5fdc11
+	0xcd2ee17f	0x50cfbfc2	0xfdc9419f	0xa61d64be
+	0xd9786507	0x4202f8e9	0x13f58fd8	0xae675835
+	0xaf0c72ea	0xadd2275e	0xa0afc1b2	0xaef42673
+	0x059895be	0x4504a91c	0x0d1abd4c	0x7986dcc6
+	0xc13fe6f8	0x4780bfd7	0x44ae446b	0xb70c300a
+	0xba32a5dc	0x807aa794	0x45e8373b	0x955cb2f6
+	0x4ff6ce64	0xa75d9feb	0xf99b0f94	0x1f6f42cf
+	0x7f3e7082	0xf05cfbc2	0x2981d66a	0x0031868d
+	0x93ad9527	0x20e0a72c	0x7af059e2	0xb4db736f
+	0xc1ee8a47	0xee31b1f2	0x075c758b	0xb796cef8
+	0xe758683a	0xa417d0b8	0xec701109	0xd5db6f14
+	0xee6759ba	0x965fd314	0xa991abc2	0xe431e1a0
+	0x8c49bd5d	0x393827a6	0xa432862f	0xc41e1a96
+	0xbe0bc3b9	0x3d8cf302	0x42bc70da	0x8748df76
+	0x110951c0	0xb1685274	0x06f426f6	0x65ec87c5
+	0xaf689ca5	0x602d9679	0x19363407	0xb0fd04c7
+	0xa38ad24a	0xfad9b36b	0xa13c711c	0x4e386365
+	0xa4f8a466	0x55276e7b	0x7e8f736d	0x6fb49d16
+	0x319c5c11	0xaf40ba4c	0xe7f84dd4	0xef4dd864
+	0x5ae207ae	0x09a3ef70	0x23a90e6b	0x9c9697f8
+	0x7155d79b	0x131fc9fb	0xb46cb500	0xeae3eb61
+	0x51e29783	0x3922bd46	0xdb8afa10	0x33b0ebfc
+	0x3e43da19	0x2fc38e51	0x97f3bf1c	0x8c3ce68b
+	0x7c0550be	0x6a53e9f6	0xbf6cf7c6	0xf338ad58
+	0xce0f1a73	0x4d372ec0	0x29281dbd	0xf6b0bd7c
+	0x85b26827	0xa454dfb2	0x52b28dab	0xdf3af48a
+	0x5f533d2f	0x2a609d20	0xeaf73bed	0x5e350bb2
+	0x95d2bd12	0x908c3f5d	0x71511f88	0xd2060f72
+	0xa818d161	0x84f5ebee	0x59ed524e	0x4e45cb9d
+	0x6ce00f42	0x33e0c310	0x75e34119	0x140e3cc3
+	0xacbeda6e	0x4c450e0c	0x9ae2ef44	0x7c98afc7
+	0xa2093bf5	0xeab6cf15	0xcba6057e	0xf04c3ce8
+	0xcb5cf30e	0x044ff594	0xc2cdb5f4	0xc8c60b17
+	0x701c8bbd	0xbf893762	0x2ac72a28	0xe777c968
+	0xcd25da52	0x747eeb7b	0x76ee7f3f	0xffa7dcdb
+	0x69e68c12	0xeec17e1d	0x93710ea9	0x5370892c
+	0x24463499	0xfa5ec00b	0x3b1f55cb	0xa6fec9d7
+	0x4fa50806	0x7f8066fb	0xf914e3dc	0x1f814780
+	0xedbff426	0xfec2a635	0x5355f69a	0xf4f47000
+	0x0be99ed6	0x6ca79305	0xb5744697	0xf50a8edf
+	0x91fc0932	0xb3ff4411	0x4d72ecd7	0x335f8ba6
+	0x1b393143	0xf0cdce19	0x95543420	0x88d44565
+	0xf47e1e74	0xd7ceb70c	0x95508187	0xfc65e9f3
+	0x92cdfb27	0xa12af6a8	0xb8754dba	0x436f5819
+	0x0e3a952e	0x91178a2c	0xa25c2395	0x15379544
+	0xaeffd675	0xb74779b5	0xd9229b70	0x7c72bd05
+	0x0349e5c9	0x3f2dd364	0x96e25f24	0x5c0fca2c
+	0xe56f81ea	0xee339b9b	0xb6f9888c	0x54ea5d03
+	0xfd136dc5	0x78ebd8a6	0x7d65dc8f	0x1f79781a
+	0x7f058e70	0x68caae5b	0x9e17a15c	0x0b0d7b34
+	0xec758cfd	0x2d2d39ee	0x72b46a64	0x98569c65
+	0xcff678a2	0x1e5eae00	0x197cff21	0xa17e1c00
+	0xf0da9430	0xa007a848	0x0be7cd80	0xc55a8077
+	0xbe7ed983	0x5c6626cb	0x103c6639	0xc0348431
+	0x48a06b34	0xd8c43a93	0x94f5dc15	0xd8282ff4
+	0x798fecbb	0x969eb56f	0x97b834f3	0x9361d4b4
+	0x451962dc	0x9411aa6e	0xa9eb502b	0x2fa0696a
+	0xcfce109a	0xbdbb187f	0x0cef3b86	0x7d420c93
+	0x6a38b476	0xdc49d8b8	0x34652cef	0x1d38f2c7
+	0x9042655d	0xfa414d42	0x79553a30	0xa1197a11
+	0x47f0892a	0x7c7cc3cd	0x0d16e724	0x205ee0e0
+	0xe8d2af7a	0x1b84e9e5	0x762b8343	0xe6f0d4f1
+	0x13c47e29	0xd625bdc8	0x16136974	0x7f4e63ad
+	0x5fb6589b	0x53699412	0x136774ad	0x4469f334
+	0xe0e90aac	0x88a24073	0x940ce7e0	0xcef6082a
+	0xaf7251bf	0x569dfc49	0x23058c3f	0xa2c897ce
+	0x6a31faae	0x352ad804	0x88cc7d68	0x68570267
+	0x07314cae	0x8cc2a6bc	0x3dabbd9f	0xdee27981
+	0x32c1ffa8	0x826ab175	0x769de94a	0x3b11317f
+	0x362a6306	0x2422aca0	0xfc53764d	0x2ca4c418
+	0x5fc2d68a	0xa74a5fc5	0x949b041a	0x0f0f69d6
+	0xd075fac4	0x965a3001	0xb6dd4eb5	0x9b5c6979
+	0xfd84a8bf	0x4ca80a7d	0x42fb907f	0x5770680c
+	0x3684714f	0xba50c3b2	0x0fed8f5b	0x42f42f2d
+	0x7e98ba74	0xcf4ad155	0x33972750	0xabbbbbe0
+	0xcab7ba1e	0xc3e54c90	0x2cf8e77c	0x7eb3c185
+	0xafbe0fc0	0x6ff94321	0x9699d3a8	0xa8f51d2e
+	0xaeba0be5	0xc519f879	0x73b89b8d	0x2c98994c
+	0x5c6688ed	0x0c4edf1e	0xd27a0c40	0xe58b6112
+	0x8b01ccb4	0x7da8a608	0x03b02b0a	0xc35c0051
+	0x33f60875	0xa215809b	0x34e2e84e	0xb1249172
+	0x9c9068f0	0xa4067a92	0xd6260de5	0x2e30b0b8
+	0x895a3ef4	0x1d0df2a1	0xf5fc1a24	0x51fea72e
+	0xa6b203f2	0x13b8ccbe	0xc411482e	0x40529a43
+	0x8ec685c6	0x31334940	0x3758077e	0xc551b5d5
+	0xeed75a95	0x1bbcd839	0x64b09366	0x426afc28
+	0x70826210	0x2cfdb0b7	0x2e1d1442	0x39db3d97
+	0x3826c5a0	0x500157d0	0xd6dacf6f	0x9b9dbe3e
+	0xab4c2657	0x98c19ffa	0xd12dcb10	0x73d3b9ba
+	0x0c15214c	0x737e36b0	0xb903b782	0xb7ac4e8c
+	0x0d0a3b55	0xcf534bc7	0x3268a6aa	0xdaf914d3
+	0x33f832b1	0x280109cf	0x270be538	0xe6bbe826
+	0x11c372ce	0x74a668fe	0x0065b4c9	0xffc007a3
+	0xbcea5c8c	0xf95f792a	0x88b93d2a	0xa76a2eaf
+	0xb6dbc1be	0x8aea9c60	0xaa7f4bcb	0xb48d40c9
+	0x5aeba8d5	0x45797ea3	0x736e4060	0x40dc0826
+	0xd497fb52	0xcdfb751e	0xebd6fdf6	0x3471bbd0
+	0x6d5bb733	0x02b6cbb1	0xd086c9c4	0x0485863e
+	0x878391a4	0x57e62c09	0x37385c15	0x96e76ac8
+	0x093dbd37	0x1ffe70f9	0xe256fc68	0x3a509a68
+	0x019d3e81	0x038168f1	0xe0b2b6b0	0xe6eee6e5
+	0x2080b0d1	0xe25aaf0c	0xada6ac13	0xa3755f0e
+	0x99f9efd7	0xb0cbe867	0x1dd5fe38	0x1bb8bd56
+	0xb54dd0ee	0x344d878d	0xf937042f	0x9ac5c721
+	0x1a60dc54	0x643b9a83	0xe66ce361	0x0d10d718
+	0x31aa90fd	0xf71e52c2	0xdf7eda2e	0xdc068ad5
+	0x095f114b	0xdb1a9b68	0x64ecb9d6	0x6f13609a
+	0x9242152a	0x1a7059cd	0xaa4c92d3	0xbf9a70e0
+	0x93936ec0	0xc8456867	0x05118674	0x0d6289af
+	0xacc6aedb	0x3cd3aea0	0xb11acc65	0x93121235
+	0xd080cb09	0x1a3e9be4	0x3772ad61	0x1277ce89
+	0x503309b8	0x7cc1ada2	0x87e93e41	0x565bfd16
+	0x8d64db91	0x8776da19	0x8068ea78	0x8c4ed3dc
+	0xb9904266	0xafc63a7b	0x120c746b	0xaa5503ae
+	0xf6c8c09a	0x7390cac4	0x736c1bdd	0x03ed0655
+	0xa692aa13	0xa95b2587	0xeeb8140f	0x97c907b5
+	0x6665d1e1	0x335794bc	0xc59a6232	0x0a6a7bfd
+	0x0820e282	0xde4982d4	0x43ce576f	0xca9f43cd
+	0x439467d8	0x513c59aa	0x40a47741	0x6c92f234
+	0x712a918f	0x5222ad75	0x90097829	0xf82f3dc7
+	0x5c95108a	0x9432a016	0x1c13d7fb	0x6a64358e
+	0x88c43a59	0x726c4bab	0xbba1d26d	0x3a6fbec6
+	0x603c6edb	0x5002f608	0x65b6e6f4	0x9911d725
+	0x1e9d73f1	0xad3facb6	0x3074a331	0xff08050d
+	0x84efd825	0x0ba49a61	0xef94c605	0x95e6fa34
+	0x42102abe	0xbb7a7327	0x53fb9fe5	0xbf3e7e13
+	0x35ed38b9	0x2af0b51b	0x59d53a64	0x77963248
+	0xe3788d31	0xe193f2b3	0xeee24485	0x8688c4ee
+	0x9c61fe6c	0x5745fc77	0x8fb588c0	0x9b8b73a9
+	0xddf4a85c	0x37f97b96	0x37ef756d	0x75b88955
+	0x4ddcf2ee	0x0ddbaaa6	0x53188169	0x9c17c6e1
+	0x6d6f6640	0x97c72398	0xf2a555d2	0xbeba7505
+	0x8a330e05	0xfd73bf33	0xa84d8356	0x928cd08f
+	0x302f868b	0x4dc8aaa4	0x0eae2165	0x0151f140
+	0x1b337b5b	0x168f2728	0x377c45df	0xd5a333cd
+	0xf9cd451c	0x386cd928	0x5e45d283	0x7e224f31
+	0xaebe5122	0x75c7e49b	0xe3949ce8	0x397bcadf
+	0x4c0e0f77	0xba92d6b0	0x9288f86a	0xe9a47d7b
+	0x344fc436	0x00a9a682	0xd15e8917	0x7dcae697
+	0xa2955662	0x9465b695	0xec9f769a	0x740159d4
+	0x738b71ab	0xfb57cfe9	0xfa582c08	0x7d5521d3
+	0xe2644c13	0x4311f413	0x3c2751d0	0xc9faa58f
+	0x36b94cf3	0xcf8cff31	0x5dbf8927	0x82f8c846
+	0x8bd2ceb8	0x2a7368e9	0x9eff066f	0xd93f3e0c
+	0x2358ff4c	0xa41ce1e6	0x41ea009a	0x04c7a7cb
+	0xa2897e54	0xdb46c580	0xeca4c4df	0x0920694c
+	0xde5d8ad0	0x23968b10	0xfda8d5ff	0x6bfaebb0
+	0x596eb388	0x797dd1b5	0x18a1e5f7	0x8b58637d
+	0xd618cddc	0xbfe51118	0x46ba28b1	0x94854536
+	0x0fa51257	0x381f2d54	0x20d68fc0	0x540b8ea8
+	0x5e81f3f8	0x55409d4c	0x03768f09	0xdf9ccc98
+	0x012b6611	0x9a8ad678	0x340313b0	0x08fb187e
+	0x3c208640	0xca62a71e	0x75e62236	0x303002e0
+	0x71d8ce8a	0x15cd2434	0x519570a8	0x2ad715ff
+	0x61f33c8b	0xdd1ec924	0xb1a4c788	0xf2c36eb4
+	0x5aa4b007	0x75e7c1e5	0x29bc37f9	0xbc7bf320
+	0xfce34584	0xbebf90d4	0x8a8be8a2	0x3ac72a9c
+	0x0de840bd	0xda21156f	0x06a72c18	0x0c31c6a8
+	0x8dbfb88b	0x2c030320	0x7b91cf76	0x4b698166
+	0x11465c72	0x2dc1af9c	0xec43656d	0x07313b0f
+	0x2347b8c1	0x3a66229e	0x3e19108b	0xe734c641
+	0xc8ab5c8a	0x295e857e	0x80ccac9c	0x52fc246d
+	0xe0d5729d	0xe788795d	0x862db49b	0x81de8327
+	0x57a24391	0x46873200	0x1d6d9e62	0xb61cbde2
+	0x40c67928	0x5983967b	0x249cf427	0xd944ba02
+	0xf915cb96	0x7f07bdf5	0x01d35dc8	0xaed094e3
+	0xfb177ba3	0x81f39bdc	0xab553569	0x09e791f2
+	0x866c4561	0xe41ed6f8	0x880ded55	0x9a6f5b07
+	0x5457168b	0x13b672a3	0xabba6ff2	0xbb92c573
+	0xf46b5af4	0xb8690988	0x8b767492	0x53e2f7c0
+	0xa6b8cd45	0xccc0f21b	0x2205c607	0x97f74f86
+	0x4a671fe4	0x2078716f	0x2530825b	0x3b0db3a3
+	0x3c86b75d	0x780e6f20	0xdf8af7d6	0x547710e3
+	0x397470a9	0xb3f04101	0x206511ae	0x30ccf385
+	0x1792e9bf	0x80ad156b	0x7325e8c7	0x88ba99a8
+	0x6d0992ce	0x07e834c7	0x334e415f	0x2c246850
+	0x8502dfaf	0xb1ef5b19	0x75ef61a9	0x98e3b45b
+	0xcb9f0a6f	0x8c5f2ae0	0x16e43384	0x7ed0eec1
+	0x940e8b42	0x03fcde5b	0xcadb2d4f	0x0a3d8362
+	0x93038e69	0xef8c8384	0x065fcb40	0xdd57dc0e
+	0xf0362942	0xb39c96ab	0x979ec3f8	0x0efb2396
+	0x67a7c975	0xf8f272c9	0x52461862	0xea391db2
+	0x11f15fb5	0x2435ce54	0x9c51b8f5	0x8c7b9119
+	0x4b48b4fd	0x9864e85d	0x9840cd3d	0xa98f4da4
+	0x9a7f03c5	0x89e50015	0x6c6d54b2	0x9e647aa2
+	0xb3835823	0xea9bafb0	0xa6839d36	0xecf71292
+	0x170f2b96	0x44b0ac85	0xaf475a0e	0xa892f2df
+	0x7e92ff6e	0x7a55a76c	0x97a6edf8	0x1a8b561a
+	0xba061934	0x2d4ba604	0x85ece0fe	0x0ab3a735
+	0x26935212	0xe74ea97a	0x33ed586f	0xca8989f3
+	0x4802c043	0xef153bc8	0x32c511aa	0x994c3044
+	0xf3608e41	0x8b2ba3c1	0x27c40d2d	0x56ae54af
+	0xb5df3e4f	0x7cf1679d	0xf76a120d	0x28af2bf0
+	0xf87650fb	0x4ef69312	0x2a28acb1	0xe78d71d5
+	0x8cb89388	0x7f25bce8	0x420545da	0xe654dc1f
+	0xe6fd962f	0xf4f06310	0x9b5ccd44	0x60e3624f
+	0x9f38c5d8	0xe5fcf792	0x839bee9c	0xb405347a
+	0xc8cc045e	0x61506b9a	0x3a3682e4	0x22ca3ee4
+	0x5aff86c7	0xb9091ac9	0x2f8c8afb	0xafb29af9
+	0x1d4a3f19	0x9de74245	0x1a0ea238	0xc8bdc6cd
+	0xf1107b01	0x1dc7552a	0xb46a8c4f	0xe716b42b
+	0xfc060840	0x15fbc29d	0xc532c4e6	0xe96c8306
+	0x9e69da96	0x7f68fcc7	0x67d18b52	0x77a87432
+	0x280a6ee1	0x9a617bd9	0xd8d601b9	0xadc7f7f1
+	0xe3349a28	0x8efa2d8a	0x37ca44b0	0x6499f67f
+	0x5fc7b339	0x690852bd	0x27bd71fd	0x07159d82
+	0x9c841ba9	0x40741162	0xd7df8ef1	0x3edecc5e
+	0x12086a65	0xe8e6ee6a	0x1c177c39	0x1bee453c
+	0x5cc0b73b	0xec84a212	0x174a641b	0x7fa732e8
+	0xdafe94cf	0xa8eb95d6	0xb658346d	0xceee084f
+	0x3ed35394	0xb339f90c	0xb9bc44b3	0x1dd76c34
+	0xf9a54771	0x1482cbec	0x3816720a	0x3a1ebcc2
+	0x15cd4a11	0x94bc6c92	0xcb4cbf26	0xa141f0a9
+	0x11d8331a	0x82a73ed8	0x129d4088	0x3718c117
+	0x9fb3a041	0x51686b91	0x6f735d1b	0xd9eaabc9
+	0x623e6caa	0xbba10978	0x4811fea9	0x9e8a6779
+	0x007ea597	0x02a71344	0x0bc9b390	0x7bca4fb3
+	0xecc97d95	0x1c82c55a	0x746391ab	0xb0fab9a5
+	0x54f66c88	0x21797043	0xcca5c581	0x4fdccf5a
+	0xaabaefdf	0xd606be82	0xcc2b2d33	0x7fd7cb14
+	0x1e3629ea	0xd8e76e94	0xa895dfbe	0x0c06919a
+	0x4ea7aa08	0x3a178b90	0x4a56dfa3	0xb98a1f87
+	0xaf5a9fdc	0x7591a3c7	0xd5b58c30	0xd4028625
+	0x55d42179	0xccf397f9	0x824b38df	0x97292483
+	0x09119e73	0x945cc1fe	0xf4b77171	0x753154e8
+	0xcf0740db	0x3282b3a7	0xcc266194	0x7cdf91b3
+	0xd123931c	0xcfbb7728	0xfe410560	0xc4cce81d
+	0x3b843933	0x75734bca	0x3ea34af3	0xb9515793
+	0xeb66b451	0x3a6a1135	0x633d086a	0x31e627e8
+	0x3d12a160	0x9909d28f	0x6b98e9fa	0xf5e81dba
+	0x8d233c7c	0xbfde17d4	0x5a442267	0x228a56d4
+	0xfcf27d3a	0x3bef2fdd	0xd0c9c057	0x84c2dd26
+	0xcb54e412	0x01f6d774	0x78d352bb	0x3403cb49
+	0xe16e92b7	0x25fdeaa6	0xa90610a3	0xcb43c17e
+	0x880f57cb	0x50908846	0x8255be3d	0xc01dbf9a
+	0x4bb1a52c	0xafc5a8c0	0xa543d14c	0xd18efbe7
+	0x5b18ff14	0x910913a7	0xb78f2a4f	0x2e9aff82
+	0xf3604dc3	0x77b5dc87	0xcbd16de3	0x9e9aa767
+	0x50c14c8d	0xa53a91f6	0xf5369c5f	0x693421e9
+	0xe7d41706	0xde2ae3c0	0x3383fe8a	0xfff54f57
+	0xb22e6bbf	0x330cc71d	0x0566d22d	0x63726b5b
+	0x4af41cf9	0x1da8b9c3	0xd8c5fb71	0xcb4860f9
+	0xbd301732	0xd0300319	0x51458c3d	0x2915617f
+	0xa76713c0	0xaab3eb2a	0x35cdab1c	0xd1958253
+	0xc42c14ed	0x9794c64c	0x3f4860d3	0x5be281bb
+	0x7153eb66	0x0fbe8b50	0x3296f7f6	0x14ca3bc9
+	0x5d3e1995	0x3f54a9a0	0x3a350e66	0xe0eaec63
+	0xf6b40eda	0xb432a3e9	0x8eaf6fd3	0xa5e02a4a
+	0x82181320	0x7b18018c	0xeba1bb24	0x192f05f9
+	0x95aa2c21	0x2635f2f9	0x13a81ac3	0x57feb353
+	0xfffbdfff	0x20c3f27c	0xfe1ccfb8	0x75e9bb2d
+	0x2470564b	0x59e7905c	0x5ad8e400	0xf575caf4
+	0x3c99a548	0x93ff04a9	0x494be39a	0x966d5c2c
+	0xa0439df2	0xb42ecb84	0x5ca0e55a	0x72bb3b6d
+	0x903f12cd	0x55b67ebf	0xaf4188f0	0xdb3828de
+	0x0e8603f1	0x35a3b856	0x63402b22	0x21ab7779
+	0x4efeaba2	0x919829f2	0x4190e5ed	0xbd99779b
+	0xbc96cd73	0x6d5eda45	0x872b6659	0x7c30cb30
+	0x1ad0c877	0xa88ef386	0x03bf7f3e	0xa6c18655
+	0xe39e2764	0xa40da119	0x01f5eb9f	0x4b6790fd
+	0xa50414de	0x4d7d8fcf	0x28e6bdfb	0x345dae6a
+	0xe706b08e	0x7958d05d	0xf6ea912a	0xeebf2736
+	0xc5ddbbc1	0xdf079dad	0x09ea5e1f	0xddea3b87
+	0x367782fd	0x7e657215	0xbce3c13a	0xd998f10e
+	0x22a6ed1b	0xbd57ee41	0x8bd6a4ff	0xbe81acf7
+	0x186aa189	0xe986fbb4	0xb4b798e0	0xa313653b
+	0xec674a01	0x656d8992	0x92104018	0x01eba2fd
+	0x99314063	0x0bc67b96	0x98891022	0x32a936e5
+	0xee8331f5	0xff55bf99	0x2e305833	0x6fea2320
+	0x261d4ad4	0xb357a04e	0x6086539b	0x12b59123
+	0x170e9c0b	0x2c509ff5	0x4684fa75	0x55535535
+	0xc47f3dd0	0xf74a35a7	0x468e5623	0xdee52521
+	0x55f86d53	0xc6c66d4a	0x0f127241	0xa89d946c
+	0x2054df6a	0x7555153a	0x91cf4407	0x71d0e3de
+	0x6dc16613	0x32a44245	0x8607574d	0x6eb010de
+	0x02cb87ad	0x16ca5da4	0x79026a0b	0xb3c22ea4
+	0x2aad720f	0xc59c6272	0x8b0ffcbc	0x90138b11
+	0x94960289	0x018dc9f4	0x28795fe7	0xa9d97031
+	0xdbabb687	0xa26c631a	0x22b60590	0x816e4981
+	0xe881272b	0xc2d2a9f3	0x251dfcc7	0xef7d7cd4
+	0xe92e8a70	0x5a41e9db	0xe4c0d1c5	0x559d1455
+	0xe661afb6	0x87819510	0x880a078d	0xc82fdc06
+	0xe27e27f1	0x9912132e	0xbee4b9de	0x04477b74
+	0xb25684d8	0xeec01992	0xd3e81251	0xfa528234
+	0x435b2dd7	0xe45673cb	0x9b4c9767	0xde5de093
+	0xa2e591dd	0xe4e27f7a	0xe94c0e70	0x5c392194
+	0xff2d4212	0x810af41d	0xf8d322c9	0x14f17d5a
+	0xac7aed44	0xb5fcd81d	0x65eb270f	0x207876ca
+	0x8a89846e	0xe6418235	0xb5a935c4	0xf188f339
+	0x9acf3f50	0x5083deba	0xea6c6c76	0xce7e9d9e
+	0x22461871	0x87f0108f	0x12a97a3b	0x7c8fdec8
+	0x8f326b24	0x617cb20e	0x21a34a79	0xce7c70ca
+	0x1b33c68d	0x92f06767	0xc51c5649	0xf5ae12cb
+	0x75c2ff79	0xe485811f	0x191c9dba	0xc87e8cbf
+	0xafd4b4d2	0x6fc0af0c	0xbb76c0ba	0x6fb0336e
+	0x46f59bb9	0x401ded33	0x88a92571	0x328d44c2
+	0xb494f4dd	0xf5a68521	0xffbacaa9	0x30ff5d32
+	0xa3dcc986	0xc10670cc	0x4d9d69d4	0x365865d7
+	0x9ae0ef1f	0x97e8a835	0x83acb6d4	0xeb6fe7b0
+	0x7337d45a	0x384731ec	0x6a12e5f5	0x5f5f0f92
+	0xb0ab43f3	0x1ecff295	0xc2c72221	0x02d90770
+	0x59869deb	0xe01eb4ed	0x38691b29	0x39b21ecf
+	0x812a2a39	0x1d211c6f	0x027ebf3f	0x9b94bc94
+	0x0be5efbb	0xd4c43105	0x0a3845c4	0xa5662a41
+	0x5110cbef	0x127d92bc	0x99924648	0x222c4bdc
+	0x4db3da4f	0x57c771fa	0x3820187a	0x0fb448c9
+	0x3c17cb96	0x76d5c447	0xdd6cf323	0x180615dc
+	0x6d133cf6	0xbed0d7f3	0xb542fdb6	0x837ff1c6
+	0x5686629f	0x1412eea2	0x45b93f3f	0xd6c324a4
+	0x9b3021fb	0xf0976d4c	0xfc02bea8	0xeab7f534
+	0x0a5f2aff	0xeabbd304	0xfc2b6ef2	0x8e1444fd
+	0x6a683e99	0xef114948	0x9c61f02f	0x702da123
+	0xa10a252a	0xb435a995	0xc828d43b	0xeb2e16a1
+	0xed91a2f1	0xb1783a96	0xae6eb190	0xf5b3ece5
+	0x15caec18	0x41d2124b	0xfe97094d	0xb63028bc
+	0x3849f412	0x60c25505	0xbee19f15	0xad10e883
+	0xcb4529e8	0x5ff6312f	0xc081c3a8	0x51d7c2b7
+	0xdf4b795d	0xe14ace52	0x639c5108	0xce31269d
+	0xed005d20	0x0f251ce6	0x105051ff	0x7ace3072
+	0x2e490489	0xd0677ac2	0x06c42d29	0x09c7eab7
+	0x03a75852	0xda74f991	0xe8bbd5d8	0x49a04f14
+	0xc034774c	0xcefa0c35	0xada23997	0x247c022a
+	0xb87a5cfd	0xd47e56ca	0xc6a48f18	0x745f325b
+	0x97fd37de	0x16ee3f7a	0x94d119a0	0xc943976d
+	0x3969772b	0x3b4eef57	0x13b0c418	0x9a03fed8
+	0x2311572b	0xaade9680	0xce4cd64c	0x63180789
+	0x00abbb28	0xd10c8e72	0x55967c83	0x6eb8b4a4
+	0x8e178a4c	0x245db146	0x37ddc447	0x265c0aad
+	0xfd20a1c7	0x3c6972a1	0xe8f63469	0x4269bc90
+	0xe5c9ede7	0x7b8f7b4f	0xe777406f	0x17e2a6cc
+	0x5ffa1f4d	0xeded9e39	0xb83702c7	0x8ac429ee
+	0x926d8060	0x91ec6bce	0x89a6f240	0xbeb1b113
+	0xd0d62f8c	0x6282f306	0x805e8d16	0xc4ce2681
+	0xf1a51ca3	0xd3f69f39	0x50ee27c5	0xdcdb84d7
+	0x7744f4c9	0xe750aebf	0xae52b932	0x7833c17e
+	0xb6adf91b	0x86c7a692	0xfb8b3854	0xee875284
+	0xc66a6e8a	0x950e6596	0x5a21665f	0xb99421aa
+	0xb2bddb7b	0xf0307281	0x22e79399	0xb541e0e9
+	0x6a45bc69	0xb6ebdd7c	0xd851e16b	0x9783cf97
+	0xafdfc7a7	0x4f011d28	0xc570cd93	0x752db80a
+	0xcf3de399	0x907d3ad2	0x91faadac	0x8c9c578a
+	0x61cfc727	0x8b20e89f	0x4d5a6666	0x8c28e00f
+	0x1a1675d8	0x7c793aa3	0xa2210e0f	0xaa5a9509
+	0xa3942ddc	0x5f8b76ec	0x00aa7a2e	0xea375121
+	0x521b786e	0x4b27e1f4	0x262332ca	0x2a739651
+	0xf442ed82	0x74f40d7d	0x0f374d95	0xd6121c68
+	0xdc6aa0e4	0x0fefe09a	0xb06ef32f	0x45951415
+	0xc25d5b51	0xa139a8f3	0x87363003	0xe59a0f0a
+	0xbfc54dc9	0x69f84ef1	0x3804453f	0x976850ab
+	0x65bfbe93	0xa0b4c673	0x5fd531fd	0x1b90f96d
+	0x93c92211	0x26236f14	0x6d67aa9e	0x1fc006aa
+	0x1e41a145	0xc952b72c	0x3e274f98	0x6cba1001
+	0x8a3007b1	0x12318114	0x82ea0917	0x4a783735
+	0x967e9463	0x957c4366	0x039c4f2a	0x732e105a
+	0xbe8f62ce	0x7acf5484	0xc1dbcbf6	0x6d663150
+	0xafcc53d0	0x9e54e869	0xaccd2f5a	0x0596bac7
+	0x6102d4bb	0x145b2201	0x85772d86	0x157fd7a4
+	0x27b4bceb	0xbc8634e8	0xd713f53b	0xb9a22cb9
+	0xbb6e509a	0xec84eb87	0x58a99ff7	0x6e026c56
+	0x262cf17a	0x96aa6b86	0xa432b5a7	0x4261f767
+	0xdeb7cfcb	0xe52bd101	0xedce6213	0x6bd1704e
+	0xd446c3ac	0x3396a979	0xe46c23ca	0x1be0b8bc
+	0x04b81418	0xb74da201	0x1ba7e42d	0x96db8852
+	0x01477c80	0x4f84f7ed	0x556e3d40	0x2c5ecaa6
+	0x784f461f	0xe6a79f5f	0x223f6345	0x7dc789f9
+	0x803cebab	0xc9fc7fab	0x144312b0	0xfb68670c
+	0x8d3bd502	0xb73a19c0	0x50b4dd3b	0x4434bc5c
+	0x3c96afa1	0x4caeef15	0x4b73b56b	0x6c2dc827
+	0x09d29490	0xda88aafa	0x58e7d66f	0x02d85153
+	0xe028d696	0x397376f4	0xa0b385d4	0xfc52d8ef
+	0x9ff7f61d	0x53d9e137	0xd7eade45	0xf61a3be9
+	0x732b9585	0x172e0d6a	0x6b439ec3	0xf7e69034
+	0x11cf3bfa	0x72db7836	0x28a71411	0xa7e541b1
+	0xa11a869b	0x40cc133a	0x99568ddf	0xf88f5407
+	0x3b9566c6	0x14ee8af3	0x0a553446	0xde19963a
+	0xb30a65df	0x620f06a9	0x23a13e20	0x677abaf9
+	0x85348c3b	0x227e886e	0x621ada06	0x29410dd6
+	0x1d3279c2	0xcb2e1db5	0x8f9e4dec	0x39c7ef14
+	0x1deb388e	0x487865ab	0x2063f724	0x13309f26
+	0xcb9c175e	0x5db6e659	0x2d4afe5e	0xf93105b7
+	0x9c88614b	0xe4c2d81f	0xee47bc34	0x05a42aa8
+	0xc7a366c1	0x717696ba	0xecfe37be	0x8ef87213
+	0x7953b258	0x6b4cc006	0x9687ef62	0x7796cc13
+	0xaeb3b791	0xd8c6d496	0x6801b485	0x75d7bc78
+	0x6b6eeb6e	0xf38743d8	0x6eb75dcd	0x384cb686
+	0x54bb91c8	0xa4c32f35	0x54bb1256	0xae792803
+	0x7764e3f6	0x24ab5fa1	0x3e629e01	0xdeef8f34
+	0xea0bd2ff	0x665e7068	0x18bdd480	0x225c0af7
+	0x96d97929	0xee100c2c	0xeff847a5	0x714dd01c
+	0x4e18e204	0xe804801f	0x9ee779dd	0x8b116fea
+	0xe46e94fe	0x3a7c2031	0x059d9ae9	0x35704f42
+	0x88d7b497	0x90c487e7	0xe82c3c79	0x4ea43be4
+	0xa898a30c	0x68d8ad90	0x675dd885	0xcd3102d8
+	0x527ae14f	0x6cecf590	0x85157cf1	0x713fa88c
+	0x1a3871ae	0xa6a7901c	0x69ed7c83	0xd65a3328
+	0xb9b99e6d	0xa8abd0a1	0x22878c58	0xfc1b1ee5
+	0x86c19e75	0xe370301b	0x312058dd	0xf886eab6
+	0x6887322c	0x5bb6097c	0x45710db2	0x0a0f0b3c
+	0x77367703	0xdd22a598	0xaca61cb7	0x41a8d898
+	0x1cfd1b9c	0x1b5efdee	0xb89bc576	0x9b7bf384
+	0xa51b486f	0x43bd652c	0xdc2a42c7	0xf1d964e4
+	0x60162276	0xecb776da	0x8debf109	0xffe59535
+	0x81a2b6a2	0x3db50d88	0x2b7446a0	0x8e3db5f5
+	0xf0e60f94	0x29c4ec91	0x7d028705	0xc9822a5b
+	0x448ce3b1	0xbb764fd8	0xc1cc6a57	0x2209a704
+	0x79e09f45	0x55bbb983	0xd49826d9	0xc4a8fde9
+	0x0d21fe4a	0xba53caf3	0x7fb4bd8a	0x726917ac
+	0x987c1240	0x06d3bec4	0x20e63056	0xb935a165
+	0xda3ea0b9	0x17c5542f	0x608e6dac	0x0d0ae11a
+	0xbfa956e7	0xec1c2a59	0x8f876337	0x08cc0abf
+	0x01893ffd	0x52ad2c87	0x20b44ffb	0x9629089d
+	0xe38c7dff	0xd170448b	0x58ec3730	0x058f49fe
+	0xf71605f4	0xae95f30e	0x392fb97b	0x1d253d57
+	0xaf27d084	0xf40ee99e	0xc7e6bb9b	0x2385218f
+	0xc33d94cb	0xb3409f26	0x84aada63	0xc519ac78
+	0xb95ababd	0x70e0d193	0x85456e9a	0x619065ab
+	0xca86977a	0x39f8b061	0x283f9b30	0x501e24b5
+	0xb7c6d6e4	0x4ae8a58f	0x2d1002b3	0x59987e28
+	0x0468ccf4	0xa2f04277	0xb0ac7e87	0xb5810d46
+	0x0bad366e	0x483e37c3	0x787222ee	0xe33251ca
+	0x632f6dc1	0xb5cd27af	0x37152a50	0x03204246
+	0x734a5b2a	0x884f4d38	0xe690b2ed	0x0cf8e2f1
+	0x5e6ea1fb	0xdde6e3f0	0x2c64badd	0xb3e27661
+	0x958d5792	0xabeb5422	0x7bd72c81	0x423ddb78
+	0x5da377f2	0x63c26b0d	0xa5bc8b76	0x407d5d9a
+	0x95d388aa	0x3bd4e246	0x9e0fdf3b	0x95a68a1d
+	0xda40dc30	0x04fb17b5	0xbcac4960	0xb21548e4
+	0xb13fb831	0x897b8443	0xba928329	0x02c9ef1e
+	0x955b70fe	0x66decee0	0x0028f1ba	0xd6abca27
+	0x07c3e749	0x81daf249	0xfcc77b67	0xd92cb560
+	0x4d99bc0a	0xfd4f2868	0x835ca0e6	0xf7cbdfce
+	0x2ef23e50	0xb73dee70	0x52c31bd3	0x0216f011
+	0x8f843803	0xbb328ce8	0xbafe6cfa	0xdc11931a
+	0xca78f5af	0x701901bf	0x0cb2f369	0xcf81f5ac
+	0x130df41c	0x4ebf5b97	0xc20e71dc	0x77c7db59
+	0x7514598e	0x076b8d81	0xb4455b6a	0xd39a43a9
+	0x1454ec13	0x16bf144f	0x873b8300	0x8cf24e90
+	0x06df232f	0x5d72ee57	0xe77b4ca0	0xfe7a93ba
+	0x71a6fe0c	0xcefb044e	0xfa41f121	0x0c736797
+	0x69d26292	0xa4571b00	0xb6cd7ba2	0xd088966e
+	0x13ba8390	0xabd689f4	0xa7348565	0xe153af32
+	0xd3af3755	0x3a291ac4	0xd0fed6e9	0xe76d077a
+	0x3fa5afb7	0xea870423	0x9bc02dda	0x0696570e
+	0xc528294c	0x8035bcb1	0x3fedf497	0x4e85da97
+	0x87834ad7	0x4cbc4464	0x7fc32e15	0x9f248783
+	0x74cc30fb	0xc004e66a	0x65b3e508	0x9dc7bf07
+	0xe70e9553	0x762c4e53	0x06377c76	0x415d95dd
+	0x4c74daf2	0x5492b248	0x2ac359c7	0xafd715ab
+	0xeea3bba9	0xdc21177d	0xb89b4364	0xdd3fbe05
+	0x5e2dc68f	0xc445c91f	0xe2a7305b	0x3b434867
+	0xd55f2fea	0x028f3861	0x8c5656d4	0xe2c04c10
+	0xaea45e47	0xe65651a0	0x6f67d97b	0x759d1fc9
+	0xa0bea30c	0xe62c32d9	0xbb57faaf	0x40207bd6
+	0x780de534	0x0fe4b81c	0x0735bbc5	0x25dc0c03
+	0x3909ff0b	0x1808cac4	0x520b8337	0xb9729f84
+	0x24fb3c1d	0xd82e0a5b	0x79f99b13	0xe9612c13
+	0xaee4bce1	0xb6c0f691	0x32d2c31c	0x9e6f92f7
+	0x86e98158	0x33643ab5	0x7617e010	0xb95bac7e
+	0x0e56bb41	0x74dfabea	0x3cf7749d	0x119b9839
+	0x875cadea	0x9327f3d2	0x1b5a9b8a	0xfcdcdd2c
+	0xbb7300f6	0x7b532fdb	0x0bce3f2a	0x93a79dac
+	0xb88f3690	0x342e1bed	0xefad0cd6	0xc31975b2
+	0x575a8a01	0xa524c868	0xcde65ef0	0x97a9c33f
+	0x735784e4	0x40498a19	0x45c63c8d	0x679a2416
+	0x046c9898	0x8e66cc4c	0xff503359	0x95dfbe22
+	0x2424bd50	0x2b882310	0xe4d6931e	0x55e4e1a6
+	0x2dbfebc6	0xe2b10c94	0x2ba0b6e4	0xbda3f610
+	0x78ccb9ed	0x15eca5aa	0xf3ef1825	0x7fff8209
+	0xb9ae92e9	0x4344502a	0xbe549a7a	0x459997b8
+	0x4c88c72e	0xcb6109f3	0x57879c01	0xc1e7d40f
+	0x79cbee03	0x52a5dfc7	0xb0a3e20c	0x11cc0682
+	0x634345d4	0xb1097bcb	0x4170bc95	0xa38e7f08
+	0xf89ecaba	0x37f4f748	0x50fd02b8	0x6b026dd7
+	0x8e9270f9	0x3c6bd04b	0xcbb680d1	0xe10f1161
+	0xfa3011fc	0x273f1915	0x66bea263	0x22ba4a11
+	0x73d679ca	0x9f88a3c7	0x40eed71e	0x974b512e
+	0xc1fe137b	0xf0054108	0x223fb47f	0x0fd0ae5d
+	0xd2352fbf	0xebc2229a	0xac38d629	0x25ec7169
+	0x1939d86a	0xc879b796	0xc7f8dce1	0x92b9dc60
+	0x3e5291de	0x936a2f7e	0x9b2d869e	0x24d0f8cd
+	0x1ba680c9	0x0c839619	0x0d69bbdb	0x26a3644d
+	0xb102adfb	0xec059a27	0xe2477ab9	0xc2e9f654
+	0xe5f257ed	0xa9cd346c	0xc0f22053	0xb9dfc03e
+	0x3f737368	0x791e3a80	0x5d6280ff	0xda55df26
+	0x8d5740e3	0x2a6d7113	0x83a70056	0xbb31a7f5
+	0x413f4612	0x5302ddfd	0x44f41d43	0x675b7e05
+	0x723af78a	0x2d833251	0xaf8419b3	0x3bc05d32
+	0xa9251294	0x92fdec09	0xa1346541	0xec186dd5
+	0x252d4e94	0x55a207dc	0x09e57c82	0x05a8198d
+	0xb970c263	0xa772c113	0xe625a4a9	0x780f80ed
+	0x5391fdc9	0x40f8e6ee	0xd37cf89b	0x35e1a4b4
+	0x8e2e14d8	0xf595c9f5	0xe457cb19	0x7da1c578
+	0xbaee8480	0x6626129b	0xb0e949b3	0xdfa72b6b
+	0x2df13902	0x041f7101	0xd7ad6d85	0x84a12d44
+	0x3c48863b	0xd77a0d78	0xc4716f33	0x5f6c80b7
+	0x8dbc331e	0xb81e99b9	0xc030f343	0x1395fa80
+	0xbbc472a9	0xaadbddf3	0x331f1162	0x62aa6ae3
+	0x329ef3ce	0x3c63ddf9	0xf74613a1	0xe6845844
+	0x2bf454d9	0x9349f051	0xe47c2353	0xedd3ad76
+	0x6e148e5a	0xefc1a92b	0x2c94fc97	0xc96ac0dc
+	0xa1b239d3	0x56fa2e07	0x5dce9da5	0xd99fc97a
+	0x151f4557	0x92d3b296	0x51c5adb2	0x472e3502
+	0xa2a9ca6d	0xdf1537fb	0x7497ee54	0x652788fb
+	0x3480f678	0x6226432d	0xd3196022	0x60af6d8e
+	0x7b9ba419	0xd510fd1e	0x48d5309e	0x5fc1c0d2
+	0x108a41de	0x0e9f8028	0x549710b4	0xc48d9ab3
+	0x36fc7bff	0x7e257815	0xd51cc507	0xd321681b
+	0xe12d9f15	0xfe39bede	0xdcc3ee34	0xeb20cba9
+	0xcd77b4a7	0x894b9283	0x2b5c1cef	0x5200e41c
+	0xf67270bb	0x5d104c61	0xeb64074f	0x22f5bbc2
+	0x37d8b7cb	0x88122de3	0x009cffd2	0xe772f72b
+	0x9c63f41a	0xc424e4ae	0x1464b37a	0xa6dda79e
+	0xcf89c39a	0xf23eba0a	0xf3f3a685	0x50120883
+	0xace33f54	0x53346d1f	0x3ce75d82	0x555040f6
+	0x4b458356	0x1d617f5b	0xbd6d29d5	0x6789cae9
+	0x3d787e1c	0xaf7dac99	0x69ae0efe	0xd5b62c89
+	0xc1b371a8	0x466c8316	0x4a1a399c	0x02d36ce4
+	0xcbdc024a	0xc69d6d8d	0x88926761	0x12a5d8b4
+	0xe01c2b8b	0x1e1991cd	0xe9aca0a8	0x49410f8b
+	0x426226d9	0x4b9d3543	0x6072827e	0x6037c39d
+	0x40e457d1	0x3361d4fc	0x7de4c8a0	0x68800165
+	0xc1e069b0	0x71bf38ab	0x4ab64b8c	0xc0acd6f4
+	0xe742be7c	0x46e21cee	0xed07ffba	0x148c7fe3
+	0x48c6a945	0x8a561bc6	0x3838c25f	0xcfed3d21
+	0x87451835	0x3a75912d	0x2ca7241b	0x5b252f6e
+	0xffc394b4	0xf4f62530	0xb933058d	0xe62195a5
+	0x09542e3d	0xdc5bbbab	0xf87bfd18	0x4a0915bd
+	0xdaee30b0	0x1c45049b	0x53057aef	0x8559c1b8
+	0xf4bd34ef	0xa70cc429	0x37ecbe19	0x5d2c0088
+	0x30c6e209	0x14d3f5ae	0xac2fce42	0x47b96c6e
+	0xe0b33111	0xefc61925	0x24554cae	0x401cca83
+	0x248148df	0x4d36387b	0x01987a6b	0x8f9ac8f9
+	0xf93718c3	0xf4c0605c	0x35600f33	0xbb57951f
+	0x01bd3ae3	0xd6b00ead	0x5c900933	0xbeafdfac
+	0xb3496a47	0x0e6d06ed	0xa69a4710	0x4aeee99c
+	0xdc59363b	0x710300bd	0x51643fc0	0xb2fa91eb
+	0x379f7f65	0x39c6e97c	0x098d6935	0x2a9d3085
+	0xd4df1162	0x5a2cf41b	0xe8671010	0xcc7d115f
+	0x328d3892	0xeea7d61f	0x573ec7e9	0x741a117d
+	0xee2ea628	0x3d1b983c	0x7f92a4bc	0x62025cbd
+	0x7ed34073	0xddb5d088	0x10139b27	0xcc217f9c
+	0x809352f2	0x6d1a1668	0x4ee31e30	0xd21e1f5f
+	0x6d37301c	0x176d8faf	0xa7768fde	0xcad1bb7d
+	0x24deebef	0x134a7f2e	0xcde8fd3d	0x409fff56
+	0x81b89c4d	0xdadf2ef1	0xe970a40f	0x4dca9906
+	0x948b6082	0x886f9c40	0x402ab8b5	0x3f3a363d
+	0x31c5f241	0x6b829609	0xf8923e52	0x2c6f3dc2
+	0x8b831a4c	0x0f847c9e	0x5dec8240	0xdd999571
+	0xe0e0bd87	0xcdabc523	0x347a64ed	0x622a5655
+	0x63a26351	0x29ff7cd6	0x5dd5dfa1	0x79996f26
+	0xde481466	0x10d4782c	0xb6e77d9c	0x0dc2853e
+	0xd0c81fd0	0x5f0bb987	0x27f4ef8d	0x9c23b96e
+	0x98fb2a24	0xa0e15d67	0x93fe17cd	0xe628130f
+	0xf2843acc	0x93bb57c9	0x4273a3fa	0x265976f3
+	0xbbee8aa4	0x52d8ef84	0xb3997bba	0x369525b6
+	0xeb7c39af	0x872c5324	0xc400f956	0x1cb37354
+	0xf4948758	0xe3096651	0x5a0ba8fc	0xfb69c499
+	0x312d8763	0xf3343ecd	0xe6fd3135	0xb3498520
+	0x5c854917	0x328b3eaa	0x1c840929	0x1c36fe47
+	0xfe0c3e42	0x56a8862d	0x3569f945	0xc22dda25
+	0xf84b1f5b	0x004dc57c	0x8a00a3e2	0xac699574
+	0x51039189	0x765e8036	0xc7afcc49	0x04842695
+	0x7b84b057	0x9c97f05c	0xcc79bb47	0x17dfb4b6
+	0x2fe652d0	0xe1498d3d	0x2ca8b3f8	0xb53ee5e3
+	0x1050d2b3	0xa2572be1	0xfcd3c334	0x70a15f82
+	0x1728b0db	0x6209c5fc	0xb44e5603	0x863332f1
+	0x96838397	0x36955feb	0x0d2da0a8	0x125e7d60
+	0xde2a310a	0xa351a181	0x6b228298	0x8a4d1cee
+	0x5e6b14b6	0x2f3a9457	0x3e9dc04c	0x74479b2e
+	0xd3d05a04	0x68d212fa	0x117406a4	0x4748ed39
+	0x41d5cd60	0x8dc01410	0x3ae6572e	0x70285c5b
+	0x83134014	0x1ef0ae5e	0x003e6be1	0x0b3ae0b5
+	0x39185245	0x5855200a	0xa12dd85f	0x35d08c8e
+	0xb8b9b054	0xe631c2b9	0x2008ecfe	0x8f3eb245
+	0x79b3a1b5	0xec1b3903	0xda6d57b0	0xcdee5055
+	0x25af467e	0x26d5f7ae	0xd97ec276	0xeea91eab
+	0xf261e901	0x3c981d7f	0xcd9dccbb	0x32136d85
+	0x9cfdb038	0x7fee83d3	0xf6e6d1f2	0x177663fc
+	0x0b6ed3a5	0x72670825	0x2cbb9cef	0xe4436641
+	0xc61f9d9f	0xb5c763d4	0x213a06bf	0xbbce6dc1
+	0xaf464963	0x343697e4	0xa2b3af13	0xf7fdd78f
+	0x6a460f6c	0x1b62c963	0x352ba307	0x91c830d3
+	0x66116773	0x280dfc31	0x302844db	0xdb47b3bb
+	0xc0ad1851	0x9979ba50	0x0083ba23	0x25c70fae
+	0x7c06b66c	0x65d20a4e	0x9848a1a2	0x295bacc7
+	0xe44c5837	0xfecf2330	0xe3ed6510	0xb1a48827
+	0xe694e108	0xa8a41bf0	0x17c797d3	0xfdae9b67
+	0x6f8ce672	0xc8d89a80	0x8f71f171	0xe95b2a4d
+	0x99f9e617	0xa6af87d5	0xa9160687	0x9d0393de
+	0x89bd4e6e	0x6528c903	0xa3ca2db1	0x6f77a5d8
+	0x9c377bb6	0xb888ea4f	0x06b81f7f	0x3c5c8de5
+	0x3bbcc468	0xcfaae47a	0x502a3f60	0x158c94c2
+	0x225ab827	0xaa630a68	0x77afe20d	0x19fde08b
+	0x171a5af6	0x81d81f8c	0xfde9be4f	0x69cd49b0
+	0xd83ff3c8	0xec30b85e	0x58621479	0xda1f95a5
+	0x0b1d8f12	0xcda765c2	0xb509d70b	0x76d158e3
+	0x7c9d02b2	0xebfd61e3	0x6e4d8ec8	0x8b779fdb
+	0x38d745b1	0x287a434b	0xf20a73ad	0x897e635c
+	0xdb9c36f1	0x12d23511	0x92f661bc	0x1e46d8a8
+	0x58d1f9e2	0x1f984e89	0x3b7d87ae	0xed74a89f
+	0x1c5614e3	0x1498a110	0x042704c3	0x287ba930
+	0x2f2a5122	0x5838d48a	0x85b720f4	0x2c99ed7c
+	0x893ab885	0xe1d9b760	0x0d097bfc	0xc0b1835a
+	0x2565db51	0x8b2c75c0	0x34b273ab	0x4e77c96b
+	0x95d64cf4	0x466a739d	0x32f2f18e	0xb993681b
+	0x2259c2e3	0xcd3c5fad	0x93b7a44b	0x56db345b
+	0xcc391356	0xa56659ce	0x9ab298d3	0xf756c870
+	0x9e8aa6b1	0x27f7ecfe	0xb02ecf08	0x3db06cfa
+	0x62225f46	0x0cbdc0f4	0x3660bc97	0xb600d787
+	0x47448beb	0xf2ec76e3	0x2f35cc41	0xaa07ac70
+	0xc8d7cfb6	0x3191df12	0xa35ed6be	0x5f6350a0
+	0xc92a1b36	0xe51e83cd	0xe67f70fe	0x2c30dc44
+	0x2720ea68	0x8989e2e3	0x1ee7a61d	0x25e49174
+	0x60370be6	0x4ad9f751	0x98269b55	0xe38875f5
+	0xa7dcebe5	0x8eaf1efb	0xaca785c1	0x75ef8dad
+	0x9c4a4e81	0x05b14e6b	0x94973929	0x8b0e51b5
+	0xad7d26fc	0x6028aca3	0x76abe148	0x2cf38c8e
+	0xf16de59b	0xe0e9ef73	0x14a157df	0xa487f134
+	0x90808475	0xc7c8fdde	0x507b2fa8	0x715be38f
+	0xe984cdcd	0xb86a2fd7	0x62996d71	0x41ae9aae
+	0xaf328519	0x6e26bd43	0xa9259149	0x43011256
+	0x8db13e02	0x666fcc5b	0x75850832	0x7a8967c3
+	0x533724bc	0x57d692dc	0x4b2bfa27	0xa94f1345
+	0xabc7f978	0x112a0629	0xdca1371b	0x99b30d9f
+	0x171c1e7d	0xba9c4528	0x715eb21f	0x824dad28
+	0x77b0faec	0xa8dba035	0x3026db98	0x5480ebd8
+	0xf6dcf737	0x9f01c720	0x505379b4	0xcfb68c56
+	0x8010d1ec	0xc0a022b6	0x0494af87	0x34a5e3bd
+	0x5f97db91	0x91c4f8ee	0x22c177a5	0xb3b3b38c
+	0x3b96b026	0x75e82ee9	0x6c25591e	0x79cb8247
+	0xb81a26a3	0xe9242a92	0x8427b5f9	0x0893338f
+	0x0d6869c3	0xec22cd57	0x5d7d4621	0x95cdac7b
+	0x8408d975	0x11d40c4e	0xf38fe7a1	0x088dbf91
+	0xa603a268	0xd9098a09	0xf8687105	0xba9e11eb
+	0x197b4e7e	0x4308d671	0x50b99383	0xc29a07bf
+	0xe1076808	0x22d410a6	0xcfdf5b6c	0x798c63b2
+	0xf8928203	0x59341208	0x9da6636c	0x7ea8b574
+	0x9c56d366	0x9ee85f63	0x27901787	0xf7fa83b6
+	0x11ec3148	0xc5866a56	0x1ac9faf8	0xc8600dcb
+	0xb4cbf815	0x6553c20e	0x408db234	0x30452ecd
+	0xa50638c3	0xac82df8c	0xc12e0fe6	0x281e6189
+	0x7f4d9cc0	0x5c12a79e	0x8da23fb4	0x8e495e59
+	0xbe52507d	0xc75d5612	0x7ca07018	0xffe33c48
+	0xe8a9c75a	0x30a3d329	0x8fda15ba	0xd7c53ea3
+	0xdd07d298	0x968dd723	0x594af13d	0x05593aa4
+	0x2fab8d67	0x3ea4294e	0x60c3d12c	0x1b2a165b
+	0xe3b5d840	0xe8f078ad	0x0bcf0df1	0x56a08b20
+	0xb99e6aa0	0xf119a946	0x1b3b1613	0x0691eae0
+	0x20a8c753	0xb864bd3c	0xeec8d111	0xfc809ccb
+	0x5230e148	0x968a3f36	0xbedb39ee	0x96ef8cec
+	0xd137d35b	0x4b336a7c	0x8fcf008a	0x65a4a722
+	0x7688912a	0x95b30531	0x8bd2df5f	0xa21f1deb
+	0x7c8288c3	0x11cb48ba	0x3604f444	0x56af95f2
+	0xe16135cf	0xa7b34be6	0x104db16e	0xcb94acf9
+	0x5e9be620	0xfbdf8d99	0x61a16de2	0xf1739a2b
+	0x177e6ccd	0x2d473093	0xf8b85187	0x10c7bdad
+	0xcd44645f	0x6a7a371d	0xe860523c	0xf631119d
+	0xaaa070d6	0x79668637	0xe9117794	0x42c496d0
+	0x9d294481	0xa640ccba	0xc1201582	0x5d86a701
+	0x1c935a06	0x10719c63	0x53889b4f	0xf0e56447
+	0xc54e8d83	0x95968c38	0xade37a4c	0x2fd5461f
+	0xb2e4cc0d	0x316c6c57	0x379cd5da	0xdb4510f0
+	0x5d71f2b6	0x10786416	0x6fcad2da	0x65f1908c
+	0x64aad9b9	0x08cc03c6	0x57ffa0f9	0xb12d0384
+	0xe12be67a	0x3dc91a85	0xd88ca183	0xb3b3512c
+	0x5b0d71c3	0x1389ed0f	0x99b6823c	0xc263b6d8
+	0x7e6a18ed	0xc74c9223	0x03e92612	0xc3b16895
+	0xebda3f4b	0x76d79b51	0x6b41a791	0xe838eb87
+	0xf80aa3dd	0x49dc8f9c	0xad7dc06f	0x0c0e6e03
+	0x9a533db8	0x51d66b1e	0x5415c797	0x9645217f
+	0x34b8dd97	0xc100b64a	0x6d2de029	0x4f7e89fe
+	0x8292bd52	0xa4309ad5	0x4a6651a4	0x4e67eaa8
+	0x97e27f87	0xd24fdbbe	0x367ec769	0x5704cfcf
+	0xc48e8c08	0x56fe9fe2	0xfb85f4ed	0xb0c68432
+	0x226d73e7	0xa1ce4c14	0xa50f188a	0x33f003bf
+	0x273e59ea	0xee1a3901	0xcf20c176	0xef66122e
+	0x197b9e36	0x4d866dc5	0x9cf4b530	0xd56ac309
+	0xf91f0f44	0x3143dae4	0x61ba2ac6	0xab3e3241
+	0xb070fe2d	0x8c7ed48d	0x9cdd506b	0xd052fe76
+	0x171287b1	0xed3fbd70	0x98f23794	0xe881dc63
+	0x916d5bcc	0x5a5d405a	0xf450ef75	0xc99b0ee3
+	0xfc1f0b8a	0xe05e94d6	0x1f0da54a	0xafc412bc
+	0x838546f2	0x7913cd41	0x029b6992	0x00bc4c0f
+	0x872c237f	0xda6114b3	0xc18ab867	0x437cfde0
+	0x33aba1cc	0xf87d202f	0x571b233c	0xd2ebc904
+	0x5efca706	0xa7d9aaa6	0xdc03ca11	0x1b5a00af
+	0xf85427bd	0x5329e108	0xae95f78d	0xf38e0d3c
+	0x8f976d3e	0x36474f32	0x8b96a672	0x2f5fb1bc
+	0x2c12ee75	0x348265d9	0x69ccbab1	0x852631d1
+	0x71a08001	0xc6e3ed3f	0xfa9a584f	0xa3e98596
+	0xd6730da6	0x41300caf	0x7b5fd490	0xc9158337
+	0xe02ed753	0x605b5f9a	0x684b6cfa	0xd8186840
+	0x1026e9c3	0xd8550587	0x37d7fcda	0x140021ca
+	0x13effe78	0x6f3184ca	0xa8f8ba37	0xf56a5c29
+	0x502f4ba0	0x36901ba0	0xdf60a738	0x6afeccf9
+	0x206e4e7d	0xe763e575	0x9e3dd2e8	0x574c3bd9
+	0x2b9050d5	0x36b1833e	0x018a432a	0xa544ffcd
+	0x94d11277	0x350c57f4	0xbde9ee5f	0xf2c634ee
+	0x826933e0	0xd807dd5a	0xe9ce6b4e	0x380419d4
+	0xc48514fa	0x9fec960b	0x612b53bd	0x3bd0f68f
+	0xa8b9573f	0xee1af1a4	0x5ba43078	0xdc4433e6
+	0x09980221	0x84e2b562	0xd0685c82	0xc821e22a
+	0x2f591314	0x36cd6cf8	0x95a584ee	0x85ac1c0b
+	0x8e1c4d17	0xfdcd3aff	0xf59140ff	0x990cecb2
+	0x5a86b9c4	0x0be7961b	0xd10cf022	0xda4e0039
+	0x0d42ac7d	0x6b6068ed	0x595b338f	0x8e66fbd1
+	0x5d76290e	0x1eb1d30d	0x02681d5e	0x675f48a9
+	0x3620fec9	0xcbeb129d	0x9d0d7d90	0x286b7f46
+	0xc96084b6	0x001d009e	0x5e0d3f04	0xfdc775cb
+	0xfdc6f6aa	0x4f29084d	0xf8fbd3a7	0xf859eb71
+	0xa7e37df0	0x9efe5fef	0x2f611654	0x7061f5ce
+	0x50f95714	0xcca9c4b2	0x72262846	0x376c21bc
+	0x4edad528	0x5d241145	0xf2dc8615	0x9ac9da86
+	0xbc5e3211	0xc6df5283	0x8f1346c8	0x52479029
+	0xa38fd13b	0x7b81167b	0xf7f2eb16	0x09e4675a
+	0xa4cbab39	0x4aaf12e8	0x0d156c19	0xf2ee198f
+	0x857661d4	0xa39f33fb	0x6f500373	0xdcd3aab6
+	0x5e4d97fd	0x8184eb1b	0x1e00850e	0x56037e60
+	0x1f5c2839	0x5fdd3d3f	0xf5462ad5	0x9e96d752
+	0xe1499fe4	0x30571868	0x895af53d	0xd37d411d
+	0x4a1a3461	0x95c4f0b0	0x5ead887c	0xf53803ac
+	0xf3cae670	0x09f151ea	0x102cfa3e	0x5784433d
+	0xcf581826	0x476cfbb9	0xd1489eb6	0x68f4727a
+	0xc4dc85a4	0x9094832a	0x0ff6725f	0x7f1f40a0
+	0xf771d9d9	0x13c2b620	0x75448c8e	0xfec2bfc1
+	0xd707e400	0xabd5b0ff	0x71753ced	0xd4e9fcf6
+	0x2a4ddfd6	0x2719afe8	0xea8dc6a6	0xf75ea39c
+	0x619a0725	0xab1110a0	0xbd63041e	0xd839bb8b
+	0x693bfce2	0x989031f9	0xf621e105	0xedcbd708
+	0x0cb4aa8d	0xf1ccef16	0x06894709	0x0aff3a4f
+	0xdefe2281	0x2ad64edb	0x349b9733	0xe062b7f4
+	0xc8aa62be	0x36a184f1	0xcb918d5b	0x844ea7ef
+	0x78585466	0x80139ac2	0xe45b2b11	0x973f0a62
+	0x5dea255e	0x916925c0	0xc9578efa	0x3ca7eb07
+	0x36c02e4b	0x89cfcaa3	0x641b07ad	0xf9e7197d
+	0xdbda750c	0x447f1191	0x690f7c39	0xd7e9a602
+	0x6edd8896	0x2b03daad	0xbd288f1e	0x7f70057e
+	0xc8567673	0xaf74fac0	0x37e31aea	0xd992d754
+	0xe8211c22	0x3eaed525	0x88fc8ef2	0x2f41b02a
+	0xf3c07f7a	0x3777c91d	0x8c3ed230	0x82c64da4
+	0xdeff0362	0x2768503b	0xcdbaf18e	0x9a45ccca
+	0xe92fd6ad	0x72a71f75	0xc5bd6f66	0xbeb4d59a
+	0xe99415ab	0xf7dd10c5	0x0db15260	0xbbac9f71
+	0xa3e434ba	0x40fdea27	0x50eb8c40	0xba26f675
+	0x2ce865b0	0x748ec966	0x6490f9fe	0x01dbda28
+	0xd4dfed39	0x645fb3b4	0xcdcb9de0	0xccd7fcb1
+	0xd0dabcac	0x60fd0fbd	0x168d9289	0x270ecd39
+	0xe1ca48ec	0xd242edb6	0x95ba25a0	0x34ef7dc9
+	0x39b20624	0x4aab3814	0xf6fffa0c	0xe6f18c9b
+	0xc579ea88	0x3c29d3cc	0x15358dc8	0xe2ca0595
+	0x067a5f59	0x98ac44bc	0xf92ecfdf	0x2a8f2847
+	0xc7098327	0xf770c58d	0x65247164	0x2356f75b
+	0xe38ee36c	0x19bc57bd	0xd1432cf8	0x4c343d9a
+	0x800294b0	0x41906df6	0x211fb5c3	0x13d372ca
+	0x8649cb8c	0x54a6908c	0x12b21839	0x188da49d
+	0xf026020b	0x9dca39f3	0x1b85ad7f	0xe16f849f
+	0xc74d6d14	0x1542b72e	0xe2e21a4f	0x13c01264
+	0x1af57985	0x15d69f66	0xf0475b50	0x791db250
+	0x16c4cd65	0x6aa3172e	0x50627731	0xc050f139
+	0x8690135f	0x6b2d53f5	0xbea8c582	0x770e5dc3
+	0xc6f1e36f	0x532b5b3d	0x5f513746	0x16a84ad7
+	0x1d429215	0x84b0905f	0x98a47e1b	0xc8b47605
+	0xf67fc56b	0x862e5696	0xeaebb6c7	0x2cd4dd80
+	0x7a2345d0	0x89f02a31	0x757d6bfa	0xe1532bd7
+	0x0eaea9e2	0x4a00dea0	0x54414e43	0xf1b723b7
+	0x84b589bb	0x17b823cf	0x885e8430	0xc658beb3
+	0x7251da37	0x9c6c0c94	0xd6237fde	0x7526c254
+	0x7abe9c40	0xc815aa39	0x5c2359f8	0xd2ccb88a
+	0xd72c3593	0xb5bac7f5	0x500d5980	0x63d1e5d6
+	0x43f2fd4b	0xd4e7a58b	0x682c83c0	0x372647da
+	0x897844b5	0xc8f43767	0x52c95bd9	0xb134d1e1
+	0xf4dcf340	0x0418a91f	0xd5f53498	0x8960aa3b
+	0x559e959d	0xc9465034	0x92f87c38	0x030bad59
+	0x535a65f3	0x2a77f8e5	0xdfa3bb3e	0x1cfb0e7b
+	0x745c3e85	0x4adb107f	0xe0ad43e6	0x2d2d7110
+	0x1d2f4281	0x2eba0483	0xf1741ce3	0x872c33d7
+	0xf43039d9	0xfe974a77	0x5bdb65de	0xa9ae81cf
+	0xd950f31d	0x4f9dba1d	0x86c23a69	0x091cf111
+	0xe658a751	0x84a91276	0xcd95d552	0x28e6ca41
+	0x49f25055	0x63d4b350	0x5bcd4eb4	0xca30011f
+	0x80c53e84	0x09bd4736	0xbaab15c7	0x240a5c91
+	0xc78d09a4	0xe65699e7	0xa53f862a	0x4dab9d76
+	0xfa9a9fc3	0x59603e35	0x2ac717ca	0x46b604d5
+	0x6c3f7387	0x8b036d97	0xf2e656e8	0x3134f9fa
+	0x07e4c866	0x5ffe4c6b	0x0b66f7d4	0xf70ec6ae
+	0x70a34f65	0x5b899964	0xfa6d75c8	0x1201342b
+	0x6a97079e	0x265e17b2	0x68c65a50	0xff89ec35
+	0x1dd400fe	0x442463d3	0x28255bc7	0x0b59c045
+	0x3184409c	0x22149a93	0x46c4e731	0x79f055dd
+	0x37f63a7e	0x7e756b2f	0x215965e0	0x50d6830e
+	0xecd76722	0x7ccf6440	0x7f35066a	0x6ae5b23d
+	0xf1b3d97b	0xc10fb8f4	0x1dc8a180	0x560fde50
+	0xc309b2d5	0x67f045a3	0x1c9b5b82	0x5a58d04e
+	0x1605cbe6	0xb39d46e7	0xfc73771c	0xb27cad4e
+	0xb11e103c	0xfcf832c7	0xa445f737	0x63704126
+	0x542bdf70	0x4a134996	0xdfbbb48a	0xd46b0c8a
+	0x658504f0	0xff3a73cf	0xd6a37646	0xc76bd82d
+	0x7f590e8b	0x45168edc	0xbc980f1e	0xb74cbd25
+	0x8ed51cfd	0x42e86550	0x098d3dca	0xa1c667fc
+	0x4a1cf2fe	0x6dac04c6	0x0c06311a	0x56c5ee6b
+	0xae2fef37	0x3077ed34	0xed2b3c58	0x704796bd
+	0x8d4b9dd7	0x58e93741	0x3d954ff6	0xdd2514b7
+	0x4bd6d974	0xd6e0f1c5	0xcd38a25f	0xa5315745
+	0x982505f2	0x16c78771	0xf03bf442	0x8433c49e
+	0x822b13a7	0x5e52a287	0x3e837cc4	0xf5246300
+	0x62235c2a	0x4286917f	0x92694b91	0xc149428b
+	0xcee47250	0x1073ca49	0xadfe26e0	0x39b7b1bf
+	0x0980b264	0x460e0f79	0xb747c221	0xd2280e13
+	0x6ebaae7f	0xbf5e4fe1	0xd83a06ae	0x15607146
+	0x9f80aee5	0x9d3d1ea1	0x3ac75973	0xbce15424
+	0xd3afad28	0x60b00359	0x15b1f6a2	0x860dfc81
+	0x3a3aced8	0x17e60cf4	0x628de10b	0x6226cf18
+	0x94aac94b	0x04e89e23	0xd647af9e	0x34fac1a0
+	0x82107a58	0x5ff06089	0xed899a38	0xa95fc727
+	0xfed5f0e1	0xfe6db6fb	0x495cc0da	0xa36d9c65
+	0x9ae386d3	0x091791a6	0xca9619dd	0xd1b1681b
+	0x283ede9d	0x54684259	0xdc0ab403	0xabf2d823
+	0xf2705407	0x48857264	0x5a49666d	0x8d73c4cc
+	0xc6d6c23b	0x924b2fc1	0xbde8db0e	0x6be302a5
+	0x13d38cee	0xab9c5a5b	0x6e3f151d	0xc68ebac7
+	0xcab34c09	0xdd0b5340	0xd7599b20	0x5c05e5fd
+	0x58975ebd	0x253b9809	0x90044065	0xa34a0b9a
+	0x7b98fa31	0xba00d0ca	0xbda6fa17	0x97937eb1
+	0x43ab04a0	0xa85e1fa3	0xe732c720	0x43113659
+	0x80e21c8c	0xc1593d8c	0x5304dbb0	0xcdb37507
+	0x99895f48	0xc1018047	0xeaab54ed	0xd5326d76
+	0xc1371a9c	0xcfd263bb	0xf9ecddc0	0x2381b427
+	0xac78b897	0x46bd1bc4	0x0b7f5dfa	0xe55ac354
+	0xd98b29e1	0x7fb53225	0xadf7fd1d	0xe7f42f6c
+	0xe42b58fa	0x31ba8f85	0xea3d049e	0xacfac52b
+	0xa50181c1	0xae6a0de6	0x16cf1122	0xa5aff99f
+	0x9d1102c1	0x10f11ca3	0xabfb8005	0x9911353f
+	0xbb430261	0x81c1400d	0xe01c0343	0x038b2e46
+	0x3f919f9d	0xc0e1c884	0xde6272fa	0xc25d6ea2
+	0x72e18fb7	0x88b8b150	0x8e85cd62	0xf0e1d37a
+	0x96ef1ce2	0xe32c8193	0x1001ff2d	0x9964ec56
+	0xbe8aaf70	0x1a416fea	0x1eb92b2a	0xa3578712
+	0x9504cab3	0x77e975ba	0xc491748c	0x3080c466
+	0xc8418a02	0xf44d7998	0x77051bcc	0xff646682
+	0x6082eb7f	0x2886a8f3	0x88315209	0xa7b9fab0
+	0x6f6c2b63	0x2aeb4634	0x809011a2	0x2df48429
+	0xcb39f8a6	0x6b879cb1	0xa7b47618	0x09b8666d
+	0x706ab210	0x0864689c	0xd1ca3fd0	0x69c1e584
+	0x5212526e	0xe1a9c5ef	0x5685d88b	0x5382bdbc
+	0xf8d5bc5b	0x8e8ded9d	0xc8cc93c5	0xe1e226f0
+	0xd2c17da9	0x23cd104c	0x4362ff2e	0x88a7a9c5
+	0x8a2e8873	0xd0581d74	0xfa1d8084	0xa9829395
+	0x31a382e8	0xf423acba	0xbd436f3e	0x00ed9514
+	0x964d6ea8	0x45e530cd	0x7b067f2d	0xe758fa63
+	0x82767a73	0xa5e5d959	0x83adda38	0xca815b70
+	0xca2eb490	0x879da759	0x3af36316	0x1c398e43
+	0xb7033303	0xde77c60d	0xa0e83068	0xa072c077
+	0xd038adcc	0x979aa6f3	0x4ff53908	0x1fcdb043
+	0x83ccc713	0x38bb8a83	0x185cb8be	0x32594da1
+	0xb5771673	0x9b371c9b	0x71554d0c	0x353452e0
+	0xeb17922f	0x86f610e5	0x219706c5	0xc2516c79
+	0xd9f1e5a5	0x4e71dd96	0x19acd081	0xcc9e8fb7
+	0x3cdca52d	0xa8eaf0b7	0x677a8883	0x29afcfeb
+	0xbe65bf18	0x578d900e	0xce1f20b0	0xc0464b95
+	0xd8a7b365	0x153ca5f8	0x338f4440	0x725fb123
+	0x0266fe31	0x20afb681	0x6ad3e79a	0x4b0fde5a
+	0xd482ceef	0xfbebb20d	0x9ba0e25f	0xad5e0225
+	0xb8a55ac3	0xa1823693	0x1ec05e62	0x5f0bc17f
+	0xd45315c1	0x581d4f7c	0x71d0fc2e	0x7ab28236
+	0x2058473c	0x59778cad	0xa31250c4	0xf5ee4b70
+	0x0182f25e	0x093d224c	0xc0e2a624	0xdef1a681
+	0xc3ac2477	0x684485dc	0x248b6733	0x2154c4d0
+	0x48125445	0xdfcc6d53	0x98648e66	0xad47ff70
+	0x98de0ea0	0x705b6663	0x585c82f5	0x41fc7750
+	0x0f9302ac	0xd84db157	0x5473b3af	0x47fc75e1
+	0xfd70ad9f	0xf8ac1ad3	0x2d44d472	0xd2efebac
+	0xc012bb8c	0xaca62095	0xb2909db6	0x71f0cd19
+	0x10f22608	0x7d2bc553	0x6a422ca4	0x5d8ca05e
+	0xbe2c2447	0xc6c7e0bf	0xa497d984	0xc647d81a
+	0xcbedee3d	0xf32ffe2c	0x6162e640	0x41f69600
+	0x91244338	0x95609997	0x8d238396	0x66e7a884
+	0xb12cdbc7	0x47161675	0x51ecf757	0x3c82038d
+	0x031421db	0xe2ef93ea	0xa68873df	0x039e0c25
+	0x5572321c	0x9df1728d	0xe6ed57c0	0x57a039f2
+	0xe31b3be2	0x55715ed2	0x59d600a5	0x3ba7f734
+	0xa429f7da	0xff7ddad3	0x1ce287d9	0xbd308541
+	0xa6b20324	0x1fd4c741	0x9244413b	0xd914325e
+	0x486a10c3	0xaba191f0	0x09cd2579	0x6fbd86d3
+	0xf9eaabea	0xcbc6a11f	0xc97eff2e	0x604949d5
+	0x73208a00	0xc5640d64	0x75fd1830	0xea2841b2
+	0x3efcac7d	0x3f2be687	0x9737b5a5	0x7846b723
+	0xfeb5d90f	0xbf9b347e	0x94629b88	0x0e0bd993
+	0xeaa3a0e6	0x92758d2f	0x06b4a92c	0xee31d291
+	0xcf91699e	0x39b5a732	0xb63b660a	0xc5ffeaa1
+	0x90833668	0xd1995d7a	0x84030c26	0x62b1ca49
+	0x7efa5144	0xe7288b77	0x6230a776	0x1be6a7db
+	0xd2a0bc0e	0xfb36d845	0x261fb4eb	0x8f8fc434
+	0xfb833fb4	0xc7474543	0xda6c6a88	0x1659bb4c
+	0x9194a11d	0x071154f5	0x82d51f58	0x63a2f751
+	0x46f7a823	0x04974444	0x360cdcdc	0x7452e132
+	0xc9a98443	0xd03ad3ab	0x30dc5c84	0xd3928173
+	0x38b6e6e1	0x0cda2c1e	0x4cd9d2bd	0x59cfadb4
+	0xbf73f35e	0xfed1a2e3	0x7c7f7fbd	0x9b5129a3
+	0x780f877b	0x2104f056	0x90bdc3a4	0x9ee71bf4
+	0xd28d3305	0xad550ee2	0x3c8f4067	0xfa0dd7e5
+	0xd625f145	0x3b5cd69e	0x645db568	0x5e56c683
+	0xfb1f1f24	0x2bfe72c3	0x0cdb2809	0x9404915b
+	0x120d6624	0xcfe55309	0x0b978365	0xb4a25446
+	0xb26e8767	0x83c6e6a8	0xaebacb46	0xd79ed05f
+	0xd4d07268	0x1bb3faf1	0xde8dbf0f	0x2e7ba152
+	0xabc0ff05	0x6ca54fc8	0x51acd5dc	0x65a18671
+	0xa619f93a	0xa84535c1	0xa0ede59b	0x6bd55a4e
+	0x5aba8fb8	0x01cc90e7	0xc3eea3cd	0x0f503e9b
+	0xad697d5d	0x6021cacf	0x70dd0dec	0x11d7617f
+	0x19e6864a	0x6b252ab4	0x6820dba3	0x9db53d55
+	0x1108f4b2	0x71aeae7e	0xdff9a4fa	0xa724e0b9
+	0xefe50832	0x91ea4d28	0x4f02d339	0x15e0212b
+	0x2c725507	0x3de817ac	0x4fcbd836	0xf9484b90
+	0xeb9ebf31	0xcfd90e4d	0xd3d6a071	0x3dff27c3
+	0xb891858e	0x99daaeeb	0x3dc5528e	0xb2fea196
+	0x2724ae08	0x6c5845a7	0x184faafc	0x44446f10
+	0xe9d1537d	0xb0933101	0x9229e352	0x4f426c82
+	0x98147850	0xca22c0fb	0x4d414090	0x981ac8f9
+	0xb8d034af	0x6b8aa278	0x6508c7b7	0x6293fe73
+	0x66f15617	0x0679cf83	0x6a58257d	0x4deae251
+	0x6e19dc6e	0x899db947	0xcb261cce	0x9c8d3929
+	0x64a097e4	0x38acf6ab	0x07beeeb0	0x9ba17f04
+	0x6897fa21	0x1445cb4d	0x6d79f51a	0x83661214
+	0x812f8cb4	0x73a15a75	0x5d9edf24	0x490b66b2
+	0xf503c382	0x9a7b92bc	0x8367b4d9	0x8df42ea5
+	0x790dc812	0xe8a51197	0x1f9ec3e8	0x0fe9d551
+	0x29facbeb	0xaaa131a7	0xc0ce9784	0x3f0b2412
+	0x63d56d18	0xe2ca7aef	0x35f66550	0xe49095c1
+	0x8d8531f1	0x815ca696	0x18f31b28	0x39a102bf
+	0x96bd3241	0x1b79f65f	0xb5750fc0	0x7e41b1aa
+	0xe7c7e0f6	0x294a848b	0x0d90877b	0x87c42915
+	0xd5839e6e	0x00635ed9	0xc51b8d91	0x34e60826
+	0x08082536	0x3550eed6	0xc78b127e	0x2f428ec3
+	0xaf95830e	0xb0c8fb6c	0xc0b5e989	0xb45d0020
+	0xce6466e0	0x8e244ba2	0x17ef4563	0x2c74b037
+	0x8d15449e	0xa96ad89d	0x0672ebbc	0xf5a037f4
+	0x633b2cd2	0x82d1cb6a	0xeae7ab21	0xfe156394
+	0xb223326d	0x6bf37192	0x349934ac	0x747e4995
+	0xfff3f992	0xe916d599	0x95917b72	0xd3e810ad
+	0x704231a5	0x041ed2f0	0x32cca85f	0x2ceb1663
+	0x80d3e7c7	0x901d33a6	0x18a99b15	0x21b50c44
+	0x295e5a16	0xceab5147	0x503b6e34	0x732a4fdf
+	0xb6b38684	0xa1317fff	0xb76492ef	0x88e7eda4
+	0x5ccde55d	0x7448f240	0x12d3436b	0x6a152377
+	0xff0b0448	0x8b124b95	0x55321a93	0xed4229ef
+	0x7ea05a46	0x992eb553	0x5f2d7278	0x90dd258f
+	0x6ecd1946	0xab971c70	0x3d341faf	0x49855465
+	0x1973c8cf	0xb5976088	0x6640e00e	0x155dd9f3
+	0x674285a8	0x720515e1	0x5fdffc94	0x0d3a3347
+	0x1dbfe5ff	0x7079f37e	0x8c470652	0x46d6c1e3
+	0x1402e1b4	0x05217695	0x67e45039	0x683ba960
+	0x97cadd4e	0x59664501	0x4726c2a6	0x7601358b
+	0xec77b4b9	0x66a912a0	0x8f157d86	0xa0e221ba
+	0x3aa4bd23	0x547e9323	0xaa94772a	0x1ba6ac0c
+	0xbed2aa6f	0x8a945e94	0xeea5c775	0xf2c66a89
+	0x89ebde2f	0xd7b4e71c	0x6a1c8bb3	0xb9392201
+	0xc7a2191f	0xf180c19a	0xc3446d78	0x7f5f61c8
+	0xc6a251da	0xa27c507f	0x329133a1	0x0c951593
+	0x344ca56a	0x329dea98	0x73112997	0x32bc47a4
+	0xbeb18227	0xd3347aaf	0x1c481ab4	0x62606e69
+	0xe18da26b	0x8243c025	0xfe05b066	0xc1b0c590
+	0xd8c107ba	0x235b8c6a	0xac4fe894	0xa012810b
+	0x5470e6de	0x6f1217ae	0xcb099ad1	0x2b03655e
+	0x91f0b417	0xc21a1af4	0xb4a8c50e	0xa5988ed2
+	0x7f03fa1e	0xa0658a65	0x5532c4b3	0x1fdcfcec
+	0x17f41c26	0xd6b29efb	0x3411f331	0x1b774029
+	0x2ee2d094	0x9f5edaab	0xc644a9f3	0xdc4cf7b1
+	0xb6304748	0xb064cfca	0x89e4dbee	0xb1563a5e
+	0xd370bca8	0xe6cb17d8	0xbfcacc87	0x76940250
+	0xf2456a18	0x3c1873e4	0x0a3d7d0e	0xeb145eb9
+	0xe88a48fb	0x9413f290	0x626e4e00	0xb234a13b
+	0xcbf49379	0xcf600cee	0xc78891b8	0x799f8e80
+	0xdbf4e604	0x89860862	0x04fb77db	0x0fb1bf13
+	0x3b1aa906	0xadaf9a45	0x48526bf7	0x09d8ffb3
+	0xce751581	0x00e35b8d	0x0549e629	0x6d3cc316
+	0x3d8f300a	0xdcd790b5	0xde1ca316	0x737d5f31
+	0x171b2646	0x4798a85d	0xea36f650	0xcf889098
+	0xe4ec65b8	0x944637d3	0x019c8103	0x5fbdc21c
+	0xa61ebe77	0x74ea95a5	0x258eb8d1	0xf8c8c4d6
+	0x9a1edc66	0x9118b309	0x639ae9b5	0xd0c40735
+	0xc6ddec32	0x36d26a75	0x86018c99	0xe8bf66df
+	0xf345dba0	0x780670a3	0xe34e60fd	0x733ad4ba
+	0x2ef04d54	0xb1b9c41f	0x84cca1c2	0xaa09279b
+	0x34797d41	0xb93d4c70	0x919ce970	0xd0d6ec5e
+	0xdc70cc95	0xd89f4680	0x458cfd33	0xc257784b
+	0x29ec9364	0x8e717417	0x6d9732df	0xa3658440
+	0x8574b5c6	0xa58ebb8c	0x81bc4dea	0x1f396663
+	0x361dfd98	0x20b35a46	0x886a7e4c	0x69f0a1c5
+	0xd0b7de5f	0xbbc08761	0xa1cef991	0x084a8ea2
+	0x4df68c5b	0xb84b4b2e	0xd4bf1770	0x94b4f7c7
+	0x9906a752	0x878c7f1f	0x385b5a5e	0x99147c87
+	0x97c54a35	0xbacb57d4	0xf85f9733	0xb5d2c83f
+	0x4405f9f5	0x020260b5	0x5c0a8556	0xb623ad79
+	0x8d42a6a3	0x35ae5806	0x2c28a60d	0xa0200ee8
+	0xed9e0ece	0xb7e0442a	0x1ddf0e2b	0x26ceec5d
+	0xda397b2c	0xb073d9a2	0x9d856bbd	0x06e35ca8
+	0x6296193e	0x292dee18	0xf5a9bd7a	0xb62fe73f
+	0x95a8775f	0x1efc0fd0	0xf3338af4	0x06ccbe78
+	0xafb3f669	0xd9f7fe16	0x09beed63	0xa2f0bb3e
+	0x02f5c52f	0x24aee650	0xf715039b	0x3f566d89
+	0xd575429b	0x9d40207d	0xa89c7de9	0xde5157f0
+	0xd79025ae	0x4259c4b6	0x61e86217	0x6d2e3273
+	0x57b5c99d	0xa18edb02	0xf5f314be	0xfa58bf5f
+	0x581e95bb	0x04967c03	0x9187d903	0xdaf34bc3
+	0xa18e49f0	0xb7973963	0x2984967f	0x7332f94f
+	0x57e5a8b5	0xe6e0a6f8	0xbc08c39f	0xc9e73ad8
+	0x0ea113d8	0xa9cfdb06	0xfda1ebbb	0x1a30e9f9
+	0x69a9029a	0x44b43320	0x04182d93	0x00220972
+	0xa7f984c5	0xb4eeae8a	0x11718517	0x06e70840
+	0xb3091fe5	0x099ccb1a	0xac3df88c	0xa8bd0ca3
+	0xa202bbc0	0x19979cf1	0x8656c385	0x139abf7b
+	0xae298ea4	0xab9481ae	0xe08e2c38	0x27967dab
+	0x1108054c	0x1ba0d3c5	0x8a0fb923	0x9c54f682
+	0x5f363a46	0xec564b34	0x8d53c918	0x47f39642
+	0x3fd68743	0x197f16cc	0x2b03d11c	0xcc574d53
+	0x8b2d1aa3	0xd403c5b0	0xce21d3a6	0x57c88abe
+	0x56d6b12b	0x204f9ac8	0xfd44c338	0x18417de6
+	0x5582f0bf	0x7ea9d04f	0x7bdee65d	0x9fe3f5b5
+	0xa14edd82	0x8301f6ba	0x24bc737a	0x5c6e71a8
+	0xdb0d7fc2	0x243b6e99	0x3941f113	0xcaaa3674
+	0x1b25b686	0xfb219a33	0x1b122757	0x27298223
+	0x44cbb8ad	0xed4e6ef9	0xae338c2d	0xa8d231ee
+	0x9bc2d8f3	0xcecd4d27	0xe8ba9908	0x9a106344
+	0xbdf27147	0x0c547009	0x46b16833	0xd89b0690
+	0x4b742f40	0x733d4cd5	0x1abb6f77	0x803f40df
+	0xf8d909bb	0x8fa6a921	0x08966531	0xdf093174
+	0xc7ee92c8	0x4272612d	0x149f8242	0xf8c07ec3
+	0x99259781	0x8bf3f9c0	0x09d6b679	0x19a1968f
+	0x735b197e	0xa98c913f	0x3e208a56	0x59b2b40b
+	0x0ed212ed	0xfc92d02a	0xe9b1b441	0x1429fc3c
+	0x8a6fb38c	0x6235d73e	0x82f5aca8	0x9ebb490a
+	0x718fed05	0xee355cdc	0xf34bbc8e	0xcfde74ac
+	0x5c267a70	0x30b66c7f	0x9a655781	0x1d354268
+	0xd0debf01	0x71798948	0x4542b707	0x66c02ecf
+	0x49763e11	0xa02f170b	0xbcf30ee9	0xba9bbfec
+	0x6d915d18	0xcadd484f	0x8eadbd10	0x91463818
+	0xe8add34f	0x55620c30	0x14d47fa5	0x63c2a25f
+	0x7213f2f4	0x6d96a516	0xf10f4ed1	0x9825aeac
+	0xe9ca9b8a	0x4bb0e2aa	0x957f8851	0x1a41de29
+	0xa0039e6c	0x3ec63393	0x66b6ac8a	0x2992d983
+	0x2d73caa4	0xb0ae06c2	0xa4008915	0x2ba7050d
+	0x6d9e01e6	0x908f316f	0x3f17dabb	0x8c86b0e3
+	0x89fcebf8	0xbada4307	0x0f6e9f6f	0x07f36992
+	0x1a82520e	0x728f11a9	0x418aa9b7	0xc57f51d7
+	0xcffa1cd0	0xf9f6d902	0xdf22329a	0x4ac48293
+	0x37326e23	0xbb39c187	0xc9086dfe	0x1347e4f8
+	0x7ae88ecb	0xc280a07f	0x7f0a6b0a	0x57cff37d
+	0x2dfd629d	0x5a8a444d	0x934bcafb	0x593b6a3a
+	0x9c62c1ca	0x0ecdb2dc	0xb4c2fd82	0x2c19c0ab
+	0x26acf079	0x71aa1041	0x8aeb2595	0xed90f704
+	0x7d68f5c5	0x624429d5	0xefd0d147	0xc8682f79
+	0xfe7e9cc0	0xaee6c970	0x33e9231e	0x4720df4d
+	0x6a3f6428	0x463b676f	0x71960ee6	0xc684d974
+	0x9f01a6d2	0x728cbec7	0x2e20d715	0x172a4a11
+	0x4153ad1e	0xb1f36e53	0xc277f818	0x94ac6d39
+	0x502f91d8	0x3028b1ee	0x48390347	0x45a8b5af
+	0x2cb8095f	0x063cbe4a	0x07a53b3b	0xcfd08c80
+	0x81679803	0x9fa4726a	0xa682f4c8	0x4d90e8bf
+	>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 60bd05afb6..936455b5e5 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -117,6 +117,7 @@
 				compatible = "intel,irq-router";
 				intel,pirq-config = "ibase";
 				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
 				intel,pirq-link = <8 8>;
 				intel,pirq-mask = <0xdee0>;
 				intel,pirq-routing = <
@@ -297,10 +298,10 @@
 
 	microcode {
 		update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
 		};
 		update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
 		};
 	};
 
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 5d601b3444..0d462a9c78 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -69,6 +69,8 @@
 			irq-router {
 				compatible = "intel,irq-router";
 				intel,pirq-config = "pci";
+				intel,actl-8bit;
+				intel,actl-addr = <0x44>;
 				intel,pirq-link = <0x60 8>;
 				intel,pirq-mask = <0x0e40>;
 				intel,pirq-routing = <
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
deleted file mode 100644
index 4872b92860..0000000000
--- a/arch/x86/include/asm/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * From coreboot
- *
- * Copyright (C) 2004 SUSE LINUX AG
- * Copyright (C) 2004 Nick Barker
- * Copyright (C) 2008-2009 coresystems GmbH
- * (Written by Stefan Reinauer <stepan@coresystems.de>)
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#ifndef __ASM_ACPI_H
-#define __ASM_ACPI_H
-
-#define RSDP_SIG		"RSD PTR "  /* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"U-BootAC"  /* Must be exactly 8 bytes long! */
-#define OEM_ID			"U-Boot"    /* Must be exactly 6 bytes long! */
-#define ASLC			"U-Bo"      /* Must be exactly 4 bytes long! */
-
-/* 0 = S0, 1 = S1 ...*/
-int acpi_get_slp_type(void);
-void apci_set_slp_type(int type);
-
-#endif
diff --git a/arch/x86/include/asm/acpi/debug.asl b/arch/x86/include/asm/acpi/debug.asl
new file mode 100644
index 0000000000..8e7b603ba0
--- /dev/null
+++ b/arch/x86/include/asm/acpi/debug.asl
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/debug.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* POST register region */
+OperationRegion(X80, SystemIO, 0x80, 1)
+Field(X80, ByteAcc, NoLock, Preserve)
+{
+	P80, 8
+}
+
+/* Legacy serial port register region */
+OperationRegion(CREG, SystemIO, 0x3F8, 8)
+Field(CREG, ByteAcc, NoLock, Preserve)
+{
+	CDAT, 8,
+	CDLM, 8,
+	    , 8,
+	CLCR, 8,
+	CMCR, 8,
+	CLSR, 8
+}
+
+/* DINI - Initialize the serial port to 115200 8-N-1 */
+Method(DINI)
+{
+	Store(0x83, CLCR)
+	Store(0x01, CDAT)	/* 115200 baud (low) */
+	Store(0x00, CDLM)	/* 115200 baud (high) */
+	Store(0x03, CLCR)	/* word=8 stop=1 parity=none */
+	Store(0x03, CMCR)	/* DTR=1 RTS=1 out1/2=Off loop=Off */
+	Store(0x00, CDLM)	/* turn off interrupts */
+}
+
+/* THRE - Wait for serial port transmitter holding register to go empty */
+Method(THRE)
+{
+	And(CLSR, 0x20, Local0)
+	While (LEqual(Local0, Zero)) {
+		And(CLSR, 0x20, Local0)
+	}
+}
+
+/* OUTX - Send a single raw character */
+Method(OUTX, 1)
+{
+	THRE()
+	Store(Arg0, CDAT)
+}
+
+/* OUTC - Send a single character, expanding LF into CR/LF */
+Method(OUTC, 1)
+{
+	If (LEqual(Arg0, 0x0a)) {
+		OUTX(0x0d)
+	}
+	OUTX(Arg0)
+}
+
+/* DBGN - Send a single hex nibble */
+Method(DBGN, 1)
+{
+	And(Arg0, 0x0f, Local0)
+	If (LLess(Local0, 10)) {
+		Add(Local0, 0x30, Local0)
+	} Else {
+		Add(Local0, 0x37, Local0)
+	}
+	OUTC(Local0)
+}
+
+/* DBGB - Send a hex byte */
+Method(DBGB, 1)
+{
+	ShiftRight(Arg0, 4, Local0)
+	DBGN(Local0)
+	DBGN(Arg0)
+}
+
+/* DBGW - Send a hex word */
+Method(DBGW, 1)
+{
+	ShiftRight(Arg0, 8, Local0)
+	DBGB(Local0)
+	DBGB(Arg0)
+}
+
+/* DBGD - Send a hex dword */
+Method(DBGD, 1)
+{
+	ShiftRight(Arg0, 16, Local0)
+	DBGW(Local0)
+	DBGW(Arg0)
+}
+
+/* Get a char from a string */
+Method(GETC, 2)
+{
+	CreateByteField(Arg0, Arg1, DBGC)
+	Return (DBGC)
+}
+
+/* DBGO - Send either a string or an integer */
+Method(DBGO, 1, Serialized)
+{
+	If (LEqual(ObjectType(Arg0), 1)) {
+		If (LGreater(Arg0, 0xffff)) {
+			DBGD(Arg0)
+		} Else {
+			If (LGreater(Arg0, 0xff)) {
+				DBGW(Arg0)
+			} Else {
+				DBGB(Arg0)
+			}
+		}
+	} Else {
+		Name(BDBG, Buffer(80) {})
+		Store(Arg0, BDBG)
+		Store(0, Local1)
+		While (One) {
+			Store(GETC(BDBG, Local1), Local0)
+			If (LEqual(Local0, 0)) {
+				Return (Zero)
+			}
+			OUTC(Local0)
+			Increment(Local1)
+		}
+	}
+
+	Return (Zero)
+}
diff --git a/arch/x86/include/asm/acpi/globutil.asl b/arch/x86/include/asm/acpi/globutil.asl
new file mode 100644
index 0000000000..46381b687e
--- /dev/null
+++ b/arch/x86/include/asm/acpi/globutil.asl
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/globutil.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Method(MIN, 2)
+{
+	If (LLess(Arg0, Arg1)) {
+		Return (Arg0)
+	} Else {
+		Return (Arg1)
+	}
+}
+
+Method(SLEN, 1)
+{
+	Store(Arg0, Local0)
+	Return (Sizeof(Local0))
+}
+
+Method(S2BF, 1, Serialized)
+{
+	Add(SLEN(Arg0), One, Local0)
+	Name(BUFF, Buffer(Local0) {})
+	Store(Arg0, BUFF)
+	Return (BUFF)
+}
+
+/*
+ * SCMP - Strong string compare
+ *
+ * Checks both length and content
+ */
+Method(SCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	Store(Zero, Local4)
+	Store(SLEN(Arg0), Local5)
+	Store(SLEN(Arg1), Local6)
+	Store(MIN(Local5, Local6), Local7)
+
+	While (LLess(Local4, Local7)) {
+		Store(Derefof(Index(Local0, Local4)), Local2)
+		Store(Derefof(Index(Local1, Local4)), Local3)
+		If (LGreater(Local2, Local3)) {
+			Return (One)
+		} Else {
+			If (LLess(Local2, Local3)) {
+				Return (Ones)
+			}
+		}
+		Increment(Local4)
+	}
+
+	If (LLess(Local4, Local5)) {
+		Return (One)
+	} Else {
+		If (LLess(Local4, Local6)) {
+			Return (Ones)
+		} Else {
+			Return (Zero)
+		}
+	}
+}
+
+/*
+ * WCMP - Weak string compare
+ *
+ * Checks to find Arg1 at beginning of Arg0.
+ * Fails if length(Arg0) < length(Arg1).
+ * Returns 0 on fail, 1 on pass.
+ */
+Method(WCMP, 2)
+{
+	Store(S2BF(Arg0), Local0)
+	Store(S2BF(Arg1), Local1)
+	If (LLess(SLEN(Arg0), SLEN(Arg1))) {
+		Return (Zero)
+	}
+	Store(Zero, Local2)
+	Store(SLEN(Arg1), Local3)
+
+	While (LLess(Local2, Local3)) {
+		If (LNotEqual(Derefof(Index(Local0, Local2)),
+			Derefof(Index(Local1, Local2)))) {
+			Return (Zero)
+		}
+		Increment(Local2)
+	}
+
+	Return (One)
+}
+
+/*
+ * I2BM - Returns Bit Map
+ *
+ * Arg0 = IRQ Number (0-15)
+ */
+Method(I2BM, 1)
+{
+	Store(0, Local0)
+	If (LNotEqual(Arg0, 0)) {
+		Store(1, Local1)
+		ShiftLeft(Local1, Arg0, Local0)
+	}
+
+	Return (Local0)
+}
diff --git a/arch/x86/include/asm/acpi/irq_helper.h b/arch/x86/include/asm/acpi/irq_helper.h
new file mode 100644
index 0000000000..f0b3a6bc0a
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irq_helper.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronics Engineering, LLC.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file intentionally gets included multiple times, to set pic and apic
+ * modes, so should not have guard statements added.
+ */
+
+/*
+ * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ
+ * routing for the platform being compiled.
+ *
+ * This method uses #defines in irqroute.h along with the macros contained
+ * in this file to generate an IRQ routing for each PCI device in the system.
+ */
+
+#undef PCI_DEV_PIRQ_ROUTES
+#undef PCI_DEV_PIRQ_ROUTE
+#undef ACPI_DEV_IRQ
+#undef PCIE_BRIDGE_DEV
+#undef RP_IRQ_ROUTES
+#undef ROOTPORT_METHODS
+#undef ROOTPORT_IRQ_ROUTES
+#undef RP_METHOD
+
+#if defined(PIC_MODE)
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## P, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+/* define as blank so ROOTPORT_METHODS only gets inserted once */
+#define ROOTPORT_METHODS(prefix_, dev_)
+
+#else /* defined(PIC_MODE) */
+
+#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \
+	Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ }
+
+#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \
+Name(prefix_ ## func_ ## A, Package() \
+{ \
+	ACPI_DEV_IRQ(0x0000, 0, a_), \
+	ACPI_DEV_IRQ(0x0000, 1, b_), \
+	ACPI_DEV_IRQ(0x0000, 2, c_), \
+	ACPI_DEV_IRQ(0x0000, 3, d_), \
+})
+
+#define ROOTPORT_METHODS(prefix_, dev_) \
+	RP_METHOD(prefix_, dev_, 0) \
+	RP_METHOD(prefix_, dev_, 1) \
+	RP_METHOD(prefix_, dev_, 2) \
+	RP_METHOD(prefix_, dev_, 3) \
+	RP_METHOD(prefix_, dev_, 4) \
+	RP_METHOD(prefix_, dev_, 5) \
+	RP_METHOD(prefix_, dev_, 6) \
+	RP_METHOD(prefix_, dev_, 7)
+
+#endif /* defined(PIC_MODE) */
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	ACPI_DEV_IRQ(dev_, 0, a_), \
+	ACPI_DEV_IRQ(dev_, 1, b_), \
+	ACPI_DEV_IRQ(dev_, 2, c_), \
+	ACPI_DEV_IRQ(dev_, 3, d_)
+
+#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \
+	ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	ROOTPORT_METHODS(prefix_, dev_)
+
+#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \
+	RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \
+	RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \
+	RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \
+	RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_)
+
+#define RP_METHOD(prefix_, dev_, func_)\
+Device (prefix_ ## 0 ## func_) \
+{ \
+	Name(_ADR, dev_ ## 000 ## func_) \
+	Name(_PRW, Package() { 0, 0 }) \
+	Method(_PRT) { \
+		If (PICM) { \
+			Return (prefix_ ## func_ ## A) \
+		} Else { \
+			Return (prefix_ ## func_ ## P) \
+		} \
+	} \
+}
+
+/* SoC specific PIRQ route configuration */
+#include <asm/arch/acpi/irqroute.h>
diff --git a/arch/x86/include/asm/acpi/irqlinks.asl b/arch/x86/include/asm/acpi/irqlinks.asl
new file mode 100644
index 0000000000..84c1e53c7d
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqlinks.asl
@@ -0,0 +1,486 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * Intel chipset PIRQ routing control ASL description
+ *
+ * The programming interface is common to most Intel chipsets. But the PRTx
+ * registers may be mapped to different blocks. Some chipsets map them to LPC
+ * device (00:1f:00) PCI configuration space (like TunnelCreek, Quark), while
+ * some newer Atom SoCs (like BayTrail, Braswell) map them to Intel Legacy
+ * Block (ILB) memory space.
+ *
+ * This file defines 8 PCI IRQ link devices which corresponds to 8 PIRQ lines
+ * PIRQ A/B/C/D/E/F/G/H. To incorperate this file, the PRTx registers must be
+ * defined somewhere else in the platform's ASL files.
+ */
+
+Device (LNKA)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 1)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTA)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTA */
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTA, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 2)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTB)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTB */
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTB, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 3)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTC)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTC */
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTC, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 4)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTD)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTD */
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTD, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 5)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTE)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTE */
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTE, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 6)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTF)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTF */
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTF, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 7)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTG)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTG */
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTG, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name(_HID, EISAID("PNP0C0F"))
+	Name(_UID, 8)
+
+	/* Disable method */
+	Method(_DIS, 0, Serialized)
+	{
+		Store(0x80, PRTH)
+	}
+
+	/* Possible Resource Settings for this Link */
+	Name(_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared) { 5, 6, 7, 10, 11, 12, 14, 15 }
+	})
+
+	/* Current Resource Settings for this link */
+	Method(_CRS, 0, Serialized)
+	{
+		Name(RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		/* Clear the WordField */
+		Store(Zero, IRQ0)
+
+		/* Set the bit from PRTH */
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	/* Set Resource Setting for this IRQ link */
+	Method(_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		/* Which bit is set? */
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	/* Status */
+	Method(_STA, 0, Serialized)
+	{
+		If (And(PRTH, 0x80)) {
+			Return (STA_DISABLED)
+		} Else {
+			Return (STA_INVISIBLE)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/acpi/irqroute.asl b/arch/x86/include/asm/acpi/irqroute.asl
new file mode 100644
index 0000000000..64d38207d9
--- /dev/null
+++ b/arch/x86/include/asm/acpi/irqroute.asl
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\PICM, 0)
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local APIC/IOAPIC configuration.
+ */
+Method(\_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice */
+	Store(Arg0, PICM)
+}
+
+/* PCI interrupt routing */
+Method(_PRT) {
+	If (PICM) {
+		Return (Package() {
+			#undef PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	} Else {
+		Return (Package() {
+			#define PIC_MODE
+			#include "irq_helper.h"
+			PCI_DEV_PIRQ_ROUTES
+		})
+	}
+
+}
+
+/* PCIe downstream ports interrupt routing */
+PCIE_BRIDGE_IRQ_ROUTES
+#undef PIC_MODE
+#include "irq_helper.h"
+PCIE_BRIDGE_IRQ_ROUTES
diff --git a/arch/x86/include/asm/acpi/statdef.asl b/arch/x86/include/asm/acpi/statdef.asl
new file mode 100644
index 0000000000..e8cff100fc
--- /dev/null
+++ b/arch/x86/include/asm/acpi/statdef.asl
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/arch/x86/acpi/statdef.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Status and notification definitions */
+
+#define STA_MISSING		0x00
+#define STA_PRESENT		0x01
+#define STA_ENABLED		0x03
+#define STA_DISABLED		0x09
+#define STA_INVISIBLE		0x0b
+#define STA_UNAVAILABLE		0x0d
+#define STA_VISIBLE		0x0f
+
+/* SMBus status codes */
+#define SMB_OK			0x00
+#define SMB_UNKNOWN_FAIL	0x07
+#define SMB_DEV_ADDR_NAK	0x10
+#define SMB_DEVICE_ERROR	0x11
+#define SMB_DEV_CMD_DENIED	0x12
+#define SMB_UNKNOWN_ERR		0x13
+#define SMB_DEV_ACC_DENIED	0x17
+#define SMB_TIMEOUT		0x18
+#define SMB_HST_UNSUPP_PROTOCOL	0x19
+#define SMB_BUSY		0x1a
+#define SMB_PKT_CHK_ERROR	0x1f
+
+/* Device Object Notification Values */
+#define NOTIFY_BUS_CHECK	0x00
+#define NOTIFY_DEVICE_CHECK	0x01
+#define NOTIFY_DEVICE_WAKE	0x02
+#define NOTIFY_EJECT_REQUEST	0x03
+#define NOTIFY_DEVICE_CHECK_JR	0x04
+#define NOTIFY_FREQUENCY_ERROR	0x05
+#define NOTIFY_BUS_MODE		0x06
+#define NOTIFY_POWER_FAULT	0x07
+#define NOTIFY_CAPABILITIES	0x08
+#define NOTIFY_PLD_CHECK	0x09
+#define NOTIFY_SLIT_UPDATE	0x0b
+#define NOTIFY_SRA_UPDATE	0x0d
+
+/* Battery Device Notification Values */
+#define NOTIFY_BAT_STATUSCHG	0x80
+#define NOTIFY_BAT_INFOCHG	0x81
+#define NOTIFY_BAT_MAINTDATA	0x82
+
+/* Power Source Object Notification Values */
+#define NOTIFY_PWR_STATUSCHG	0x80
+#define NOTIFY_PWR_INFOCHG	0x81
+
+/* Thermal Zone Object Notification Values */
+#define NOTIFY_TZ_STATUSCHG	0x80
+#define NOTIFY_TZ_TRIPPTCHG	0x81
+#define NOTIFY_TZ_DEVLISTCHG	0x82
+#define NOTIFY_TZ_RELTBLCHG	0x83
+
+/* Power Button Notification Values */
+#define NOTIFY_POWER_BUTTON	0x80
+
+/* Sleep Button Notification Values */
+#define NOTIFY_SLEEP_BUTTON	0x80
+
+/* Lid Notification Values */
+#define NOTIFY_LID_STATUSCHG	0x80
+
+/* Processor Device Notification Values */
+#define NOTIFY_CPU_PPCCHG	0x80
+#define NOTIFY_CPU_CSTATECHG	0x81
+#define NOTIFY_CPU_THROTLCHG	0x82
+
+/* User Presence Device Notification Values */
+#define NOTIFY_USR_PRESNCECHG	0x80
+
+/* Ambient Light Sensor Notification Values */
+#define NOTIFY_ALS_ILLUMCHG	0x80
+#define NOTIFY_ALS_COLORTMPCHG	0x81
+#define NOTIFY_ALS_RESPCHG	0x82
diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h
index 9856fa6c43..56aa282127 100644
--- a/arch/x86/include/asm/acpi_table.h
+++ b/arch/x86/include/asm/acpi_table.h
@@ -2,83 +2,19 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
 
-#include <common.h>
-#include <malloc.h>
-#include <asm/post.h>
-#include <linux/string.h>
-
-#define RSDP_SIG		"RSD PTR "	/* RSDT pointer signature */
-#define ACPI_TABLE_CREATOR	"UBOOT   "	/* Must be 8 bytes long! */
-#define OEM_ID			"UBOOT "	/* Must be 6 bytes long! */
-#define ASLC			"INTL"		/* Must be 4 bytes long! */
-
-#define OEM_REVISION	42
-#define ASL_COMPILER_REVISION	42
-
-/* IO ports to generate SMIs */
-#define APM_CNT			0xb2
-#define APM_CNT_CST_CONTROL	0x85
-#define APM_CNT_PST_CONTROL	0x80
-#define APM_CNT_ACPI_DISABLE	0x1e
-#define APM_CNT_ACPI_ENABLE	0xe1
-#define APM_CNT_MBI_UPDATE	0xeb
-#define APM_CNT_GNVS_UPDATE	0xea
-#define APM_CNT_FINALIZE	0xcb
-#define APM_CNT_LEGACY		0xcc
-#define APM_ST			0xb3
-
-/* Multiple Processor Interrupts */
-#define MP_IRQ_POLARITY_DEFAULT	0x0
-#define MP_IRQ_POLARITY_HIGH	0x1
-#define MP_IRQ_POLARITY_LOW	0x3
-#define MP_IRQ_POLARITY_MASK	0x3
-#define MP_IRQ_TRIGGER_DEFAULT	0x0
-#define MP_IRQ_TRIGGER_EDGE	0x4
-#define MP_IRQ_TRIGGER_LEVEL	0xc
-#define MP_IRQ_TRIGGER_MASK	0xc
-
-/*
- * Interrupt assigned for SCI in order to
- * create the ACPI MADT IRQ override entry
- */
-#define ACTL		0x00
-#define SCIS_MASK	0x07
-#define SCIS_IRQ9	0x00
-#define SCIS_IRQ10	0x01
-#define SCIS_IRQ11	0x02
-#define SCIS_IRQ20	0x04
-#define SCIS_IRQ21	0x05
-#define SCIS_IRQ22	0x06
-#define SCIS_IRQ23	0x07
-
-#define ACPI_REV_ACPI_1_0	1
-#define ACPI_REV_ACPI_2_0	1
-#define ACPI_REV_ACPI_3_0	2
-#define ACPI_REV_ACPI_4_0	3
-#define ACPI_REV_ACPI_5_0	5
+#define RSDP_SIG		"RSD PTR "	/* RSDP pointer signature */
+#define OEM_ID			"U-BOOT"	/* U-Boot */
+#define OEM_TABLE_ID		"U-BOOTBL"	/* U-Boot Table */
+#define ASLC_ID			"INTL"		/* Intel ASL Compiler */
 
 #define ACPI_RSDP_REV_ACPI_1_0	0
 #define ACPI_RSDP_REV_ACPI_2_0	2
 
-typedef struct acpi_gen_regaddr {
-	u8  space_id;	/* Address space ID */
-	u8  bit_width;	/* Register size in bits */
-	u8  bit_offset;	/* Register bit offset */
-	union {
-		/* Reserved in ACPI 2.0 - 2.0b */
-		u8  resv;
-		/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-		u8  access_size;
-	};
-	u32 addrl;	/* Register address, low 32 bits */
-	u32 addrh;	/* Register address, high 32 bits */
-} acpi_addr_t;
-
-
 /*
  * RSDP (Root System Description Pointer)
  * Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum
@@ -87,7 +23,7 @@ struct acpi_rsdp {
 	char signature[8];	/* RSDP signature */
 	u8 checksum;		/* Checksum of the first 20 bytes */
 	char oem_id[6];		/* OEM ID */
-	u8 revision;		/* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
+	u8 revision;		/* 0 for ACPI 1.0, others 2 */
 	u32 rsdt_address;	/* Physical address of RSDT (32 bits) */
 	u32 length;		/* Total RSDP length (incl. extended part) */
 	u64 xsdt_address;	/* Physical address of XSDT (64 bits) */
@@ -95,35 +31,8 @@ struct acpi_rsdp {
 	u8 reserved[3];
 };
 
-enum acpi_address_space_type {
-	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
-	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
-	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
-	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
-	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
-	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
-	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
-};
-
-/* functional fixed hardware */
-#define ACPI_FFIXEDHW_VENDOR_INTEL	1	/* Intel */
-#define ACPI_FFIXEDHW_CLASS_HLT		0	/* C1 Halt */
-#define ACPI_FFIXEDHW_CLASS_IO_HLT	1	/* C1 I/O then Halt */
-#define ACPI_FFIXEDHW_CLASS_MWAIT	2	/* MWAIT Native C-state */
-#define ACPI_FFIXEDHW_FLAG_HW_COORD	1	/* Hardware Coordination bit */
-#define ACPI_FFIXEDHW_FLAG_BM_STS	2	/* BM_STS avoidance bit */
-
-/* Access size definitions for Generic address structure */
-enum acpi_address_space_size {
-	ACPI_ACCESS_SIZE_UNDEFINED = 0,	/* Undefined (legacy reasons) */
-	ACPI_ACCESS_SIZE_BYTE_ACCESS = 1,
-	ACPI_ACCESS_SIZE_WORD_ACCESS = 2,
-	ACPI_ACCESS_SIZE_DWORD_ACCESS = 3,
-	ACPI_ACCESS_SIZE_QWORD_ACCESS = 4
-};
-
 /* Generic ACPI header, provided by (almost) all tables */
-typedef struct acpi_table_header {
+struct acpi_table_header {
 	char signature[4];	/* ACPI signature (4 ASCII characters) */
 	u32 length;		/* Table length in bytes (incl. header) */
 	u8 revision;		/* Table version (not ACPI version!) */
@@ -131,12 +40,12 @@ typedef struct acpi_table_header {
 	char oem_id[6];		/* OEM identification */
 	char oem_table_id[8];	/* OEM table identification */
 	u32 oem_revision;	/* OEM revision number */
-	char asl_compiler_id[4]; /* ASL compiler vendor ID */
-	u32 asl_compiler_revision; /* ASL compiler revision number */
-} acpi_header_t;
+	char aslc_id[4];	/* ASL compiler vendor ID */
+	u32 aslc_revision;	/* ASL compiler revision number */
+};
 
 /* A maximum number of 32 ACPI tables ought to be enough for now */
-#define MAX_ACPI_TABLES	32
+#define MAX_ACPI_TABLES		32
 
 /* RSDT (Root System Description Table) */
 struct acpi_rsdt {
@@ -150,103 +59,80 @@ struct acpi_xsdt {
 	u64 entry[MAX_ACPI_TABLES];
 };
 
-/* MCFG (PCI Express MMIO config space BAR description table) */
-struct acpi_mcfg {
-	struct acpi_table_header header;
-	u8 reserved[8];
-};
-
-struct acpi_mcfg_mmconfig {
-	u32 base_address;
-	u32 base_reserved;
-	u16 pci_segment_group_number;
-	u8 start_bus_number;
-	u8 end_bus_number;
-	u8 reserved[4];
-};
-
-/* MADT (Multiple APIC Description Table) */
-struct acpi_madt {
-	struct acpi_table_header header;
-	u32 lapic_addr;			/* Local APIC address */
-	u32 flags;			/* Multiple APIC flags */
-} acpi_madt_t;
-
-enum dev_scope_type {
-	SCOPE_PCI_ENDPOINT = 1,
-	SCOPE_PCI_SUB = 2,
-	SCOPE_IOAPIC = 3,
-	SCOPE_MSI_HPET = 4
+/* FADT Preferred Power Management Profile */
+enum acpi_pm_profile {
+	ACPI_PM_UNSPECIFIED = 0,
+	ACPI_PM_DESKTOP,
+	ACPI_PM_MOBILE,
+	ACPI_PM_WORKSTATION,
+	ACPI_PM_ENTERPRISE_SERVER,
+	ACPI_PM_SOHO_SERVER,
+	ACPI_PM_APPLIANCE_PC,
+	ACPI_PM_PERFORMANCE_SERVER,
+	ACPI_PM_TABLET
 };
 
-typedef struct dev_scope {
-	u8 type;
-	u8 length;
-	u8 reserved[2];
-	u8 enumeration;
-	u8 start_bus;
-	struct {
-		u8 dev;
-		u8 fn;
-	} path[0];
-} __packed dev_scope_t;
-
-/* MADT: APIC Structure Type*/
-enum acpi_apic_types {
-	LOCALAPIC	= 0,	/* Processor local APIC */
-	IOAPIC,			/* I/O APIC */
-	IRQSOURCEOVERRIDE,	/* Interrupt source override */
-	NMITYPE,		/* NMI source */
-	LOCALNMITYPE, 		/* Local APIC NMI */
-	LAPICADDRESSOVERRIDE,	/* Local APIC address override */
-	IOSAPIC,		/* I/O SAPIC */
-	LOCALSAPIC,		/* Local SAPIC */
-	PLATFORMIRQSOURCES,	/* Platform interrupt sources */
-	LOCALX2SAPIC,		/* Processor local x2APIC */
-	LOCALX2APICNMI,		/* Local x2APIC NMI */
-};
+/* FADT flags for p_lvl2_lat and p_lvl3_lat */
+#define ACPI_FADT_C2_NOT_SUPPORTED	101
+#define ACPI_FADT_C3_NOT_SUPPORTED	1001
 
-/* MADT: Processor Local APIC Structure */
-struct acpi_madt_lapic {
-	u8 type;		/* Type (0) */
-	u8 length;		/* Length in bytes (8) */
-	u8 processor_id;	/* ACPI processor ID */
-	u8 apic_id;		/* Local APIC ID */
-	u32 flags;		/* Local APIC flags */
-};
+/* FADT Boot Architecture Flags */
+#define ACPI_FADT_LEGACY_FREE		0x00
+#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
+#define ACPI_FADT_8042			(1 << 1)
+#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
+#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
+#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
 
-#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
-/* bits 1-31: reserved */
-#define PCAT_COMPAT		(1 << 0)
-/* bits 1-31: reserved */
+/* FADT Feature Flags */
+#define ACPI_FADT_WBINVD		(1 << 0)
+#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
+#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
+#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
+#define ACPI_FADT_POWER_BUTTON		(1 << 4)
+#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
+#define ACPI_FADT_FIXED_RTC		(1 << 6)
+#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
+#define ACPI_FADT_32BIT_TIMER		(1 << 8)
+#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
+#define ACPI_FADT_RESET_REGISTER	(1 << 10)
+#define ACPI_FADT_SEALED_CASE		(1 << 11)
+#define ACPI_FADT_HEADLESS		(1 << 12)
+#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
+#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
+#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
+#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
+#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
+#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
+#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
+#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
+#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
 
-/* MADT: Local APIC NMI Structure */
-struct acpi_madt_lapic_nmi {
-	u8 type;		/* Type (4) */
-	u8 length;		/* Length in bytes (6) */
-	u8 processor_id;	/* ACPI processor ID */
-	u16 flags;		/* MPS INTI flags */
-	u8 lint;		/* Local APIC LINT# */
+enum acpi_address_space_type {
+	ACPI_ADDRESS_SPACE_MEMORY = 0,	/* System memory */
+	ACPI_ADDRESS_SPACE_IO,		/* System I/O */
+	ACPI_ADDRESS_SPACE_PCI,		/* PCI config space */
+	ACPI_ADDRESS_SPACE_EC,		/* Embedded controller */
+	ACPI_ADDRESS_SPACE_SMBUS,	/* SMBus */
+	ACPI_ADDRESS_SPACE_PCC = 0x0a,	/* Platform Comm. Channel */
+	ACPI_ADDRESS_SPACE_FIXED = 0x7f	/* Functional fixed hardware */
 };
 
-/* MADT: I/O APIC Structure */
-struct acpi_madt_ioapic {
-	u8 type;		/* Type (1) */
-	u8 length;		/* Length in bytes (12) */
-	u8 ioapic_id;		/* I/O APIC ID */
-	u8 reserved;
-	u32 ioapic_addr;	/* I/O APIC address */
-	u32 gsi_base;		/* Global system interrupt base */
+enum acpi_address_space_size {
+	ACPI_ACCESS_SIZE_UNDEFINED = 0,
+	ACPI_ACCESS_SIZE_BYTE_ACCESS,
+	ACPI_ACCESS_SIZE_WORD_ACCESS,
+	ACPI_ACCESS_SIZE_DWORD_ACCESS,
+	ACPI_ACCESS_SIZE_QWORD_ACCESS
 };
 
-/* MADT: Interrupt Source Override Structure */
-struct acpi_madt_irqoverride {
-	u8 type;		/* Type (2) */
-	u8 length;		/* Length in bytes (10) */
-	u8 bus;			/* ISA (0) */
-	u8 source;		/* Bus-relative int. source (IRQ) */
-	u32 gsirq;		/* Global system interrupt */
-	u16 flags;		/* MPS INTI flags */
+struct acpi_gen_regaddr {
+	u8 space_id;	/* Address space ID */
+	u8 bit_width;	/* Register size in bits */
+	u8 bit_offset;	/* Register bit offset */
+	u8 access_size;	/* Access size */
+	u32 addrl;	/* Register address, low 32 bits */
+	u32 addrh;	/* Register address, high 32 bits */
 };
 
 /* FADT (Fixed ACPI Description Table) */
@@ -254,7 +140,7 @@ struct __packed acpi_fadt {
 	struct acpi_table_header header;
 	u32 firmware_ctrl;
 	u32 dsdt;
-	u8 model;
+	u8 res1;
 	u8 preferred_pm_profile;
 	u16 sci_int;
 	u32 smi_cmd;
@@ -309,85 +195,121 @@ struct __packed acpi_fadt {
 	struct acpi_gen_regaddr x_gpe1_blk;
 };
 
-/* Flags for p_lvl2_lat and p_lvl3_lat */
-#define ACPI_FADT_C2_NOT_SUPPORTED	101
-#define ACPI_FADT_C3_NOT_SUPPORTED	1001
+/* FACS flags */
+#define ACPI_FACS_S4BIOS_F	(1 << 0)
+#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
 
-/* FADT Feature Flags */
-#define ACPI_FADT_WBINVD		(1 << 0)
-#define ACPI_FADT_WBINVD_FLUSH		(1 << 1)
-#define ACPI_FADT_C1_SUPPORTED		(1 << 2)
-#define ACPI_FADT_C2_MP_SUPPORTED	(1 << 3)
-#define ACPI_FADT_POWER_BUTTON		(1 << 4)
-#define ACPI_FADT_SLEEP_BUTTON		(1 << 5)
-#define ACPI_FADT_FIXED_RTC		(1 << 6)
-#define ACPI_FADT_S4_RTC_WAKE		(1 << 7)
-#define ACPI_FADT_32BIT_TIMER		(1 << 8)
-#define ACPI_FADT_DOCKING_SUPPORTED	(1 << 9)
-#define ACPI_FADT_RESET_REGISTER	(1 << 10)
-#define ACPI_FADT_SEALED_CASE		(1 << 11)
-#define ACPI_FADT_HEADLESS		(1 << 12)
-#define ACPI_FADT_SLEEP_TYPE		(1 << 13)
-#define ACPI_FADT_PCI_EXPRESS_WAKE	(1 << 14)
-#define ACPI_FADT_PLATFORM_CLOCK	(1 << 15)
-#define ACPI_FADT_S4_RTC_VALID		(1 << 16)
-#define ACPI_FADT_REMOTE_POWER_ON	(1 << 17)
-#define ACPI_FADT_APIC_CLUSTER		(1 << 18)
-#define ACPI_FADT_APIC_PHYSICAL		(1 << 19)
-/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
-#define ACPI_FADT_HW_REDUCED_ACPI	(1 << 20)
-#define ACPI_FADT_LOW_PWR_IDLE_S0	(1 << 21)
-/* bits 22-31: reserved ACPI 5.0 */
+/* FACS (Firmware ACPI Control Structure) */
+struct acpi_facs {
+	char signature[4];		/* "FACS" */
+	u32 length;			/* Length in bytes (>= 64) */
+	u32 hardware_signature;		/* Hardware signature */
+	u32 firmware_waking_vector;	/* Firmware waking vector */
+	u32 global_lock;		/* Global lock */
+	u32 flags;			/* FACS flags */
+	u32 x_firmware_waking_vector_l;	/* X FW waking vector, low */
+	u32 x_firmware_waking_vector_h;	/* X FW waking vector, high */
+	u8 version;			/* Version 2 */
+	u8 res1[3];
+	u32 ospm_flags;			/* OSPM enabled flags */
+	u8 res2[24];
+};
 
-/* FADT Boot Architecture Flags */
-#define ACPI_FADT_LEGACY_DEVICES	(1 << 0)
-#define ACPI_FADT_8042			(1 << 1)
-#define ACPI_FADT_VGA_NOT_PRESENT	(1 << 2)
-#define ACPI_FADT_MSI_NOT_SUPPORTED	(1 << 3)
-#define ACPI_FADT_NO_PCIE_ASPM_CONTROL	(1 << 4)
-/* No legacy devices (including 8042) */
-#define ACPI_FADT_LEGACY_FREE		0x00
+/* MADT flags */
+#define ACPI_MADT_PCAT_COMPAT	(1 << 0)
 
-/* FADT Preferred Power Management Profile */
-#define PM_UNSPECIFIED		0
-#define PM_DESKTOP		1
-#define PM_MOBILE		2
-#define PM_WORKSTATION		3
-#define PM_ENTERPRISE_SERVER	4
-#define PM_SOHO_SERVER		5
-#define PM_APPLIANCE_PC		6
-#define PM_PERFORMANCE_SERVER	7
-#define PM_TABLET		8	/* ACPI 5.0 */
+/* MADT (Multiple APIC Description Table) */
+struct acpi_madt {
+	struct acpi_table_header header;
+	u32 lapic_addr;			/* Local APIC address */
+	u32 flags;			/* Multiple APIC flags */
+};
 
-/* FACS (Firmware ACPI Control Structure) */
-struct acpi_facs {
-	char signature[4];			/* "FACS" */
-	u32 length;				/* Length in bytes (>= 64) */
-	u32 hardware_signature;			/* Hardware signature */
-	u32 firmware_waking_vector;		/* Firmware waking vector */
-	u32 global_lock;			/* Global lock */
-	u32 flags;				/* FACS flags */
-	u32 x_firmware_waking_vector_l;		/* X FW waking vector, low */
-	u32 x_firmware_waking_vector_h;		/* X FW waking vector, high */
-	u8 version;				/* ACPI 4.0: 2 */
-	u8 resv[31];				/* FIXME: 4.0: ospm_flags */
+/* MADT: APIC Structure Type*/
+enum acpi_apic_types {
+	ACPI_APIC_LAPIC	= 0,		/* Processor local APIC */
+	ACPI_APIC_IOAPIC,		/* I/O APIC */
+	ACPI_APIC_IRQ_SRC_OVERRIDE,	/* Interrupt source override */
+	ACPI_APIC_NMI_SRC,		/* NMI source */
+	ACPI_APIC_LAPIC_NMI,		/* Local APIC NMI */
+	ACPI_APIC_LAPIC_ADDR_OVERRIDE,	/* Local APIC address override */
+	ACPI_APIC_IOSAPIC,		/* I/O SAPIC */
+	ACPI_APIC_LSAPIC,		/* Local SAPIC */
+	ACPI_APIC_PLATFORM_IRQ_SRC,	/* Platform interrupt sources */
+	ACPI_APIC_LX2APIC,		/* Processor local x2APIC */
+	ACPI_APIC_LX2APIC_NMI,		/* Local x2APIC NMI */
 };
 
-/* FACS flags */
-#define ACPI_FACS_S4BIOS_F	(1 << 0)
-#define ACPI_FACS_64BIT_WAKE_F	(1 << 1)
-/* Bits 31..2: reserved */
+/* MADT: Processor Local APIC Structure */
+
+#define LOCAL_APIC_FLAG_ENABLED	(1 << 0)
+
+struct acpi_madt_lapic {
+	u8 type;		/* Type (0) */
+	u8 length;		/* Length in bytes (8) */
+	u8 processor_id;	/* ACPI processor ID */
+	u8 apic_id;		/* Local APIC ID */
+	u32 flags;		/* Local APIC flags */
+};
+
+/* MADT: I/O APIC Structure */
+struct acpi_madt_ioapic {
+	u8 type;		/* Type (1) */
+	u8 length;		/* Length in bytes (12) */
+	u8 ioapic_id;		/* I/O APIC ID */
+	u8 reserved;
+	u32 ioapic_addr;	/* I/O APIC address */
+	u32 gsi_base;		/* Global system interrupt base */
+};
+
+/* MADT: Interrupt Source Override Structure */
+struct __packed acpi_madt_irqoverride {
+	u8 type;		/* Type (2) */
+	u8 length;		/* Length in bytes (10) */
+	u8 bus;			/* ISA (0) */
+	u8 source;		/* Bus-relative int. source (IRQ) */
+	u32 gsirq;		/* Global system interrupt */
+	u16 flags;		/* MPS INTI flags */
+};
+
+/* MADT: Local APIC NMI Structure */
+struct __packed acpi_madt_lapic_nmi {
+	u8 type;		/* Type (4) */
+	u8 length;		/* Length in bytes (6) */
+	u8 processor_id;	/* ACPI processor ID */
+	u16 flags;		/* MPS INTI flags */
+	u8 lint;		/* Local APIC LINT# */
+};
+
+/* MCFG (PCI Express MMIO config space BAR description table) */
+struct acpi_mcfg {
+	struct acpi_table_header header;
+	u8 reserved[8];
+};
+
+struct acpi_mcfg_mmconfig {
+	u32 base_address_l;
+	u32 base_address_h;
+	u16 pci_segment_group_number;
+	u8 start_bus_number;
+	u8 end_bus_number;
+	u8 reserved[4];
+};
+
+/* PM1_CNT bit defines */
+#define PM1_CNT_SCI_EN		(1 << 0)
 
 /* These can be used by the target port */
 
-unsigned long acpi_create_madt_lapics(unsigned long current);
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base);
-int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags);
-unsigned long acpi_fill_madt(unsigned long current);
+void acpi_fill_header(struct acpi_table_header *header, char *signature);
 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
-			 void *dsdt);
-int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu,
-			 u16 flags, u8 lint);
+		      void *dsdt);
+int acpi_create_madt_lapics(u32 current);
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base);
+int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
+				 u8 bus, u8 source, u32 gsirq, u16 flags);
+int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
+			       u8 cpu, u16 flags, u8 lint);
+u32 acpi_fill_madt(u32 current);
 u32 write_acpi_tables(u32 start);
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
new file mode 100644
index 0000000000..ef340f3d7b
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/gpio.asl
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/gpio.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* SouthCluster GPIO */
+Device (GPSC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 1)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* NorthCluster GPIO */
+Device (GPNC)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 2)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_NC_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
+
+/* SUS GPIO */
+Device (GPSS)
+{
+	Name(_HID, "INT33FC")
+	Name(_CID, "INT33FC")
+	Name(_UID, 3)
+
+	Name(RBUF, ResourceTemplate()
+	{
+		Memory32Fixed(ReadWrite, 0, 0x1000, RMEM)
+		Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , ,)
+		{
+			GPIO_SUS_IRQ
+		}
+	})
+
+	Method(_CRS)
+	{
+		CreateDwordField(^RBUF, ^RMEM._BAS, RBAS)
+		Add(IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS)
+		Return (^RBUF)
+	}
+
+	Method(_STA)
+	{
+		Return (STA_VISIBLE)
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
new file mode 100644
index 0000000000..d7463140f1
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SD_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(LPE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(HDA_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,	A, A, A, A), \
+	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,	A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,	A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, PCIE_DEV,	A, B, C, D)
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
new file mode 100644
index 0000000000..22f0d68f4d
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Scope (\)
+{
+	/* Intel Legacy Block */
+	OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+	Field(ILBS, AnyAcc, NoLock, Preserve) {
+		Offset (0x8),
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+		Offset (0x88),
+		    , 3,
+		UI3E, 1,
+		UI4E, 1
+	}
+}
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field(LPC0, AnyAcc, NoLock, Preserve) {
+		Offset(0x08),
+		SRID, 8,
+		Offset(0x80),
+		C1EN, 1,
+		Offset(0x84)
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Internal UART */
+	Device (IURT)
+	{
+		Name(_HID, EISAID("PNP0501"))
+		Name(_UID, 1)
+
+		Method(_STA, 0, Serialized)
+		{
+			/*
+			 * TODO:
+			 *
+			 * Need to hide the internal UART depending on whether
+			 * internal UART is enabled or not so that external
+			 * SuperIO UART can be exposed to system.
+			 */
+			Store(1, UI3E)
+			Store(1, UI4E)
+			Store(1, C1EN)
+			Return (STA_VISIBLE)
+
+		}
+
+		Method(_DIS, 0, Serialized)
+		{
+			Store(0, UI3E)
+			Store(0, UI4E)
+			Store(0, C1EN)
+		}
+
+		Method(_CRS, 0, Serialized)
+		{
+			Name(BUF0, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 3 }
+			})
+
+			Name(BUF1, ResourceTemplate()
+			{
+				IO(Decode16, 0x03f8, 0x03f8, 0x01, 0x08)
+				IRQNoFlags() { 4 }
+			})
+
+			If (LLessEqual(SRID, 0x04)) {
+				Return (BUF0)
+			} Else {
+				Return (BUF1)
+			}
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			/*
+			 * Disable as Windows doesn't like it, and systems
+			 * don't seem to use it
+			 */
+			/* IRQNoFlags() { 8 } */
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
new file mode 100644
index 0000000000..6bc82ecfe1
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+
+	/* ACPI devices */
+	#include "gpio.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
new file mode 100644
index 0000000000..eb5ae76186
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
new file mode 100644
index 0000000000..e89ff26f75
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
@@ -0,0 +1,211 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+
+		/* High PCI Memory Region */
+		QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , UMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value.
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		/* Update High PCI resource area */
+		CreateQwordField(MCRS, ^UMEM._MIN, UMIN)
+		CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
+		CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
+
+		/* Set base address to 48GB and allocate 16GB for PCI space */
+		Store(0xc00000000, UMIN)
+		Store(0x400000000, ULEN)
+		Add(UMIN, Subtract(ULEN, 1), UMAX)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+			Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+			Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* USB EHCI 0:1d.0 */
+	#include "usb.asl"
+
+	/* USB XHCI 0:14.0 */
+	#include "xhci.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
new file mode 100644
index 0000000000..311f471843
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* EHCI Controller 0:1d.0 */
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 4 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 2)
+
+	/* Highest D state in S4 state */
+	Name(_S4D, 2)
+
+	Device (HUB7)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device(PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device(PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device(PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device(PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
new file mode 100644
index 0000000000..a5a4404651
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* XHCI Controller 0:14.0 */
+
+Device (XHCI)
+{
+	Name(_ADR, 0x00140000)
+
+	/* Power Resources for Wake */
+	Name(_PRW, Package() { 13, 3 })
+
+	/* Highest D state in S3 state */
+	Name(_S3D, 3)
+
+	Device (RHUB)
+	{
+		Name(_ADR, 0x00000000)
+
+		Device (PRT1) { Name(_ADR, 1) }	/* USB Port 0 */
+		Device (PRT2) { Name(_ADR, 2) }	/* USB Port 1 */
+		Device (PRT3) { Name(_ADR, 3) }	/* USB Port 2 */
+		Device (PRT4) { Name(_ADR, 4) }	/* USB Port 3 */
+	}
+}
diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h
new file mode 100644
index 0000000000..798d35bccf
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/device.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DEVICE_H_
+#define _DEVICE_H_
+
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
+
+/* SoC transaction router */
+#define SOC_DEV		0x00
+
+/* Graphics and Display */
+#define GFX_DEV		0x02
+
+/* MIPI */
+#define MIPI_DEV	0x03
+
+/* EMMC Port */
+#define EMMC_DEV	0x10
+
+/* SDIO Port */
+#define SDIO_DEV	0x11
+
+/* SD Port */
+#define SD_DEV		0x12
+
+/* SATA */
+#define SATA_DEV	0x13
+
+/* xHCI */
+#define XHCI_DEV	0x14
+
+/* LPE Audio */
+#define LPE_DEV		0x15
+
+/* OTG */
+#define OTG_DEV		0x16
+
+/* MMC45 Port */
+#define MMC45_DEV	0x17
+
+/* Serial IO 1 */
+#define SIO1_DEV	0x18
+
+/* Trusted Execution Engine */
+#define TXE_DEV		0x1a
+
+/* HD Audio */
+#define HDA_DEV		0x1b
+
+/* PCIe Ports */
+#define PCIE_DEV	0x1c
+
+/* EHCI */
+#define EHCI_DEV	0x1d
+
+/* Serial IO 2 */
+#define SIO2_DEV	0x1e
+
+/* Platform Controller Unit */
+#define PCU_DEV		0x1f
+
+#endif /* _DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h
new file mode 100644
index 0000000000..62a91051e4
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/iomap.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IOMAP_H_
+#define _BAYTRAIL_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS		0xfd000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS		0xfeb00000
+#define ABORT_BASE_SIZE			0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS		0xfed01000
+#define SPI_BASE_SIZE			0x400
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS		0xfed03000
+#define PMC_BASE_SIZE			0x400
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS		0xfed05000
+#define PUNIT_BASE_SIZE			0x800
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS		0xfed08000
+#define ILB_BASE_SIZE			0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS			0xfed0c000
+#define  IO_BASE_OFFSET_GPSCORE		0x0000
+#define  IO_BASE_OFFSET_GPNCORE		0x1000
+#define  IO_BASE_OFFSET_GPSSUS		0x2000
+#define IO_BASE_SIZE			0x4000
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		0xfed1c000
+#define RCBA_BASE_SIZE			0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS		0xfef00000
+#define MPHY_BASE_SIZE			0x100000
+
+/* IO Port bases */
+#define ACPI_BASE_ADDRESS		0x0400
+#define ACPI_BASE_SIZE			0x80
+
+#define GPIO_BASE_ADDRESS		0x0500
+#define GPIO_BASE_SIZE			0x100
+
+#define SMBUS_BASE_ADDRESS		0xefa0
+
+#endif /* _BAYTRAIL_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h
new file mode 100644
index 0000000000..cd66f83c41
--- /dev/null
+++ b/arch/x86/include/asm/arch-baytrail/irq.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BAYTRAIL_IRQ_H_
+#define _BAYTRAIL_IRQ_H_
+
+#define PIRQA_APIC_IRQ			16
+#define PIRQB_APIC_IRQ			17
+#define PIRQC_APIC_IRQ			18
+#define PIRQD_APIC_IRQ			19
+#define PIRQE_APIC_IRQ			20
+#define PIRQF_APIC_IRQ			21
+#define PIRQG_APIC_IRQ			22
+#define PIRQH_APIC_IRQ			23
+
+/* The below IRQs are for when devices are in ACPI mode */
+#define LPE_DMA0_IRQ			24
+#define LPE_DMA1_IRQ			25
+#define LPE_SSP0_IRQ			26
+#define LPE_SSP1_IRQ			27
+#define LPE_SSP2_IRQ			28
+#define LPE_IPC2HOST_IRQ		29
+#define LPSS_I2C1_IRQ			32
+#define LPSS_I2C2_IRQ			33
+#define LPSS_I2C3_IRQ			34
+#define LPSS_I2C4_IRQ			35
+#define LPSS_I2C5_IRQ			36
+#define LPSS_I2C6_IRQ			37
+#define LPSS_I2C7_IRQ			38
+#define LPSS_HSUART1_IRQ		39
+#define LPSS_HSUART2_IRQ		40
+#define LPSS_SPI_IRQ			41
+#define LPSS_DMA1_IRQ			42
+#define LPSS_DMA2_IRQ			43
+#define SCC_EMMC_IRQ			44
+#define SCC_SDIO_IRQ			46
+#define SCC_SD_IRQ			47
+#define GPIO_NC_IRQ			48
+#define GPIO_SC_IRQ			49
+#define GPIO_SUS_IRQ			50
+/* GPIO direct / dedicated IRQs */
+#define GPIO_S0_DED_IRQ_0		51
+#define GPIO_S0_DED_IRQ_1		52
+#define GPIO_S0_DED_IRQ_2		53
+#define GPIO_S0_DED_IRQ_3		54
+#define GPIO_S0_DED_IRQ_4		55
+#define GPIO_S0_DED_IRQ_5		56
+#define GPIO_S0_DED_IRQ_6		57
+#define GPIO_S0_DED_IRQ_7		58
+#define GPIO_S0_DED_IRQ_8		59
+#define GPIO_S0_DED_IRQ_9		60
+#define GPIO_S0_DED_IRQ_10		61
+#define GPIO_S0_DED_IRQ_11		62
+#define GPIO_S0_DED_IRQ_12		63
+#define GPIO_S0_DED_IRQ_13		64
+#define GPIO_S0_DED_IRQ_14		65
+#define GPIO_S0_DED_IRQ_15		66
+#define GPIO_S5_DED_IRQ_0		67
+#define GPIO_S5_DED_IRQ_1		68
+#define GPIO_S5_DED_IRQ_2		69
+#define GPIO_S5_DED_IRQ_3		70
+#define GPIO_S5_DED_IRQ_4		71
+#define GPIO_S5_DED_IRQ_5		72
+#define GPIO_S5_DED_IRQ_6		73
+#define GPIO_S5_DED_IRQ_7		74
+#define GPIO_S5_DED_IRQ_8		75
+#define GPIO_S5_DED_IRQ_9		76
+#define GPIO_S5_DED_IRQ_10		77
+#define GPIO_S5_DED_IRQ_11		78
+#define GPIO_S5_DED_IRQ_12		79
+#define GPIO_S5_DED_IRQ_13		80
+#define GPIO_S5_DED_IRQ_14		81
+#define GPIO_S5_DED_IRQ_15		82
+/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
+#define _GPIO_S0_DED_IRQ(slot)		GPIO_S0_DED_IRQ_##slot
+#define _GPIO_S5_DED_IRQ(slot)		GPIO_S5_DED_IRQ_##slot
+#define GPIO_S0_DED_IRQ(slot)		_GPIO_S0_DED_IRQ(slot)
+#define GPIO_S5_DED_IRQ(slot)		_GPIO_S5_DED_IRQ(slot)
+
+#endif /* _BAYTRAIL_IRQ_H_ */
diff --git a/arch/x86/include/asm/arch-quark/acpi/irqroute.h b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
new file mode 100644
index 0000000000..5ba31da9ec
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/irqroute.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/device.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
+	PCI_DEV_PIRQ_ROUTE(QUARK_DEV_23, A, B, C, D)
+
+#define PCIE_BRIDGE_IRQ_ROUTES \
+	PCIE_BRIDGE_DEV(RP, QUARK_DEV_23, A, B, C, D)
diff --git a/arch/x86/include/asm/arch-quark/acpi/lpc.asl b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
new file mode 100644
index 0000000000..c3b0b1dbe4
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/lpc.asl
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Intel LPC Bus Device - 0:1f.0 */
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(PRTX, PCI_Config, 0x60, 8)
+	Field(PRTX, AnyAcc, NoLock, Preserve) {
+		PRTA, 8,
+		PRTB, 8,
+		PRTC, 8,
+		PRTD, 8,
+		PRTE, 8,
+		PRTF, 8,
+		PRTG, 8,
+		PRTH, 8,
+	}
+
+	#include <asm/acpi/irqlinks.asl>
+
+	/* Firmware Hub */
+	Device (FWH)
+	{
+		Name(_HID, EISAID("INT0800"))
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	/* 8259 Interrupt Controller */
+	Device (PIC)
+	{
+		Name(_HID, EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO(Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO(Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO(Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO(Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO(Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO(Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO(Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO(Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO(Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO(Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO(Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO(Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO(Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO(Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO(Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	/* 8254 timer */
+	Device (TIMR)
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO(Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() { 0 }
+		})
+	}
+
+	/* HPET */
+	Device (HPET)
+	{
+		Name(_HID, EISAID("PNP0103"))
+		Name(_CID, 0x010CD041)
+		Name(_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE)
+		})
+
+		Method(_STA)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* Real Time Clock */
+	Device (RTC)
+	{
+		Name(_HID, EISAID("PNP0B00"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x70, 0x70, 1, 8)
+			IRQNoFlags() { 8 }
+		})
+	}
+
+	/* LPC device: Resource consumption */
+	Device (LDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 2)
+
+		Name(RBUF, ResourceTemplate()
+		{
+			IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */
+			IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */
+			IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
+			IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */
+		})
+
+		Method(_CRS, 0, NotSerialized)
+		{
+			Return (RBUF)
+		}
+	}
+}
diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl
new file mode 100644
index 0000000000..bd72842dd6
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/acpi/statdef.asl>
+#include <asm/arch/iomap.h>
+#include <asm/arch/irq.h>
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0.
+ */
+Method(_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+Method(_WAK, 1)
+{
+	Return (Package() {0, 0})
+}
+
+/* TODO: add CPU ASL support */
+
+Scope (\_SB)
+{
+	#include "southcluster.asl"
+}
+
+/* Chipset specific sleep states */
+#include "sleepstates.asl"
diff --git a/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
new file mode 100644
index 0000000000..63c82fa123
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/sleepstates.asl
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0})
+Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0})
+Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0})
+Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0})
diff --git a/arch/x86/include/asm/arch-quark/acpi/southcluster.asl b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
new file mode 100644
index 0000000000..a89cfaf8af
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/acpi/southcluster.asl
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+Device (PCI0)
+{
+	Name(_HID, EISAID("PNP0A08"))	/* PCIe */
+	Name(_CID, EISAID("PNP0A03"))	/* PCI */
+
+	Name(_ADR, 0)
+	Name(_BBN, 0)
+
+	Name(MCRS, ResourceTemplate()
+	{
+		/* Bus Numbers */
+		WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
+
+		/* IO Region 0 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
+
+		/* PCI Config Space */
+		IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		/* IO Region 1 */
+		WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
+
+		/* VGA memory (0xa0000-0xbffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000, , , ASEG)
+
+		/* OPROM reserved (0xc0000-0xc3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000, , , OPR0)
+
+		/* OPROM reserved (0xc4000-0xc7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000, , , OPR1)
+
+		/* OPROM reserved (0xc8000-0xcbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000, , , OPR2)
+
+		/* OPROM reserved (0xcc000-0xcffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000, , , OPR3)
+
+		/* OPROM reserved (0xd0000-0xd3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000, , , OPR4)
+
+		/* OPROM reserved (0xd4000-0xd7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000, , , OPR5)
+
+		/* OPROM reserved (0xd8000-0xdbfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000, , , OPR6)
+
+		/* OPROM reserved (0xdc000-0xdffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000, , , OPR7)
+
+		/* BIOS Extension (0xe0000-0xe3fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000, , , ESG0)
+
+		/* BIOS Extension (0xe4000-0xe7fff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000, , , ESG1)
+
+		/* BIOS Extension (0xe8000-0xebfff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000, , , ESG2)
+
+		/* BIOS Extension (0xec000-0xeffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000, , , ESG3)
+
+		/* System BIOS (0xf0000-0xfffff) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000, , , FSEG)
+
+		/* PCI Memory Region (TOLM-CONFIG_MMCONF_BASE_ADDRESS) */
+		DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000, , , PMEM)
+	})
+
+	Method(_CRS, 0, Serialized)
+	{
+		/* Update PCI resource area */
+		CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+		CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+		CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+		/*
+		 * Hardcode TOLM to 2GB for now (see DRAM_MAX_SIZE in quark.h)
+		 *
+		 * TODO: for generic usage, read TOLM value from register, or
+		 * from global NVS (not implemented by U-Boot yet).
+		 */
+		Store(0x80000000, PMIN)
+		Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX)
+		Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+		Return (MCRS)
+	}
+
+	/* Device Resource Consumption */
+	Device (PDRC)
+	{
+		Name(_HID, EISAID("PNP0C02"))
+		Name(_UID, 1)
+
+		Name(PDRS, ResourceTemplate() {
+			Memory32Fixed(ReadWrite, CONFIG_ESRAM_BASE, 0x80000)
+			Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+			Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+			IO(Decode16, SPI_DMA_BASE_ADDRESS, SPI_DMA_BASE_ADDRESS, 0x0010, SPI_DMA_BASE_SIZE)
+			IO(Decode16, GPIO_BASE_ADDRESS, GPIO_BASE_ADDRESS, 0x0080, GPIO_BASE_SIZE)
+			IO(Decode16, WDT_BASE_ADDRESS, WDT_BASE_ADDRESS, 0x0040, WDT_BASE_SIZE)
+		})
+
+		/* Current Resource Settings */
+		Method(_CRS, 0, Serialized)
+		{
+			Return (PDRS)
+		}
+	}
+
+	Method(_OSC, 4)
+	{
+		/* Check for proper GUID */
+		If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+			/* Let OS control everything */
+			Return (Arg3)
+		} Else {
+			/* Unrecognized UUID */
+			CreateDWordField(Arg3, 0, CDW1)
+			Or(CDW1, 4, CDW1)
+			Return (Arg3)
+		}
+	}
+
+	/* LPC Bridge 0:1f.0 */
+	#include "lpc.asl"
+
+	/* IRQ routing for each PCI device */
+	#include <asm/acpi/irqroute.asl>
+}
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 7882f339f0..4760aa2f7f 100644
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -7,12 +7,17 @@
 #ifndef _QUARK_DEVICE_H_
 #define _QUARK_DEVICE_H_
 
-#include <pci.h>
+/*
+ * Internal PCI device numbers within the SoC.
+ *
+ * Note it must start with 0x_ prefix, as the device number macro will be
+ * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
+ */
 
-#define QUARK_HOST_BRIDGE_DEV	0
+#define QUARK_HOST_BRIDGE_DEV	0x00
 #define QUARK_HOST_BRIDGE_FUNC	0
 
-#define QUARK_DEV_20		20
+#define QUARK_DEV_20		0x14
 #define QUARK_MMC_SDIO_FUNC	0
 #define QUARK_UART0_FUNC	1
 #define QUARK_USB_DEVICE_FUNC	2
@@ -22,18 +27,21 @@
 #define QUARK_EMAC0_FUNC	6
 #define QUARK_EMAC1_FUNC	7
 
-#define QUARK_DEV_21		21
+#define QUARK_DEV_21		0x15
 #define QUARK_SPI0_FUNC		0
 #define QUARK_SPI1_FUNC		1
 #define QUARK_I2C_GPIO_FUNC	2
 
-#define QUARK_DEV_23		23
+#define QUARK_DEV_23		0x17
 #define QUARK_PCIE0_FUNC	0
 #define QUARK_PCIE1_FUNC	1
 
-#define QUARK_LGC_BRIDGE_DEV	31
+#define QUARK_LGC_BRIDGE_DEV	0x1f
 #define QUARK_LGC_BRIDGE_FUNC	0
 
+#ifndef __ASSEMBLY__
+#include <pci.h>
+
 #define QUARK_HOST_BRIDGE	\
 	PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
 #define QUARK_MMC_SDIO		\
@@ -64,5 +72,6 @@
 	PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
 #define QUARK_LEGACY_BRIDGE	\
 	PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
+#endif /* __ASSEMBLY__ */
 
 #endif /* _QUARK_DEVICE_H_ */
diff --git a/arch/x86/include/asm/arch-quark/iomap.h b/arch/x86/include/asm/arch-quark/iomap.h
new file mode 100644
index 0000000000..fd1ef987d7
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/iomap.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IOMAP_H_
+#define _QUARK_IOMAP_H_
+
+/* Memory Mapped IO bases */
+
+/* ESRAM */
+#define ESRAM_BASE_ADDRESS		CONFIG_ESRAM_BASE
+#define ESRAM_BASE_SIZE			ESRAM_SIZE
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS		CONFIG_PCIE_ECAM_BASE
+#define MCFG_BASE_SIZE			0x10000000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS		0xfed00000
+#define HPET_BASE_SIZE			0x400
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS		CONFIG_RCBA_BASE
+#define RCBA_BASE_SIZE			0x4000
+
+/* IO Port bases */
+#define ACPI_PM1_BASE_ADDRESS		CONFIG_ACPI_PM1_BASE
+#define ACPI_PM1_BASE_SIZE		0x10
+
+#define ACPI_PBLK_BASE_ADDRESS		CONFIG_ACPI_PBLK_BASE
+#define ACPI_PBLK_BASE_SIZE		0x10
+
+#define SPI_DMA_BASE_ADDRESS		CONFIG_SPI_DMA_BASE
+#define SPI_DMA_BASE_SIZE		0x10
+
+#define GPIO_BASE_ADDRESS		CONFIG_GPIO_BASE
+#define GPIO_BASE_SIZE			0x80
+
+#define ACPI_GPE0_BASE_ADDRESS		CONFIG_ACPI_GPE0_BASE
+#define ACPI_GPE0_BASE_SIZE		0x40
+
+#define WDT_BASE_ADDRESS		CONFIG_WDT_BASE
+#define WDT_BASE_SIZE			0x40
+
+#endif /* _QUARK_IOMAP_H_ */
diff --git a/arch/x86/include/asm/arch-quark/irq.h b/arch/x86/include/asm/arch-quark/irq.h
new file mode 100644
index 0000000000..21e68307f8
--- /dev/null
+++ b/arch/x86/include/asm/arch-quark/irq.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _QUARK_IRQ_H_
+#define _QUARK_IRQ_H_
+
+#define PIRQA_APIC_IRQ	16
+#define PIRQB_APIC_IRQ	17
+#define PIRQC_APIC_IRQ	18
+#define PIRQD_APIC_IRQ	19
+#define PIRQE_APIC_IRQ	20
+#define PIRQF_APIC_IRQ	21
+#define PIRQG_APIC_IRQ	22
+#define PIRQH_APIC_IRQ	23
+
+#endif /* _QUARK_IRQ_H_ */
diff --git a/arch/x86/include/asm/coreboot_tables.h b/arch/x86/include/asm/coreboot_tables.h
index 15ccf9be6c..e036f744f6 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -295,6 +295,25 @@ struct cbmem_entry {
 #define CBMEM_ID_NONE			0x00000000
 
 /**
+ * high_table_reserve() - reserve configuration table in high memory
+ *
+ * This reserves configuration table in high memory.
+ *
+ * @return:	always 0
+ */
+int high_table_reserve(void);
+
+/**
+ * high_table_malloc() - allocate configuration table in high memory
+ *
+ * This allocates configuration table in high memory.
+ *
+ * @bytes:	size of configuration table to be allocated
+ * @return:	pointer to configuration table in high memory
+ */
+void *high_table_malloc(size_t bytes);
+
+/**
  * write_coreboot_table() - write coreboot table
  *
  * This writes coreboot table at a given address.
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 3bc2ac24cf..7434f779b6 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -93,6 +93,10 @@ struct arch_global_data {
 	char *mrc_output;
 	unsigned int mrc_output_len;
 	ulong table;			/* Table pointer from previous loader */
+#ifdef CONFIG_SEABIOS
+	u32 high_table_ptr;
+	u32 high_table_limit;
+#endif
 };
 
 #endif
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 5b9e673763..ddb529e581 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -34,6 +34,8 @@ enum pirq_config {
  *		IRQ N is available to be routed
  * @lb_bdf:	irq router's PCI bus/device/function number encoding
  * @ibase:	IBASE register block base address
+ * @actl_8bit:	ACTL register width is 8-bit (for ICH series chipset)
+ * @actl_addr:	ACTL register offset
  */
 struct irq_router {
 	int config;
@@ -41,6 +43,8 @@ struct irq_router {
 	u16 irq_mask;
 	u32 bdf;
 	u32 ibase;
+	bool actl_8bit;
+	int actl_addr;
 };
 
 struct pirq_routing {
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index dc90df2050..e17f0bb0f2 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -10,7 +10,7 @@ obj-y += bios_asm.o
 obj-y += bios_interrupts.o
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-y	+= cmd_boot.o
-obj-y	+= coreboot_table.o
+obj-$(CONFIG_SEABIOS) += coreboot_table.o
 obj-$(CONFIG_EFI) += efi/
 obj-y	+= e820.o
 obj-y	+= gcc.o
@@ -31,7 +31,7 @@ obj-$(CONFIG_X86_RAMTEST) += ramtest.o
 obj-y += sfi.o
 obj-$(CONFIG_GENERATE_SMBIOS_TABLE) += smbios.o
 obj-y	+= string.o
-ifndef CONFIG_QEMU_ACPI_TABLE
+ifndef CONFIG_QEMU
 obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o
 endif
 obj-y	+= tables.o
diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c
index 790f6fbd0f..ffb4678e51 100644
--- a/arch/x86/lib/acpi_table.c
+++ b/arch/x86/lib/acpi_table.c
@@ -2,6 +2,7 @@
  * Based on acpi.c from coreboot
  *
  * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -10,25 +11,92 @@
 #include <cpu.h>
 #include <dm.h>
 #include <dm/uclass-internal.h>
-#include <dm/lists.h>
 #include <asm/acpi_table.h>
-#include <asm/cpu.h>
-#include <asm/ioapic.h>
+#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/tables.h>
-#include <asm/pci.h>
 
 /*
- * IASL compiles the dsdt entries and
- * writes the hex values to AmlCode array.
- * CamelCase cannot be handled here.
+ * IASL compiles the dsdt entries and writes the hex values
+ * to a C array AmlCode[] (see dsdt.c).
  */
 extern const unsigned char AmlCode[];
 
+static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
+			    struct acpi_xsdt *xsdt)
+{
+	memset(rsdp, 0, sizeof(struct acpi_rsdp));
+
+	memcpy(rsdp->signature, RSDP_SIG, 8);
+	memcpy(rsdp->oem_id, OEM_ID, 6);
+
+	rsdp->length = sizeof(struct acpi_rsdp);
+	rsdp->rsdt_address = (u32)rsdt;
+
+	/*
+	 * Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
+	 *
+	 * Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
+	 * If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
+	 * revision 0)
+	 */
+	if (xsdt == NULL) {
+		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
+	} else {
+		rsdp->xsdt_address = (u64)(u32)xsdt;
+		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
+	}
+
+	/* Calculate checksums */
+	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
+	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
+			sizeof(struct acpi_rsdp));
+}
+
+void acpi_fill_header(struct acpi_table_header *header, char *signature)
+{
+	memcpy(header->signature, signature, 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, OEM_TABLE_ID, 8);
+	memcpy(header->aslc_id, ASLC_ID, 4);
+}
+
+static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
+{
+	struct acpi_table_header *header = &(rsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "RSDT");
+	header->length = sizeof(struct acpi_rsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)rsdt,
+			sizeof(struct acpi_rsdt));
+}
+
+static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+{
+	struct acpi_table_header *header = &(xsdt->header);
+
+	/* Fill out header fields */
+	acpi_fill_header(header, "XSDT");
+	header->length = sizeof(struct acpi_xsdt);
+	header->revision = 1;
+
+	/* Entries are filled in later, we come with an empty set */
+
+	/* Fix checksum */
+	header->checksum = table_compute_checksum((void *)xsdt,
+			sizeof(struct acpi_xsdt));
+}
+
 /**
-* Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
-* and checksum.
-*/
+ * Add an ACPI table to the RSDT (and XSDT) structure, recalculate length
+ * and checksum.
+ */
 static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 {
 	int i, entries_num;
@@ -50,7 +118,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 
 	if (i >= entries_num) {
-		debug("ACPI: Error: too many tables.\n");
+		debug("ACPI: Error: too many tables\n");
 		return;
 	}
 
@@ -58,12 +126,13 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	rsdt->entry[i] = (u32)table;
 
 	/* Fix RSDT length or the kernel will assume invalid entries */
-	rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1));
+	rsdt->header.length = sizeof(struct acpi_table_header) +
+				(sizeof(u32) * (i + 1));
 
 	/* Re-calculate checksum */
 	rsdt->header.checksum = 0;
 	rsdt->header.checksum = table_compute_checksum((u8 *)rsdt,
-						       rsdt->header.length);
+			rsdt->header.length);
 
 	/*
 	 * And now the same thing for the XSDT. We use the same index as for
@@ -74,8 +143,8 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 		xsdt->entry[i] = (u64)(u32)table;
 
 		/* Fix XSDT length */
-		xsdt->header.length = sizeof(acpi_header_t) +
-			 (sizeof(u64) * (i + 1));
+		xsdt->header.length = sizeof(struct acpi_table_header) +
+			(sizeof(u64) * (i + 1));
 
 		/* Re-calculate checksum */
 		xsdt->header.checksum = 0;
@@ -84,38 +153,56 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table)
 	}
 }
 
+static void acpi_create_facs(struct acpi_facs *facs)
+{
+	memset((void *)facs, 0, sizeof(struct acpi_facs));
+
+	memcpy(facs->signature, "FACS", 4);
+	facs->length = sizeof(struct acpi_facs);
+	facs->hardware_signature = 0;
+	facs->firmware_waking_vector = 0;
+	facs->global_lock = 0;
+	facs->flags = 0;
+	facs->x_firmware_waking_vector_l = 0;
+	facs->x_firmware_waking_vector_h = 0;
+	facs->version = 1;
+}
+
 static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic,
-			 u8 cpu, u8 apic)
+				  u8 cpu, u8 apic)
 {
-	lapic->type = LOCALAPIC; /* Local APIC structure */
+	lapic->type = ACPI_APIC_LAPIC;
 	lapic->length = sizeof(struct acpi_madt_lapic);
-	lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */
+	lapic->flags = LOCAL_APIC_FLAG_ENABLED;
 	lapic->processor_id = cpu;
 	lapic->apic_id = apic;
 
 	return lapic->length;
 }
 
-unsigned long acpi_create_madt_lapics(unsigned long current)
+int acpi_create_madt_lapics(u32 current)
 {
 	struct udevice *dev;
+	int length = 0;
 
 	for (uclass_find_first_device(UCLASS_CPU, &dev);
 	     dev;
 	     uclass_find_next_device(&dev)) {
 		struct cpu_platdata *plat = dev_get_parent_platdata(dev);
 
-		current += acpi_create_madt_lapic(
+		length += acpi_create_madt_lapic(
 			(struct acpi_madt_lapic *)current,
 			plat->cpu_id, plat->cpu_id);
-		}
-		return current;
+		current += length;
+	}
+
+	return length;
 }
 
-int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
-			 u32 gsi_base)
+int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id,
+			    u32 addr, u32 gsi_base)
 {
-	ioapic->type = IOAPIC;
+	ioapic->type = ACPI_APIC_IOAPIC;
 	ioapic->length = sizeof(struct acpi_madt_ioapic);
 	ioapic->reserved = 0x00;
 	ioapic->gsi_base = gsi_base;
@@ -126,9 +213,9 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr,
 }
 
 int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
-			 u8 bus, u8 source, u32 gsirq, u16 flags)
+				 u8 bus, u8 source, u32 gsirq, u16 flags)
 {
-	irqoverride->type = IRQSOURCEOVERRIDE;
+	irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE;
 	irqoverride->length = sizeof(struct acpi_madt_irqoverride);
 	irqoverride->bus = bus;
 	irqoverride->source = source;
@@ -139,9 +226,9 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride,
 }
 
 int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
-			 u8 cpu, u16 flags, u8 lint)
+			       u8 cpu, u16 flags, u8 lint)
 {
-	lapic_nmi->type = LOCALNMITYPE;
+	lapic_nmi->type = ACPI_APIC_LAPIC_NMI;
 	lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi);
 	lapic_nmi->flags = flags;
 	lapic_nmi->processor_id = cpu;
@@ -150,45 +237,35 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi,
 	return lapic_nmi->length;
 }
 
-static void fill_header(acpi_header_t *header, char *signature, int length)
-{
-	memcpy(header->signature, signature, length);
-	memcpy(header->oem_id, OEM_ID, 6);
-	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
-	memcpy(header->asl_compiler_id, ASLC, 4);
-}
-
 static void acpi_create_madt(struct acpi_madt *madt)
 {
-	acpi_header_t *header = &(madt->header);
-	unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);
+	struct acpi_table_header *header = &(madt->header);
+	u32 current = (u32)madt + sizeof(struct acpi_madt);
 
 	memset((void *)madt, 0, sizeof(struct acpi_madt));
 
 	/* Fill out header fields */
-	fill_header(header, "APIC", 4);
+	acpi_fill_header(header, "APIC");
 	header->length = sizeof(struct acpi_madt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 4;
 
 	madt->lapic_addr = LAPIC_DEFAULT_BASE;
-	madt->flags = PCAT_COMPAT;
+	madt->flags = ACPI_MADT_PCAT_COMPAT;
 
 	current = acpi_fill_madt(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)madt;
+	header->length = current - (u32)madt;
 
 	header->checksum = table_compute_checksum((void *)madt, header->length);
 }
 
 static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
-			 u32 base, u16 seg_nr, u8 start, u8 end)
+				     u32 base, u16 seg_nr, u8 start, u8 end)
 {
 	memset(mmconfig, 0, sizeof(*mmconfig));
-	mmconfig->base_address = base;
-	mmconfig->base_reserved = 0;
+	mmconfig->base_address_l = base;
+	mmconfig->base_address_h = 0;
 	mmconfig->pci_segment_group_number = seg_nr;
 	mmconfig->start_bus_number = start;
 	mmconfig->end_bus_number = end;
@@ -196,11 +273,11 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig,
 	return sizeof(struct acpi_mcfg_mmconfig);
 }
 
-static unsigned long acpi_fill_mcfg(unsigned long current)
+static u32 acpi_fill_mcfg(u32 current)
 {
 	current += acpi_create_mcfg_mmconfig
 		((struct acpi_mcfg_mmconfig *)current,
-		 CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
+		CONFIG_PCIE_ECAM_BASE, 0x0, 0x0, 255);
 
 	return current;
 }
@@ -208,132 +285,45 @@ static unsigned long acpi_fill_mcfg(unsigned long current)
 /* MCFG is defined in the PCI Firmware Specification 3.0 */
 static void acpi_create_mcfg(struct acpi_mcfg *mcfg)
 {
-	acpi_header_t *header = &(mcfg->header);
-	unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);
+	struct acpi_table_header *header = &(mcfg->header);
+	u32 current = (u32)mcfg + sizeof(struct acpi_mcfg);
 
 	memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));
 
 	/* Fill out header fields */
-	fill_header(header, "MCFG", 4);
+	acpi_fill_header(header, "MCFG");
 	header->length = sizeof(struct acpi_mcfg);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
+	header->revision = 1;
 
 	current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum */
-	header->length = current - (unsigned long)mcfg;
+	header->length = current - (u32)mcfg;
 	header->checksum = table_compute_checksum((void *)mcfg, header->length);
 }
 
-static void acpi_create_facs(struct acpi_facs *facs)
-{
-	memset((void *)facs, 0, sizeof(struct acpi_facs));
-
-	memcpy(facs->signature, "FACS", 4);
-	facs->length = sizeof(struct acpi_facs);
-	facs->hardware_signature = 0;
-	facs->firmware_waking_vector = 0;
-	facs->global_lock = 0;
-	facs->flags = 0;
-	facs->x_firmware_waking_vector_l = 0;
-	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
-}
-
-static void acpi_write_rsdt(struct acpi_rsdt *rsdt)
-{
-	acpi_header_t *header = &(rsdt->header);
-
-	/* Fill out header fields */
-	fill_header(header, "RSDT", 4);
-	header->length = sizeof(struct acpi_rsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)rsdt,
-			sizeof(struct acpi_rsdt));
-}
-
-static void acpi_write_xsdt(struct acpi_xsdt *xsdt)
+static void enter_acpi_mode(int pm1_cnt)
 {
-	acpi_header_t *header = &(xsdt->header);
-
-	/* Fill out header fields */
-	fill_header(header, "XSDT", 4);
-	header->length = sizeof(struct acpi_xsdt);
-
-	/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
-	header->revision = ACPI_REV_ACPI_2_0;
-
-	/* Entries are filled in later, we come with an empty set */
-
-	/* Fix checksum */
-	header->checksum = table_compute_checksum((void *)xsdt,
-			sizeof(struct acpi_xsdt));
-}
-
-static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt,
-			 struct acpi_xsdt *xsdt)
-{
-	memset(rsdp, 0, sizeof(struct acpi_rsdp));
-
-	memcpy(rsdp->signature, RSDP_SIG, 8);
-	memcpy(rsdp->oem_id, OEM_ID, 6);
-
-	rsdp->length = sizeof(struct acpi_rsdp);
-	rsdp->rsdt_address = (u32)rsdt;
-
 	/*
-	* Revision: ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2
-	*
-	* Some OSes expect an XSDT to be present for RSD PTR revisions >= 2.
-	* If we don't have an ACPI XSDT, force ACPI 1.0 (and thus RSD PTR
-	* revision 0)
-	*/
-	if (xsdt == NULL) {
-		rsdp->revision = ACPI_RSDP_REV_ACPI_1_0;
-	} else {
-		rsdp->xsdt_address = (u64)(u32)xsdt;
-		rsdp->revision = ACPI_RSDP_REV_ACPI_2_0;
-	}
-
-	/* Calculate checksums */
-	rsdp->checksum = table_compute_checksum((void *)rsdp, 20);
-	rsdp->ext_checksum = table_compute_checksum((void *)rsdp,
-			sizeof(struct acpi_rsdp));
-}
-
-static void acpi_create_ssdt_generator(acpi_header_t *ssdt,
-			 const char *oem_table_id)
-{
-	unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
-
-	memset((void *)ssdt, 0, sizeof(acpi_header_t));
-
-	memcpy(&ssdt->signature, "SSDT", 4);
-	/* Access size in ACPI 2.0c/3.0/4.0/5.0 */
-	ssdt->revision = ACPI_REV_ACPI_3_0;
-	memcpy(&ssdt->oem_id, OEM_ID, 6);
-	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
-	ssdt->oem_revision = OEM_REVISION;
-	memcpy(&ssdt->asl_compiler_id, ASLC, 4);
-	ssdt->asl_compiler_revision = ASL_COMPILER_REVISION;
-	ssdt->length = sizeof(acpi_header_t);
-
-	/* (Re)calculate length and checksum */
-	ssdt->length = current - (unsigned long)ssdt;
-	ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
+	 * PM1_CNT register bit0 selects the power management event to be
+	 * either an SCI or SMI interrupt. When this bit is set, then power
+	 * management events will generate an SCI interrupt. When this bit
+	 * is reset power management events will generate an SMI interrupt.
+	 *
+	 * Per ACPI spec, it is the responsibility of the hardware to set
+	 * or reset this bit. OSPM always preserves this bit position.
+	 *
+	 * U-Boot does not support SMI. And we don't have plan to support
+	 * anything running in SMM within U-Boot. To create a legacy-free
+	 * system, and expose ourselves to OSPM as working under ACPI mode
+	 * already, turn this bit on.
+	 */
+	outw(PM1_CNT_SCI_EN, pm1_cnt);
 }
 
 /*
  * QEMU's version of write_acpi_tables is defined in
- * arch/x86/cpu/qemu/fw_cfg.c
+ * arch/x86/cpu/qemu/acpi_table.c
  */
 u32 write_acpi_tables(u32 start)
 {
@@ -342,18 +332,17 @@ u32 write_acpi_tables(u32 start)
 	struct acpi_rsdt *rsdt;
 	struct acpi_xsdt *xsdt;
 	struct acpi_facs *facs;
-	acpi_header_t *dsdt;
+	struct acpi_table_header *dsdt;
 	struct acpi_fadt *fadt;
 	struct acpi_mcfg *mcfg;
 	struct acpi_madt *madt;
-	acpi_header_t *ssdt;
 
 	current = start;
 
-	/* Align ACPI tables to 16byte */
+	/* Align ACPI tables to 16 byte */
 	current = ALIGN(current, 16);
 
-	debug("ACPI: Writing ACPI tables at %lx.\n", start);
+	debug("ACPI: Writing ACPI tables at %x\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
 	rsdp = (struct acpi_rsdp *)current;
@@ -364,7 +353,11 @@ u32 write_acpi_tables(u32 start)
 	current = ALIGN(current, 16);
 	xsdt = (struct acpi_xsdt *)current;
 	current += sizeof(struct acpi_xsdt);
-	current = ALIGN(current, 16);
+	/*
+	 * Per ACPI spec, the FACS table address must be aligned to a 64 byte
+	 * boundary (Windows checks this, but Linux does not).
+	 */
+	current = ALIGN(current, 64);
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
@@ -381,21 +374,13 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_facs(facs);
 
 	debug("ACPI:    * DSDT\n");
-	dsdt = (acpi_header_t *)current;
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	if (dsdt->length >= sizeof(acpi_header_t)) {
-		current += sizeof(acpi_header_t);
-		memcpy((char *)current,
-				(char *)&AmlCode + sizeof(acpi_header_t),
-				dsdt->length - sizeof(acpi_header_t));
-		current += dsdt->length - sizeof(acpi_header_t);
-
-		/* (Re)calculate length and checksum */
-		dsdt->length = current - (unsigned long)dsdt;
-		dsdt->checksum = 0;
-		dsdt->checksum = table_compute_checksum((void *)dsdt,
-				dsdt->length);
-	}
+	dsdt = (struct acpi_table_header *)current;
+	memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
+	current += sizeof(struct acpi_table_header);
+	memcpy((char *)current,
+	       (char *)&AmlCode + sizeof(struct acpi_table_header),
+	       dsdt->length - sizeof(struct acpi_table_header));
+	current += dsdt->length - sizeof(struct acpi_table_header);
 	current = ALIGN(current, 16);
 
 	debug("ACPI:    * FADT\n");
@@ -405,36 +390,29 @@ u32 write_acpi_tables(u32 start)
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
 
-	debug("ACPI:    * MCFG\n");
-	mcfg = (struct acpi_mcfg *)current;
-	acpi_create_mcfg(mcfg);
-	if (mcfg->header.length > sizeof(struct acpi_mcfg)) {
-		current += mcfg->header.length;
-		current = ALIGN(current, 16);
-		acpi_add_table(rsdp, mcfg);
-	}
-
 	debug("ACPI:    * MADT\n");
 	madt = (struct acpi_madt *)current;
 	acpi_create_madt(madt);
-	if (madt->header.length > sizeof(struct acpi_madt)) {
-		current += madt->header.length;
-		acpi_add_table(rsdp, madt);
-	}
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
 	current = ALIGN(current, 16);
 
-	debug("ACPI:    * SSDT\n");
-	ssdt = (acpi_header_t *)current;
-	acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
-	if (ssdt->length > sizeof(acpi_header_t)) {
-		current += ssdt->length;
-		acpi_add_table(rsdp, ssdt);
-		current = ALIGN(current, 16);
-	}
+	debug("ACPI:    * MCFG\n");
+	mcfg = (struct acpi_mcfg *)current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdp, mcfg);
+	current = ALIGN(current, 16);
+
+	debug("current = %x\n", current);
 
-	debug("current = %lx\n", current);
+	debug("ACPI: done\n");
 
-	debug("ACPI: done.\n");
+	/*
+	 * Other than waiting for OSPM to request us to switch to ACPI mode,
+	 * do it by ourselves, since SMI will not be triggered.
+	 */
+	enter_acpi_mode(fadt->pm1a_cnt_blk);
 
 	return current;
 }
diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c
index 783be691af..7cf9de4d7b 100644
--- a/arch/x86/lib/bootm.c
+++ b/arch/x86/lib/bootm.c
@@ -26,14 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define COMMAND_LINE_OFFSET 0x9000
 
-/*
- * Implement a weak default function for boards that optionally
- * need to clean up the system before jumping to the kernel.
- */
-__weak void board_final_cleanup(void)
-{
-}
-
 void bootm_announce_and_cleanup(void)
 {
 	printf("\nStarting kernel ...\n\n");
@@ -45,7 +37,6 @@ void bootm_announce_and_cleanup(void)
 #ifdef CONFIG_BOOTSTAGE_REPORT
 	bootstage_report();
 #endif
-	board_final_cleanup();
 }
 
 #if defined(CONFIG_OF_LIBFDT) && !defined(CONFIG_OF_NO_KERNEL)
diff --git a/arch/x86/lib/coreboot_table.c b/arch/x86/lib/coreboot_table.c
index cb45a79857..ceab3cf5e4 100644
--- a/arch/x86/lib/coreboot_table.c
+++ b/arch/x86/lib/coreboot_table.c
@@ -9,6 +9,37 @@
 #include <asm/coreboot_tables.h>
 #include <asm/e820.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
+int high_table_reserve(void)
+{
+	/* adjust stack pointer to reserve space for configuration tables */
+	gd->arch.high_table_limit = gd->start_addr_sp;
+	gd->start_addr_sp -= CONFIG_HIGH_TABLE_SIZE;
+	gd->arch.high_table_ptr = gd->start_addr_sp;
+
+	/* clear the memory */
+	memset((void *)gd->arch.high_table_ptr, 0, CONFIG_HIGH_TABLE_SIZE);
+
+	gd->start_addr_sp &= ~0xf;
+
+	return 0;
+}
+
+void *high_table_malloc(size_t bytes)
+{
+	u32 new_ptr;
+	void *ptr;
+
+	new_ptr = gd->arch.high_table_ptr + bytes;
+	if (new_ptr >= gd->arch.high_table_limit)
+		return NULL;
+	ptr = (void *)gd->arch.high_table_ptr;
+	gd->arch.high_table_ptr = new_ptr;
+
+	return ptr;
+}
+
 /**
  * cb_table_init() - initialize a coreboot table header
  *
diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c
index 3cc6adbbbb..a93d355d8a 100644
--- a/arch/x86/lib/pirq_routing.c
+++ b/arch/x86/lib/pirq_routing.c
@@ -10,7 +10,6 @@
 #include <pci.h>
 #include <asm/pci.h>
 #include <asm/pirq_routing.h>
-#include <asm/tables.h>
 
 static bool irq_already_routed[16];
 
@@ -111,9 +110,6 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
 {
 	struct irq_routing_table *rom_rt;
 
-	/* Fix up the table checksum */
-	rt->checksum = table_compute_checksum(rt, rt->size);
-
 	/* Align the table to be 16 byte aligned */
 	addr = ALIGN(addr, 16);
 
diff --git a/arch/x86/lib/smbios.c b/arch/x86/lib/smbios.c
index 441fca99f1..9f3055020b 100644
--- a/arch/x86/lib/smbios.c
+++ b/arch/x86/lib/smbios.c
@@ -105,8 +105,8 @@ static int smbios_write_type1(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type1));
 	fill_smbios_header(t, SMBIOS_SYSTEM_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 
 	len = t->length + smbios_string_table_len(t->eos);
 	*current += len;
@@ -121,8 +121,8 @@ static int smbios_write_type2(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type2));
 	fill_smbios_header(t, SMBIOS_BOARD_INFORMATION, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
-	t->product_name = smbios_add_string(t->eos, CONFIG_SYS_BOARD);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
+	t->product_name = smbios_add_string(t->eos, CONFIG_SMBIOS_PRODUCT_NAME);
 	t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
 	t->board_type = SMBIOS_BOARD_MOTHERBOARD;
 
@@ -139,7 +139,7 @@ static int smbios_write_type3(u32 *current, int handle)
 
 	memset(t, 0, sizeof(struct smbios_type3));
 	fill_smbios_header(t, SMBIOS_SYSTEM_ENCLOSURE, len, handle);
-	t->manufacturer = smbios_add_string(t->eos, CONFIG_SYS_VENDOR);
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_SMBIOS_MANUFACTURER);
 	t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP;
 	t->bootup_state = SMBIOS_STATE_SAFE;
 	t->power_supply_state = SMBIOS_STATE_SAFE;
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index a156f2ce31..f92111e4c8 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -80,9 +80,8 @@ void write_tables(void)
 
 #ifdef CONFIG_SEABIOS
 		table_size = rom_table_end - rom_table_start;
-		high_table = (u32)memalign(ROM_TABLE_ALIGN, table_size);
+		high_table = (u32)high_table_malloc(table_size);
 		if (high_table) {
-			memset((void *)high_table, 0, table_size);
 			table_write_funcs[i](high_table);
 
 			cfg_tables[i].start = high_table;
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c
index ce4acc13e0..e947e54c39 100644
--- a/board/BuR/common/common.c
+++ b/board/BuR/common/common.c
@@ -259,7 +259,7 @@ static int load_devicetree(void)
 	}
 #ifdef CONFIG_NAND
 	dtbsize = 0x20000;
-	rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize,
+	rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize,
 				NULL, 0x20000, (u_char *)dtbaddr);
 #else
 	char *dtbname = getenv("dtb");
diff --git a/board/Marvell/common/bootseq.txt b/board/Marvell/common/bootseq.txt
deleted file mode 100644
index 6cae9ea074..0000000000
--- a/board/Marvell/common/bootseq.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-(cpu/mpc7xxx/start.S)
-
-start:
-    b boot_cold
-
-start_warm:
-    b boot_warm
-
-
-boot_cold:
-boot_warm:
-    clear bats
-    init l2 (if enabled)
-    init altivec (if enabled)
-    invalidate l2 (if enabled)
-    setup bats (from defines in config_EVB)
-    enable_addr_trans: (if MMU enabled)
-	enable MSR_IR and MSR_DR
-    jump to in_flash
-
-in_flash:
-    enable l1 dcache
-    gal_low_init: (board/evb64260/sdram_init.S)
-	config SDRAM (CFG, TIMING, DECODE)
-	init scratch regs (810 + 814)
-
-	detect DIMM0 (bank 0 only)
-	config SDRAM_PARA0 to 256/512Mbit
-	bl sdram_op_mode
-	detect bank0 width
-	    write scratch reg 810
-	config SDRAM_PARA0 with results
-	config SDRAM_PARA1 with results
-
-	detect DIMM1 (bank 2 only)
-	config SDRAM_PARA2 to 256/512Mbit
-	detect bank2 width
-	    write scratch reg 814
-	config SDRAM_PARA2 with results
-	config SDRAM_PARA3 with results
-
-	setup device bus timings/width
-	setup boot device timings/width
-
-	setup CPU_CONF (0x0)
-	setup cpu master control register 0x160
-	setup PCI0 TIMEOUT
-	setup PCI1 TIMEOUT
-	setup PCI0 BAR
-	setup PCI1 BAR
-
-	setup MPP control 0-3
-	setup GPP level control
-	setup Serial ports multiplex
-
-    setup stack pointer (r1)
-    setup GOT
-    call cpu_init_f
-	debug leds
-    board_init_f: (common/board.c)
-	board_early_init_f:
-	    remap gt regs?
-	    map PCI mem/io
-	    map device space
-	    clear out interrupts
-	init_timebase
-	env_init
-	serial_init
-	console_init_f
-	display_options
-	initdram: (board/evb64260/evb64260.c)
-	    detect memory
-	    for each bank:
-		dram_size()
-		setup PCI slave memory mappings
-		setup SCS
-	setup monitor
-	alloc board info struct
-	init bd struct
-	relocate_code: (cpu/mpc7xxx/start.S)
-	    copy,got,clearbss
-	    board_init_r(bd, dest_addr) (common/board.c)
-		setup bd function pointers
-		trap_init
-		flash_init: (board/evb64260/flash.c)
-		setup bd flash info
-		cpu_init_r: (cpu/mpc7xxx/cpu_init.c)
-		    nothing
-		mem_malloc_init
-		malloc_bin_reloc
-		spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
-		env_relocated
-		misc_init_r(bd): (board/evb64260/evb64260.c)
-		    mpsc_init2
diff --git a/board/Marvell/common/i2c.h b/board/Marvell/common/i2c.h
deleted file mode 100644
index a879ea93c8..0000000000
--- a/board/Marvell/common/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the DB64360 board by Ingo.Assmus@keymile.com
- */
-
-#ifndef __I2C_H__
-#define __I2C_H__
-
-/* function declarations */
-uchar i2c_read(uchar, unsigned int, int, uchar*, int);
-
-#endif
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
deleted file mode 100644
index 5531f95ca2..0000000000
--- a/board/Marvell/common/intel_flash.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Hacked for the marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- */
-
-/*************** DEFINES for Intel StrataFlash FLASH chip ********************/
-
-/*
- * acceptable chips types are:
- *
- *	28F320J5, 28F640J5, 28F320J3A, 28F640J3A and 28F128J3A
- */
-
-/* register addresses, valid only following an CHIP_CMD_RD_ID command */
-#define CHIP_ADDR_REG_MAN	0x000000	/* manufacturer's id */
-#define CHIP_ADDR_REG_DEV	0x000001	/* device id */
-#define CHIP_ADDR_REG_CFGM	0x000003	/* master lock config */
-#define CHIP_ADDR_REG_CFG(b)	(((b)<<16)|2)	/* lock config for block b */
-
-/* Commands */
-#define CHIP_CMD_RST		0xFF		/* reset flash */
-#define CHIP_CMD_RD_ID		0x90		/* read the id and lock bits */
-#define CHIP_CMD_RD_QUERY	0x98		/* read device capabilities */
-#define CHIP_CMD_RD_STAT	0x70		/* read the status register */
-#define CHIP_CMD_CLR_STAT	0x50		/* clear the staus register */
-#define CHIP_CMD_WR_BUF		0xE8		/* clear the staus register */
-#define CHIP_CMD_PROG		0x40		/* program word command */
-#define CHIP_CMD_ERASE1		0x20		/* 1st word for block erase */
-#define CHIP_CMD_ERASE2		0xD0		/* 2nd word for block erase */
-#define CHIP_CMD_ERASE_SUSP	0xB0		/* suspend block erase */
-#define CHIP_CMD_LOCK		0x60		/* 1st word for all lock cmds */
-#define CHIP_CMD_SET_LOCK_BLK	0x01		/* 2nd wrd set block lock bit */
-#define CHIP_CMD_SET_LOCK_MSTR	0xF1		/* 2nd wrd set master lck bit */
-#define CHIP_CMD_CLR_LOCK_BLK	0xD0		/* 2nd wrd clear blk lck bit */
-
-/* status register bits */
-#define CHIP_STAT_DPS		0x02		/* Device Protect Status */
-#define CHIP_STAT_VPPS		0x08		/* VPP Status */
-#define CHIP_STAT_PSLBS		0x10		/* Program+Set Lock Bit Stat */
-#define CHIP_STAT_ECLBS		0x20		/* Erase+Clr Lock Bit Stat */
-#define CHIP_STAT_ESS		0x40		/* Erase Suspend Status */
-#define CHIP_STAT_RDY		0x80		/* WSM Mach Status, 1=rdy */
-
-#define CHIP_STAT_ERR		(CHIP_STAT_VPPS | CHIP_STAT_DPS | \
-				    CHIP_STAT_ECLBS | CHIP_STAT_PSLBS)
-
-/* ID and Lock Configuration */
-#define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
-#define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
-
-/* dimensions */
-#define CHIP_WIDTH		2		/* chips are in 16 bit mode */
-#define CHIP_WSHIFT		1		/* (log2 of CHIP_WIDTH) */
-#define CHIP_NBLOCKS		128
-#define CHIP_BLKSZ		(128 * 1024)	/* of 128Kbytes each */
-#define CHIP_SIZE		(CHIP_BLKSZ * CHIP_NBLOCKS)
-
-/********************** DEFINES for Hymod Flash ******************************/
-
-/*
- * The hymod board has 2 x 28F320J5 chips running in
- * 16 bit mode, for a 32 bit wide bank.
- */
-
-typedef unsigned short bank_word_t;		/* 8/16/32/64bit unsigned int */
-typedef volatile bank_word_t *bank_addr_t;
-typedef unsigned long bank_size_t;		/* want this big - >= 32 bit */
-
-#define BANK_CHIP_WIDTH		1		/* each bank is 1 chip wide */
-#define BANK_CHIP_WSHIFT	0		/* (log2 of BANK_CHIP_WIDTH) */
-
-#define BANK_WIDTH		(CHIP_WIDTH * BANK_CHIP_WIDTH)
-#define BANK_WSHIFT		(CHIP_WSHIFT + BANK_CHIP_WSHIFT)
-#define BANK_NBLOCKS		CHIP_NBLOCKS
-#define BANK_BLKSZ		(CHIP_BLKSZ * BANK_CHIP_WIDTH)
-#define BANK_SIZE		(CHIP_SIZE * BANK_CHIP_WIDTH)
-
-#define MAX_BANKS		1		/* only one bank possible */
-
-/* align bank addresses and sizes to bank word boundaries */
-#define BANK_ADDR_WORD_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_WIDTH - 1)))
-#define BANK_SIZE_WORD_ALIGN(s)	((bank_size_t)BANK_ADDR_WORD_ALIGN( \
-				    (bank_size_t)(s) + (BANK_WIDTH - 1)))
-
-/* align bank addresses and sizes to bank block boundaries */
-#define BANK_ADDR_BLK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_BLKSZ - 1)))
-#define BANK_SIZE_BLK_ALIGN(s)	((bank_size_t)BANK_ADDR_BLK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_BLKSZ - 1)))
-
-/* align bank addresses and sizes to bank boundaries */
-#define BANK_ADDR_BANK_ALIGN(a)	((bank_addr_t)((bank_size_t)(a) \
-				    & ~(BANK_SIZE - 1)))
-#define BANK_SIZE_BANK_ALIGN(s)	((bank_size_t)BANK_ADDR_BANK_ALIGN( \
-				    (bank_size_t)(s) + (BANK_SIZE - 1)))
-
-/* add an offset to a bank address */
-#define BANK_ADDR_OFFSET(a, o)	(bank_addr_t)((bank_size_t)(a) + \
-				    (bank_size_t)(o))
-
-/* get base address of bank b, given flash base address a */
-#define BANK_ADDR_BASE(a, b)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    (bank_size_t)(b) * BANK_SIZE)
-
-/* adjust a bank address to start of next word, block or bank */
-#define BANK_ADDR_NEXT_WORD(a)	BANK_ADDR_OFFSET(BANK_ADDR_WORD_ALIGN(a), \
-				    BANK_WIDTH)
-#define BANK_ADDR_NEXT_BLK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BLK_ALIGN(a), \
-				    BANK_BLKSZ)
-#define BANK_ADDR_NEXT_BANK(a)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    BANK_SIZE)
-
-/* get bank address of chip register r given a bank base address a */
-#define BANK_ADDR_REG(a, r)	BANK_ADDR_OFFSET(BANK_ADDR_BANK_ALIGN(a), \
-				    ((bank_size_t)(r) << BANK_WSHIFT))
-
-/* make a bank address for each chip register address */
-
-#define BANK_ADDR_REG_MAN(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_MAN)
-#define BANK_ADDR_REG_DEV(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_DEV)
-#define BANK_ADDR_REG_CFGM(a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFGM)
-#define BANK_ADDR_REG_CFG(b,a)	BANK_ADDR_REG((a), CHIP_ADDR_REG_CFG(b))
-
-/*
- * replicate a chip cmd/stat/rd value into each byte position within a word
- * so that multiple chips are accessed in a single word i/o operation
- *
- * this must be as wide as the bank_word_t type, and take into account the
- * chip width and bank layout
- */
-
-#define BANK_FILL_WORD(o)	((bank_word_t)(o))
-
-/* make a bank word value for each chip cmd/stat/rd value */
-
-/* Commands */
-#define BANK_CMD_RST		BANK_FILL_WORD(CHIP_CMD_RST)
-#define BANK_CMD_RD_ID		BANK_FILL_WORD(CHIP_CMD_RD_ID)
-#define BANK_CMD_RD_STAT	BANK_FILL_WORD(CHIP_CMD_RD_STAT)
-#define BANK_CMD_CLR_STAT	BANK_FILL_WORD(CHIP_CMD_CLR_STAT)
-#define BANK_CMD_ERASE1		BANK_FILL_WORD(CHIP_CMD_ERASE1)
-#define BANK_CMD_ERASE2		BANK_FILL_WORD(CHIP_CMD_ERASE2)
-#define BANK_CMD_PROG		BANK_FILL_WORD(CHIP_CMD_PROG)
-#define BANK_CMD_LOCK		BANK_FILL_WORD(CHIP_CMD_LOCK)
-#define BANK_CMD_SET_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_BLK)
-#define BANK_CMD_SET_LOCK_MSTR	BANK_FILL_WORD(CHIP_CMD_SET_LOCK_MSTR)
-#define BANK_CMD_CLR_LOCK_BLK	BANK_FILL_WORD(CHIP_CMD_CLR_LOCK_BLK)
-
-/* status register bits */
-#define BANK_STAT_DPS		BANK_FILL_WORD(CHIP_STAT_DPS)
-#define BANK_STAT_PSS		BANK_FILL_WORD(CHIP_STAT_PSS)
-#define BANK_STAT_VPPS		BANK_FILL_WORD(CHIP_STAT_VPPS)
-#define BANK_STAT_PSLBS		BANK_FILL_WORD(CHIP_STAT_PSLBS)
-#define BANK_STAT_ECLBS		BANK_FILL_WORD(CHIP_STAT_ECLBS)
-#define BANK_STAT_ESS		BANK_FILL_WORD(CHIP_STAT_ESS)
-#define BANK_STAT_RDY		BANK_FILL_WORD(CHIP_STAT_RDY)
-
-#define BANK_STAT_ERR		BANK_FILL_WORD(CHIP_STAT_ERR)
-
-/* ID and Lock Configuration */
-#define BANK_RD_ID_LOCK		BANK_FILL_WORD(CHIP_RD_ID_LOCK)
-#define BANK_RD_ID_MAN		BANK_FILL_WORD(CHIP_RD_ID_MAN)
-#define BANK_RD_ID_DEV		BANK_FILL_WORD(CHIP_RD_ID_DEV)
diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c
deleted file mode 100644
index 610b411faa..0000000000
--- a/board/Marvell/common/memory.c
+++ /dev/null
@@ -1,1374 +0,0 @@
-/*
- * Copyright - Galileo technology.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- *
- * written or collected and sometimes rewritten by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- */
-
-
-#include <common.h>
-#include "../include/core.h"
-#include "../include/memory.h"
-
-/*******************************************************************************
-* memoryGetBankBaseAddress - Returns the base address of a memory bank.
-* DESCRIPTION:
-*       This function returns the base address of one of the SDRAM's memory
-*       banks. There are 4 memory banks and each one represents one DIMM side.
-* INPUT:
-*       MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit Memory bank base address.
-*******************************************************************************/
-static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
-{
-	switch (bank) {
-	case BANK0:
-		return SCS_0_LOW_DECODE_ADDRESS;
-	case BANK1:
-		return SCS_1_LOW_DECODE_ADDRESS;
-	case BANK2:
-		return SCS_2_LOW_DECODE_ADDRESS;
-	case BANK3:
-		return SCS_3_LOW_DECODE_ADDRESS;
-
-	}
-	return SCS_0_LOW_DECODE_ADDRESS;	/* default value */
-}
-
-unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
-{
-	unsigned int base;
-	unsigned int regOffset = memoryGetBankRegOffset (bank);
-
-	GT_REG_READ (regOffset, &base);
-	base = base << 16;	/* MV6436x */
-	return base;
-}
-
-/*******************************************************************************
-* memoryGetDeviceBaseAddress - Returns the base address of a device.
-* DESCRIPTION:
-*       This function returns the base address of a device on the system. There
-*       are 5 possible devices (0 - 4 and one boot device) as defined in
-*       gtMemory.h. Each of the device parameters is maped to one of the CS
-*       (Devices chip selects) base address register.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit Device base address.
-*
-*******************************************************************************/
-static unsigned int memoryGetDeviceRegOffset (DEVICE device)
-{
-	switch (device) {
-	case DEVICE0:
-		return CS_0_LOW_DECODE_ADDRESS;
-	case DEVICE1:
-		return CS_1_LOW_DECODE_ADDRESS;
-	case DEVICE2:
-		return CS_2_LOW_DECODE_ADDRESS;
-	case DEVICE3:
-		return CS_3_LOW_DECODE_ADDRESS;
-	case BOOT_DEVICE:
-		return BOOTCS_LOW_DECODE_ADDRESS;
-	}
-	return CS_0_LOW_DECODE_ADDRESS;	/* default value */
-}
-
-unsigned int memoryGetDeviceBaseAddress (DEVICE device)
-{
-	unsigned int regBase;
-	unsigned int regOffset = memoryGetDeviceRegOffset (device);
-
-	GT_REG_READ (regOffset, &regBase);
-
-	regBase = regBase << 16;	/* MV6436x */
-	return regBase;
-}
-
-/*******************************************************************************
-* MemoryGetPciBaseAddr - Returns the base address of a PCI window.
-* DESCRIPTION:
-*       This function returns the base address of a PCI window. There are 5
-*       possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
-*       interface as defined in gtMemory.h, used by the CPU's address decoding
-*       mechanism.
-*	New in MV6436x
-* INPUT:
-*       pciWindow - Selects one of the PCI windows as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit PCI window base address.
-*******************************************************************************/
-unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
-{
-	unsigned int baseAddrReg, base;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR;  */
-		break;
-	case PCI_0_MEM0:
-		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
-		break;
-	case PCI_0_MEM1:
-		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
-		break;
-	case PCI_0_MEM2:
-		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR;  */
-		break;
-	case PCI_0_MEM3:
-		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR;  */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM0:
-		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
-		break;
-	case PCI_1_MEM1:
-		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM2:
-		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
-		break;
-	case PCI_1_MEM3:
-		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return 0xffffffff;
-	}
-	GT_REG_READ (baseAddrReg, &base);
-	return (base << 16);
-}
-
-/*******************************************************************************
-* memoryGetBankSize - Returns the size of a memory bank.
-* DESCRIPTION:
-*       This function returns the size of memory bank as described in
-*       'gtMemoryGetBankBaseAddress' function.
-* INPUT:
-*       bank - Selects one of the four banks as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size memory bank size or 0 for a closed or non populated bank.
-*
-*******************************************************************************/
-unsigned int memoryGetBankSize (MEMORY_BANK bank)
-{
-	unsigned int sizeReg, size;
-	MEMORY_WINDOW window;
-
-	switch (bank) {
-	case BANK0:
-		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/* CS_0_SIZE; */
-		window = CS_0_WINDOW;
-		break;
-	case BANK1:
-		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/* CS_1_SIZE; */
-		window = CS_1_WINDOW;
-		break;
-	case BANK2:
-		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/* CS_2_SIZE; */
-		window = CS_2_WINDOW;
-		break;
-	case BANK3:
-		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/* CS_3_SIZE; */
-		window = CS_3_WINDOW;
-		break;
-	default:
-		return 0;
-		break;
-	}
-	/* If the window is closed, a size of 0 is returned */
-	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceSize - Returns the size of a device memory space.
-* DESCRIPTION:
-*       This function returns the memory space size of a given device.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size of a device memory space.
-*******************************************************************************/
-unsigned int memoryGetDeviceSize (DEVICE device)
-{
-	unsigned int sizeReg, size;
-	MEMORY_WINDOW window;
-
-	switch (device) {
-	case DEVICE0:
-		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
-		window = DEVCS_0_WINDOW;
-		break;
-	case DEVICE1:
-		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
-		window = DEVCS_1_WINDOW;
-		break;
-	case DEVICE2:
-		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
-		window = DEVCS_2_WINDOW;
-		break;
-	case DEVICE3:
-		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
-		window = DEVCS_3_WINDOW;
-		break;
-	case BOOT_DEVICE:
-		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
-		window = BOOT_CS_WINDOW;
-		break;
-	default:
-		return 0;
-		break;
-	}
-	/* If the window is closed, a size of 0 is returned */
-	if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* MemoryGetPciWindowSize - Returns the size of a PCI memory window.
-* DESCRIPTION:
-*       This function returns the size of a PCI window.
-* INPUT:
-*       pciWindow - Selects one of the PCI memory windows as defined in
-*       Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit size of a PCI memory window.
-*******************************************************************************/
-unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
-{
-	unsigned int sizeReg, size;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
-		break;
-	case PCI_0_MEM0:
-		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
-		break;
-	case PCI_0_MEM1:
-		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
-		break;
-	case PCI_0_MEM2:
-		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
-		break;
-	case PCI_0_MEM3:
-		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
-		break;
-	case PCI_1_MEM0:
-		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
-		break;
-	case PCI_1_MEM1:
-		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE;  */
-		break;
-	case PCI_1_MEM2:
-		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE;  */
-		break;
-	case PCI_1_MEM3:
-		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return 0x0;
-	}
-	/* If the memory window is disabled, retrun size = 0 */
-	if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
-	    == MEM_WINDOW_DISABLED)
-		return 0;
-	GT_REG_READ (sizeReg, &size);
-	size = ((size << 16) | 0xffff) + 1;
-	return size;
-}
-
-/*******************************************************************************
-* memoryGetDeviceWidth - Returns the width of a given device.
-* DESCRIPTION:
-*       The MV's device interface supports up to 32 Bit wide devices. A device
-*       can have a  1, 2, 4 or 8 Bytes data width. This function returns the
-*       width of a device as defined by the user or the operating system.
-* INPUT:
-*       device - Selects one of the five devices as defined in Memory.h.
-* OUTPUT:
-*       None.
-* RETURN:
-*       Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
-*******************************************************************************/
-unsigned int memoryGetDeviceWidth (DEVICE device)
-{
-	unsigned int width;
-	unsigned int regValue;
-
-	GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, &regValue);
-	width = (regValue & (BIT20 | BIT21)) >> 20;
-	return (BIT0 << width);
-}
-
-/*******************************************************************************
-* memoryMapBank - Set new base address and size for one of the memory
-*                         banks.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the memory banks
-*       (CS0 - CS3). It is the programmer`s responsibility to make sure that
-*       there are no conflicts with other memory spaces. When two memory spaces
-*       overlap, the MV's behavior is not defined .If a bank needs to be closed,
-*       set the 'bankLength' parameter size to 0x0.
-*
-* INPUT:
-*       bank      - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
-*       bankBase  - The memory bank base address.
-*       bankLength  - The memory bank size. This function will decrement the
-*                   'bankLength' parameter by one and then check if the size is
-*                   valid. A valid size must be programed from LSB to MSB as
-*                   sequence of '1's followed by sequence of '0's.
-*                   To close a memory window simply set the size to 0.
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-* OUTPUT:
-*       None.
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
-		    unsigned int bankLength)
-{
-	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/*    PCI_INTERNAL_BAR pciBAR; */
-
-	switch (bank) {
-	case BANK0:
-		baseReg = SCS_0_LOW_DECODE_ADDRESS;	/*CS_0_BASE_ADDR; */
-		sizeReg = SCS_0_HIGH_DECODE_ADDRESS;	/*CS_0_SIZE; */
-/*        pciBAR = PCI_CS0_BAR; */
-		break;
-	case BANK1:
-		baseReg = SCS_1_LOW_DECODE_ADDRESS;	/*CS_1_BASE_ADDR; */
-		sizeReg = SCS_1_HIGH_DECODE_ADDRESS;	/*CS_1_SIZE; */
-		/*        pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
-		break;
-	case BANK2:
-		baseReg = SCS_2_LOW_DECODE_ADDRESS;	/*CS_2_BASE_ADDR; */
-		sizeReg = SCS_2_HIGH_DECODE_ADDRESS;	/*CS_2_SIZE; */
-/*        pciBAR = PCI_CS2_BAR;*/
-		break;
-	case BANK3:
-		baseReg = SCS_3_LOW_DECODE_ADDRESS;	/*CS_3_BASE_ADDR; */
-		sizeReg = SCS_3_HIGH_DECODE_ADDRESS;	/*CS_3_SIZE; */
-/*        pciBAR = PCI_CS3_BAR; */
-		break;
-	default:
-		return false;
-	}
-	/* If the size is 0, the window will be disabled */
-	if (bankLength == 0) {
-		MemoryDisableWindow (CS_0_WINDOW << bank);
-		/* Disable the BAR from the PCI slave side */
-/*        gtPci0DisableInternalBAR(pciBAR); */
-/*        gtPci1DisableInternalBAR(pciBAR); */
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((bankBase % bankLength) != 0) {
-		return false;
-	}
-	if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
-		newBase = bankBase >> 16;
-		newSize = bankLength >> 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = newSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid	 */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-#ifdef DEBUG
-		{
-			unsigned int oldBase, oldSize;
-
-			GT_REG_READ (baseReg, &oldBase);
-			GT_REG_READ (sizeReg + 8, &oldSize);
-
-			printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
-				bank, oldBase, oldSize, newBase, newSize);
-		}
-#endif
-		/* writing the new values */
-		GT_REG_WRITE (baseReg, newBase);
-		GT_REG_WRITE (sizeReg, newSize - 1);
-		/* Enable back the window */
-		MemoryEnableWindow (CS_0_WINDOW << bank);
-		/* Enable the BAR from the PCI slave side */
-/*        gtPci0EnableInternalBAR(pciBAR); */
-/*        gtPci1EnableInternalBAR(pciBAR); */
-		return true;
-	}
-	return false;
-}
-
-
-/*******************************************************************************
-* memoryMapDeviceSpace - Set new base address and size for one of the device
-*                           windows.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the device windows
-*       (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
-*       that there are no conflicts with other memory spaces. When two memory
-*       spaces overlap, the MV's behavior is not defined .If a device window
-*       needs to be closed, set the 'deviceLength' parameter size to 0x0.
-*
-* INPUT:
-*       device           - One of the device windows (DEV_CS0-DEV_CS3) as
-*                          defined in gtMemory.h.
-*       deviceBase - The device window base address.
-*       deviceLength - The device window size. This function will decrement
-*                          the 'deviceLength' parameter by one and then
-*                          check if the size is valid. A valid size must be
-*                          programed from LSB to MSB as sequence of '1's
-*                          followed by sequence of '0's.
-*                          To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-* CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
-*
-*******************************************************************************/
-
-bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
-			   unsigned int deviceLength)
-{
-	unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
-
-/*    PCI_INTERNAL_BAR pciBAR;*/
-
-	switch (device) {
-	case DEVICE0:
-		baseReg = CS_0_LOW_DECODE_ADDRESS;	/*DEV_CS0_BASE_ADDR; */
-		sizeReg = CS_0_HIGH_DECODE_ADDRESS;	/*DEV_CS0_SIZE; */
-/*        pciBAR = PCI_DEV_CS0_BAR; */
-		break;
-	case DEVICE1:
-		baseReg = CS_1_LOW_DECODE_ADDRESS;	/*DEV_CS1_BASE_ADDR; */
-		sizeReg = CS_1_HIGH_DECODE_ADDRESS;	/*DEV_CS1_SIZE; */
-/*        pciBAR = PCI_DEV_CS1_BAR; */
-		break;
-	case DEVICE2:
-		baseReg = CS_2_LOW_DECODE_ADDRESS;	/*DEV_CS2_BASE_ADDR; */
-		sizeReg = CS_2_HIGH_DECODE_ADDRESS;	/*DEV_CS2_SIZE; */
-/*        pciBAR = PCI_DEV_CS2_BAR; */
-		break;
-	case DEVICE3:
-		baseReg = CS_3_LOW_DECODE_ADDRESS;	/*DEV_CS3_BASE_ADDR; */
-		sizeReg = CS_3_HIGH_DECODE_ADDRESS;	/*DEV_CS3_SIZE; */
-/*        pciBAR = PCI_DEV_CS3_BAR; */
-		break;
-	case BOOT_DEVICE:
-		baseReg = BOOTCS_LOW_DECODE_ADDRESS;	/*BOOTCS_BASE_ADDR; */
-		sizeReg = BOOTCS_HIGH_DECODE_ADDRESS;	/*BOOTCS_SIZE; */
-/*        pciBAR = PCI_BOOT_CS_BAR; */
-		break;
-	default:
-		return false;
-	}
-	if (deviceLength == 0) {
-		MemoryDisableWindow (DEVCS_0_WINDOW << device);
-		/* Disable the BAR from the PCI slave side */
-/*        gtPci0DisableInternalBAR(pciBAR); */
-/*        gtPci1DisableInternalBAR(pciBAR); */
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((deviceBase % deviceLength) != 0) {
-		return false;
-	}
-	if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
-		newBase = deviceBase >> 16;
-		newSize = deviceLength >> 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = newSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		/* writing the new values */
-		GT_REG_WRITE (baseReg, newBase);
-		GT_REG_WRITE (sizeReg, newSize - 1);
-		MemoryEnableWindow (DEVCS_0_WINDOW << device);
-		/* Enable the BAR from the PCI slave side */
-/*        gtPci0EnableInternalBAR(pciBAR); */
-/*        gtPci1EnableInternalBAR(pciBAR); */
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* MemorySetPciWindow - Set new base address and size for one of the PCI
-*                        windows.
-*
-* DESCRIPTION:
-*       The CPU interface address decoding map consists of 21 address windows
-*       for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
-*       window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
-*       space. Each address window is defined by two registers - base and size.
-*       The CPU address is compared with the values in the various CPU windows
-*       until a match is found and the address is than targeted to that window.
-*       This function sets new base and size for one the PCI windows
-*       (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
-*       that there are no conflicts with other memory spaces. When two memory
-*       spaces overlap, the MV's behavior is not defined. If a PCI window
-*       needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
-*
-* INPUT:
-*       pciWindow     - One of the PCI windows as defined in gtMemory.h.
-*       pciWindowBase - The PCI window base address.
-*       pciWindowSize - The PCI window size. This function will decrement the
-*                       'pciWindowSize' parameter by one and then check if the
-*                       size is valid. A valid size must be programed from LSB
-*                       to MSB as sequence of '1's followed by sequence of '0's.
-*                       To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
-			 unsigned int pciWindowSize)
-{
-	unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
-
-	switch (pciWindow) {
-	case PCI_0_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_0_IO_BASE_ADDR; */
-		sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS;	/*PCI_0_IO_SIZE; */
-		break;
-	case PCI_0_MEM0:
-		baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY0_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY0_SIZE; */
-		break;
-	case PCI_0_MEM1:
-		baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY1_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY1_SIZE; */
-		break;
-	case PCI_0_MEM2:
-		baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY2_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY2_SIZE; */
-		break;
-	case PCI_0_MEM3:
-		baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_0_MEMORY3_BASE_ADDR; */
-		sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_0_MEMORY3_SIZE; */
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS;	/*PCI_1_IO_BASE_ADDR; */
-		sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS;	/*PCI_1_IO_SIZE; */
-		break;
-	case PCI_1_MEM0:
-		baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY0_BASE_ADDR; */
-		sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY0_SIZE; */
-		break;
-	case PCI_1_MEM1:
-		baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY1_BASE_ADDR;  */
-		sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY1_SIZE; */
-		break;
-	case PCI_1_MEM2:
-		baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY2_BASE_ADDR;  */
-		sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY2_SIZE; */
-		break;
-	case PCI_1_MEM3:
-		baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS;	/*PCI_1_MEMORY3_BASE_ADDR; */
-		sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS;	/*PCI_1_MEMORY3_SIZE; */
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		return false;
-	}
-	if (pciWindowSize == 0) {
-		MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
-		return true;
-	}
-	/* The base address must be aligned to the size */
-	if ((pciWindowBase % pciWindowSize) != 0) {
-		return false;
-	}
-	if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
-		pciWindowBase >>= 16;
-		pciWindowSize >>= 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = pciWindowSize - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		GT_REG_WRITE (sizeReg, pciWindowSize - 1);
-		GT_REG_READ (baseAddrReg, &currentLow);
-		pciWindowBase =
-			(pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
-		GT_REG_WRITE (baseAddrReg, pciWindowBase);
-		MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internal
-*                                  registers memory space.
-*
-* DESCRIPTION:
-*       This function set new base address for the internal registers memory
-*       space (the size is fixed and cannot be modified). The function does not
-*       handle overlapping with other memory spaces, it is the programer's
-*       responsibility to ensure that overlapping does not occur.
-*       When two memory spaces overlap, the MV's behavior is not defined.
-*
-* INPUT:
-*       internalRegBase - new base address for the internal registers memory
-*                         space.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*        true on success, false on failure
-*
-*******************************************************************************/
-/********************************************************************
-* memoryMapInternalRegistersSpace - Sets new base address for the internals
-*                                   registers.
-*
-* INPUTS:  unsigned int internalRegBase - The new base address.
-* RETURNS: true on success, false on failure
-*********************************************************************/
-bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
-{
-	unsigned int currentValue;
-	unsigned int internalValue = internalRegBase;
-
-	internalRegBase = (internalRegBase >> 16);
-	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
-	internalRegBase = (currentValue & 0xff000000) | internalRegBase;
-	GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
-	/* initializing also the global variable 'internalRegBaseAddr' */
-/*    gtInternalRegBaseAddr = internalValue; */
-	INTERNAL_REG_BASE_ADDR = internalValue;
-	return true;
-}
-
-/*******************************************************************************
-* memoryGetInternalRegistersSpace - Returns the internal registers Base
-*                                     address.
-*
-* DESCRIPTION:
-*       This function returns the base address of  the internal registers
-*       memory space .
-*
-* INPUT:
-*       None.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       32 bit base address of the internal registers memory space.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalRegistersSpace (void)
-{
-	unsigned int currentValue = 0;
-
-	GT_REG_READ (INTERNAL_SPACE_DECODE, &currentValue);
-	return ((currentValue & 0x000fffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
-*
-* DESCRIPTION:
-*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-*       funcnion return the SRAM's base address.
-* INPUT:
-*       None.
-* OUTPUT:
-*       None.
-* RETURN:
-*       32 bit SRAM's base address.
-*
-*******************************************************************************/
-unsigned int memoryGetInternalSramBaseAddr (void)
-{
-	return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
-}
-
-/*******************************************************************************
-* gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
-*
-* DESCRIPTION:
-*       The Atlantis incorporate integrated 2Mbit SRAM for general use. This
-*       function sets a new base address to the SRAM .
-* INPUT:
-*       sramBaseAddress - The SRAM's base address.
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
-{
-	GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
-}
-
-/*******************************************************************************
-* memorySetProtectRegion - Set protection mode for one of the 8 regions.
-*
-* DESCRIPTION:
-*       The CPU interface supports configurable access protection. This includes
-*       up to eight address ranges defined to a different protection type :
-*       whether the address range is cacheable or not, whether it is writable or
-*       not , and whether it is accessible or not. A Low and High registers
-*       define each window while the minimum address range of each window is
-*       1Mbyte. An address driven by the CPU, in addition to the address
-*       decoding and remapping process, is compared against the eight Access
-*       Protection Low/High registers , if an address matches one of the windows
-*       , the MV device checks the transaction type against the protection bits
-*       defined in CPU Access Protection register, to determine if the access is
-*       allowed. This function set a protection mode to one of the 8 possible
-*       regions.
-*      NOTE:
-*       The CPU address windows are restricted to a size of  2 power n and the
-*       start address must be aligned to the window size. For example, if using
-*       a 16 MB window, the start address bits [23:0] must be 0.The MV's
-*       internal registers space is not protected, even if the access protection
-*       windows contain this space.
-*
-* INPUT:
-*       region - selects which region to be configured. The values defined in
-*                gtMemory.h:
-*
-*                 - MEM_REGION0
-*                 - MEM_REGION1
-*                 - etc.
-*
-*       memAccess - Allows or forbids access (read or write ) to the region. The
-*                   values defined in gtMemory.h:
-*
-*                    - MEM_ACCESS_ALLOWED
-*                    - MEM_ACCESS_FORBIDEN
-*
-*       memWrite - CPU write protection to the region. The values defined in
-*                  gtMemory.h:
-*
-*                   - MEM_WRITE_ALLOWED
-*                   - MEM_WRITE_FORBIDEN
-*
-*       cacheProtection - Defines whether caching the region is allowed or not.
-*                         The values defined in gtMemory.h:
-*
-*                          - MEM_CACHE_ALLOWED
-*                          - MEM_CACHE_FORBIDEN
-*
-*       baseAddress - the region's base Address.
-*       regionSize  - The region's size. This function will decrement the
-*                     'regionSize' parameter by one and then check if the size
-*                     is valid. A valid size must be programed from LSB to MSB
-*                     as sequence of '1's followed by sequence of '0's.
-*                     To close a memory window simply set the size to 0.
-*
-*      NOTE!!!
-*       The size must be in 64Kbyte granularity.
-*       The base address must be aligned to the size.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false for invalid size, true otherwise.
-*
-*******************************************************************************/
-bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
-			     MEMORY_ACCESS memAccess,
-			     MEMORY_ACCESS_WRITE memWrite,
-			     MEMORY_CACHE_PROTECT cacheProtection,
-			     unsigned int baseAddress, unsigned int size)
-{
-	unsigned int dataForReg, temp, rShift;
-
-	if (size == 0) {
-		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
-			      0x0);
-		return true;
-	}
-	/* The base address must be aligned to the size.  */
-	if (baseAddress % size != 0) {
-		return false;
-	}
-	if (size >= MINIMUM_ACCESS_WIN_SIZE) {
-		baseAddress = ((baseAddress >> 16) & 0xfffff);
-		dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
-			((memWrite << 21) & BIT21) | ((cacheProtection << 22)
-						      & BIT22) | BIT31;
-		GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
-			      dataForReg);
-		size >>= 16;
-		/* Checking that the size is a sequence of '1' followed by a
-		   sequence of '0' starting from LSB to MSB. */
-		temp = size - 1;
-		for (rShift = 0; rShift < 16; rShift++) {
-			temp = temp >> rShift;
-			if ((temp & 0x1) == 0) {	/* Either we got to the last '1' */
-							/* or the size is not valid       */
-				if (temp > 0x0)
-					return false;
-				else
-					break;
-			}
-		}
-		GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
-			      size - 1);
-		return true;
-	}
-	return false;
-}
-
-/*******************************************************************************
-* gtMemoryDisableProtectRegion - Disable a protected window.
-*
-* DESCRIPTION:
-*       This function disable a protected window set by
-*       'gtMemorySetProtectRegion' function.
-*
-* INPUT:
-*       window - one of the 4 windows ( defined in gtMemory.h ).
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       None.
-*
-*******************************************************************************/
-void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
-{
-	RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
-			BIT31);
-}
-
-/*******************************************************************************
-* memorySetPciRemapValue - Set a remap value to a PCI memory space target.
-*
-* DESCRIPTION:
-*       In addition to the address decoding mechanism, the CPU has an address
-*       remapping mechanism to be used by every PCI decoding window. Each PCI
-*       window can be remaped to a desired address target according to the remap
-*       value within the remap register. The address remapping is useful when a
-*       CPU address range must be reallocated to a different location on the
-*       PCI bus. Also, it enables CPU access to a PCI agent located above the
-*       4Gbyte space. On system boot, each of the PCI memory spaces is maped to
-*       a defualt value (see CPU interface section in the MV spec for the
-*       default values). The remap mechanism does not always produce the desired
-*       address on the PCI bus because of the remap mechanism way of working
-*       (to fully understand why, please see the 'Address Remapping' section in
-*       the MV's spec). Therefor, this function sets a desired remap value to
-*       one of the PCI memory windows and return the effective address that
-*       should be used when exiting the PCI memory window. You should ALWAYS use
-*       the returned value by this function when remapping a PCI window and
-*       exiting it. If for example the base address of PCI0 memory 0 is
-*       0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
-*       the function will return the value of 0x91000000 that MUST
-*       be used to exit this memory window in order to achive the deisred
-*       remapping.
-*
-* INPUT:
-*       memoryWindow   - One of the PCI memory windows as defined in Memory.h
-*       remapValueLow  - The low remap value.
-*       remapValueHigh - The high remap value.
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       The effective base address to exit the PCI, or 0xffffffff if one of the
-*       parameters is erroneous or the effective base address is higher the top
-*       decode value.
-*
-*******************************************************************************/
-unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
-				     unsigned int remapValueHigh,
-				     unsigned int remapValueLow)
-{
-	unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
-	unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
-	unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
-
-	/* Initializing the base and size variables of the PCI
-	   memory windows */
-	switch (memoryWindow) {
-	case PCI_0_IO:
-		pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_IO_SIZE;
-		remapRegLow = PCI_0_IO_ADDR_REMAP;
-		remapRegHigh = PCI_0_IO_ADDR_REMAP;
-		break;
-	case PCI_0_MEM0:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
-		remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM1:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
-		remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM2:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
-		remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
-		break;
-	case PCI_0_MEM3:
-		pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
-		remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
-		break;
-#ifdef INCLUDE_PCI_1
-	case PCI_1_IO:
-		pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_IO_SIZE;
-		remapRegLow = PCI_1_IO_ADDR_REMAP;
-		remapRegHigh = PCI_1_IO_ADDR_REMAP;
-		break;
-	case PCI_1_MEM0:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
-		remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM1:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
-		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM2:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
-		remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
-		break;
-	case PCI_1_MEM3:
-		pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
-		pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
-		remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
-		remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
-		break;
-#endif /* INCLUDE_PCI_1 */
-	default:
-		/* Retrun an invalid effective base address */
-		return 0xffffffff;
-	}
-	/* Writing the remap value to the remap regisers */
-	GT_REG_WRITE (remapRegHigh, remapValueHigh);
-	GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
-	/* Reading the values from the base address and size registers */
-	baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
-	windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
-	/* Start calculating the effective Base Address */
-	effectiveBaseAddress = baseAddrValue << 16;
-	/* The effective base address will be combined from the chopped (if any)
-	   remap value (according to the size value and remap mechanism) and the
-	   window's base address */
-	effectiveBaseAddress |=
-		(((windowSizeValue << 16) | 0xffff) & remapValueLow);
-	/* If the effectiveBaseAddress exceed the window boundaries return an
-	   invalid value. */
-	if (effectiveBaseAddress >
-	    ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
-		return 0xffffffff;
-	return effectiveBaseAddress;
-}
-
-/********************************************************************
-* memorySetRegionSnoopMode - This function modifys one of the 4 regions which
-*                            supports Cache Coherency.
-*
-*
-* Inputs: SNOOP_REGION region - One of the four regions.
-*         SNOOP_TYPE snoopType - There is four optional Types:
-*                               1. No Snoop.
-*                               2. Snoop to WT region.
-*                               3. Snoop to WB region.
-*                               4. Snoop & Invalidate to WB region.
-*         unsigned int baseAddress - Base Address of this region.
-*         unsigned int topAddress - Top Address of this region.
-* Returns: false if one of the parameters is wrong and true else
-*********************************************************************/
-/* evb6260 code */
-#if 0
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength)
-{
-    unsigned int snoopXbaseAddress;
-    unsigned int snoopXtopAddress;
-    unsigned int data;
-    unsigned int snoopHigh = baseAddress + regionLength;
-
-    if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
-	return false;
-    snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
-    snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
-				 if(regionLength == 0) /* closing the region */
-    {
-	GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
-	GT_REG_WRITE(snoopXtopAddress,0);
-	return true;
-    }
-    baseAddress = baseAddress & 0xffff0000;
-    data = (baseAddress >> 16) | snoopType << 16;
-    GT_REG_WRITE(snoopXbaseAddress,data);
-    snoopHigh = (snoopHigh & 0xfff00000) >> 20;
-    GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
-    return true;
-}
-#endif
-
-/********************************************************************
-* memoryRemapAddress - This fubction used for address remapping.
-*
-*
-* Inputs: regOffset: remap register
-*         remapValue :
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*
-* Not needed function To_do !!!!
-*********************************************************************/
-bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
-{
-	unsigned int valueForReg;
-
-	valueForReg = (remapValue & 0xfff00000) >> 20;
-	GT_REG_WRITE (remapReg, valueForReg);
-	return true;
-}
-
-/*******************************************************************************
-* memoryGetDeviceParam - Extract the device parameters from the device bank
-*                          parameters register.
-*
-* DESCRIPTION:
-*       To allow interfacing with very slow devices and fast synchronous SRAMs,
-*       each device can be programed to different timing parameters. Each bank
-*       has its own parameters register. Bank width can be programmed to 8, 16,
-*       or 32-bits. Bank timing parameters can be programmed to support
-*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-*       Controllers). The MV allows you to set timing parameters and width for
-*       each device through parameters register .
-*       This function extracts the parameters described from the Device Bank
-*       parameters register and fills the given 'deviceParam' (defined in
-*       gtMemory.h) structure with the read data.
-*
-* INPUT:
-*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
-*                      Memory.h).For details about each structure field please
-*                      see the device timing parameter section in the MV
-*                      datasheet.
-*       deviceNum  -   Select on of the five device banks (defined in
-*                      Memory.h) :
-*
-*                       - DEVICE0
-*                       - DEVICE1
-*                       - DEVICE2
-*                       - etc.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memoryGetDeviceParam - This function used for getting device parameters from
-*                        DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs:        - deviceParam: STRUCT with paramiters for DEVICE BANK
-*                  PARAMETERS REGISTER
-*                - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-
-bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
-	unsigned int valueOfReg;
-	unsigned int calcData;
-
-	if (deviceNum > 4)
-		return false;
-	GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
-	calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
-	deviceParam->turnOff = calcData;	/* Turn Off */
-
-	calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
-	deviceParam->acc2First = calcData;	/* Access To First */
-
-	calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
-	deviceParam->acc2Next = calcData;	/* Access To Next */
-
-	calcData =
-		((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
-	deviceParam->ale2Wr = calcData;	/* Ale To Write */
-
-	calcData = ((0x1c000 & valueOfReg) >> 14) +
-		((BIT26 & valueOfReg) >> 23);
-	deviceParam->wrLow = calcData;	/* Write Active */
-
-	calcData = ((0xe0000 & valueOfReg) >> 17) +
-		((BIT27 & valueOfReg) >> 24);
-	deviceParam->wrHigh = calcData;	/* Write High */
-
-	calcData = ((0x300000 & valueOfReg) >> 20);
-	deviceParam->deviceWidth = (BIT0 << calcData);	/* In bytes */
-	calcData = ((0x30000000 & valueOfReg) >> 28);
-	deviceParam->badrSkew = calcData;	/* Cycles gap between BAdr
-						   toggle to read data sample. */
-	calcData = ((0x40000000 & valueOfReg) >> 30);
-	deviceParam->DPEn = calcData;	/*  Data Parity enable  */
-	return true;
-}
-
-/*******************************************************************************
-* memorySetDeviceParam - Set new parameters for a device.
-*
-*
-* DESCRIPTION:
-*       To allow interfacing with very slow devices and fast synchronous SRAMs,
-*       each device can be programed to different timing parameters. Each bank
-*       has its own parameters register. Bank width can be programmed to 8, 16,
-*       or 32-bits. Bank timing parameters can be programmed to support
-*       different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
-*       Controllers). The MV allows you to set timing parameters and width for
-*       each device through parameters register. This function set new
-*       parameters to a device Bank from the delivered structure 'deviceParam'
-*       (defined in gtMemory.h). The structure must be initialized with data
-*       prior to the use of these function.
-*
-* INPUT:
-*       deviceParam -  pointer to a structure DEVICE_PARAM (defined in
-*                      Memory.h).For details about each structure field please
-*                      see the device timing parameter section in the MV
-*                      datasheet.
-*       deviceNum  -   Select on of the five device banks (defined in
-*                      Memory.h) :
-*
-*                       - DEVICE0
-*                       - DEVICE1
-*                       - DEVICE2
-*                       - etc.
-*
-* OUTPUT:
-*       None.
-*
-* RETURN:
-*       false if one of the parameters is erroneous,true otherwise.
-*
-*******************************************************************************/
-/********************************************************************
-* memorySetDeviceParam - This function used for setting device parameters to
-*                        DEVICE BANK PARAMETERS REGISTER
-*
-*
-* Inputs:        - deviceParam: STRUCT for store paramiters from DEVICE BANK
-*                  PARAMETERS REGISTER
-*                - deviceNum : number of device
-* Returns: false if one of the parameters is erroneous,true otherwise.
-*********************************************************************/
-bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
-{
-	unsigned int valueForReg;
-
-	if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
-	    (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
-	    (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
-	    (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
-		return false;
-	}
-	valueForReg = (((deviceParam->turnOff) & 0x7) |
-		       (((deviceParam->turnOff) & 0x8) << 19) |
-		       (((deviceParam->acc2First) & 0xf) << 3) |
-		       (((deviceParam->acc2First) & 0x10) << 19) |
-		       (((deviceParam->acc2Next) & 0xf) << 7) |
-		       (((deviceParam->acc2Next) & 0x10) << 20) |
-		       (((deviceParam->ale2Wr) & 0x7) << 11) |
-		       (((deviceParam->ale2Wr) & 0xf) << 22) |
-		       (((deviceParam->wrLow) & 0x7) << 14) |
-		       (((deviceParam->wrLow) & 0xf) << 23) |
-		       (((deviceParam->wrHigh) & 0x7) << 17) |
-		       (((deviceParam->wrHigh) & 0xf) << 24) |
-		       (((deviceParam->badrSkew) & 0x3) << 28) |
-		       (((deviceParam->DPEn) & 0x1) << 30));
-
-	/* insert the device width: */
-	switch (deviceParam->deviceWidth) {
-	case 1:
-		valueForReg = valueForReg | _8BIT;
-		break;
-	case 2:
-		valueForReg = valueForReg | _16BIT;
-		break;
-	case 4:
-		valueForReg = valueForReg | _32BIT;
-		break;
-	default:
-		valueForReg = valueForReg | _8BIT;
-		break;
-	}
-	GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
-	return true;
-}
-
-/*******************************************************************************
-* MemoryDisableWindow - Disable a memory space by the disable bit.
-* DESCRIPTION:
-*       This function disables one of the 21 availiable windows dedicated for
-*       the CPU decoding mechanism. Its possible to combine several windows with
-*       the OR command.
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*******************************************************************************/
-void MemoryDisableWindow (MEMORY_WINDOW window)
-{
-	SET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryEnableWindow - Enable a memory space that was disabled by
-*                       'MemoryDisableWindow'.
-* DESCRIPTION:
-*       This function enables one of the 21 availiable windows dedicated for the
-*       CPU decoding mechanism. Its possible to combine several windows with the
-*       OR command.
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       None.
-*******************************************************************************/
-void MemoryEnableWindow (MEMORY_WINDOW window)
-{
-	RESET_REG_BITS (BASE_ADDR_ENABLE, window);
-}
-
-/*******************************************************************************
-* MemoryGetMemWindowStatus - This function check whether the memory window is
-*                              disabled or not.
-* DESCRIPTION:
-*       This function checks if the given memory window is closed .
-* INPUT:
-*       window - One or more of the memory windows (defined in gtMemory.h).
-* OUTPUT:
-*       None.
-* RETURN:
-*       true for a closed window, false otherwise .
-*******************************************************************************/
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
-{
-	if (GTREGREAD (BASE_ADDR_ENABLE) & window)
-		return MEM_WINDOW_DISABLED;
-	return MEM_WINDOW_ENABLED;
-}
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
deleted file mode 100644
index 7839b68d42..0000000000
--- a/board/Marvell/common/ns16550.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- *
- * further modified by Josh Huber <huber@mclx.com> to support
- * the DUART on the Galileo Eval board. (db64360)
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-#ifdef ZUMA_NTL
-/* no 16550 device */
-#else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
-	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
-};
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
-	volatile struct NS16550 *com_port;
-
-	com_port = (struct NS16550 *) COM_PORTS[chan];
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-	return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
-	com_port->ier = 0x00;
-	com_port->lcr = LCR_BKSE;	/* Access baud rate */
-	com_port->dll = baud_divisor & 0xff;	/* 9600 baud */
-	com_port->dlm = (baud_divisor >> 8) & 0xff;
-	com_port->lcr = LCR_8N1;	/* 8 data, 1 stop, no parity */
-	com_port->mcr = MCR_DTR | MCR_RTS;	/* RTS/DTR */
-
-	/* Clear & enable FIFOs */
-	com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR;
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
-	while ((com_port->lsr & LSR_THRE) == 0);
-	com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
-	while ((com_port->lsr & LSR_DR) == 0);
-	return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
-	return ((com_port->lsr & LSR_DR) != 0);
-}
-#endif
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
deleted file mode 100644
index 9306381353..0000000000
--- a/board/Marvell/common/ns16550.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- *
- * further modified to support the DUART in the Galileo eval board
- * modifications (c) Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- */
-
-#ifndef __NS16550_H__
-#define __NS16550_H__
-
-/* the padding is necessary because on the galileo board the UART is
-   wired in with the 3 address lines shifted over by 2 bits */
-struct NS16550
-{
-	unsigned char rbr;  /* 0 = 0-3*/
-	int pad1:24;
-
-	unsigned char ier;  /* 1 = 4-7*/
-	int pad2:24;
-
-	unsigned char fcr;  /* 2 = 8-b*/
-	int pad3:24;
-
-	unsigned char lcr;  /* 3 = c-f*/
-	int pad4:24;
-
-	unsigned char mcr;  /* 4 = 10-13*/
-	int pad5:24;
-
-	unsigned char lsr;  /* 5 = 14-17*/
-	int pad6:24;
-
-	unsigned char msr;  /* 6 =18-1b*/
-	int pad7:24;
-
-	unsigned char scr;  /* 7 =1c-1f*/
-	int pad8:24;
-} __attribute__ ((packed));
-
-/* aliases */
-#define thr rbr
-#define iir fcr
-#define dll rbr
-#define dlm ier
-
-#define FCR_FIFO_EN     0x01    /*fifo enable*/
-#define FCR_RXSR        0x02    /*receiver soft reset*/
-#define FCR_TXSR        0x04    /*transmitter soft reset*/
-
-
-#define MCR_DTR         0x01
-#define MCR_RTS         0x02
-#define MCR_DMA_EN      0x04
-#define MCR_TX_DFR      0x08
-
-
-#define LCR_WLS_MSK 0x03    /* character length slect mask*/
-#define LCR_WLS_5   0x00    /* 5 bit character length */
-#define LCR_WLS_6   0x01    /* 6 bit character length */
-#define LCR_WLS_7   0x02    /* 7 bit character length */
-#define LCR_WLS_8   0x03    /* 8 bit character length */
-#define LCR_STB     0x04    /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN     0x08    /* Parity eneble*/
-#define LCR_EPS     0x10    /* Even Parity Select*/
-#define LCR_STKP    0x20    /* Stick Parity*/
-#define LCR_SBRK    0x40    /* Set Break*/
-#define LCR_BKSE    0x80    /* Bank select enable*/
-
-#define LSR_DR      0x01    /* Data ready */
-#define LSR_OE      0x02    /* Overrun */
-#define LSR_PE      0x04    /* Parity error */
-#define LSR_FE      0x08    /* Framing error */
-#define LSR_BI      0x10    /* Break */
-#define LSR_THRE    0x20    /* Xmit holding register empty */
-#define LSR_TEMT    0x40    /* Xmitter empty */
-#define LSR_ERR     0x80    /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1     0x03
-
-
-#define COM1 0x03F8
-#define COM2 0x02F8
-
-volatile struct NS16550 * NS16550_init(int chan, int baud_divisor);
-void NS16550_putc(volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc(volatile struct NS16550 *com_port);
-int NS16550_tstc(volatile struct NS16550 *com_port);
-void NS16550_reinit(volatile struct NS16550 *com_port, int baud_divisor);
-
-typedef struct NS16550 *NS16550_t;
-
-extern const NS16550_t COM_PORTS[];
-
-#endif
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
deleted file mode 100644
index 432aa0660e..0000000000
--- a/board/Marvell/common/serial.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * (C) Copyright 2001
- * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
- *
- * modified for marvell db64360 eval board by
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * serial.c - serial support for the gal ev board
- */
-
-/* supports both the 16650 duart and the MPSC */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <linux/compiler.h>
-
-#include "../include/memory.h"
-
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_MPSC
-static int marvell_serial_init(void)
-{
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-	int clock_divisor = 230400 / gd->baudrate;
-#endif
-
-	mpsc_init (gd->baudrate);
-
-	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CONFIG_SYS_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-	return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
-	if (c == '\n')
-		mpsc_putchar ('\r');
-
-	mpsc_putchar (c);
-}
-
-static int marvell_serial_getc(void)
-{
-	return mpsc_getchar ();
-}
-
-static int marvell_serial_tstc(void)
-{
-	return mpsc_test_char ();
-}
-
-static void marvell_serial_setbrg(void)
-{
-	galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
-}
-
-#else  /* ! CONFIG_MPSC */
-
-static int marvell_serial_init(void)
-{
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
-	(void) NS16550_init (0, clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	(void) NS16550_init (1, clock_divisor);
-#endif
-	return (0);
-}
-
-static void marvell_serial_putc(const char c)
-{
-	if (c == '\n')
-		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
-	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-static int marvell_serial_getc(void)
-{
-	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static int marvell_serial_tstc(void)
-{
-	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-static void marvell_serial_setbrg(void)
-{
-	int clock_divisor = 230400 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
-	NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
-	NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-#endif /* CONFIG_MPSC */
-
-static struct serial_device marvell_serial_drv = {
-	.name	= "marvell_serial",
-	.start	= marvell_serial_init,
-	.stop	= NULL,
-	.setbrg	= marvell_serial_setbrg,
-	.putc	= marvell_serial_putc,
-	.puts	= default_serial_puts,
-	.getc	= marvell_serial_getc,
-	.tstc	= marvell_serial_tstc,
-};
-
-void marvell_serial_initialize(void)
-{
-	serial_register(&marvell_serial_drv);
-}
-
-__weak struct serial_device *default_serial_console(void)
-{
-	return &marvell_serial_drv;
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
-	serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
-	serial_puts (str);
-}
-
-int getDebugChar (void)
-{
-	return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
-	return;
-}
-#endif
diff --git a/board/Marvell/include/memory.h b/board/Marvell/include/memory.h
deleted file mode 100644
index 0947b6e4ff..0000000000
--- a/board/Marvell/include/memory.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/* Memory.h - Memory mappings and remapping functions declarations */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCmemoryh
-#define __INCmemoryh
-
-/* includes */
-
-#include "core.h"
-
-/* defines */
-
-#define DONT_MODIFY	0xffffffff
-#define PARITY_SUPPORT	0x40000000
-#define MINIMUM_MEM_BANK_SIZE		0x10000
-#define MINIMUM_DEVICE_WINDOW_SIZE	0x10000
-#define MINIMUM_PCI_WINDOW_SIZE		0x10000
-#define MINIMUM_ACCESS_WIN_SIZE		0x10000
-
-#define _8BIT		0x00000000
-#define _16BIT		0x00100000
-#define _32BIT		0x00200000
-#define _64BIT		0x00300000
-
-/* typedefs */
-
- typedef struct deviceParam
-{						/* boundary values  */
-    unsigned int    turnOff;			/* 0x0 - 0xf	    */
-    unsigned int    acc2First;			/* 0x0 - 0x1f	    */
-    unsigned int    acc2Next;		/* 0x0 - 0x1f	    */
-    unsigned int    ale2Wr;			/* 0x0 - 0xf	    */
-    unsigned int    wrLow;			/* 0x0 - 0xf	    */
-    unsigned int    wrHigh;			/* 0x0 - 0xf	    */
-    unsigned int    badrSkew;		/* 0x0 - 0x2	   */
-    unsigned int    DPEn;			/* 0x0 - 0x1	   */
-    unsigned int    deviceWidth;	/* in Bytes  */
-} DEVICE_PARAM;
-
-
-typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
-typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
-
-/*typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2,	\
-				   MEM_REGION3,MEM_REGION4,MEM_REGION5,	      \
-				   MEM_REGION6,MEM_REGION7}		      \
-				   MEMORY_PROTECT_REGION;*/
-/* There are four possible windows that can be defined as protected */
-typedef enum _memoryProtectWindow{MEM_WINDOW0,MEM_WINDOW1,MEM_WINDOW2,
-				  MEM_WINDOW3
-				 } MEMORY_PROTECT_WINDOW;
-/* When defining a protected window , this paramter indicates whether it
-   is accessible or not */
-typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN}	      \
-			    MEMORY_ACCESS;
-typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN}	      \
-			   MEMORY_ACCESS_WRITE;
-typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN}	      \
-				  MEMORY_CACHE_PROTECT;
-typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB}	      \
-			       MEMORY_SNOOP_TYPE;
-typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1,	      \
-				 MEM_SNOOP_REGION2,MEM_SNOOP_REGION3}	      \
-				 MEMORY_SNOOP_REGION;
-
-/* There are 21 memory windows dedicated for the varios interfaces (PCI,
-   devCS (devices), CS(DDR), interenal registers and SRAM) used by the CPU's
-   address decoding mechanism. */
-typedef enum _memoryWindow {CS_0_WINDOW = BIT0, CS_1_WINDOW = BIT1,
-			    CS_2_WINDOW = BIT2, CS_3_WINDOW = BIT3,
-			    DEVCS_0_WINDOW = BIT4, DEVCS_1_WINDOW = BIT5,
-			    DEVCS_2_WINDOW = BIT6, DEVCS_3_WINDOW = BIT7,
-			    BOOT_CS_WINDOW = BIT8, PCI_0_IO_WINDOW = BIT9,
-			    PCI_0_MEM0_WINDOW = BIT10,
-			    PCI_0_MEM1_WINDOW = BIT11,
-			    PCI_0_MEM2_WINDOW = BIT12,
-			    PCI_0_MEM3_WINDOW = BIT13, PCI_1_IO_WINDOW = BIT14,
-			    PCI_1_MEM0_WINDOW = BIT15, PCI_1_MEM1_WINDOW =BIT16,
-			    PCI_1_MEM2_WINDOW = BIT17, PCI_1_MEM3_WINDOW =BIT18,
-			    INTEGRATED_SRAM_WINDOW = BIT19,
-			    INTERNAL_SPACE_WINDOW = BIT20,
-			    ALL_WINDOWS = 0X1FFFFF
-			   } MEMORY_WINDOW;
-
-typedef enum _memoryWindowStatus {MEM_WINDOW_ENABLED,MEM_WINDOW_DISABLED
-				 } MEMORY_WINDOW_STATUS;
-
-
-typedef enum _pciMemWindow{PCI_0_IO,PCI_0_MEM0,PCI_0_MEM1,PCI_0_MEM2,PCI_0_MEM3
-#ifdef INCLUDE_PCI_1
-			  ,PCI_1_IO,PCI_1_MEM0,PCI_1_MEM1,PCI_1_MEM2,PCI_1_MEM3
-#endif /* INCLUDE_PCI_1 */
-			  } PCI_MEM_WINDOW;
-
-
-/* -------------------------------------------------------------------------------------------------*/
-
-/* functions */
-unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
-unsigned int memoryGetDeviceBaseAddress(DEVICE device);
-/* New at MV6436x */
-unsigned int MemoryGetPciBaseAddr(PCI_MEM_WINDOW pciWindow);
-unsigned int memoryGetBankSize(MEMORY_BANK bank);
-unsigned int memoryGetDeviceSize(DEVICE device);
-unsigned int memoryGetDeviceWidth(DEVICE device);
-/* New at MV6436x */
-unsigned int gtMemoryGetPciWindowSize(PCI_MEM_WINDOW pciWindow);
-
-/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
-bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
-/* Set a new base and size for one of the memory banks (CS0 - CS3) */
-bool gtMemorySetMemoryBank(MEMORY_BANK bank, unsigned int bankBase,
-			   unsigned int bankSize);
-bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
-
-/* Change the Internal Register Base Address to a new given Address. */
-bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
-/* returns internal Register Space Base Address. */
-unsigned int memoryGetInternalRegistersSpace(void);
-
-/* Returns the integrated SRAM Base Address. */
-unsigned int memoryGetInternalSramBaseAddr(void);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Set new base address for the integrated SRAM. */
-void memorySetInternalSramBaseAddr(unsigned int sramBaseAddress);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Delete a protection feature to a given space. */
-void memoryDisableProtectRegion(MEMORY_PROTECT_WINDOW window);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Writes a new remap value to the remap register */
-unsigned int memorySetPciRemapValue(PCI_MEM_WINDOW memoryWindow,
-				      unsigned int remapValueHigh,
-				      unsigned int remapValueLow);
-/* -------------------------------------------------------------------------------------------------*/
-
-/* Configurate the protection feature to a given space. */
-bool memorySetProtectRegion(MEMORY_PROTECT_WINDOW window,
-			      MEMORY_ACCESS gtMemoryAccess,
-			      MEMORY_ACCESS_WRITE gtMemoryWrite,
-			      MEMORY_CACHE_PROTECT cacheProtection,
-			      unsigned int baseAddress,
-			      unsigned int size);
-
-/* Configurate the protection feature to a given space. */
-/*bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
-			    MEMORY_ACCESS memoryAccess,
-			    MEMORY_ACCESS_WRITE memoryWrite,
-			    MEMORY_CACHE_PROTECT cacheProtection,
-			    unsigned int baseAddress,
-			    unsigned int regionLength); */
-/* Configurate the snoop feature to a given space. */
-bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
-			      MEMORY_SNOOP_TYPE snoopType,
-			      unsigned int baseAddress,
-			      unsigned int regionLength);
-
-bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
-bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
-/* Set a new base and size for one of the PCI windows. */
-bool memorySetPciWindow(PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
-			  unsigned int pciWindowSize);
-
-/* Disable or enable one of the 21 windows dedicated for the CPU's
-   address decoding mechanism */
-void MemoryDisableWindow(MEMORY_WINDOW window);
-void MemoryEnableWindow (MEMORY_WINDOW window);
-MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus(MEMORY_WINDOW window);
-#endif	/* __INCmemoryh */
diff --git a/board/Marvell/include/pci.h b/board/Marvell/include/pci.h
deleted file mode 100644
index 572e0d345d..0000000000
--- a/board/Marvell/include/pci.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/* PCI.h - PCI functions header file */
-
-/* Copyright - Galileo technology. */
-
-#ifndef __INCpcih
-#define __INCpcih
-
-/* includes */
-
-#include "core.h"
-#include "memory.h"
-
-/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
-#define PCI_MAX_DEVICES 22
-
-
-/* Macros */
-
-/* The next Macros configurate the initiator board (SELF) or any any agent on
-   the PCI to become: MASTER, response to MEMORY transactions , response to
-   IO transactions or TWO both MEMORY_IO transactions. Those configuration
-   are for both PCI0 and PCI1. */
-
-#define PCI_MEMORY_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_IO_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_SLAVE_ENABLE(host, deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_DISABLE(host, deviceNumber) pciWriteConfigReg(host,		       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &		     \
-	  pciReadConfigReg(host, PCI_STATUS_AND_COMMAND,deviceNumber))
-
-#define PCI_MASTER_ENABLE(host,deviceNumber) pciWriteConfigReg(host,	       \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define PCI_MASTER_DISABLE(deviceNumber) pciWriteConfigReg(host,	      \
-	  PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &		     \
-	  pciReadConfigReg(host,PCI_STATUS_AND_COMMAND,deviceNumber) )
-
-#define		MASTER_ENABLE			BIT2
-#define		MEMORY_ENABLE			BIT1
-#define		I_O_ENABLE			BIT0
-#define	    SELF		    32
-
-/* Agent on the PCI bus may have up to 6 BARS. */
-#define	    BAR0		    0x10
-#define	    BAR1		    0x14
-#define	    BAR2		    0x18
-#define	    BAR3		    0x1c
-#define	    BAR4		    0x20
-#define	    BAR5		    0x24
-#define		BAR_SEL_MEM_IO			BIT0
-#define		BAR_MEM_TYPE_32_BIT		NO_BIT
-#define		BAR_MEM_TYPE_BELOW_1M		       BIT1
-#define		BAR_MEM_TYPE_64_BIT			      BIT2
-#define		BAR_MEM_TYPE_RESERVED		      (BIT1 | BIT2)
-#define		BAR_MEM_TYPE_MASK		      (BIT1 | BIT2)
-#define		BAR_PREFETCHABLE				      BIT3
-#define		BAR_CONFIG_MASK			(BIT0 | BIT1 | BIT2 | BIT3)
-
-/* Defines for the access regions. */
-#define	    PREFETCH_ENABLE		    BIT12
-#define	    PREFETCH_DISABLE		    NO_BIT
-#define	    DELAYED_READ_ENABLE		    BIT13
-/* #define     CACHING_ENABLE		       BIT14 */
-/* aggressive prefetch: PCI slave prefetch two burst in advance*/
-#define	    AGGRESSIVE_PREFETCH		     BIT16
-/* read line aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_LINE_AGGRESSIVE_PREFETCH   BIT17
-/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/
-#define	    READ_MULTI_AGGRESSIVE_PREFETCH  BIT18
-#define	    MAX_BURST_4			    NO_BIT
-#define	    MAX_BURST_8			    BIT20  /* Bits[21:20] = 01 */
-#define	    MAX_BURST_16		    BIT21  /* Bits[21:20] = 10 */
-#define	    PCI_BYTE_SWAP		    NO_BIT /* Bits[25:24] = 00 */
-#define	    PCI_NO_SWAP			    BIT24  /* Bits[25:24] = 01 */
-#define	    PCI_BYTE_AND_WORD_SWAP	    BIT25  /* Bits[25:24] = 10 */
-#define	    PCI_WORD_SWAP		   (BIT24 | BIT25) /* Bits[25:24] = 11 */
-#define	    PCI_ACCESS_PROTECT		    BIT28
-#define	    PCI_WRITE_PROTECT		    BIT29
-
-/* typedefs */
-
-typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,
-				REGION6,REGION7} PCI_ACCESS_REGIONS;
-
-typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;
-typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;
-
-typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB}
-			    PCI_SNOOP_TYPE;
-typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,
-			      PCI_SNOOP_REGION2,PCI_SNOOP_REGION3}
-			      PCI_SNOOP_REGION;
-
-typedef enum __memPciHost{PCI_HOST0,PCI_HOST1} PCI_HOST;
-typedef enum __memPciRegion{PCI_REGION0,PCI_REGION1,
-			 PCI_REGION2,PCI_REGION3,
-			 PCI_IO}
-			 PCI_REGION;
-
-/*ronen 7/Dec/03 */
-typedef enum __pci_bar_windows{PCI_CS0_BAR, PCI_CS1_BAR, PCI_CS2_BAR,
-			       PCI_CS3_BAR, PCI_DEV_CS0_BAR, PCI_DEV_CS1_BAR,
-			       PCI_DEV_CS2_BAR, PCI_DEV_CS3_BAR, PCI_BOOT_CS_BAR,
-			       PCI_MEM_INT_REG_BAR, PCI_IO_INT_REG_BAR,
-			       PCI_P2P_MEM0_BAR, PCI_P2P_MEM1_BAR,
-			       PCI_P2P_IO_BAR, PCI_CPU_BAR, PCI_INT_SRAM_BAR,
-			       PCI_LAST_BAR} PCI_INTERNAL_BAR;
-
-typedef struct pciBar {
-    unsigned int detectBase;
-    unsigned int base;
-    unsigned int size;
-    unsigned int type;
-} PCI_BAR;
-
-typedef struct pciDevice {
-    PCI_HOST	     host;
-    char	    type[40];
-    unsigned int    deviceNum;
-    unsigned int    venID;
-    unsigned int    deviceID;
-    PCI_BAR bar[6];
-} PCI_DEVICE;
-
-typedef struct pciSelfBars {
-    unsigned int    SCS0Base;
-    unsigned int    SCS0Size;
-    unsigned int    SCS1Base;
-    unsigned int    SCS1Size;
-    unsigned int    SCS2Base;
-    unsigned int    SCS2Size;
-    unsigned int    SCS3Base;
-    unsigned int    SCS3Size;
-    unsigned int    internalMemBase;
-    unsigned int    internalIOBase;
-    unsigned int    CS0Base;
-    unsigned int    CS0Size;
-    unsigned int    CS1Base;
-    unsigned int    CS1Size;
-    unsigned int    CS2Base;
-    unsigned int    CS2Size;
-    unsigned int    CS3Base;
-    unsigned int    CS3Size;
-    unsigned int    CSBootBase;
-    unsigned int    CSBootSize;
-    unsigned int    P2PMem0Base;
-    unsigned int    P2PMem0Size;
-    unsigned int    P2PMem1Base;
-    unsigned int    P2PMem1Size;
-    unsigned int    P2PIOBase;
-    unsigned int    P2PIOSize;
-    unsigned int    CPUBase;
-    unsigned int    CPUSize;
-} PCI_SELF_BARS;
-
-/* read/write configuration registers on local PCI bus. */
-void pciWriteConfigReg(PCI_HOST host, unsigned int regOffset,
-		       unsigned int pciDevNum, unsigned int data);
-unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
-			       unsigned int pciDevNum);
-
-/* read/write configuration registers on another PCI bus. */
-void pciOverBridgeWriteConfigReg(PCI_HOST host,
-				 unsigned int regOffset,
-				 unsigned int pciDevNum,
-				 unsigned int busNum,unsigned int data);
-unsigned int pciOverBridgeReadConfigReg(PCI_HOST host,
-					unsigned int regOffset,
-					unsigned int pciDevNum,
-					unsigned int busNum);
-
-/* Performs full scane on both PCI and returns all detail possible on the
-   agents which exist on the bus. */
-void pciScanDevices(PCI_HOST host, PCI_DEVICE *pci0Detect,
-		    unsigned int numberOfElment);
-
-/*	Master`s memory space	*/
-bool pciMapSpace(PCI_HOST host, PCI_REGION region,
-		unsigned int remapBase,
-		unsigned int deviceBase,
-		unsigned int deviceLength);
-unsigned int pciGetSpaceBase(PCI_HOST host, PCI_REGION region);
-unsigned int pciGetSpaceSize(PCI_HOST host, PCI_REGION region);
-
-/*	Slave`s memory space   */
-void pciMapMemoryBank(PCI_HOST host, MEMORY_BANK bank,
-		      unsigned int pci0Dram0Base, unsigned int pci0Dram0Size);
-
-#if 0 /* GARBAGE routines - dont use till they get cleaned up */
-void pci0ScanSelfBars(PCI_SELF_BARS *pci0SelfBars);
-void pci1ScanSelfBars(PCI_SELF_BARS *pci1SelfBars);
-void pci0MapInternalRegSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegSpace(unsigned int pci1InternalBase);
-void pci0MapInternalRegIOSpace(unsigned int pci0InternalBase);
-void pci1MapInternalRegIOSpace(unsigned int pci1InternalBase);
-void pci0MapDevice0MemorySpace(unsigned int pci0Dev0Base,
-			       unsigned int pci0Dev0Length);
-void pci1MapDevice0MemorySpace(unsigned int pci1Dev0Base,
-			       unsigned int pci1Dev0Length);
-void pci0MapDevice1MemorySpace(unsigned int pci0Dev1Base,
-			       unsigned int pci0Dev1Length);
-void pci1MapDevice1MemorySpace(unsigned int pci1Dev1Base,
-			       unsigned int pci1Dev1Length);
-void pci0MapDevice2MemorySpace(unsigned int pci0Dev2Base,
-			       unsigned int pci0Dev2Length);
-void pci1MapDevice2MemorySpace(unsigned int pci1Dev2Base,
-			       unsigned int pci1Dev2Length);
-void pci0MapDevice3MemorySpace(unsigned int pci0Dev3Base,
-			       unsigned int pci0Dev3Length);
-void pci1MapDevice3MemorySpace(unsigned int pci1Dev3Base,
-			       unsigned int pci1Dev3Length);
-void pci0MapBootDeviceMemorySpace(unsigned int pci0DevBootBase,
-				  unsigned int pci0DevBootLength);
-void pci1MapBootDeviceMemorySpace(unsigned int pci1DevBootBase,
-				  unsigned int pci1DevBootLength);
-void pci0MapP2pMem0Space(unsigned int pci0P2pMem0Base,
-			 unsigned int pci0P2pMem0Length);
-void pci1MapP2pMem0Space(unsigned int pci1P2pMem0Base,
-			 unsigned int pci1P2pMem0Length);
-void pci0MapP2pMem1Space(unsigned int pci0P2pMem1Base,
-			 unsigned int pci0P2pMem1Length);
-void pci1MapP2pMem1Space(unsigned int pci1P2pMem1Base,
-			 unsigned int pci1P2pMem1Length);
-void pci0MapP2pIoSpace(unsigned int pci0P2pIoBase,
-		       unsigned int pci0P2pIoLength);
-void pci1MapP2pIoSpace(unsigned int pci1P2pIoBase,
-		       unsigned int pci1P2pIoLength);
-
-void pci0MapCPUspace(unsigned int pci0CpuBase, unsigned int pci0CpuLengs);
-void pci1MapCPUspace(unsigned int pci1CpuBase, unsigned int pci1CpuLengs);
-#endif
-
-/* PCI region options */
-
-bool  pciSetRegionFeatures(PCI_HOST host, PCI_ACCESS_REGIONS region,
-	unsigned int features, unsigned int baseAddress,
-	unsigned int regionLength);
-
-void  pciDisableAccessRegion(PCI_HOST host, PCI_ACCESS_REGIONS region);
-
-/* PCI arbiter */
-
-bool pciArbiterEnable(PCI_HOST host);
-bool pciArbiterDisable(PCI_HOST host);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciSetArbiterAgentsPriority(PCI_HOST host, PCI_AGENT_PRIO internalAgent,
-				  PCI_AGENT_PRIO externalAgent0,
-				  PCI_AGENT_PRIO externalAgent1,
-				  PCI_AGENT_PRIO externalAgent2,
-				  PCI_AGENT_PRIO externalAgent3,
-				  PCI_AGENT_PRIO externalAgent4,
-				  PCI_AGENT_PRIO externalAgent5);
-bool pciParkingDisable(PCI_HOST host, PCI_AGENT_PARK internalAgent,
-			PCI_AGENT_PARK externalAgent0,
-			PCI_AGENT_PARK externalAgent1,
-			PCI_AGENT_PARK externalAgent2,
-			PCI_AGENT_PARK externalAgent3,
-			PCI_AGENT_PARK externalAgent4,
-			PCI_AGENT_PARK externalAgent5);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-bool pciEnableBrokenAgentDetection(PCI_HOST host, unsigned char brokenValue);
-
-/* PCI-to-PCI (P2P) */
-
-bool pciP2PConfig(PCI_HOST host,
-		  unsigned int SecondBusLow,unsigned int SecondBusHigh,
-		  unsigned int busNum,unsigned int devNum);
-/* PCI Cache-coherency */
-
-bool pciSetRegionSnoopMode(PCI_HOST host, PCI_SNOOP_REGION region,
-			    PCI_SNOOP_TYPE snoopType,
-			    unsigned int baseAddress,
-			    unsigned int regionLength);
-
-PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
-
-#endif /* __INCpcih */
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
index ee1681b5db..55d0bc80c0 100644
--- a/board/a3m071/a3m071.c
+++ b/board/a3m071/a3m071.c
@@ -391,14 +391,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #ifdef CONFIG_SPL_OS_BOOT
 /*
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
index c5d161bca3..20d8b80f7e 100644
--- a/board/a4m072/a4m072.c
+++ b/board/a4m072/a4m072.c
@@ -170,14 +170,14 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 int board_eth_init(bd_t *bis)
 {
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index c5cc4ffa69..dc2e3ba3a0 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -489,7 +489,7 @@ int misc_init_r(void)
 }
 #endif	/* !defined(CONFIG_ARCHES) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 extern int __ft_board_setup(void *blob, bd_t *bd);
 
 int ft_board_setup(void *blob, bd_t *bd)
@@ -518,4 +518,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 7b7cd2c426..6398bcbc9e 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -212,7 +212,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index af68e10390..04e5812db3 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -191,7 +191,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #ifndef CONFIG_SYS_NO_FLASH
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 4c6431266f..6871916865 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -272,7 +272,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
index d3555bbdf6..fc4f50d219 100644
--- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c
+++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c
@@ -124,7 +124,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20);
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 9ef2864bb1..994f246078 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -151,7 +151,7 @@ void lcd_show_board_info(void)
 		dram_size += gd->bd->bi_dram[i].size;
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 		dram_size >> 20,
 		nand_size >> 20 );
diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index c14df303b2..b0d440d728 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -196,7 +196,7 @@ void lcd_show_board_info(void)
 			dram_size += gd->bd->bi_dram[i].size;
 		nand_size = 0;
 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-			nand_size += nand_info[i].size;
+			nand_size += nand_info[i]->size;
 		lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 			dram_size >> 20,
 			nand_size >> 20);
diff --git a/board/atmel/sama5d2_ptc/Kconfig b/board/atmel/sama5d2_ptc/Kconfig
new file mode 100644
index 0000000000..d2661c689a
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SAMA5D2_PTC
+
+config SYS_BOARD
+	default "sama5d2_ptc"
+
+config SYS_VENDOR
+	default "atmel"
+
+config SYS_SOC
+	default "at91"
+
+config SYS_CONFIG_NAME
+	default "sama5d2_ptc"
+
+endif
diff --git a/board/atmel/sama5d2_ptc/MAINTAINERS b/board/atmel/sama5d2_ptc/MAINTAINERS
new file mode 100644
index 0000000000..7ab03d6eaf
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/MAINTAINERS
@@ -0,0 +1,7 @@
+SAMA5D2 PTC Engineering BOARD
+M:	Wenyou Yang <wenyou.yang@atmel.com>
+S:	Maintained
+F:	board/atmel/sama5d2_ptc/
+F:	include/configs/sama5d2_ptc.h
+F:	configs/sama5d2_ptc_spiflash_defconfig
+F:	configs/sama5d2_ptc_nandflash_defconfig
diff --git a/board/atmel/sama5d2_ptc/Makefile b/board/atmel/sama5d2_ptc/Makefile
new file mode 100644
index 0000000000..1fe0392da0
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Atmel
+#		     Wenyou Yang <wenyou.yang@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += sama5d2_ptc.o
diff --git a/board/atmel/sama5d2_ptc/sama5d2_ptc.c b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
new file mode 100644
index 0000000000..9e6544bc07
--- /dev/null
+++ b/board/atmel/sama5d2_ptc/sama5d2_ptc.c
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou.Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <atmel_hlcdc.h>
+#include <lcd.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <spi.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
+#include <asm/arch/atmel_sdhci.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama5_sfr.h>
+#include <asm/arch/sama5d2.h>
+#include <asm/arch/sama5d3_smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+}
+
+static void board_spi0_hw_init(void)
+{
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 14, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 15, 0);
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 16, 0);
+
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 17, 1);
+
+	at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+
+static void board_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	at91_periph_clk_enable(ATMEL_ID_HSMC);
+
+	writel(AT91_SFR_EBICFG_DRIVE0_HIGH |
+	       AT91_SFR_EBICFG_PULL0_NONE |
+	       AT91_SFR_EBICFG_DRIVE1_HIGH |
+	       AT91_SFR_EBICFG_PULL1_NONE, &sfr->ebicfg);
+
+	/* Configure SMC CS3 for NAND */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
+	       AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
+	       AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3) |
+	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 0, 0);	/* D0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 1, 0);	/* D1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 2, 0);	/* D2 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 3, 0);	/* D3 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 4, 0);	/* D4 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 5, 0);	/* D5 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 6, 0);	/* D6 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 7, 0);	/* D7 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 12, 0);	/* RE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 8, 0);	/* WE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 9, 1);	/* NCS */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 21, 1);	/* RDY */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 10, 1);	/* ALE */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTA, 11, 1);	/* CLE */
+}
+
+static void board_usb_hw_init(void)
+{
+	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 28, 1);
+}
+
+static void board_gmac_hw_init(void)
+{
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 14, 0);	/* GTXCK */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 15, 0);	/* GTXEN */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 16, 0);	/* GRXDV */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 17, 0);	/* GRXER */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 18, 0);	/* GRX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 19, 0);	/* GRX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 20, 0);	/* GTX0 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 21, 0);	/* GTX1 */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 22, 0);	/* GMDC */
+	atmel_pio4_set_f_periph(AT91_PIO_PORTB, 23, 0);	/* GMDIO */
+
+	at91_periph_clk_enable(ATMEL_ID_GMAC);
+}
+
+static void board_uart0_hw_init(void)
+{
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, 1);	/* URXD0 */
+	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
+
+	at91_periph_clk_enable(CONFIG_USART_ID);
+}
+
+int board_early_init_f(void)
+{
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+	board_uart0_hw_init();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_ATMEL_SPI
+	board_spi0_hw_init();
+#endif
+#ifdef CONFIG_NAND_ATMEL
+	board_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	board_gmac_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	board_usb_hw_init();
+#endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	at91_udp_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
+	if (rc)
+		printf("GMAC register failed\n");
+#endif
+
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+	usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+	usb_eth_initialize(bis);
+#endif
+#endif
+
+	return rc;
+}
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+	board_spi0_hw_init();
+#endif
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+	board_nand_hw_init();
+#endif
+}
+
+static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
+{
+	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
+
+	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
+		    ATMEL_MPDDRC_CR_DIC_DS |
+		    ATMEL_MPDDRC_CR_DIS_DLL |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+	ddrc->rtr = 0x511;
+
+	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
+		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
+
+	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
+		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
+		      (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
+
+	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
+		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
+		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
+		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
+}
+
+void mem_init(void)
+{
+	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	struct atmel_mpddrc_config ddrc_config;
+	u32 reg;
+
+	ddrc_conf(&ddrc_config);
+
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	at91_system_clk_enable(AT91_PMC_DDR);
+
+	reg = readl(&mpddrc->io_calibr);
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
+	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
+	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
+	writel(reg, &mpddrc->io_calibr);
+
+	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
+	       &mpddrc->rd_data_path);
+
+	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
+
+	writel(0x3, &mpddrc->cal_mr4);
+	writel(64, &mpddrc->tim_cal);
+}
+
+void at91_pmc_init(void)
+{
+	at91_plla_init(AT91_PMC_PLLAR_29 |
+		       AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+		       AT91_PMC_PLLXR_MUL(82) |
+		       AT91_PMC_PLLXR_DIV(1));
+
+	at91_pllicpr_init(0);
+
+	at91_mck_init(AT91_PMC_MCKR_H32MXDIV |
+		      AT91_PMC_MCKR_PLLADIV_2 |
+		      AT91_PMC_MCKR_MDIV_3 |
+		      AT91_PMC_MCKR_CSS_PLLA);
+}
+#endif
diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
index 10edf28a9b..93df7ba32a 100644
--- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c
+++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c
@@ -171,10 +171,11 @@ static void board_sdhci0_hw_init(void)
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 9, 0);	/* SDMMC0_DAT7 */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 10, 0);	/* SDMMC0_RSTN */
 	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 11, 0);	/* SDMMC0_VDDSEL */
+	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* SDMMC0_CD */
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC0,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 static void board_sdhci1_hw_init(void)
@@ -190,7 +191,7 @@ static void board_sdhci1_hw_init(void)
 
 	at91_periph_clk_enable(ATMEL_ID_SDMMC1);
 	at91_enable_periph_generated_clk(ATMEL_ID_SDMMC1,
-					 GCK_CSS_PLLA_CLK, 1);
+					 GCK_CSS_UPLL_CLK, 1);
 }
 
 int board_mmc_init(bd_t *bis)
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index e8ee612036..fa90270b86 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -207,7 +207,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index f4eef9609f..23ec274468 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -191,7 +191,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index aee621789e..72bad23087 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -187,7 +187,7 @@ void lcd_show_board_info(void)
 	nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 #endif
 	lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
 		   dram_size >> 20, nand_size >> 20);
diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
index 1704627112..106be9b761 100644
--- a/board/avionic-design/common/tamonten-ng.c
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -42,12 +42,12 @@ void pinmux_init(void)
 void gpio_early_init(void)
 {
 	/* Turn on the alive signal */
-	gpio_request(GPIO_PV2, "ALIVE");
-	gpio_direction_output(GPIO_PV2, 1);
+	gpio_request(TEGRA_GPIO(V, 2), "ALIVE");
+	gpio_direction_output(TEGRA_GPIO(V, 2), 1);
 
 	/* Remove the reset on the external periph */
-	gpio_request(GPIO_PI4, "nRST_PERIPH");
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH");
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 
 void pmu_write(uchar reg, uchar data)
@@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void)
 	pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
 
 	/* Switch the power on */
-	gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
-	gpio_direction_output(GPIO_PJ2, 1);
+	gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC");
+	gpio_direction_output(TEGRA_GPIO(J, 2), 1);
 }
 
 /*
diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c
index 9c8677943a..4fb36a2cf8 100644
--- a/board/avionic-design/common/tamonten.c
+++ b/board/avionic-design/common/tamonten.c
@@ -23,8 +23,8 @@
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 void gpio_early_init(void)
 {
-	gpio_request(GPIO_PI4, NULL);
-	gpio_direction_output(GPIO_PI4, 1);
+	gpio_request(TEGRA_GPIO(I, 4), NULL);
+	gpio_direction_output(TEGRA_GPIO(I, 4), 1);
 }
 #endif
 
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
new file mode 100644
index 0000000000..c71af11c1c
--- /dev/null
+++ b/board/bosch/shc/Kconfig
@@ -0,0 +1,87 @@
+if TARGET_AM335X_SHC
+
+config SYS_BOARD
+	default "shc"
+
+config SYS_VENDOR
+	default "bosch"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "am335x_shc"
+
+choice
+	prompt "enable different boot versions for the shc board"
+	default EMMC
+	help
+	  Select the boot version of the shc board.
+
+config SHC_EMMC
+	bool "enable eMMC"
+	help
+	  enable here the eMMC functionality on the bosch shc board.
+
+config SHC_ICT
+	bool "enable ICT"
+	help
+	  enable here the ICT functionality on the bosch shc board
+
+config SHC_NETBOOT
+	bool "enable NETBOOT"
+	help
+	  enable here the NETBOOT functionality on the bosch shc board
+
+config SHC_SDBOOT
+	bool "enable SDBOOT"
+	help
+	  enable here the SDBOOT functionality on the bosch shc board
+
+endchoice
+
+choice
+	prompt "enable different board versions for the shc board"
+	default C3_SAMPLE
+	help
+	  Select the board version of the shc board.
+
+config B_SAMPLE
+	bool "B Sample board version"
+	help
+	  activate, if you want to build for the B sample version
+	  of the bosch shc board
+
+config B2_SAMPLE
+	bool "B2 Sample board version"
+	help
+	  activate, if you want to build for the B2 sample version
+	  of the bosch shc board
+
+config C_SAMPLE
+	bool "C Sample board version"
+	help
+	  activate, if you want to build for the C sample version
+	  of the bosch shc board
+
+config C2_SAMPLE
+	bool "C2 Sample board version"
+	help
+	  activate, if you want to build for the C2 sample version
+	  of the bosch shc board
+
+config C3_SAMPLE
+	bool "C3 Sample board version"
+	help
+	  activate, if you want to build for the C3 sample version
+	  of the bosch shc board
+
+config SERIES
+	bool "Series board version"
+	help
+	  activate, if you want to build for the Series version
+	  of the bosch shc board
+
+endchoice
+
+endif
diff --git a/board/bosch/shc/MAINTAINERS b/board/bosch/shc/MAINTAINERS
new file mode 100644
index 0000000000..ae3c0355c0
--- /dev/null
+++ b/board/bosch/shc/MAINTAINERS
@@ -0,0 +1,11 @@
+SHC BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/bosch/shc
+F:	include/configs/am335x_shc.h
+F:	configs/am335x_shc_defconfig
+F:	configs/am335x_shc_ict_defconfig
+F:	configs/am335x_shc_netboot_defconfig
+F:	configs/am335x_shc_prompt_defconfig
+F:	configs/am335x_shc_sdboot_defconfig
+F:	configs/am335x_shc_sdboot_prompt_defconfig
diff --git a/board/bosch/shc/Makefile b/board/bosch/shc/Makefile
new file mode 100644
index 0000000000..4fec2bff29
--- /dev/null
+++ b/board/bosch/shc/Makefile
@@ -0,0 +1,10 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mux.o
+obj-y	+= board.o
diff --git a/board/bosch/shc/README b/board/bosch/shc/README
new file mode 100644
index 0000000000..2f206e0d55
--- /dev/null
+++ b/board/bosch/shc/README
@@ -0,0 +1,114 @@
+Summary
+=======
+
+This document covers various features of the 'am335x_shc' build.
+
+Hardware
+========
+
+AM335X based board:
+
+I2C:   ready
+DRAM:  512 MiB
+Enabling the D-Cache
+MMC:   OMAP SD/MMC: 0 @ 26 MHz, OMAP SD/MMC: 1 @ 26 MHz
+Net:   cpsw
+
+Following boot options are possible:
+
+2 Jumpers:
+
+Jumper 1 Jumper 2 Bootmode
+off      off    eMMC boot
+on       off    SD boot
+off      on     Net boot
+
+Compiling
+=========
+
+$ make am335x_shc_defconfig
+  HOSTCC  scripts/basic/fixdep
+  HOSTCC  scripts/kconfig/conf.o
+  SHIPPED scripts/kconfig/zconf.tab.c
+  SHIPPED scripts/kconfig/zconf.lex.c
+  SHIPPED scripts/kconfig/zconf.hash.c
+  HOSTCC  scripts/kconfig/zconf.tab.o
+  HOSTLD  scripts/kconfig/conf
+#
+# configuration written to .config
+#
+$ make -s all
+
+-> now you have the MLO and the u-boot.img file, you can put
+on your SD card or eMMC.
+
+Configuring
+===========
+
+There are a lot of board versions and boot configurations, which
+can be selected through "make menuconfig"
+
+ARM architecture  --->
+  enable different boot versions for the shc board (enable eMMC)  --->
+   (X) enable eMMC
+   ( ) enable ICT
+   ( ) enable NETBOOT
+   ( ) enable SDBOOT
+
+  enable different board versions for the shc board (C3 Sample board version)  --->
+   ( ) B Sample board version
+   ( ) B2 Sample board version
+   ( ) C Sample board version
+   ( ) C2 Sample board version
+   (X) C3 Sample board version
+   ( ) Series board version
+
+Netboot
+=======
+- see also doc/SPL/README.am335x-network
+
+- set the jumper into netboot mode
+- compile the U-boot sources with:
+  make am335x_shc_netboot_defconfig
+  make all
+- copy the images into your tftp boot directory
+  cp spl/u-boot-spl.bin /tftpboot/.../u-boot-spl-restore.bin
+  cp u-boot.img /tftpboot/.../u-boot-restore.img
+- power on the board, and you should get something like this:
+
+U-Boot SPL 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18)
+#### NETBOOT ####
+SHC
+MPU reference clock runs at 6 MHz
+Setting MPU clock to 594 MHz
+Enabling Spread Spectrum of 18 permille for MPU
+Trying to boot from net
+Using default environment
+
+<ethaddr> not set. Validating first E-fuse MAC
+cpsw
+cpsw Waiting for PHY auto negotiation to complete... done
+link up on port 0, speed 100, full duplex
+BOOTP broadcast 1
+BOOTP broadcast 2
+DHCP client bound to address 192.168.20.91 (258 ms)
+Using cpsw device
+TFTP from server 192.168.1.1; our IP address is 192.168.20.91
+Filename 'shc/u-boot-restore.img'.
+Load address: 0x807fffc0
+Loading: ##################
+         1.2 MiB/s
+done
+Bytes transferred = 262480 (40150 hex)
+
+
+U-Boot 2016.05-rc2-00016-gf23b960-dirty (Apr 26 2016 - 09:02:18 +0200)
+
+       Watchdog enabled
+I2C:   ready
+DRAM:  512 MiB
+MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
+*** Warning - bad CRC, using default environment
+
+Net:   cpsw
+switch to partitions #0, OK
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
new file mode 100644
index 0000000000..e90693feea
--- /dev/null
+++ b/board/bosch/shc/board.c
@@ -0,0 +1,648 @@
+/*
+ * board.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Board functions for TI AM335X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
+#include <power/tps65217.h>
+#include <environment.h>
+#include <watchdog.h>
+#include <environment.h>
+#include "mmc.h"
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD) || \
+	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+#endif
+static struct shc_eeprom __attribute__((section(".data"))) header;
+static int shc_eeprom_valid;
+
+/*
+ * Read header information from EEPROM into global structure.
+ */
+static int read_eeprom(void)
+{
+	/* Check if baseboard eeprom is available */
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -ENODEV;
+	}
+
+	/* read the eeprom using i2c */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
+		     sizeof(header))) {
+		puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+
+	if (header.magic != HDR_MAGIC) {
+		printf("Incorrect magic number (0x%x) in EEPROM\n",
+		       header.magic);
+		return -EIO;
+	}
+
+	shc_eeprom_valid = 1;
+
+	return 0;
+}
+
+static void shc_request_gpio(void)
+{
+	gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
+	gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
+	gpio_request(RESET_GPIO, "reset");
+	gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
+	gpio_request(WIFI_RST_GPIO, "WIFI rst");
+	gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
+	gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
+	gpio_request(ENOC_RST_GPIO, "ENOC rst");
+#if defined CONFIG_B_SAMPLE
+	gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
+	gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
+	gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
+	gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
+#else
+	gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
+	gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
+	gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
+	gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
+	gpio_request(LED_PWM_GPIO, "LED PWM");
+	gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
+#endif
+	gpio_request(BACK_BUTTON_GPIO, "Back button");
+	gpio_request(FRONT_BUTTON_GPIO, "Front button");
+}
+
+/*
+ * Function which forces all installed modules into running state for ICT
+ * testing. Called by SPL.
+ */
+static void __maybe_unused force_modules_running(void)
+{
+	/* Wi-Fi power regulator enable - high = enabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 1);
+	/*
+	 * Wait for Wi-Fi power regulator to reach a stable voltage
+	 * (soft-start time, max. 350 µs)
+	 */
+	__udelay(350);
+
+	/* Wi-Fi module reset - high = running */
+	gpio_direction_output(WIFI_RST_GPIO, 1);
+
+	/* ZigBee reset - high = running */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 1);
+
+	/* BidCos reset - high = running */
+	gpio_direction_output(BIDCOS_RST_GPIO, 1);
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - high = running */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 1);
+#endif
+
+	/* EnOcean reset - low = running */
+	gpio_direction_output(ENOC_RST_GPIO, 0);
+}
+
+/*
+ * Function which forces all installed modules into reset - to be released by
+ * the OS, called by SPL
+ */
+static void __maybe_unused force_modules_reset(void)
+{
+	/* Wi-Fi module reset - low = reset */
+	gpio_direction_output(WIFI_RST_GPIO, 0);
+
+	/* Wi-Fi power regulator enable - low = disabled */
+	gpio_direction_output(WIFI_REGEN_GPIO, 0);
+
+	/* ZigBee reset - low = reset */
+	gpio_direction_output(ZIGBEE_RST_GPIO, 0);
+
+	/* BidCos reset - low = reset */
+	/*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
+
+#if !defined(CONFIG_B_SAMPLE)
+	/* Z-Wave reset - low = reset */
+	gpio_direction_output(Z_WAVE_RST_GPIO, 0);
+#endif
+
+	/* EnOcean reset - high = reset*/
+	gpio_direction_output(ENOC_RST_GPIO, 1);
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader booting"
+ */
+static void __maybe_unused leds_set_booting(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_CONN_RD_GPIO, 1);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+	/* Turn all red LEDs on */
+	gpio_direction_output(LED_PWR_RD_GPIO, 1);
+	gpio_direction_output(LED_LAN_RD_GPIO, 1);
+	gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
+
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader error"
+ */
+static void leds_set_failure(int state)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all blue and green LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_CONN_RD_GPIO, state);
+
+#else /* All other SHCs starting with B2-Sample */
+	/* Set the PWM GPIO */
+	gpio_direction_output(LED_PWM_GPIO, 1);
+
+	/* Turn all blue LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+
+	/* Turn all red LEDs to 'state' */
+	gpio_set_value(LED_PWR_RD_GPIO, state);
+	gpio_set_value(LED_LAN_RD_GPIO, state);
+	gpio_set_value(LED_CLOUD_RD_GPIO, state);
+#endif
+}
+
+/*
+ * Function to set the LEDs in the state "Bootloader finished"
+ */
+static void leds_set_finish(void)
+{
+#if defined(CONFIG_B_SAMPLE)
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_PWR_GN_GPIO, 0);
+	gpio_set_value(LED_CONN_BL_GPIO, 0);
+	gpio_set_value(LED_CONN_RD_GPIO, 0);
+	gpio_set_value(LED_CONN_GN_GPIO, 0);
+#else /* All other SHCs starting with B2-Sample */
+	/* Turn all LEDs off */
+	gpio_set_value(LED_PWR_BL_GPIO, 0);
+	gpio_set_value(LED_PWR_RD_GPIO, 0);
+	gpio_set_value(LED_LAN_BL_GPIO, 0);
+	gpio_set_value(LED_LAN_RD_GPIO, 0);
+	gpio_set_value(LED_CLOUD_BL_GPIO, 0);
+	gpio_set_value(LED_CLOUD_RD_GPIO, 0);
+
+	/* Turn off the PWM GPIO and mux it to EHRPWM */
+	gpio_set_value(LED_PWM_GPIO, 0);
+	enable_shc_board_pwm_pin_mux();
+#endif
+}
+
+static void check_button_status(void)
+{
+	ulong value;
+	gpio_direction_input(FRONT_BUTTON_GPIO);
+	value = gpio_get_value(FRONT_BUTTON_GPIO);
+
+	if (value == 0) {
+		printf("front button activated !\n");
+		setenv("harakiri", "1");
+	}
+}
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+	return 1;
+}
+#endif
+
+static void shc_board_early_init(void)
+{
+	shc_request_gpio();
+# ifdef CONFIG_SHC_ICT
+	/* Force all modules into enabled state for ICT testing */
+	force_modules_running();
+# else
+	/* Force all modules to enter Reset state until released by the OS */
+	force_modules_reset();
+# endif
+	leds_set_booting();
+}
+
+#define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
+#define OSC	(V_OSCK/1000000)
+/* Bosch: Predivider must be fixed to 4, so N = 4-1 */
+#define MPUPLL_N        (4-1)
+/* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
+#define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
+
+const struct dpll_params dpll_ddr_shc = {
+		400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr_shc;
+}
+
+/*
+ * As we enabled downspread SSC with 1.8%, the values needed to be corrected
+ * such that the 20% overshoot will not lead to too high frequencies.
+ * In all cases, this is achieved by subtracting one from M (6 MHz less).
+ * Example: 600 MHz CPU
+ *   Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
+ *   600 MHz - 6 MHz (1x Fref) = 594 MHz
+ *   SSC: 594 MHz * 1.8% = 10.7 MHz SSC
+ *   Overshoot: 10.7 MHz * 20 % = 2.2 MHz
+ *   --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
+ */
+const struct dpll_params dpll_mpu_shc_opp100 = {
+		99, MPUPLL_N, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	int sil_rev;
+	int mpu_vdd;
+
+	puts(BOARD_ID_STR);
+
+	/*
+	 * Set CORE Frequency to OPP100
+	 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
+	 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	if (sil_rev < 2) {
+		puts("We do not support Silicon Revisions below 2.0!\n");
+		return;
+	}
+
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+	if (i2c_probe(TPS65217_CHIP_PM))
+		return;
+
+	/*
+	 * Retrieve the CPU max frequency by reading the efuse
+	 * SHC-Default: 600 MHz
+	 */
+	switch (dpll_mpu_opp100.m) {
+	case MPUPLL_M_1000:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
+		break;
+	case MPUPLL_M_800:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
+		break;
+	case MPUPLL_M_720:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
+		break;
+	case MPUPLL_M_600:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
+		break;
+	case MPUPLL_M_300:
+		mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
+		break;
+	default:
+		puts("Cannot determine the frequency, failing!\n");
+		return;
+	}
+
+	if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
+		puts("tps65217_voltage_update failure\n");
+		return;
+	}
+
+	/* Set MPU Frequency to what we detected */
+	printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
+	printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
+	       dpll_mpu_shc_opp100.m);
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
+
+	/* Enable Spread Spectrum for this freq to be clean on EMI side */
+	set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
+
+	/*
+	 * Using the default voltages for the PMIC (TPS65217D)
+	 * LS1 = 1.8V (VDD_1V8)
+	 * LS2 = 3.3V (VDD_3V3A)
+	 * LDO1 = 1.8V (VIO and VRTC)
+	 * LDO2 = 3.3V (VDD_3V3AUX)
+	 */
+	shc_board_early_init();
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_shc_board_pin_mux();
+}
+
+const struct ctrl_ioregs ioregs_evmsk = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_shc_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_shc_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+	/* Configure the DDR3 RAM */
+	config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
+		   &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+#if defined(CONFIG_HW_WATCHDOG)
+	hw_watchdog_init();
+#endif
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	if (read_eeprom() < 0)
+		puts("EEPROM Content Invalid.\n");
+
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
+	gpmc_init();
+#endif
+	shc_request_gpio();
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	check_button_status();
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	if (shc_eeprom_valid)
+		if (is_valid_ethaddr(header.mac_addr))
+			eth_setenv_enetaddr("ethaddr", header.mac_addr);
+#endif
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_DM_ETH
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slaves[] = {
+	{
+		.slave_reg_ofs	= 0x208,
+		.sliver_reg_ofs	= 0xd80,
+		.phy_addr	= 0,
+	},
+	{
+		.slave_reg_ofs	= 0x308,
+		.sliver_reg_ofs	= 0xdc0,
+		.phy_addr	= 1,
+	},
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= cpsw_slaves,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+#endif
+
+/*
+ * This function will:
+ * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
+ * in the environment
+ * Perform fixups to the PHY present on certain boards.  We only need this
+ * function in:
+ * - SPL with either CPSW or USB ethernet support
+ * - Full U-Boot, with either CPSW or USB ethernet
+ * Build in only these cases to avoid warnings about unused variables
+ * when we build an SPL that has neither option but full U-Boot will.
+ */
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
+	defined(CONFIG_SPL_USBETH_SUPPORT)) && \
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	uint8_t mac_addr[6];
+	uint32_t mac_hi, mac_lo;
+
+	/* try reading mac address from efuse */
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	mac_addr[0] = mac_hi & 0xFF;
+	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
+	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
+	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
+	mac_addr[4] = mac_lo & 0xFF;
+	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
+
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+	if (!getenv("ethaddr")) {
+		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
+
+		if (is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	writel(MII_MODE_ENABLE, &cdev->miisel);
+	cpsw_slaves[0].phy_if =	PHY_INTERFACE_MODE_MII;
+	cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+#endif
+
+#if defined(CONFIG_USB_ETHER) && \
+	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
+	if (is_valid_ethaddr(mac_addr))
+		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
+
+	rv = usb_eth_initialize(bis);
+	if (rv < 0)
+		printf("Error %d registering USB_ETHER\n", rv);
+	else
+		n += rv;
+#endif
+	return n;
+}
+#endif
+
+#endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+static void bosch_check_reset_pin(void)
+{
+	if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
+		printf("Resetting ...\n");
+		writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+		disable_interrupts();
+		reset_cpu(0);
+		/*NOTREACHED*/
+	}
+}
+
+static void hang_bosch(const char *cause, int code)
+{
+	int lv;
+
+	gpio_direction_input(RESET_GPIO);
+
+	/* Enable reset pin interrupt on falling edge */
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
+	writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
+	enable_interrupts();
+
+	puts(cause);
+	for (;;) {
+		for (lv = 0; lv < code; lv++) {
+			bosch_check_reset_pin();
+			leds_set_failure(1);
+			__udelay(150 * 1000);
+			leds_set_failure(0);
+			__udelay(150 * 1000);
+		}
+#if defined(BLINK_CODE)
+		__udelay(300 * 1000);
+#endif
+	}
+}
+
+void show_boot_progress(int val)
+{
+	switch (val) {
+	case BOOTSTAGE_ID_NEED_RESET:
+		hang_bosch("need reset", 4);
+		break;
+	}
+}
+#endif
+
+void arch_preboot_os(void)
+{
+	leds_set_finish();
+}
+
+#if defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
+	ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+	if (ret)
+		return ret;
+
+	ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
+	return ret;
+}
+#endif
diff --git a/board/bosch/shc/board.h b/board/bosch/shc/board.h
new file mode 100644
index 0000000000..46167fe59e
--- /dev/null
+++ b/board/bosch/shc/board.h
@@ -0,0 +1,187 @@
+/*
+ * board.h
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/* Definition to control the GPIOs (for LEDs and Reset) */
+#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
+
+static inline int board_is_b_sample(void)
+{
+#if defined CONFIG_B_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c_sample(void)
+{
+#if defined CONFIG_C_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_c3_sample(void)
+{
+#if defined CONFIG_C3_SAMPLE
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+static inline int board_is_series(void)
+{
+#if defined CONFIG_SERIES
+	return 1;
+#else
+	return 0;
+#endif
+}
+
+/*
+ * Definitions for pinmuxing header and Board ID strings
+ */
+#if defined CONFIG_B_SAMPLE
+# define BOARD_ID_STR "SHC B-Sample\n"
+#elif defined CONFIG_B2_SAMPLE
+# define BOARD_ID_STR "SHC B2-Sample\n"
+#elif defined CONFIG_C_SAMPLE
+# if defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C-Sample\n"
+# endif
+#elif defined CONFIG_C2_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C2-Sample\n"
+# endif
+#elif defined CONFIG_C3_SAMPLE
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
+# else
+#  define BOARD_ID_STR "SHC C3-Sample\n"
+# endif
+#elif defined CONFIG_SERIES
+# if defined(CONFIG_SHC_ICT)
+#  define BOARD_ID_STR "#### ICT ####\nSHC\n"
+# elif defined(CONFIG_SHC_NETBOOT)
+#  define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
+# elif defined(CONFIG_SHC_SDBOOT)
+#  define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
+# else
+#  define BOARD_ID_STR "SHC\n"
+# endif
+#else
+# define BOARD_ID_STR "Unknown device!\n"
+#endif
+
+/*
+ * Definitions for GPIO pin assignments
+ */
+#if defined CONFIG_B_SAMPLE
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(1, 18)
+# define LED_PWR_GN_GPIO   GPIO_TO_PIN(1, 19)
+# define LED_CONN_BL_GPIO  GPIO_TO_PIN(0, 26)
+# define LED_CONN_RD_GPIO  GPIO_TO_PIN(0, 22)
+# define LED_CONN_GN_GPIO  GPIO_TO_PIN(0, 23)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(0, 12)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#else
+
+# define LED_PWR_BL_GPIO   GPIO_TO_PIN(0, 22)
+# define LED_PWR_RD_GPIO   GPIO_TO_PIN(0, 23)
+# define LED_LAN_BL_GPIO   GPIO_TO_PIN(1, 17)
+# define LED_LAN_RD_GPIO   GPIO_TO_PIN(0, 26)
+# define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
+# define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
+# define LED_PWM_GPIO      GPIO_TO_PIN(1, 19)
+# define RESET_GPIO        GPIO_TO_PIN(1, 29)
+# define WIFI_REGEN_GPIO   GPIO_TO_PIN(1, 16)
+# define WIFI_RST_GPIO     GPIO_TO_PIN(0, 27)
+# define ZIGBEE_RST_GPIO   GPIO_TO_PIN(3, 18)
+# define BIDCOS_RST_GPIO   GPIO_TO_PIN(1, 24)
+# define Z_WAVE_RST_GPIO   GPIO_TO_PIN(1, 21)
+# define ENOC_RST_GPIO     GPIO_TO_PIN(1, 22)
+
+#endif
+
+#define BACK_BUTTON_GPIO    GPIO_TO_PIN(1, 29)
+#define FRONT_BUTTON_GPIO   GPIO_TO_PIN(1, 25)
+
+/* Reset is on GPIO pin 29 of GPIO bank 1 */
+#define RESET_MASK	(0x1 << 29)
+
+#define HDR_MAGIC	0x43485342
+#define HDR_ETH_ALEN	6
+#define HDR_NAME_LEN	8
+#define HDR_REV_LEN	8
+#define HDR_SER_LEN	16
+#define HDR_ROOT_LEN	12
+#define HDR_FATC_LEN	12
+
+/*
+* SHC parameters held in On-Board I²C EEPROM device.
+*
+* Header Format
+*
+*  Name     Size   Contents
+*-------------------------------------------------------------
+*  Magic     4     0x42 0x53 0x48 0x43  [BSHC]
+*
+*  Version   2     0x0100 for v1.0
+*
+*  Lenght    2     The length of the complete structure, not only this header
+*
+*  Eth-MAC   6     Ethernet MAC Address
+*                  SHC Pool: 7C:AC:B2:00:10:01 - TBD
+*
+*  --- Further values follow, not important for Bootloader ---
+*/
+
+struct  shc_eeprom {
+	u32  magic;
+	u16  version;
+	u16  lenght;
+	uint8_t mac_addr[HDR_ETH_ALEN];
+};
+
+void enable_uart0_pin_mux(void);
+void enable_shc_board_pin_mux(void);
+void enable_shc_board_pwm_pin_mux(void);
+
+#endif
diff --git a/board/bosch/shc/mux.c b/board/bosch/shc/mux.c
new file mode 100644
index 0000000000..e8ada6540c
--- /dev/null
+++ b/board/bosch/shc/mux.c
@@ -0,0 +1,261 @@
+/*
+ * mux.c
+ *
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)},		/* UART0_TXD */
+	{OFFSET(uart0_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART0_CTS */
+	{OFFSET(uart0_rtsn), (MODE(0) | PULLUDDIS)},		/* UART0_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)},	/* UART1_RXD */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDDIS)},		/* UART1_TXD */
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | RXACTIVE)},	/* UART1_CTS */
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDDIS)},		/* UART1_RTS */
+	{-1},
+};
+
+static struct module_pin_mux uart2_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(1) | PULLUDDIS | RXACTIVE)},	/* UART2_RXD */
+	{OFFSET(spi0_d0), (MODE(1) | PULLUDDIS)},		/* UART2_TXD */
+	{-1},
+};
+
+static struct module_pin_mux spi1_pin_mux[] = {
+	{OFFSET(mcasp0_aclkx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_SCLK */
+	{OFFSET(mcasp0_fsx), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D0 */
+	{OFFSET(mcasp0_axr0), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_D1 */
+	{OFFSET(mcasp0_ahclkr), (MODE(3) | PULLUDEN | RXACTIVE)},/* SPI1_CS0 */
+	{-1},
+};
+
+static struct module_pin_mux uart4_pin_mux[] = {
+	{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)},	/* UART4_RXD */
+	{OFFSET(gpmc_wpn), (MODE(6) | PULLUP_EN)},		/* UART4_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUDDIS)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDDIS)},	/* MMC0_CD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUDDIS)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
+	{-1},
+};
+
+static struct module_pin_mux mmc2_pin_mux[] = {
+	{OFFSET(gpmc_ad12), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT0 */
+	{OFFSET(gpmc_ad13), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT1 */
+	{OFFSET(gpmc_ad14), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT2 */
+	{OFFSET(gpmc_ad15), (MODE(3) | PULLUDDIS | RXACTIVE)}, /* MMC2_DAT3 */
+	{OFFSET(gpmc_csn3), (MODE(3) | RXACTIVE | PULLUDDIS)}, /* MMC2_CMD */
+	{OFFSET(gpmc_clk), (MODE(3) | RXACTIVE | PULLUDDIS)},  /* MMC2_CLK */
+	{-1},
+};
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, /* I2C_SCLK */
+	{-1},
+};
+
+static struct module_pin_mux gpio0_7_pin_mux[] = {
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUP_EN)},	/* GPIO0_7 */
+	{-1},
+};
+
+static struct module_pin_mux jtag_pin_mux[] = {
+	{OFFSET(xdma_event_intr0), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(xdma_event_intr1), (MODE(6) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nresetin_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
+	{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
+	{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rsvd2), (MODE(0) | PULLUP_EN)},
+	{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
+	{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
+	{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN)},
+	{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)},
+	{-1},
+};
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad8), (MODE(7) | PULLUDDIS)},	/* gpio0[22] - LED_PWR_BL (external pull-down) */
+	{OFFSET(gpmc_ad9), (MODE(7) | PULLUDDIS)},	/* gpio0[23] - LED_PWR_RD (external pull-down) */
+	{OFFSET(gpmc_ad10), (MODE(7) | PULLUDDIS)},	/* gpio0[26] - LED_LAN_RD (external pull-down) */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},	/* gpio0[27] - #WIFI_RST (external pull-down) */
+	{OFFSET(gpmc_a0), (MODE(7) | PULLUDDIS)},	/* gpio1[16] - WIFI_REGEN */
+	{OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS)},	/* gpio1[17] - LED_LAN_BL */
+	{OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS)},	/* gpio1[18] - LED_Cloud_BL */
+	{OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS)},	/* gpio1[19] -  LED_PWM as GPIO */
+	{OFFSET(gpmc_a4), (MODE(7))},			/* gpio1[20] -  #eMMC_RST */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},	/* gpio1[21] -  #Z-Wave_RST */
+	{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)},	/* gpio1[22] -  ENOC_RST */
+	{OFFSET(gpmc_a7), (MODE(7) | PULLUP_EN)},	/* gpio1[23] -  WIFI_MODE */
+	{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[24] -  #BIDCOS_RST */
+	{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[25] -  USR_BUTTON */
+	{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[26] -  #USB1_OC */
+	{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[27] -  BIDCOS_PROG */
+	{OFFSET(gpmc_be1n), (MODE(7) | PULLUP_EN)},	/* gpio1[28] -  ZIGBEE_PC7 */
+	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUDDIS)},	/* gpio1[29] -  RESET_BUTTON */
+	{OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS)},	/* gpio2[2] -  LED_Cloud_RD */
+	{OFFSET(gpmc_oen_ren), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* gpio2[3] -  #WIFI_POR */
+	{OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)},	/* gpio2[4] -  N/C */
+	{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS)},	/* gpio2[5] -  EEPROM_WP */
+	{OFFSET(lcd_data0), (MODE(7) | PULLUDDIS)},	/* gpio2[6] */
+	{OFFSET(lcd_data1), (MODE(7) | PULLUDDIS)},	/* gpio2[7] */
+	{OFFSET(lcd_data2), (MODE(7) | PULLUDDIS)},	/* gpio2[8] */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDDIS)},	/* gpio2[9] */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDDIS)},	/* gpio2[10] */
+	{OFFSET(lcd_data5), (MODE(7) | PULLUDDIS)},	/* gpio2[11] */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDDIS)},	/* gpio2[12] */
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDDIS)},	/* gpio2[13] */
+	{OFFSET(lcd_data8), (MODE(7) | PULLUDDIS)},	/* gpio2[14] */
+	{OFFSET(lcd_data9), (MODE(7) | PULLUDDIS)},	/* gpio2[15] */
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDDIS)},	/* gpio2[16] */
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDDIS)},	/* gpio2[17] */
+	{OFFSET(lcd_data12), (MODE(7) | PULLUDDIS)},	/* gpio0[8] */
+	{OFFSET(lcd_data13), (MODE(7) | PULLUDDIS)},	/* gpio0[9] */
+	{OFFSET(lcd_data14), (MODE(7) | PULLUDDIS)},	/* gpio0[10] */
+	{OFFSET(lcd_data15), (MODE(7) | PULLUDDIS)},	/* gpio0[11] */
+	{OFFSET(lcd_vsync), (MODE(7) | PULLUDDIS)},	/* gpio2[22] */
+	{OFFSET(lcd_hsync), (MODE(7) | PULLUDDIS)},	/* gpio2[23] */
+	{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)},	/* gpio2[24] */
+	{OFFSET(lcd_ac_bias_en), (MODE(7) | PULLUDDIS)},/* gpio2[25] */
+	{OFFSET(spi0_d1), (MODE(7) | PULLUDDIS)},	/* gpio0[4] */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)},	/* gpio0[5] */
+	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDDIS)},	/* gpio3[18] - #ZIGBEE_RST */
+	{OFFSET(mcasp0_fsr), (MODE(7)) | PULLUDDIS},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},	/* gpio3[19] - ZIGBEE_BOOT */
+	{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE | PULLUP_EN)},/* gpio3[21] - ZIGBEE_PC5 */
+	{-1},
+};
+
+static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txen), MODE(0)},
+	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd3), MODE(0)},
+	{OFFSET(mii1_txd2), MODE(0)},
+	{OFFSET(mii1_txd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txd0), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},
+	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},
+	{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE},
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},
+	{-1},
+};
+
+static struct module_pin_mux pwm_pin_mux[] = {
+	{OFFSET(gpmc_a3), (MODE(6) | PULLUDDIS)},
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart2_pin_mux(void)
+{
+	configure_module_pin_mux(uart2_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+}
+
+void enable_uart4_pin_mux(void)
+{
+	configure_module_pin_mux(uart4_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_shc_board_pwm_pin_mux(void)
+{
+	configure_module_pin_mux(pwm_pin_mux);
+}
+
+void enable_shc_board_pin_mux(void)
+{
+	/* Do board-specific muxes. */
+	if (board_is_c3_sample() || board_is_series()) {
+		configure_module_pin_mux(mii1_pin_mux);
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(mmc1_pin_mux);
+		configure_module_pin_mux(mmc2_pin_mux);
+		configure_module_pin_mux(i2c0_pin_mux);
+		configure_module_pin_mux(gpio0_7_pin_mux);
+		configure_module_pin_mux(gpio_pin_mux);
+		configure_module_pin_mux(uart1_pin_mux);
+		configure_module_pin_mux(uart2_pin_mux);
+		configure_module_pin_mux(uart4_pin_mux);
+		configure_module_pin_mux(spi1_pin_mux);
+		configure_module_pin_mux(jtag_pin_mux);
+	} else {
+		puts("Unknown board, cannot configure pinmux.");
+		hang();
+	}
+}
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 5276907b45..fce998d00f 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -237,7 +237,7 @@ static void compose_hostname(hw_id_t hw_id, char *buf)
 }
 
 
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+#ifdef CONFIG_OF_BOARD_SETUP
 /*
  * Update 'model' and 'memory' properties in the blob according to the module
  * that we are running on.
@@ -255,7 +255,7 @@ static void ft_blob_update(void *blob, bd_t *bd)
 	printf("ft_blob_update(): cannot set /model property err:%s\n",
 		fdt_strerror(ret));
 }
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 
 /*
@@ -358,7 +358,7 @@ int last_stage_init(void)
 #endif /* CONFIG_LAST_STAGE_INIT */
 
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
@@ -366,4 +366,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/congatec/conga-qeval20-qa3-e3845/.gitignore b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile
index 23b8748c69..b784510f39 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Makefile
+++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= conga-qeval20-qa3.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
new file mode 100644
index 0000000000..eace459ae0
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */
diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
index a15a9edac4..1b6c40f8d5 100644
--- a/board/davedenx/aria/aria.c
+++ b/board/davedenx/aria/aria.c
@@ -106,11 +106,11 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index b813adb840..448176d8ba 100644
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -9,6 +9,21 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "dbau1x00"
 
+config SYS_TEXT_BASE
+	default 0xbfc00000
+
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 menu "dbau1x00 board options"
 
 choice
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index f46936ca36..51ac10c8c0 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -16,7 +16,7 @@
  */
 static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	if (ctrl & NAND_CTRL_CHANGE) {
 		if ( ctrl & NAND_CLE )
 			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index ca9a94427f..c510ab13ac 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -471,7 +471,7 @@ int pci_pre_init(struct pci_controller *hose)
 }
 #endif /* defined(CONFIG_PCI) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -493,4 +493,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
index cda1d7bccc..656f0fa83f 100644
--- a/board/esd/mecp5123/mecp5123.c
+++ b/board/esd/mecp5123/mecp5123.c
@@ -198,11 +198,11 @@ int checkboard(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 24e4977c9b..31ac72861f 100644
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -300,7 +300,7 @@ int pci_pre_init(struct pci_controller *hose)
 	return 1;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -322,7 +322,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 7e35c1984d..0d43505e35 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -882,7 +882,7 @@ int board_usb_cleanup(int index, enum usb_init_type init)
 }
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int rc;
@@ -903,4 +903,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
index 0acd2a9aa4..673d2ea56a 100644
--- a/board/freescale/b4860qds/Makefile
+++ b/board/freescale/b4860qds/Makefile
@@ -5,11 +5,11 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y	+= b4860qds.o
-obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o
-obj-$(CONFIG_PCI)      += pci.o
+obj-$(CONFIG_B4860QDS)	+= eth_b4860qds.o
+obj-$(CONFIG_PCI)	+= pci.o
 endif
 
 obj-y	+= ddr.o
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index eb10a6f364..31b186ea8c 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -179,15 +179,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
 
diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c
index 3f7cc03581..fabc78301a 100644
--- a/board/freescale/b4860qds/spl.c
+++ b/board/freescale/b4860qds/spl.c
@@ -91,6 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
index b26d3a1e63..8027750efb 100644
--- a/board/freescale/bsc9131rdb/Makefile
+++ b/board/freescale/bsc9131rdb/Makefile
@@ -13,15 +13,11 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
-obj-y        += bsc9131rdb.o
-obj-y        += ddr.o
-obj-y        += law.o
-obj-y        += tlb.o
-#obj-y		+= bsc9131rdb_mux.o
-
+obj-y	+= bsc9131rdb.o
+obj-y	+= ddr.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile
index 2e4170f512..54193350af 100644
--- a/board/freescale/bsc9132qds/Makefile
+++ b/board/freescale/bsc9132qds/Makefile
@@ -13,14 +13,11 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
 obj-y	+= bsc9132qds.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-
-endif
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile
index 818484a57d..93b3cba031 100644
--- a/board/freescale/c29xpcie/Makefile
+++ b/board/freescale/c29xpcie/Makefile
@@ -11,15 +11,15 @@ endif
 endif
 
 ifdef MINIMAL
-obj-y	+= spl_minimal.o tlb.o law.o
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 endif
-
 obj-y	+= c29xpcie.o
 obj-y	+= cpld.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-endif
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index e325b4db4a..45f463f01f 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
 
 	while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
 			CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
-			+ offset * 0x20000)) >= 0) {
+			+ offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
 		fdt_del_node(blob, nodeoff);
 		offset++;
 	}
diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c
index 3d31d41a4f..d8d73c70b8 100644
--- a/board/freescale/c29xpcie/spl.c
+++ b/board/freescale/c29xpcie/spl.c
@@ -57,6 +57,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 	/* relocate environment function pointers etc. */
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c
index f43426991b..0abaffb334 100644
--- a/board/freescale/common/ls102xa_stream_id.c
+++ b/board/freescale/common/ls102xa_stream_id.c
@@ -10,11 +10,14 @@
 
 void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
 {
-	uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
+	void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int i;
+	u32 icid;
 
-	for (i = 0; i < num; i++)
-		out_be32(scfg + id[i].offset, id[i].stream_id);
+	for (i = 0; i < num; i++) {
+		icid = (id[i].stream_id & 0xff) << 24;
+		out_be32((u32 *)(scfg + id[i].offset), icid);
+	}
 }
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
@@ -28,6 +31,6 @@ void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)
 		else
 			liodn = tbl[i].id[0];
 
-		out_le32((uint32_t *)(tbl[i].reg_offset), liodn);
+		out_le32((u32 *)(tbl[i].reg_offset), liodn);
 	}
 }
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 113295f64a..0db0ed6670 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -14,6 +14,13 @@
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
 	void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
 
 	out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
@@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
 	u8 reg;
 
-	reg = QIXIS_READ(brdcfg[0]);
+	reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
 	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-	QIXIS_WRITE(brdcfg[0], reg);
+	QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
new file mode 100644
index 0000000000..a34521cf79
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif
diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS
new file mode 100644
index 0000000000..842f86f861
--- /dev/null
+++ b/board/freescale/ls1012afrdm/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig
diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile
new file mode 100644
index 0000000000..dbfa2cea38
--- /dev/null
+++ b/board/freescale/ls1012afrdm/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o
diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README
new file mode 100644
index 0000000000..181c4615a8
--- /dev/null
+++ b/board/freescale/ls1012afrdm/README
@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
new file mode 100644
index 0000000000..a94a458f53
--- /dev/null
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	puts("Board: LS1012AFRDM ");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
new file mode 100644
index 0000000000..1257ec8d06
--- /dev/null
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+	default "ls1012aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012aqds"
+
+endif
diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS
new file mode 100644
index 0000000000..27c4affd30
--- /dev/null
+++ b/board/freescale/ls1012aqds/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_qspi_defconfig
diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
new file mode 100644
index 0000000000..0b813f9784
--- /dev/null
+++ b/board/freescale/ls1012aqds/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o
diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README
new file mode 100644
index 0000000000..dee4b302c1
--- /dev/null
+++ b/board/freescale/ls1012aqds/README
@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	• Provides MIC bias
+	• Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
new file mode 100644
index 0000000000..71eea82a03
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+
+	i2c_set_bus_num(0);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
new file mode 100644
index 0000000000..584f604aa8
--- /dev/null
+++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
new file mode 100644
index 0000000000..3f67c2841f
--- /dev/null
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+	default "ls1012ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012ardb"
+
+endif
diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS
new file mode 100644
index 0000000000..79a2a7dd24
--- /dev/null
+++ b/board/freescale/ls1012ardb/MAINTAINERS
@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012ardb/
+F:	include/configs/ls1012ardb.h
+F:	configs/ls1012ardb_qspi_defconfig
diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
new file mode 100644
index 0000000000..05fa9d9c5b
--- /dev/null
+++ b/board/freescale/ls1012ardb/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o
diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README
new file mode 100644
index 0000000000..453b432915
--- /dev/null
+++ b/board/freescale/ls1012ardb/README
@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory (2 virtual banks)
+    - the QSPI emulator.s
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: Three dual 1:4 mux/demux devices,
+    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+    SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
new file mode 100644
index 0000000000..f69768d24e
--- /dev/null
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	u8 in1;
+
+	puts("Board: LS1012ARDB ");
+
+	/* Initialize i2c early for Serial flash bank information */
+	i2c_set_bus_num(0);
+
+	if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	puts("Version");
+	if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+		puts(": RevA");
+	else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+		puts(": RevB");
+	else
+		puts(": unknown");
+
+	printf(", boot from QSPI");
+	if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+		puts(": emu\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+		puts(": bank1\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+		puts(": bank2\n");
+	else
+		puts("unknown\n");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h
index f819c99dba..b39b561dc1 100644
--- a/board/freescale/ls1021aqds/ddr.h
+++ b/board/freescale/ls1021aqds/ddr.h
@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     8, 0x090A0B0B, 0x0C0D0E0C,},
+	{1,  1900, 0, 8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README
index a6fd7a35f5..913537d451 100644
--- a/board/freescale/ls1043aqds/README
+++ b/board/freescale/ls1043aqds/README
@@ -8,41 +8,8 @@ debugging environment.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 3d3c53385a..0fd835d74f 100644
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -116,6 +116,7 @@ phys_size_t initdram(int board_type)
 
 	dram_size = fsl_ddr_sdram();
 #endif
+	erratum_a008850_post();
 
 #ifdef CONFIG_FSL_DEEP_SLEEP
 	fsl_dp_ddr_restore();
diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index 8adb660012..ad709ba216 100644
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -7,6 +7,8 @@
 #ifndef __DDR_H__
 #define __DDR_H__
 
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -32,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fba6b88951..7e47ef0d82 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -238,8 +238,8 @@ int board_early_init_f(void)
 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 	usb_pwrfault =
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif
@@ -307,14 +307,6 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-				   CONFIG_SYS_CCI400_ADDR;
-
-	/* Set CCI-400 control override register to enable barrier
-	 * transaction */
-	out_le32(&cci->ctrl_ord,
-		 CCI400_CTRLORD_EN_BARRIER);
-
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	board_retimer_init();
 
@@ -325,10 +317,6 @@ int board_init(void)
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
 #endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
-	gd->env_addr = (ulong)&default_environment[0];
-#endif
 	return 0;
 }
 
diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README
index 0556e73b3a..709ddbbef3 100644
--- a/board/freescale/ls1043ardb/README
+++ b/board/freescale/ls1043ardb/README
@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043ARDB board Overview
  -----------------------
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c
index 78c28246a8..c6452830ed 100644
--- a/board/freescale/ls1043ardb/cpld.c
+++ b/board/freescale/ls1043ardb/cpld.c
@@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
 /* Set the boot bank to the alternate bank */
 void cpld_set_altbank(void)
 {
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
 	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
 	u8 reg7 = CPLD_READ(vbank);
 
-	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
 
 	reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
 	CPLD_WRITE(vbank, reg7);
@@ -42,7 +50,21 @@ void cpld_set_altbank(void)
 /* Set the boot bank to the default bank */
 void cpld_set_defbank(void)
 {
-	CPLD_WRITE(global_rst, 1);
+	u16 reg = CPLD_CFG_RCW_SRC_NOR;
+	u8 reg4 = CPLD_READ(soft_mux_on);
+	u8 reg5 = (u8)(reg >> 1);
+	u8 reg6 = (u8)(reg & 1);
+
+	cpld_rev_bit(&reg5);
+
+	CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
+
+	CPLD_WRITE(cfg_rcw_src1, reg5);
+	CPLD_WRITE(cfg_rcw_src2, reg6);
+
+	CPLD_WRITE(vbank, 0);
+
+	CPLD_WRITE(system_rst, 1);
 }
 
 void cpld_set_nand(void)
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h
index bd59c0e5d5..cb175b56fa 100644
--- a/board/freescale/ls1043ardb/cpld.h
+++ b/board/freescale/ls1043ardb/cpld.h
@@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
 #define CPLD_SW_MUX_BANK_SEL	0x40
 #define CPLD_BANK_SEL_MASK	0x07
 #define CPLD_BANK_SEL_ALTBANK	0x04
+#define CPLD_CFG_RCW_SRC_NOR	0x025
 #define CPLD_CFG_RCW_SRC_NAND	0x106
 #define CPLD_CFG_RCW_SRC_SD	0x040
 #endif
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 11bc0f24d9..1e2fd2ed0c 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -177,6 +177,8 @@ phys_size_t initdram(int board_type)
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	erratum_a008850_post();
+
 #ifdef CONFIG_FSL_DEEP_SLEEP
 	fsl_dp_ddr_restore();
 #endif
diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index b17eb80885..a77ddf3d24 100644
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -6,6 +6,9 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
 	u32 n_ranks;
 	u32 datarate_mhz_high;
@@ -31,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{1,  1666, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  1900, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  2200, 0, 6,     7, 0x07090800, 0x00000000,},
+	{1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
 #endif
 	{}
 };
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbfe27..14365207da 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -19,7 +19,6 @@
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <environment.h>
 #include <fsl_sec.h>
 #include "cpld.h"
 #ifdef CONFIG_U_QE
@@ -31,12 +30,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
-	static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
+	static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
 #ifndef CONFIG_SD_BOOT
 	u8 cfg_rcw_src1, cfg_rcw_src2;
-	u32 cfg_rcw_src;
+	u16 cfg_rcw_src;
 #endif
-	u32 sd1refclk_sel;
+	u8 sd1refclk_sel;
 
 	printf("Board: LS1043ARDB, boot from ");
 
@@ -83,22 +82,12 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
-	/*
-	 * Set CCI-400 control override register to enable barrier
-	 * transaction
-	 */
-	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_FSL_IFC
 	init_final_memctl_regs();
 #endif
 
-#ifdef CONFIG_ENV_IS_NOWHERE
-	gd->env_addr = (ulong)&default_environment[0];
-#endif
-
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 	enable_layerscape_ns_access();
 #endif
@@ -106,6 +95,8 @@ int board_init(void)
 #ifdef CONFIG_U_QE
 	u_qe_init();
 #endif
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 
 	return 0;
 }
diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS
index 7d3bfc8e4e..076532622f 100644
--- a/board/freescale/ls2080aqds/MAINTAINERS
+++ b/board/freescale/ls2080aqds/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080aqds/
 F:	board/freescale/ls2080a/ls2080aqds.c
diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README
index 6ddad92f2c..5c98866712 100644
--- a/board/freescale/ls2080aqds/README
+++ b/board/freescale/ls2080aqds/README
@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080AQDS board Overview
  -----------------------
diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h
index b76ea61ba0..eba62c33b2 100644
--- a/board/freescale/ls2080aqds/ddr.h
+++ b/board/freescale/ls2080aqds/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index b3bd40afb7..897793d85b 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS
index 5562917ec9..a20c003ce7 100644
--- a/board/freescale/ls2080ardb/MAINTAINERS
+++ b/board/freescale/ls2080ardb/MAINTAINERS
@@ -1,5 +1,5 @@
 LS2080A BOARD
-M:	Prabhakar Kushwaha <prabhakar@freescale.com>
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
 S:	Maintained
 F:	board/freescale/ls2080ardb/
 F:	board/freescale/ls2080a/ls2080ardb.c
diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README
index 6708ca9cc7..b1613ba680 100644
--- a/board/freescale/ls2080ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080ARDB board Overview
  -----------------------
diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h
index bda9d4a40f..8d5a49061c 100644
--- a/board/freescale/ls2080ardb/ddr.h
+++ b/board/freescale/ls2080ardb/ddr.h
@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     8, 0x08090B0D, 0x0E10100C,},
-	{2,  1900, 0, 4,     8, 0x090A0C0E, 0x1012120D,},
-	{2,  2300, 0, 4,     9, 0x0A0B0C10, 0x1114140E,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
+	{2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
+	{2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index fb39af6445..52e5e3f516 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -156,7 +156,9 @@ int board_init(void)
 {
 	char *env_hwconfig;
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
 	u32 val;
 
 	init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
 	return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index 8d88bc03c0..88496812bf 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 92cef2a97d..a96a59991f 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 40bd55dfba..7c44282ca2 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -274,11 +274,11 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile
index 660d1bbc2a..86eb6946dd 100644
--- a/board/freescale/p1010rdb/Makefile
+++ b/board/freescale/p1010rdb/Makefile
@@ -13,18 +13,14 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
-
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
-
 obj-y	+= p1010rdb.o
 obj-y	+= ddr.o
+endif
+
 obj-y	+= law.o
 obj-y	+= tlb.o
-
-endif
diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c
index eb8e567554..f8584084ce 100644
--- a/board/freescale/p1010rdb/spl.c
+++ b/board/freescale/p1010rdb/spl.c
@@ -72,6 +72,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index a5821277ef..9793853463 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -13,17 +13,15 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y        += spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
 obj-y	+= p1022ds.o
 obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
-
 obj-$(CONFIG_FSL_DIU_FB) += diu.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 89ef95aab8..04db767f98 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -86,6 +86,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
 #endif
diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile
index a2a1f92ce8..045d4093ae 100644
--- a/board/freescale/p1_p2_rdb_pc/Makefile
+++ b/board/freescale/p1_p2_rdb_pc/Makefile
@@ -13,17 +13,14 @@ endif
 endif
 
 ifdef MINIMAL
-
-obj-y	+= spl_minimal.o tlb.o law.o
-
+obj-y	+= spl_minimal.o
 else
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 endif
-
-obj-y        += p1_p2_rdb_pc.o
-obj-y        += ddr.o
-obj-y        += law.o
-obj-y        += tlb.o
-
+obj-y	+= p1_p2_rdb_pc.o
+obj-y	+= ddr.o
 endif
+
+obj-y	+= law.o
+obj-y	+= tlb.o
diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c
index 0142746c84..76a3cf47cc 100644
--- a/board/freescale/p1_p2_rdb_pc/spl.c
+++ b/board/freescale/p1_p2_rdb_pc/spl.c
@@ -83,6 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifndef CONFIG_SPL_NAND_BOOT
 	env_init();
diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile
index c74f4c62f8..a335ec65fa 100644
--- a/board/freescale/p2041rdb/Makefile
+++ b/board/freescale/p2041rdb/Makefile
@@ -7,6 +7,6 @@
 #
 
 obj-y	+= p2041rdb.o
-obj-y += cpld.o
+obj-y	+= cpld.o
 obj-y	+= ddr.o
 obj-y	+= eth.o
diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile
index d94f2307d9..afbc9146ed 100644
--- a/board/freescale/t102xqds/Makefile
+++ b/board/freescale/t102xqds/Makefile
@@ -5,7 +5,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y	+= t102xqds.o
 obj-y	+= eth_t102xqds.o
diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c
index 2d4d10f351..c26f3503b9 100644
--- a/board/freescale/t102xqds/ddr.c
+++ b/board/freescale/t102xqds/ddr.c
@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #if defined(CONFIG_SYS_FSL_DDR4)
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
-	{1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
+	{1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
@@ -172,14 +172,13 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c
index 073ff2dcde..d59d3431ec 100644
--- a/board/freescale/t102xqds/spl.c
+++ b/board/freescale/t102xqds/spl.c
@@ -120,6 +120,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index 052006610e..64528656ac 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -5,7 +5,7 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
 obj-y   += t102xrdb.o
 obj-$(CONFIG_T1024RDB)   += cpld.o
diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c
index adf9fd5f78..edfbdbf3a8 100644
--- a/board/freescale/t102xrdb/ddr.c
+++ b/board/freescale/t102xrdb/ddr.c
@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 	{}
 };
 
@@ -234,12 +234,12 @@ phys_size_t initdram(int board_type)
 	puts("Initializing....using SPD\n");
 #endif
 	dram_size = fsl_ddr_sdram();
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index da97c440c4..bd3cbbf11c 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h
index a6e1673525..1e087460cb 100644
--- a/board/freescale/t1040qds/ddr.h
+++ b/board/freescale/t1040qds/ddr.h
@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{1,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  2200, 0, 4,     7, 0x08090A0D, 0x0F0F100C,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index cf79d2ddb2..22d6a5f617 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -124,15 +124,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 	fsl_dp_resume();
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index b9c02f7fe0..012991cf46 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+	{2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
 #else
 #error DDR type not defined
 #endif
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index 81f48c4c30..4b35af63f6 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -98,6 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_initialize(bd);
diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS
index deda092a6a..d747de3f34 100644
--- a/board/freescale/t208xqds/MAINTAINERS
+++ b/board/freescale/t208xqds/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XQDS BOARD
-#M:	-
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
 S:	Maintained
 F:	board/freescale/t208xqds/
 F:	include/configs/T208xQDS.h
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 6cb72c9fd5..ef04a26463 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -7,10 +7,8 @@
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
-obj-$(CONFIG_T2080QDS) += t208xqds.o
-obj-$(CONFIG_T2080QDS) += eth_t208xqds.o
-obj-$(CONFIG_T2081QDS) += t208xqds.o
-obj-$(CONFIG_T2081QDS) += eth_t208xqds.o
+obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o
+obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c
index f1aff5481e..f96470f020 100644
--- a/board/freescale/t208xqds/ddr.c
+++ b/board/freescale/t208xqds/ddr.c
@@ -108,13 +108,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size =  fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }
diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h
index 9c26fdf3bd..255ab2c543 100644
--- a/board/freescale/t208xqds/ddr.h
+++ b/board/freescale/t208xqds/ddr.h
@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
 	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200,  0,  5,  7,  0x0708090a,  0x0b0c0d09},
-	{2,  1400,  0,  5,  7,  0x08090a0c,  0x0d0e0f0a},
-	{2,  1700,  0,  5,  8,  0x090a0b0c,  0x0e10110c},
-	{2,  1900,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{2,  2140,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{1,  1700,  0,  4,  8,  0x080a0a0c,  0x0c0d0e0a},
-	{1,  1900,  0,  5,  8,  0x090a0c0d,  0x0e0f110c},
-	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+	{2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
+	{2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
+	{2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
+	{2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
+	{1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 	/* TODO: need tuning these parameters if RDIMM is used */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c
index 55a0f8fdce..bb02dab2f1 100644
--- a/board/freescale/t208xqds/spl.c
+++ b/board/freescale/t208xqds/spl.c
@@ -106,6 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS
index 16428798cd..ccbfbab142 100644
--- a/board/freescale/t208xrdb/MAINTAINERS
+++ b/board/freescale/t208xrdb/MAINTAINERS
@@ -1,5 +1,5 @@
 T208XRDB BOARD
-#M:	-
+M:	Shengzhou Liu <Shengzhou.Liu@nxp.com>
 S:	Maintained
 F:	board/freescale/t208xrdb/
 F:	include/configs/T208xRDB.h
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 9605f8b606..cd8fe096d8 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -5,11 +5,9 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T2080RDB) += t208xrdb.o
-obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
-obj-$(CONFIG_T2080RDB) += cpld.o
+obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
 obj-$(CONFIG_PCI)      += pci.o
 endif
 
diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c
index 053f128e5b..f6c8ca30ac 100644
--- a/board/freescale/t208xrdb/ddr.c
+++ b/board/freescale/t208xrdb/ddr.c
@@ -101,12 +101,12 @@ phys_size_t initdram(int board_type)
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h
index 08cbb606d5..175cf56a09 100644
--- a/board/freescale/t208xrdb/ddr.h
+++ b/board/freescale/t208xrdb/ddr.h
@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
+	{2,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+	{1,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
 	{}
 };
 
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index f63366bb0e..2ff05a29f5 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -76,6 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile
index bd2c1f1622..731ccb0b29 100644
--- a/board/freescale/t4qds/Makefile
+++ b/board/freescale/t4qds/Makefile
@@ -5,12 +5,12 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240QDS) += t4240qds.o
-obj-$(CONFIG_T4240QDS)+= eth.o
+obj-$(CONFIG_T4240QDS)	+= t4240qds.o eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+
 obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 62d58c5b1f..d533924a0d 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -117,13 +117,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
-
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
 	return dram_size;
 }
diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h
index 4d0e3c497d..0b0cc9af39 100644
--- a/board/freescale/t4qds/ddr.h
+++ b/board/freescale/t4qds/ddr.h
@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
 	{}
 };
 
diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c
index d52059a145..6ca0f03ffe 100644
--- a/board/freescale/t4qds/spl.c
+++ b/board/freescale/t4qds/spl.c
@@ -116,6 +116,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 #ifdef CONFIG_SPL_NAND_BOOT
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index 83b55ee193..4f29eea0f4 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -5,13 +5,14 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-y += spl.o
+obj-y	+= spl.o
 else
-obj-$(CONFIG_T4240RDB) += t4240rdb.o
-obj-y	+= cpld.o
-obj-y	+= eth.o
+obj-$(CONFIG_T4240RDB)	+= t4240rdb.o
+obj-y			+= cpld.o
+obj-y			+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+
 obj-y	+= ddr.o
 obj-y	+= law.o
 obj-y	+= tlb.o
diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c
index 27b37b5cc4..230f031a3b 100644
--- a/board/freescale/t4rdb/ddr.c
+++ b/board/freescale/t4rdb/ddr.c
@@ -110,13 +110,12 @@ phys_size_t initdram(int board_type)
 
 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	dram_size = fsl_ddr_sdram();
-
-	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-	dram_size *= 0x100000;
 #else
 	/* DDR has been initialised by first stage boot loader */
 	dram_size = fsl_ddr_sdram_size();
 #endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
 
 	return dram_size;
 }
diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h
index 7b854767e7..f01ebb22b5 100644
--- a/board/freescale/t4rdb/ddr.h
+++ b/board/freescale/t4rdb/ddr.h
@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
 	{}
 };
 
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 
diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c
index e563a6169a..ae2451e4ba 100644
--- a/board/freescale/t4rdb/eth.c
+++ b/board/freescale/t4rdb/eth.c
@@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis)
 		puts("Invalid SerDes1 protocol for T4240RDB\n");
 	}
 
+	fm_disable_port(FM1_DTSEC5);
+	fm_disable_port(FM1_DTSEC6);
+
 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
@@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis)
 		puts("Invalid SerDes2 protocol for T4240RDB\n");
 	}
 
+	fm_disable_port(FM2_DTSEC5);
+	fm_disable_port(FM2_DTSEC6);
 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
 		interface = fm_info_get_enet_if(i);
 		switch (interface) {
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 4c1e0cc8d0..b148a7fd1f 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -80,6 +80,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
+	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 
 	mmc_initialize(bd);
 	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index 82313e8a7a..70395ac91d 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -743,7 +743,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 
 static int ft_sethdmiinfmt(void *blob, char *mode)
 {
@@ -996,7 +996,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
 	.reg = (struct mxc_uart *)UART2_BASE,
diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile
index ce230455c8..d4f0e70573 100644
--- a/board/gdsys/common/Makefile
+++ b/board/gdsys/common/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
 obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
 obj-$(CONFIG_STRIDER) += fanctrl.o
 obj-$(CONFIG_STRIDER_CON) += osd.o
+obj-$(CONFIG_STRIDER_CON_DP) += osd.o
diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c
index 96f02d68ed..f72a01e5b2 100644
--- a/board/gdsys/common/ioep-fpga.c
+++ b/board/gdsys/common/ioep-fpga.c
@@ -25,8 +25,9 @@ enum {
 
 enum {
 	COMPRESSION_NONE = 0,
-	COMPRESSION_TYPE1_DELTA = 1,
-	COMPRESSION_TYPE1_TYPE2_DELTA = 3,
+	COMPRESSION_TYPE_1 = 1,
+	COMPRESSION_TYPE_1_2 = 3,
+	COMPRESSION_TYPE_1_2_3 = 7,
 };
 
 enum {
@@ -158,12 +159,16 @@ void ioep_fpga_print_info(unsigned int fpga)
 		printf(" no compression");
 		break;
 
-	case COMPRESSION_TYPE1_DELTA:
-		printf(" type1-deltacompression");
+	case COMPRESSION_TYPE_1:
+		printf(" compression type1(delta)");
 		break;
 
-	case COMPRESSION_TYPE1_TYPE2_DELTA:
-		printf(" type1-deltacompression, type2-inlinecompression");
+	case COMPRESSION_TYPE_1_2:
+		printf(" compression type1(delta), type2(inline)");
+		break;
+
+	case COMPRESSION_TYPE_1_2_3:
+		printf(" compression type1(delta), type2(inline), type3(intempo)");
 		break;
 
 	default:
diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 4e292f5662..add9574369 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -469,6 +469,9 @@ int osd_size(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	}
 
 	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
+
 		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
 		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
 		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 8d01d8b116..2d7d789b23 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -203,7 +203,7 @@ int misc_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 extern void __ft_board_setup(void *blob, bd_t *bd);
 
 int ft_board_setup(void *blob, bd_t *bd)
@@ -218,4 +218,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c
index eee582bb0f..121977d315 100644
--- a/board/gdsys/mpc8308/strider.c
+++ b/board/gdsys/mpc8308/strider.c
@@ -133,6 +133,9 @@ int last_stage_init(void)
 	unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
 #endif
 	bool hw_type_cat = pca9698_get_value(0x20, 18);
+#ifdef CONFIG_STRIDER_CON_DP
+	bool is_dh = pca9698_get_value(0x20, 25);
+#endif
 	bool ch0_sgmii2_present = false;
 
 	/* Turn on Analog Devices ADV7611 */
@@ -140,6 +143,7 @@ int last_stage_init(void)
 
 	/* Turn on Parade DP501 */
 	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
 
 	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
 
@@ -202,6 +206,14 @@ int last_stage_init(void)
 		osd_probe(0);
 #endif
 
+#ifdef CONFIG_STRIDER_CON_DP
+	if (ioep_fpga_has_osd(0)) {
+		osd_probe(0);
+		if (is_dh)
+			osd_probe(4);
+	}
+#endif
+
 #ifdef CONFIG_STRIDER_CPU
 	ch7301_probe(0, false);
 	dp501_probe(0, false);
@@ -226,6 +238,13 @@ int last_stage_init(void)
 		if (ioep_fpga_has_osd(k))
 			osd_probe(k);
 #endif
+#ifdef CONFIG_STRIDER_CON_DP
+		if (ioep_fpga_has_osd(k)) {
+			osd_probe(k);
+			if (is_dh)
+				osd_probe(k + 4);
+		}
+#endif
 #ifdef CONFIG_STRIDER_CPU
 		if (!adv7611_probe(k))
 			printf("       Advantiv ADV7611 HDMI Receiver\n");
@@ -270,6 +289,24 @@ int fpga_gpio_get(unsigned int bus, int pin)
 	return val & pin;
 }
 
+#ifdef CONFIG_STRIDER_CON_DP
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus, control, &val);
+	FPGA_SET_REG(bus, control, val & ~pin);
+}
+#endif
+
 void mpc8308_init(void)
 {
 	pca9698_direction_output(0x20, 26, 1);
diff --git a/board/hardkernel/odroid-c2/Kconfig b/board/hardkernel/odroid-c2/Kconfig
new file mode 100644
index 0000000000..687d9c6d28
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_C2
+
+config SYS_BOARD
+	default "odroid-c2"
+
+config SYS_VENDOR
+	default "hardkernel"
+
+config SYS_CONFIG_NAME
+	default "odroid-c2"
+
+endif
diff --git a/board/hardkernel/odroid-c2/MAINTAINERS b/board/hardkernel/odroid-c2/MAINTAINERS
new file mode 100644
index 0000000000..23ae1e7cbc
--- /dev/null
+++ b/board/hardkernel/odroid-c2/MAINTAINERS
@@ -0,0 +1,6 @@
+ODROID-C2
+M:	Beniamino Galvani <b.galvani@gmail.com>
+S:	Maintained
+F:	board/hardkernel/odroid-c2/
+F:	include/configs/odroid-c2.h
+F:	configs/odroid-c2_defconfig
diff --git a/board/hardkernel/odroid-c2/Makefile b/board/hardkernel/odroid-c2/Makefile
new file mode 100644
index 0000000000..571044b66a
--- /dev/null
+++ b/board/hardkernel/odroid-c2/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= odroid-c2.o
diff --git a/board/hardkernel/odroid-c2/README b/board/hardkernel/odroid-c2/README
new file mode 100644
index 0000000000..d6d266a5ce
--- /dev/null
+++ b/board/hardkernel/odroid-c2/README
@@ -0,0 +1,60 @@
+U-Boot for ODROID-C2
+====================
+
+ODROID-C2 is a single board computer manufactured by Hardkernel
+Co. Ltd with the following specifications:
+
+ - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 2GHz
+ - ARM Mali 450 GPU
+ - 2GB DDR3 SDRAM
+ - Gigabit Ethernet
+ - HDMI 2.0 4K/60Hz display
+ - 40-pin GPIO header
+ - 4 x USB 2.0 Host, 1 x USB OTG
+ - eMMC, microSD
+ - Infrared receiver
+
+Schematics are available on the manufacturer website.
+
+Currently the u-boot port supports the following devices:
+ - serial
+ - Ethernet
+
+u-boot compilation
+==================
+
+ > export ARCH=arm
+ > export CROSS_COMPILE=aarch64-none-elf-
+ > make odroid-c2_defconfig
+ > make
+
+Image creation
+==============
+
+Amlogic doesn't provide sources for the firmware and for tools needed
+to create the bootloader image, so it is necessary to obtain them from
+the git tree published by the board vendor:
+
+ > DIR=odroid-c2
+ > git clone --depth 1 \
+       https://github.com/hardkernel/u-boot.git -b odroidc2-v2015.01 \
+       $DIR
+ > $DIR/fip/fip_create --bl30  $DIR/fip/gxb/bl30.bin \
+                       --bl301 $DIR/fip/gxb/bl301.bin \
+                       --bl31  $DIR/fip/gxb/bl31.bin \
+                       --bl33  u-boot.bin \
+                       $DIR/fip.bin
+ > $DIR/fip/fip_create --dump $DIR/fip.bin
+ > cat $DIR/fip/gxb/bl2.package $DIR/fip.bin > $DIR/boot_new.bin
+ > $DIR/fip/gxb/aml_encrypt_gxb --bootsig \
+                                --input $DIR/boot_new.bin \
+                                --output $DIR/u-boot.img
+ > dd if=$DIR/u-boot.img of=$DIR/u-boot.gxbb bs=512 skip=96
+
+and then write the image to SD with:
+
+ > DEV=/dev/your_sd_device
+ > BL1=$DIR/sd_fuse/bl1.bin.hardkernel
+ > dd if=$BL1 of=$DEV conv=fsync bs=1 count=442
+ > dd if=$BL1 of=$DEV conv=fsync bs=512 skip=1 seek=1
+ > dd if=$DIR/u-boot.gxbb of=$DEV conv=fsync bs=512 seek=97
diff --git a/board/hardkernel/odroid-c2/odroid-c2.c b/board/hardkernel/odroid-c2/odroid-c2.c
new file mode 100644
index 0000000000..bd72100e09
--- /dev/null
+++ b/board/hardkernel/odroid-c2/odroid-c2.c
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <dm/platdata.h>
+#include <phy.h>
+
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
+int board_init(void)
+{
+	return 0;
+}
+
+static const struct eth_pdata gxbb_eth_pdata = {
+	.iobase = GXBB_ETH_BASE,
+	.phy_interface = PHY_INTERFACE_MODE_RGMII,
+};
+
+U_BOOT_DEVICE(meson_eth) = {
+	.name = "eth_designware",
+	.platdata = &gxbb_eth_pdata,
+};
+
+int misc_init_r(void)
+{
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	ssize_t len;
+
+	/* Select Ethernet function */
+	setbits_le32(GXBB_PINMUX(6), 0x3fff);
+
+	/* Set RGMII mode */
+	setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
+				     GXBB_ETH_REG_0_TX_PHASE(1) |
+				     GXBB_ETH_REG_0_TX_RATIO(4) |
+				     GXBB_ETH_REG_0_PHY_CLK_EN |
+				     GXBB_ETH_REG_0_CLK_EN);
+
+	/* Enable power and clock gate */
+	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+	/* Reset PHY on GPIOZ_14 */
+	clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
+	clrbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+	mdelay(10);
+	setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_setenv_enetaddr("ethaddr", mac_addr);
+	}
+
+	return 0;
+}
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
index 72932ca69f..75bf1bb33c 100644
--- a/board/ifm/ac14xx/ac14xx.c
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -607,11 +607,11 @@ int checkboard(void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
index ca09767d28..4fc6809ad6 100644
--- a/board/ifm/o2dnt2/o2dnt2.c
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -303,7 +303,7 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
 static void ft_adapt_flash_base(void *blob)
 {
@@ -383,4 +383,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 4c06d0c0d8..98eb4d16c7 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -9,4 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "malta"
 
+config SYS_TEXT_BASE
+	default 0xbe000000 if 32BIT
+	default 0xffffffffbe000000 if 64BIT
+
 endif
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index 534db1d832..3d48cdc1f4 100644
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -10,6 +10,7 @@
 #include <pci.h>
 
 #include <asm/addrspace.h>
+#include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/malta.h>
 #include <asm/mipsregs.h>
@@ -34,7 +35,7 @@ lowlevel_init:
 	mtc0	t0, CP0_CONFIG, 2
 
 	/* detect the core card */
-	li	t0, KSEG1ADDR(MALTA_REVISION)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_REVISION)
 	lw	t0, 0(t0)
 	srl	t0, t0, MALTA_REVISION_CORID_SHF
 	andi	t0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -68,12 +69,12 @@ lowlevel_init:
 	 */
 _gt64120:
 	/* move GT64120 registers from 0x14000000 to 0x1be00000 */
-	li	t1, KSEG1ADDR(GT_DEF_BASE)
+	PTR_LI	t1, CKSEG1ADDR(GT_DEF_BASE)
 	li	t0, CPU_TO_GT32(0xdf000000)
 	sw	t0, GT_ISD_OFS(t1)
 
 	/* setup MEM-to-PCI0 mapping */
-	li	t1, KSEG1ADDR(MALTA_GT_BASE)
+	PTR_LI	t1, CKSEG1ADDR(MALTA_GT_BASE)
 
 	/* setup PCI0 io window to 0x18000000-0x181fffff */
 	li	t0, CPU_TO_GT32(0xc0000000)
@@ -100,7 +101,7 @@ _gt64120:
 	 */
 _msc01:
 	/* setup peripheral bus controller clock divide */
-	li	t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
 	li	t1, 0x1 << MSC01_PBC_CLKCFG_SHF
 	sw	t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -122,7 +123,7 @@ _msc01:
 	sw	t1, MSC01_PBC_CS0CFG_OFS(t0)
 
 	/* setup basic address decode */
-	li	t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
 	li	t1, 0x0
 	li	t2, -CONFIG_SYS_MEM_SIZE
 	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
@@ -157,7 +158,7 @@ _msc01:
 	sw	t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
 	/* setup PCI memory */
-	li	t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
 	li	t1, MALTA_MSC01_PCIMEM_BASE
 	li	t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
 	li	t3, MALTA_MSC01_PCIMEM_MAP
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 3a9e7807c6..495504372a 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -12,7 +12,6 @@
 #include <pci_gt64120.h>
 #include <pci_msc01.h>
 #include <rtc.h>
-#include <serial.h>
 
 #include <asm/addrspace.h>
 #include <asm/io.h>
@@ -161,18 +160,6 @@ int misc_init_r(void)
 	return 0;
 }
 
-struct serial_device *default_serial_console(void)
-{
-	switch (malta_sys_con()) {
-	case SYSCON_GT64120:
-		return &eserial1_device;
-
-	default:
-	case SYSCON_MSC01:
-		return &eserial2_device;
-	}
-}
-
 void pci_init_board(void)
 {
 	pci_dev_t bdf;
diff --git a/board/intel/bayleybay/.gitignore b/board/intel/bayleybay/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/intel/bayleybay/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile
index 88b5aad634..52dda7ddab 100644
--- a/board/intel/bayleybay/Makefile
+++ b/board/intel/bayleybay/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= bayleybay.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl
new file mode 100644
index 0000000000..21785ea73b
--- /dev/null
+++ b/board/intel/bayleybay/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/intel/bayleybay/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/galileo/.gitignore b/board/intel/galileo/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/intel/galileo/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 6515bacd76..87a0ec4ccc 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -21,4 +21,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select INTEL_QUARK
 	select BOARD_ROMSIZE_KB_1024
 
+config SMBIOS_PRODUCT_NAME
+	default "GalileoGen2"
+	help
+	  Override the default product name U-Boot reports in the SMBIOS
+	  table, to be compatible with the Intel provided UEFI BIOS, as
+	  Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
+	  drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
+	  it to do different board level configuration.
+
+	  This can be "Galileo" for GEN1 Galileo board.
+
 endif
diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile
index 8356df198c..bbe2f8bf5b 100644
--- a/board/intel/galileo/Makefile
+++ b/board/intel/galileo/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= galileo.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/galileo/acpi/mainboard.asl b/board/intel/galileo/acpi/mainboard.asl
new file mode 100644
index 0000000000..21785ea73b
--- /dev/null
+++ b/board/intel/galileo/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/galileo/dsdt.asl b/board/intel/galileo/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/intel/galileo/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intel/minnowmax/.gitignore b/board/intel/minnowmax/.gitignore
new file mode 100644
index 0000000000..6eb8a5481a
--- /dev/null
+++ b/board/intel/minnowmax/.gitignore
@@ -0,0 +1,3 @@
+dsdt.aml
+dsdt.asl.tmp
+dsdt.c
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 1a614324a2..73e5a8fd02 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,3 +5,4 @@
 #
 
 obj-y	+= minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000000..21785ea73b
--- /dev/null
+++ b/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,11 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000000..6042011acf
--- /dev/null
+++ b/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
index 4ab71609c0..2e52d51b6b 100644
--- a/board/intercontrol/digsy_mtc/digsy_mtc.c
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -378,7 +378,7 @@ void ide_set_reset(int idereset)
 #endif /* CONFIG_IDE_RESET */
 #endif /* CONFIG_CMD_IDE */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 static void ft_delete_node(void *fdt, const char *compat)
 {
 	int off = -1;
@@ -481,4 +481,4 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
index 2078f53769..2e62355c48 100644
--- a/board/ipek01/ipek01.c
+++ b/board/ipek01/ipek01.c
@@ -195,7 +195,7 @@ void pci_init_board (void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup (blob, bd);
@@ -203,7 +203,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 int board_eth_init(bd_t *bis)
 {
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 8856393686..d56902bcd2 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -282,11 +282,11 @@ void ide_set_reset (int idereset)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
index 8acb393369..4f08e98b97 100644
--- a/board/microchip/pic32mzda/Kconfig
+++ b/board/microchip/pic32mzda/Kconfig
@@ -10,4 +10,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "pic32mzdask"
 
+config SYS_TEXT_BASE
+	default 0x9d004000
+
 endif
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index c518079efa..df7c0296c7 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -9,6 +9,21 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "vct"
 
+config SYS_TEXT_BASE
+	default 0x87000000
+
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 menu "vct board options"
 
 choice
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 4d0ebaab74..dc237c1ced 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -184,14 +184,14 @@ int checkboard(void)
 }
 
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 
 #if defined(CONFIG_STATUS_LED)
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 23d0f56bd6..8f292ea8e2 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -145,11 +145,11 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c
index ba15e2e6cf..f04f843c31 100644
--- a/board/nvidia/cardhu/cardhu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -110,11 +110,11 @@ int tegra_pcie_board_init(void)
 	}
 
 	/* GPIO: PEX = 3.3V */
-	err = gpio_request(GPIO_PL7, "PEX");
+	err = gpio_request(TEGRA_GPIO(L, 7), "PEX");
 	if (err < 0)
 		return err;
 
-	gpio_direction_output(GPIO_PL7, 1);
+	gpio_direction_output(TEGRA_GPIO(L, 7), 1);
 
 	/* TPS659110: LDO2_REG = 1.05V, ACTIVE */
 	data[0] = 0x15;
diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
index 7eb1e6c1b3..7955ca5cdf 100644
--- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
+++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h
@@ -15,71 +15,71 @@
 #ifndef _PINMUX_CONFIG_E2220_1170_H_
 #define _PINMUX_CONFIG_E2220_1170_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config e2220_1170_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(A6,   IN),
-	GPIO_INIT(B4,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G2,   OUT0),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   OUT0),
-	GPIO_INIT(K3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB4,  IN),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC5,  OUT0),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(A,    6,   IN),
+	GPIO_INIT(B,    4,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    2,   OUT0),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   OUT0),
+	GPIO_INIT(K,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   4,   IN),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   5,   OUT0),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
index 00e0cdc4b8..01237dbc29 100644
--- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -15,63 +15,63 @@
 #ifndef _PINMUX_CONFIG_JETSON_TK1_H_
 #define _PINMUX_CONFIG_JETSON_TK1_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(G4,   IN),
-	GPIO_INIT(H2,   OUT0),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O1,   IN),
-	GPIO_INIT(O4,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q5,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R2,   OUT0),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U0,   IN),
-	GPIO_INIT(U1,   IN),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(BB5,  OUT0),
-	GPIO_INIT(BB6,  OUT0),
-	GPIO_INIT(BB7,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC2,  IN),
-	GPIO_INIT(EE2,  OUT1),
+	/*        port, pin, init_val */
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(G,    4,   IN),
+	GPIO_INIT(H,    2,   OUT0),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    1,   IN),
+	GPIO_INIT(O,    4,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    5,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    2,   OUT0),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    0,   IN),
+	GPIO_INIT(U,    1,   IN),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(BB,   5,   OUT0),
+	GPIO_INIT(BB,   6,   OUT0),
+	GPIO_INIT(BB,   7,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   2,   IN),
+	GPIO_INIT(EE,   2,   OUT1),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c
index ba96401890..8f68ae9fbe 100644
--- a/board/nvidia/nyan-big/nyan-big.c
+++ b/board/nvidia/nyan-big/nyan-big.c
@@ -36,8 +36,9 @@ void pinmux_init(void)
 
 int tegra_board_id(void)
 {
-	static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1,
-					GPIO_PX4, -1};
+	static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1),
+					TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4),
+					-1};
 
 	gpio_claim_vector(vector, "board_id%d");
 	return gpio_get_values_as_int(vector);
diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
index dca0171f26..fd7f1d17f4 100644
--- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h
+++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h
@@ -15,59 +15,59 @@
 #ifndef _PINMUX_CONFIG_NYAN_BIG_H_
 #define _PINMUX_CONFIG_NYAN_BIG_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(I7,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(R7,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(I,    7,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(R,    7,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
index 35706b4745..24acbccd97 100644
--- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
+++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h
@@ -15,62 +15,62 @@
 #ifndef _PINMUX_CONFIG_P2371_0000_H_
 #define _PINMUX_CONFIG_P2371_0000_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_0000_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G3,   OUT0),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   OUT0),
-	GPIO_INIT(H7,   OUT0),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I3,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   OUT0),
-	GPIO_INIT(L0,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(V7,   OUT1),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC6,  IN),
-	GPIO_INIT(CC7,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    3,   OUT0),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   OUT0),
+	GPIO_INIT(H,    7,   OUT0),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    3,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   OUT0),
+	GPIO_INIT(L,    0,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(V,    7,   OUT1),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   6,   IN),
+	GPIO_INIT(CC,   7,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
index d5be6ecda9..601728e469 100644
--- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
+++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h
@@ -15,73 +15,73 @@
 #ifndef _PINMUX_CONFIG_P2371_2180_H_
 #define _PINMUX_CONFIG_P2371_2180_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2371_2180_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(B0,   IN),
-	GPIO_INIT(B1,   IN),
-	GPIO_INIT(B2,   IN),
-	GPIO_INIT(B3,   IN),
-	GPIO_INIT(C0,   IN),
-	GPIO_INIT(C1,   IN),
-	GPIO_INIT(C2,   IN),
-	GPIO_INIT(C3,   IN),
-	GPIO_INIT(C4,   IN),
-	GPIO_INIT(E4,   IN),
-	GPIO_INIT(E5,   IN),
-	GPIO_INIT(E6,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H1,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(K4,   IN),
-	GPIO_INIT(K5,   OUT0),
-	GPIO_INIT(K6,   IN),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(L1,   IN),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S5,   OUT0),
-	GPIO_INIT(S6,   OUT0),
-	GPIO_INIT(S7,   OUT0),
-	GPIO_INIT(T0,   OUT0),
-	GPIO_INIT(T1,   OUT0),
-	GPIO_INIT(U2,   IN),
-	GPIO_INIT(U3,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V2,   OUT0),
-	GPIO_INIT(V3,   IN),
-	GPIO_INIT(V5,   OUT0),
-	GPIO_INIT(V6,   OUT0),
-	GPIO_INIT(X0,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X2,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X5,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y0,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z2,   IN),
-	GPIO_INIT(Z3,   OUT0),
-	GPIO_INIT(BB0,  IN),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(BB3,  IN),
-	GPIO_INIT(CC1,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(B,    0,   IN),
+	GPIO_INIT(B,    1,   IN),
+	GPIO_INIT(B,    2,   IN),
+	GPIO_INIT(B,    3,   IN),
+	GPIO_INIT(C,    0,   IN),
+	GPIO_INIT(C,    1,   IN),
+	GPIO_INIT(C,    2,   IN),
+	GPIO_INIT(C,    3,   IN),
+	GPIO_INIT(C,    4,   IN),
+	GPIO_INIT(E,    4,   IN),
+	GPIO_INIT(E,    5,   IN),
+	GPIO_INIT(E,    6,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    1,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(K,    4,   IN),
+	GPIO_INIT(K,    5,   OUT0),
+	GPIO_INIT(K,    6,   IN),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(L,    1,   IN),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    5,   OUT0),
+	GPIO_INIT(S,    6,   OUT0),
+	GPIO_INIT(S,    7,   OUT0),
+	GPIO_INIT(T,    0,   OUT0),
+	GPIO_INIT(T,    1,   OUT0),
+	GPIO_INIT(U,    2,   IN),
+	GPIO_INIT(U,    3,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    2,   OUT0),
+	GPIO_INIT(V,    3,   IN),
+	GPIO_INIT(V,    5,   OUT0),
+	GPIO_INIT(V,    6,   OUT0),
+	GPIO_INIT(X,    0,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    2,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    5,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    0,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    2,   IN),
+	GPIO_INIT(Z,    3,   OUT0),
+	GPIO_INIT(BB,   0,   IN),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(BB,   3,   IN),
+	GPIO_INIT(CC,   1,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c
index d80a7d0d3e..7ce656f51a 100644
--- a/board/nvidia/p2571/p2571.c
+++ b/board/nvidia/p2571/p2571.c
@@ -58,6 +58,6 @@ void pinmux_init(void)
 void start_cpu_fan(void)
 {
 	/* GPIO_PE4 is PS_VDD_FAN_ENABLE */
-	gpio_request(GPIO_PE4, "FAN_VDD");
-	gpio_direction_output(GPIO_PE4, 1);
+	gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD");
+	gpio_direction_output(TEGRA_GPIO(E, 4), 1);
 }
diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h
index d3233016b5..dd4228f671 100644
--- a/board/nvidia/p2571/pinmux-config-p2571.h
+++ b/board/nvidia/p2571/pinmux-config-p2571.h
@@ -15,37 +15,37 @@
 #ifndef _PINMUX_CONFIG_P2571_H_
 #define _PINMUX_CONFIG_P2571_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config p2571_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(A5,   IN),
-	GPIO_INIT(D4,   IN),
-	GPIO_INIT(E4,   OUT0),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(H0,   OUT0),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H3,   OUT0),
-	GPIO_INIT(H4,   OUT0),
-	GPIO_INIT(H5,   IN),
-	GPIO_INIT(I0,   OUT0),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(V1,   OUT0),
-	GPIO_INIT(V6,   OUT1),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X6,   IN),
-	GPIO_INIT(X7,   IN),
-	GPIO_INIT(Y1,   IN),
-	GPIO_INIT(Z0,   IN),
-	GPIO_INIT(Z4,   OUT0),
-	GPIO_INIT(BB2,  OUT0),
-	GPIO_INIT(CC1,  IN),
-	GPIO_INIT(CC3,  IN),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(A,    5,   IN),
+	GPIO_INIT(D,    4,   IN),
+	GPIO_INIT(E,    4,   OUT0),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(H,    0,   OUT0),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    3,   OUT0),
+	GPIO_INIT(H,    4,   OUT0),
+	GPIO_INIT(H,    5,   IN),
+	GPIO_INIT(I,    0,   OUT0),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(V,    1,   OUT0),
+	GPIO_INIT(V,    6,   OUT1),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    6,   IN),
+	GPIO_INIT(X,    7,   IN),
+	GPIO_INIT(Y,    1,   IN),
+	GPIO_INIT(Z,    0,   IN),
+	GPIO_INIT(Z,    4,   OUT0),
+	GPIO_INIT(BB,   2,   OUT0),
+	GPIO_INIT(CC,   1,   IN),
+	GPIO_INIT(CC,   3,   IN),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv)	\
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
new file mode 100644
index 0000000000..1b1116f020
--- /dev/null
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+if TARGET_P2771_0000
+
+config SYS_BOARD
+	default "p2771-0000"
+
+config SYS_VENDOR
+	default "nvidia"
+
+config SYS_CONFIG_NAME
+	default "p2771-0000"
+
+endif
diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS
new file mode 100644
index 0000000000..4fc4ebd5e0
--- /dev/null
+++ b/board/nvidia/p2771-0000/MAINTAINERS
@@ -0,0 +1,6 @@
+P2771-0000 BOARD
+M:	Stephen Warren <swarren@nvidia.com>
+S:	Maintained
+F:	board/nvidia/p2771-0000/
+F:	include/configs/p2771-0000.h
+F:	configs/p2771-0000_defconfig
diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile
new file mode 100644
index 0000000000..b28a47d907
--- /dev/null
+++ b/board/nvidia/p2771-0000/Makefile
@@ -0,0 +1,5 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y	+= p2771-0000.o
diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c
new file mode 100644
index 0000000000..4ba8ebc0dc
--- /dev/null
+++ b/board/nvidia/p2771-0000/p2771-0000.c
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c
index 2d07001800..fc9c1c9b34 100644
--- a/board/nvidia/seaboard/seaboard.c
+++ b/board/nvidia/seaboard/seaboard.c
@@ -20,8 +20,8 @@
 void gpio_early_init_uart(void)
 {
 	/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
-	gpio_request(GPIO_PI3, "uart_en");
-	gpio_direction_output(GPIO_PI3, 0);
+	gpio_request(TEGRA_GPIO(I, 3), "uart_en");
+	gpio_direction_output(TEGRA_GPIO(I, 3), 0);
 }
 #endif
 
diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h
index fb444b3b1d..59d53efe44 100644
--- a/board/nvidia/venice2/pinmux-config-venice2.h
+++ b/board/nvidia/venice2/pinmux-config-venice2.h
@@ -15,70 +15,70 @@
 #ifndef _PINMUX_CONFIG_VENICE2_H_
 #define _PINMUX_CONFIG_VENICE2_H_
 
-#define GPIO_INIT(_gpio, _init)				\
+#define GPIO_INIT(_port, _gpio, _init)			\
 	{						\
-		.gpio	= GPIO_P##_gpio,		\
+		.gpio	= TEGRA_GPIO(_port, _gpio),	\
 		.init	= TEGRA_GPIO_INIT_##_init,	\
 	}
 
 static const struct tegra_gpio_config venice2_gpio_inits[] = {
-	/*        gpio, init_val */
-	GPIO_INIT(A0,   IN),
-	GPIO_INIT(C7,   IN),
-	GPIO_INIT(G0,   IN),
-	GPIO_INIT(G1,   IN),
-	GPIO_INIT(G2,   IN),
-	GPIO_INIT(G3,   IN),
-	GPIO_INIT(H2,   IN),
-	GPIO_INIT(H4,   IN),
-	GPIO_INIT(H5,   OUT0),
-	GPIO_INIT(H6,   IN),
-	GPIO_INIT(H7,   OUT1),
-	GPIO_INIT(I0,   IN),
-	GPIO_INIT(I1,   IN),
-	GPIO_INIT(I2,   OUT0),
-	GPIO_INIT(I4,   OUT0),
-	GPIO_INIT(I5,   OUT1),
-	GPIO_INIT(I6,   IN),
-	GPIO_INIT(J0,   IN),
-	GPIO_INIT(J7,   IN),
-	GPIO_INIT(K0,   IN),
-	GPIO_INIT(K1,   OUT0),
-	GPIO_INIT(K2,   IN),
-	GPIO_INIT(K3,   IN),
-	GPIO_INIT(K4,   OUT0),
-	GPIO_INIT(K6,   OUT0),
-	GPIO_INIT(K7,   IN),
-	GPIO_INIT(N7,   IN),
-	GPIO_INIT(O2,   IN),
-	GPIO_INIT(O5,   IN),
-	GPIO_INIT(O6,   OUT0),
-	GPIO_INIT(O7,   IN),
-	GPIO_INIT(P2,   OUT0),
-	GPIO_INIT(Q0,   IN),
-	GPIO_INIT(Q2,   IN),
-	GPIO_INIT(Q3,   IN),
-	GPIO_INIT(Q6,   IN),
-	GPIO_INIT(Q7,   IN),
-	GPIO_INIT(R0,   OUT0),
-	GPIO_INIT(R1,   IN),
-	GPIO_INIT(R4,   IN),
-	GPIO_INIT(S0,   IN),
-	GPIO_INIT(S3,   OUT0),
-	GPIO_INIT(S4,   OUT0),
-	GPIO_INIT(S7,   IN),
-	GPIO_INIT(T1,   IN),
-	GPIO_INIT(U4,   IN),
-	GPIO_INIT(U5,   IN),
-	GPIO_INIT(U6,   IN),
-	GPIO_INIT(V0,   IN),
-	GPIO_INIT(V1,   IN),
-	GPIO_INIT(W3,   IN),
-	GPIO_INIT(X1,   IN),
-	GPIO_INIT(X3,   IN),
-	GPIO_INIT(X4,   IN),
-	GPIO_INIT(X7,   OUT0),
-	GPIO_INIT(CC5,  OUT0),
+	/*        port, pin, init_val */
+	GPIO_INIT(A,    0,   IN),
+	GPIO_INIT(C,    7,   IN),
+	GPIO_INIT(G,    0,   IN),
+	GPIO_INIT(G,    1,   IN),
+	GPIO_INIT(G,    2,   IN),
+	GPIO_INIT(G,    3,   IN),
+	GPIO_INIT(H,    2,   IN),
+	GPIO_INIT(H,    4,   IN),
+	GPIO_INIT(H,    5,   OUT0),
+	GPIO_INIT(H,    6,   IN),
+	GPIO_INIT(H,    7,   OUT1),
+	GPIO_INIT(I,    0,   IN),
+	GPIO_INIT(I,    1,   IN),
+	GPIO_INIT(I,    2,   OUT0),
+	GPIO_INIT(I,    4,   OUT0),
+	GPIO_INIT(I,    5,   OUT1),
+	GPIO_INIT(I,    6,   IN),
+	GPIO_INIT(J,    0,   IN),
+	GPIO_INIT(J,    7,   IN),
+	GPIO_INIT(K,    0,   IN),
+	GPIO_INIT(K,    1,   OUT0),
+	GPIO_INIT(K,    2,   IN),
+	GPIO_INIT(K,    3,   IN),
+	GPIO_INIT(K,    4,   OUT0),
+	GPIO_INIT(K,    6,   OUT0),
+	GPIO_INIT(K,    7,   IN),
+	GPIO_INIT(N,    7,   IN),
+	GPIO_INIT(O,    2,   IN),
+	GPIO_INIT(O,    5,   IN),
+	GPIO_INIT(O,    6,   OUT0),
+	GPIO_INIT(O,    7,   IN),
+	GPIO_INIT(P,    2,   OUT0),
+	GPIO_INIT(Q,    0,   IN),
+	GPIO_INIT(Q,    2,   IN),
+	GPIO_INIT(Q,    3,   IN),
+	GPIO_INIT(Q,    6,   IN),
+	GPIO_INIT(Q,    7,   IN),
+	GPIO_INIT(R,    0,   OUT0),
+	GPIO_INIT(R,    1,   IN),
+	GPIO_INIT(R,    4,   IN),
+	GPIO_INIT(S,    0,   IN),
+	GPIO_INIT(S,    3,   OUT0),
+	GPIO_INIT(S,    4,   OUT0),
+	GPIO_INIT(S,    7,   IN),
+	GPIO_INIT(T,    1,   IN),
+	GPIO_INIT(U,    4,   IN),
+	GPIO_INIT(U,    5,   IN),
+	GPIO_INIT(U,    6,   IN),
+	GPIO_INIT(V,    0,   IN),
+	GPIO_INIT(V,    1,   IN),
+	GPIO_INIT(W,    3,   IN),
+	GPIO_INIT(X,    1,   IN),
+	GPIO_INIT(X,    3,   IN),
+	GPIO_INIT(X,    4,   IN),
+	GPIO_INIT(X,    7,   OUT0),
+	GPIO_INIT(CC,   5,   OUT0),
 };
 
 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel)	\
diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 251db6ab63..ef8905d46a 100644
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -9,4 +9,19 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "pb1x00"
 
+config SYS_TEXT_BASE
+	default 0x83800000
+
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 endif
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
index 81f3024ed9..d91d427c6b 100644
--- a/board/pdm360ng/pdm360ng.c
+++ b/board/pdm360ng/pdm360ng.c
@@ -429,7 +429,7 @@ int checkboard (void)
 	return 0;
 }
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
 struct node_info nodes[] = {
 	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
@@ -529,7 +529,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 /*
  * If argument is NULL, set the LCD brightness to the
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
index ed41de13d4..8a9de0d963 100644
--- a/board/phytec/pcm030/pcm030.c
+++ b/board/phytec/pcm030/pcm030.c
@@ -163,14 +163,14 @@ void pci_init_board(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	ft_cpu_setup(blob, bd);
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index f7e768ad58..4fd6a7167a 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -9,4 +9,19 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap121"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 endif
diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c
index d6c60fea86..e245faa5cf 100644
--- a/board/qca/ap121/ap121.c
+++ b/board/qca/ap121/ap121.c
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -46,5 +47,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 4cdac0d06d..74c632a03e 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -9,4 +9,19 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "ap143"
 
+config SYS_TEXT_BASE
+	default 0x9f000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 endif
diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c
index 1572472ca3..e921ea53f3 100644
--- a/board/qca/ap143/ap143.c
+++ b/board/qca/ap143/ap143.c
@@ -10,6 +10,7 @@
 #include <asm/types.h>
 #include <mach/ar71xx_regs.h>
 #include <mach/ddr.h>
+#include <mach/ath79.h>
 #include <debug_uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -62,5 +63,6 @@ int board_early_init_f(void)
 	debug_uart_init();
 #endif
 	ddr_init();
+	ath79_eth_reset();
 	return 0;
 }
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 18d78b5100..e696a12192 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -7,4 +7,20 @@ config SYS_CONFIG_NAME
 	default "qemu-mips" if 32BIT
 	default "qemu-mips64" if 64BIT
 
+config SYS_TEXT_BASE
+	default 0xbfc00000 if 32BIT
+	default 0xffffffffbfc00000 if 64BIT
+
+config SYS_DCACHE_SIZE
+	default 16384
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 16384
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 endif
diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds
index 053df642ea..6cd4056bc0 100644
--- a/board/renesas/sh7752evb/u-boot.lds
+++ b/board/renesas/sh7752evb/u-boot.lds
@@ -65,6 +65,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/board/renesas/sh7753evb/u-boot.lds b/board/renesas/sh7753evb/u-boot.lds
index 053df642ea..6cd4056bc0 100644
--- a/board/renesas/sh7753evb/u-boot.lds
+++ b/board/renesas/sh7753evb/u-boot.lds
@@ -65,6 +65,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds
index 4027fe3af5..d701367603 100644
--- a/board/renesas/sh7757lcr/u-boot.lds
+++ b/board/renesas/sh7757lcr/u-boot.lds
@@ -66,6 +66,7 @@ SECTIONS
 		KEEP(*(SORT(.u_boot_list*)));
 	}
 
+	PROVIDE (__init_end = .);
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index 3cc01cb687..e2cb94ee13 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -194,7 +194,7 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 276ff80943..e9f9b67b77 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -293,7 +293,7 @@ void lcd_show_board_info(void)
 
 	nand_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += nand_info[i].size;
+		nand_size += nand_info[i]->size;
 
 	flash_size = 0;
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c
index 1334c22ddd..0eb066ce47 100644
--- a/board/samsung/common/board.c
+++ b/board/samsung/common/board.c
@@ -27,6 +27,8 @@
 #include <usb.h>
 #include <dwc3-uboot.h>
 #include <samsung/misc.h>
+#include <dm/pinctrl.h>
+#include <dm.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -97,7 +99,7 @@ int board_init(void)
 int dram_init(void)
 {
 	unsigned int i;
-	u32 addr;
+	unsigned long addr;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -109,7 +111,7 @@ int dram_init(void)
 void dram_init_banksize(void)
 {
 	unsigned int i;
-	u32 addr, size;
+	unsigned long addr, size;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
@@ -122,6 +124,7 @@ void dram_init_banksize(void)
 
 static int board_uart_init(void)
 {
+#ifndef CONFIG_PINCTRL_EXYNOS
 	int err, uart_id, ret = 0;
 
 	for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
@@ -133,6 +136,9 @@ static int board_uart_init(void)
 		}
 	}
 	return ret;
+#else
+	return 0;
+#endif
 }
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
@@ -152,21 +158,6 @@ int board_early_init_f(void)
 	board_i2c_init(gd->fdt_blob);
 #endif
 
-#if defined(CONFIG_EXYNOS_FB)
-	/*
-	 * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
-	 * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix,
-	 * to reserve frame-buffer memory at a very early stage. So, we need
-	 * to fill panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix
-	 * before lcd_setmem() is called.
-	 */
-	err = exynos_lcd_early_init(gd->fdt_blob);
-	if (err) {
-		debug("LCD early init failed\n");
-		return err;
-	}
-#endif
-
 	return exynos_early_init_f();
 }
 #endif
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 4d9e151756..2e3b16df45 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -147,164 +147,6 @@ int board_get_revision(void)
 	return 0;
 }
 
-#ifdef CONFIG_LCD
-
-static int board_dp_bridge_init(struct udevice *dev)
-{
-	const int max_tries = 10;
-	int num_tries;
-	int ret;
-
-	debug("%s\n", __func__);
-	ret = video_bridge_attach(dev);
-	if (ret) {
-		debug("video bridge init failed: %d\n", ret);
-		return ret;
-	}
-
-	/*
-	 * We need to wait for 90ms after bringing up the bridge since there
-	 * is a phantom "high" on the HPD chip during its bootup.  The phantom
-	 * high comes within 7ms of de-asserting PD and persists for at least
-	 * 15ms.  The real high comes roughly 50ms after PD is de-asserted. The
-	 * phantom high makes it hard for us to know when the NXP chip is up.
-	 */
-	mdelay(90);
-
-	for (num_tries = 0; num_tries < max_tries; num_tries++) {
-		/* Check HPD. If it's high, or we don't have it, all is well */
-		ret = video_bridge_check_attached(dev);
-		if (!ret || ret == -ENOENT)
-			return 0;
-
-		debug("%s: eDP bridge failed to come up; try %d of %d\n",
-		      __func__, num_tries, max_tries);
-	}
-
-	/* Immediately go into bridge reset if the hp line is not high */
-	return -EIO;
-}
-
-static int board_dp_bridge_setup(const void *blob)
-{
-	const int max_tries = 2;
-	int num_tries;
-	struct udevice *dev;
-	int ret;
-
-	/* Configure I2C registers for Parade bridge */
-	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
-	if (ret) {
-		debug("video bridge init failed: %d\n", ret);
-		return ret;
-	}
-
-	if (strncmp(dev->driver->name, "parade", 6)) {
-		/* Mux HPHPD to the special hotplug detect mode */
-		exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
-	}
-
-	for (num_tries = 0; num_tries < max_tries; num_tries++) {
-		ret = board_dp_bridge_init(dev);
-		if (!ret)
-			return 0;
-		if (num_tries == max_tries - 1)
-			break;
-
-		/*
-		* If we're here, the bridge chip failed to initialise.
-		* Power down the bridge in an attempt to reset.
-		*/
-		video_bridge_set_active(dev, false);
-
-		/*
-		* Arbitrarily wait 300ms here with DP_N low.  Don't know for
-		* sure how long we should wait, but we're being paranoid.
-		*/
-		mdelay(300);
-	}
-
-	return ret;
-}
-
-void exynos_cfg_lcd_gpio(void)
-{
-	/* For Backlight */
-	gpio_request(EXYNOS5_GPIO_B20, "lcd_backlight");
-	gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_OUTPUT);
-	gpio_set_value(EXYNOS5_GPIO_B20, 1);
-}
-
-void exynos_set_dp_phy(unsigned int onoff)
-{
-	set_dp_phy_ctrl(onoff);
-}
-
-static int board_dp_set_backlight(int percent)
-{
-	struct udevice *dev;
-	int ret;
-
-	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
-	if (!ret)
-		ret = video_bridge_set_backlight(dev, percent);
-
-	return ret;
-}
-
-void exynos_backlight_on(unsigned int on)
-{
-	struct udevice *dev;
-	int ret;
-
-	debug("%s(%u)\n", __func__, on);
-	if (!on)
-		return;
-
-	ret = regulator_get_by_platname("vcd_led", &dev);
-	if (!ret)
-		ret = regulator_set_enable(dev, true);
-	if (ret)
-		debug("Failed to enable backlight: ret=%d\n", ret);
-
-	/* T5 in the LCD timing spec (defined as > 10ms) */
-	mdelay(10);
-
-	/* board_dp_backlight_pwm */
-	gpio_direction_output(EXYNOS5_GPIO_B20, 1);
-
-	/* T6 in the LCD timing spec (defined as > 10ms) */
-	mdelay(10);
-
-	/* try to set the backlight in the bridge registers */
-	ret = board_dp_set_backlight(80);
-
-	/* if we have no bridge or it does not support backlight, use a GPIO */
-	if (ret == -ENODEV || ret == -ENOSYS) {
-		gpio_request(EXYNOS5_GPIO_X30, "board_dp_backlight_en");
-		gpio_direction_output(EXYNOS5_GPIO_X30, 1);
-	}
-}
-
-void exynos_lcd_power_on(void)
-{
-	struct udevice *dev;
-	int ret;
-
-	debug("%s\n", __func__);
-	ret = regulator_get_by_platname("lcd_vdd", &dev);
-	if (!ret)
-		ret = regulator_set_enable(dev, true);
-	if (ret)
-		debug("Failed to enable LCD panel: ret=%d\n", ret);
-
-	ret = board_dp_bridge_setup(gd->fdt_blob);
-	if (ret && ret != -ENODEV)
-		printf("LCD bridge failed to enable: %d\n", ret);
-}
-
-#endif
-
 #ifdef CONFIG_USB_DWC3
 static struct dwc3_device dwc3_device_data = {
 	.maximum_speed = USB_SPEED_SUPER,
diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c
index da0d4db1f9..77d0a4e837 100644
--- a/board/samsung/common/misc.c
+++ b/board/samsung/common/misc.c
@@ -147,6 +147,7 @@ static int key_pressed(int key)
 	return value;
 }
 
+#ifdef CONFIG_LCD
 static int check_keys(void)
 {
 	int keys = 0;
@@ -235,9 +236,11 @@ static void display_board_info(void)
 
 	lcd_printf("\tDisplay BPP: %u\n", 1 << vid->vl_bpix);
 }
+#endif
 
 static int mode_leave_menu(int mode)
 {
+#ifdef CONFIG_LCD
 	char *exit_option;
 	char *exit_reset = "reset";
 	char *exit_back = "back";
@@ -301,8 +304,12 @@ static int mode_leave_menu(int mode)
 
 	lcd_clear();
 	return leave;
+#else
+	return 0;
+#endif
 }
 
+#ifdef CONFIG_LCD
 static void display_download_menu(int mode)
 {
 	char *selection[BOOT_MODE_EXIT + 1];
@@ -320,9 +327,11 @@ static void display_download_menu(int mode)
 		lcd_printf("\t%s  %s - %s\n\n", selection[i],
 			   mode_name[i][0], mode_info[i]);
 }
+#endif
 
 static void download_menu(void)
 {
+#ifdef CONFIG_LCD
 	int mode = 0;
 	int last_mode = 0;
 	int run;
@@ -393,6 +402,7 @@ static void download_menu(void)
 	}
 
 	lcd_clear();
+#endif
 }
 
 void check_boot_mode(void)
diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
new file mode 100644
index 0000000000..62251c5126
--- /dev/null
+++ b/board/samsung/espresso7420/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_ESPRESSO7420
+
+config SYS_BOARD
+	default "espresso7420"
+	help
+	  Espresso7420 is a development/evaluation board for Exynos7420 SoC.
+	  It includes multiple onboard compoments (EMMC/Codec) and various
+	  interconnects (USB/HDMI).
+
+config SYS_VENDOR
+	default "samsung"
+
+config SYS_CONFIG_NAME
+	default "espresso7420"
+
+endif
diff --git a/board/samsung/espresso7420/MAINTAINERS b/board/samsung/espresso7420/MAINTAINERS
new file mode 100644
index 0000000000..aaebc4c22d
--- /dev/null
+++ b/board/samsung/espresso7420/MAINTAINERS
@@ -0,0 +1,5 @@
+ESPRESSO7420 Board
+M:	Thomas Abraham <thomas.ab@samsung.com>
+S:	Maintained
+F:	board/samsung/espresso7420/
+F:	include/configs/espresso7420.h
diff --git a/board/samsung/espresso7420/Makefile b/board/samsung/espresso7420/Makefile
new file mode 100644
index 0000000000..d514dc2a45
--- /dev/null
+++ b/board/samsung/espresso7420/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef CONFIG_SPL_BUILD
+obj-y	+= espresso7420.o
+endif
diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c
new file mode 100644
index 0000000000..04a83bc07d
--- /dev/null
+++ b/board/samsung/espresso7420/espresso7420.c
@@ -0,0 +1,16 @@
+/*
+ * Espresso7420 board file
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int exynos_init(void)
+{
+	return 0;
+}
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 54d01ec439..66a54d436d 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -596,6 +596,7 @@ int mipi_power(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN
@@ -606,3 +607,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 	setenv("lcdinfo", "lcd=s6e8ax0");
 #endif
 }
+#endif
diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c
index 426ae14af2..81e35b6f75 100644
--- a/board/samsung/universal_c210/universal.c
+++ b/board/samsung/universal_c210/universal.c
@@ -367,6 +367,7 @@ int exynos_init(void)
 	return 0;
 }
 
+#ifdef CONFIG_LCD
 void exynos_lcd_misc_init(vidinfo_t *vid)
 {
 #ifdef CONFIG_TIZEN
@@ -379,3 +380,4 @@ void exynos_lcd_misc_init(vidinfo_t *vid)
 
 	setenv("lcdinfo", "lcd=ld9040");
 }
+#endif
diff --git a/board/samtec/vining_fpga/MAINTAINERS b/board/samtec/vining_fpga/MAINTAINERS
new file mode 100644
index 0000000000..c2002fe3ce
--- /dev/null
+++ b/board/samtec/vining_fpga/MAINTAINERS
@@ -0,0 +1,5 @@
+VINING FPGA BOARD
+M:	Marek Vasut <marex@denx.de>
+S:	Maintained
+F:	include/configs/socfpga_vining_fpga.h
+F:	configs/socfpga_vining_fpga_defconfig
diff --git a/board/samtec/vining_fpga/Makefile b/board/samtec/vining_fpga/Makefile
new file mode 100644
index 0000000000..86f9b78cad
--- /dev/null
+++ b/board/samtec/vining_fpga/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/samtec/vining_fpga/qts/iocsr_config.h b/board/samtec/vining_fpga/qts/iocsr_config.h
new file mode 100644
index 0000000000..fe5cb61a62
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/iocsr_config.h
@@ -0,0 +1,660 @@
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x00000000,
+	0x300C0000,
+	0x000000C0,
+	0x00000000,
+	0x00000000,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00601806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x300C0300,
+	0x300C0000,
+	0x0FF00000,
+	0x00000000,
+	0x000300C0,
+	0x00008000,
+	0x18060180,
+	0x18060000,
+	0x00000000,
+	0x00000000,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x00000030,
+	0x00000000,
+	0x0300C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+	0x0000C030,
+	0x00000000,
+	0x03000000,
+	0x0000000C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0xE4400000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680A28,
+	0x41034051,
+	0x12481A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A02490,
+	0x080D0000,
+	0x51406802,
+	0x02490340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0xC8800000,
+	0x00003001,
+	0x00C00722,
+	0x00000FF0,
+	0x72200000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x00001800,
+	0x00600391,
+	0x800E4400,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x72200000,
+	0x80000C00,
+	0x003001C8,
+	0xC0072200,
+	0x1C880000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x49034051,
+	0x12481A02,
+	0x80A280D0,
+	0x34030C06,
+	0x01A00040,
+	0x280D0002,
+	0x5140680A,
+	0x02490340,
+	0xD012481A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x00000000,
+	0x01800E44,
+	0x00391000,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3D5,
+	0xF6D1451E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x05140680,
+	0xD569A47A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00035292,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8A28A3D5,
+	0xF4D1451E,
+	0x034AD348,
+	0x821A0186,
+	0x0000D000,
+	0x00000680,
+	0xD569A47A,
+	0x1EF228A3,
+	0x48F4D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F36080,
+	0x1A041404,
+	0x00D00000,
+	0x0C864000,
+	0x59647A03,
+	0xCB2CA3DD,
+	0xF6D9651E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1E8A28A3,
+	0x48F6D965,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0x7FFFFFFF,
+	0x14F16080,
+	0x1A041404,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0xF228A3D5,
+	0xF4D1451E,
+	0x03529248,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8A28A3,
+	0x48F6D145,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pinmux_config.h b/board/samtec/vining_fpga/qts/pinmux_config.h
new file mode 100644
index 0000000000..968036587d
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pinmux_config.h
@@ -0,0 +1,219 @@
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	2, /* FLASHIO0 */
+	2, /* FLASHIO1 */
+	2, /* FLASHIO2 */
+	2, /* FLASHIO3 */
+	2, /* FLASHIO4 */
+	2, /* FLASHIO5 */
+	2, /* FLASHIO6 */
+	2, /* FLASHIO7 */
+	2, /* FLASHIO8 */
+	2, /* FLASHIO9 */
+	2, /* FLASHIO10 */
+	2, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	2, /* GENERALIO15 */
+	2, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	2, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	1, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	1, /* SPIS1USEFPGA */
+	1, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/pll_config.h b/board/samtec/vining_fpga/qts/pll_config.h
new file mode 100644
index 0000000000..c8a6e961fd
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/pll_config.h
@@ -0,0 +1,91 @@
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 488281
+#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/qts/sdram_config.h b/board/samtec/vining_fpga/qts/sdram_config.h
new file mode 100644
index 0000000000..74cb405601
--- /dev/null
+++ b/board/samtec/vining_fpga/qts/sdram_config.h
@@ -0,0 +1,341 @@
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		200
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0		0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x5555048c
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090046,
+	0x100a0088,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0026,
+	0x10090110,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c
new file mode 100644
index 0000000000..f3a92b5e64
--- /dev/null
+++ b/board/samtec/vining_fpga/socfpga.c
@@ -0,0 +1,100 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_late_init(void)
+{
+	const unsigned int phy_nrst_gpio = 0;
+	const unsigned int usb_nrst_gpio = 35;
+	int ret;
+
+	status_led_set(1, STATUS_LED_ON);
+	status_led_set(2, STATUS_LED_ON);
+
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(phy_nrst_gpio, 1);
+	else
+		printf("Cannot remove PHY from reset!\n");
+
+	ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
+	if (!ret)
+		gpio_direction_output(usb_nrst_gpio, 1);
+	else
+		printf("Cannot remove USB from reset!\n");
+
+	mdelay(50);
+
+	return 0;
+}
+
+#ifndef CONFIG_SPL_BUILD
+int misc_init_r(void)
+{
+	uchar data[128];
+	char str[32];
+	u32 serial;
+	int ret;
+
+	/* EEPROM is at bus 0. */
+	ret = i2c_set_bus_num(0);
+	if (ret) {
+		puts("Cannot select EEPROM I2C bus.\n");
+		return 0;
+	}
+
+	/* EEPROM is at address 0x50. */
+	ret = eeprom_read(0x50, 0, data, sizeof(data));
+	if (ret) {
+		puts("Cannot read I2C EEPROM.\n");
+		return 0;
+	}
+
+	/* Check EEPROM signature. */
+	if (!(data[0] == 0xa5 && data[1] == 0x5a)) {
+		puts("Invalid I2C EEPROM signature.\n");
+		setenv("unit_serial", "invalid");
+		setenv("unit_ident", "VINing-xxxx-STD");
+		setenv("hostname", "vining-invalid");
+		return 0;
+	}
+
+	/* If 'unit_serial' is already set, do nothing. */
+	if (!getenv("unit_serial")) {
+		/* This field is Big Endian ! */
+		serial = (data[0x54] << 24) | (data[0x55] << 16) |
+			 (data[0x56] << 8) | (data[0x57] << 0);
+		memset(str, 0, sizeof(str));
+		sprintf(str, "%07i", serial);
+		setenv("unit_serial", str);
+	}
+
+	if (!getenv("unit_ident")) {
+		memset(str, 0, sizeof(str));
+		memcpy(str, &data[0x2e], 18);
+		setenv("unit_ident", str);
+	}
+
+	/* Set ethernet address from EEPROM. */
+	if (!getenv("ethaddr") && is_valid_ethaddr(&data[0x62]))
+		eth_setenv_enetaddr("ethaddr", &data[0x62]);
+
+	return 0;
+}
+#endif
diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox
index fa1842bc00..9fe3bf171a 100644
--- a/board/sandbox/README.sandbox
+++ b/board/sandbox/README.sandbox
@@ -186,8 +186,7 @@ U-Boot sandbox supports these emulations:
 A wide range of commands is implemented. Filesystems which use a block
 device are supported.
 
-Also sandbox uses generic board (CONFIG_SYS_GENERIC_BOARD) and supports
-driver model (CONFIG_DM) and associated commands.
+Also sandbox supports driver model (CONFIG_DM) and associated commands.
 
 
 Linux RAW Networking Bridge
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index c127f6ca27..9cafcea53a 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -83,8 +83,12 @@ int board_init(void)
 #ifdef CONFIG_FACTORYSET
 	factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
 #endif
+
 	gpmc_init();
 
+#ifdef CONFIG_NAND_CS_INIT
+	board_nand_cs_init();
+#endif
 #ifdef CONFIG_VIDEO
 	board_video_init();
 #endif
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 819d187087..a699c7d46f 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
 	default "rastaban"
 
 endif
+
+if TARGET_ETAMIN
+
+config SYS_BOARD
+        default "draco"
+
+config SYS_VENDOR
+        default "siemens"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "etamin"
+
+endif
diff --git a/board/siemens/draco/MAINTAINERS b/board/siemens/draco/MAINTAINERS
index 484dd739c1..e9107f08bf 100644
--- a/board/siemens/draco/MAINTAINERS
+++ b/board/siemens/draco/MAINTAINERS
@@ -4,6 +4,7 @@ S:	Maintained
 F:	board/siemens/draco/
 F:	include/configs/draco.h
 F:	configs/draco_defconfig
+F:	configs/etamin_defconfig
 F:	include/configs/thuban.h
 F:	configs/thuban_defconfig
 F:	include/configs/rastaban.h
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index 988c12ac7c..d8869a09dd 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -24,6 +24,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
@@ -33,6 +34,7 @@
 #include <watchdog.h>
 #include "board.h"
 #include "../common/factoryset.h"
+#include <nand.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct draco_baseboard_id __attribute__((section(".data"))) settings;
 
 #if DDR_PLL_FREQ == 303
+#if !defined(CONFIG_TARGET_ETAMIN)
 /* Default@303MHz-i0 */
 const struct ddr3_data ddr3_default = {
 	0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
 	"default name @303MHz           \0",
 	"default marking                \0",
 };
+#else
+/* etamin board */
+const struct ddr3_data ddr3_default = {
+	0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
+	0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
+	0x0000093B, 0x0000018A,
+	"test-etamin                    \0",
+	"generic-8Gbit                  \0",
+};
+#endif
 #elif DDR_PLL_FREQ == 400
 /* Default@400MHz-i0 */
 const struct ddr3_data ddr3_default = {
@@ -105,6 +118,40 @@ static void print_chip_data(void)
 }
 #endif /* CONFIG_SPL_BUILD */
 
+#define AM335X_NAND_ECC_MASK 0x0f
+#define AM335X_NAND_ECC_TYPE_16 0x02
+
+static int ecc_type;
+
+struct am335x_nand_geometry {
+	u32 magic;
+	u8 nand_geo_addr;
+	u8 nand_geo_page;
+	u8 nand_bus;
+};
+
+static int draco_read_nand_geometry(void)
+{
+	struct am335x_nand_geometry geo;
+
+	/* Read NAND geometry */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x80, 2,
+		     (uchar *)&geo, sizeof(struct am335x_nand_geometry))) {
+		printf("Could not read the NAND geomtery; something fundamentally wrong on the I2C bus.\n");
+		return -EIO;
+	}
+	if (geo.magic != 0xa657b310) {
+		printf("%s: bad magic: %x\n", __func__, geo.magic);
+		return -EFAULT;
+	}
+	if ((geo.nand_bus & AM335X_NAND_ECC_MASK) == AM335X_NAND_ECC_TYPE_16)
+		ecc_type = 16;
+	else
+		ecc_type = 8;
+
+	return 0;
+}
+
 /*
  * Read header information from EEPROM into global structure.
  */
@@ -147,6 +194,8 @@ static int read_eeprom(void)
 		printf("Warning: No chip data in eeprom\n");
 
 	print_ddr3_timings();
+
+	return draco_read_nand_geometry();
 #endif
 	return 0;
 }
@@ -174,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
 	draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 		settings.ddr3.emif_ddr_phy_ctlr_1;
 	draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
+	draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
 	draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 
 	draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
@@ -207,7 +257,18 @@ static void spl_siemens_board_init(void)
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
-	omap_nand_switch_ecc(1, 8);
+	int ret;
+
+	ret = draco_read_nand_geometry();
+	if (ret != 0)
+		return ret;
+
+	nand_curr_device = 0;
+	omap_nand_switch_ecc(1, ecc_type);
+#ifdef CONFIG_TARGET_ETAMIN
+	nand_curr_device = 1;
+	omap_nand_switch_ecc(1, ecc_type);
+#endif
 #ifdef CONFIG_FACTORYSET
 	/* Set ASN in environment*/
 	if (factory_dat.asn[0] != 0) {
@@ -283,7 +344,7 @@ int board_eth_init(bd_t *bis)
 }
 
 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
-			   char *const argv[])
+			  char *const argv[])
 {
 	/* Reset SMSC LAN9303 switch for default configuration */
 	gpio_request(GPIO_LAN9303_NRST, "nRST");
@@ -303,4 +364,23 @@ U_BOOT_CMD(
 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 
+#ifdef CONFIG_NAND_CS_INIT
+/* GPMC definitions for second nand cs1 */
+static const u32 gpmc_nand_config[] = {
+	ETAMIN_NAND_GPMC_CONFIG1,
+	ETAMIN_NAND_GPMC_CONFIG2,
+	ETAMIN_NAND_GPMC_CONFIG3,
+	ETAMIN_NAND_GPMC_CONFIG4,
+	ETAMIN_NAND_GPMC_CONFIG5,
+	ETAMIN_NAND_GPMC_CONFIG6,
+	/*CONFIG7- computed as params */
+};
+
+static void board_nand_cs_init(void)
+{
+	enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
+			      0x18000000, GPMC_SIZE_16M);
+}
+#endif
+
 #include "../common/board.c"
diff --git a/board/siemens/draco/mux.c b/board/siemens/draco/mux.c
index dbcc80b61f..38a484eb43 100644
--- a/board/siemens/draco/mux.c
+++ b/board/siemens/draco/mux.c
@@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
 	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
 	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN},    /* NAND_CS1 */
 	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
 	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
 	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
@@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = {
 	{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y3 GPIO2_28*/
 	{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y7 GPIO2_27*/
 	/* Triacs initial HW Rev */
-	{OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_30 Y0 */
 	{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_28 Y1 */
 	{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_31 Y2 */
 	{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_11 Y3 */
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 15e6ea6944..a67d812c81 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -48,7 +48,7 @@ static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte)
 static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++) {
 		out_be32(this->IO_ADDR_W,
@@ -88,7 +88,7 @@ static u16 sc_nand_read_word(struct mtd_info *mtd)
 static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int val;
 
 	val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ;
@@ -105,7 +105,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  */
 static int sc_nand_device_ready(struct mtd_info *mtdinfo)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 
 	if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY)
 		return 0; /* busy */
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 953a43ff31..8b34a80e8f 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -217,7 +217,7 @@ int board_early_init_r (void)
 }
 #endif /* CONFIG_BOARD_EARLY_INIT_R */
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	u32 val[12];
@@ -253,7 +253,7 @@ int ft_board_setup(void *blob, bd_t *bd)
 
 	return 0;
 }
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+#endif /* CONFIG_OF_BOARD_SETUP */
 
 #define DEFAULT_BRIGHTNESS	25
 #define BACKLIGHT_ENABLE	(1 << 31)
diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c
index b8edfcd071..f8e9fddb0f 100644
--- a/board/spear/x600/x600.c
+++ b/board/spear/x600/x600.c
@@ -8,6 +8,7 @@
  */
 
 #include <common.h>
+#include <micrel.h>
 #include <nand.h>
 #include <netdev.h>
 #include <phy.h>
@@ -69,27 +70,64 @@ void board_nand_init(void)
 
 int board_phy_config(struct phy_device *phydev)
 {
-	/* Extended PHY control 1, select GMII */
-	phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
-
-	/* Software reset necessary after GMII mode selction */
-	phy_reset(phydev);
-
-	/* Enable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
-
-	/* 17e: Enhanced LED behavior, needs to be written twice */
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-	phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
-
-	/* 16e: Enhanced LED method select */
-	phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
-
-	/* Disable extended page register access */
-	phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
-
-	/* Enable clock output pin */
-	phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+	unsigned short id1, id2;
+
+	/* check whether KSZ9031 or AR8035 has to be configured */
+	id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2);
+	id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3);
+
+	if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) {
+		/* PHY configuration for Micrel KSZ9031 */
+		printf("PHY KSZ9031 detected - ");
+
+		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
+
+		/* control data pad skew - devaddr = 0x02, register = 0x04 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* rx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* tx data pad skew - devaddr = 0x02, register = 0x05 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x0000);
+		/* gtx and rx clock pad skew - devaddr = 0x02, reg = 0x08 */
+		ksz9031_phy_extended_write(phydev, 0x02,
+					   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+					   MII_KSZ9031_MOD_DATA_NO_POST_INC,
+					   0x03FF);
+	} else {
+		/* PHY configuration for Vitesse VSC8641 */
+		printf("PHY VSC8641 detected - ");
+
+		/* Extended PHY control 1, select GMII */
+		phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
+
+		/* Software reset necessary after GMII mode selction */
+		phy_reset(phydev);
+
+		/* Enable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
+
+		/* 17e: Enhanced LED behavior, needs to be written twice */
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+		phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
+
+		/* 16e: Enhanced LED method select */
+		phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
+
+		/* Disable extended page register access */
+		phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
+
+		/* Enable clock output pin */
+		phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
+	}
 
 	if (phydev->drv->config)
 		phydev->drv->config(phydev);
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index fa7872031b..c1ae6f5d9e 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -18,7 +18,6 @@ config SUNXI_GEN_SUN6I
 
 choice
 	prompt "Sunxi SoC Variant"
-	optional
 
 config MACH_SUN4I
 	bool "sun4i (Allwinner A10)"
@@ -68,6 +67,12 @@ config MACH_SUN8I_A33
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
+config MACH_SUN8I_A83T
+	bool "sun8i (Allwinner A83T)"
+	select CPU_V7
+	select SUNXI_GEN_SUN6I
+	select SUPPORT_SPL
+
 config MACH_SUN8I_H3
 	bool "sun8i (Allwinner H3)"
 	select CPU_V7
@@ -77,22 +82,16 @@ config MACH_SUN8I_H3
 	select SUPPORT_SPL
 	select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 
-config MACH_SUN50I
-	bool "sun50i (Allwinner A64)"
-	select ARM64
-	select SUNXI_GEN_SUN6I
-
-config MACH_SUN8I_A83T
-	bool "sun8i (Allwinner A83T)"
-	select CPU_V7
-	select SUNXI_GEN_SUN6I
-	select SUPPORT_SPL
-
 config MACH_SUN9I
 	bool "sun9i (Allwinner A80)"
 	select CPU_V7
 	select SUNXI_GEN_SUN6I
 
+config MACH_SUN50I
+	bool "sun50i (Allwinner A64)"
+	select ARM64
+	select SUNXI_GEN_SUN6I
+
 endchoice
 
 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -261,6 +260,7 @@ config MMC
 
 config MMC0_CD_PIN
 	string "Card detect pin for mmc0"
+	default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
 	default ""
 	---help---
 	Set the card detect pin for mmc0, leave empty to not use cd. This
@@ -368,6 +368,7 @@ config I2C0_ENABLE
 	bool "Enable I2C/TWI controller 0"
 	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 	default n if MACH_SUN6I || MACH_SUN8I
+	select CMD_I2C
 	---help---
 	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 	its clock and setting up the bus. This is especially useful on devices
@@ -377,12 +378,14 @@ config I2C0_ENABLE
 config I2C1_ENABLE
 	bool "Enable I2C/TWI controller 1"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 
 config I2C2_ENABLE
 	bool "Enable I2C/TWI controller 2"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 
@@ -390,6 +393,7 @@ if MACH_SUN6I || MACH_SUN7I
 config I2C3_ENABLE
 	bool "Enable I2C/TWI controller 3"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 endif
@@ -399,6 +403,7 @@ config R_I2C_ENABLE
 	bool "Enable the PRCM I2C/TWI controller"
 	# This is used for the pmic on H3
 	default y if SY8106A_POWER
+	select CMD_I2C
 	---help---
 	Set this to y to enable the I2C controller which is part of the PRCM.
 endif
@@ -407,6 +412,7 @@ if MACH_SUN7I
 config I2C4_ENABLE
 	bool "Enable I2C/TWI controller 4"
 	default n
+	select CMD_I2C
 	---help---
 	See I2C0_ENABLE help text.
 endif
@@ -419,7 +425,7 @@ config AXP_GPIO
 
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
-	depends on !MACH_SUN8I_A83T
+	depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64
 	default y
 	---help---
 	Say Y here to add support for using a cfb console on the HDMI, LCD
@@ -535,6 +541,7 @@ config VIDEO_LCD_PANEL_I2C
 	bool "LCD panel needs to be configured via i2c"
 	depends on VIDEO
 	default n
+	select CMD_I2C
 	---help---
 	Say y here if the LCD panel needs to be configured via i2c. This
 	will add a bitbang i2c controller using gpios to talk to the LCD.
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 3cf36147b2..d09cf6dfb5 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,15 +133,6 @@ int dram_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_MACH_SUN50I
-void dram_init_banksize(void)
-{
-	/* We need to reserve the first 16MB of RAM for ATF */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE + (16 * 1024 * 1024);
-	gd->bd->bi_dram[0].size = get_effective_memsize() - (16 * 1024 * 1024);
-}
-#endif
-
 #if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD)
 static void nand_pinmux_setup(void)
 {
@@ -483,10 +474,12 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-	defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
@@ -494,11 +487,13 @@ void sunxi_board_init(void)
 #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 #endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
 	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
@@ -509,11 +504,14 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 #endif
 
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP818_POWER)
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
+	defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
 	power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
+#if !defined CONFIG_AXP809_POWER
 	power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
 	power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
+#endif
 	power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
 	power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
 	power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
@@ -524,6 +522,10 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
 	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
 #endif
+
+#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
+#endif
 #endif
 	printf("DRAM:");
 	ramsize = sunxi_dram_init();
diff --git a/board/ti/am335x/MAINTAINERS b/board/ti/am335x/MAINTAINERS
index 7dc2b83839..c99e06dc10 100644
--- a/board/ti/am335x/MAINTAINERS
+++ b/board/ti/am335x/MAINTAINERS
@@ -6,7 +6,6 @@ F:	include/configs/am335x_evm.h
 F:	configs/am335x_boneblack_defconfig
 F:	configs/am335x_boneblack_vboot_defconfig
 F:	configs/am335x_evm_defconfig
-F:	configs/am335x_gp_evm_defconfig
 F:	configs/am335x_evm_nor_defconfig
 F:	configs/am335x_evm_norboot_defconfig
 F:	configs/am335x_evm_spiboot_defconfig
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 4330be6499..56f4984f47 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -11,11 +11,13 @@
 #include <common.h>
 #include <errno.h>
 #include <spl.h>
+#include <serial.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/clk_synthesizer.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
@@ -37,7 +39,13 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN		7
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define GPIO_DDR_VTT_EN		GPIO_TO_PIN(0, 7)
+#define ICE_GPIO_DDR_VTT_EN	GPIO_TO_PIN(0, 18)
+#define GPIO_PR1_MII_CTRL	GPIO_TO_PIN(3, 4)
+#define GPIO_MUX_MII_CTRL	GPIO_TO_PIN(3, 10)
+#define GPIO_FET_SWITCH_CTRL	GPIO_TO_PIN(0, 7)
+#define GPIO_PHY_RESET		GPIO_TO_PIN(2, 5)
 
 #if defined(CONFIG_SPL_BUILD) || \
 	(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
@@ -52,6 +60,16 @@ static inline int __maybe_unused read_eeprom(void)
 	return ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR);
 }
 
+#ifndef CONFIG_DM_SERIAL
+struct serial_device *default_serial_console(void)
+{
+	if (board_is_icev2())
+		return &eserial4_device;
+	else
+		return &eserial1_device;
+}
+#endif
+
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
@@ -97,6 +115,13 @@ static const struct ddr_data ddr3_evm_data = {
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 };
 
+static const struct ddr_data ddr3_icev2_data = {
+	.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
+	.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
+	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
+	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
+};
+
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
@@ -130,6 +155,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 
+static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
+	.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+
+	.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
+	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
+};
+
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
@@ -162,6 +198,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 				PHY_EN_DYN_PWRDN,
 };
 
+static struct emif_regs ddr3_icev2_emif_reg_data = {
+	.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
+	.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
+	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
+	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
+	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
+	.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
+				PHY_EN_DYN_PWRDN,
+};
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
@@ -339,7 +386,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 
 	if (board_is_evm_sk())
 		return &dpll_ddr_evm_sk;
-	else if (board_is_bone_lt())
+	else if (board_is_bone_lt() || board_is_icev2())
 		return &dpll_ddr_bone_black;
 	else if (board_is_evm_15_or_later())
 		return &dpll_ddr_evm_sk;
@@ -418,6 +465,11 @@ void sdram_init(void)
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 
+	if (board_is_icev2()) {
+		gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
+		gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
+	}
+
 	if (board_is_evm_sk())
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
@@ -429,12 +481,59 @@ void sdram_init(void)
 	else if (board_is_evm_15_or_later())
 		config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
+	else if (board_is_icev2())
+		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
+			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
+			   0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
 
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
+	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
+static void request_and_set_gpio(int gpio, char *name)
+{
+	int ret;
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		return;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	gpio_set_value(gpio, 1);
+
+	return;
+
+err_free_gpio:
+	gpio_free(gpio);
+}
+
+#define REQUEST_AND_SET_GPIO(N)	request_and_set_gpio(N, #N);
+
+/**
+ * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
+ * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
+ * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
+ * give 50MHz output for Eth0 and 1.
+ */
+static struct clk_synth cdce913_data = {
+	.id = 0x81,
+	.capacitor = 0x90,
+	.mux = 0x6d,
+	.pdiv2 = 0x2,
+	.pdiv3 = 0x2,
+};
+#endif
+
 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
@@ -448,6 +547,23 @@ int board_init(void)
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
+#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD))
+	int rv;
+
+	if (board_is_icev2()) {
+		REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_MUX_MII_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
+		REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
+
+		rv = setup_clock_synthesizer(&cdce913_data);
+		if (rv) {
+			printf("Clock synthesizer setup failed %d\n", rv);
+			return rv;
+		}
+	}
+#endif
+
 	return 0;
 }
 
@@ -515,6 +631,12 @@ static struct cpsw_platform_data cpsw_data = {
 };
 #endif
 
+#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
+	defined(CONFIG_SPL_BUILD)) || \
+	((defined(CONFIG_DRIVER_TI_CPSW) || \
+	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
+	 !defined(CONFIG_SPL_BUILD))
+
 /*
  * This function will:
  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
@@ -526,11 +648,6 @@ static struct cpsw_platform_data cpsw_data = {
  * Build in only these cases to avoid warnings about unused variables
  * when we build an SPL that has neither option but full U-Boot will.
  */
-#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
-		&& defined(CONFIG_SPL_BUILD)) || \
-	((defined(CONFIG_DRIVER_TI_CPSW) || \
-	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
-	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
@@ -581,6 +698,12 @@ int board_eth_init(bd_t *bis)
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
+	} else if (board_is_icev2()) {
+		writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
+		cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
+		cpsw_slaves[0].phy_addr = 1;
+		cpsw_slaves[1].phy_addr = 3;
 	} else {
 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
@@ -632,3 +755,23 @@ int board_eth_init(bd_t *bis)
 #endif
 
 #endif /* CONFIG_DM_ETH */
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
+		return 0;
+	else if (board_is_bone() && !strcmp(name, "am335x-bone"))
+		return 0;
+	else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
+		return 0;
+	else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
+		return 0;
+	else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
+		return 0;
+	else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
+		return 0;
+	else
+		return -1;
+}
+#endif
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 062c34512f..9776df7959 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -47,6 +47,11 @@ static inline int board_is_evm_15_or_later(void)
 		strncmp("1.5", board_ti_get_rev(), 3) <= 0);
 }
 
+static inline int board_is_icev2(void)
+{
+	return board_ti_is("A335_ICE") && !strncmp("2", board_ti_get_rev(), 1);
+}
+
 /*
  * We have three pin mux functions that must exist.  We must be able to enable
  * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fdf827fe54..8afa5f9b40 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -135,6 +135,11 @@ static struct module_pin_mux gpio0_7_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux gpio0_18_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDEN)},	/* GPIO0_18 */
+	{-1},
+};
+
 static struct module_pin_mux rgmii1_pin_mux[] = {
 	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
 	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
@@ -172,6 +177,20 @@ static struct module_pin_mux mii1_pin_mux[] = {
 	{-1},
 };
 
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},	/* MII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},			/* MII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},			/* MII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},			/* MII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},	/* MII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},	/* MII1_RXD0 */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE},	/* RMII1_REFCLK */
+	{-1},
+};
+
 #ifdef CONFIG_NAND
 static struct module_pin_mux nand_pin_mux[] = {
 	{OFFSET(gpmc_ad0),	(MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0  */
@@ -237,6 +256,12 @@ static struct module_pin_mux bone_norcape_pin_mux[] = {
 };
 #endif
 
+static struct module_pin_mux uart3_icev2_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)},	/* UART3_RXD */
+	{OFFSET(mii1_rxd2), MODE(1) | PULLUDEN},		/* UART3_TXD */
+	{-1},
+};
+
 #if defined(CONFIG_NOR_BOOT)
 void enable_norboot_pin_mux(void)
 {
@@ -365,6 +390,12 @@ void enable_board_pin_mux(void)
 #else
 		configure_module_pin_mux(mmc1_pin_mux);
 #endif
+	} else if (board_is_icev2()) {
+		configure_module_pin_mux(mmc0_pin_mux);
+		configure_module_pin_mux(gpio0_18_pin_mux);
+		configure_module_pin_mux(uart3_icev2_pin_mux);
+		configure_module_pin_mux(rmii1_pin_mux);
+		configure_module_pin_mux(spi0_pin_mux);
 	} else {
 		puts("Unknown board, cannot configure pinmux.");
 		hang();
diff --git a/board/ti/am43xx/MAINTAINERS b/board/ti/am43xx/MAINTAINERS
index 96ef85b462..3d40b171d2 100644
--- a/board/ti/am43xx/MAINTAINERS
+++ b/board/ti/am43xx/MAINTAINERS
@@ -7,5 +7,3 @@ F:	configs/am43xx_evm_defconfig
 F:	configs/am43xx_evm_qspiboot_defconfig
 F:	configs/am43xx_evm_ethboot_defconfig
 F:	configs/am43xx_evm_usbhost_boot_defconfig
-F:	configs/am437x_gp_evm_defconfig
-F:	configs/am437x_sk_evm_defconfig
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index d208d2fa89..bde5ac7c99 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -341,7 +341,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
 
 	if (board_is_eposevm())
 		return &epos_evm_dpll_ddr[ind];
-	else if (board_is_gpevm() || board_is_sk())
+	else if (board_is_evm() || board_is_sk())
 		return &gp_evm_dpll_ddr;
 	else if (board_is_idk())
 		return &idk_dpll_ddr;
@@ -553,7 +553,7 @@ void sdram_init(void)
 		enable_vtt_regulator();
 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
 			   &ddr3_emif_regs_400Mhz_beta, 0);
-	} else if (board_is_gpevm()) {
+	} else if (board_is_evm()) {
 		enable_vtt_regulator();
 		config_ddr(0, &ioregs_ddr3, NULL, NULL,
 			   &ddr3_emif_regs_400Mhz, 0);
@@ -678,71 +678,71 @@ static struct ti_usb_phy_device usb_phy2_device = {
 	.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 		if (init == USB_INIT_DEVICE) {
 			usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+			dwc3_omap_uboot_init(&usb_otg_ss1_glue);
+			ti_usb_phy_uboot_init(&usb_phy1_device);
+			dwc3_uboot_init(&usb_otg_ss1);
 		}
-
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_uboot_init(&usb_otg_ss1);
 		break;
 	case 1:
 		if (init == USB_INIT_DEVICE) {
 			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
-		} else {
-			usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
 		}
-
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 
 	return 0;
 }
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 	disable_usb_clocks(index);
 
 	return 0;
 }
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 
@@ -846,3 +846,19 @@ int board_eth_init(bd_t *bis)
 	return rv;
 }
 #endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (board_is_gpevm() && !strcmp(name, "am437x-gp-evm"))
+		return 0;
+	else if (board_is_sk() && !strcmp(name, "am437x-sk-evm"))
+		return 0;
+	else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm"))
+		return 0;
+	else if (board_is_idk() && !strcmp(name, "am437x-idk-evm"))
+		return 0;
+	else
+		return -1;
+}
+#endif
diff --git a/board/ti/am43xx/board.h b/board/ti/am43xx/board.h
index 2cf7a7751d..3f93d13727 100644
--- a/board/ti/am43xx/board.h
+++ b/board/ti/am43xx/board.h
@@ -37,14 +37,24 @@ static inline int board_is_idk(void)
 	return board_ti_is("AM43_IDK");
 }
 
+static inline int board_is_hsevm(void)
+{
+	return board_ti_is("AM43XXHS");
+}
+
+static inline int board_is_evm(void)
+{
+	return board_is_gpevm() || board_is_hsevm();
+}
+
 static inline int board_is_evm_14_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0);
+	return board_is_evm() && strncmp("1.4", board_ti_get_rev(), 3) <= 0;
 }
 
 static inline int board_is_evm_12_or_later(void)
 {
-	return (board_is_gpevm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0);
+	return board_is_evm() && strncmp("1.2", board_ti_get_rev(), 3) <= 0;
 }
 
 void enable_uart0_pin_mux(void);
diff --git a/board/ti/am43xx/mux.c b/board/ti/am43xx/mux.c
index e03b1bcfaa..f26b21e869 100644
--- a/board/ti/am43xx/mux.c
+++ b/board/ti/am43xx/mux.c
@@ -126,7 +126,7 @@ void enable_board_pin_mux(void)
 	configure_module_pin_mux(i2c0_pin_mux);
 	configure_module_pin_mux(mdio_pin_mux);
 
-	if (board_is_gpevm()) {
+	if (board_is_evm()) {
 		configure_module_pin_mux(gpio5_7_pin_mux);
 		configure_module_pin_mux(rgmii1_pin_mux);
 #if defined(CONFIG_NAND)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 86b8f6e895..ccf97b2b13 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -63,28 +63,28 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 }
 
 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61851b32,
-	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x08000000,
-	.ref_ctrl		= 0x000040F1,
-	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36ab,
-	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x409f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x5007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36ab,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x409f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
 };
 
 /* Ext phy ctrl regs 1-35 */
@@ -127,28 +127,28 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
 };
 
 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
-	.sdram_config_init	= 0x61851b32,
-	.sdram_config		= 0x61851b32,
-	.sdram_config2		= 0x08000000,
-	.ref_ctrl		= 0x000040F1,
-	.ref_ctrl_final		= 0x00001035,
-	.sdram_tim1		= 0xcccf36b3,
-	.sdram_tim2		= 0x308f7fda,
-	.sdram_tim3		= 0x407f88a8,
-	.read_idle_ctrl		= 0x00050000,
-	.zq_config		= 0x5007190b,
-	.temp_alert_config	= 0x00000000,
-	.emif_ddr_phy_ctlr_1_init = 0x0024400b,
-	.emif_ddr_phy_ctlr_1	= 0x0e24400b,
-	.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
-	.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
-	.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
-	.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
-	.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
-	.emif_rd_wr_lvl_rmp_win	= 0x00000000,
-	.emif_rd_wr_lvl_rmp_ctl	= 0x80000000,
-	.emif_rd_wr_lvl_ctl	= 0x00000000,
-	.emif_rd_wr_exec_thresh	= 0x00000305
+	.sdram_config_init		= 0x61851b32,
+	.sdram_config			= 0x61851b32,
+	.sdram_config2			= 0x08000000,
+	.ref_ctrl			= 0x000040F1,
+	.ref_ctrl_final			= 0x00001035,
+	.sdram_tim1			= 0xcccf36b3,
+	.sdram_tim2			= 0x308f7fda,
+	.sdram_tim3			= 0x407f88a8,
+	.read_idle_ctrl			= 0x00050000,
+	.zq_config			= 0x5007190b,
+	.temp_alert_config		= 0x00000000,
+	.emif_ddr_phy_ctlr_1_init 	= 0x0024400b,
+	.emif_ddr_phy_ctlr_1		= 0x0e24400b,
+	.emif_ddr_ext_phy_ctrl_1 	= 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2 	= 0x00910091,
+	.emif_ddr_ext_phy_ctrl_3 	= 0x00950095,
+	.emif_ddr_ext_phy_ctrl_4 	= 0x009b009b,
+	.emif_ddr_ext_phy_ctrl_5 	= 0x009e009e,
+	.emif_rd_wr_lvl_rmp_win		= 0x00000000,
+	.emif_rd_wr_lvl_rmp_ctl		= 0x80000000,
+	.emif_rd_wr_lvl_ctl		= 0x00000000,
+	.emif_rd_wr_exec_thresh		= 0x00000305
 };
 
 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
@@ -216,41 +216,77 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
 }
 
 struct vcores_data beagle_x15_volts = {
-	.mpu.value		= VDD_MPU_DRA752,
-	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU_NOM,
+	.mpu.value		= VDD_MPU_DRA7,
+	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
 	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
 	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
 	.mpu.pmic		= &tps659038,
-	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
 
-	.eve.value		= VDD_EVE_DRA752,
-	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
+	.eve.value		= VDD_EVE_DRA7,
+	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
 	.eve.pmic		= &tps659038,
 	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
 
-	.gpu.value		= VDD_GPU_DRA752,
-	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU_NOM,
+	.gpu.value		= VDD_GPU_DRA7,
+	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.gpu.addr		= TPS659038_REG_ADDR_SMPS45,
 	.gpu.pmic		= &tps659038,
 	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
 
-	.core.value		= VDD_CORE_DRA752,
-	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE_NOM,
+	.core.value		= VDD_CORE_DRA7,
+	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
 	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.core.addr		= TPS659038_REG_ADDR_SMPS6,
 	.core.pmic		= &tps659038,
 
-	.iva.value		= VDD_IVA_DRA752,
-	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA_NOM,
+	.iva.value		= VDD_IVA_DRA7,
+	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
 	.iva.addr		= TPS659038_REG_ADDR_SMPS45,
 	.iva.pmic		= &tps659038,
 	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
 };
 
+struct vcores_data am572x_idk_volts = {
+	.mpu.value		= VDD_MPU_DRA7,
+	.mpu.efuse.reg		= STD_FUSE_OPP_VMIN_MPU,
+	.mpu.efuse.reg_bits     = DRA752_EFUSE_REGBITS,
+	.mpu.addr		= TPS659038_REG_ADDR_SMPS12,
+	.mpu.pmic		= &tps659038,
+	.mpu.abb_tx_done_mask	= OMAP_ABB_MPU_TXDONE_MASK,
+
+	.eve.value		= VDD_EVE_DRA7,
+	.eve.efuse.reg		= STD_FUSE_OPP_VMIN_DSPEVE,
+	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.eve.addr		= TPS659038_REG_ADDR_SMPS45,
+	.eve.pmic		= &tps659038,
+	.eve.abb_tx_done_mask	= OMAP_ABB_EVE_TXDONE_MASK,
+
+	.gpu.value		= VDD_GPU_DRA7,
+	.gpu.efuse.reg		= STD_FUSE_OPP_VMIN_GPU,
+	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.gpu.addr		= TPS659038_REG_ADDR_SMPS6,
+	.gpu.pmic		= &tps659038,
+	.gpu.abb_tx_done_mask	= OMAP_ABB_GPU_TXDONE_MASK,
+
+	.core.value		= VDD_CORE_DRA7,
+	.core.efuse.reg		= STD_FUSE_OPP_VMIN_CORE,
+	.core.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.core.addr		= TPS659038_REG_ADDR_SMPS7,
+	.core.pmic		= &tps659038,
+
+	.iva.value		= VDD_IVA_DRA7,
+	.iva.efuse.reg		= STD_FUSE_OPP_VMIN_IVA,
+	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
+	.iva.addr		= TPS659038_REG_ADDR_SMPS8,
+	.iva.pmic		= &tps659038,
+	.iva.abb_tx_done_mask	= OMAP_ABB_IVA_TXDONE_MASK,
+};
+
 #ifdef CONFIG_SPL_BUILD
 /* No env to setup for SPL */
 static inline void setup_board_eeprom_env(void) { }
@@ -315,11 +351,18 @@ invalid_eeprom:
 
 #endif	/* CONFIG_SPL_BUILD */
 
+void vcores_init(void)
+{
+	if (board_is_am572x_idk())
+		*omap_vcores = &am572x_idk_volts;
+	else
+		*omap_vcores = &beagle_x15_volts;
+}
+
 void hw_data_init(void)
 {
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra7xx_dplls;
-	*omap_vcores = &beagle_x15_volts;
 	*ctrl = &dra7xx_ctrl;
 }
 
@@ -439,6 +482,19 @@ static struct ti_usb_phy_device usb_phy2_device = {
 	.index = 1,
 };
 
+int usb_gadget_handle_interrupts(int index)
+{
+	u32 status;
+
+	status = dwc3_omap_uboot_interrupt_status(index);
+	if (status)
+		dwc3_uboot_handle_interrupt(index);
+
+	return 0;
+}
+#endif /* CONFIG_USB_DWC3 */
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 int board_usb_init(int index, enum usb_init_type init)
 {
 	enable_usb_clocks(index);
@@ -448,31 +504,23 @@ int board_usb_init(int index, enum usb_init_type init)
 			printf("port %d can't be used as device\n", index);
 			disable_usb_clocks(index);
 			return -EINVAL;
-		} else {
-			usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
-			usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
-			setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
-				     OTG_SS_CLKCTRL_MODULEMODE_HW |
-				     OPTFCLKEN_REFCLK960M);
 		}
-
-		ti_usb_phy_uboot_init(&usb_phy1_device);
-		dwc3_omap_uboot_init(&usb_otg_ss1_glue);
-		dwc3_uboot_init(&usb_otg_ss1);
 		break;
 	case 1:
 		if (init == USB_INIT_DEVICE) {
+#ifdef CONFIG_USB_DWC3
 			usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
 			usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
+			ti_usb_phy_uboot_init(&usb_phy2_device);
+			dwc3_omap_uboot_init(&usb_otg_ss2_glue);
+			dwc3_uboot_init(&usb_otg_ss2);
+#endif
 		} else {
 			printf("port %d can't be used as host\n", index);
 			disable_usb_clocks(index);
 			return -EINVAL;
 		}
 
-		ti_usb_phy_uboot_init(&usb_phy2_device);
-		dwc3_omap_uboot_init(&usb_otg_ss2_glue);
-		dwc3_uboot_init(&usb_otg_ss2);
 		break;
 	default:
 		printf("Invalid Controller Index\n");
@@ -483,31 +531,24 @@ int board_usb_init(int index, enum usb_init_type init)
 
 int board_usb_cleanup(int index, enum usb_init_type init)
 {
+#ifdef CONFIG_USB_DWC3
 	switch (index) {
 	case 0:
 	case 1:
-		ti_usb_phy_uboot_exit(index);
-		dwc3_uboot_exit(index);
-		dwc3_omap_uboot_exit(index);
+		if (init == USB_INIT_DEVICE) {
+			ti_usb_phy_uboot_exit(index);
+			dwc3_uboot_exit(index);
+			dwc3_omap_uboot_exit(index);
+		}
 		break;
 	default:
 		printf("Invalid Controller Index\n");
 	}
+#endif
 	disable_usb_clocks(index);
 	return 0;
 }
-
-int usb_gadget_handle_interrupts(int index)
-{
-	u32 status;
-
-	status = dwc3_omap_uboot_interrupt_status(index);
-	if (status)
-		dwc3_uboot_handle_interrupt(index);
-
-	return 0;
-}
-#endif
+#endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 
@@ -686,3 +727,12 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
diff --git a/board/ti/dra7xx/MAINTAINERS b/board/ti/dra7xx/MAINTAINERS
index 3f638d0a7e..46b6e82b36 100644
--- a/board/ti/dra7xx/MAINTAINERS
+++ b/board/ti/dra7xx/MAINTAINERS
@@ -3,8 +3,5 @@ M:	Lokesh Vutla <lokeshvutla@ti.com>
 S:	Maintained
 F:	board/ti/dra7xx/
 F:	include/configs/dra7xx_evm.h
-F:	configs/dra72_evm_defconfig
-F:	configs/dra74_evm_defconfig
 F:	configs/dra7xx_evm_defconfig
-F:	configs/dra7xx_evm_qspiboot_defconfig
-F:	configs/dra7xx_evm_uart3_defconfig
+F:	configs/dra7xx_hs_evm_defconfig
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9bd71d87ba..3fbbc9b23b 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -718,3 +718,24 @@ int board_early_init_f(void)
 	return 0;
 }
 #endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	if (is_dra72x() && !strcmp(name, "dra72-evm"))
+		return 0;
+	else if (!is_dra72x() && !strcmp(name, "dra7-evm"))
+		return 0;
+	else
+		return -1;
+}
+#endif
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index 9e8ad932d4..1de7df00b4 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -131,7 +131,7 @@ u32 spl_boot_device(void)
 }
 #endif
 
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+#ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	int lpae;
@@ -273,4 +273,4 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
 
 	ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
 }
-#endif
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c412250..8f16845d8e 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+	/* Unlock the reset mux register */
+	clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+	/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+	clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+			RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+	/* lock the reset mux register to prevent any spurious writes. */
+	setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
 int board_early_init_f(void)
 {
 	init_plls();
 
 	k2g_mux_config();
 
+	k2g_reset_mux_config();
+
 	/* deassert FLASH_HOLD */
 	clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
 		     BIT(9));
diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c
index 879f25a538..68fbf49579 100644
--- a/board/toradex/colibri_t20/colibri_t20.c
+++ b/board/toradex/colibri_t20/colibri_t20.c
@@ -103,11 +103,11 @@ void pin_mux_usb(void)
 	pinmux_tristate_disable(PMUX_PINGRP_DTE);
 
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PV4, "LAN_RESET");
-	gpio_direction_output(GPIO_PV4, 0);
+	gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(V, 4), 0);
 	pinmux_tristate_disable(PMUX_PINGRP_GPV);
 	udelay(5);
-	gpio_set_value(GPIO_PV4, 1);
+	gpio_set_value(TEGRA_GPIO(V, 4), 1);
 
 	/* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */
 	pinmux_tristate_disable(PMUX_PINGRP_SPIG);
diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c
index 44b5beb928..e32362a93a 100644
--- a/board/toradex/colibri_t30/colibri_t30.c
+++ b/board/toradex/colibri_t30/colibri_t30.c
@@ -47,8 +47,8 @@ void pinmux_init(void)
 void pin_mux_usb(void)
 {
 	/* Reset ASIX using LAN_RESET */
-	gpio_request(GPIO_PDD0, "LAN_RESET");
-	gpio_direction_output(GPIO_PDD0, 0);
+	gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET");
+	gpio_direction_output(TEGRA_GPIO(DD, 0), 0);
 	udelay(5);
-	gpio_set_value(GPIO_PDD0, 1);
+	gpio_set_value(TEGRA_GPIO(DD, 0), 1);
 }
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 902abf560d..67a0228773 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -12,4 +12,19 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "tplink_wdr4300"
 
+config SYS_TEXT_BASE
+	default 0xa1000000
+
+config SYS_DCACHE_SIZE
+	default 32768
+
+config SYS_DCACHE_LINE_SIZE
+	default 32
+
+config SYS_ICACHE_SIZE
+	default 65536
+
+config SYS_ICACHE_LINE_SIZE
+	default 32
+
 endif
diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c
index bf896fe0ce..d1f3668bcb 100644
--- a/board/xes/common/actl_nand.c
+++ b/board/xes/common/actl_nand.c
@@ -16,7 +16,7 @@
  */
 static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 461d7dce2c..02ac65c1d3 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -9,4 +9,28 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "microblaze-generic"
 
+config XILINX_MICROBLAZE0_USE_MSR_INSTR
+	int "USE_MSR_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_PCMP_INSTR
+	int "USE_PCMP_INSTR range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_BARREL
+	int "USE_BARREL range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_DIV
+	int "USE_DIV range (0:1)"
+	default 0
+
+config XILINX_MICROBLAZE0_USE_HW_MUL
+	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
+	default 0
+
+config XILINX_MICROBLAZE0_HW_VER
+	string "Core version number"
+	default 7.10.d
+
 endif
diff --git a/board/xilinx/microblaze-generic/config.mk b/board/xilinx/microblaze-generic/config.mk
index 95ef9c0f06..1dee2d6e3a 100644
--- a/board/xilinx/microblaze-generic/config.mk
+++ b/board/xilinx/microblaze-generic/config.mk
@@ -1,16 +1,20 @@
 #
-# (C) Copyright 2007 Michal Simek
+# (C) Copyright 2007 - 2016 Michal Simek
 #
-# Michal  SIMEK <monstr@monstr.eu>
+# Michal SIMEK <monstr@monstr.eu>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
-# CAUTION: This file is a faked configuration !!!
-#          There is no real target for the microblaze-generic
-#          configuration. You have to replace this file with
-#          the generated file from your Xilinx design flow.
-#
 
-PLATFORM_CPPFLAGS += -mno-xl-soft-mul
-PLATFORM_CPPFLAGS += -mno-xl-soft-div
-PLATFORM_CPPFLAGS += -mxl-barrel-shift
+CPU_VER := $(shell echo $(CONFIG_XILINX_MICROBLAZE0_HW_VER))
+
+# USE_HW_MUL can be 0, 1, or 2, defining a hierarchy of HW Mul support.
+CPUFLAGS-$(subst 1,,$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL)) += -mxl-multiply-high
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL) += -mno-xl-soft-mul
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_DIV) += -mno-xl-soft-div
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_BARREL) += -mxl-barrel-shift
+CPUFLAGS-$(CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR) += -mxl-pattern-compare
+
+CPUFLAGS-1 += $(call cc-option,-mcpu=v$(CPU_VER))
+
+PLATFORM_CPPFLAGS += $(CPUFLAGS-1) $(CPUFLAGS-2)
diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h
index dc5645bd14..ee7d0875d2 100644
--- a/board/xilinx/microblaze-generic/xparameters.h
+++ b/board/xilinx/microblaze-generic/xparameters.h
@@ -14,7 +14,6 @@
 #define XILINX_BOARD_NAME	microblaze-generic
 
 /* Microblaze is microblaze_0 */
-#define XILINX_USE_MSR_INSTR	1
 #define XILINX_FSL_NUMBER	3
 
 /* GPIO is LEDs_4Bit*/
diff --git a/board/xilinx/zynq/Makefile b/board/xilinx/zynq/Makefile
index eab93038ce..7de0212bc9 100644
--- a/board/xilinx/zynq/Makefile
+++ b/board/xilinx/zynq/Makefile
@@ -7,17 +7,7 @@
 
 obj-y	:= board.o
 
-# Copied from Xilinx SDK 2014.4
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZED)		:= zed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_MICROZED)	:= MicroZed_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC702)		:= ZC702_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZC706)		:= ZC706_hw_platform
-hw-platform-$(CONFIG_TARGET_ZYNQ_ZYBO)		:= zybo_hw_platform
-# If you want to use customized ps7_init_gpl.c/h,
-# enable CONFIG_ZYNQ_CUSTOM_INIT and put them into custom_hw_platform/.
-# This line must be placed at the bottom of the list because
-# it takes precedence over the default ones.
-hw-platform-$(CONFIG_ZYNQ_CUSTOM_INIT)		:= custom_hw_platform
+hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE))
 
 init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/ps7_init_gpl.c),\
 	$(hw-platform-y)/ps7_init_gpl.o)
diff --git a/board/xilinx/zynq/custom_hw_platform/.gitignore b/board/xilinx/zynq/custom_hw_platform/.gitignore
deleted file mode 100644
index c455361df6..0000000000
--- a/board/xilinx/zynq/custom_hw_platform/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-ps7_init_gpl.[ch]
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
index eb290023a1..eb290023a1 100644
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
index bdea5a0443..bdea5a0443 100644
--- a/board/xilinx/zynq/MicroZed_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
index abfd91187d..abfd91187d 100644
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
index 16fa8104a4..16fa8104a4 100644
--- a/board/xilinx/zynq/ZC702_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
index 77fd9499df..77fd9499df 100644
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
index 8527eef447..8527eef447 100644
--- a/board/xilinx/zynq/ZC706_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
index f4f45becd6..f4f45becd6 100644
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
index 9b41e28697..9b41e28697 100644
--- a/board/xilinx/zynq/zed_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
index 83daf7bf15..83daf7bf15 100644
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.c
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c
diff --git a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
index 22d9fd9250..22d9fd9250 100644
--- a/board/xilinx/zynq/zybo_hw_platform/ps7_init_gpl.h
+++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h
diff --git a/board/xilinx/zynqmp/Makefile b/board/xilinx/zynqmp/Makefile
index 2ab3f190ac..90f00c650a 100644
--- a/board/xilinx/zynqmp/Makefile
+++ b/board/xilinx/zynqmp/Makefile
@@ -1,8 +1,29 @@
 #
-# (C) Copyright 2014 - 2015 Xilinx, Inc.
+# (C) Copyright 2014 - 2016 Xilinx, Inc.
 # Michal Simek <michal.simek@xilinx.com>
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
 obj-y	:= zynqmp.o
+
+hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
+
+init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
+	$(hw-platform-y)/psu_init_gpl.o)
+
+ifeq ($(init-objs),)
+ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
+init-objs := psu_init_gpl.o
+$(if $(CONFIG_SPL_BUILD),\
+$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
+endif
+endif
+
+obj-$(CONFIG_SPL_BUILD) += $(init-objs)
+
+# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
+
+# To include xil_io.h
+CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)
diff --git a/board/xilinx/zynqmp/xil_io.h b/board/xilinx/zynqmp/xil_io.h
new file mode 100644
index 0000000000..57ca4adf11
--- /dev/null
+++ b/board/xilinx/zynqmp/xil_io.h
@@ -0,0 +1,35 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef XIL_IO_H /* prevent circular inclusions */
+#define XIL_IO_H
+
+/* FIXME remove this when vivado is fixed */
+#include <asm/io.h>
+
+#define xil_printf(...)
+
+void Xil_ICacheEnable(void)
+{}
+
+void Xil_DCacheEnable(void)
+{}
+
+void Xil_ICacheDisable(void)
+{}
+
+void Xil_DCacheDisable(void)
+{}
+
+void Xil_Out32(unsigned long addr, unsigned long val)
+{
+	writel(val, addr);
+}
+
+int Xil_In32(unsigned long addr)
+{
+	return readl(addr);
+}
+
+#endif /* XIL_IO_H */
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 132d724fbd..f15dc5d715 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -9,12 +9,14 @@
 #include <sata.h>
 #include <ahci.h>
 #include <scsi.h>
+#include <malloc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <usb.h>
 #include <dwc3-uboot.h>
+#include <i2c.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +52,22 @@ int board_early_init_r(void)
 	return 0;
 }
 
+int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
+{
+#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
+    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET) && \
+    defined(CONFIG_ZYNQ_EEPROM_BUS)
+	i2c_set_bus_num(CONFIG_ZYNQ_EEPROM_BUS);
+
+	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
+			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
+			ethaddr, 6))
+		printf("I2C EEPROM MAC address read failed\n");
+#endif
+
+	return 0;
+}
+
 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 /*
  * fdt_get_reg - Fill buffer by information from DT
@@ -197,6 +215,13 @@ int board_late_init(void)
 {
 	u32 reg = 0;
 	u8 bootmode;
+	const char *mode;
+	char *new_targets;
+
+	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
+		debug("Saved variables - Skipping\n");
+		return 0;
+	}
 
 	reg = readl(&crlapb_base->boot_mode);
 	bootmode = reg & BOOT_MODES_MASK;
@@ -205,37 +230,49 @@ int board_late_init(void)
 	switch (bootmode) {
 	case JTAG_MODE:
 		puts("JTAG_MODE\n");
-		setenv("modeboot", "jtagboot");
+		mode = "pxe dhcp";
 		break;
 	case QSPI_MODE_24BIT:
 	case QSPI_MODE_32BIT:
-		setenv("modeboot", "qspiboot");
+		mode = "qspi0";
 		puts("QSPI_MODE\n");
 		break;
 	case EMMC_MODE:
 		puts("EMMC_MODE\n");
-		setenv("modeboot", "sdboot");
+		mode = "mmc0";
 		break;
 	case SD_MODE:
 		puts("SD_MODE\n");
-		setenv("modeboot", "sdboot");
+		mode = "mmc0";
 		break;
 	case SD_MODE1:
 		puts("SD_MODE1\n");
 #if defined(CONFIG_ZYNQ_SDHCI0) && defined(CONFIG_ZYNQ_SDHCI1)
-		setenv("sdbootdev", "1");
+		mode = "mmc1";
+#else
+		mode = "mmc0";
 #endif
-		setenv("modeboot", "sdboot");
 		break;
 	case NAND_MODE:
 		puts("NAND_MODE\n");
-		setenv("modeboot", "nandboot");
+		mode = "nand0";
 		break;
 	default:
+		mode = "";
 		printf("Invalid Boot Mode:0x%x\n", bootmode);
 		break;
 	}
 
+	/*
+	 * One terminating char + one byte for space between mode
+	 * and default boot_targets
+	 */
+	new_targets = calloc(1, strlen(mode) +
+				strlen(getenv("boot_targets")) + 2);
+
+	sprintf(new_targets, "%s %s", mode, getenv("boot_targets"));
+	setenv("boot_targets", new_targets);
+
 	return 0;
 }
 
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9336752128..d51645c634 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -593,6 +593,13 @@ config CMD_SOUND
 	     sound init   - set up sound system
 	     sound play   - play a sound
 
+config CMD_QFW
+	bool "qfw"
+	select QFW
+	help
+	  This provides access to the QEMU firmware interface.  The main
+	  feature is to allow easy loading of files passed to qemu-system
+	  via -kernel / -initrd
 endmenu
 
 config CMD_BOOTSTAGE
diff --git a/cmd/Makefile b/cmd/Makefile
index e3e0c74ffc..9ce7861f82 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -105,6 +105,7 @@ endif
 obj-y += pcmcia.o
 obj-$(CONFIG_CMD_PORTIO) += portio.o
 obj-$(CONFIG_CMD_PXE) += pxe.o
+obj-$(CONFIG_CMD_QFW) += qfw.o
 obj-$(CONFIG_CMD_READ) += read.o
 obj-$(CONFIG_CMD_REGINFO) += reginfo.o
 obj-$(CONFIG_CMD_REISER) += reiser.o
diff --git a/cmd/bootefi.c b/cmd/bootefi.c
index 7f552fc0d4..216906527f 100644
--- a/cmd/bootefi.c
+++ b/cmd/bootefi.c
@@ -197,11 +197,22 @@ static unsigned long do_bootefi_exec(void *efi, void *fdt)
 #ifdef CONFIG_LCD
 	efi_gop_register();
 #endif
+#ifdef CONFIG_NET
+	void *nethandle = loaded_image_info.device_handle;
+	efi_net_register(&nethandle);
 
-	/* Call our payload! */
-#ifdef DEBUG_EFI
-	printf("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
+	if (!memcmp(bootefi_device_path[0].str, "N\0e\0t", 6))
+		loaded_image_info.device_handle = nethandle;
 #endif
+
+	/* Call our payload! */
+	debug("%s:%d Jumping to 0x%lx\n", __func__, __LINE__, (long)entry);
+
+	if (setjmp(&loaded_image_info.exit_jmp)) {
+		efi_status_t status = loaded_image_info.exit_status;
+		return status == EFI_SUCCESS ? 0 : -EINVAL;
+	}
+
 	return entry(&loaded_image_info, &systab);
 }
 
diff --git a/cmd/bootm.c b/cmd/bootm.c
index 1bca6fa920..f5e91f40a9 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -372,8 +372,8 @@ next_bank:	;
 #endif
 
 #if defined(CONFIG_CMD_IMLS_NAND)
-static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
-		size_t len)
+static int nand_imls_legacyimage(struct mtd_info *mtd, int nand_dev,
+				 loff_t off, size_t len)
 {
 	void *imgdata;
 	int ret;
@@ -386,8 +386,7 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
 		return -ENOMEM;
 	}
 
-	ret = nand_read_skip_bad(nand, off, &len,
-			imgdata);
+	ret = nand_read_skip_bad(mtd, off, &len, imgdata);
 	if (ret < 0 && ret != -EUCLEAN) {
 		free(imgdata);
 		return ret;
@@ -413,8 +412,8 @@ static int nand_imls_legacyimage(nand_info_t *nand, int nand_dev, loff_t off,
 	return 0;
 }
 
-static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
-		size_t len)
+static int nand_imls_fitimage(struct mtd_info *mtd, int nand_dev, loff_t off,
+			      size_t len)
 {
 	void *imgdata;
 	int ret;
@@ -427,8 +426,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
 		return -ENOMEM;
 	}
 
-	ret = nand_read_skip_bad(nand, off, &len,
-			imgdata);
+	ret = nand_read_skip_bad(mtd, off, &len, imgdata);
 	if (ret < 0 && ret != -EUCLEAN) {
 		free(imgdata);
 		return ret;
@@ -449,7 +447,7 @@ static int nand_imls_fitimage(nand_info_t *nand, int nand_dev, loff_t off,
 
 static int do_imls_nand(void)
 {
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 	int nand_dev = nand_curr_device;
 	size_t len;
 	loff_t off;
@@ -463,20 +461,20 @@ static int do_imls_nand(void)
 	printf("\n");
 
 	for (nand_dev = 0; nand_dev < CONFIG_SYS_MAX_NAND_DEVICE; nand_dev++) {
-		nand = &nand_info[nand_dev];
-		if (!nand->name || !nand->size)
+		mtd = nand_info[nand_dev];
+		if (!mtd->name || !mtd->size)
 			continue;
 
-		for (off = 0; off < nand->size; off += nand->erasesize) {
+		for (off = 0; off < mtd->size; off += mtd->erasesize) {
 			const image_header_t *header;
 			int ret;
 
-			if (nand_block_isbad(nand, off))
+			if (nand_block_isbad(mtd, off))
 				continue;
 
 			len = sizeof(buffer);
 
-			ret = nand_read(nand, off, &len, (u8 *)buffer);
+			ret = nand_read(mtd, off, &len, (u8 *)buffer);
 			if (ret < 0 && ret != -EUCLEAN) {
 				printf("NAND read error %d at offset %08llX\n",
 						ret, off);
@@ -489,13 +487,13 @@ static int do_imls_nand(void)
 				header = (const image_header_t *)buffer;
 
 				len = image_get_image_size(header);
-				nand_imls_legacyimage(nand, nand_dev, off, len);
+				nand_imls_legacyimage(mtd, nand_dev, off, len);
 				break;
 #endif
 #if defined(CONFIG_FIT)
 			case IMAGE_FORMAT_FIT:
 				len = fit_get_size(buffer);
-				nand_imls_fitimage(nand, nand_dev, off, len);
+				nand_imls_fitimage(mtd, nand_dev, off, len);
 				break;
 #endif
 			}
@@ -655,6 +653,7 @@ static int booti_setup(bootm_headers_t *images)
 {
 	struct Image_header *ih;
 	uint64_t dst;
+	uint64_t image_size;
 
 	ih = (struct Image_header *)map_sysmem(images->ep, 0);
 
@@ -665,14 +664,16 @@ static int booti_setup(bootm_headers_t *images)
 	
 	if (ih->image_size == 0) {
 		puts("Image lacks image_size field, assuming 16MiB\n");
-		ih->image_size = (16 << 20);
+		image_size = 16 << 20;
+	} else {
+		image_size = le64_to_cpu(ih->image_size);
 	}
 
 	/*
 	 * If we are not at the correct run-time location, set the new
 	 * correct location and then move the image there.
 	 */
-	dst = gd->bd->bi_dram[0].start + le32_to_cpu(ih->text_offset);
+	dst = gd->bd->bi_dram[0].start + le64_to_cpu(ih->text_offset);
 
 	unmap_sysmem(ih);
 
@@ -683,7 +684,7 @@ static int booti_setup(bootm_headers_t *images)
 
 		src = (void *)images->ep;
 		images->ep = dst;
-		memmove((void *)dst, src, le32_to_cpu(ih->image_size));
+		memmove((void *)dst, src, image_size);
 	}
 
 	return 0;
diff --git a/cmd/disk.c b/cmd/disk.c
index fcc4123127..92de3af8a5 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -13,7 +13,8 @@
 int common_diskboot(cmd_tbl_t *cmdtp, const char *intf, int argc,
 		    char *const argv[])
 {
-	int dev, part;
+	__maybe_unused int dev;
+	int part;
 	ulong addr = CONFIG_SYS_LOAD_ADDR;
 	ulong cnt;
 	disk_partition_t info;
diff --git a/cmd/itest.c b/cmd/itest.c
index fb4d797e43..60626c7fe9 100644
--- a/cmd/itest.c
+++ b/cmd/itest.c
@@ -65,13 +65,13 @@ static long evalexp(char *s, int w)
 		}
 		switch (w) {
 		case 1:
-			l = (long)(*(unsigned char *)buf);
+			l = (long)(*(u8 *)buf);
 			break;
 		case 2:
-			l = (long)(*(unsigned short *)buf);
+			l = (long)(*(u16 *)buf);
 			break;
 		case 4:
-			l = (long)(*(unsigned long *)buf);
+			l = (long)(*(u32 *)buf);
 			break;
 		}
 		unmap_physmem(buf, w);
diff --git a/cmd/jffs2.c b/cmd/jffs2.c
index 0b2eefa195..f00d53a6c8 100644
--- a/cmd/jffs2.c
+++ b/cmd/jffs2.c
@@ -167,7 +167,7 @@ static int mtd_device_validate(u8 type, u8 num, u32 *size)
 	} else if (type == MTD_DEV_TYPE_NAND) {
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
 		if (num < CONFIG_SYS_MAX_NAND_DEVICE) {
-			*size = nand_info[num].size;
+			*size = nand_info[num]->size;
 			return 0;
 		}
 
@@ -242,11 +242,11 @@ static int mtd_id_parse(const char *id, const char **ret_id, u8 *dev_type, u8 *d
 static inline u32 get_part_sector_size_nand(struct mtdids *id)
 {
 #if defined(CONFIG_JFFS2_NAND) && defined(CONFIG_CMD_NAND)
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 
-	nand = &nand_info[id->num];
+	mtd = nand_info[id->num];
 
-	return nand->erasesize;
+	return mtd->erasesize;
 #else
 	BUG();
 	return 0;
diff --git a/cmd/mmc.c b/cmd/mmc.c
index eb4a547a97..b2761e934b 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -11,66 +11,6 @@
 #include <mmc.h>
 
 static int curr_device = -1;
-#ifndef CONFIG_GENERIC_MMC
-int do_mmc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int dev;
-
-	if (argc < 2)
-		return CMD_RET_USAGE;
-
-	if (strcmp(argv[1], "init") == 0) {
-		if (argc == 2) {
-			if (curr_device < 0)
-				dev = 1;
-			else
-				dev = curr_device;
-		} else if (argc == 3) {
-			dev = (int)simple_strtoul(argv[2], NULL, 10);
-		} else {
-			return CMD_RET_USAGE;
-		}
-
-		if (mmc_legacy_init(dev) != 0) {
-			puts("No MMC card found\n");
-			return 1;
-		}
-
-		curr_device = dev;
-		printf("mmc%d is available\n", curr_device);
-	} else if (strcmp(argv[1], "device") == 0) {
-		if (argc == 2) {
-			if (curr_device < 0) {
-				puts("No MMC device available\n");
-				return 1;
-			}
-		} else if (argc == 3) {
-			dev = (int)simple_strtoul(argv[2], NULL, 10);
-
-#ifdef CONFIG_SYS_MMC_SET_DEV
-			if (mmc_set_dev(dev) != 0)
-				return 1;
-#endif
-			curr_device = dev;
-		} else {
-			return CMD_RET_USAGE;
-		}
-
-		printf("mmc%d is current device\n", curr_device);
-	} else {
-		return CMD_RET_USAGE;
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	mmc, 3, 1, do_mmc,
-	"MMC sub-system",
-	"init [dev] - init MMC sub system\n"
-	"mmc device [dev] - show or set current device"
-);
-#else /* !CONFIG_GENERIC_MMC */
 
 static void print_mmcinfo(struct mmc *mmc)
 {
@@ -881,5 +821,3 @@ U_BOOT_CMD(
 	"display MMC info",
 	"- display info of the current MMC device"
 );
-
-#endif /* !CONFIG_GENERIC_MMC */
diff --git a/cmd/nand.c b/cmd/nand.c
index a6b67e29f1..583a18f341 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -38,7 +38,8 @@ int find_dev_and_part(const char *id, struct mtd_device **dev,
 		      u8 *part_num, struct part_info **part);
 #endif
 
-static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
+static int nand_dump(struct mtd_info *mtd, ulong off, int only_oob,
+		     int repeat)
 {
 	int i;
 	u_char *datbuf, *oobbuf, *p;
@@ -46,32 +47,32 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	int ret = 0;
 
 	if (repeat)
-		off = last + nand->writesize;
+		off = last + mtd->writesize;
 
 	last = off;
 
-	datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
+	datbuf = memalign(ARCH_DMA_MINALIGN, mtd->writesize);
 	if (!datbuf) {
 		puts("No memory for page buffer\n");
 		return 1;
 	}
 
-	oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize);
+	oobbuf = memalign(ARCH_DMA_MINALIGN, mtd->oobsize);
 	if (!oobbuf) {
 		puts("No memory for page buffer\n");
 		ret = 1;
 		goto free_dat;
 	}
-	off &= ~(nand->writesize - 1);
+	off &= ~(mtd->writesize - 1);
 	loff_t addr = (loff_t) off;
 	struct mtd_oob_ops ops;
 	memset(&ops, 0, sizeof(ops));
 	ops.datbuf = datbuf;
 	ops.oobbuf = oobbuf;
-	ops.len = nand->writesize;
-	ops.ooblen = nand->oobsize;
+	ops.len = mtd->writesize;
+	ops.ooblen = mtd->oobsize;
 	ops.mode = MTD_OPS_RAW;
-	i = mtd_read_oob(nand, addr, &ops);
+	i = mtd_read_oob(mtd, addr, &ops);
 	if (i < 0) {
 		printf("Error (%d) reading page %08lx\n", i, off);
 		ret = 1;
@@ -80,7 +81,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	printf("Page %08lx dump:\n", off);
 
 	if (!only_oob) {
-		i = nand->writesize >> 4;
+		i = mtd->writesize >> 4;
 		p = datbuf;
 
 		while (i--) {
@@ -94,7 +95,7 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
 	}
 
 	puts("OOB:\n");
-	i = nand->oobsize >> 3;
+	i = mtd->oobsize >> 3;
 	p = oobbuf;
 	while (i--) {
 		printf("\t%02x %02x %02x %02x %02x %02x %02x %02x\n",
@@ -115,7 +116,7 @@ free_dat:
 static int set_dev(int dev)
 {
 	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[dev].name) {
+	    !nand_info[dev]->name) {
 		puts("No such device\n");
 		return -1;
 	}
@@ -123,12 +124,12 @@ static int set_dev(int dev)
 	if (nand_curr_device == dev)
 		return 0;
 
-	printf("Device %d: %s", dev, nand_info[dev].name);
+	printf("Device %d: %s", dev, nand_info[dev]->name);
 	puts("... is now current device\n");
 	nand_curr_device = dev;
 
 #ifdef CONFIG_SYS_NAND_SELECT_DEVICE
-	board_nand_select_device(nand_info[dev].priv, dev);
+	board_nand_select_device(nand_info[dev]->priv, dev);
 #endif
 
 	return 0;
@@ -152,32 +153,32 @@ static void print_status(ulong start, ulong end, ulong erasesize, int status)
 		((status & NAND_LOCK_STATUS_UNLOCK) ?  "UNLOCK " : ""));
 }
 
-static void do_nand_status(nand_info_t *nand)
+static void do_nand_status(struct mtd_info *mtd)
 {
 	ulong block_start = 0;
 	ulong off;
 	int last_status = -1;
 
-	struct nand_chip *nand_chip = nand->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 	/* check the WP bit */
-	nand_chip->cmdfunc(nand, NAND_CMD_STATUS, -1, -1);
+	nand_chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 	printf("device is %swrite protected\n",
-		(nand_chip->read_byte(nand) & 0x80 ?
-		"NOT " : ""));
+		(nand_chip->read_byte(mtd) & 0x80 ?
+		 "NOT " : ""));
 
-	for (off = 0; off < nand->size; off += nand->erasesize) {
-		int s = nand_get_lock_status(nand, off);
+	for (off = 0; off < mtd->size; off += mtd->erasesize) {
+		int s = nand_get_lock_status(mtd, off);
 
 		/* print message only if status has changed */
 		if (s != last_status && off != 0) {
-			print_status(block_start, off, nand->erasesize,
+			print_status(block_start, off, mtd->erasesize,
 					last_status);
 			block_start = off;
 		}
 		last_status = s;
 	}
 	/* Print the last block info */
-	print_status(block_start, off, nand->erasesize, last_status);
+	print_status(block_start, off, mtd->erasesize, last_status);
 }
 #endif
 
@@ -188,10 +189,10 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 {
 	int ret;
 	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
-	nand_info_t *nand = &nand_info[0];
+	struct mtd_info *mtd = nand_info[0];
 	char *cmd = argv[1];
 
-	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !nand->name) {
+	if (CONFIG_SYS_MAX_NAND_DEVICE == 0 || !mtd->name) {
 		puts("no devices available\n");
 		return 1;
 	}
@@ -199,7 +200,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 	set_dev(0);
 
 	if (!strcmp(cmd, "get")) {
-		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
 		if (ret)
 			return 1;
 
@@ -215,7 +216,7 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 
 		/* We don't care about size, or maxsize. */
 		if (mtd_arg_off(argv[2], &idx, &addr, &maxsize, &maxsize,
-				MTD_DEV_TYPE_NAND, nand_info[idx].size)) {
+				MTD_DEV_TYPE_NAND, nand_info[idx]->size)) {
 			puts("Offset or partition name expected\n");
 			return 1;
 		}
@@ -229,15 +230,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 			return 1;
 		}
 
-		if (nand->oobavail < ENV_OFFSET_SIZE) {
+		if (mtd->oobavail < ENV_OFFSET_SIZE) {
 			printf("Insufficient available OOB bytes:\n"
 			       "%d OOB bytes available but %d required for "
 			       "env.oob support\n",
-			       nand->oobavail, ENV_OFFSET_SIZE);
+			       mtd->oobavail, ENV_OFFSET_SIZE);
 			return 1;
 		}
 
-		if ((addr & (nand->erasesize - 1)) != 0) {
+		if ((addr & (mtd->erasesize - 1)) != 0) {
 			printf("Environment offset must be block-aligned\n");
 			return 1;
 		}
@@ -249,15 +250,15 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[])
 		ops.oobbuf = (void *) oob_buf;
 
 		oob_buf[0] = ENV_OOB_MARKER;
-		oob_buf[1] = addr / nand->erasesize;
+		oob_buf[1] = addr / mtd->erasesize;
 
-		ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+		ret = mtd->write_oob(mtd, ENV_OFFSET_SIZE, &ops);
 		if (ret) {
 			printf("Error writing OOB block 0\n");
 			return ret;
 		}
 
-		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		ret = get_nand_env_oob(mtd, &nand_env_oob_offset);
 		if (ret) {
 			printf("Error reading env offset in OOB\n");
 			return ret;
@@ -283,29 +284,29 @@ usage:
 
 static void nand_print_and_set_info(int idx)
 {
-	nand_info_t *nand = &nand_info[idx];
-	struct nand_chip *chip = nand->priv;
+	struct mtd_info *mtd = nand_info[idx];
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	printf("Device %d: ", idx);
 	if (chip->numchips > 1)
 		printf("%dx ", chip->numchips);
 	printf("%s, sector size %u KiB\n",
-	       nand->name, nand->erasesize >> 10);
-	printf("  Page size   %8d b\n", nand->writesize);
-	printf("  OOB size    %8d b\n", nand->oobsize);
-	printf("  Erase size  %8d b\n", nand->erasesize);
+	       mtd->name, mtd->erasesize >> 10);
+	printf("  Page size   %8d b\n", mtd->writesize);
+	printf("  OOB size    %8d b\n", mtd->oobsize);
+	printf("  Erase size  %8d b\n", mtd->erasesize);
 	printf("  subpagesize %8d b\n", chip->subpagesize);
 	printf("  options     0x%8x\n", chip->options);
 	printf("  bbt options 0x%8x\n", chip->bbt_options);
 
 	/* Set geometry info */
-	setenv_hex("nand_writesize", nand->writesize);
-	setenv_hex("nand_oobsize", nand->oobsize);
-	setenv_hex("nand_erasesize", nand->erasesize);
+	setenv_hex("nand_writesize", mtd->writesize);
+	setenv_hex("nand_oobsize", mtd->oobsize);
+	setenv_hex("nand_erasesize", mtd->erasesize);
 }
 
-static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
-			int read)
+static int raw_access(struct mtd_info *mtd, ulong addr, loff_t off,
+		      ulong count, int read)
 {
 	int ret = 0;
 
@@ -313,18 +314,18 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
 		/* Raw access */
 		mtd_oob_ops_t ops = {
 			.datbuf = (u8 *)addr,
-			.oobbuf = ((u8 *)addr) + nand->writesize,
-			.len = nand->writesize,
-			.ooblen = nand->oobsize,
+			.oobbuf = ((u8 *)addr) + mtd->writesize,
+			.len = mtd->writesize,
+			.ooblen = mtd->oobsize,
 			.mode = MTD_OPS_RAW
 		};
 
 		if (read) {
-			ret = mtd_read_oob(nand, off, &ops);
+			ret = mtd_read_oob(mtd, off, &ops);
 		} else {
-			ret = mtd_write_oob(nand, off, &ops);
+			ret = mtd_write_oob(mtd, off, &ops);
 			if (!ret)
-				ret = nand_verify_page_oob(nand, &ops, off);
+				ret = nand_verify_page_oob(mtd, &ops, off);
 		}
 
 		if (ret) {
@@ -333,8 +334,8 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count,
 			break;
 		}
 
-		addr += nand->writesize + nand->oobsize;
-		off += nand->writesize;
+		addr += mtd->writesize + mtd->oobsize;
+		off += mtd->writesize;
 	}
 
 	return ret;
@@ -348,18 +349,18 @@ static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
 	/* We grab the nand info object here fresh because this is usually
 	 * called after arg_off_size() which can change the value of dev.
 	 */
-	nand_info_t *nand = &nand_info[dev];
+	struct mtd_info *mtd = nand_info[dev];
 	loff_t maxoffset = offset + *size;
 	int badblocks = 0;
 
 	/* count badblocks in NAND from offset to offset + size */
-	for (; offset < maxoffset; offset += nand->erasesize) {
-		if (nand_block_isbad(nand, offset))
+	for (; offset < maxoffset; offset += mtd->erasesize) {
+		if (nand_block_isbad(mtd, offset))
 			badblocks++;
 	}
 	/* adjust size if any bad blocks found */
 	if (badblocks) {
-		*size -= badblocks * nand->erasesize;
+		*size -= badblocks * mtd->erasesize;
 		printf("size adjusted to 0x%llx (%d bad blocks)\n",
 		       (unsigned long long)*size, badblocks);
 	}
@@ -371,7 +372,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	ulong addr;
 	loff_t off, size, maxsize;
 	char *cmd, *s;
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 #ifdef CONFIG_SYS_NAND_QUIET
 	int quiet = CONFIG_SYS_NAND_QUIET;
 #else
@@ -398,7 +399,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		putc('\n');
 		for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
-			if (nand_info[i].name)
+			if (nand_info[i]->name)
 				nand_print_and_set_info(i);
 		}
 		return 0;
@@ -433,16 +434,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	 * for another device is to be used.
 	 */
 	if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[dev].name) {
+	    !nand_info[dev]->name) {
 		puts("\nno devices available\n");
 		return 1;
 	}
-	nand = &nand_info[dev];
+	mtd = nand_info[dev];
 
 	if (strcmp(cmd, "bad") == 0) {
 		printf("\nDevice %d bad blocks:\n", dev);
-		for (off = 0; off < nand->size; off += nand->erasesize)
-			if (nand_block_isbad(nand, off))
+		for (off = 0; off < mtd->size; off += mtd->erasesize)
+			if (nand_block_isbad(mtd, off))
 				printf("  %08llx\n", (unsigned long long)off);
 		return 0;
 	}
@@ -496,13 +497,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		/* skip first two or three arguments, look for offset and size */
 		if (mtd_arg_off_size(argc - o, argv + o, &dev, &off, &size,
 				     &maxsize, MTD_DEV_TYPE_NAND,
-				     nand_info[dev].size) != 0)
+				     nand_info[dev]->size) != 0)
 			return 1;
 
 		if (set_dev(dev))
 			return 1;
 
-		nand = &nand_info[dev];
+		mtd = nand_info[dev];
 
 		memset(&opts, 0, sizeof(opts));
 		opts.offset = off;
@@ -524,7 +525,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				}
 			}
 		}
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		printf("%s\n", ret ? "ERROR" : "OK");
 
 		return ret == 0 ? 0 : 1;
@@ -535,7 +536,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			goto usage;
 
 		off = (int)simple_strtoul(argv[2], NULL, 16);
-		ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat);
+		ret = nand_dump(mtd, off, !strcmp(&cmd[4], ".oob"), repeat);
 
 		return ret == 0 ? 1 : 0;
 	}
@@ -561,30 +562,30 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 			if (mtd_arg_off(argv[3], &dev, &off, &size, &maxsize,
 					MTD_DEV_TYPE_NAND,
-					nand_info[dev].size))
+					nand_info[dev]->size))
 				return 1;
 
 			if (set_dev(dev))
 				return 1;
 
-			nand = &nand_info[dev];
+			mtd = nand_info[dev];
 
 			if (argc > 4 && !str2long(argv[4], &pagecount)) {
 				printf("'%s' is not a number\n", argv[4]);
 				return 1;
 			}
 
-			if (pagecount * nand->writesize > size) {
+			if (pagecount * mtd->writesize > size) {
 				puts("Size exceeds partition or device limit\n");
 				return -1;
 			}
 
-			rwsize = pagecount * (nand->writesize + nand->oobsize);
+			rwsize = pagecount * (mtd->writesize + mtd->oobsize);
 		} else {
 			if (mtd_arg_off_size(argc - 3, argv + 3, &dev, &off,
 					     &size, &maxsize,
 					     MTD_DEV_TYPE_NAND,
-					     nand_info[dev].size) != 0)
+					     nand_info[dev]->size) != 0)
 				return 1;
 
 			if (set_dev(dev))
@@ -596,16 +597,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			rwsize = size;
 		}
 
-		nand = &nand_info[dev];
+		mtd = nand_info[dev];
 
 		if (!s || !strcmp(s, ".jffs2") ||
 		    !strcmp(s, ".e") || !strcmp(s, ".i")) {
 			if (read)
-				ret = nand_read_skip_bad(nand, off, &rwsize,
+				ret = nand_read_skip_bad(mtd, off, &rwsize,
 							 NULL, maxsize,
 							 (u_char *)addr);
 			else
-				ret = nand_write_skip_bad(nand, off, &rwsize,
+				ret = nand_write_skip_bad(mtd, off, &rwsize,
 							  NULL, maxsize,
 							  (u_char *)addr,
 							  WITH_WR_VERIFY);
@@ -615,7 +616,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				printf("Unknown nand command suffix '%s'\n", s);
 				return 1;
 			}
-			ret = nand_write_skip_bad(nand, off, &rwsize, NULL,
+			ret = nand_write_skip_bad(mtd, off, &rwsize, NULL,
 						maxsize, (u_char *)addr,
 						WITH_DROP_FFS | WITH_WR_VERIFY);
 #endif
@@ -628,11 +629,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 			};
 
 			if (read)
-				ret = mtd_read_oob(nand, off, &ops);
+				ret = mtd_read_oob(mtd, off, &ops);
 			else
-				ret = mtd_write_oob(nand, off, &ops);
+				ret = mtd_write_oob(mtd, off, &ops);
 		} else if (raw) {
-			ret = raw_access(nand, addr, off, pagecount, read);
+			ret = raw_access(mtd, addr, off, pagecount, read);
 		} else {
 			printf("Unknown nand command suffix '%s'.\n", s);
 			return 1;
@@ -655,8 +656,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		}
 
 		printf("\nNAND torture: device %d offset 0x%llx size 0x%x\n",
-			dev, off, nand->erasesize);
-		ret = nand_torture(nand, off);
+			dev, off, mtd->erasesize);
+		ret = nand_torture(mtd, off);
 		printf(" %s\n", ret ? "Failed" : "Passed");
 
 		return ret == 0 ? 0 : 1;
@@ -673,7 +674,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 		while (argc > 0) {
 			addr = simple_strtoul(*argv, NULL, 16);
 
-			if (mtd_block_markbad(nand, addr)) {
+			if (mtd_block_markbad(mtd, addr)) {
 				printf("block 0x%08lx NOT marked "
 					"as bad! ERROR %d\n",
 					addr, ret);
@@ -705,9 +706,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 				status = 1;
 		}
 		if (status) {
-			do_nand_status(nand);
+			do_nand_status(mtd);
 		} else {
-			if (!nand_lock(nand, tight)) {
+			if (!nand_lock(mtd, tight)) {
 				puts("NAND flash successfully locked\n");
 			} else {
 				puts("Error locking NAND flash\n");
@@ -727,13 +728,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 		if (mtd_arg_off_size(argc - 2, argv + 2, &dev, &off, &size,
 				     &maxsize, MTD_DEV_TYPE_NAND,
-				     nand_info[dev].size) < 0)
+				     nand_info[dev]->size) < 0)
 			return 1;
 
 		if (set_dev(dev))
 			return 1;
 
-		if (!nand_unlock(&nand_info[dev], off, size, allexcept)) {
+		if (!nand_unlock(nand_info[dev], off, size, allexcept)) {
 			puts("NAND flash successfully unlocked\n");
 		} else {
 			puts("Error unlocking NAND flash, "
@@ -801,7 +802,7 @@ U_BOOT_CMD(
 	"NAND sub-system", nand_help_text
 );
 
-static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
+static int nand_load_image(cmd_tbl_t *cmdtp, struct mtd_info *mtd,
 			   ulong offset, ulong addr, char *cmd)
 {
 	int r;
@@ -822,11 +823,11 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 		return 1;
 	}
 
-	printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset);
+	printf("\nLoading from %s, offset 0x%lx\n", mtd->name, offset);
 
-	cnt = nand->writesize;
-	r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
-			(u_char *)addr);
+	cnt = mtd->writesize;
+	r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+			       (u_char *)addr);
 	if (r) {
 		puts("** Read error\n");
 		bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ);
@@ -860,8 +861,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
 	}
 	bootstage_mark(BOOTSTAGE_ID_NAND_TYPE);
 
-	r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size,
-			(u_char *)addr);
+	r = nand_read_skip_bad(mtd, offset, &cnt, NULL, mtd->size,
+			       (u_char *)addr);
 	if (r) {
 		puts("** Read error\n");
 		bootstage_error(BOOTSTAGE_ID_NAND_READ);
@@ -914,7 +915,7 @@ static int do_nandboot(cmd_tbl_t *cmdtp, int flag, int argc,
 				addr = simple_strtoul(argv[1], NULL, 16);
 			else
 				addr = CONFIG_SYS_LOAD_ADDR;
-			return nand_load_image(cmdtp, &nand_info[dev->id->num],
+			return nand_load_image(cmdtp, nand_info[dev->id->num],
 					       part->offset, addr, argv[0]);
 		}
 	}
@@ -957,14 +958,14 @@ usage:
 
 	idx = simple_strtoul(boot_device, NULL, 16);
 
-	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx].name) {
+	if (idx < 0 || idx >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[idx]->name) {
 		printf("\n** Device %d not available\n", idx);
 		bootstage_error(BOOTSTAGE_ID_NAND_AVAILABLE);
 		return 1;
 	}
 	bootstage_mark(BOOTSTAGE_ID_NAND_AVAILABLE);
 
-	return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]);
+	return nand_load_image(cmdtp, nand_info[idx], offset, addr, argv[0]);
 }
 
 U_BOOT_CMD(nboot, 4, 1, do_nandboot,
diff --git a/cmd/qfw.c b/cmd/qfw.c
new file mode 100644
index 0000000000..12436ec9b4
--- /dev/null
+++ b/cmd/qfw.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <qfw.h>
+
+/*
+ * This function prepares kernel for zboot. It loads kernel data
+ * to 'load_addr', initrd to 'initrd_addr' and kernel command
+ * line using qemu fw_cfg interface.
+ */
+static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
+{
+	char *data_addr;
+	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
+
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
+
+	if (setup_size == 0 || kernel_size == 0) {
+		printf("warning: no kernel available\n");
+		return -1;
+	}
+
+	data_addr = load_addr;
+	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
+			      le32_to_cpu(setup_size), data_addr);
+	data_addr += le32_to_cpu(setup_size);
+
+	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
+			      le32_to_cpu(kernel_size), data_addr);
+	data_addr += le32_to_cpu(kernel_size);
+
+	data_addr = initrd_addr;
+	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
+	if (initrd_size == 0) {
+		printf("warning: no initrd available\n");
+	} else {
+		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
+				      le32_to_cpu(initrd_size), data_addr);
+		data_addr += le32_to_cpu(initrd_size);
+	}
+
+	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
+	if (cmdline_size) {
+		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
+				      le32_to_cpu(cmdline_size), data_addr);
+		/*
+		 * if kernel cmdline only contains '\0', (e.g. no -append
+		 * when invoking qemu), do not update bootargs
+		 */
+		if (*data_addr != '\0') {
+			if (setenv("bootargs", data_addr) < 0)
+				printf("warning: unable to change bootargs\n");
+		}
+	}
+
+	printf("loading kernel to address %p size %x", load_addr,
+	       le32_to_cpu(kernel_size));
+	if (initrd_size)
+		printf(" initrd %p size %x\n",
+		       initrd_addr,
+		       le32_to_cpu(initrd_size));
+	else
+		printf("\n");
+
+	return 0;
+}
+
+static int qemu_fwcfg_list_firmware(void)
+{
+	int ret;
+	struct fw_cfg_file_iter iter;
+	struct fw_file *file;
+
+	/* make sure fw_list is loaded */
+	ret = qemu_fwcfg_read_firmware_list();
+	if (ret)
+		return ret;
+
+
+	for (file = qemu_fwcfg_file_iter_init(&iter);
+	     !qemu_fwcfg_file_iter_end(&iter);
+	     file = qemu_fwcfg_file_iter_next(&iter)) {
+		printf("%-56s\n", file->cfg.name);
+	}
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	if (qemu_fwcfg_list_firmware() < 0)
+		return CMD_RET_FAILURE;
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	int ret = qemu_fwcfg_online_cpus();
+	if (ret < 0) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_FAILURE;
+	}
+
+	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+
+	return 0;
+}
+
+static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
+		int argc, char * const argv[])
+{
+	char *env;
+	void *load_addr;
+	void *initrd_addr;
+
+	env = getenv("loadaddr");
+	load_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_LOADADDR
+		(void *)CONFIG_LOADADDR;
+#else
+		NULL;
+#endif
+
+	env = getenv("ramdiskaddr");
+	initrd_addr = env ?
+		(void *)simple_strtoul(env, NULL, 16) :
+#ifdef CONFIG_RAMDISK_ADDR
+		(void *)CONFIG_RAMDISK_ADDR;
+#else
+		NULL;
+#endif
+
+	if (argc == 2) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else if (argc == 1) {
+		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	}
+
+	if (!load_addr || !initrd_addr) {
+		printf("missing load or initrd address\n");
+		return CMD_RET_FAILURE;
+	}
+
+	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
+}
+
+static cmd_tbl_t fwcfg_commands[] = {
+	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
+	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
+	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
+};
+
+static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int ret;
+	cmd_tbl_t *fwcfg_cmd;
+
+	if (!qemu_fwcfg_present()) {
+		printf("QEMU fw_cfg interface not found\n");
+		return CMD_RET_USAGE;
+	}
+
+	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
+				 ARRAY_SIZE(fwcfg_commands));
+	argc -= 2;
+	argv += 2;
+	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
+		return CMD_RET_USAGE;
+
+	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+
+	return cmd_process_error(fwcfg_cmd, ret);
+}
+
+U_BOOT_CMD(
+	qfw,	4,	1,	do_qemu_fw,
+	"QEMU firmware interface",
+	"<command>\n"
+	"    - list                             : print firmware(s) currently loaded\n"
+	"    - cpus                             : print online cpu number\n"
+	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
+)
diff --git a/cmd/ubi.c b/cmd/ubi.c
index 753a4dba3d..4a92d840b6 100644
--- a/cmd/ubi.c
+++ b/cmd/ubi.c
@@ -443,14 +443,8 @@ static int ubi_dev_scan(struct mtd_info *info, char *ubidev,
 	return 0;
 }
 
-int ubi_part(char *part_name, const char *vid_header_offset)
+int ubi_detach(void)
 {
-	int err = 0;
-	char mtd_dev[16];
-	struct mtd_device *dev;
-	struct part_info *part;
-	u8 pnum;
-
 	if (mtdparts_init() != 0) {
 		printf("Error initializing mtdparts!\n");
 		return 1;
@@ -466,17 +460,28 @@ int ubi_part(char *part_name, const char *vid_header_offset)
 		cmd_ubifs_umount();
 #endif
 
-	/* todo: get dev number for NAND... */
-	ubi_dev.nr = 0;
-
 	/*
 	 * Call ubi_exit() before re-initializing the UBI subsystem
 	 */
 	if (ubi_initialized) {
 		ubi_exit();
 		del_mtd_partitions(ubi_dev.mtd_info);
+		ubi_initialized = 0;
 	}
 
+	ubi_dev.selected = 0;
+	return 0;
+}
+
+int ubi_part(char *part_name, const char *vid_header_offset)
+{
+	int err = 0;
+	char mtd_dev[16];
+	struct mtd_device *dev;
+	struct part_info *part;
+	u8 pnum;
+
+	ubi_detach();
 	/*
 	 * Search the mtd device number where this partition
 	 * is located
@@ -517,6 +522,15 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
+
+	if (strcmp(argv[1], "detach") == 0) {
+		if (argc < 2)
+			return CMD_RET_USAGE;
+
+		return ubi_detach();
+	}
+
+
 	if (strcmp(argv[1], "part") == 0) {
 		const char *vid_header_offset = NULL;
 
@@ -661,7 +675,9 @@ static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 U_BOOT_CMD(
 	ubi, 6, 1, do_ubi,
 	"ubi commands",
-	"part [part] [offset]\n"
+	"detach"
+		" - detach ubi from a mtd partition\n"
+	"ubi part [part] [offset]\n"
 		" - Show or set current partition (with optional VID"
 		" header offset)\n"
 	"ubi info [l[ayout]]"
diff --git a/common/Kconfig b/common/Kconfig
index 067545d8a3..4d17b101a1 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -97,6 +97,15 @@ config BOOTSTAGE_STASH_SIZE
 
 endmenu
 
+config BOOTDELAY
+	int "delay in seconds before automatically booting"
+	default 0
+	help
+	  Delay before automatically running bootcmd;
+	  set to -1 to disable autoboot.
+	  set to -2 to autoboot with no delay and not check for abort
+	  (even when CONFIG_ZERO_BOOTDELAY_CHECK is defined).
+
 config CONSOLE_RECORD
 	bool "Console recording"
 	help
diff --git a/common/Makefile b/common/Makefile
index 0562d5cea4..1557a044de 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -26,8 +26,8 @@ obj-y += bootretry.o
 endif
 
 # boards
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
-obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
+obj-y += board_f.o
+obj-y += board_r.o
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
 obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o
 
diff --git a/common/board_f.c b/common/board_f.c
index 109025a68d..d405b5b407 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -274,7 +274,7 @@ static int setup_mon_len(void)
 	gd->mon_len = CONFIG_SYS_MONITOR_LEN;
 #elif defined(CONFIG_NDS32)
 	gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
-#else
+#elif defined(CONFIG_SYS_MONITOR_BASE)
 	/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
 	gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
 #endif
diff --git a/common/bootm.c b/common/bootm.c
index c965326db4..49414142dc 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -246,6 +246,16 @@ int bootm_find_images(int flag, int argc, char * const argv[])
 #endif
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+	/* find bitstreams */
+	ret = boot_get_fpga(argc, argv, &images, IH_ARCH_DEFAULT,
+			    NULL, NULL);
+	if (ret) {
+		printf("FPGA image is corrupted or invalid\n");
+		return 1;
+	}
+#endif
+
 	/* find all of the loadables */
 	ret = boot_get_loadable(argc, argv, &images, IH_ARCH_DEFAULT,
 			       NULL, NULL);
diff --git a/common/bootm_os.c b/common/bootm_os.c
index cb83f4a9bd..9ec84bd0db 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -484,9 +484,8 @@ int boot_selected_os(int argc, char * const argv[], int state,
 	    state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
 		return 0;
 	bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-#ifdef DEBUG
-	puts("\n## Control returned to monitor - resetting...\n");
-#endif
+	debug("\n## Control returned to monitor - resetting...\n");
+
 	return BOOTM_ERR_RESET;
 }
 
diff --git a/common/env_common.c b/common/env_common.c
index af59c72e1f..13db7dc3f7 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -123,6 +123,7 @@ void set_default_env(const char *s)
 		error("Environment import failed: errno = %d\n", errno);
 
 	gd->flags |= GD_FLG_ENV_READY;
+	gd->flags |= GD_FLG_ENV_DEFAULT;
 }
 
 
diff --git a/common/env_mmc.c b/common/env_mmc.c
index c7fef188cd..16f6a17514 100644
--- a/common/env_mmc.c
+++ b/common/env_mmc.c
@@ -128,12 +128,12 @@ static inline int write_env(struct mmc *mmc, unsigned long size,
 			    unsigned long offset, const void *buffer)
 {
 	uint blk_start, blk_cnt, n;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
 	blk_start	= ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len;
 	blk_cnt		= ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len;
 
-	n = mmc->block_dev.block_write(&mmc->block_dev, blk_start,
-					blk_cnt, (u_char *)buffer);
+	n = blk_dwrite(desc, blk_start, blk_cnt, (u_char *)buffer);
 
 	return (n == blk_cnt) ? 0 : -1;
 }
@@ -197,12 +197,12 @@ static inline int read_env(struct mmc *mmc, unsigned long size,
 			   unsigned long offset, const void *buffer)
 {
 	uint blk_start, blk_cnt, n;
+	struct blk_desc *desc = mmc_get_blk_desc(mmc);
 
 	blk_start	= ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt		= ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 
-	n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt,
-				      (uchar *)buffer);
+	n = blk_dread(desc, blk_start, blk_cnt, (uchar *)buffer);
 
 	return (n == blk_cnt) ? 0 : -1;
 }
diff --git a/common/env_nand.c b/common/env_nand.c
index b32eeac9d7..fc99a5e3fc 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -132,15 +132,15 @@ static int writeenv(size_t offset, u_char *buf)
 	size_t blocksize, len;
 	u_char *char_ptr;
 
-	blocksize = nand_info[0].erasesize;
+	blocksize = nand_info[0]->erasesize;
 	len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
 
 	while (amount_saved < CONFIG_ENV_SIZE && offset < end) {
-		if (nand_block_isbad(&nand_info[0], offset)) {
+		if (nand_block_isbad(nand_info[0], offset)) {
 			offset += blocksize;
 		} else {
 			char_ptr = &buf[amount_saved];
-			if (nand_write(&nand_info[0], offset, &len, char_ptr))
+			if (nand_write(nand_info[0], offset, &len, char_ptr))
 				return 1;
 
 			offset += blocksize;
@@ -164,7 +164,7 @@ static int erase_and_write_env(const struct env_location *location,
 	int ret = 0;
 
 	printf("Erasing %s...\n", location->name);
-	if (nand_erase_opts(&nand_info[0], &location->erase_opts))
+	if (nand_erase_opts(nand_info[0], &location->erase_opts))
 		return 1;
 
 	printf("Writing to %s... ", location->name);
@@ -247,20 +247,20 @@ static int readenv(size_t offset, u_char *buf)
 	size_t blocksize, len;
 	u_char *char_ptr;
 
-	blocksize = nand_info[0].erasesize;
+	blocksize = nand_info[0]->erasesize;
 	if (!blocksize)
 		return 1;
 
 	len = min(blocksize, (size_t)CONFIG_ENV_SIZE);
 
 	while (amount_loaded < CONFIG_ENV_SIZE && offset < end) {
-		if (nand_block_isbad(&nand_info[0], offset)) {
+		if (nand_block_isbad(nand_info[0], offset)) {
 			offset += blocksize;
 		} else {
 			char_ptr = &buf[amount_loaded];
-			if (nand_read_skip_bad(&nand_info[0], offset,
+			if (nand_read_skip_bad(nand_info[0], offset,
 					       &len, NULL,
-					       nand_info[0].size, char_ptr))
+					       nand_info[0]->size, char_ptr))
 				return 1;
 
 			offset += blocksize;
@@ -276,7 +276,7 @@ static int readenv(size_t offset, u_char *buf)
 #endif /* #if defined(CONFIG_SPL_BUILD) */
 
 #ifdef CONFIG_ENV_OFFSET_OOB
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result)
 {
 	struct mtd_oob_ops ops;
 	uint32_t oob_buf[ENV_OFFSET_SIZE / sizeof(uint32_t)];
@@ -288,14 +288,14 @@ int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
 	ops.ooblen	= ENV_OFFSET_SIZE;
 	ops.oobbuf	= (void *)oob_buf;
 
-	ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
+	ret = mtd->read_oob(mtd, ENV_OFFSET_SIZE, &ops);
 	if (ret) {
 		printf("error reading OOB block 0\n");
 		return ret;
 	}
 
 	if (oob_buf[0] == ENV_OOB_MARKER) {
-		*result = oob_buf[1] * nand->erasesize;
+		*result = oob_buf[1] * mtd->erasesize;
 	} else if (oob_buf[0] == ENV_OOB_MARKER_OLD) {
 		*result = oob_buf[1];
 	} else {
@@ -387,7 +387,7 @@ void env_relocate_spec(void)
 	ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
 
 #if defined(CONFIG_ENV_OFFSET_OOB)
-	ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+	ret = get_nand_env_oob(nand_info[0], &nand_env_oob_offset);
 	/*
 	 * If unable to read environment offset from NAND OOB then fall through
 	 * to the normal environment reading code below
diff --git a/common/fb_nand.c b/common/fb_nand.c
index 9ca8602a73..e55ea3872f 100644
--- a/common/fb_nand.c
+++ b/common/fb_nand.c
@@ -19,7 +19,7 @@
 static char *response_str;
 
 struct fb_nand_sparse {
-	nand_info_t		*nand;
+	struct mtd_info		*nand;
 	struct part_info	*part;
 };
 
@@ -34,7 +34,7 @@ __weak int board_fastboot_write_partition_setup(char *name)
 }
 
 static int fb_nand_lookup(const char *partname, char *response,
-			  nand_info_t **nand,
+			  struct mtd_info **nand,
 			  struct part_info **part)
 {
 	struct mtd_device *dev;
@@ -62,12 +62,12 @@ static int fb_nand_lookup(const char *partname, char *response,
 		return -EINVAL;
 	}
 
-	*nand = &nand_info[dev->id->num];
+	*mtd = nand_info[dev->id->num];
 
 	return 0;
 }
 
-static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
+static int _fb_nand_erase(struct mtd_info *mtd, struct part_info *part)
 {
 	nand_erase_options_t opts;
 	int ret;
@@ -80,7 +80,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
 	printf("Erasing blocks 0x%llx to 0x%llx\n",
 	       part->offset, part->offset + part->size);
 
-	ret = nand_erase_opts(nand, &opts);
+	ret = nand_erase_opts(mtd, &opts);
 	if (ret)
 		return ret;
 
@@ -90,7 +90,7 @@ static int _fb_nand_erase(nand_info_t *nand, struct part_info *part)
 	return 0;
 }
 
-static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
+static int _fb_nand_write(struct mtd_info *mtd, struct part_info *part,
 			  void *buffer, unsigned int offset,
 			  unsigned int length, size_t *written)
 {
@@ -100,7 +100,7 @@ static int _fb_nand_write(nand_info_t *nand, struct part_info *part,
 	flags |= WITH_DROP_FFS;
 #endif
 
-	return nand_write_skip_bad(nand, offset, &length, written,
+	return nand_write_skip_bad(mtd, offset, &length, written,
 				   part->size - (offset - part->offset),
 				   buffer, flags);
 }
@@ -131,13 +131,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 			 char *response)
 {
 	struct part_info *part;
-	nand_info_t *nand = NULL;
+	struct mtd_info *mtd = NULL;
 	int ret;
 
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &nand, &part);
+	ret = fb_nand_lookup(partname, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
@@ -152,10 +152,10 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		struct fb_nand_sparse sparse_priv;
 		sparse_storage_t sparse;
 
-		sparse_priv.nand = nand;
+		sparse_priv.nand = mtd;
 		sparse_priv.part = part;
 
-		sparse.block_sz = nand->writesize;
+		sparse.block_sz = mtd->writesize;
 		sparse.start = part->offset / sparse.block_sz;
 		sparse.size = part->size  / sparse.block_sz;
 		sparse.name = part->name;
@@ -167,7 +167,7 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 		printf("Flashing raw image at offset 0x%llx\n",
 		       part->offset);
 
-		ret = _fb_nand_write(nand, part, download_buffer, part->offset,
+		ret = _fb_nand_write(mtd, part, download_buffer, part->offset,
 				     download_bytes, NULL);
 
 		printf("........ wrote %u bytes to '%s'\n",
@@ -185,13 +185,13 @@ void fb_nand_flash_write(const char *partname, unsigned int session_id,
 void fb_nand_erase(const char *partname, char *response)
 {
 	struct part_info *part;
-	nand_info_t *nand = NULL;
+	struct mtd_info *mtd = NULL;
 	int ret;
 
 	/* initialize the response buffer */
 	response_str = response;
 
-	ret = fb_nand_lookup(partname, response, &nand, &part);
+	ret = fb_nand_lookup(partname, response, &mtd, &part);
 	if (ret) {
 		error("invalid NAND device");
 		fastboot_fail(response_str, "invalid NAND device");
@@ -202,9 +202,9 @@ void fb_nand_erase(const char *partname, char *response)
 	if (ret)
 		return;
 
-	ret = _fb_nand_erase(nand, part);
+	ret = _fb_nand_erase(mtd, part);
 	if (ret) {
-		error("failed erasing from device %s", nand->name);
+		error("failed erasing from device %s", mtd->name);
 		fastboot_fail(response_str, "failed erasing from device");
 		return;
 	}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 42e5d8a1d2..5d8eb12f10 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -964,10 +964,40 @@ static void of_dump_addr(const char *s, const fdt32_t *addr, int na)
 static void of_dump_addr(const char *s, const fdt32_t *addr, int na) { }
 #endif
 
-/* Callbacks for bus specific translators */
+/**
+ * struct of_bus - Callbacks for bus specific translators
+ * @name:	A string used to identify this bus in debug output.
+ * @addresses:	The name of the DT property from which addresses are
+ *		to be read, typically "reg".
+ * @match:	Return non-zero if the node whose parent is at
+ *		parentoffset in the FDT blob corresponds to a bus
+ *		of this type, otherwise return zero. If NULL a match
+ *		is assumed.
+ * @count_cells:Count how many cells (be32 values) a node whose parent
+ *		is at parentoffset in the FDT blob will require to
+ *		represent its address (written to *addrc) & size
+ *		(written to *sizec).
+ * @map:	Map the address addr from the address space of this
+ *		bus to that of its parent, making use of the ranges
+ *		read from DT to an array at range. na and ns are the
+ *		number of cells (be32 values) used to hold and address
+ *		or size, respectively, for this bus. pna is the number
+ *		of cells used to hold an address for the parent bus.
+ *		Returns the address in the address space of the parent
+ *		bus.
+ * @translate:	Update the value of the address cells at addr within an
+ *		FDT by adding offset to it. na specifies the number of
+ *		cells used to hold the address being translated. Returns
+ *		zero on success, non-zero on error.
+ *
+ * Each bus type will include a struct of_bus in the of_busses array,
+ * providing implementations of some or all of the functions used to
+ * match the bus & handle address translation for its children.
+ */
 struct of_bus {
 	const char	*name;
 	const char	*addresses;
+	int		(*match)(void *blob, int parentoffset);
 	void		(*count_cells)(void *blob, int parentoffset,
 				int *addrc, int *sizec);
 	u64		(*map)(fdt32_t *addr, const fdt32_t *range,
@@ -1022,8 +1052,70 @@ static int of_bus_default_translate(fdt32_t *addr, u64 offset, int na)
 	return 0;
 }
 
+#ifdef CONFIG_OF_ISA_BUS
+
+/* ISA bus translator */
+static int of_bus_isa_match(void *blob, int parentoffset)
+{
+	const char *name;
+
+	name = fdt_get_name(blob, parentoffset, NULL);
+	if (!name)
+		return 0;
+
+	return !strcmp(name, "isa");
+}
+
+static void of_bus_isa_count_cells(void *blob, int parentoffset,
+				   int *addrc, int *sizec)
+{
+	if (addrc)
+		*addrc = 2;
+	if (sizec)
+		*sizec = 1;
+}
+
+static u64 of_bus_isa_map(fdt32_t *addr, const fdt32_t *range,
+			  int na, int ns, int pna)
+{
+	u64 cp, s, da;
+
+	/* Check address type match */
+	if ((addr[0] ^ range[0]) & cpu_to_be32(1))
+		return OF_BAD_ADDR;
+
+	cp = of_read_number(range + 1, na - 1);
+	s  = of_read_number(range + na + pna, ns);
+	da = of_read_number(addr + 1, na - 1);
+
+	debug("OF: ISA map, cp=%" PRIu64 ", s=%" PRIu64
+	      ", da=%" PRIu64 "\n", cp, s, da);
+
+	if (da < cp || da >= (cp + s))
+		return OF_BAD_ADDR;
+	return da - cp;
+}
+
+static int of_bus_isa_translate(fdt32_t *addr, u64 offset, int na)
+{
+	return of_bus_default_translate(addr + 1, offset, na - 1);
+}
+
+#endif /* CONFIG_OF_ISA_BUS */
+
 /* Array of bus specific translators */
 static struct of_bus of_busses[] = {
+#ifdef CONFIG_OF_ISA_BUS
+	/* ISA */
+	{
+		.name = "isa",
+		.addresses = "reg",
+		.match = of_bus_isa_match,
+		.count_cells = of_bus_isa_count_cells,
+		.map = of_bus_isa_map,
+		.translate = of_bus_isa_translate,
+	},
+#endif /* CONFIG_OF_ISA_BUS */
 	/* Default */
 	{
 		.name = "default",
@@ -1034,6 +1126,28 @@ static struct of_bus of_busses[] = {
 	},
 };
 
+static struct of_bus *of_match_bus(void *blob, int parentoffset)
+{
+	struct of_bus *bus;
+
+	if (ARRAY_SIZE(of_busses) == 1)
+		return of_busses;
+
+	for (bus = of_busses; bus; bus++) {
+		if (!bus->match || bus->match(blob, parentoffset))
+			return bus;
+	}
+
+	/*
+	 * We should always have matched the default bus at least, since
+	 * it has a NULL match field. If we didn't then it somehow isn't
+	 * in the of_busses array or something equally catastrophic has
+	 * gone wrong.
+	 */
+	assert(0);
+	return NULL;
+}
+
 static int of_translate_one(void * blob, int parent, struct of_bus *bus,
 			    struct of_bus *pbus, fdt32_t *addr,
 			    int na, int ns, int pna, const char *rprop)
@@ -1113,7 +1227,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 	parent = fdt_parent_offset(blob, node_offset);
 	if (parent < 0)
 		goto bail;
-	bus = &of_busses[0];
+	bus = of_match_bus(blob, parent);
 
 	/* Cound address cells & copy address locally */
 	bus->count_cells(blob, parent, &na, &ns);
@@ -1142,7 +1256,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in
 		}
 
 		/* Get new parent bus and counts */
-		pbus = &of_busses[0];
+		pbus = of_match_bus(blob, parent);
 		pbus->count_cells(blob, parent, &pna, &pns);
 		if (!OF_CHECK_COUNTS(pna, pns)) {
 			printf("%s: Bad cell count for %s\n", __FUNCTION__,
diff --git a/common/image-fit.c b/common/image-fit.c
index c86b7c6b11..98739572a1 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -422,7 +422,8 @@ void fit_image_print(const void *fit, int image_noffset, const char *p)
 	}
 
 	if ((type == IH_TYPE_KERNEL) || (type == IH_TYPE_STANDALONE) ||
-	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK)) {
+	    (type == IH_TYPE_FIRMWARE) || (type == IH_TYPE_RAMDISK) ||
+	    (type == IH_TYPE_FPGA)) {
 		ret = fit_image_get_load(fit, image_noffset, &load);
 		printf("%s  Load Address: ", p);
 		if (ret)
@@ -1483,6 +1484,10 @@ void fit_conf_print(const void *fit, int noffset, const char *p)
 	if (uname)
 		printf("%s  FDT:          %s\n", p, uname);
 
+	uname = (char *)fdt_getprop(fit, noffset, FIT_FPGA_PROP, NULL);
+	if (uname)
+		printf("%s  FPGA:         %s\n", p, uname);
+
 	/* Print out all of the specified loadables */
 	for (loadables_index = 0;
 	     fdt_get_string_index(fit, noffset,
@@ -1567,6 +1572,8 @@ static const char *fit_get_image_type_property(int type)
 		return FIT_SETUP_PROP;
 	case IH_TYPE_LOADABLE:
 		return FIT_LOADABLE_PROP;
+	case IH_TYPE_FPGA:
+		return FIT_FPGA_PROP;
 	}
 
 	return "unknown";
@@ -1681,7 +1688,7 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
 			fit_image_check_type(fit, noffset,
 					     IH_TYPE_KERNEL_NOLOAD));
 
-	os_ok = image_type == IH_TYPE_FLATDT ||
+	os_ok = image_type == IH_TYPE_FLATDT || IH_TYPE_FPGA ||
 		fit_image_check_os(fit, noffset, IH_OS_LINUX) ||
 		fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
 
diff --git a/common/image.c b/common/image.c
index 26d6c9a592..0be09e5c63 100644
--- a/common/image.c
+++ b/common/image.c
@@ -32,6 +32,8 @@
 #if IMAGE_ENABLE_FIT || IMAGE_ENABLE_OF_LIBFDT
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <fpga.h>
+#include <xilinx.h>
 #endif
 
 #include <u-boot/md5.h>
@@ -159,6 +161,8 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_RKSD,       "rksd",       "Rockchip SD Boot Image" },
 	{	IH_TYPE_RKSPI,      "rkspi",      "Rockchip SPI Boot Image" },
 	{	IH_TYPE_ZYNQIMAGE,  "zynqimage",  "Xilinx Zynq Boot Image" },
+	{	IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" },
+	{	IH_TYPE_FPGA,       "fpga",       "FPGA Image" },
 	{	-1,		    "",		  "",			},
 };
 
@@ -1210,6 +1214,96 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 }
 
 #if IMAGE_ENABLE_FIT
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
+{
+	ulong tmp_img_addr, img_data, img_len;
+	void *buf;
+	int conf_noffset;
+	int fit_img_result;
+	char *uname, *name;
+	int err;
+	int devnum = 0; /* TODO support multi fpga platforms */
+	const fpga_desc * const desc = fpga_get_desc(devnum);
+	xilinx_desc *desc_xilinx = desc->devdesc;
+
+	/* Check to see if the images struct has a FIT configuration */
+	if (!genimg_has_config(images)) {
+		debug("## FIT configuration was not specified\n");
+		return 0;
+	}
+
+	/*
+	 * Obtain the os FIT header from the images struct
+	 * copy from dataflash if needed
+	 */
+	tmp_img_addr = map_to_sysmem(images->fit_hdr_os);
+	tmp_img_addr = genimg_get_image(tmp_img_addr);
+	buf = map_sysmem(tmp_img_addr, 0);
+	/*
+	 * Check image type. For FIT images get FIT node
+	 * and attempt to locate a generic binary.
+	 */
+	switch (genimg_get_format(buf)) {
+	case IMAGE_FORMAT_FIT:
+		conf_noffset = fit_conf_get_node(buf, images->fit_uname_cfg);
+
+		err = fdt_get_string_index(buf, conf_noffset, FIT_FPGA_PROP, 0,
+					   (const char **)&uname);
+		if (err < 0) {
+			debug("## FPGA image is not specified\n");
+			return 0;
+		}
+		fit_img_result = fit_image_load(images,
+						tmp_img_addr,
+						(const char **)&uname,
+						&(images->fit_uname_cfg),
+						arch,
+						IH_TYPE_FPGA,
+						BOOTSTAGE_ID_FPGA_INIT,
+						FIT_LOAD_OPTIONAL_NON_ZERO,
+						&img_data, &img_len);
+
+		debug("FPGA image (%s) loaded to 0x%lx/size 0x%lx\n",
+		      uname, img_data, img_len);
+
+		if (fit_img_result < 0) {
+			/* Something went wrong! */
+			return fit_img_result;
+		}
+
+		if (img_len >= desc_xilinx->size) {
+			name = "full";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_FULL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_FULL);
+		} else {
+			name = "partial";
+			err = fpga_loadbitstream(devnum, (char *)img_data,
+						 img_len, BIT_PARTIAL);
+			if (err)
+				err = fpga_load(devnum, (const void *)img_data,
+						img_len, BIT_PARTIAL);
+		}
+
+		printf("   Programming %s bitstream... ", name);
+		if (err)
+			printf("failed\n");
+		else
+			printf("OK\n");
+		break;
+	default:
+		printf("The given image format is not supported (corrupt?)\n");
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
 int boot_get_loadable(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
diff --git a/common/init/board_init.c b/common/init/board_init.c
index d17bb298d7..ef01a9aeaa 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -146,3 +146,8 @@ void board_init_f_init_reserve(ulong base)
 	base += CONFIG_SYS_MALLOC_F_LEN;
 #endif
 }
+
+/*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
diff --git a/common/main.c b/common/main.c
index 42bbb50733..2116a9e0a2 100644
--- a/common/main.c
+++ b/common/main.c
@@ -47,12 +47,6 @@ void main_loop(void)
 
 	bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
 
-#ifndef CONFIG_SYS_GENERIC_BOARD
-	puts("Warning: Your board does not use generic board. Please read\n");
-	puts("doc/README.generic-board and take action. Boards not\n");
-	puts("upgraded by the late 2014 may break or be removed.\n");
-#endif
-
 #ifdef CONFIG_VERSION_VARIABLE
 	setenv("ver", version_string);  /* set version variable */
 #endif /* CONFIG_VERSION_VARIABLE */
diff --git a/common/scsi.c b/common/scsi.c
index 8ac28dd416..dbbf4043b2 100644
--- a/common/scsi.c
+++ b/common/scsi.c
@@ -584,7 +584,7 @@ U_BOOT_DRIVER(scsi_blk) = {
 };
 #else
 U_BOOT_LEGACY_BLK(scsi) = {
-	.if_typename	= "sata",
+	.if_typename	= "scsi",
 	.if_type	= IF_TYPE_SCSI,
 	.max_devs	= CONFIG_SYS_SCSI_MAX_DEVICE,
 	.desc		= scsi_dev_desc,
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 93f9bd13fc..840910a684 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -36,6 +36,11 @@ struct spl_image_info spl_image;
 static bd_t bdata __attribute__ ((section(".data")));
 
 /*
+ * Board-specific Platform code can reimplement show_boot_progress () if needed
+ */
+__weak void show_boot_progress(int val) {}
+
+/*
  * Default function to determine if u-boot or the OS should
  * be started. This implementation always returns 1.
  *
@@ -64,6 +69,11 @@ __weak void spl_board_prepare_for_linux(void)
 	/* Nothing to do! */
 }
 
+__weak void spl_board_prepare_for_boot(void)
+{
+	/* Nothing to do! */
+}
+
 void spl_set_header_raw_uboot(void)
 {
 	spl_image.size = CONFIG_SYS_MONITOR_LEN;
@@ -135,20 +145,47 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 	image_entry();
 }
 
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+# define CONFIG_SPL_LOAD_FIT_ADDRESS	0
+#endif
+
 #ifdef CONFIG_SPL_RAM_DEVICE
+static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector,
+			       ulong count, void *buf)
+{
+	debug("%s: sector %lx, count %lx, buf %lx\n",
+	      __func__, sector, count, (ulong)buf);
+	memcpy(buf, (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + sector), count);
+	return count;
+}
+
 static int spl_ram_load_image(void)
 {
-	const struct image_header *header;
+	struct image_header *header;
 
-	/*
-	 * Get the header.  It will point to an address defined by handoff
-	 * which will tell where the image located inside the flash. For
-	 * now, it will temporary fixed to address pointed by U-Boot.
-	 */
-	header = (struct image_header *)
-		(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+	header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS;
 
-	spl_parse_image_header(header);
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.bl_len = 1;
+		load.read = spl_ram_load_read;
+		spl_load_simple_fit(&load, 0, header);
+	} else {
+		debug("Legacy image\n");
+		/*
+		 * Get the header.  It will point to an address defined by
+		 * handoff which will tell where the image located inside
+		 * the flash. For now, it will temporary fixed to address
+		 * pointed by U-Boot.
+		 */
+		header = (struct image_header *)
+			(CONFIG_SYS_TEXT_BASE -	sizeof(struct image_header));
+
+		spl_parse_image_header(header);
+	}
 
 	return 0;
 }
@@ -160,6 +197,9 @@ int spl_init(void)
 
 	debug("spl_init()\n");
 #if defined(CONFIG_SYS_MALLOC_F_LEN)
+#ifdef CONFIG_MALLOC_F_ADDR
+	gd->malloc_base = CONFIG_MALLOC_F_ADDR;
+#endif
 	gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
 	gd->malloc_ptr = 0;
 #endif
@@ -404,6 +444,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 #endif
 
 	debug("loaded - jumping to U-Boot...");
+	spl_board_prepare_for_boot();
 	jump_to_image_no_args(&spl_image);
 }
 
@@ -453,9 +494,6 @@ ulong spl_relocate_stack_gd(void)
 
 #ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE
 	if (CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN) {
-		if (!(gd->flags & GD_FLG_SPL_INIT))
-			panic_str("spl_init must be called before heap reloc");
-
 		ptr -= CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
 		gd->malloc_base = ptr;
 		gd->malloc_limit = CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN;
diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c
index 5b0d96925e..db676186d3 100644
--- a/common/spl/spl_fat.c
+++ b/common/spl/spl_fat.c
@@ -15,6 +15,7 @@
 #include <fat.h>
 #include <errno.h>
 #include <image.h>
+#include <libfdt.h>
 
 static int fat_registered;
 
@@ -39,6 +40,20 @@ static int spl_register_fat_device(struct blk_desc *block_dev, int partition)
 	return err;
 }
 
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+			  ulong size, void *buf)
+{
+	loff_t actread;
+	int ret;
+	char *filename = (char *)load->filename;
+
+	ret = fat_read_file(filename, buf, file_offset, size, &actread);
+	if (ret)
+		return ret;
+
+	return actread;
+}
+
 int spl_load_image_fat(struct blk_desc *block_dev,
 						int partition,
 						const char *filename)
@@ -57,11 +72,24 @@ int spl_load_image_fat(struct blk_desc *block_dev,
 	if (err <= 0)
 		goto end;
 
-	err = spl_parse_image_header(header);
-	if (err)
-		goto end;
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
+
+		debug("Found FIT\n");
+		load.read = spl_fit_read;
+		load.bl_len = 1;
+		load.filename = (void *)filename;
+		load.priv = NULL;
 
-	err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+		return spl_load_simple_fit(&load, 0, header);
+	} else {
+		err = spl_parse_image_header(header);
+		if (err)
+			goto end;
+
+		err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
+	}
 
 end:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 26842ba285..987470896c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -67,9 +67,7 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 
 		*fdt_offsetp = fdt_getprop_u32(fdt, fdt_node, "data-offset");
 		len = fdt_getprop_u32(fdt, fdt_node, "data-size");
-#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
-		printf("FIT: Selected '%s'\n", name);
-#endif
+		debug("FIT: Selected '%s'\n", name);
 
 		return len;
 	}
@@ -79,7 +77,7 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 	for (node = fdt_first_subnode(fdt, conf);
 	     node >= 0;
 	     node = fdt_next_subnode(fdt, node)) {
-		name = fdt_getprop(fdt, node, "name", &len);
+		name = fdt_getprop(fdt, node, "description", &len);
 		printf("   %s\n", name);
 	}
 #endif
@@ -87,6 +85,42 @@ static int spl_fit_select_fdt(const void *fdt, int images, int *fdt_offsetp)
 	return -ENOENT;
 }
 
+static int get_aligned_image_offset(struct spl_load_info *info, int offset)
+{
+	/*
+	 * If it is a FS read, get the first address before offset which is
+	 * aligned to ARCH_DMA_MINALIGN. If it is raw read return the
+	 * block number to which offset belongs.
+	 */
+	if (info->filename)
+		return offset & ~(ARCH_DMA_MINALIGN - 1);
+
+	return offset / info->bl_len;
+}
+
+static int get_aligned_image_overhead(struct spl_load_info *info, int offset)
+{
+	/*
+	 * If it is a FS read, get the difference between the offset and
+	 * the first address before offset which is aligned to
+	 * ARCH_DMA_MINALIGN. If it is raw read return the offset within the
+	 * block.
+	 */
+	if (info->filename)
+		return offset & (ARCH_DMA_MINALIGN - 1);
+
+	return offset % info->bl_len;
+}
+
+static int get_aligned_image_size(struct spl_load_info *info, int data_size,
+				  int offset)
+{
+	if (info->filename)
+		return data_size + get_aligned_image_overhead(info, offset);
+
+	return (data_size + info->bl_len - 1) / info->bl_len;
+}
+
 int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 {
 	int sectors;
@@ -96,7 +130,7 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	void *load_ptr;
 	int fdt_offset, fdt_len;
 	int data_offset, data_size;
-	int base_offset;
+	int base_offset, align_len = ARCH_DMA_MINALIGN - 1;
 	int src_sector;
 	void *dst;
 
@@ -122,8 +156,9 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * In fact the FIT has its own load address, but we assume it cannot
 	 * be before CONFIG_SYS_TEXT_BASE.
 	 */
-	fit = (void *)(CONFIG_SYS_TEXT_BASE - size - info->bl_len);
-	sectors = (size + info->bl_len - 1) / info->bl_len;
+	fit = (void *)((CONFIG_SYS_TEXT_BASE - size - info->bl_len -
+			align_len) & ~align_len);
+	sectors = get_aligned_image_size(info, size, 0);
 	count = info->read(info, sector, sectors, fit);
 	debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu\n",
 	      sector, sectors, fit, count);
@@ -156,19 +191,23 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * byte will be at 'load'. This may mean we need to load it starting
 	 * before then, since we can only read whole blocks.
 	 */
-	sectors = (data_size + info->bl_len - 1) / info->bl_len;
 	data_offset += base_offset;
+	sectors = get_aligned_image_size(info, data_size, data_offset);
 	load_ptr = (void *)load;
 	debug("U-Boot size %x, data %p\n", data_size, load_ptr);
-	dst = load_ptr - (data_offset % info->bl_len);
+	dst = load_ptr;
 
 	/* Read the image */
-	src_sector = sector + data_offset / info->bl_len;
-	debug("image: data_offset=%x, dst=%p, src_sector=%x, sectors=%x\n",
-	      data_offset, dst, src_sector, sectors);
+	src_sector = sector + get_aligned_image_offset(info, data_offset);
+	debug("Aligned image read: dst=%p, src_sector=%x, sectors=%x\n",
+	      dst, src_sector, sectors);
 	count = info->read(info, src_sector, sectors, dst);
 	if (count != sectors)
 		return -EIO;
+	debug("image: dst=%p, data_offset=%x, size=%x\n", dst, data_offset,
+	      data_size);
+	memcpy(dst, dst + get_aligned_image_overhead(info, data_offset),
+	       data_size);
 
 	/* Figure out which device tree the board wants to use */
 	fdt_len = spl_fit_select_fdt(fit, images, &fdt_offset);
@@ -178,13 +217,15 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	/*
 	 * Read the device tree and place it after the image. There may be
 	 * some extra data before it since we can only read entire blocks.
+	 * And also align the destination address to ARCH_DMA_MINALIGN.
 	 */
-	dst = load_ptr + data_size;
+	dst = (void *)((load + data_size + align_len) & ~align_len);
 	fdt_offset += base_offset;
-	count = info->read(info, sector + fdt_offset / info->bl_len, sectors,
-			   dst);
-	debug("fit read %x sectors to %x, dst %p, data_offset %x\n",
-	      sectors, spl_image.load_addr, dst, fdt_offset);
+	sectors = get_aligned_image_size(info, fdt_len, fdt_offset);
+	src_sector = sector + get_aligned_image_offset(info, fdt_offset);
+	count = info->read(info, src_sector, sectors, dst);
+	debug("Aligned fdt read: dst %p, src_sector = %x, sectors %x\n",
+	      dst, src_sector, sectors);
 	if (count != sectors)
 		return -EIO;
 
@@ -193,7 +234,10 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit)
 	 * After this we will have the U-Boot image and its device tree ready
 	 * for us to start.
 	 */
-	memcpy(dst, dst + fdt_offset % info->bl_len, fdt_len);
+	debug("fdt: dst=%p, data_offset=%x, size=%x\n", dst, fdt_offset,
+	      fdt_len);
+	memcpy(load_ptr + data_size,
+	       dst + get_aligned_image_overhead(info, fdt_offset), fdt_len);
 
 	return 0;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 5676acdde3..ef8583a1a6 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -34,9 +34,8 @@ static int mmc_load_legacy(struct mmc *mmc, ulong sector,
 			     mmc->read_bl_len;
 
 	/* Read the header too to avoid extra memcpy */
-	count = mmc->block_dev.block_read(&mmc->block_dev, sector,
-					  image_size_sectors,
-					  (void *)(ulong)spl_image.load_addr);
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors,
+			  (void *)(ulong)spl_image.load_addr);
 	debug("read %x sectors to %x\n", image_size_sectors,
 	      spl_image.load_addr);
 	if (count != image_size_sectors)
@@ -50,7 +49,7 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector,
 {
 	struct mmc *mmc = load->dev;
 
-	return mmc->block_dev.block_read(&mmc->block_dev, sector, count, buf);
+	return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf);
 }
 
 static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
@@ -63,7 +62,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 					 sizeof(struct image_header));
 
 	/* read image header to find the image size & load address */
-	count = mmc->block_dev.block_read(&mmc->block_dev, sector, 1, header);
+	count = blk_dread(mmc_get_blk_desc(mmc), sector, 1, header);
 	debug("hdr read sector %lx, count=%lu\n", sector, count);
 	if (count == 0) {
 		ret = -EIO;
@@ -77,6 +76,7 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector)
 		debug("Found FIT\n");
 		load.dev = mmc;
 		load.priv = NULL;
+		load.filename = NULL;
 		load.bl_len = mmc->read_bl_len;
 		load.read = h_spl_load_read;
 		ret = spl_load_simple_fit(&load, sector, header);
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index bbd9546987..7cf0d1b986 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -9,6 +9,8 @@
 #include <spl.h>
 #include <asm/io.h>
 #include <nand.h>
+#include <libfdt_env.h>
+#include <fdt.h>
 
 #if defined(CONFIG_SPL_NAND_RAW_ONLY)
 int spl_nand_load_image(void)
@@ -24,6 +26,19 @@ int spl_nand_load_image(void)
 	return 0;
 }
 #else
+
+static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
+			       ulong size, void *dst)
+{
+	int ret;
+
+	ret = nand_spl_load_image(offs, size, dst);
+	if (!ret)
+		return size;
+	else
+		return 0;
+}
+
 static int spl_nand_load_element(int offset, struct image_header *header)
 {
 	int err;
@@ -32,12 +47,24 @@ static int spl_nand_load_element(int offset, struct image_header *header)
 	if (err)
 		return err;
 
-	err = spl_parse_image_header(header);
-	if (err)
-		return err;
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic(header) == FDT_MAGIC) {
+		struct spl_load_info load;
 
-	return nand_spl_load_image(offset, spl_image.size,
-				   (void *)(unsigned long)spl_image.load_addr);
+		debug("Found FIT\n");
+		load.dev = NULL;
+		load.priv = NULL;
+		load.filename = NULL;
+		load.bl_len = 1;
+		load.read = spl_nand_fit_read;
+		return spl_load_simple_fit(&load, offset, header);
+	} else {
+		err = spl_parse_image_header(header);
+		if (err)
+			return err;
+		return nand_spl_load_image(offset, spl_image.size,
+					   (void *)(ulong)spl_image.load_addr);
+	}
 }
 
 int spl_nand_load_image(void)
diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c
index 4f26ea5d21..5402301c78 100644
--- a/common/spl/spl_ymodem.c
+++ b/common/spl/spl_ymodem.c
@@ -14,15 +14,60 @@
 #include <xyzModem.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
+#include <libfdt.h>
 
 #define BUF_SIZE 1024
 
+/*
+ * Information required to load image using ymodem.
+ *
+ * @image_read: Now of bytes read from the image.
+ * @buf: pointer to the previous read block.
+ */
+struct ymodem_fit_info {
+	int image_read;
+	char *buf;
+};
+
 static int getcymodem(void) {
 	if (tstc())
 		return (getc());
 	return -1;
 }
 
+static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset,
+			     ulong size, void *addr)
+{
+	int res, err;
+	struct ymodem_fit_info *info = load->priv;
+	char *buf = info->buf;
+
+	while (info->image_read < offset) {
+		res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+		if (res <= 0)
+			return res;
+		info->image_read += res;
+	}
+
+	if (info->image_read > offset) {
+		res = info->image_read - offset;
+		memcpy(addr, &buf[BUF_SIZE - res], res);
+		addr = addr + res;
+	}
+
+	while (info->image_read < offset + size) {
+		res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+		if (res <= 0)
+			return res;
+
+		memcpy(addr, buf, res);
+		info->image_read += res;
+		addr += res;
+	}
+
+	return size;
+}
+
 int spl_ymodem_load_image(void)
 {
 	int size = 0;
@@ -31,30 +76,55 @@ int spl_ymodem_load_image(void)
 	int ret;
 	connection_info_t info;
 	char buf[BUF_SIZE];
-	ulong store_addr = ~0;
 	ulong addr = 0;
 
 	info.mode = xyzModem_ymodem;
 	ret = xyzModem_stream_open(&info, &err);
+	if (ret) {
+		printf("spl: ymodem err - %s\n", xyzModem_error(err));
+		return ret;
+	}
+
+	res = xyzModem_stream_read(buf, BUF_SIZE, &err);
+	if (res <= 0)
+		goto end_stream;
+
+	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+	    image_get_magic((struct image_header *)buf) == FDT_MAGIC) {
+		struct spl_load_info load;
+		struct ymodem_fit_info info;
+
+		debug("Found FIT\n");
+		load.dev = NULL;
+		load.priv = (void *)&info;
+		load.filename = NULL;
+		load.bl_len = 1;
+		info.buf = buf;
+		info.image_read = BUF_SIZE;
+		load.read = ymodem_read_fit;
+		ret =  spl_load_simple_fit(&load, 0, (void *)buf);
+		size = info.image_read;
 
-	if (!ret) {
-		while ((res =
-			xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
-			if (addr == 0) {
-				ret = spl_parse_image_header((struct image_header *)buf);
-				if (ret)
-					return ret;
-			}
-			store_addr = addr + spl_image.load_addr;
+		while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0)
+			size += res;
+	} else {
+		spl_parse_image_header((struct image_header *)buf);
+		ret = spl_parse_image_header((struct image_header *)buf);
+		if (ret)
+			return ret;
+		addr = spl_image.load_addr;
+		memcpy((void *)addr, buf, res);
+		size += res;
+		addr += res;
+
+		while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) {
+			memcpy((void *)addr, buf, res);
 			size += res;
 			addr += res;
-			memcpy((char *)(store_addr), buf, res);
 		}
-	} else {
-		printf("spl: ymodem err - %s\n", xyzModem_error(err));
-		return ret;
 	}
 
+end_stream:
 	xyzModem_stream_close(&err);
 	xyzModem_stream_terminate(false, &getcymodem);
 
diff --git a/common/splash_source.c b/common/splash_source.c
index a09dd4b46e..f86a78a436 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -45,9 +45,9 @@ static int splash_sf_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 #ifdef CONFIG_CMD_NAND
 static int splash_nand_read_raw(u32 bmp_load_addr, int offset, size_t read_size)
 {
-	return nand_read_skip_bad(&nand_info[nand_curr_device], offset,
+	return nand_read_skip_bad(nand_info[nand_curr_device], offset,
 				  &read_size, NULL,
-				  nand_info[nand_curr_device].size,
+				  nand_info[nand_curr_device]->size,
 				  (u_char *)bmp_load_addr);
 }
 #else
diff --git a/common/usb.c b/common/usb.c
index 8d9efe516b..b3ba487890 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1182,7 +1182,7 @@ int usb_new_device(struct usb_device *dev)
 	 * with the device. So a get_descriptor will fail before any
 	 * of that is done for XHCI unlike EHCI.
 	 */
-#ifdef CONFIG_USB_XHCI
+#ifdef CONFIG_USB_XHCI_HCD
 	do_read = false;
 #endif
 	err = usb_setup_device(dev, do_read, dev->parent);
diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig
index d7725e4e54..378f7a1928 100644
--- a/configs/A10-OLinuXino-Lime_defconfig
+++ b/configs/A10-OLinuXino-Lime_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_EMR1=4
 CONFIG_SYS_CLK_FREQ=912000000
@@ -9,20 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig
index c39daf167f..6a0d81530c 100644
--- a/configs/A10s-OLinuXino-M_defconfig
+++ b/configs/A10s-OLinuXino-M_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig
index 955b6cf00a..a790856e00 100644
--- a/configs/A13-OLinuXinoM_defconfig
+++ b/configs/A13-OLinuXinoM_defconfig
@@ -14,19 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig
index 30ea836f39..d12a3cc756 100644
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -16,22 +16,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig
index 546c84c930..cc5858ec68 100644
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -9,20 +9,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig
index 5dc4ba3fd7..7b0309c8cd 100644
--- a/configs/A20-OLinuXino-Lime_defconfig
+++ b/configs/A20-OLinuXino-Lime_defconfig
@@ -7,20 +7,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-lime"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO3_VOLT=2800
 CONFIG_AXP_ALDO4_VOLT=2800
diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig
index e952562205..f121cabeb1 100644
--- a/configs/A20-OLinuXino_MICRO_defconfig
+++ b/configs/A20-OLinuXino_MICRO_defconfig
@@ -10,19 +10,10 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig
index cecf4c20c5..57609b384f 100644
--- a/configs/A20-Olimex-SOM-EVB_defconfig
+++ b/configs/A20-Olimex-SOM-EVB_defconfig
@@ -12,20 +12,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som-evb"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_RTL8211X_PHY_FORCE_MASTER=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig
index 7479f7f7dd..fc1be7d819 100644
--- a/configs/Ainol_AW1_defconfig
+++ b/configs/Ainol_AW1_defconfig
@@ -14,18 +14,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig
index fde84acd14..8262be5405 100644
--- a/configs/Ampe_A76_defconfig
+++ b/configs/Ampe_A76_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig
index 45539c1ea1..44f3982f64 100644
--- a/configs/Auxtek-T003_defconfig
+++ b/configs/Auxtek-T003_defconfig
@@ -8,19 +8,8 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t003"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig
index 52dfdf25f0..9d5365dce6 100644
--- a/configs/Auxtek-T004_defconfig
+++ b/configs/Auxtek-T004_defconfig
@@ -6,19 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-auxtek-t004"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig
index 369afbb22a..06d89af4b0 100644
--- a/configs/B4420QDS_NAND_defconfig
+++ b/configs/B4420QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig
index 408e84e58f..0e2d3f9908 100644
--- a/configs/B4420QDS_SPIFLASH_defconfig
+++ b/configs/B4420QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig
index bab96cac60..36986b5fd8 100644
--- a/configs/B4420QDS_defconfig
+++ b/configs/B4420QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig
index 10fe1d0361..6aea615f57 100644
--- a/configs/B4860QDS_NAND_defconfig
+++ b/configs/B4860QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig
index 5e754ebee1..505e014854 100644
--- a/configs/B4860QDS_SECURE_BOOT_defconfig
+++ b/configs/B4860QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig
index fca6f5aeb0..4696d6d37e 100644
--- a/configs/B4860QDS_SPIFLASH_defconfig
+++ b/configs/B4860QDS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
index e833e0c391..dfbf2cb4d8 100644
--- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig
index cd27638359..b6c45ea336 100644
--- a/configs/B4860QDS_defconfig
+++ b/configs/B4860QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
index cdfccbed43..85d4a85bdb 100644
--- a/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_NAND_SYSCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND,SYS_CLK_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_NAND_defconfig b/configs/BSC9131RDB_NAND_defconfig
index 555e446a3b..2937dc3cbb 100644
--- a/configs/BSC9131RDB_NAND_defconfig
+++ b/configs/BSC9131RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
index 014916c0d4..fd33d14291 100644
--- a/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH,SYS_CLK_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9131RDB_SPIFLASH_defconfig b/configs/BSC9131RDB_SPIFLASH_defconfig
index 941fe75f37..572de826dd 100644
--- a/configs/BSC9131RDB_SPIFLASH_defconfig
+++ b/configs/BSC9131RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9131RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
index ae8271be58..523b7ada86 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
index 502ba3c7ca..f15c4a16db 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
index d60c0c1bf8..6d685b6d48 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
index 43fa804e3b..7cdc2b2a78 100644
--- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
index adc42c515a..8fdc698aa3 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
index d591a373fc..c40b6fe31d 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
index 034109eba4..b5fc43376a 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
index c804b4f1cd..c4bbb5140b 100644
--- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
index 49609b7f5c..456fb8dc62 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
index a64db9bb98..867e433465 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
index 0850d84da9..effdd33ef1 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
index 7d7ecd277d..3d86331544 100644
--- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
index a46d8d77f0..0ac319cf24 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
index 3ef15fcef7..25e5afa96f 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
index 307813cc8f..00fe70b917 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
index aef5e7bdd9..f20f23102e 100644
--- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
+++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig
index fd6b8de357..d9b1bd6ca4 100644
--- a/configs/Bananapi_defconfig
+++ b/configs/Bananapi_defconfig
@@ -8,20 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig
index ae385835fb..496c20edd3 100644
--- a/configs/Bananapro_defconfig
+++ b/configs/Bananapro_defconfig
@@ -10,20 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-bananapro"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_NETCONSOLE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO4_VOLT=2500
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index cbbec4706c..19ae280dfb 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -8,25 +8,15 @@ CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_ALDO3_VOLT=3300
 CONFIG_AXP_ALDO4_VOLT=3300
+CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Allwinner Technology"
 CONFIG_G_DNL_VENDOR_NUM=0x1f3a
 CONFIG_G_DNL_PRODUCT_NUM=0x1010
-CONFIG_USB_EHCI_HCD=y
diff --git a/configs/CPCI2DP_defconfig b/configs/CPCI2DP_defconfig
index ea0775d585..99e4ad007d 100644
--- a/configs/CPCI2DP_defconfig
+++ b/configs/CPCI2DP_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI2DP=y
+CONFIG_BOOTDELAY=3
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/CPCI4052_defconfig b/configs/CPCI4052_defconfig
index 25818bd3b4..d7c71c1a99 100644
--- a/configs/CPCI4052_defconfig
+++ b/configs/CPCI4052_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_CPCI4052=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig
index ab6f329bed..1cb010d7d5 100644
--- a/configs/CSQ_CS908_defconfig
+++ b/configs/CSQ_CS908_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-cs908"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_DLDO1_VOLT=3300
diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig
index 080bfbd36d..4b9abea67b 100644
--- a/configs/Chuwi_V7_CW0825_defconfig
+++ b/configs/Chuwi_V7_CW0825_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
@@ -14,20 +13,9 @@ CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SPI_CS="PA0"
 CONFIG_VIDEO_LCD_SPI_SCLK="PA1"
diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig
index 6380a22a99..2ce8cb1996 100644
--- a/configs/Colombus_defconfig
+++ b/configs/Colombus_defconfig
@@ -18,20 +18,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-colombus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig
index 683f7f9730..4b9d722bcc 100644
--- a/configs/Cubieboard2_defconfig
+++ b/configs/Cubieboard2_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubieboard2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig
index f8c7107563..97bdcd64f2 100644
--- a/configs/Cubieboard_defconfig
+++ b/configs/Cubieboard_defconfig
@@ -1,24 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=480
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-cubieboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig
index 0d43c53d9d..4e25392a3b 100644
--- a/configs/Cubietruck_defconfig
+++ b/configs/Cubietruck_defconfig
@@ -12,22 +12,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-cubietruck"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_GADGET=y
diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig
index b5959eea47..f2c6fe7fd5 100644
--- a/configs/Cubietruck_plus_defconfig
+++ b/configs/Cubietruck_plus_defconfig
@@ -4,7 +4,6 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="AXP0-VBUS-ENABLE"
 CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT"
 CONFIG_USB0_ID_DET="PH11"
@@ -15,20 +14,9 @@ CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO3_VOLT=2500
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_AXP_FLDO1_VOLT=1200
diff --git a/configs/Cyrus_P5020_defconfig b/configs/Cyrus_P5020_defconfig
index 78e94ab7fa..d53c629483 100644
--- a/configs/Cyrus_P5020_defconfig
+++ b/configs/Cyrus_P5020_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/Cyrus_P5040_defconfig b/configs/Cyrus_P5040_defconfig
index f03d738b52..a7c6307a83 100644
--- a/configs/Cyrus_P5040_defconfig
+++ b/configs/Cyrus_P5040_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig
index 7cc162b376..5f0176083d 100644
--- a/configs/Empire_electronix_d709_defconfig
+++ b/configs/Empire_electronix_d709_defconfig
@@ -17,18 +17,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-empire-electronix-d709"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig
index f424557fcc..02bcdbf56a 100644
--- a/configs/Hummingbird_A31_defconfig
+++ b/configs/Hummingbird_A31_defconfig
@@ -10,19 +10,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-hummingbird"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig
index 4ff0a6bc5c..77e496c25f 100644
--- a/configs/Hyundai_A7HD_defconfig
+++ b/configs/Hyundai_A7HD_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB09"
 CONFIG_USB0_VBUS_DET="PH5"
@@ -15,18 +14,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig
index f4832a7830..cb6dfe4d10 100644
--- a/configs/Itead_Ibox_A20_defconfig
+++ b/configs/Itead_Ibox_A20_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-itead-ibox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig
index 122799425b..d2111c6b41 100644
--- a/configs/Lamobo_R1_defconfig
+++ b/configs/Lamobo_R1_defconfig
@@ -8,19 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-lamobo-r1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,SATAPWR=SUNXI_GPB(3)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig
index 3b0d8cfa1e..378abce94b 100644
--- a/configs/Linksprite_pcDuino3_Nano_defconfig
+++ b/configs/Linksprite_pcDuino3_Nano_defconfig
@@ -9,19 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3-nano"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig
index 28768ec519..c3f0421e91 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig
index 11bb7091fc..94aab9dba8 100644
--- a/configs/Linksprite_pcDuino_defconfig
+++ b/configs/Linksprite_pcDuino_defconfig
@@ -1,24 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB1_VBUS_PIN=""
 CONFIG_USB2_VBUS_PIN=""
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pcduino"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig
index 93e39b4943..36067000ef 100644
--- a/configs/M52277EVB_defconfig
+++ b/configs/M52277EVB_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x00000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="-> "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig
index b63386d59a..af463c3c7c 100644
--- a/configs/M52277EVB_stmicro_defconfig
+++ b/configs/M52277EVB_stmicro_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_M52277EVB=y
 CONFIG_SYS_TEXT_BASE=0x43E00000
 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig
index fc29e306ac..e758873c4d 100644
--- a/configs/M5253DEMO_defconfig
+++ b/configs/M5253DEMO_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5253DEMO=y
 CONFIG_SYS_TEXT_BASE=0xFF800000
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig
index 15c22df7a5..17ded58887 100644
--- a/configs/M5253EVBE_defconfig
+++ b/configs/M5253EVBE_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5253EVBE=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NET is not set
 CONFIG_CMD_CACHE=y
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index 585ea17d5d..7638b18991 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5272C3=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig
index cd751181d1..a7af3564ba 100644
--- a/configs/M5275EVB_defconfig
+++ b/configs/M5275EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5275EVB=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig
index df12b3a832..f415f7b5f4 100644
--- a/configs/M5282EVB_defconfig
+++ b/configs/M5282EVB_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_M5282EVB=y
 CONFIG_SYS_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="-> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig
index 0d0c029d66..c9913ae3af 100644
--- a/configs/MIP405T_defconfig
+++ b/configs/MIP405T_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
 CONFIG_SYS_EXTRA_OPTIONS="MIP405T"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig
index aa23499326..1d8e38ebc5 100644
--- a/configs/MIP405_defconfig
+++ b/configs/MIP405_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MIP405=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig
index ca61e5c3ea..49bb26a098 100644
--- a/configs/MK808C_defconfig
+++ b/configs/MK808C_defconfig
@@ -5,18 +5,7 @@ CONFIG_DRAM_CLK=384
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig
index 9e6f50b719..4e25193cf6 100644
--- a/configs/MPC8308RDB_defconfig
+++ b/configs/MPC8308RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig
index 978e23164b..2fdffa9b43 100644
--- a/configs/MPC8313ERDB_33_defconfig
+++ b/configs/MPC8313ERDB_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig
index 35db54169c..56538ccb94 100644
--- a/configs/MPC8313ERDB_66_defconfig
+++ b/configs/MPC8313ERDB_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8313ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig
index 63c6d7b264..efabb9a1eb 100644
--- a/configs/MPC8313ERDB_NAND_33_defconfig
+++ b/configs/MPC8313ERDB_NAND_33_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ,NAND"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig
index a3d5294057..be0e274867 100644
--- a/configs/MPC8313ERDB_NAND_66_defconfig
+++ b/configs/MPC8313ERDB_NAND_66_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ,NAND"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_GPIO=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index dfb41f0cee..f2aef3332e 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8315ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig
index cf2f6557e8..5e5a2d0f98 100644
--- a/configs/MPC8323ERDB_defconfig
+++ b/configs/MPC8323ERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8323ERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig
index 0c85f409e4..72aacf3178 100644
--- a/configs/MPC832XEMDS_ATM_defconfig
+++ b/configs/MPC832XEMDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig
index e9cf0c8d97..3e7390f84e 100644
--- a/configs/MPC832XEMDS_HOST_33_defconfig
+++ b/configs/MPC832XEMDS_HOST_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M,PQ_MDS_PIB=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig
index 92724311a6..c65d3c9402 100644
--- a/configs/MPC832XEMDS_HOST_66_defconfig
+++ b/configs/MPC832XEMDS_HOST_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M,PQ_MDS_PIB=1"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig
index d8078847f5..5c95787e2a 100644
--- a/configs/MPC832XEMDS_SLAVE_defconfig
+++ b/configs/MPC832XEMDS_SLAVE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCISLAVE"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig
index 8900665b5b..4d7c52f054 100644
--- a/configs/MPC832XEMDS_defconfig
+++ b/configs/MPC832XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC832XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig
index 60561cfdd5..7ed79233b1 100644
--- a/configs/MPC8349EMDS_defconfig
+++ b/configs/MPC8349EMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8349EMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig
index fb7485cd90..f1afcf853c 100644
--- a/configs/MPC8349ITXGP_defconfig
+++ b/configs/MPC8349ITXGP_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX-GP> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig
index 65edb63925..5c9f7fc076 100644
--- a/configs/MPC8349ITX_LOWBOOT_defconfig
+++ b/configs/MPC8349ITX_LOWBOOT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX,SYS_TEXT_BASE=0xFE000000"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig
index 358656e8e0..df08fe38df 100644
--- a/configs/MPC8349ITX_defconfig
+++ b/configs/MPC8349ITX_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8349ITX=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC8349ITX"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="MPC8349E-mITX> "
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig
index 0e09e77afe..d8b5607093 100644
--- a/configs/MPC837XEMDS_HOST_defconfig
+++ b/configs/MPC837XEMDS_HOST_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig
index f7ad159f0a..c04c2560a8 100644
--- a/configs/MPC837XEMDS_defconfig
+++ b/configs/MPC837XEMDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XEMDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 1b2c7870e8..0d6e4b6791 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC837XERDB=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig
index 40d1a3a235..2ffc6474cf 100644
--- a/configs/MPC8536DS_36BIT_defconfig
+++ b/configs/MPC8536DS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig
index c6afe45adf..5f4d51a6c7 100644
--- a/configs/MPC8536DS_SDCARD_defconfig
+++ b/configs/MPC8536DS_SDCARD_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig
index eafa11c44e..0fdc9de5e6 100644
--- a/configs/MPC8536DS_SPIFLASH_defconfig
+++ b/configs/MPC8536DS_SPIFLASH_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig
index 0ae81ef618..13e06d655a 100644
--- a/configs/MPC8536DS_defconfig
+++ b/configs/MPC8536DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8536DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/MPC8540ADS_defconfig b/configs/MPC8540ADS_defconfig
index 401a86dbdf..e3cb0d5e9a 100644
--- a/configs/MPC8540ADS_defconfig
+++ b/configs/MPC8540ADS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8540ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8541CDS_defconfig b/configs/MPC8541CDS_defconfig
index ddc3b5b8d3..1ea8800441 100644
--- a/configs/MPC8541CDS_defconfig
+++ b/configs/MPC8541CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8541CDS_legacy_defconfig b/configs/MPC8541CDS_legacy_defconfig
index a340c8bb55..ae529d1725 100644
--- a/configs/MPC8541CDS_legacy_defconfig
+++ b/configs/MPC8541CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8541CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
index 06569e288b..ecb05acbb6 100644
--- a/configs/MPC8544DS_defconfig
+++ b/configs/MPC8544DS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8544DS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index d038267d90..066eaf229b 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index a42d991dbb..ee400a38fd 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 3a730f9af8..b7334615f9 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8548CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8555CDS_defconfig b/configs/MPC8555CDS_defconfig
index 86db71c70a..da42112fab 100644
--- a/configs/MPC8555CDS_defconfig
+++ b/configs/MPC8555CDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8555CDS_legacy_defconfig b/configs/MPC8555CDS_legacy_defconfig
index 485e9870a0..fb148912b9 100644
--- a/configs/MPC8555CDS_legacy_defconfig
+++ b/configs/MPC8555CDS_legacy_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8555CDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LEGACY"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8560ADS_defconfig b/configs/MPC8560ADS_defconfig
index 19407b347c..67063c81da 100644
--- a/configs/MPC8560ADS_defconfig
+++ b/configs/MPC8560ADS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8560ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PING=y
diff --git a/configs/MPC8568MDS_defconfig b/configs/MPC8568MDS_defconfig
index 5ec3712467..2e7dcebd07 100644
--- a/configs/MPC8568MDS_defconfig
+++ b/configs/MPC8568MDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8568MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MII=y
diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig
index daacef7576..505a8536aa 100644
--- a/configs/MPC8569MDS_ATM_defconfig
+++ b/configs/MPC8569MDS_ATM_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="ATM"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig
index 26ab184b45..0f9cc2fb92 100644
--- a/configs/MPC8569MDS_defconfig
+++ b/configs/MPC8569MDS_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_MPC8569MDS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig
index 1720d9e6fc..8218ef688f 100644
--- a/configs/MPC8572DS_36BIT_defconfig
+++ b/configs/MPC8572DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig
index 63cf745ce7..6c65fbe7de 100644
--- a/configs/MPC8572DS_defconfig
+++ b/configs/MPC8572DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8610HPCD_defconfig b/configs/MPC8610HPCD_defconfig
index 6883249cb7..10607e80dc 100644
--- a/configs/MPC8610HPCD_defconfig
+++ b/configs/MPC8610HPCD_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8610HPCD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8641HPCN_36BIT_defconfig b/configs/MPC8641HPCN_36BIT_defconfig
index c85ddfe1c9..b90e6ea359 100644
--- a/configs/MPC8641HPCN_36BIT_defconfig
+++ b/configs/MPC8641HPCN_36BIT_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PHYS_64BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MPC8641HPCN_defconfig b/configs/MPC8641HPCN_defconfig
index d71369ece2..d8f74b31dc 100644
--- a/configs/MPC8641HPCN_defconfig
+++ b/configs/MPC8641HPCN_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_MPC8641HPCN=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index a9d5aae5a7..555944479b 100644
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -10,17 +10,6 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig
index 14db5ae02c..3d71bf50a7 100644
--- a/configs/MSI_Primo81_defconfig
+++ b/configs/MSI_Primo81_defconfig
@@ -13,19 +13,9 @@ CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
 CONFIG_VIDEO_LCD_SSD2828_TX_CLK=27
diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig
index cb9ca3baf8..d230a68c9f 100644
--- a/configs/Marsboard_A10_defconfig
+++ b/configs/Marsboard_A10_defconfig
@@ -1,23 +1,11 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig
index bae638fd49..b3f825e33f 100644
--- a/configs/Mele_A1000G_quad_defconfig
+++ b/configs/Mele_A1000G_quad_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mele-a1000g-quad"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig
index 931179909b..64f2c74213 100644
--- a/configs/Mele_A1000_defconfig
+++ b/configs/Mele_A1000_defconfig
@@ -1,24 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_VIDEO_VGA=y
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-a1000"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig
index 831578ee5e..eccf372caa 100644
--- a/configs/Mele_I7_defconfig
+++ b/configs/Mele_I7_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-i7"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig
index d628c7c293..d72dcc0311 100644
--- a/configs/Mele_M3_defconfig
+++ b/configs/Mele_M3_defconfig
@@ -10,19 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig
index 35df2258f2..0d1ba151e2 100644
--- a/configs/Mele_M5_defconfig
+++ b/configs/Mele_M5_defconfig
@@ -9,19 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-m5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,AHCI,STATUSLED=234"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig
index 8a4980e1c8..f0b4384239 100644
--- a/configs/Mele_M9_defconfig
+++ b/configs/Mele_M9_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-m9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DCDC1_VOLT=3300
 CONFIG_AXP_ALDO1_VOLT=3300
diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
index 842db29e55..198fda95fe 100644
--- a/configs/Merrii_A80_Optimus_defconfig
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -5,19 +5,8 @@ CONFIG_DRAM_CLK=360
 CONFIG_DRAM_ZQ=123
 CONFIG_SYS_CLK_FREQ=1008000000
 CONFIG_MMC0_CD_PIN="PH18"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/MigoR_defconfig b/configs/MigoR_defconfig
index 57b7db4d3b..129403c34a 100644
--- a/configs/MigoR_defconfig
+++ b/configs/MigoR_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MIGOR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig
index 102b96c071..f96757e263 100644
--- a/configs/Mini-X_defconfig
+++ b/configs/Mini-X_defconfig
@@ -1,24 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/MiniFAP_defconfig b/configs/MiniFAP_defconfig
index bad6a39003..39fdf6a93d 100644
--- a/configs/MiniFAP_defconfig
+++ b/configs/MiniFAP_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MINIFAP"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/O2D300_defconfig b/configs/O2D300_defconfig
index f7d7f00bf7..3b36d8fa34 100644
--- a/configs/O2D300_defconfig
+++ b/configs/O2D300_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D300=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2DNT2_RAMBOOT_defconfig b/configs/O2DNT2_RAMBOOT_defconfig
index 31e309fedb..977da33c68 100644
--- a/configs/O2DNT2_RAMBOOT_defconfig
+++ b/configs/O2DNT2_RAMBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x00100000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
diff --git a/configs/O2DNT2_defconfig b/configs/O2DNT2_defconfig
index eb65c22aea..32e475d531 100644
--- a/configs/O2DNT2_defconfig
+++ b/configs/O2DNT2_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2DNT2=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press password to stop\n"
diff --git a/configs/O2D_defconfig b/configs/O2D_defconfig
index 67a7757e7d..22e83577bd 100644
--- a/configs/O2D_defconfig
+++ b/configs/O2D_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2I_defconfig b/configs/O2I_defconfig
index 7a29872fa9..a1c2794c0d 100644
--- a/configs/O2I_defconfig
+++ b/configs/O2I_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2I=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M110_defconfig b/configs/O2MNT_O2M110_defconfig
index 4f35c2e8fc..f33496cfd1 100644
--- a/configs/O2MNT_O2M110_defconfig
+++ b/configs/O2MNT_O2M110_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M110\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M112_defconfig b/configs/O2MNT_O2M112_defconfig
index 77d18798dd..04a8fdda4b 100644
--- a/configs/O2MNT_O2M112_defconfig
+++ b/configs/O2MNT_O2M112_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M112\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_O2M113_defconfig b/configs/O2MNT_O2M113_defconfig
index 6d91a1153b..2e4b8abe95 100644
--- a/configs/O2MNT_O2M113_defconfig
+++ b/configs/O2MNT_O2M113_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="IFM_SENSOR_TYPE=\"O2M113\""
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O2MNT_defconfig b/configs/O2MNT_defconfig
index e135f93b2d..9176431e01 100644
--- a/configs/O2MNT_defconfig
+++ b/configs/O2MNT_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O2MNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/O3DNT_defconfig b/configs/O3DNT_defconfig
index b6bc88e638..55054ac757 100644
--- a/configs/O3DNT_defconfig
+++ b/configs/O3DNT_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_O3DNT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig
index 212f98cfa7..00c671b12c 100644
--- a/configs/Orangepi_defconfig
+++ b/configs/Orangepi_defconfig
@@ -11,19 +11,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig
index 148b4fa547..a8652554e4 100644
--- a/configs/Orangepi_mini_defconfig
+++ b/configs/Orangepi_mini_defconfig
@@ -13,19 +13,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-orangepi-mini"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
index af6a4be901..5e05795cbb 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index 5ed93a169a..5e12add6ce 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
index 2c05f6e181..b63475c634 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index 4dbff83c04..74168dabbd 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index f421b224e8..2e34a10a0a 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
index f0a74fdba6..d5bf9467c7 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 6bd7dcb655..aa08a595c6 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
index b8968a8457..a745bb9410 100644
--- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index 551b9db1ea..8ac7c11551 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
index 7d8ebfece1..808851a826 100644
--- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 6fd23ac04b..ca3ba080d3 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 1f29b11e9e..dff79c60c6 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
index 6da92e415e..800e7b9c23 100644
--- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index fa7cab84df..e1be2ebba0 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
index 860bc6a639..e8564f9f58 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 23d938bd30..425344b5bb 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
index 5bc446b585..dce2a1a92e 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index 7b83294b1b..883de6f423 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 234645eef4..381caad7b4 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
index 7adcca84e3..293a945569 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index c455059c9a..0c8ae441c9 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
index 45f54f7a0d..880be23ad9 100644
--- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 7d6de18ebe..d6f4f58f1f 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
index 629fbbb7da..a875553390 100644
--- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 8f44aee479..3e966315f2 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 37ebca3763..5adfa4940d 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
index 6d6edd1f4c..be7f0e28f4 100644
--- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index d21afae47e..f82850c863 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
index a0e44718f8..bb27831776 100644
--- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig
index d2095819f4..79a4282e04 100644
--- a/configs/P1020MBG-PC_36BIT_defconfig
+++ b/configs/P1020MBG-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig
index d07ed43aee..9b6370d794 100644
--- a/configs/P1020MBG-PC_SDCARD_defconfig
+++ b/configs/P1020MBG-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig
index 0fe87d1c42..5c5eb5ed5a 100644
--- a/configs/P1020MBG-PC_defconfig
+++ b/configs/P1020MBG-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020MBG"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 735c53f8cf..1c98b5503f 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 953552d68a..e5bff617f3 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index ec94e061e5..dda50fb590 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index 044e7393e1..b69370506a 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 3bd72f0749..3d4a746e07 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index a9a659c660..121ff7925a 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f01dbc3bb4..9dde9c7d05 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index 37e14da144..8ee1fa46bf 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 63faa06a46..a296fee4c6 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 255b8e221a..045216c915 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 61a635ab77..7ff3b741b1 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index f8e633aba8..32c504708a 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
index d6775d913b..6dfe195197 100644
--- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig
index 054e9fc76d..98f928524a 100644
--- a/configs/P1020UTM-PC_36BIT_defconfig
+++ b/configs/P1020UTM-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig
index b0553ef342..136e5ac820 100644
--- a/configs/P1020UTM-PC_SDCARD_defconfig
+++ b/configs/P1020UTM-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig
index 36f7366c5e..42f28cdfb3 100644
--- a/configs/P1020UTM-PC_defconfig
+++ b/configs/P1020UTM-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1020UTM"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig
index b24f8ec995..eeb232d7a2 100644
--- a/configs/P1021RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
index 8f618ae38e..d2f83fa2b4 100644
--- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
index 70e4d44419..09ba6eaecd 100644
--- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig
index e119befc39..7652d29ad8 100644
--- a/configs/P1021RDB-PC_36BIT_defconfig
+++ b/configs/P1021RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig
index 772a3133b9..a49dfca4e0 100644
--- a/configs/P1021RDB-PC_NAND_defconfig
+++ b/configs/P1021RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig
index 9206cc7b4a..c2d23b8254 100644
--- a/configs/P1021RDB-PC_SDCARD_defconfig
+++ b/configs/P1021RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig
index 85c03aa92e..facbf9efc7 100644
--- a/configs/P1021RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1021RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig
index ae78a8e91d..eebc69b7f6 100644
--- a/configs/P1021RDB-PC_defconfig
+++ b/configs/P1021RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1021RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig
index af98b8e57c..352305d8df 100644
--- a/configs/P1022DS_36BIT_NAND_defconfig
+++ b/configs/P1022DS_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig
index 0ea0201a11..68a6c11838 100644
--- a/configs/P1022DS_36BIT_SDCARD_defconfig
+++ b/configs/P1022DS_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig
index 4093449412..21300da457 100644
--- a/configs/P1022DS_36BIT_SPIFLASH_defconfig
+++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig
index 24e8678309..c63abc3d6a 100644
--- a/configs/P1022DS_36BIT_defconfig
+++ b/configs/P1022DS_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig
index cbc3d76391..6d90082236 100644
--- a/configs/P1022DS_NAND_defconfig
+++ b/configs/P1022DS_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig
index 8c36f58b7f..7643544694 100644
--- a/configs/P1022DS_SDCARD_defconfig
+++ b/configs/P1022DS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig
index 1c7b323229..2e96cb2806 100644
--- a/configs/P1022DS_SPIFLASH_defconfig
+++ b/configs/P1022DS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig
index b5dee335e9..679353e952 100644
--- a/configs/P1022DS_defconfig
+++ b/configs/P1022DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig
index bcc0aede64..d3731a87d2 100644
--- a/configs/P1024RDB_36BIT_defconfig
+++ b/configs/P1024RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig
index dc747089a5..2a53c57c12 100644
--- a/configs/P1024RDB_NAND_defconfig
+++ b/configs/P1024RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig
index a59ddde351..dc93a19d29 100644
--- a/configs/P1024RDB_SDCARD_defconfig
+++ b/configs/P1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig
index 9993593391..b41e590b1c 100644
--- a/configs/P1024RDB_SPIFLASH_defconfig
+++ b/configs/P1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig
index 8f723c6ff2..5541bf98e1 100644
--- a/configs/P1024RDB_defconfig
+++ b/configs/P1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1024RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig
index 5285f79adf..98644861b5 100644
--- a/configs/P1025RDB_36BIT_defconfig
+++ b/configs/P1025RDB_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig
index ec6038c520..8a3b80497a 100644
--- a/configs/P1025RDB_NAND_defconfig
+++ b/configs/P1025RDB_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig
index 6ba76fa69f..eed18337cf 100644
--- a/configs/P1025RDB_SDCARD_defconfig
+++ b/configs/P1025RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig
index 86b9cd7d58..89daf1cc88 100644
--- a/configs/P1025RDB_SPIFLASH_defconfig
+++ b/configs/P1025RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig
index f7ce9b69de..746e150b66 100644
--- a/configs/P1025RDB_defconfig
+++ b/configs/P1025RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P1025RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 21d98e3afa..2421a7371d 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index ce42c822c7..fce023ba5b 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index c8f86e2b58..a3162649cc 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index a6a01e8fc8..0bc2d1a2b5 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 0f10e08bbc..cf1ccbfe5e 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -8,6 +8,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 8649e52008..e8b6e2a392 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 1764f2c01a..bfbaea1b81 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index b9610e4389..82e7b4b2c2 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="P2020RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index d4b1c557f0..66f6ec4e3e 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index a36e73193e..5901458094 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig
index 4d4051176d..b7f3a0d429 100644
--- a/configs/P2041RDB_SECURE_BOOT_defconfig
+++ b/configs/P2041RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index c2dbd98886..7f07d2d9c6 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
index 3dbf5a3107..a767520644 100644
--- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index aea98c63a4..17e2ad5ee8 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
index d5b1c12add..c2790b22d5 100644
--- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index dfe0e1754e..1c863dee7c 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index a8e21319a3..028b9f077a 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig
index 13e2fed459..d1b3f7001d 100644
--- a/configs/P3041DS_SECURE_BOOT_defconfig
+++ b/configs/P3041DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 901c373d40..acce0840a4 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
index f9285a8a69..d20defab5e 100644
--- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index d648d975aa..641f2635ab 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index aaa97f74cc..deba469617 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig
index 437e05a810..68c910ee0f 100644
--- a/configs/P4080DS_SECURE_BOOT_defconfig
+++ b/configs/P4080DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index a3f0d85316..130e2f4848 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
index 7059c81aa4..b47fc08a4a 100644
--- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 752a6c6389..f9a7ed3015 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
index 2ecb0b864b..ae9843c66e 100644
--- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig
index c26e72987f..3edbee003d 100644
--- a/configs/P5020DS_NAND_defconfig
+++ b/configs/P5020DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig
index acc617ece6..b7a2f1d547 100644
--- a/configs/P5020DS_SDCARD_defconfig
+++ b/configs/P5020DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig
index 24d4f17366..9523a07ddc 100644
--- a/configs/P5020DS_SECURE_BOOT_defconfig
+++ b/configs/P5020DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig
index 3e97ee0084..93d92d312d 100644
--- a/configs/P5020DS_SPIFLASH_defconfig
+++ b/configs/P5020DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
index f381326a58..b5906514f2 100644
--- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig
index d7145aee5a..8b8e557821 100644
--- a/configs/P5020DS_defconfig
+++ b/configs/P5020DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
index 0495c4de07..e45ed753f3 100644
--- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 9be5ff1748..73b2216c82 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index 66751641fb..72923ca4e2 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig
index 552d93a645..21a7ba542f 100644
--- a/configs/P5040DS_SECURE_BOOT_defconfig
+++ b/configs/P5040DS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 2caec57f12..0722667d00 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 07e67c893e..9c3a2ce9d7 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig
index ae957320e5..53fdfad6fe 100644
--- a/configs/PATI_defconfig
+++ b/configs/PATI_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_5xx=y
 CONFIG_TARGET_PATI=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="pati=> "
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig
index fe887396da..dee793b3e6 100644
--- a/configs/PIP405_defconfig
+++ b/configs/PIP405_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PIP405=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/PLU405_defconfig b/configs/PLU405_defconfig
index c1795a4ae5..a0e8411705 100644
--- a/configs/PLU405_defconfig
+++ b/configs/PLU405_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PLU405=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/PMC405DE_defconfig b/configs/PMC405DE_defconfig
index 8f60d87311..cdb82d6448 100644
--- a/configs/PMC405DE_defconfig
+++ b/configs/PMC405DE_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC405DE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/PMC440_defconfig b/configs/PMC440_defconfig
index 4d060ab696..704cd36bce 100644
--- a/configs/PMC440_defconfig
+++ b/configs/PMC440_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_PMC440=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig
index 4136841a2c..ae1f1e83aa 100644
--- a/configs/Sinlinx_SinA31s_defconfig
+++ b/configs/Sinlinx_SinA31s_defconfig
@@ -12,19 +12,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sina31s"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig
index 03cef97c06..013c35e1a8 100644
--- a/configs/Sinlinx_SinA33_defconfig
+++ b/configs/Sinlinx_SinA33_defconfig
@@ -6,16 +6,6 @@ CONFIG_DRAM_ZQ=15291
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-sinlinx-sina33"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig
index dc781dbd12..181e1e29da 100644
--- a/configs/Sinovoip_BPI_M2_defconfig
+++ b/configs/Sinovoip_BPI_M2_defconfig
@@ -8,19 +8,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_AXP_ALDO2_VOLT=1800
diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig
index 13dbb98689..77b0525e11 100644
--- a/configs/Sinovoip_BPI_M3_defconfig
+++ b/configs/Sinovoip_BPI_M3_defconfig
@@ -15,20 +15,11 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-sinovoip-bpi-m3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPD(25)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DCDC5_VOLT=1200
 CONFIG_AXP_DLDO3_VOLT=2500
+CONFIG_AXP_SW_ON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig
index 9a916c96fa..32df4e5875 100644
--- a/configs/T1023RDB_NAND_defconfig
+++ b/configs/T1023RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig
index 2c41d03d79..069f5d36bc 100644
--- a/configs/T1023RDB_SDCARD_defconfig
+++ b/configs/T1023RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
index e3cf48d835..984e60b63a 100644
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ b/configs/T1023RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig
index 5ce9ed991e..109cade718 100644
--- a/configs/T1023RDB_SPIFLASH_defconfig
+++ b/configs/T1023RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig
index 44c9584655..de0d50c241 100644
--- a/configs/T1023RDB_defconfig
+++ b/configs/T1023RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
index 6c4505fcf7..6253b05229 100644
--- a/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_DDR4_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_DDR4_defconfig b/configs/T1024QDS_DDR4_defconfig
index 0af7eab817..71ff16606d 100644
--- a/configs/T1024QDS_DDR4_defconfig
+++ b/configs/T1024QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig
index efdcbeb48c..04204fb2b4 100644
--- a/configs/T1024QDS_NAND_defconfig
+++ b/configs/T1024QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig
index 12a03766fc..80dd6df6e6 100644
--- a/configs/T1024QDS_SDCARD_defconfig
+++ b/configs/T1024QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig
index 84da5830ac..21f7ed40a9 100644
--- a/configs/T1024QDS_SECURE_BOOT_defconfig
+++ b/configs/T1024QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig
index 03d009f406..a869853745 100644
--- a/configs/T1024QDS_SPIFLASH_defconfig
+++ b/configs/T1024QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig
index a70963fbd3..c824674afa 100644
--- a/configs/T1024QDS_defconfig
+++ b/configs/T1024QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index a012f3d80b..ce0ba29f6c 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index d7cce8b8a6..21707f64a7 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index ceae6cf171..557897605d 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index 1359aad17c..6a9df4804d 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 7ffacd420c..d54b83543d 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
index a07a59aed3..9295c61ca2 100644
--- a/configs/T1040D4RDB_NAND_defconfig
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
index e4c095e8d2..de3aef0ea1 100644
--- a/configs/T1040D4RDB_SDCARD_defconfig
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
index a2c1495316..fe7b9d18e9 100644
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
index 9a78aa9d77..b762e1914c 100644
--- a/configs/T1040D4RDB_SPIFLASH_defconfig
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
index f2415d9e35..4147f385aa 100644
--- a/configs/T1040D4RDB_defconfig
+++ b/configs/T1040D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_DDR4_defconfig b/configs/T1040QDS_DDR4_defconfig
index df9e295127..11ff5f085e 100644
--- a/configs/T1040QDS_DDR4_defconfig
+++ b/configs/T1040QDS_DDR4_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig
index 7f889c7ac0..33c6772c8c 100644
--- a/configs/T1040QDS_SECURE_BOOT_defconfig
+++ b/configs/T1040QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig
index f93f0b9a1e..fd512dbf9f 100644
--- a/configs/T1040QDS_defconfig
+++ b/configs/T1040QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig
index 023dc37d3d..8f99f8fda8 100644
--- a/configs/T1040RDB_NAND_defconfig
+++ b/configs/T1040RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig
index bacb060c20..899339a70f 100644
--- a/configs/T1040RDB_SDCARD_defconfig
+++ b/configs/T1040RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
index 9d6d9fb41e..4e5682c5dc 100644
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ b/configs/T1040RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig
index b5a050cae1..a20259556c 100644
--- a/configs/T1040RDB_SPIFLASH_defconfig
+++ b/configs/T1040RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig
index a50f177487..e2a8321b5f 100644
--- a/configs/T1040RDB_defconfig
+++ b/configs/T1040RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index f70d5ce27f..17b6b83a96 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 4f21813051..097bb8a9e0 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index 07bdcf6800..fa0e2a6329 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index a49d32d987..6dd0cdbb43 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 23f83e6720..60fc267d2e 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig
index 1935dad2b5..106b2f05fd 100644
--- a/configs/T1042RDB_PI_NAND_defconfig
+++ b/configs/T1042RDB_PI_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig
index f093e92b61..3dd11a5d28 100644
--- a/configs/T1042RDB_PI_SDCARD_defconfig
+++ b/configs/T1042RDB_PI_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig
index f7126e5856..5af19870b3 100644
--- a/configs/T1042RDB_PI_SPIFLASH_defconfig
+++ b/configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig
index f0aed08eb7..2c72833ee8 100644
--- a/configs/T1042RDB_PI_defconfig
+++ b/configs/T1042RDB_PI_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
index 0057e22d7e..c7777140a1 100644
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
index 8905b6c00c..bb1bee7504 100644
--- a/configs/T1042RDB_defconfig
+++ b/configs/T1042RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 2459eba3f7..e4aec61e9d 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index b937af4a83..d314307bcf 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index 049819e4b7..5e5635807d 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 8634477609..cf15e001d5 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index 40c871e7c4..db6e7fb2a2 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index 795a3f0028..d5f1de54a2 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index c6e07104d6..673655c131 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index 51caeeb60d..32c0a571f8 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig
index f4190af51b..af64f230aa 100644
--- a/configs/T2080RDB_SECURE_BOOT_defconfig
+++ b/configs/T2080RDB_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 9d4821dafb..75a56d564a 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
index 0a15e05f81..b1cacf763d 100644
--- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 955b394f9e..1161f0820b 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig
index 0b0e1204e1..1e196a03b0 100644
--- a/configs/T2081QDS_NAND_defconfig
+++ b/configs/T2081QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig
index bffca4001c..85029cf4ac 100644
--- a/configs/T2081QDS_SDCARD_defconfig
+++ b/configs/T2081QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig
index fc8f1f5035..66350d0af7 100644
--- a/configs/T2081QDS_SPIFLASH_defconfig
+++ b/configs/T2081QDS_SPIFLASH_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
index ed075eb390..88702bccfe 100644
--- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig
index 844fe10653..d8fadec534 100644
--- a/configs/T2081QDS_defconfig
+++ b/configs/T2081QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig
index 92b0391357..4e7dbe55fa 100644
--- a/configs/T4160QDS_NAND_defconfig
+++ b/configs/T4160QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig
index 2a30e11c2d..d70417999f 100644
--- a/configs/T4160QDS_SDCARD_defconfig
+++ b/configs/T4160QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig
index 37aac2a792..560fce8c85 100644
--- a/configs/T4160QDS_SECURE_BOOT_defconfig
+++ b/configs/T4160QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig
index 3b13a34368..a9cd51cd64 100644
--- a/configs/T4160QDS_defconfig
+++ b/configs/T4160QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig
index 3523fe16db..9adcc21183 100644
--- a/configs/T4160RDB_defconfig
+++ b/configs/T4160RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig
index c2a16fd1f3..7ce7ff0da9 100644
--- a/configs/T4240QDS_NAND_defconfig
+++ b/configs/T4240QDS_NAND_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig
index 3ec6c75c01..9fd17a9149 100644
--- a/configs/T4240QDS_SDCARD_defconfig
+++ b/configs/T4240QDS_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig
index 18c8e67624..2d6b47f771 100644
--- a/configs/T4240QDS_SECURE_BOOT_defconfig
+++ b/configs/T4240QDS_SECURE_BOOT_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
index c590410997..193d54c24d 100644
--- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_GREPENV=y
diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig
index afb665dac8..4a241849d6 100644
--- a/configs/T4240QDS_defconfig
+++ b/configs/T4240QDS_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 85fd13b4e9..27093ec356 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 21e22be06e..c14f9b8e6c 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
diff --git a/configs/TQM5200S_HIGHBOOT_defconfig b/configs/TQM5200S_HIGHBOOT_defconfig
index 7adc71cc2b..6a14703465 100644
--- a/configs/TQM5200S_HIGHBOOT_defconfig
+++ b/configs/TQM5200S_HIGHBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200S_defconfig b/configs/TQM5200S_defconfig
index f09895417e..0d8f096938 100644
--- a/configs/TQM5200S_defconfig
+++ b/configs/TQM5200S_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,TQM5200S"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_B_HIGHBOOT_defconfig b/configs/TQM5200_B_HIGHBOOT_defconfig
index 70eb3834f3..9c310aa464 100644
--- a/configs/TQM5200_B_HIGHBOOT_defconfig
+++ b/configs/TQM5200_B_HIGHBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B,SYS_TEXT_BASE=0xFFF00000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_B_defconfig b/configs/TQM5200_B_defconfig
index 6734495f02..da88fcc8c3 100644
--- a/configs/TQM5200_B_defconfig
+++ b/configs/TQM5200_B_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="TQM5200_B"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_STK100_defconfig b/configs/TQM5200_STK100_defconfig
index d0adb77b9d..9926fd7a90 100644
--- a/configs/TQM5200_STK100_defconfig
+++ b/configs/TQM5200_STK100_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="STK52XX_REV100"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM5200_defconfig b/configs/TQM5200_defconfig
index 445636102c..fe68631018 100644
--- a/configs/TQM5200_defconfig
+++ b/configs/TQM5200_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TQM823L_LCD_defconfig b/configs/TQM823L_LCD_defconfig
index 9bf21f5742..38f511967c 100644
--- a/configs/TQM823L_LCD_defconfig
+++ b/configs/TQM823L_LCD_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,NEC_NL6448BC20"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM823L_defconfig b/configs/TQM823L_defconfig
index 9f3218b783..3bc293410a 100644
--- a/configs/TQM823L_defconfig
+++ b/configs/TQM823L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM823M_defconfig b/configs/TQM823M_defconfig
index 9a0ba9d0df..9d40a1ff6b 100644
--- a/configs/TQM823M_defconfig
+++ b/configs/TQM823M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM823M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig
index 00dd80d746..b56d780bb4 100644
--- a/configs/TQM834x_defconfig
+++ b/configs/TQM834x_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_TQM834X=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/TQM850L_defconfig b/configs/TQM850L_defconfig
index 088ed6d22e..8427f5872b 100644
--- a/configs/TQM850L_defconfig
+++ b/configs/TQM850L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM850M_defconfig b/configs/TQM850M_defconfig
index ab3c44b3b0..1c3f4240a8 100644
--- a/configs/TQM850M_defconfig
+++ b/configs/TQM850M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM850M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM855L_defconfig b/configs/TQM855L_defconfig
index 6ece0683bc..0234813995 100644
--- a/configs/TQM855L_defconfig
+++ b/configs/TQM855L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM855M_defconfig b/configs/TQM855M_defconfig
index 9940f96e5b..15541e5cfa 100644
--- a/configs/TQM855M_defconfig
+++ b/configs/TQM855M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM855M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM860L_defconfig b/configs/TQM860L_defconfig
index 4aec4ff284..becd4e1e2f 100644
--- a/configs/TQM860L_defconfig
+++ b/configs/TQM860L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM860M_defconfig b/configs/TQM860M_defconfig
index 12b090aef9..3b27e7f89b 100644
--- a/configs/TQM860M_defconfig
+++ b/configs/TQM860M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM860M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM862L_defconfig b/configs/TQM862L_defconfig
index 41737a39f8..36e2433713 100644
--- a/configs/TQM862L_defconfig
+++ b/configs/TQM862L_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862L=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM862M_defconfig b/configs/TQM862M_defconfig
index 642dd023cb..84d2cb2b96 100644
--- a/configs/TQM862M_defconfig
+++ b/configs/TQM862M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM862M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM866M_defconfig b/configs/TQM866M_defconfig
index 3d0bf8c9e7..ddde240b4c 100644
--- a/configs/TQM866M_defconfig
+++ b/configs/TQM866M_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM866M=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TQM885D_defconfig b/configs/TQM885D_defconfig
index 2238cdd752..92b34f646b 100644
--- a/configs/TQM885D_defconfig
+++ b/configs/TQM885D_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_8xx=y
 CONFIG_TARGET_TQM885D=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/TTTech_defconfig b/configs/TTTech_defconfig
index df4efa40c4..e5458480d0 100644
--- a/configs/TTTech_defconfig
+++ b/configs/TTTech_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ104V7DS01"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig
index 8d2f2e6ef3..ae8feda701 100644
--- a/configs/TWR-P1025_defconfig
+++ b/configs/TWR-P1025_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig
index 948107c829..d36a5dccd0 100644
--- a/configs/UTOO_P66_defconfig
+++ b/configs/UTOO_P66_defconfig
@@ -20,19 +20,8 @@ CONFIG_VIDEO_LCD_TL059WV5C0=y
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/VCMA9_defconfig b/configs/VCMA9_defconfig
index 4c2df57eea..550e6b8431 100644
--- a/configs/VCMA9_defconfig
+++ b/configs/VCMA9_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_VCMA9=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="VCMA9 # "
 CONFIG_CMD_I2C=y
diff --git a/configs/VOM405_defconfig b/configs/VOM405_defconfig
index 8fb023a863..800731b18e 100644
--- a/configs/VOM405_defconfig
+++ b/configs/VOM405_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_VOM405=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig
index d754ccdf3f..5f3d624292 100644
--- a/configs/Wexler_TAB7200_defconfig
+++ b/configs/Wexler_TAB7200_defconfig
@@ -13,19 +13,8 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wexler-tab7200"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig
index 4a7dbdbdac..bfc8cba7d3 100644
--- a/configs/Wits_Pro_A20_DKT_defconfig
+++ b/configs/Wits_Pro_A20_DKT_defconfig
@@ -12,19 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-wits-pro-a20-dkt"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,AHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig
index 0b40b83843..fc43cc5fb1 100644
--- a/configs/Wobo_i5_defconfig
+++ b/configs/Wobo_i5_defconfig
@@ -7,18 +7,7 @@ CONFIG_USB1_VBUS_PIN="PG12"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-wobo-i5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig
index fab74f4cc2..65c1d8e28a 100644
--- a/configs/Yones_Toptech_BD1078_defconfig
+++ b/configs/Yones_Toptech_BD1078_defconfig
@@ -19,18 +19,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig
index 71f01dbb21..958104e750 100644
--- a/configs/Yones_Toptech_BS1078_V2_defconfig
+++ b/configs/Yones_Toptech_BS1078_V2_defconfig
@@ -16,18 +16,8 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-yones-toptech-bs1078-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/a3m071_defconfig b/configs/a3m071_defconfig
index 97e4fc5e22..c62018369f 100644
--- a/configs/a3m071_defconfig
+++ b/configs/a3m071_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_A3M071=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/a4m2k_defconfig b/configs/a4m2k_defconfig
index fc344c5caa..61f7da7e7f 100644
--- a/configs/a4m2k_defconfig
+++ b/configs/a4m2k_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="A4M2K"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_LOOPW=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/acadia_defconfig b/configs/acadia_defconfig
index 31889fa759..24d802eb27 100644
--- a/configs/acadia_defconfig
+++ b/configs/acadia_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ACADIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 6daefcc547..0def407446 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -1,5 +1,6 @@
 CONFIG_NDS32=y
 CONFIG_TARGET_ADP_AG101P=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="NDS32 # "
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index bfa243fb24..661d544545 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_ALT=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index 62f26b5ec7..3a1e5a47da 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -1,15 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_AM335X_EVM=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
-CONFIG_AUTOBOOT_DELAY_STR="d"
-CONFIG_AUTOBOOT_STOP_STR=" "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
@@ -30,9 +28,15 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_GADGET=y
@@ -41,4 +45,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_RSA=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am335x_gp_evm_defconfig b/configs/am335x_gp_evm_defconfig
deleted file mode 100644
index d7f126e503..0000000000
--- a/configs/am335x_gp_evm_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_AM335X_EVM=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_ETH=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_RSA=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
new file mode 100644
index 0000000000..2c7091b584
--- /dev/null
+++ b/configs/am335x_shc_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
new file mode 100644
index 0000000000..ffda4d2ce7
--- /dev/null
+++ b/configs/am335x_shc_ict_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_ICT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
new file mode 100644
index 0000000000..54558b68a5
--- /dev/null
+++ b/configs/am335x_shc_netboot_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_NETBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_prompt_defconfig b/configs/am335x_shc_prompt_defconfig
new file mode 100644
index 0000000000..a415ab471f
--- /dev/null
+++ b/configs/am335x_shc_prompt_defconfig
@@ -0,0 +1,19 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
new file mode 100644
index 0000000000..944256fe9c
--- /dev/null
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_SDBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am335x_shc_sdboot_prompt_defconfig b/configs/am335x_shc_sdboot_prompt_defconfig
new file mode 100644
index 0000000000..2767012429
--- /dev/null
+++ b/configs/am335x_shc_sdboot_prompt_defconfig
@@ -0,0 +1,21 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_SHC=y
+CONFIG_SHC_SDBOOT=y
+CONFIG_SERIES=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Enter 'shc' to enter prompt (times out) %d \nEnter 'noautoboot' to enter prompt without timeout\n"
+CONFIG_AUTOBOOT_DELAY_STR="shc"
+CONFIG_AUTOBOOT_STOP_STR="noautoboot"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig
index a8b8465536..6d1dcde1be 100644
--- a/configs/am3517_crane_defconfig
+++ b/configs/am3517_crane_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_AM3517_CRANE=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_CRANE # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index d400c35c72..b4aa3c63cd 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_AM3517_EVM=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="NAND"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="AM3517_EVM # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/am437x_gp_evm_defconfig b/configs/am437x_hs_evm_defconfig
index 03b02ac9fe..95b28fb9c2 100644
--- a/configs/am437x_gp_evm_defconfig
+++ b/configs/am437x_hs_evm_defconfig
@@ -1,5 +1,8 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40302ae0
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
@@ -38,6 +41,8 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
deleted file mode 100644
index 48ec91f4f1..0000000000
--- a/configs/am437x_sk_evm_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_AM43XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="am437x-sk-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DMA=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0403
-CONFIG_G_DNL_PRODUCT_NUM=0xbd00
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index a6ae01150a..cb3de11808 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -1,7 +1,15 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND"
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -23,12 +31,19 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
@@ -38,4 +53,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am43xx_evm_ethboot_defconfig b/configs/am43xx_evm_ethboot_defconfig
index 662556a0c5..9cdae19b99 100644
--- a/configs/am43xx_evm_ethboot_defconfig
+++ b/configs/am43xx_evm_ethboot_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_ETH_SUPPORT"
@@ -28,6 +29,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 00fa6be676..7b345adba9 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x30000000
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -27,6 +29,8 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index e3d6b570f8..6b53eba209 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -1,7 +1,16 @@
 CONFIG_ARM=y
+CONFIG_AM43XX=y
 CONFIG_TARGET_AM43XX_EVM=y
+CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
 CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND,SPL_USB_HOST_SUPPORT"
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -23,11 +32,19 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
@@ -37,4 +54,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0403
 CONFIG_G_DNL_PRODUCT_NUM=0xbd00
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 8fc3ebb8eb..b63ff89da2 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -32,3 +33,6 @@ CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig
index 47d103beef..1cf82d293e 100644
--- a/configs/am57xx_evm_nodt_defconfig
+++ b/configs/am57xx_evm_nodt_defconfig
@@ -22,4 +22,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_qspiboot_defconfig b/configs/am57xx_hs_evm_defconfig
index 8ebfe49668..aa459a1bed 100644
--- a/configs/dra7xx_evm_qspiboot_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -1,21 +1,23 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_TARGET_BEAGLE_X15=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
@@ -26,18 +28,12 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
 CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig
index 7604e2ee16..fbd63e97a8 100644
--- a/configs/ap121_defconfig
+++ b/configs/ap121_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SPI=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_ARCH_ATH79=y
 CONFIG_DEFAULT_DEVICE_TREE="ap121"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="ap121 # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,8 +20,9 @@ CONFIG_SYS_PROMPT="ap121 # "
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_NET is not set
-# CONFIG_CMD_NFS is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ATMEL=y
@@ -33,6 +35,8 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_AR933X_PINCTRL=y
@@ -43,5 +47,3 @@ CONFIG_DEBUG_UART_CLOCK=25000000
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_AR933X_UART=y
 CONFIG_ATH79_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig
index 1aa6e5d7ab..15fe36fca4 100644
--- a/configs/ap143_defconfig
+++ b/configs/ap143_defconfig
@@ -6,6 +6,7 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_ARCH_ATH79=y
 CONFIG_TARGET_AP143=y
 CONFIG_DEFAULT_DEVICE_TREE="ap143"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="ap143 # "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -43,5 +44,3 @@ CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_SYS_NS16550=y
 CONFIG_ATH79_SPI=y
-CONFIG_USE_PRIVATE_LIBGCC=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig
index 51920329c3..51a48de877 100644
--- a/configs/ap325rxa_defconfig
+++ b/configs/ap325rxa_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_AP325RXA=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/ap_sh4a_4a_defconfig b/configs/ap_sh4a_4a_defconfig
index 77a0aa5120..73e6f04a31 100644
--- a/configs/ap_sh4a_4a_defconfig
+++ b/configs/ap_sh4a_4a_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_AP_SH4A_4A=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 40a65d21e6..17e8595bb2 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -38,4 +38,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/apf27_defconfig b/configs/apf27_defconfig
index 88912e50af..a175274b24 100644
--- a/configs/apf27_defconfig
+++ b/configs/apf27_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_APF27=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="BIOS> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/arcangel4-be_defconfig b/configs/arcangel4-be_defconfig
index 4c6fcb02e2..c0c2e4be90 100644
--- a/configs/arcangel4-be_defconfig
+++ b/configs/arcangel4-be_defconfig
@@ -5,6 +5,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=70000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/arcangel4_defconfig b/configs/arcangel4_defconfig
index 2157e0cc33..efa55d0e99 100644
--- a/configs/arcangel4_defconfig
+++ b/configs/arcangel4_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=70000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="arcangel4"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="arcangel4# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/arches_defconfig b/configs/arches_defconfig
index e05a64c01e..d97715b4b5 100644
--- a/configs/arches_defconfig
+++ b/configs/arches_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_ARCHES=y
 CONFIG_DEFAULT_DEVICE_TREE="arches"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/aria_defconfig b/configs/aria_defconfig
index fb3257b3ae..14919e59fe 100644
--- a/configs/aria_defconfig
+++ b/configs/aria_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_ARIA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 1224da490a..9bae3c3efa 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_ARMADILLO_800EVA=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig
index 0cd529ee88..a026fd6104 100644
--- a/configs/arndale_defconfig
+++ b/configs/arndale_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_ARNDALE=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale"
diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig
index 4f5df351fc..9ac66570cd 100644
--- a/configs/aspenite_defconfig
+++ b/configs/aspenite_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ASPENITE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_I2C=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index bea73a5a45..f1303b3ae0 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 8012531175..8b00ee266e 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91RM9200EK=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index d8ec7f1c99..5a369bb0c1 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index eb17f91332..b465395914 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig
index 26ffd97e64..a30c40bfe1 100644
--- a/configs/at91sam9260ek_nandflash_defconfig
+++ b/configs/at91sam9260ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 4e8dfa1943..4406e58bb5 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index c5684f2e34..2d599156e1 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig
index 0fba31434b..45bc42769d 100644
--- a/configs/at91sam9261ek_nandflash_defconfig
+++ b/configs/at91sam9261ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index b09395f6ff..c94e7a4312 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index b09395f6ff..c94e7a4312 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index dd46a686c6..05c3f3dd9e 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 25b9a1710c..eb20eba841 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 3cdce9b80f..aed72da76b 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index 9ff65b514d..f829a18306 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 76c3b15361..a4b9719d9c 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig
index 7438b86d1f..199b5bbb1b 100644
--- a/configs/at91sam9g10ek_nandflash_defconfig
+++ b/configs/at91sam9g10ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 0cded82d60..bb176a095d 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index ddfce140aa..7287860c63 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 8ce99ee110..ffc3a95312 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 9ed2b84a70..9069f30969 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig
index f8f6afba2f..eaaa6ae13b 100644
--- a/configs/at91sam9g20ek_nandflash_defconfig
+++ b/configs/at91sam9g20ek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index c931af2b5b..5452afd85c 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 4aeca480d0..011fdadc86 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index 2c4a81ab8e..e61f3b9076 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 726d8114f9..62efd6ea91 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index d0cff22198..6a54f033e6 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index dda3edfbee..69be1d20d6 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index c300438920..c49bf18192 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 6b033fb96e..142122ed09 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index 56aa2a0080..85ed41c863 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index db501c5879..cecd41651b 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 7f0b1a42bc..002c833cec 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index f7a4d16b6b..cefe859cfa 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 0ded2ab414..77c65b2550 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 7995419ef6..9eaf146d8e 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig
index c859cb6e7f..b17b9a5a01 100644
--- a/configs/at91sam9xeek_nandflash_defconfig
+++ b/configs/at91sam9xeek_nandflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index ba43e3501b..0e0eadf684 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 07a6a1855e..10e802d655 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=750000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 01a51432ac..96a3de63c8 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=50000000
 CONFIG_SYS_TEXT_BASE=0x81000000
 CONFIG_DEFAULT_DEVICE_TREE="axs10x"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="AXS# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig
index b61b15cb57..6da4b694a2 100644
--- a/configs/ba10_tv_box_defconfig
+++ b/configs/ba10_tv_box_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=384
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
@@ -10,19 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/bamboo_defconfig b/configs/bamboo_defconfig
index b0f6bb34e2..e1f1f3d582 100644
--- a/configs/bamboo_defconfig
+++ b/configs/bamboo_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BAMBOO=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index ce1f5198ff..9f1d7fbca9 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -9,6 +9,8 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_VGA_BIOS_ADDR=0xfffa0000
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig
index bfd519ec13..71a52a12ad 100644
--- a/configs/bcm28155_ap_defconfig
+++ b/configs/bcm28155_ap_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig
index 19111226d5..97fe622f91 100644
--- a/configs/bcm28155_w1d_defconfig
+++ b/configs/bcm28155_w1d_defconfig
@@ -1,4 +1,5 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_TARGET_BCM28155_AP=y
 CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index b9323c2338..8557c02d4e 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/bf525-ucr2_defconfig b/configs/bf525-ucr2_defconfig
index 84f229fc14..68d2f48b45 100644
--- a/configs/bf525-ucr2_defconfig
+++ b/configs/bf525-ucr2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF525_UCR2=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/bf526-ezbrd_defconfig b/configs/bf526-ezbrd_defconfig
index 85c2a6be19..ea4f8e4baf 100644
--- a/configs/bf526-ezbrd_defconfig
+++ b/configs/bf526-ezbrd_defconfig
@@ -17,3 +17,4 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_USB=y
diff --git a/configs/bf527-ezkit-v2_defconfig b/configs/bf527-ezkit-v2_defconfig
index ff797f8786..faac28d39c 100644
--- a/configs/bf527-ezkit-v2_defconfig
+++ b/configs/bf527-ezkit-v2_defconfig
@@ -17,4 +17,5 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bf527-ezkit_defconfig b/configs/bf527-ezkit_defconfig
index eff2a1263e..d69b14622e 100644
--- a/configs/bf527-ezkit_defconfig
+++ b/configs/bf527-ezkit_defconfig
@@ -17,3 +17,4 @@ CONFIG_NET_RANDOM_ETHADDR=y
 # CONFIG_NET_TFTP_VARS is not set
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
diff --git a/configs/bf537-minotaur_defconfig b/configs/bf537-minotaur_defconfig
index 7c17cbb2ac..fea8c3240f 100644
--- a/configs/bf537-minotaur_defconfig
+++ b/configs/bf537-minotaur_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_MINOTAUR=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="minotaur> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bf537-srv1_defconfig b/configs/bf537-srv1_defconfig
index f8288d9d19..dc88c44fa5 100644
--- a/configs/bf537-srv1_defconfig
+++ b/configs/bf537-srv1_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BF537_SRV1=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="srv1> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/bf548-ezkit_defconfig b/configs/bf548-ezkit_defconfig
index 6d398ac57d..e4fa136451 100644
--- a/configs/bf548-ezkit_defconfig
+++ b/configs/bf548-ezkit_defconfig
@@ -16,5 +16,6 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_USB=y
 CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
 CONFIG_LIB_RAND=y
diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig
index 709dfab999..b3a13c63e6 100644
--- a/configs/bg0900_defconfig
+++ b/configs/bg0900_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_BG0900=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/blackstamp_defconfig b/configs/blackstamp_defconfig
index 679aee167c..7aa5a52f9b 100644
--- a/configs/blackstamp_defconfig
+++ b/configs/blackstamp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKSTAMP=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/blackvme_defconfig b/configs/blackvme_defconfig
index 808cc3de0f..7c3eb9dc6b 100644
--- a/configs/blackvme_defconfig
+++ b/configs/blackvme_defconfig
@@ -1,5 +1,6 @@
 CONFIG_BLACKFIN=y
 CONFIG_TARGET_BLACKVME=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/bubinga_defconfig b/configs/bubinga_defconfig
index d570d41e23..9bfe828593 100644
--- a/configs/bubinga_defconfig
+++ b/configs/bubinga_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_BUBINGA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig
index 2eefd15ca6..c2e454a658 100644
--- a/configs/caddy2_defconfig
+++ b/configs/caddy2_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="CADDY2"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/cam5200_defconfig b/configs/cam5200_defconfig
index 722458883c..f2da039223 100644
--- a/configs/cam5200_defconfig
+++ b/configs/cam5200_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/cam5200_niosflash_defconfig b/configs/cam5200_niosflash_defconfig
index 00d8045485..d04ac552a4 100644
--- a/configs/cam5200_niosflash_defconfig
+++ b/configs/cam5200_niosflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/canmb_defconfig b/configs/canmb_defconfig
index 8d3b4764de..f1e3265ec5 100644
--- a/configs/canmb_defconfig
+++ b/configs/canmb_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CANMB=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig
index aac031b6f4..fe9fbd041f 100644
--- a/configs/canyonlands_defconfig
+++ b/configs/canyonlands_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_CANYONLANDS=y
 CONFIG_DEFAULT_DEVICE_TREE="canyonlands"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig
index 979b6934ac..ee8e793926 100644
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/charon_defconfig b/configs/charon_defconfig
index ea50729efd..ae9b62a711 100644
--- a/configs/charon_defconfig
+++ b/configs/charon_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CHARON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index 25ead92778..6bebcee882 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -47,7 +47,7 @@ CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
@@ -73,7 +73,6 @@ CONFIG_ROCKCHIP_SPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 0fde640deb..3bf538891b 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_CLEARFOG=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/cm5200_defconfig b/configs/cm5200_defconfig
index c7df40022a..2a67b43ce8 100644
--- a/configs/cm5200_defconfig
+++ b/configs/cm5200_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_CM5200=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig
index 72283a61d4..bbb76a5c61 100644
--- a/configs/cm_t3517_defconfig
+++ b/configs/cm_t3517_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T3517=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3517 # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index 9a7b2057cc..110e002d95 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_CM_T35=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T3x # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index c926a3a4bb..b80ca0da4e 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -37,4 +37,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index bcab16bb05..4f2425b194 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP54XX=y
 CONFIG_TARGET_CM_T54=y
 CONFIG_SPL=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="CM-T54 # "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index 3cb69ac205..400fca0f21 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -1,6 +1,7 @@
 CONFIG_M68K=y
 CONFIG_TARGET_COBRA5272=y
 CONFIG_SYS_TEXT_BASE=0xffe00000
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="COBRA > "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index a3b2a3c862..a0c40fecd1 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -44,4 +44,3 @@ CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index c920b396aa..c7f6982f12 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -36,4 +36,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig
index 655a0e7353..ae67c375b5 100644
--- a/configs/colorfly_e708_q1_defconfig
+++ b/configs/colorfly_e708_q1_defconfig
@@ -16,19 +16,9 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-colorfly-e708-q1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_AXP_DLDO2_VOLT=1800
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 5186345fde..64fd7c9cff 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -8,6 +8,8 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
index 7cc9a6ed68..aff63280ca 100644
--- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD,DEVELOP"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig
index ee7739a57e..74b67f7179 100644
--- a/configs/controlcenterd_36BIT_SDCARD_defconfig
+++ b/configs/controlcenterd_36BIT_SDCARD_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 37488dd456..2efffb5985 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_CORVUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 7c6b692c6b..8e086c512a 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -8,8 +8,6 @@ CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
 CONFIG_FIT=y
-CONFIG_BOOTSTAGE=y
-CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
@@ -24,7 +22,6 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
-CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig
index 0b77b1bdc0..8282e25d9a 100644
--- a/configs/d2net_v2_defconfig
+++ b/configs/d2net_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="d2v2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig
index 8fd51ad546..69839df7d2 100644
--- a/configs/da850_am18xxevm_defconfig
+++ b/configs/da850_am18xxevm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 866d187726..0e281a5e67 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index 0bb2d37ac9..9c5428db6a 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_DA850EVM=y
 CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_CMD_ASKENV=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index 75eaad8775..980e153ce3 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig
index e9ba1ef70f..f06f27f9c5 100644
--- a/configs/db-88f6720_defconfig
+++ b/configs/db-88f6720_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_DB_88F6720=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-375-db"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 7ad3bb66b1..123e7fccd7 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DB_88F6820_GP=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 44f64fda64..f2c4a9ee6a 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_DB_MV784MP_GP=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig
index c3fa26faa4..996e2f78a5 100644
--- a/configs/dbau1000_defconfig
+++ b/configs/dbau1000_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig
index 5e2c9bd125..2b3ccd8915 100644
--- a/configs/dbau1100_defconfig
+++ b/configs/dbau1100_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig
index 10fe8aa37f..7459c6342f 100644
--- a/configs/dbau1500_defconfig
+++ b/configs/dbau1500_defconfig
@@ -12,4 +12,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig
index 7f1bdf4100..964d8a8eab 100644
--- a/configs/dbau1550_defconfig
+++ b/configs/dbau1550_defconfig
@@ -9,4 +9,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig
index 6cd01614d5..dfe0102ffe 100644
--- a/configs/dbau1550_el_defconfig
+++ b/configs/dbau1550_el_defconfig
@@ -10,4 +10,3 @@ CONFIG_SYS_PROMPT="DbAu1xx0 # "
 # CONFIG_CMD_FPGA is not set
 # CONFIG_CMD_SETEXPR is not set
 # CONFIG_CMD_NFS is not set
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig
index 5449cff710..bf7f545079 100644
--- a/configs/devconcenter_defconfig
+++ b/configs/devconcenter_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig
index 2b6dba8a22..c76af0ec01 100644
--- a/configs/difrnce_dit4350_defconfig
+++ b/configs/difrnce_dit4350_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-difrnce-dit4350"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig
index 1ebfd23e4d..e22461d480 100644
--- a/configs/dlvision-10g_defconfig
+++ b/configs/dlvision-10g_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION_10G=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig
index 7b28d1d0bc..fba3611903 100644
--- a/configs/dlvision_defconfig
+++ b/configs/dlvision_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_DLVISION=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig
index a3d053d3f0..e997f6d0fb 100644
--- a/configs/dns325_defconfig
+++ b/configs/dns325_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DNS325=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig
index 6ae447c962..2d99796085 100644
--- a/configs/dockstar_defconfig
+++ b/configs/dockstar_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DOCKSTAR=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="DockStar> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/dra72_evm_defconfig b/configs/dra72_evm_defconfig
deleted file mode 100644
index 00c6ac3cb7..0000000000
--- a/configs/dra72_evm_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_DM_SERIAL=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_DM_GPIO=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_DEFAULT_DEVICE_TREE="dra72-evm"
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_CONTROL=y
-CONFIG_DM=y
-CONFIG_DM_MMC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_TIMER=y
-CONFIG_OMAP_TIMER=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index b6458ae0e5..1237a73271 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -1,9 +1,17 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_DRA7XX_EVM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_GPIO=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -25,12 +33,20 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
+CONFIG_DM=y
+CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SYS_NS16550=y
 CONFIG_TI_QSPI=y
+CONFIG_TIMER=y
+CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
@@ -40,4 +56,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/dra7xx_evm_uart3_defconfig b/configs/dra7xx_evm_uart3_defconfig
deleted file mode 100644
index 54c7ba9990..0000000000
--- a/configs/dra7xx_evm_uart3_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_DRA7XX_EVM=y
-CONFIG_CONS_INDEX=3
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SYS_EXTRA_OPTIONS="SPL_YMODEM_SUPPORT"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SYS_NS16550=y
-CONFIG_TI_QSPI=y
-CONFIG_USB=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GADGET=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
-CONFIG_G_DNL_VENDOR_NUM=0x0451
-CONFIG_G_DNL_PRODUCT_NUM=0xd022
-CONFIG_OF_LIBFDT=y
diff --git a/configs/dra74_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index a11dcd56c3..0724916615 100644
--- a/configs/dra74_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -1,5 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP54XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TI_SECURE_DEVICE=y
 CONFIG_TARGET_DRA7XX_EVM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_SPI=y
@@ -9,6 +11,9 @@ CONFIG_SPL_STACK_R_ADDR=0x82000000
 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SPL_LOAD_FIT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -31,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="dra7-evm dra72-evm"
 CONFIG_DM=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH=y
@@ -41,6 +47,8 @@ CONFIG_TI_QSPI=y
 CONFIG_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_OMAP=y
@@ -50,3 +58,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 0a437ed16b..d17e42f3e9 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_DRACO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index 2566ded58a..37c5ea7761 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -23,7 +23,7 @@ CONFIG_MSM_GPIO=y
 CONFIG_PM8916_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_MSM_SDHCI=y
 CONFIG_DM_PMIC=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index d293e3034b..8f745f8b3b 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_DREAMPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 4d3cb34405..a21473255c 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_DS414=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig
index b0791b9008..ba50ce0515 100644
--- a/configs/dserve_dsrv9703c_defconfig
+++ b/configs/dserve_dsrv9703c_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_MMC0_CD_PIN="PH1"
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
@@ -14,18 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-dserve-dsrv9703c"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig
index d6e51f80b0..57df04fb41 100644
--- a/configs/ea20_defconfig
+++ b/configs/ea20_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_EA20=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ea20 > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig
index 55d5552354..bf9177b351 100644
--- a/configs/eb_cpu5282_defconfig
+++ b/configs/eb_cpu5282_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_EB_CPU5282=y
 CONFIG_SYS_TEXT_BASE=0xFF000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400"
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="\nEB+CPU5282> "
 # CONFIG_CMD_LOADB is not set
 CONFIG_CMD_I2C=y
diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig
index e204ba266e..4f6de89214 100644
--- a/configs/eb_cpu5282_internal_defconfig
+++ b/configs/eb_cpu5282_internal_defconfig
@@ -2,6 +2,7 @@ CONFIG_M68K=y
 CONFIG_TARGET_EB_CPU5282=y
 CONFIG_SYS_TEXT_BASE=0xF0000000
 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418"
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_LOADB is not set
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig
index 467a0a14f3..b81ad58a15 100644
--- a/configs/eco5pk_defconfig
+++ b/configs/eco5pk_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_ECO5PK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ECO5-PK # "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ecovec_defconfig b/configs/ecovec_defconfig
index 0066c7d9f4..a23f52a36e 100644
--- a/configs/ecovec_defconfig
+++ b/configs/ecovec_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_ECOVEC=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig
index fa7c1b5113..e57dfdaa74 100644
--- a/configs/edminiv2_defconfig
+++ b/configs/edminiv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ORION5X=y
 CONFIG_TARGET_EDMINIV2=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="EDMiniV2> "
 CONFIG_CMD_I2C=y
diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig
new file mode 100644
index 0000000000..8d0bacef52
--- /dev/null
+++ b/configs/espresso7420_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS7=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420"
+CONFIG_SYS_PROMPT="ESPRESSO7420 # "
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_SETEXPR is not set
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
new file mode 100644
index 0000000000..6c747df66b
--- /dev/null
+++ b/configs/etamin_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_ETAMIN=y
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_PROMPT="U-Boot# "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
+CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 579efd3f98..a88d37b620 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_ETHERNUT5=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 4dd4586243..3f77981f94 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -28,7 +28,7 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
@@ -39,6 +39,5 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_BASE=0x20068000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index 0995f9b329..a64f6de349 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -28,7 +28,7 @@ CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
 CONFIG_SYSCON=y
@@ -40,7 +40,7 @@ CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
@@ -65,7 +65,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 298888c24b..f6e01c1a36 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="flea3 U-Boot > "
 CONFIG_CMD_SPI=y
diff --git a/configs/fo300_defconfig b/configs/fo300_defconfig
index babfaf4675..aad6eaa8d4 100644
--- a/configs/fo300_defconfig
+++ b/configs/fo300_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_TQM5200=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="FO300"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig
index 03cdb1787c..34e74af9f6 100644
--- a/configs/ga10h_v1_1_defconfig
+++ b/configs/ga10h_v1_1_defconfig
@@ -18,19 +18,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 17b14589cc..080c2ed50d 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -4,10 +4,13 @@ CONFIG_DEFAULT_DEVICE_TREE="galileo"
 CONFIG_TARGET_GALILEO=y
 CONFIG_ENABLE_MRC_CACHE=y
 CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
 CONFIG_FIT=y
 CONFIG_BOOTSTAGE=y
 CONFIG_BOOTSTAGE_REPORT=y
 CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
@@ -30,6 +33,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
+CONFIG_CPU=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig
index eacd4bb1eb..ef4c4ed5d4 100644
--- a/configs/gdppc440etx_defconfig
+++ b/configs/gdppc440etx_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_GDPPC440ETX=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig
index 6d0dabe119..d8b42274d3 100644
--- a/configs/glacier_defconfig
+++ b/configs/glacier_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_CANYONLANDS=y
 CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/glacier_ramboot_defconfig b/configs/glacier_ramboot_defconfig
index e7e1287511..2875492c3d 100644
--- a/configs/glacier_ramboot_defconfig
+++ b/configs/glacier_ramboot_defconfig
@@ -5,6 +5,7 @@ CONFIG_GLACIER=y
 CONFIG_DEFAULT_DEVICE_TREE="glacier"
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/canyonlands/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig
index ee024694d6..cf251162a7 100644
--- a/configs/goflexhome_defconfig
+++ b/configs/goflexhome_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_GOFLEXHOME=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="GoFlexHome> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 9f6589a1e9..f2075fe27d 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_GOSE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig
index 2bdd0e7bed..9fee96aee0 100644
--- a/configs/gplugd_defconfig
+++ b/configs/gplugd_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_GPLUGD=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig
index d3f9c0285e..b30590ea2b 100644
--- a/configs/gr_cpci_ax2000_defconfig
+++ b/configs/gr_cpci_ax2000_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_CPCI_AX2000=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_CPCI_AX2000=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig
index 29c7f29bee..302d936e27 100644
--- a/configs/gr_ep2s60_defconfig
+++ b/configs/gr_ep2s60_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_EP2S60=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_EP2S60=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig
index e4877f23f5..d6ed30581c 100644
--- a/configs/gr_xc3s_1500_defconfig
+++ b/configs/gr_xc3s_1500_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GR_XC3S_1500=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GR_XC3S_1500=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig
index d2f709f834..f827113ab5 100644
--- a/configs/grsim_defconfig
+++ b/configs/grsim_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GRSIM=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GRSIM=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig
index 9c9c968582..f5e7c433fa 100644
--- a/configs/grsim_leon2_defconfig
+++ b/configs/grsim_leon2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SPARC=y
-CONFIG_TARGET_GRSIM_LEON2=y
 CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_TARGET_GRSIM_LEON2=y
+CONFIG_BOOTDELAY=5
 # CONFIG_CMD_BOOTD is not set
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig
index c11aed8bd4..a14de0d0bf 100644
--- a/configs/gt90h_v4_defconfig
+++ b/configs/gt90h_v4_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-gt90h-v4"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 0baf3a30af..31794b9ea2 100644
--- a/configs/guruplug_defconfig
+++ b/configs/guruplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_GURUPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig
index 7c731b30cc..c4bd2c51de 100644
--- a/configs/h8_homlet_v2_defconfig
+++ b/configs/h8_homlet_v2_defconfig
@@ -4,26 +4,15 @@ CONFIG_MACH_SUN8I_A83T=y
 CONFIG_DRAM_CLK=480
 CONFIG_DRAM_ZQ=15355
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB0_VBUS_PIN="PL5"
 CONFIG_USB1_VBUS_PIN="PL6"
 CONFIG_AXP_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-allwinner-h8homlet-v2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO4_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/haleakala_defconfig b/configs/haleakala_defconfig
index c90eff4141..4130e27602 100644
--- a/configs/haleakala_defconfig
+++ b/configs/haleakala_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="HALEAKALA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig
index 129a72b1cf..16b0297f97 100644
--- a/configs/harmony_defconfig
+++ b/configs/harmony_defconfig
@@ -35,4 +35,3 @@ CONFIG_USB_ULPI_VIEWPORT=y
 CONFIG_USB_ULPI=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index d150dd3bcd..ba0a37ebe2 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
@@ -13,5 +14,3 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_LIBFDT=y
-CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey"
diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig
index 32d0486955..f67eda701c 100644
--- a/configs/hrcon_defconfig
+++ b/configs/hrcon_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig
index 657826a7a6..5eff4ac164 100644
--- a/configs/hrcon_dh_defconfig
+++ b/configs/hrcon_dh_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_I2C=y
diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig
index 266015a617..54fa8190e6 100644
--- a/configs/i12-tvbox_defconfig
+++ b/configs/i12-tvbox_defconfig
@@ -7,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-i12-tvbox"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,MACPWR=SUNXI_GPH(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig
index e9ec810ef8..ebf103a2ce 100644
--- a/configs/iNet_3F_defconfig
+++ b/configs/iNet_3F_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_MMC0_CD_PIN="PH1"
@@ -14,18 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig
index 64da00f461..2cadf17201 100644
--- a/configs/iNet_3W_defconfig
+++ b/configs/iNet_3W_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_ZQ=127
 CONFIG_DRAM_EMR1=4
@@ -14,18 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig
index 8b64678b97..3dea793b91 100644
--- a/configs/iNet_86VS_defconfig
+++ b/configs/iNet_86VS_defconfig
@@ -13,18 +13,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig
index 265114f211..3b24256dd2 100644
--- a/configs/ib62x0_defconfig
+++ b/configs/ib62x0_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_IB62X0=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ib62x0 => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig
index d432ff0c9a..548a07e733 100644
--- a/configs/icnova-a20-swac_defconfig
+++ b/configs/icnova-a20-swac_defconfig
@@ -14,19 +14,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-icnova-swac"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,CMD_BMP,CMD_UNZIP"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/icon_defconfig b/configs/icon_defconfig
index d32bbc4ce2..a2a70731da 100644
--- a/configs/icon_defconfig
+++ b/configs/icon_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_ICON=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig
index 44a474e634..516b2393f2 100644
--- a/configs/iconnect_defconfig
+++ b/configs/iconnect_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_ICONNECT=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="iconnect => "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig
index e824616c0f..136b9d14ad 100644
--- a/configs/imx31_phycore_defconfig
+++ b/configs/imx31_phycore_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="uboot> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig
index afe3c3c1b1..96252c3eac 100644
--- a/configs/imx31_phycore_eet_defconfig
+++ b/configs/imx31_phycore_eet_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_IMX31_PHYCORE=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig
index b0f244dece..e84ed57e53 100644
--- a/configs/inet1_defconfig
+++ b/configs/inet1_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
@@ -14,19 +13,8 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet1"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig
index a95379557f..2444a38c8f 100644
--- a/configs/inet97fv2_defconfig
+++ b/configs/inet97fv2_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
@@ -13,18 +12,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet97fv2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig
index dace876a1e..27b5019237 100644
--- a/configs/inet98v_rev2_defconfig
+++ b/configs/inet98v_rev2_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-98v-rev2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig
index 35d9d7c574..a2489c4b1a 100644
--- a/configs/inet9f_rev03_defconfig
+++ b/configs/inet9f_rev03_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=408
 CONFIG_DRAM_EMR1=4
 CONFIG_USB0_VBUS_PIN="PB9"
@@ -13,18 +12,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet9f-rev03"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig
index 483703ac36..3cbff46aa4 100644
--- a/configs/inetspace_v2_defconfig
+++ b/configs/inetspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/intip_defconfig b/configs/intip_defconfig
index 512d4a817f..cd0f234e0c 100644
--- a/configs/intip_defconfig
+++ b/configs/intip_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_INTIP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="INTIB"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/io64_defconfig b/configs/io64_defconfig
index afc5a83db7..27ffaeae10 100644
--- a/configs/io64_defconfig
+++ b/configs/io64_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO64=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/io_defconfig b/configs/io_defconfig
index 1bb9248c57..2392d9bcb9 100644
--- a/configs/io_defconfig
+++ b/configs/io_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_IO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig
index 2e66b9497e..c7b3b277c4 100644
--- a/configs/iocon_defconfig
+++ b/configs/iocon_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_IOCON=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/ipek01_defconfig b/configs/ipek01_defconfig
index e0b4390c7d..19f53dfb5c 100644
--- a/configs/ipek01_defconfig
+++ b/configs/ipek01_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_IPEK01=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_LOOPW=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig
index 79f3cfbf82..a9b90841cb 100644
--- a/configs/jesurun_q5_defconfig
+++ b/configs/jesurun_q5_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=312
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_VIDEO_COMPOSITE=y
@@ -8,19 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-jesurun-q5"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_EMAC,MACPWR=SUNXI_GPH(19)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 7b04a0c150..f672aa2f96 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -44,4 +44,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/jupiter_defconfig b/configs/jupiter_defconfig
index 21c448b805..48249b0bd8 100644
--- a/configs/jupiter_defconfig
+++ b/configs/jupiter_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_JUPITER=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_SNTP=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 044a9bf5b6..9fcdfe9b9f 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -32,3 +32,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index d0b45ce3f8..8efa58c8c4 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -32,3 +32,6 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_REMOTEPROC_TI_POWER=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 3975e804e5..278eaf32fd 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -32,3 +32,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 844dd57163..8417e0ab07 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -32,3 +32,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_DM_ETH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/katmai_defconfig b/configs/katmai_defconfig
index b3e61f8a7d..30c8bf02bf 100644
--- a/configs/katmai_defconfig
+++ b/configs/katmai_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_KATMAI=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/kilauea_defconfig b/configs/kilauea_defconfig
index f85cfbb4b1..698de8c386 100644
--- a/configs/kilauea_defconfig
+++ b/configs/kilauea_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_KILAUEA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="KILAUEA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 5c45f7be60..217a868230 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KOELSCH=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 50fbe654bf..bed9df82d0 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -28,12 +28,11 @@ CONFIG_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_LED=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
 CONFIG_ROCKCHIP_3036_PINCTRL=y
 CONFIG_RAM=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index e3902ce01e..00a54416b5 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_KZM9G=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_I2C=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index c26211706a..19dd1fe27e 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_LAGER=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig
new file mode 100644
index 0000000000..1aed0c45a8
--- /dev/null
+++ b/configs/ls1012afrdm_qspi_defconfig
@@ -0,0 +1,33 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
new file mode 100644
index 0000000000..86ddf719d4
--- /dev/null
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
new file mode 100644
index 0000000000..3806412919
--- /dev/null
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=10
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPI_FLASH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 6feb581d6e..6012d49595 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,3 +27,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 563af4802e..685f1da1b3 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,3 +27,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 0786f20aaf..eca1cca113 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -21,4 +24,7 @@ CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index 243fcddc0c..a39a4037ae 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 # CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -22,5 +25,8 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index 3cecdfe424..67485465c1 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -2,8 +2,11 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -23,3 +26,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 75b763e03a..81035c9a1a 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,3 +27,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index c47fbce801..a1504c3a15 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -30,3 +33,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index 61ab25106c..f8bdfe8ec4 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -2,7 +2,10 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -22,3 +25,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index bb887431ba..a1ee5b95c4 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -3,7 +3,10 @@ CONFIG_TARGET_LS1021AQDS=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -29,3 +32,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index a5cbb22e46..0d406ac24f 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 # CONFIG_SYS_MALLOC_F is not set
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -22,5 +25,8 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 465054fad9..a6be6c63e6 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -2,8 +2,11 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -23,3 +26,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index e96e31af21..3b6c5cf961 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-lpuart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="LPUART"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,3 +27,6 @@ CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 987638cfe3..0a6cbcd498 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -2,9 +2,12 @@ CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -31,3 +34,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index df4d428260..2128c464cc 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -1,9 +1,12 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -20,4 +23,7 @@ CONFIG_CMD_FAT=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index 583325d80a..8d1f8edef0 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -3,9 +3,12 @@ CONFIG_TARGET_LS1021ATWR=y
 CONFIG_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -31,3 +34,6 @@ CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index 346faf46a0..8dfad69a4a 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -25,3 +26,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 2c6ac35c4f..56f5efe5c5 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -26,3 +27,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_FSL_LPUART=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index cc8d8fa51f..61368878e7 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -26,3 +27,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index 7d0646c1bd..7c78b6eaa6 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -24,3 +25,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index 8ea14164ab..2b2a71426d 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,QSPI_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -26,3 +27,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index 7e5949d98d..f90a6be38b 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_GREPENV=y
@@ -26,3 +27,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index 609fd636e4..d85f771628 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -27,3 +28,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index cacee2f748..218dd76dad 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
@@ -21,4 +22,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 49d0740fae..983e4c22b2 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
@@ -21,3 +22,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index d240cde39e..c420548141 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
@@ -22,3 +23,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index f85368541e..a5a870b182 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -7,6 +7,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
@@ -22,3 +23,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig
index f9b4eacb64..21a02830d6 100644
--- a/configs/ls2080a_emu_defconfig
+++ b/configs/ls2080a_emu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -25,3 +26,4 @@ CONFIG_CMD_CACHE=y
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig
index 728fa25549..1b670b0c05 100644
--- a/configs/ls2080a_simu_defconfig
+++ b/configs/ls2080a_simu_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_IMLS is not set
@@ -28,3 +29,4 @@ CONFIG_CMD_FAT=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NS16550=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index 216559c90a..947ac3d420 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -29,4 +30,8 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 854630a194..cd8a7bdca6 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -29,3 +30,7 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 4f385a1409..8c5b69d77f 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -22,4 +23,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index 41d30a6e2f..8f98720ad1 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A, SECURE_BOOT"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -29,4 +30,8 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_RSA=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index 2b775cd239..c0b8a98da3 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -9,6 +9,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -29,3 +30,7 @@ CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_FSL_DSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 0f184c01f4..26ffe98505 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GREPENV=y
 CONFIG_CMD_MMC=y
@@ -22,4 +23,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_OF_LIBFDT=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig
index 4af7e5d7ef..002ca44d5b 100644
--- a/configs/lschlv2_defconfig
+++ b/configs/lschlv2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig
index 5bcd367857..4f63da9b6c 100644
--- a/configs/lsxhl_defconfig
+++ b/configs/lsxhl_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_LSXL=y
 CONFIG_SYS_EXTRA_OPTIONS="LSXHL"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/luan_defconfig b/configs/luan_defconfig
index e0fa805420..90801f4a93 100644
--- a/configs/luan_defconfig
+++ b/configs/luan_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_LUAN=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/lwmon5_defconfig b/configs/lwmon5_defconfig
index 64794a1f1b..eaf6c97623 100644
--- a/configs/lwmon5_defconfig
+++ b/configs/lwmon5_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_LWMON5=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_LOOPW=y
diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig
index c598c7209d..b505d29334 100644
--- a/configs/m28evk_defconfig
+++ b/configs/m28evk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_M28EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/m53evk_defconfig b/configs/m53evk_defconfig
index 62496c39c6..962e03644d 100644
--- a/configs/m53evk_defconfig
+++ b/configs/m53evk_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_M53EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/denx/m53evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig
index 81a67004ff..75affaa23f 100644
--- a/configs/ma5d4evk_defconfig
+++ b/configs/ma5d4evk_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_MA5D4EVK=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/makalu_defconfig b/configs/makalu_defconfig
index 8f7baea636..4967e10a10 100644
--- a/configs/makalu_defconfig
+++ b/configs/makalu_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_MAKALU=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/malta64_defconfig b/configs/malta64_defconfig
new file mode 100644
index 0000000000..590f9b5674
--- /dev/null
+++ b/configs/malta64_defconfig
@@ -0,0 +1,15 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="malta # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/malta64el_defconfig b/configs/malta64el_defconfig
new file mode 100644
index 0000000000..ff93931c00
--- /dev/null
+++ b/configs/malta64el_defconfig
@@ -0,0 +1,16 @@
+CONFIG_MIPS=y
+CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R2=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="maltael # "
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
+CONFIG_SYS_NS16550=y
diff --git a/configs/malta_defconfig b/configs/malta_defconfig
index a16f10be6a..3a875860e4 100644
--- a/configs/malta_defconfig
+++ b/configs/malta_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="malta # "
 # CONFIG_CMD_LOADB is not set
@@ -9,5 +10,5 @@ CONFIG_SYS_PROMPT="malta # "
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig
index 5289797748..11ff25927a 100644
--- a/configs/maltael_defconfig
+++ b/configs/maltael_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_MALTA=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DEFAULT_DEVICE_TREE="mti,malta"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="maltael # "
 # CONFIG_CMD_LOADB is not set
@@ -10,5 +11,5 @@ CONFIG_SYS_PROMPT="maltael # "
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
+CONFIG_OF_EMBED=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig
index 7a5eeba022..b67bc51fe1 100644
--- a/configs/maxbcm_defconfig
+++ b/configs/maxbcm_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_MAXBCM=y
 CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_SF=y
diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig
index ab814cc213..2e819e40b4 100644
--- a/configs/mcx_defconfig
+++ b/configs/mcx_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MCX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mcx # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/mecp5123_defconfig b/configs/mecp5123_defconfig
index 9597482cb4..98f006889f 100644
--- a/configs/mecp5123_defconfig
+++ b/configs/mecp5123_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MECP5123=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig
index 02eb70431b..4dd4dcef16 100644
--- a/configs/medcom-wide_defconfig
+++ b/configs/medcom-wide_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 3d295f574d..b214a923e4 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index aac7cc5e21..727d193679 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_MEESC=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 8c7e4b7938..2ef713fee3 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -2,6 +2,10 @@ CONFIG_MICROBLAZE=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_TARGET_MICROBLAZE_GENERIC=y
+CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1
+CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1
+CONFIG_XILINX_MICROBLAZE0_USE_DIV=1
+CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=1
 CONFIG_SYS_TEXT_BASE=0x29000000
 CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic"
 CONFIG_SPL=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 9930d56a6b..28b837daab 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -8,6 +8,8 @@ CONFIG_SMP=y
 CONFIG_HAVE_VGA_BIOS=y
 CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
 CONFIG_FIT=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_BOOTSTAGE=y
diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig
index 9a4446637d..ce81309b0f 100644
--- a/configs/mixtile_loftq_defconfig
+++ b/configs/mixtile_loftq_defconfig
@@ -9,19 +9,9 @@ CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-mixtile-loftq"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPA(21)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_AXP_ALDO1_VOLT=3300
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig
index 5e545d083c..720aefad30 100644
--- a/configs/mk802_a10s_defconfig
+++ b/configs/mk802_a10s_defconfig
@@ -7,19 +7,8 @@ CONFIG_USB1_VBUS_PIN="PB10"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig
index a76a699044..63b6a766f0 100644
--- a/configs/mk802_defconfig
+++ b/configs/mk802_defconfig
@@ -1,24 +1,12 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_USB2_VBUS_PIN="PH12"
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SUNXI_NO_PMIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig
index bdfb59756d..c366411805 100644
--- a/configs/mk802ii_defconfig
+++ b/configs/mk802ii_defconfig
@@ -1,21 +1,9 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/mpc5121ads_defconfig b/configs/mpc5121ads_defconfig
index 34935adcd2..4bc7e4378e 100644
--- a/configs/mpc5121ads_defconfig
+++ b/configs/mpc5121ads_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/mpc5121ads_rev2_defconfig b/configs/mpc5121ads_rev2_defconfig
index 664d9495e1..6c942fc3ec 100644
--- a/configs/mpc5121ads_rev2_defconfig
+++ b/configs/mpc5121ads_rev2_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC512X=y
 CONFIG_TARGET_MPC5121ADS=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="MPC5121ADS_REV2"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig
index 1f28c08f63..a1fdcf26ec 100644
--- a/configs/mpc8308_p1m_defconfig
+++ b/configs/mpc8308_p1m_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_MPC8308_P1M=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/ms7722se_defconfig b/configs/ms7722se_defconfig
index a9bc3d4ea8..026f566750 100644
--- a/configs/ms7722se_defconfig
+++ b/configs/ms7722se_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_MS7722SE=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig
index dda0daa71b..af58328448 100644
--- a/configs/mt_ventoux_defconfig
+++ b/configs/mt_ventoux_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_MT_VENTOUX=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="mt_ventoux => "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/munices_defconfig b/configs/munices_defconfig
index eabfe1ec4d..169fc93cba 100644
--- a/configs/munices_defconfig
+++ b/configs/munices_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_MUNICES=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_PING=y
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index e201abbb5e..a028482bf0 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX23_OLINUXINO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
index 9ccf06964e..b4c2ad3135 100644
--- a/configs/mx31ads_defconfig
+++ b/configs/mx31ads_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX31ADS=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_SPI=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index 500b39c4da..7a62c2b954 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53ARD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 45f5e4570d..9a05a8bf8c 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53EVK=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53evk/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index c24aec6d68..93b20d7044 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_MX53SMD=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig
index f904e12b7b..224b5b7805 100644
--- a/configs/nas220_defconfig
+++ b/configs/nas220_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NAS220=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nas220> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/neo_defconfig b/configs/neo_defconfig
index e306d681b3..b61b7190a6 100644
--- a/configs/neo_defconfig
+++ b/configs/neo_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_NEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_ELF is not set
 CONFIG_CMD_ASKENV=y
diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig
index f930e473e4..fcd4b13f2c 100644
--- a/configs/net2big_v2_defconfig
+++ b/configs/net2big_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NET2BIG_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="2big2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig
index 7917336c89..a117946f48 100644
--- a/configs/netspace_lite_v2_defconfig
+++ b/configs/netspace_lite_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig
index 55978f2ef9..e4a1149b03 100644
--- a/configs/netspace_max_v2_defconfig
+++ b/configs/netspace_max_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig
index 67b142d236..f46b9a1ecd 100644
--- a/configs/netspace_mini_v2_defconfig
+++ b/configs/netspace_mini_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig
index 8199bbd911..1b76bc2741 100644
--- a/configs/netspace_v2_defconfig
+++ b/configs/netspace_v2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NETSPACE_V2=y
 CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ns2> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 6eb01ea511..da103929b7 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_NOKIA_RX51=y
+CONFIG_BOOTDELAY=30
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Nokia RX-51 # "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig
index 51da5ad6ad..fdec8dc04d 100644
--- a/configs/nsa310s_defconfig
+++ b/configs/nsa310s_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_NSA310S=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="nsa310s => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 262042d87f..6cf304f3b3 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -61,6 +61,5 @@ CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_TEGRA124=y
 CONFIG_VIDEO_BRIDGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_TPM=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
new file mode 100644
index 0000000000..483d4900b7
--- /dev/null
+++ b/configs/odroid-c2_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_MESON_GXBB=y
+CONFIG_TARGET_ODROID_C2=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_BASE=0xc81004c0
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 8995cc2f6b..44b5c16043 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
-CONFIG_TARGET_ODROID_XU3=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
@@ -36,6 +36,8 @@ CONFIG_PMIC_S2MPS11=y
 CONFIG_DM_REGULATOR=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_DWC3_PHY_SAMSUNG=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index ff3b3390f6..76ab144fbb 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_ODROID=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid"
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 1a9f2076c7..adca570327 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_OMAP3_EVM=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="OMAP3_EVM # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig
index 5f0dece597..e446586dcb 100644
--- a/configs/omap3_ha_defconfig
+++ b/configs/omap3_ha_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 322624781a..b8c7621298 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -33,4 +33,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="TI"
 CONFIG_G_DNL_VENDOR_NUM=0x0451
 CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 4d5e8a0c9e..51dc1dba35 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_DAVINCI=y
 CONFIG_TARGET_OMAPL138_LCDK=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index 700192132e..2f4035541e 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index fd53c783fc..336104e695 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index 52b9a5b74a..11a49fe579 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_OPENRD=y
 CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig
index f33ac36fb3..d5383d4c6b 100644
--- a/configs/orangepi_2_defconfig
+++ b/configs/orangepi_2_defconfig
@@ -4,25 +4,12 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_USB1_VBUS_PIN="PG13"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig
index de6e9c8ddb..9b6a1af8fc 100644
--- a/configs/orangepi_one_defconfig
+++ b/configs/orangepi_one_defconfig
@@ -4,22 +4,10 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-one"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig
index 7bade8faab..7f360f5d07 100644
--- a/configs/orangepi_pc_defconfig
+++ b/configs/orangepi_pc_defconfig
@@ -4,23 +4,11 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=624
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-pc"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig
index 2df5859891..88df36064e 100644
--- a/configs/orangepi_plus_defconfig
+++ b/configs/orangepi_plus_defconfig
@@ -4,27 +4,14 @@ CONFIG_MACH_SUN8I_H3=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881979
 CONFIG_DRAM_ODT_EN=y
-CONFIG_MMC0_CD_PIN="PF6"
 CONFIG_MMC_SUNXI_SLOT_EXTRA=2
 CONFIG_USB1_VBUS_PIN="PG13"
-# CONFIG_VIDEO is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-orangepi-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="SATAPWR=SUNXI_GPG(11)"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_SY8106A_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index b1740dcc3f..6ad01af520 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_ORIGEN=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-origen"
 CONFIG_SPL=y
diff --git a/configs/p2771-0000_defconfig b/configs/p2771-0000_defconfig
new file mode 100644
index 0000000000..1136e1f021
--- /dev/null
+++ b/configs/p2771-0000_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_TEGRA=y
+CONFIG_TEGRA186=y
+CONFIG_DEFAULT_DEVICE_TREE="tegra186-p2771-0000"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Tegra186 (P2771-0000) # "
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig
index 0fe43b1c95..64b956f594 100644
--- a/configs/paz00_defconfig
+++ b/configs/paz00_defconfig
@@ -33,4 +33,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig
index 6aa2c43ecb..5a7fa80e0d 100644
--- a/configs/pb1000_defconfig
+++ b/configs/pb1000_defconfig
@@ -14,4 +14,3 @@ CONFIG_SYS_PROMPT="Pb1x00 # "
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pcm030_LOWBOOT_defconfig b/configs/pcm030_LOWBOOT_defconfig
index dbfaea1d90..6205aa3bd2 100644
--- a/configs/pcm030_LOWBOOT_defconfig
+++ b/configs/pcm030_LOWBOOT_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFF000000"
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/pcm030_defconfig b/configs/pcm030_defconfig
index 6d2588498e..994a369991 100644
--- a/configs/pcm030_defconfig
+++ b/configs/pcm030_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_PCM030=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="uboot> "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index db8ebdd620..5d30f30bb8 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="pcm052"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pdm360ng_defconfig b/configs/pdm360ng_defconfig
index c3521955ee..f3de685392 100644
--- a/configs/pdm360ng_defconfig
+++ b/configs/pdm360ng_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_PDM360NG=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig
index c8c74c0301..313fb03e66 100644
--- a/configs/peach-pi_defconfig
+++ b/configs/peach-pi_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PI=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi"
@@ -46,6 +47,8 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65090=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
@@ -55,6 +58,10 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig
index c5fbf8c822..eb5558a408 100644
--- a/configs/peach-pit_defconfig
+++ b/configs/peach-pit_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_PEACH_PIT=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit"
@@ -46,6 +47,8 @@ CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65090=y
 CONFIG_DM_REGULATOR=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_SOUND=y
 CONFIG_I2S=y
 CONFIG_I2S_SAMSUNG=y
@@ -55,6 +58,10 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index 9547d4891b..d5e9408260 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -6,6 +6,7 @@ CONFIG_MACH_PIC32=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_DEFAULT_DEVICE_TREE="pic32mzda_sk"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="dask # "
 # CONFIG_CMD_IMLS is not set
@@ -42,6 +43,5 @@ CONFIG_DM_USB=y
 CONFIG_USB_MUSB_HOST=y
 CONFIG_USB_MUSB_PIC32=y
 CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 723466f694..f7069e90c1 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PICOSAM9G45=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 0494a9f1cc..2d9c4a6990 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -1,20 +1,12 @@
 CONFIG_ARM=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_MACH_SUN50I=y
 CONFIG_DRAM_CLK=672
 CONFIG_DRAM_ZQ=3881915
 # CONFIG_VIDEO is not set
-CONFIG_DEFAULT_DEVICE_TREE="pine64_plus"
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
-CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig
index ed519a04ab..6b60335d92 100644
--- a/configs/plutux_defconfig
+++ b/configs/plutux_defconfig
@@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index cb10fa3700..2062dcd3fc 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9261=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="pm9261> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index 37629ba0f5..e6ebd9b783 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9263=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="u-boot-pm9263> "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 0949e1f621..aea412ce5d 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_PM9G45=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig
index 2b3b4c84b8..bd4db7165e 100644
--- a/configs/pogo_e02_defconfig
+++ b/configs/pogo_e02_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_POGO_E02=y
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="PogoE02> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig
index cedbf53153..04c99b9e6b 100644
--- a/configs/polaroid_mid2809pxe04_defconfig
+++ b/configs/polaroid_mid2809pxe04_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-polaroid-mid2809pxe04"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 2f819f5035..a587ed5ab2 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_PORTER=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig
index aad9619c1c..23bd9a9d09 100644
--- a/configs/pov_protab2_ips9_defconfig
+++ b/configs/pov_protab2_ips9_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_USB0_VBUS_PIN="PB9"
 CONFIG_USB0_VBUS_DET="PH5"
@@ -14,18 +13,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-pov-protab2-ips9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 86556650a9..6f70d6805b 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_PXM2=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig
index 97232cede3..b467b62f9b 100644
--- a/configs/q8_a13_tablet_defconfig
+++ b/configs/q8_a13_tablet_defconfig
@@ -16,18 +16,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig
index 79dcc33f36..73914641a4 100644
--- a/configs/q8_a23_tablet_800x480_defconfig
+++ b/configs/q8_a23_tablet_800x480_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig
index ff29e81c5f..16f8600c22 100644
--- a/configs/q8_a33_tablet_1024x600_defconfig
+++ b/configs/q8_a33_tablet_1024x600_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig
index d87700c8d6..6378918883 100644
--- a/configs/q8_a33_tablet_800x480_defconfig
+++ b/configs/q8_a33_tablet_800x480_defconfig
@@ -17,18 +17,8 @@ CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-q8-tablet"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP_DLDO1_VOLT=3300
 CONFIG_USB_MUSB_HOST=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 53b1ff65af..45bb3ec0e9 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -20,6 +20,7 @@ CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_PING=y
 CONFIG_CMD_TIME=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
index 0826a0ca88..b013a17f9d 100644
--- a/configs/qemu_mips64_defconfig
+++ b/configs/qemu_mips64_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips64 # "
 # CONFIG_CMD_LOADB is not set
@@ -11,4 +12,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
index f70ebc30b1..bffa1a38cb 100644
--- a/configs/qemu_mips64el_defconfig
+++ b/configs/qemu_mips64el_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS64_R1=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips64el # "
 # CONFIG_CMD_LOADB is not set
@@ -12,4 +13,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
index bb097966e8..9cab7dd43e 100644
--- a/configs/qemu_mips_defconfig
+++ b/configs/qemu_mips_defconfig
@@ -1,5 +1,6 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mips # "
 # CONFIG_CMD_LOADB is not set
@@ -9,4 +10,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
index 19e6c7d7ad..b9226a8d4e 100644
--- a/configs/qemu_mipsel_defconfig
+++ b/configs/qemu_mipsel_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_QEMU_MIPS=y
 CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="qemu-mipsel # "
 # CONFIG_CMD_LOADB is not set
@@ -10,4 +11,3 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/r0p7734_defconfig b/configs/r0p7734_defconfig
index 52149239d7..5f77e05348 100644
--- a/configs/r0p7734_defconfig
+++ b/configs/r0p7734_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_R0P7734=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig
index 4e1c39345e..9d9d4bffed 100644
--- a/configs/r7-tv-dongle_defconfig
+++ b/configs/r7-tv-dongle_defconfig
@@ -6,19 +6,8 @@ CONFIG_USB1_VBUS_PIN="PG13"
 CONFIG_DEFAULT_DEVICE_TREE="sun5i-a10s-r7-tv-dongle"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_AXP152_POWER=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/r7780mp_defconfig b/configs/r7780mp_defconfig
index ad6f2f0815..fbf2dd51cf 100644
--- a/configs/r7780mp_defconfig
+++ b/configs/r7780mp_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_R7780MP=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/rainier_defconfig b/configs/rainier_defconfig
index 27998f38f8..093207ce4c 100644
--- a/configs/rainier_defconfig
+++ b/configs/rainier_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rainier_ramboot_defconfig b/configs/rainier_ramboot_defconfig
index 6ebdb380ca..a7879aef5d 100644
--- a/configs/rainier_ramboot_defconfig
+++ b/configs/rainier_ramboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index ec89f050c7..7de5a199fe 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_RASTABAN=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/redwood_defconfig b/configs/redwood_defconfig
index 89c129f8fe..1cf4832c18 100644
--- a/configs/redwood_defconfig
+++ b/configs/redwood_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_REDWOOD=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index fd32fb521e..516bee7a3c 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -38,7 +38,7 @@ CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_ROCKCHIP_DWMMC=y
 CONFIG_PINCTRL=y
@@ -63,7 +63,6 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
-CONFIG_USE_PRIVATE_LIBGCC=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_ERRNO_STR=y
diff --git a/configs/rsk7264_defconfig b/configs/rsk7264_defconfig
index 272bd863e8..9cc5a201f2 100644
--- a/configs/rsk7264_defconfig
+++ b/configs/rsk7264_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SH=y
 CONFIG_TARGET_RSK7264=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rsk7269_defconfig b/configs/rsk7269_defconfig
index 41e70a5c58..58a5644275 100644
--- a/configs/rsk7269_defconfig
+++ b/configs/rsk7269_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SH=y
 CONFIG_TARGET_RSK7269=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 406eaf33db..14a158f6ef 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_RUT=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 638b72896d..5eb7a40e90 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_S5PC210_UNIVERSAL=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-universal_c210"
 CONFIG_HUSH_PARSER=y
diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig
new file mode 100644
index 0000000000..fce501b32e
--- /dev/null
+++ b/configs/sama5d2_ptc_nandflash_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig
new file mode 100644
index 0000000000..c090264e75
--- /dev/null
+++ b/configs/sama5d2_ptc_spiflash_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_TARGET_SAMA5D2_PTC=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_SPI_FLASH=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 7fd37d6bee..9ca2a9c5e9 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index de4e6bc9b4..617d73a77e 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D2_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index 189a3e96ae..db6592ac06 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 16e3f226dc..d70c3b78a9 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 8d3c3cfac8..5738d2a6a5 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index 8e15286a0d..93aef74e3f 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index ffbafae89e..a938fe7965 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 1ea5cda391..74e208769f 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index 5384917700..3af7ed48d1 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index b709cf6d89..0e037c3db3 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4_XPLAINED=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 45128e9c30..9811326642 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 9c1c23206c..37b080aade 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 59eb4ddaf7..ba939b103b 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -2,7 +2,9 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SAMA5D4EK=y
 CONFIG_SPL=y
+CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index aec2e538a1..71f713083a 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_BLK=y
 CONFIG_MMC=y
 CONFIG_PCI=y
 CONFIG_DEFAULT_DEVICE_TREE="sandbox"
@@ -48,6 +49,7 @@ CONFIG_CMD_LINK_LOCAL=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_SOUND=y
+CONFIG_CMD_QFW=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -69,7 +71,6 @@ CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
-CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CPU=y
 CONFIG_DM_DEMO=y
@@ -88,6 +89,9 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y
 CONFIG_CROS_EC_KEYB=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
+CONFIG_DM_MAILBOX=y
+CONFIG_SANDBOX_MBOX=y
+CONFIG_MISC=y
 CONFIG_CMD_CROS_EC=y
 CONFIG_CROS_EC=y
 CONFIG_CROS_EC_I2C=y
@@ -96,7 +100,7 @@ CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_SANDBOX_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
diff --git a/configs/sandbox_noblk_defconfig b/configs/sandbox_noblk_defconfig
index 93167c2f65..60c73398db 100644
--- a/configs/sandbox_noblk_defconfig
+++ b/configs/sandbox_noblk_defconfig
@@ -94,7 +94,7 @@ CONFIG_CROS_EC_SANDBOX=y
 CONFIG_CROS_EC_SPI=y
 CONFIG_PWRSEQ=y
 CONFIG_SPL_PWRSEQ=y
-CONFIG_RESET=y
+CONFIG_SYSRESET=y
 CONFIG_DM_MMC=y
 CONFIG_SPI_FLASH_SANDBOX=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig
index 9dd60b7b0b..16f61de521 100644
--- a/configs/sansa_fuze_plus_defconfig
+++ b/configs/sansa_fuze_plus_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SANSA_FUZE_PLUS=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig
index 60bb817180..7231b60274 100644
--- a/configs/sbc8349_PCI_33_defconfig
+++ b/configs/sbc8349_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_33M"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig
index 6c0fd99f07..bf125a5623 100644
--- a/configs/sbc8349_PCI_66_defconfig
+++ b/configs/sbc8349_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,PCI_66M"
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig
index e22c70ad3d..daa2313f39 100644
--- a/configs/sbc8349_defconfig
+++ b/configs/sbc8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_SBC8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig
index 6d5b3f6c46..c5fc4a0e04 100644
--- a/configs/sbc8548_PCI_33_PCIE_defconfig
+++ b/configs/sbc8548_PCI_33_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig
index 8ecb12661a..1fd17cabb4 100644
--- a/configs/sbc8548_PCI_33_defconfig
+++ b/configs/sbc8548_PCI_33_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,33"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig
index bbea0cb4c3..5396e5aa8e 100644
--- a/configs/sbc8548_PCI_66_PCIE_defconfig
+++ b/configs/sbc8548_PCI_66_PCIE_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig
index f146b2d846..ffde0564b3 100644
--- a/configs/sbc8548_PCI_66_defconfig
+++ b/configs/sbc8548_PCI_66_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="PCI,66"
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig
index 3dea198cb6..a8a8a93ee1 100644
--- a/configs/sbc8548_defconfig
+++ b/configs/sbc8548_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC85xx=y
 CONFIG_TARGET_SBC8548=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig
index ad38457991..a382794dad 100644
--- a/configs/sbc8641d_defconfig
+++ b/configs/sbc8641d_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC86xx=y
 CONFIG_TARGET_SBC8641D=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig
index 4b73506c98..a3bf903ff1 100644
--- a/configs/sc_sps_1_defconfig
+++ b/configs/sc_sps_1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SC_SPS_1=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig
index 3f8648ddeb..9ffefbd433 100644
--- a/configs/seaboard_defconfig
+++ b/configs/seaboard_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/sequoia_defconfig b/configs/sequoia_defconfig
index 66d6a1aba3..8619c57f8f 100644
--- a/configs/sequoia_defconfig
+++ b/configs/sequoia_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/sequoia_ramboot_defconfig b/configs/sequoia_ramboot_defconfig
index 5c548ff279..81cda465a4 100644
--- a/configs/sequoia_ramboot_defconfig
+++ b/configs/sequoia_ramboot_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_SEQUOIA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/sh7752evb_defconfig b/configs/sh7752evb_defconfig
index 07594d1abb..f7e055b922 100644
--- a/configs/sh7752evb_defconfig
+++ b/configs/sh7752evb_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7752EVB=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7753evb_defconfig b/configs/sh7753evb_defconfig
index 5e7a9c9e04..fc6c7b1644 100644
--- a/configs/sh7753evb_defconfig
+++ b/configs/sh7753evb_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SH7753EVB=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7757lcr_defconfig b/configs/sh7757lcr_defconfig
index fafba4ce82..b0d3f28591 100644
--- a/configs/sh7757lcr_defconfig
+++ b/configs/sh7757lcr_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7757LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7785lcr_32bit_defconfig b/configs/sh7785lcr_32bit_defconfig
index cc31e1cb4d..d98e073e06 100644
--- a/configs/sh7785lcr_32bit_defconfig
+++ b/configs/sh7785lcr_32bit_defconfig
@@ -1,6 +1,7 @@
 CONFIG_SH=y
 CONFIG_SH_32BIT=y
 CONFIG_TARGET_SH7785LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sh7785lcr_defconfig b/configs/sh7785lcr_defconfig
index d7724b30d6..368cb3027b 100644
--- a/configs/sh7785lcr_defconfig
+++ b/configs/sh7785lcr_defconfig
@@ -1,5 +1,6 @@
 CONFIG_SH=y
 CONFIG_TARGET_SH7785LCR=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 71ce49c568..5cd37a430e 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_KIRKWOOD=y
 CONFIG_TARGET_SHEEVAPLUG=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 0beef09f05..f5d7afde58 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_SILK=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 2ec6e48868..1c29a290c0 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -4,6 +4,7 @@ CONFIG_TARGET_SMARTWEB=y
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig
index 702b36c012..4d40a29c14 100644
--- a/configs/smdk2410_defconfig
+++ b/configs/smdk2410_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_SMDK2410=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDK2410 # "
 CONFIG_CMD_USB=y
diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig
index 5d883918b1..7fe410d7b3 100644
--- a/configs/smdk5250_defconfig
+++ b/configs/smdk5250_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5250=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250"
diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig
index 40de7c149c..43d33894c8 100644
--- a/configs/smdk5420_defconfig
+++ b/configs/smdk5420_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SMDK5420=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420"
@@ -36,4 +37,6 @@ CONFIG_DM_REGULATOR=y
 CONFIG_EXYNOS_SPI=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_VIDEO_BRIDGE=y
diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig
index a989e244a6..0948534e89 100644
--- a/configs/smdkc100_defconfig
+++ b/configs/smdkc100_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_S5PC1XX=y
 CONFIG_TARGET_SMDKC100=y
 CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="SMDKC100 # "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig
index b8638e2ce3..5e3844cf47 100644
--- a/configs/smdkv310_defconfig
+++ b/configs/smdkv310_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
-CONFIG_TARGET_SMDKV310=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
 CONFIG_SPL=y
 CONFIG_HUSH_PARSER=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 2f8dd50ab3..166fd2f0e9 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Snapper> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index f72569323e..3cfe694d06 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_SNAPPER9260=y
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_IMI is not set
diff --git a/configs/snow_defconfig b/configs/snow_defconfig
index 97133dfe68..c16c90c453 100644
--- a/configs/snow_defconfig
+++ b/configs/snow_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SNOW=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow"
@@ -51,6 +52,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_S5P=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
@@ -64,6 +67,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index a662e72cc7..2478ae571d 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -53,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index b2933f778a..1619b86a9f 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -53,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index f197b6d2b0..43d939bbd1 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -47,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 6624f9e07d..c5c662b47e 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_DENX_MCVEVK=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -47,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="denx"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index c6414f8be5..1c4a40dd0e 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -53,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index b47a5602b8..e34d13e39a 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -53,3 +55,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="ebv"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index aab4498973..d1cfbcd7f8 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_SR1500=y
@@ -9,6 +10,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
@@ -42,3 +44,4 @@ CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
new file mode 100644
index 0000000000..80552a5be2
--- /dev/null
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -0,0 +1,58 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SAMTEC_VINING_FPGA=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="samtec"
+CONFIG_G_DNL_VENDOR_NUM=0x0525
+CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
+CONFIG_USE_TINY_PRINTF=y
diff --git a/configs/spring_defconfig b/configs/spring_defconfig
index b720e040d3..b68cab0543 100644
--- a/configs/spring_defconfig
+++ b/configs/spring_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS5=y
 CONFIG_TARGET_SPRING=y
 CONFIG_DM_I2C=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos5250-spring"
@@ -51,6 +52,8 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_MAX77686=y
 CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_EXYNOS=y
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_S5P=y
 CONFIG_DEBUG_UART_BASE=0x12c30000
@@ -64,6 +67,8 @@ CONFIG_EXYNOS_SPI=y
 CONFIG_TPM_TIS_INFINEON=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
 CONFIG_VIDEO_BRIDGE=y
 CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y
 CONFIG_TPM=y
diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig
index 86dfd0e83f..ae9976bb6e 100644
--- a/configs/stm32f429-discovery_defconfig
+++ b/configs/stm32f429-discovery_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F4=y
 CONFIG_TARGET_STM32F429_DISCOVERY=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index 00482269c2..e3e6333add 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_STM32=y
 CONFIG_STM32F7=y
 CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot > "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index a8f59ca86c..9073c17875 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_RMOBILE=y
 CONFIG_TARGET_STOUT=y
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
 # CONFIG_CMD_BOOTD is not set
diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig
index 985aab8da2..6253615eb5 100644
--- a/configs/strider_con_defconfig
+++ b/configs/strider_con_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig
new file mode 100644
index 0000000000..3d325f4346
--- /dev/null
+++ b/configs/strider_con_dp_defconfig
@@ -0,0 +1,21 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig
index 2766104a4c..160df247f1 100644
--- a/configs/strider_cpu_defconfig
+++ b/configs/strider_cpu_defconfig
@@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_STOP_STR=" "
diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig
new file mode 100644
index 0000000000..2a2733dfba
--- /dev/null
+++ b/configs/strider_cpu_dp_defconfig
@@ -0,0 +1,21 @@
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_STRIDER=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
+CONFIG_BOOTDELAY=5
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig
index 6a3b5b8357..40ca293bad 100644
--- a/configs/stv0991_defconfig
+++ b/configs/stv0991_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_STV0991=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="stv0991"
 CONFIG_SYS_EXTRA_OPTIONS="stv0991"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="STV0991> "
 CONFIG_AUTOBOOT_KEYED=y
 CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig
index 3677da7e5a..5861cff64d 100644
--- a/configs/sunxi_Gemei_G9_defconfig
+++ b/configs/sunxi_Gemei_G9_defconfig
@@ -1,6 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SUNXI=y
-CONFIG_MACH_SUN4I=y
 CONFIG_DRAM_CLK=432
 CONFIG_DRAM_EMR1=4
 CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:18,pclk_khz:100000,le:799,ri:260,up:15,lo:16,hs:1,vs:1,sync:3,vmode:0"
@@ -11,18 +10,7 @@ CONFIG_VIDEO_LCD_PANEL_LVDS=y
 CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-gemei-g9"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_I2C=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/sycamore_defconfig b/configs/sycamore_defconfig
index 9fdb2b3722..5f7b40d896 100644
--- a/configs/sycamore_defconfig
+++ b/configs/sycamore_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig
index c5562c936d..750599689f 100644
--- a/configs/t3corp_defconfig
+++ b/configs/t3corp_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_T3CORP=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig
index 6d0877d165..4ee5737ccc 100644
--- a/configs/tao3530_defconfig
+++ b/configs/tao3530_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_OMAP34XX=y
 CONFIG_TARGET_TAO3530=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="TAO-3530 # "
 # CONFIG_CMD_IMI is not set
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 20f33a8528..e566f7f023 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y
 CONFIG_TARGET_TAURUS=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/tb100_defconfig b/configs/tb100_defconfig
index 83b1b56c57..2d157b2b3e 100644
--- a/configs/tb100_defconfig
+++ b/configs/tb100_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_SYS_CLK_FREQ=500000000
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="abilis_tb100"
+CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="[tb100]:~# "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig
index b7102298e3..7dbb4cd8d4 100644
--- a/configs/tec-ng_defconfig
+++ b/configs/tec-ng_defconfig
@@ -35,4 +35,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SLINK=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/tec_defconfig b/configs/tec_defconfig
index 2055101399..742d90d1c0 100644
--- a/configs/tec_defconfig
+++ b/configs/tec_defconfig
@@ -34,4 +34,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
index 83587575c5..05368bdfa0 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
index 157985f34b..17bf8cd78e 100644
--- a/configs/theadorable_defconfig
+++ b/configs/theadorable_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index f9391f2f11..0b69c075d6 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_THUBAN=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot# "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig
index b7078e0390..4a8655f9bb 100644
--- a/configs/thunderx_88xx_defconfig
+++ b/configs/thunderx_88xx_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_THUNDERX_88XX=y
 CONFIG_DM_SERIAL=y
 CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx"
 CONFIG_SYS_EXTRA_OPTIONS="ARM64"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ThunderX_88XX> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 4eb7923723..c4240e900a 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_TI816X_EVM=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="u-boot/ti816x# "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
index b1af2f6f35..a69c0b63b1 100644
--- a/configs/tplink_wdr4300_defconfig
+++ b/configs/tplink_wdr4300_defconfig
@@ -1,34 +1,24 @@
 CONFIG_MIPS=y
-CONFIG_ARCH_ATH79=y
-CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_NS16550=y
 CONFIG_DM_SERIAL=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+CONFIG_BOOTDELAY=3
 # CONFIG_CMD_ELF is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
 # CONFIG_CMD_FPGA is not set
-CONFIG_CMD_NET=y
-CONFIG_CMD_NFS=y
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_PING=y
 CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_ETH=y
-CONFIG_AG7XXX=y
 CONFIG_CLK=y
-CONFIG_CMD_USB=y
-CONFIG_USB=y
-CONFIG_DM_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_ATH79_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
@@ -40,4 +30,13 @@ CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_DATAFLASH=y
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
 CONFIG_PINCTRL=y
+CONFIG_SYS_NS16550=y
+CONFIG_ATH79_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index c2ed8c8adf..1362ffb7b8 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_TRATS2=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4412-trats2"
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 46bfc4e71c..525bbefa14 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_EXYNOS=y
+CONFIG_ARCH_EXYNOS4=y
 CONFIG_TARGET_TRATS=y
 CONFIG_DEFAULT_DEVICE_TREE="exynos4210-trats"
 CONFIG_FIT=y
diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig
index 67857a5024..72e641d9f6 100644
--- a/configs/trimslice_defconfig
+++ b/configs/trimslice_defconfig
@@ -36,4 +36,3 @@ CONFIG_SYS_NS16550=y
 CONFIG_TEGRA20_SFLASH=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/twister_defconfig b/configs/twister_defconfig
index ffbc025124..0e57f7c852 100644
--- a/configs/twister_defconfig
+++ b/configs/twister_defconfig
@@ -3,6 +3,7 @@ CONFIG_OMAP34XX=y
 CONFIG_TARGET_TWISTER=y
 CONFIG_SPL=y
 CONFIG_FIT=y
+CONFIG_BOOTDELAY=10
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="twister => "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/uniphier_ld11_defconfig b/configs/uniphier_ld11_defconfig
new file mode 100644
index 0000000000..e7f9b15a21
--- /dev/null
+++ b/configs/uniphier_ld11_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_ARCH_UNIPHIER=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ARCH_UNIPHIER_LD11=y
+CONFIG_MICRO_SUPPORT_CARD=y
+CONFIG_SYS_TEXT_BASE=0x84000000
+CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld11-ref"
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_GPIO_UNIPHIER=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig
index cbc65ddc8d..d073e3d127 100644
--- a/configs/uniphier_ld20_defconfig
+++ b/configs/uniphier_ld20_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD20=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_XIMG is not set
 # CONFIG_CMD_ENV_EXISTS is not set
diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig
index 22615a647c..04d651d358 100644
--- a/configs/uniphier_ld4_sld8_defconfig
+++ b/configs/uniphier_ld4_sld8_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_LD4_SLD8=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pro4_defconfig b/configs/uniphier_pro4_defconfig
index 18f4caf33b..d5fc13829f 100644
--- a/configs/uniphier_pro4_defconfig
+++ b/configs/uniphier_pro4_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_pxs2_ld6b_defconfig b/configs/uniphier_pxs2_ld6b_defconfig
index cf6d3e4231..285ea98553 100644
--- a/configs/uniphier_pxs2_ld6b_defconfig
+++ b/configs/uniphier_pxs2_ld6b_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_UNIPHIER_PRO5_PXS2_LD6B=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-proxstream2-vodka"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
index 0965019318..13f31470f0 100644
--- a/configs/uniphier_sld3_defconfig
+++ b/configs/uniphier_sld3_defconfig
@@ -4,6 +4,7 @@ CONFIG_ARCH_UNIPHIER_SLD3=y
 CONFIG_MICRO_SUPPORT_CARD=y
 CONFIG_SYS_TEXT_BASE=0x84000000
 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_XIMG is not set
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index fa5561aeb3..916a9c6922 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_USB_A9263=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="U-Boot> "
 # CONFIG_CMD_BDI is not set
diff --git a/configs/v38b_defconfig b/configs/v38b_defconfig
index 4dd26123ff..a54999c7ce 100644
--- a/configs/v38b_defconfig
+++ b/configs/v38b_defconfig
@@ -1,6 +1,7 @@
 CONFIG_PPC=y
 CONFIG_MPC5xxx=y
 CONFIG_TARGET_V38B=y
+CONFIG_BOOTDELAY=3
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig
index ed27d853c2..c65a20014b 100644
--- a/configs/vct_platinum_defconfig
+++ b/configs/vct_platinum_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -10,4 +11,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig
index 82708f0da2..23bfe4ad66 100644
--- a/configs/vct_platinum_onenand_defconfig
+++ b/configs/vct_platinum_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -13,4 +14,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig
index 7b379be2cc..3306a45e48 100644
--- a/configs/vct_platinum_onenand_small_defconfig
+++ b/configs/vct_platinum_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig
index 78d215d54c..06476139ca 100644
--- a/configs/vct_platinum_small_defconfig
+++ b/configs/vct_platinum_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUM=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig
index c47f1026df..1660c662e8 100644
--- a/configs/vct_platinumavc_defconfig
+++ b/configs/vct_platinumavc_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="VCT# "
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
@@ -8,4 +9,3 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig
index e7aef319c5..55dfd4cd49 100644
--- a/configs/vct_platinumavc_onenand_defconfig
+++ b/configs/vct_platinumavc_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -11,4 +12,3 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_DHCP=y
 # CONFIG_CMD_NFS is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig
index be70588cf0..98b5ea217c 100644
--- a/configs/vct_platinumavc_onenand_small_defconfig
+++ b/configs/vct_platinumavc_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig
index b7e0a782fb..f4a95493db 100644
--- a/configs/vct_platinumavc_small_defconfig
+++ b/configs/vct_platinumavc_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PLATINUMAVC=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig
index 29d16e3aa1..f85deb38cf 100644
--- a/configs/vct_premium_defconfig
+++ b/configs/vct_premium_defconfig
@@ -1,6 +1,7 @@
 CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
@@ -10,4 +11,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig
index 31b89e3718..11879e5bb9 100644
--- a/configs/vct_premium_onenand_defconfig
+++ b/configs/vct_premium_onenand_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_ONENAND=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
@@ -13,4 +14,3 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_FAT=y
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig
index a3a93b84cd..ff5e7a68cd 100644
--- a/configs/vct_premium_onenand_small_defconfig
+++ b/configs/vct_premium_onenand_small_defconfig
@@ -3,6 +3,7 @@ CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_ONENAND=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -19,4 +20,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig
index fddc04d75d..c601676bcb 100644
--- a/configs/vct_premium_small_defconfig
+++ b/configs/vct_premium_small_defconfig
@@ -2,6 +2,7 @@ CONFIG_MIPS=y
 CONFIG_TARGET_VCT=y
 CONFIG_VCT_PREMIUM=y
 CONFIG_VCT_SMALL_IMAGE=y
+CONFIG_BOOTDELAY=5
 CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_BDI is not set
 # CONFIG_CMD_CONSOLE is not set
@@ -16,4 +17,3 @@ CONFIG_SYS_PROMPT="$ "
 # CONFIG_CMD_NFS is not set
 # CONFIG_CMD_MISC is not set
 CONFIG_SYS_NS16550=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig
index 4ae35505b1..faeb15cc16 100644
--- a/configs/ve8313_defconfig
+++ b/configs/ve8313_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VE8313=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index 17a6000d77..edbb18fb6a 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -42,4 +42,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="NVIDIA"
 CONFIG_G_DNL_VENDOR_NUM=0x0955
 CONFIG_G_DNL_PRODUCT_NUM=0x701a
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig
index 97b13a1b1d..aeb9025032 100644
--- a/configs/ventana_defconfig
+++ b/configs/ventana_defconfig
@@ -33,4 +33,3 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_DM_VIDEO=y
 CONFIG_VIDEO_TEGRA20=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index c014294ae7..63a6ab97df 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_MMC"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index d50ad90787..f66ff4aec6 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -4,6 +4,7 @@ CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="vf610-twr"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/vf610twr/imximage.cfg,ENV_IS_IN_NAND"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index e79cc4d21b..0a373a3995 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
 CONFIG_TARGET_VINCO=y
 CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="vinco => "
 CONFIG_CMD_BOOTZ=y
diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig
index 887afdf9f2..b23f2356dc 100644
--- a/configs/vme8349_defconfig
+++ b/configs/vme8349_defconfig
@@ -3,6 +3,7 @@ CONFIG_MPC83xx=y
 CONFIG_TARGET_VME8349=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=6
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/walnut_defconfig b/configs/walnut_defconfig
index 9fdb2b3722..5f7b40d896 100644
--- a/configs/walnut_defconfig
+++ b/configs/walnut_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_WALNUT=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/whistler_defconfig b/configs/whistler_defconfig
index ca753a4541..754e5cb46a 100644
--- a/configs/whistler_defconfig
+++ b/configs/whistler_defconfig
@@ -29,4 +29,3 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y
-CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index b4660cdb9b..a2e5957610 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_MMC=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index bb1ef0aa18..3b381302e6 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -2,6 +2,7 @@ CONFIG_ARM=y
 CONFIG_TARGET_WOODBURN_SD=y
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="woodburn U-Boot > "
 CONFIG_CMD_MMC=y
diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig
index 5663b2f361..e9fa7734e6 100644
--- a/configs/work_92105_defconfig
+++ b/configs/work_92105_defconfig
@@ -5,6 +5,7 @@ CONFIG_SPL_DM=y
 CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/wtk_defconfig b/configs/wtk_defconfig
index 9341087de2..336d8e42bf 100644
--- a/configs/wtk_defconfig
+++ b/configs/wtk_defconfig
@@ -3,6 +3,7 @@ CONFIG_8xx=y
 CONFIG_TARGET_TQM823L=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="LCD,SHARP_LQ065T9DR51U"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 # CONFIG_CMD_SETEXPR is not set
diff --git a/configs/x600_defconfig b/configs/x600_defconfig
index ace620ba3a..b91a711169 100644
--- a/configs/x600_defconfig
+++ b/configs/x600_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_X600=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="X600> "
 CONFIG_AUTOBOOT_KEYED=y
@@ -22,3 +23,4 @@ CONFIG_NETDEVICES=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_USE_TINY_PRINTF=y
 CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig
index 59e1014a3a..31a647e2e7 100644
--- a/configs/xfi3_defconfig
+++ b/configs/xfi3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_XFI3=y
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig
index 6c021d7076..8e07d4001e 100644
--- a/configs/xilinx-ppc405-generic_defconfig
+++ b/configs/xilinx-ppc405-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc405-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="xlx-ppc405:/# "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig
index ab0ea5a718..7f085de146 100644
--- a/configs/xilinx-ppc440-generic_defconfig
+++ b/configs/xilinx-ppc440-generic_defconfig
@@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="board:/# "
 CONFIG_CMD_ASKENV=y
diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig
index b185593dc9..7325f190f0 100644
--- a/configs/xilinx_zynqmp_ep_defconfig
+++ b/configs/xilinx_zynqmp_ep_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_ep"
 CONFIG_ARCH_ZYNQMP=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
@@ -9,6 +9,8 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_CONSOLE is not set
@@ -19,6 +21,7 @@ CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_LOADB is not set
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
@@ -40,13 +43,24 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_NAND_ARASAN=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_GADGET=y
@@ -55,3 +69,4 @@ CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03fd
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
 # CONFIG_REGEX is not set
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
index cc08b03842..91af8ce326 100644
--- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm015_dc1"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
@@ -8,6 +9,9 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -30,6 +34,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
@@ -40,7 +46,14 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
@@ -50,3 +63,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
index 14d24a03bf..3e7331257c 100644
--- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm016_dc2"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
@@ -8,10 +9,14 @@ CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_NAND=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
@@ -29,6 +34,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_NAND_ARASAN=y
@@ -37,7 +44,14 @@ CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
@@ -47,3 +61,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
new file mode 100644
index 0000000000..2805219f7b
--- /dev/null
+++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4"
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_DM_I2C=y
+CONFIG_DM_GPIO=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_DM_MMC=y
+CONFIG_ZYNQ_SDHCI=y
+CONFIG_DM_ETH=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
index e1e11b7011..32bea4b20d 100644
--- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
+++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig
@@ -1,12 +1,16 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm019_dc5"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_I2C=y
 CONFIG_DM_GPIO=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -25,7 +29,10 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_SYS_I2C_CADENCE=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_DM_ETH=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig
index 6f1cff8c65..d7eb8c2730 100644
--- a/configs/xilinx_zynqmp_zcu102_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_defconfig
@@ -1,12 +1,16 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -29,6 +33,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
@@ -38,7 +44,14 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
@@ -48,3 +61,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig
index a8982a04a5..80a59ef07d 100644
--- a/configs/xilinx_zynqmp_zcu102_revB_defconfig
+++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig
@@ -1,12 +1,16 @@
 CONFIG_ARM=y
 CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102"
 CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_DM_GPIO=y
 CONFIG_ZYNQMP_USB=y
 CONFIG_SYS_TEXT_BASE=0x8000000
 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revB"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="ZynqMP> "
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_MEMTEST=y
@@ -29,6 +33,8 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_EMBED=y
 CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
 CONFIG_DM_MMC=y
 CONFIG_ZYNQ_SDHCI=y
 CONFIG_SPI_FLASH=y
@@ -38,7 +44,14 @@ CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_DM_ETH=y
 CONFIG_ZYNQ_GEM=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC3_GADGET=y
 CONFIG_USB_ULPI_VIEWPORT=y
@@ -48,3 +61,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_G_DNL_MANUFACTURER="Xilinx"
 CONFIG_G_DNL_VENDOR_NUM=0x03FD
 CONFIG_G_DNL_PRODUCT_NUM=0x0300
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xpedite1000_defconfig b/configs/xpedite1000_defconfig
index 4c0e58ec0b..f023c73084 100644
--- a/configs/xpedite1000_defconfig
+++ b/configs/xpedite1000_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_XPEDITE1000=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite517x_defconfig b/configs/xpedite517x_defconfig
index b0e92e0308..2839bc6b2a 100644
--- a/configs/xpedite517x_defconfig
+++ b/configs/xpedite517x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite520x_defconfig b/configs/xpedite520x_defconfig
index 4a328cd228..c3b91f4e95 100644
--- a/configs/xpedite520x_defconfig
+++ b/configs/xpedite520x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite537x_defconfig b/configs/xpedite537x_defconfig
index e0fe947ecb..5ababef491 100644
--- a/configs/xpedite537x_defconfig
+++ b/configs/xpedite537x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/xpedite550x_defconfig b/configs/xpedite550x_defconfig
index e16c8c8fd1..f893abf5ed 100644
--- a/configs/xpedite550x_defconfig
+++ b/configs/xpedite550x_defconfig
@@ -5,6 +5,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_I2C=y
diff --git a/configs/yellowstone_defconfig b/configs/yellowstone_defconfig
index 00992e0c0c..059ff71175 100644
--- a/configs/yellowstone_defconfig
+++ b/configs/yellowstone_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YELLOWSTONE"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/yosemite_defconfig b/configs/yosemite_defconfig
index 3a803f6160..df37b909b9 100644
--- a/configs/yosemite_defconfig
+++ b/configs/yosemite_defconfig
@@ -3,6 +3,7 @@ CONFIG_4xx=y
 CONFIG_TARGET_YOSEMITE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="YOSEMITE"
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/yucca_defconfig b/configs/yucca_defconfig
index e219fd2a34..d3ccad7d09 100644
--- a/configs/yucca_defconfig
+++ b/configs/yucca_defconfig
@@ -2,6 +2,7 @@ CONFIG_PPC=y
 CONFIG_4xx=y
 CONFIG_TARGET_YUCCA=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_GREPENV=y
diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig
index 9368610f2e..42e38da55c 100644
--- a/configs/zmx25_defconfig
+++ b/configs/zmx25_defconfig
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_ZMX25=y
+CONFIG_BOOTDELAY=5
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="zmx25> "
 CONFIG_AUTOBOOT_KEYED=y
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index 7c66247d3e..d88c61bf4e 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_microzed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_MICROZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-microzed"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig
index b46ab44b78..aeb127020f 100644
--- a/configs/zynq_picozed_defconfig
+++ b/configs/zynq_picozed_defconfig
@@ -1,8 +1,9 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_picozed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_PICOZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed"
 CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig
index 052679a1dc..d68ed0edff 100644
--- a/configs/zynq_zc702_defconfig
+++ b/configs/zynq_zc702_defconfig
@@ -1,10 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc702"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig
index 3539f0547f..8bd9230580 100644
--- a/configs/zynq_zc706_defconfig
+++ b/configs/zynq_zc706_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc70x"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC706=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig
index 6a4726cb9a..81f16ec158 100644
--- a/configs/zynq_zc770_xm010_defconfig
+++ b/configs/zynq_zc770_xm010_defconfig
@@ -1,12 +1,13 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm010"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig
index 46dd6bee19..271fcfd538 100644
--- a/configs/zynq_zc770_xm011_defconfig
+++ b/configs/zynq_zc770_xm011_defconfig
@@ -1,12 +1,13 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig
index 12f0e2ca3b..a9ea971126 100644
--- a/configs/zynq_zc770_xm012_defconfig
+++ b/configs/zynq_zc770_xm012_defconfig
@@ -1,12 +1,13 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm012"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 CONFIG_CMD_GPIO=y
diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig
index 8c7efe5320..56062b18a8 100644
--- a/configs/zynq_zc770_xm013_defconfig
+++ b/configs/zynq_zc770_xm013_defconfig
@@ -1,12 +1,13 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zc770"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZC770=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
 CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013"
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig
index 7976e07c3b..c70b860b62 100644
--- a/configs/zynq_zed_defconfig
+++ b/configs/zynq_zed_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zed"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZED=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zed"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig
index cd222c5a7b..624545edaa 100644
--- a/configs/zynq_zybo_defconfig
+++ b/configs/zynq_zybo_defconfig
@@ -1,11 +1,12 @@
 CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="zynq_zybo"
 CONFIG_ARCH_ZYNQ=y
-CONFIG_TARGET_ZYNQ_ZYBO=y
 CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
 CONFIG_SPL=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTDELAY=3
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
diff --git a/disk/part_efi.c b/disk/part_efi.c
index fe308d76a9..0af1e9248d 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -439,7 +439,7 @@ int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
 			gpt_e[i].starting_lba = cpu_to_le64(offset);
 			offset += partitions[i].size;
 		}
-		if (offset >= last_usable_lba) {
+		if (offset > (last_usable_lba + 1)) {
 			printf("Partitions layout exceds disk size\n");
 			return -1;
 		}
diff --git a/doc/README.fdt-control b/doc/README.fdt-control
index 29fd56a815..2913fcb360 100644
--- a/doc/README.fdt-control
+++ b/doc/README.fdt-control
@@ -33,12 +33,6 @@ the features of each board in the device tree file, and have a single
 generic source base.
 
 To enable this feature, add CONFIG_OF_CONTROL to your board config file.
-It is currently supported on ARM, x86 and Microblaze - other architectures
-will need to add code to their arch/xxx/lib/board.c file to locate the
-FDT. Alternatively you can enable generic board support on your board
-(with CONFIG_SYS_GENERIC_BOARD) if this is available (as it is for
-PowerPC). For ARM, Tegra and Exynos5 have device trees available for
-common devices.
 
 
 What is a Flat Device Tree?
diff --git a/doc/README.generic-board b/doc/README.generic-board
index 734f1aa924..6858c4daaf 100644
--- a/doc/README.generic-board
+++ b/doc/README.generic-board
@@ -5,29 +5,22 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-DEPRECATION NOTICE FOR arch/<arch>/lib/board.c
-
-For board maintainers: Please submit patches for boards you maintain before
-July 2014, to make them use generic board.
-
-For architecture maintainers: Please submit patches to remove your
-architecture-specific board.c file before October 2014.
-
-
 Background
 ----------
 
-U-Boot has traditionally had a board.c file for each architecture. This has
-introduced quite a lot of duplication, with each architecture tending to do
+U-Boot traditionally had a board.c file for each architecture. This introduced
+quite a lot of duplication, with each architecture tending to do
 initialisation slightly differently. To address this, a new 'generic board
-init' feature was introduced a year ago in March 2013 (further motivation is
+init' feature was introduced in March 2013 (further motivation is
 provided in the cover letter below).
 
+All boards and architectures have moved to this as of mid 2016.
+
 
 What has changed?
 -----------------
 
-The main change is that the arch/<arch>/lib/board.c file is being removed in
+The main change is that the arch/<arch>/lib/board.c file is removed in
 favour of common/board_f.c (for pre-relocation init) and common/board_r.c
 (for post-relocation init).
 
@@ -36,55 +29,6 @@ fields which are common to all architectures. Architecture-specific fields
 have been moved to separate structures.
 
 
-Supported Architectures
-------------------------
-
-If you are unlucky then your architecture may not support generic board.
-The following architectures are supported now:
-
-   arc
-   arm
-   avr32
-   blackfin
-   m68k
-   microblaze
-   mips
-   nios2
-   powerpc
-   sandbox
-   x86
-
-If your architecture is not supported, you need to select
-HAVE_GENERIC_BOARD in arch/Kconfig
-and test it with a suitable board, as follows.
-
-
-Adding Support for your Board
------------------------------
-
-To enable generic board for your board, define CONFIG_SYS_GENERIC_BOARD in
-your board config header file.
-
-Test that U-Boot still functions correctly on your board, and fix any
-problems you find. Don't be surprised if there are no problems - generic
-board has had a reasonable amount of testing with common boards.
-
-
-DeadLine
---------
-
-Please don't take this the wrong way - there is no intent to make your life
-miserable, and we have the greatest respect and admiration for U-Boot users.
-However, with any migration there has to be a period where the old way is
-deprecated and removed. Every patch to the deprecated code introduces a
-potential breakage in the new unused code. Therefore:
-
-Boards or architectures not converted over to general board by the
-end of 2014 may be forcibly changed over (potentially causing run-time
-breakage) or removed.
-
-
-
 Further Background
 ------------------
 
@@ -190,3 +134,4 @@ convenience.
 
 Simon Glass, sjg@chromium.org
 March 2014
+Updated after final removal, May 2016
diff --git a/doc/README.nand b/doc/README.nand
index 545d88ca68..96ffc48940 100644
--- a/doc/README.nand
+++ b/doc/README.nand
@@ -136,15 +136,8 @@ Configuration Options:
       Example of new init to be added to the end of an existing driver
       init:
 
-	/*
-	 * devnum is the device number to be used in nand commands
-	 * and in mtd->name.  Must be less than
-	 * CONFIG_SYS_NAND_MAX_DEVICE.
-	 */
-	mtd = &nand_info[devnum];
-
 	/* chip is struct nand_chip, and is now provided by the driver. */
-	mtd->priv = &chip;
+	mtd = &chip.mtd;
 
 	/*
 	 * Fill in appropriate values if this driver uses these fields,
@@ -165,7 +158,11 @@ Configuration Options:
 	if (nand_scan_tail(mtd))
 		error out
 
-	if (nand_register(devnum))
+	/*
+	 * devnum is the device number to be used in nand commands
+	 * and in mtd->name.  Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
+	 */
+	if (nand_register(devnum, mtd))
 		error out
 
       In addition to providing more flexibility to the driver, it reduces
diff --git a/doc/README.ti-secure b/doc/README.ti-secure
new file mode 100644
index 0000000000..7fc9b9bc30
--- /dev/null
+++ b/doc/README.ti-secure
@@ -0,0 +1,91 @@
+README on how boot images are created for secure TI devices
+
+CONFIG_TI_SECURE_DEVICE:
+Secure TI devices require a boot image that is authenticated by ROM
+code to function. Without this, even JTAG remains locked and the
+device is essentially useless. In order to create a valid boot image for
+a secure device from TI, the initial public software image must be signed
+and combined with various headers, certificates, and other binary images.
+
+Information on the details on the complete boot image format can be obtained
+from Texas Instruments. The tools used to generate boot images for secure
+devices are part of a secure development package (SECDEV) that can be
+downloaded from:
+
+	http://www.ti.com/mysecuresoftware (login required)
+
+The secure development package is access controlled due to NDA and export
+control restrictions. Access must be requested and granted by TI before the
+package is viewable and downloadable. Contact TI, either online or by way
+of a local TI representative, to request access.
+
+When CONFIG_TI_SECURE_DEVICE is set, the U-Boot SPL build process requires
+the presence and use of these tools in order to create a viable boot image.
+The build process will look for the environment variable TI_SECURE_DEV_PKG,
+which should be the path of the installed SECDEV package. If the
+TI_SECURE_DEV_PKG variable is not defined or if it is defined but doesn't
+point to a valid SECDEV package, a warning is issued during the build to
+indicate that a final secure bootable image was not created.
+
+Within the SECDEV package exists an image creation script:
+
+${TI_SECURE_DEV_PKG}/scripts/create-boot-image.sh
+
+This is called as part of the SPL/u-boot build process. As the secure boot
+image formats and requirements differ between secure SOC from TI, the
+purpose of this script is to abstract these details as much as possible.
+
+The script is basically the only required interface to the TI SECDEV package
+for secure TI devices.
+
+Invoking the script for AM43xx Secure Devices
+=============================================
+
+create-boot-image.sh <IMAGE_FLAG> <INPUT_FILE> <OUTPUT_FILE> <SPL_LOAD_ADDR>
+
+<IMAGE_FLAG> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+	SPI_X-LOADER - Generates an image for SPI flash (byte swapped)
+	XIP_X-LOADER - Generates a single stage u-boot for NOR/QSPI XiP
+	ISSW - Generates an image for all other boot modes
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (depending on the boot media, this is usually either
+u-boot-spl.bin or u-boot.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+	u-boot-spl_HS_SPI_X-LOADER - byte swapped boot image for SPI flash
+	u-boot_HS_XIP_X-LOADER - boot image for NOR or QSPI flash
+	u-boot-spl_HS_ISSW - boot image for all other boot media
+
+<SPL_LOAD_ADDR> is the address at which SOC ROM should load the <INPUT_FILE>
+
+Invoking the script for DRA7xx/AM57xx Secure Devices
+====================================================
+
+create-boot-image.sh <IMAGE_TYPE> <INPUT_FILE> <OUTPUT_FILE>
+
+<IMAGE_TYPE> is a value that specifies the type of the image to generate OR
+the action the image generation tool will take. Valid values are:
+	X-LOADER - Generates an image for NOR or QSPI boot modes
+	MLO - Generates an image for SD/MMC/eMMC boot modes
+	ULO - Generates an image for USB/UART peripheral boot modes
+	Note: ULO is not yet used by the u-boot build process
+
+<INPUT_FILE> is the full path and filename of the public world boot loader
+binary file (for this platform, this is always u-boot-spl.bin).
+
+<OUTPUT_FILE> is the full path and filename of the final secure image. The
+output binary images should be used in place of the standard non-secure
+binary images (see the platform-specific user's guides and releases notes
+for how the non-secure images are typically used)
+	u-boot-spl_HS_MLO - boot image for SD/MMC/eMMC. This image is
+		copied to a file named MLO, which is the name that
+		the device ROM bootloader requires for loading from
+		the FAT partition of an SD card (same as on
+		non-secure devices)
+	u-boot-spl_HS_X-LOADER - boot image for all other flash memories
+		including QSPI and NOR flash
diff --git a/doc/README.x86 b/doc/README.x86
index c5c3010ee2..a548b54b5b 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -23,7 +23,8 @@ In this case, known as bare mode, from the fact that it runs on the
 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
 are supported:
 
-   - Bayley Bay
+   - Bayley Bay CRB
+   - Congatec QEVAL 2.0 & conga-QA3/E3845
    - Cougar Canyon 2 CRB
    - Crown Bay CRB
    - Galileo
@@ -303,12 +304,12 @@ Offset   Description         Controlling config
 000000   descriptor.bin      Hard-coded to 0 in ifdtool
 001000   me.bin              Set by the descriptor
 500000   <spare>
+6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
 790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
-7fe000   Environment         CONFIG_ENV_OFFSET
 7ff800   U-Boot 16-bit boot  CONFIG_SYS_X86_START16
 
 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
@@ -412,18 +413,19 @@ If you want to check both consoles, use '-serial stdio'.
 Multicore is also supported by QEMU via '-smp n' where n is the number of cores
 to instantiate. Note, the maximum supported CPU number in QEMU is 255.
 
-The fw_cfg interface in QEMU also provides information about kernel data, initrd,
-command-line arguments and more. U-Boot supports directly accessing these informtion
-from fw_cfg interface, this saves the time of loading them from hard disk or
-network again, through emulated devices. To use it , simply providing them in
-QEMU command line:
+The fw_cfg interface in QEMU also provides information about kernel data,
+initrd, command-line arguments and more. U-Boot supports directly accessing
+these informtion from fw_cfg interface, which saves the time of loading them
+from hard disk or network again, through emulated devices. To use it , simply
+providing them in QEMU command line:
 
 $ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024 -kernel /path/to/bzImage
     -append 'root=/dev/ram console=ttyS0' -initrd /path/to/initrd -smp 8
 
 Note: -initrd and -smp are both optional
 
-Then start QEMU, in U-Boot command line use the following U-Boot command to setup kernel:
+Then start QEMU, in U-Boot command line use the following U-Boot command to
+setup kernel:
 
  => qfw
 qfw - QEMU firmware interface
@@ -437,8 +439,8 @@ qfw <command>
 => qfw load
 loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
 
-Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then, 'zboot'
-can be used to boot the kernel:
+Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
+'zboot' can be used to boot the kernel:
 
 => zboot 02000000 - 04000000 1b1ab50
 
@@ -490,8 +492,8 @@ Booting Ubuntu
 --------------
 As an example of how to set up your boot flow with U-Boot, here are
 instructions for starting Ubuntu from U-Boot. These instructions have been
-tested on Minnowboard MAX with a SATA driver but are equally applicable on
-other platforms and other media. There are really only four steps and its a
+tested on Minnowboard MAX with a SATA drive but are equally applicable on
+other platforms and other media. There are really only four steps and it's a
 very simple script, but a more detailed explanation is provided here for
 completeness.
 
@@ -499,7 +501,7 @@ Note: It is possible to set up U-Boot to boot automatically using syslinux.
 It could also use the grub.cfg file (/efi/ubuntu/grub.cfg) to obtain the
 GUID. If you figure these out, please post patches to this README.
 
-Firstly, you will need Ubunutu installed on an available disk. It should be
+Firstly, you will need Ubuntu installed on an available disk. It should be
 possible to make U-Boot start a USB start-up disk but for now let's assume
 that you used another boot loader to install Ubuntu.
 
@@ -659,7 +661,7 @@ U-Boot:
    Loading bzImage at address 100000 (5805728 bytes)
    Magic signature found
    Initial RAM disk at linear address 0x04000000, size 19215259 bytes
-   Kernel command line: "console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
+   Kernel command line: "root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro"
 
    Starting kernel ...
 
@@ -679,13 +681,14 @@ above commands into a script since then it will be faster.
                   240,329  ahci
                 1,422,704  vesa display
 
-Now the kernel actually starts:
+Now the kernel actually starts: (if you want to examine kernel boot up message
+on the serial console, append "console=ttyS0,115200" to the kernel command line)
 
    [    0.000000] Initializing cgroup subsys cpuset
    [    0.000000] Initializing cgroup subsys cpu
    [    0.000000] Initializing cgroup subsys cpuacct
    [    0.000000] Linux version 3.13.0-58-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #97-Ubuntu SMP Wed Jul 8 02:56:15 UTC 2015 (Ubuntu 3.13.0-58.97-generic 3.13.11-ckt22)
-   [    0.000000] Command line: console=ttyS0,115200 root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro
+   [    0.000000] Command line: root=/dev/disk/by-partuuid/965c59ee-1822-4326-90d2-b02446050059 ro console=ttyS0,115200
 
 It continues for a long time. Along the way you will see it pick up your
 ramdisk:
@@ -736,14 +739,6 @@ If you want to put this in a script you can use something like this:
 The \ is to tell the shell not to evaluate ${filesize} as part of the setenv
 command.
 
-You will also need to add this to your board configuration file, e.g.
-include/configs/minnowmax.h:
-
-   #define CONFIG_BOOTDELAY	2
-
-Now when you reset your board it wait a few seconds (in case you want to
-interrupt) and then should boot straight into Ubuntu.
-
 You can also bake this behaviour into your build by hard-coding the
 environment variables if you add this to minnowmax.h:
 
@@ -812,6 +807,30 @@ to install/boot a Windows XP OS (below for example command to install Windows).
 This is also tested on Intel Crown Bay board with a PCIe graphics card, booting
 SeaBIOS then chain-loading a GRUB on a USB drive, then Linux kernel finally.
 
+If you are using Intel Integrated Graphics Device (IGD) as the primary display
+device on your board, SeaBIOS needs to be patched manually to get its VGA ROM
+loaded and run by SeaBIOS. SeaBIOS locates VGA ROM via the PCI expansion ROM
+register, but IGD device does not have its VGA ROM mapped by this register.
+Its VGA ROM is packaged as part of u-boot.rom at a configurable flash address
+which is unknown to SeaBIOS. An example patch is needed for SeaBIOS below:
+
+diff --git a/src/optionroms.c b/src/optionroms.c
+index 65f7fe0..c7b6f5e 100644
+--- a/src/optionroms.c
++++ b/src/optionroms.c
+@@ -324,6 +324,8 @@ init_pcirom(struct pci_device *pci, int isvga, u64 *sources)
+         rom = deploy_romfile(file);
+     else if (RunPCIroms > 1 || (RunPCIroms == 1 && isvga))
+         rom = map_pcirom(pci);
++    if (pci->bdf == pci_to_bdf(0, 2, 0))
++        rom = (struct rom_header *)0xfff90000;
+     if (! rom)
+         // No ROM present.
+         return;
+
+Note: the patch above expects IGD device is at PCI b.d.f 0.2.0 and its VGA ROM
+is at 0xfff90000 which corresponds to CONFIG_VGA_BIOS_ADDR on Minnowboard MAX.
+Change these two accordingly if this is not the case on your board.
 
 Development Flow
 ----------------
@@ -963,12 +982,65 @@ transformations. Remember to add attribution to coreboot for new files added
 to U-Boot. This should go at the top of each file and list the coreboot
 filename where the code originated.
 
+Debugging ACPI issues with Windows:
+
+Windows might cache system information and only detect ACPI changes if you
+modify the ACPI table versions. So tweak them liberally when debugging ACPI
+issues with Windows.
+
+ACPI Support Status
+-------------------
+Advanced Configuration and Power Interface (ACPI) [16] aims to establish
+industry-standard interfaces enabling OS-directed configuration, power
+management, and thermal management of mobile, desktop, and server platforms.
+
+Linux can boot without ACPI with "acpi=off" command line parameter, but
+with ACPI the kernel gains the capabilities to handle power management.
+For Windows, ACPI is a must-have firmware feature since Windows Vista.
+CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in
+U-Boot. This requires Intel ACPI compiler to be installed on your host to
+compile ACPI DSDT table written in ASL format to AML format. You can get
+the compiler via "apt-get install iasl" if you are on Ubuntu or download
+the source from [17] to compile one by yourself.
+
+Current ACPI support in U-Boot is not complete. More features will be added
+in the future. The status as of today is:
+
+ * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables.
+ * Support one static DSDT table only, compiled by Intel ACPI compiler.
+ * Support S0/S5, reboot and shutdown from OS.
+ * Support booting a pre-installed Ubuntu distribution via 'zboot' command.
+ * Support installing and booting Ubuntu 14.04 (or above) from U-Boot with
+   the help of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support installing and booting Windows 8.1/10 from U-Boot with the help
+   of SeaBIOS using legacy interface (non-UEFI mode).
+ * Support ACPI interrupts with SCI only.
+
+Features not supported so far (to make it a complete ACPI solution):
+ * S3 (Suspend to RAM), S4 (Suspend to Disk).
+
+Features that are optional:
+ * ACPI global NVS support. We may need it to simplify ASL code logic if
+   utilizing NVS variables. Most likely we will need this sooner or later.
+ * Dynamic AML bytecodes insertion at run-time. We may need this to support
+   SSDT table generation and DSDT fix up.
+ * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
+   those legacy stuff into U-Boot. ACPI spec allows a system that does not
+   support SMI (a legacy-free system).
+
+ACPI was initially enabled on BayTrail based boards. Testing was done by booting
+a pre-installed Ubuntu 14.04 from a SATA drive. Installing Ubuntu 14.04 and
+Windows 8.1/10 to a SATA drive and booting from there is also tested. Most
+devices seem to work correctly and the board can respond a reboot/shutdown
+command from the OS.
+
+For other platform boards, ACPI support status can be checked by examining their
+board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
 
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
-- SMI and ACPI support, to provide platform info and facilities to Linux
 
 References
 ----------
@@ -987,3 +1059,5 @@ References
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] http://www.seabios.org/SeaBIOS
 [15] doc/device-tree-bindings/misc/intel,irq-router.txt
+[16] http://www.acpi.info
+[17] https://www.acpica.org/downloads
diff --git a/doc/SPL/README.am335x-network b/doc/SPL/README.am335x-network
index 9b63791ad1..e3cf93f8dc 100644
--- a/doc/SPL/README.am335x-network
+++ b/doc/SPL/README.am335x-network
@@ -66,6 +66,10 @@ subnet 192.168.8.0 netmask 255.255.255.0 {
   }
 }
 
+  May the ROM bootloader sends another "vendor-class-identifier"
+  on the shc board with an AM335X it is:
+  "AM335x ROM"
+
   2. Setup TFTP server.
      Install TFTP server and put image files to it's root directory
 (likely /tftpboot or /var/lib/tftpboot or /srv/tftp). You will need
diff --git a/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
new file mode 100644
index 0000000000..c82a2e221b
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/nvidia,tegra186-gpio.txt
@@ -0,0 +1,161 @@
+NVIDIA Tegra186 GPIO controllers
+
+Tegra186 contains two GPIO controllers; a main controller and an "AON"
+controller. This binding document applies to both controllers. The register
+layouts for the controllers share many similarities, but also some significant
+differences. Hence, this document describes closely related but different
+bindings and compatible values.
+
+The Tegra186 GPIO controller allows software to set the IO direction of, and
+read/write the value of, numerous GPIO signals. Routing of GPIO signals to
+package balls is under the control of a separate pin controller HW block. Two
+major sets of registers exist:
+
+a) Security registers, which allow configuration of allowed access to the GPIO
+register set. These registers exist in a single contiguous block of physical
+address space. The size of this block, and the security features available,
+varies between the different GPIO controllers.
+
+Access to this set of registers is not necessary in all circumstances. Code
+that wishes to configure access to the GPIO registers needs access to these
+registers to do so. Code which simply wishes to read or write GPIO data does not
+need access to these registers.
+
+b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
+controllers, these registers are exposed via multiple "physical aliases" in
+address space, each of which access the same underlying state. See the hardware
+documentation for rationale. Any particular GPIO client is expected to access
+just one of these physical aliases.
+
+Tegra HW documentation describes a unified naming convention for all GPIOs
+implemented by the SoC. Each GPIO is assigned to a port, and a port may control
+a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
+name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
+or GPIO_PCC3.
+
+The number of ports implemented by each GPIO controller varies. The number of
+implemented GPIOs within each port varies. GPIO registers within a controller
+are grouped and laid out according to the port they affect.
+
+The mapping from port name to the GPIO controller that implements that port, and
+the mapping from port name to register offset within a controller, are both
+extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
+describes the port-level mapping. In that file, the naming convention for ports
+matches the HW documentation. The values chosen for the names are alphabetically
+sorted within a particular controller. Drivers need to map between the DT GPIO
+IDs and HW register offsets using a lookup table.
+
+Each GPIO controller can generate a number of interrupt signals. Each signal
+represents the aggregate status for all GPIOs within a set of ports. Thus, the
+number of interrupt signals generated by a controller varies as a rough function
+of the number of ports it implements. Note that the HW documentation refers to
+both the overall controller HW module and the sets-of-ports as "controllers".
+
+Each GPIO controller in fact generates multiple interrupts signals for each set
+of ports. Each GPIO may be configured to feed into a specific one of the
+interrupt signals generated by a set-of-ports. The intent is for each generated
+signal to be routed to a different CPU, thus allowing different CPUs to each
+handle subsets of the interrupts within a port. The status of each of these
+per-port-set signals is reported via a separate register. Thus, a driver needs
+to know which status register to observe. This binding currently defines no
+configuration mechanism for this. By default, drivers should use register
+GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
+define a property to configure this.
+
+Required properties:
+- compatible
+    Array of strings.
+    One of:
+    - "nvidia,tegra186-gpio".
+    - "nvidia,tegra186-gpio-aon".
+- reg-names
+    Array of strings.
+    Contains a list of names for the register spaces described by the reg
+    property. May contain the following entries, in any order:
+    - "gpio": Mandatory. GPIO control registers. This may cover either:
+        a) The single physical alias that this OS should use.
+        b) All physical aliases that exist in the controller. This is
+           appropriate when the OS is responsible for managing assignment of
+           the physical aliases.
+    - "security": Optional. Security configuration registers.
+    Users of this binding MUST look up entries in the reg property by name,
+    using this reg-names property to do so.
+- reg
+    Array of (physical base address, length) tuples.
+    Must contain one entry per entry in the reg-names property, in a matching
+    order.
+- interrupts
+    Array of interrupt specifiers.
+    The interrupt outputs from the HW block, one per set of ports, in the
+    order the HW manual describes them. The number of entries required varies
+    depending on compatible value:
+    - "nvidia,tegra186-gpio": 6 entries.
+    - "nvidia,tegra186-gpio-aon": 1 entry.
+- gpio-controller
+    Boolean.
+    Marks the device node as a GPIO controller/provider.
+- #gpio-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's GPIO specifier.
+    In the specifier:
+    - The first cell is the pin number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell contains flags:
+        - Bit 0 specifies polarity
+            - 0: Active-high (normal).
+            - 1: Active-low (inverted).
+- interrupt-controller
+    Boolean.
+    Marks the device node as an interrupt controller/provider.
+- #interrupt-cells
+    Single-cell integer.
+    Must be <2>.
+    Indicates how many cells are used in a consumer's interrupt specifier.
+    In the specifier:
+    - The first cell is the GPIO number.
+        See <dt-bindings/gpio/tegra186-gpio.h>.
+    - The second cell is contains flags:
+        - Bits [3:0] indicate trigger type and level:
+            - 1: Low-to-high edge triggered.
+            - 2: High-to-low edge triggered.
+            - 4: Active high level-sensitive.
+            - 8: Active low level-sensitive.
+            Valid combinations are 1, 2, 3, 4, 8.
+
+Example:
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+gpio@2200000 {
+	compatible = "nvidia,tegra186-gpio";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0x2200000 0x0 0x10000>,
+		<0x0 0x2210000 0x0 0x10000>;
+	interrupts =
+		<0 47 IRQ_TYPE_LEVEL_HIGH>,
+		<0 50 IRQ_TYPE_LEVEL_HIGH>,
+		<0 53 IRQ_TYPE_LEVEL_HIGH>,
+		<0 56 IRQ_TYPE_LEVEL_HIGH>,
+		<0 59 IRQ_TYPE_LEVEL_HIGH>,
+		<0 180 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
+
+gpio@c2f0000 {
+	compatible = "nvidia,tegra186-gpio-aon";
+	reg-names = "security", "gpio";
+	reg =
+		<0x0 0xc2f0000 0x0 0x1000>,
+		<0x0 0xc2f1000 0x0 0x1000>;
+	interrupts =
+		<0 60 IRQ_TYPE_LEVEL_HIGH>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	interrupt-controller;
+	#interrupt-cells = <2>;
+};
diff --git a/doc/device-tree-bindings/mailbox/mailbox.txt b/doc/device-tree-bindings/mailbox/mailbox.txt
new file mode 100644
index 0000000000..be05b9746c
--- /dev/null
+++ b/doc/device-tree-bindings/mailbox/mailbox.txt
@@ -0,0 +1,32 @@
+* Generic Mailbox Controller and client driver bindings
+
+Generic binding to provide a way for Mailbox controller drivers to
+assign appropriate mailbox channel to client drivers.
+
+* Mailbox Controller
+
+Required property:
+- #mbox-cells: Must be at least 1. Number of cells in a mailbox
+		specifier.
+
+Example:
+	mailbox: mailbox {
+		...
+		#mbox-cells = <1>;
+	};
+
+
+* Mailbox Client
+
+Required property:
+- mboxes: List of phandle and mailbox channel specifiers.
+
+Optional property:
+- mbox-names: List of identifier strings for each mailbox channel.
+
+Example:
+	pwr_cntrl: power {
+		...
+		mbox-names = "pwr-ctrl", "rpc";
+		mboxes = <&mailbox 0 &mailbox 1>;
+	};
diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt
index e4d8ead2ee..04ad34654c 100644
--- a/doc/device-tree-bindings/misc/intel,irq-router.txt
+++ b/doc/device-tree-bindings/misc/intel,irq-router.txt
@@ -14,6 +14,11 @@ Required properties :
       "ibase": IRQ routing is in the memory-mapped IBASE register block
 - intel,ibase-offset : IBASE register offset in the interrupt router's PCI
     configuration space, required only if intel,pirq-config = "ibase".
+- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must
+    be specified. The 8-bit ACTL register is seen on ICH series chipset, like
+    ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register.
+- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either
+    in the interrupt router's PCI configuration space, or IBASE.
 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
     first cell is the register offset that controls the first PIRQ link routing.
     The second cell is the total number of PIRQ links the router supports.
diff --git a/doc/device-tree-bindings/net/ti,dp83867.txt b/doc/device-tree-bindings/net/ti,dp83867.txt
new file mode 100644
index 0000000000..cb77fdf082
--- /dev/null
+++ b/doc/device-tree-bindings/net/ti,dp83867.txt
@@ -0,0 +1,25 @@
+* Texas Instruments - dp83867 Giga bit ethernet phy
+
+Required properties:
+	- reg - The ID number for the phy, usually a small integer
+	- ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
+		for applicable values
+	- ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
+		for applicable values
+
+Default child nodes are standard Ethernet PHY device
+nodes as described in doc/devicetree/bindings/net/ethernet.txt
+
+Example:
+
+	ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+
+Datasheet can be found:
+http://www.ti.com/product/DP83867IR/datasheet
diff --git a/doc/driver-model/README.txt b/doc/driver-model/README.txt
index 7a24552560..1b5ccec4b2 100644
--- a/doc/driver-model/README.txt
+++ b/doc/driver-model/README.txt
@@ -606,19 +606,24 @@ methods actually defined.
 
 1. Bind stage
 
-A device and its driver are bound using one of these two methods:
+U-Boot discovers devices using one of these two methods:
 
-   - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the
-name specified by each, to find the appropriate driver. It then calls
-device_bind() to create a new device and bind' it to its driver. This will
-call the device's bind() method.
+   - Scan the U_BOOT_DEVICE() definitions. U-Boot looks up the name specified
+by each, to find the appropriate U_BOOT_DRIVER() definition. In this case,
+there is no path by which driver_data may be provided, but the U_BOOT_DEVICE()
+may provide platdata.
 
    - Scan through the device tree definitions. U-Boot looks at top-level
 nodes in the the device tree. It looks at the compatible string in each node
-and uses the of_match part of the U_BOOT_DRIVER() structure to find the
-right driver for each node. It then calls device_bind() to bind the
-newly-created device to its driver (thereby creating a device structure).
-This will also call the device's bind() method.
+and uses the of_match table of the U_BOOT_DRIVER() structure to find the
+right driver for each node. In this case, the of_match table may provide a
+driver_data value, but platdata cannot be provided until later.
+
+For each device that is discovered, U-Boot then calls device_bind() to create a
+new device, initializes various core fields of the device object such as name,
+uclass & driver, initializes any optional fields of the device object that are
+applicable such as of_offset, driver_data & platdata, and finally calls the
+driver's bind() method if one is defined.
 
 At this point all the devices are known, and bound to their drivers. There
 is a 'struct udevice' allocated for all devices. However, nothing has been
diff --git a/doc/uImage.FIT/multi-with-fpga.its b/doc/uImage.FIT/multi-with-fpga.its
new file mode 100644
index 0000000000..0cdb31fe91
--- /dev/null
+++ b/doc/uImage.FIT/multi-with-fpga.its
@@ -0,0 +1,67 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ * This example makes use of the 'loadables' field
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Configuration to load fpga before Kernel";
+	#address-cells = <1>;
+
+	images {
+		fdt@1 {
+			description = "zc706";
+			data = /incbin/("/tftpboot/devicetree.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			load = <0x10000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		fpga@1 {
+			description = "FPGA";
+			data = /incbin/("/tftpboot/download.bit");
+			type = "fpga";
+			arch = "arm";
+			compression = "none";
+			load = <0x30000000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+
+		linux_kernel@1 {
+			description = "Linux";
+			data = /incbin/("/tftpboot/zImage");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+			load = <0x8000>;
+			entry = <0x8000>;
+			hash@1 {
+				algo = "md5";
+			};
+		};
+	};
+
+	configurations {
+		default = "config@2";
+		config@1 {
+			description = "Linux";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+		};
+
+		config@2 {
+			description = "Linux with fpga";
+			kernel = "linux_kernel@1";
+			fdt = "fdt@1";
+			fpga = "fpga@1";
+		};
+	};
+};
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 9c527c3e01..3f5418045e 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -236,6 +236,7 @@ o config@1
   |- kernel = "kernel sub-node unit name"
   |- ramdisk = "ramdisk sub-node unit name"
   |- fdt = "fdt sub-node unit-name"
+  |- fpga = "fpga sub-node unit-name"
   |- loadables = "loadables sub-node unit-name"
 
 
@@ -251,6 +252,8 @@ o config@1
     "fdt type").
   - setup : Unit name of the corresponding setup binary (used for booting
     an x86 kernel). This contains the setup.bin file built by the kernel.
+  - fpga : Unit name of the corresponding fpga bitstream blob
+    (component image node of a "fpga type").
   - loadables : Unit name containing a list of additional binaries to be
     loaded at their given locations.  "loadables" is a comma-separated list
     of strings. U-Boot will load each binary at its given start-address.
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 118b66ed0e..f2a137ad87 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -30,6 +30,8 @@ source "drivers/input/Kconfig"
 
 source "drivers/led/Kconfig"
 
+source "drivers/mailbox/Kconfig"
+
 source "drivers/memory/Kconfig"
 
 source "drivers/misc/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 99dd07fc76..f6295d285e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -64,6 +64,7 @@ obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
 obj-$(CONFIG_U_QE) += qe/
+obj-y += mailbox/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a98b74bbc0..6eee8eb369 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -21,5 +21,6 @@ config SPL_CLK
 	  used as U-Boot proper.
 
 source "drivers/clk/uniphier/Kconfig"
+source "drivers/clk/exynos/Kconfig"
 
 endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index c51db1562b..81fe600188 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
 obj-$(CONFIG_SANDBOX) += clk_sandbox.o
 obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
+obj-$(CONFIG_CLK_EXYNOS) += exynos/
diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/clk_rk3036.c
index bd5f22a753..7ec65bdff0 100644
--- a/drivers/clk/clk_rk3036.c
+++ b/drivers/clk/clk_rk3036.c
@@ -407,7 +407,7 @@ static int rk3036_clk_bind(struct udevice *dev)
 	}
 
 	/* The reset driver does not have a device node, so bind it here */
-	ret = device_bind_driver(gd->dm_root, "rk3036_reset", "reset", &dev);
+	ret = device_bind_driver(gd->dm_root, "rk3036_sysreset", "reset", &dev);
 	if (ret)
 		debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
 
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 2a85e93a6c..d88893c8ea 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -326,6 +326,17 @@ static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
 	return 0;
 }
 
+static int rockchip_mac_set_clk(struct rk3288_cru *cru,
+				  int periph, uint freq)
+{
+	/* Assuming mac_clk is fed by an external clock */
+	rk_clrsetreg(&cru->cru_clksel_con[21],
+		     RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+		     RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+
+	 return 0;
+}
+
 static int rockchip_vop_set_clk(struct rk3288_cru *cru, struct rk3288_grf *grf,
 				int periph, unsigned int rate_hz)
 {
@@ -759,6 +770,9 @@ static ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate)
 		new_rate = rockchip_spi_set_clk(cru, gclk_rate, periph, rate);
 		break;
 #ifndef CONFIG_SPL_BUILD
+	case SCLK_MAC:
+		new_rate = rockchip_mac_set_clk(priv->cru, periph, rate);
+		break;
 	case DCLK_VOP0:
 	case DCLK_VOP1:
 		new_rate = rockchip_vop_set_clk(cru, priv->grf, periph, rate);
@@ -877,7 +891,7 @@ static int rk3288_clk_bind(struct udevice *dev)
 	}
 
 	/* The reset driver does not have a device node, so bind it here */
-	ret = device_bind_driver(gd->dm_root, "rk3288_reset", "reset", &dev);
+	ret = device_bind_driver(gd->dm_root, "rk3288_sysreset", "reset", &dev);
 	if (ret)
 		debug("Warning: No RK3288 reset driver: ret=%d\n", ret);
 
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
new file mode 100644
index 0000000000..eb0efa97d1
--- /dev/null
+++ b/drivers/clk/exynos/Kconfig
@@ -0,0 +1,18 @@
+config CLK_EXYNOS
+	bool
+	select CLK
+	help
+	  This enables support for common clock driver API on Samsung
+	  Exynos SoCs.
+
+menu "Clock drivers for Exynos SoCs"
+	depends on CLK_EXYNOS
+
+config CLK_EXYNOS7420
+	bool "Clock driver for Samsung's Exynos7420 SoC"
+	default y
+	help
+	  This enables common clock driver support for platforms based
+	  on Samsung Exynos7420 SoC.
+
+endmenu
diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile
new file mode 100644
index 0000000000..1df10fe84a
--- /dev/null
+++ b/drivers/clk/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y				+= clk-pll.o
+obj-$(CONFIG_CLK_EXYNOS7420)	+= clk-exynos7420.o
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
new file mode 100644
index 0000000000..bf5d0e6e60
--- /dev/null
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -0,0 +1,236 @@
+/*
+ * Samsung Exynos7420 clock driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/exynos7420-clk.h>
+#include "clk-pll.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIVIDER(reg, shift, mask)	\
+	(((readl(reg) >> shift) & mask) + 1)
+
+/* CMU TOPC block device structure */
+struct exynos7420_clk_cmu_topc {
+	unsigned int	rsvd1[68];
+	unsigned int	bus0_pll_con[2];
+	unsigned int	rsvd2[2];
+	unsigned int	bus1_pll_con[2];
+	unsigned int	rsvd3[54];
+	unsigned int	mux_sel[6];
+	unsigned int	rsvd4[250];
+	unsigned int	div[4];
+};
+
+/* CMU TOP0 block device structure */
+struct exynos7420_clk_cmu_top0 {
+	unsigned int	rsvd0[128];
+	unsigned int	mux_sel[7];
+	unsigned int	rsvd1[261];
+	unsigned int	div_peric[5];
+};
+
+/**
+ * struct exynos7420_clk_topc_priv - private data for CMU topc clock driver.
+ *
+ * @topc: base address of the memory mapped CMU TOPC controller.
+ * @fin_freq: frequency of the Oscillator clock.
+ * @sclk_bus0_pll_a: frequency of sclk_bus0_pll_a clock.
+ * @sclk_bus1_pll_a: frequency of sclk_bus1_pll_a clock.
+ */
+struct exynos7420_clk_topc_priv {
+	struct exynos7420_clk_cmu_topc *topc;
+	unsigned long fin_freq;
+	unsigned long sclk_bus0_pll_a;
+	unsigned long sclk_bus1_pll_a;
+};
+
+/**
+ * struct exynos7420_clk_top0_priv - private data for CMU top0 clock driver.
+ *
+ * @top0: base address of the memory mapped CMU TOP0 controller.
+ * @mout_top0_bus0_pll_half: frequency of mout_top0_bus0_pll_half clock
+ * @sclk_uart2: frequency of sclk_uart2 clock.
+ */
+struct exynos7420_clk_top0_priv {
+	struct exynos7420_clk_cmu_top0 *top0;
+	unsigned long mout_top0_bus0_pll_half;
+	unsigned long sclk_uart2;
+};
+
+static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+
+	switch (periph) {
+	case DOUT_SCLK_BUS0_PLL:
+	case SCLK_BUS0_PLL_A:
+	case SCLK_BUS0_PLL_B:
+		return priv->sclk_bus0_pll_a;
+	case DOUT_SCLK_BUS1_PLL:
+	case SCLK_BUS1_PLL_A:
+	case SCLK_BUS1_PLL_B:
+		return priv->sclk_bus1_pll_a;
+	default:
+		return 0;
+	}
+}
+
+static struct clk_ops exynos7420_clk_topc_ops = {
+	.get_periph_rate	= exynos7420_topc_get_periph_rate,
+};
+
+static int exynos7420_clk_topc_probe(struct udevice *dev)
+{
+	struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_cmu_topc *topc;
+	struct udevice *clk_dev;
+	unsigned long rate;
+	fdt_addr_t base;
+	int ret;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	topc = (struct exynos7420_clk_cmu_topc *)base;
+	priv->topc = topc;
+
+	ret = clk_get_by_index(dev, 0, &clk_dev);
+	if (ret >= 0)
+		priv->fin_freq = clk_get_rate(clk_dev);
+
+	rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
+	if (readl(&topc->mux_sel[1]) & (1 << 16))
+		rate >>= 1;
+	rate /= DIVIDER(&topc->div[3], 0, 0xf);
+	priv->sclk_bus0_pll_a = rate;
+
+	rate = pll145x_get_rate(&topc->bus1_pll_con[0], priv->fin_freq) /
+			DIVIDER(&topc->div[3], 8, 0xf);
+	priv->sclk_bus1_pll_a = rate;
+
+	return 0;
+}
+
+static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+	struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
+
+	switch (periph) {
+	case CLK_SCLK_UART2:
+		return priv->mout_top0_bus0_pll_half /
+			DIVIDER(&top0->div_peric[3], 8, 0xf);
+	default:
+		return 0;
+	}
+}
+
+static struct clk_ops exynos7420_clk_top0_ops = {
+	.get_periph_rate	= exynos7420_top0_get_periph_rate,
+};
+
+static int exynos7420_clk_top0_probe(struct udevice *dev)
+{
+	struct exynos7420_clk_top0_priv *priv;
+	struct exynos7420_clk_cmu_top0 *top0;
+	struct udevice *clk_dev;
+	fdt_addr_t base;
+	int ret;
+
+	priv = dev_get_priv(dev);
+	if (!priv)
+		return -EINVAL;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	top0 = (struct exynos7420_clk_cmu_top0 *)base;
+	priv->top0 = top0;
+
+	ret = clk_get_by_index(dev, 1, &clk_dev);
+	if (ret >= 0) {
+		priv->mout_top0_bus0_pll_half =
+			clk_get_periph_rate(clk_dev, ret);
+		if (readl(&top0->mux_sel[1]) & (1 << 16))
+			priv->mout_top0_bus0_pll_half >>= 1;
+	}
+
+	return 0;
+}
+
+static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+{
+	struct udevice *clk_dev;
+	unsigned int ret;
+	unsigned long freq = 0;
+
+	switch (periph) {
+	case SCLK_UART2:
+		ret = clk_get_by_index(dev, 3, &clk_dev);
+		if (ret < 0)
+			return ret;
+		freq = clk_get_periph_rate(clk_dev, ret);
+		break;
+	}
+
+	return freq;
+}
+
+static struct clk_ops exynos7420_clk_peric1_ops = {
+	.get_periph_rate	= exynos7420_peric1_get_periph_rate,
+};
+
+static const struct udevice_id exynos7420_clk_topc_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-topc" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_topc) = {
+	.name = "exynos7420-clock-topc",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_topc_compat,
+	.probe = exynos7420_clk_topc_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos7420_clk_topc_priv),
+	.ops = &exynos7420_clk_topc_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id exynos7420_clk_top0_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-top0" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_top0) = {
+	.name = "exynos7420-clock-top0",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_top0_compat,
+	.probe = exynos7420_clk_top0_probe,
+	.priv_auto_alloc_size = sizeof(struct exynos7420_clk_top0_priv),
+	.ops = &exynos7420_clk_top0_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+static const struct udevice_id exynos7420_clk_peric1_compat[] = {
+	{ .compatible = "samsung,exynos7-clock-peric1" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos7420_clk_peric1) = {
+	.name = "exynos7420-clock-peric1",
+	.id = UCLASS_CLK,
+	.of_match = exynos7420_clk_peric1_compat,
+	.ops = &exynos7420_clk_peric1_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c
new file mode 100644
index 0000000000..27220c5911
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.c
@@ -0,0 +1,33 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+
+#define PLL145X_MDIV_SHIFT	16
+#define PLL145X_MDIV_MASK	0x3ff
+#define PLL145X_PDIV_SHIFT	8
+#define PLL145X_PDIV_MASK	0x3f
+#define PLL145X_SDIV_SHIFT	0
+#define PLL145X_SDIV_MASK	0x7
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
+{
+	unsigned long pll_con1 = readl(con1);
+	unsigned long mdiv, sdiv, pdiv;
+	uint64_t fvco = fin_freq;
+
+	mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+	pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+	sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+	fvco *= mdiv;
+	do_div(fvco, (pdiv << sdiv));
+	return (unsigned long)fvco;
+}
diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
new file mode 100644
index 0000000000..631d035f83
--- /dev/null
+++ b/drivers/clk/exynos/clk-pll.h
@@ -0,0 +1,9 @@
+/*
+ * Exynos PLL helper functions for clock drivers.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index a2b0e80a33..c6ecd119bd 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -165,6 +165,10 @@ static const struct udevice_id uniphier_mio_clk_match[] = {
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
 	{
+		.compatible = "socionext,ph1-ld11-mioctrl",
+		.data = (ulong)&uniphier_mio_clk_data,
+	},
+	{
 		.compatible = "socionext,ph1-ld20-mioctrl",
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index c5c9d2a42e..87495614c2 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -178,4 +178,27 @@ config SPL_OF_TRANSLATE
 	  used for the address translation. This function is faster and
 	  smaller in size than fdt_translate_address().
 
+config OF_ISA_BUS
+	bool
+	depends on OF_TRANSLATE
+	help
+	  Is this option is enabled then support for the ISA bus will
+	  be included for addresses read from DT. This is something that
+	  should be known to be required or not based upon the board
+	  being targetted, and whether or not it makes use of an ISA bus.
+
+	  The bus is matched based upon its node name equalling "isa". The
+	  busses #address-cells should equal 2, with the first cell being
+	  used to hold flags & flag 0x1 indicating that the address range
+	  should be accessed using I/O port in/out accessors. The second
+	  cell holds the offset into ISA bus address space. The #size-cells
+	  property should equal 1, and of course holds the size of the
+	  address range used by a device.
+
+	  If this option is not enabled then support for the ISA bus is
+	  not included and any such busses used in DT will be treated as
+	  typical simple-bus compatible busses. This will lead to
+	  mistranslation of device addresses, so ensure that this is
+	  enabled if your board does include an ISA bus.
+
 endmenu
diff --git a/drivers/core/device.c b/drivers/core/device.c
index 5c2dc7021f..eb75b1734f 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -26,9 +26,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int device_bind(struct udevice *parent, const struct driver *drv,
-		const char *name, void *platdata, int of_offset,
-		struct udevice **devp)
+static int device_bind_common(struct udevice *parent, const struct driver *drv,
+			      const char *name, void *platdata,
+			      ulong driver_data, int of_offset,
+			      struct udevice **devp)
 {
 	struct udevice *dev;
 	struct uclass *uc;
@@ -56,6 +57,7 @@ int device_bind(struct udevice *parent, const struct driver *drv,
 	INIT_LIST_HEAD(&dev->devres_head);
 #endif
 	dev->platdata = platdata;
+	dev->driver_data = driver_data;
 	dev->name = name;
 	dev->of_offset = of_offset;
 	dev->parent = parent;
@@ -193,6 +195,23 @@ fail_alloc1:
 	return ret;
 }
 
+int device_bind_with_driver_data(struct udevice *parent,
+				 const struct driver *drv, const char *name,
+				 ulong driver_data, int of_offset,
+				 struct udevice **devp)
+{
+	return device_bind_common(parent, drv, name, NULL, driver_data,
+				  of_offset, devp);
+}
+
+int device_bind(struct udevice *parent, const struct driver *drv,
+		const char *name, void *platdata, int of_offset,
+		struct udevice **devp)
+{
+	return device_bind_common(parent, drv, name, platdata, 0, of_offset,
+				  devp);
+}
+
 int device_bind_by_name(struct udevice *parent, bool pre_reloc_only,
 			const struct driver_info *info, struct udevice **devp)
 {
@@ -721,3 +740,17 @@ int device_set_name(struct udevice *dev, const char *name)
 
 	return 0;
 }
+
+bool of_device_is_compatible(struct udevice *dev, const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+}
+
+bool of_machine_is_compatible(const char *compat)
+{
+	const void *fdt = gd->fdt_blob;
+
+	return !fdt_node_check_compatible(fdt, 0, compat);
+}
diff --git a/drivers/core/lists.c b/drivers/core/lists.c
index a72db13a11..0c27717790 100644
--- a/drivers/core/lists.c
+++ b/drivers/core/lists.c
@@ -170,7 +170,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 		}
 
 		dm_dbg("   - found match at '%s'\n", entry->name);
-		ret = device_bind(parent, entry, name, NULL, offset, &dev);
+		ret = device_bind_with_driver_data(parent, entry, name,
+						   id->data, offset, &dev);
 		if (ret == -ENODEV) {
 			dm_dbg("Driver '%s' refuses to bind\n", entry->name);
 			continue;
@@ -180,7 +181,6 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset,
 				ret);
 			return ret;
 		} else {
-			dev->driver_data = id->data;
 			found = true;
 			if (devp)
 				*devp = dev;
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 8bc517dadc..510fa4e376 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -19,11 +19,26 @@
 #define CIRC_CNT(head, tail, size)	(((head) - (tail)) & (size - 1))
 #define CIRC_SPACE(head, tail, size)	CIRC_CNT((tail), (head) + 1, (size))
 
-struct jobring jr;
+uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
+	0,
+#if defined(CONFIG_PPC_C29X)
+	CONFIG_SYS_FSL_SEC_IDX_OFFSET,
+	2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
+#endif
+};
+
+#define SEC_ADDR(idx)	\
+	((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
+
+#define SEC_JR0_ADDR(idx)	\
+	(SEC_ADDR(idx) +	\
+	 (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+
+struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
 
-static inline void start_jr0(void)
+static inline void start_jr0(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
 	u32 scfgr = sec_in32(&sec->scfgr);
 
@@ -42,15 +57,15 @@ static inline void start_jr0(void)
 	}
 }
 
-static inline void jr_reset_liodn(void)
+static inline void jr_reset_liodn(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	sec_out32(&sec->jrliodnr[0].ls, 0);
 }
 
-static inline void jr_disable_irq(void)
+static inline void jr_disable_irq(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t jrcfg = sec_in32(&regs->jrcfg1);
 
 	jrcfg = jrcfg | JR_INTMASK;
@@ -58,11 +73,12 @@ static inline void jr_disable_irq(void)
 	sec_out32(&regs->jrcfg1, jrcfg);
 }
 
-static void jr_initregs(void)
+static void jr_initregs(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
-	phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
+	phys_addr_t op_base = virt_to_phys((void *)jr->output_ring);
 
 #ifdef CONFIG_PHYS_64BIT
 	sec_out32(&regs->irba_h, ip_base >> 32);
@@ -79,59 +95,63 @@ static void jr_initregs(void)
 	sec_out32(&regs->ors, JR_SIZE);
 	sec_out32(&regs->irs, JR_SIZE);
 
-	if (!jr.irq)
-		jr_disable_irq();
+	if (!jr->irq)
+		jr_disable_irq(sec_idx);
 }
 
-static int jr_init(void)
+static int jr_init(uint8_t sec_idx)
 {
-	memset(&jr, 0, sizeof(struct jobring));
+	struct jobring *jr = &jr0[sec_idx];
 
-	jr.jq_id = DEFAULT_JR_ID;
-	jr.irq = DEFAULT_IRQ;
+	memset(jr, 0, sizeof(struct jobring));
+
+	jr->jq_id = DEFAULT_JR_ID;
+	jr->irq = DEFAULT_IRQ;
 
 #ifdef CONFIG_FSL_CORENET
-	jr.liodn = DEFAULT_JR_LIODN;
+	jr->liodn = DEFAULT_JR_LIODN;
 #endif
-	jr.size = JR_SIZE;
-	jr.input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
+	jr->size = JR_SIZE;
+	jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN,
 				JR_SIZE * sizeof(dma_addr_t));
-	if (!jr.input_ring)
+	if (!jr->input_ring)
 		return -1;
 
-	jr.op_size = roundup(JR_SIZE * sizeof(struct op_ring),
-			     ARCH_DMA_MINALIGN);
-	jr.output_ring =
-	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr.op_size);
-	if (!jr.output_ring)
+	jr->op_size = roundup(JR_SIZE * sizeof(struct op_ring),
+			      ARCH_DMA_MINALIGN);
+	jr->output_ring =
+	    (struct op_ring *)memalign(ARCH_DMA_MINALIGN, jr->op_size);
+	if (!jr->output_ring)
 		return -1;
 
-	memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
-	memset(jr.output_ring, 0, jr.op_size);
+	memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
+	memset(jr->output_ring, 0, jr->op_size);
 
-	start_jr0();
+	start_jr0(sec_idx);
 
-	jr_initregs();
+	jr_initregs(sec_idx);
 
 	return 0;
 }
 
-static int jr_sw_cleanup(void)
+static int jr_sw_cleanup(uint8_t sec_idx)
 {
-	jr.head = 0;
-	jr.tail = 0;
-	jr.read_idx = 0;
-	jr.write_idx = 0;
-	memset(jr.info, 0, sizeof(jr.info));
-	memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
-	memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
+	struct jobring *jr = &jr0[sec_idx];
+
+	jr->head = 0;
+	jr->tail = 0;
+	jr->read_idx = 0;
+	jr->write_idx = 0;
+	memset(jr->info, 0, sizeof(jr->info));
+	memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t));
+	memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
 
 	return 0;
 }
 
-static int jr_hw_reset(void)
+static int jr_hw_reset(uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
 	uint32_t timeout = 100000;
 	uint32_t jrint, jrcr;
 
@@ -161,10 +181,11 @@ static int jr_hw_reset(void)
 /* -1 --- error, can't enqueue -- no space available */
 static int jr_enqueue(uint32_t *desc_addr,
 	       void (*callback)(uint32_t status, void *arg),
-	       void *arg)
+	       void *arg, uint8_t sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	int head = jr.head;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	int head = jr->head;
 	uint32_t desc_word;
 	int length = desc_len(desc_addr);
 	int i;
@@ -184,18 +205,14 @@ static int jr_enqueue(uint32_t *desc_addr,
 
 	phys_addr_t desc_phys_addr = virt_to_phys(desc_addr);
 
-	if (sec_in32(&regs->irsa) == 0 ||
-	    CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
-		return -1;
-
-	jr.info[head].desc_phys_addr = desc_phys_addr;
-	jr.info[head].callback = (void *)callback;
-	jr.info[head].arg = arg;
-	jr.info[head].op_done = 0;
+	jr->info[head].desc_phys_addr = desc_phys_addr;
+	jr->info[head].callback = (void *)callback;
+	jr->info[head].arg = arg;
+	jr->info[head].op_done = 0;
 
-	unsigned long start = (unsigned long)&jr.info[head] &
+	unsigned long start = (unsigned long)&jr->info[head] &
 					~(ARCH_DMA_MINALIGN - 1);
-	unsigned long end = ALIGN((unsigned long)&jr.info[head] +
+	unsigned long end = ALIGN((unsigned long)&jr->info[head] +
 				  sizeof(struct jr_info), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
@@ -205,11 +222,11 @@ static int jr_enqueue(uint32_t *desc_addr,
 	 * depend on endianness of SEC block.
 	 */
 #ifdef CONFIG_SYS_FSL_SEC_LE
-	addr_lo = (uint32_t *)(&jr.input_ring[head]);
-	addr_hi = (uint32_t *)(&jr.input_ring[head]) + 1;
+	addr_lo = (uint32_t *)(&jr->input_ring[head]);
+	addr_hi = (uint32_t *)(&jr->input_ring[head]) + 1;
 #elif defined(CONFIG_SYS_FSL_SEC_BE)
-	addr_hi = (uint32_t *)(&jr.input_ring[head]);
-	addr_lo = (uint32_t *)(&jr.input_ring[head]) + 1;
+	addr_hi = (uint32_t *)(&jr->input_ring[head]);
+	addr_lo = (uint32_t *)(&jr->input_ring[head]) + 1;
 #endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 
 	sec_out32(addr_hi, (uint32_t)(desc_phys_addr >> 32));
@@ -217,21 +234,21 @@ static int jr_enqueue(uint32_t *desc_addr,
 
 #else
 	/* Write the 32 bit Descriptor address on Input Ring. */
-	sec_out32(&jr.input_ring[head], desc_phys_addr);
+	sec_out32(&jr->input_ring[head], desc_phys_addr);
 #endif /* ifdef CONFIG_PHYS_64BIT */
 
-	start = (unsigned long)&jr.input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
-	end = ALIGN((unsigned long)&jr.input_ring[head] +
+	start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1);
+	end = ALIGN((unsigned long)&jr->input_ring[head] +
 		     sizeof(dma_addr_t), ARCH_DMA_MINALIGN);
 	flush_dcache_range(start, end);
 
-	jr.head = (head + 1) & (jr.size - 1);
+	jr->head = (head + 1) & (jr->size - 1);
 
 	/* Invalidate output ring */
-	start = (unsigned long)jr.output_ring &
+	start = (unsigned long)jr->output_ring &
 					~(ARCH_DMA_MINALIGN - 1);
-	end = ALIGN((unsigned long)jr.output_ring + jr.op_size,
-		     ARCH_DMA_MINALIGN);
+	end = ALIGN((unsigned long)jr->output_ring + jr->op_size,
+		    ARCH_DMA_MINALIGN);
 	invalidate_dcache_range(start, end);
 
 	sec_out32(&regs->irja, 1);
@@ -239,11 +256,12 @@ static int jr_enqueue(uint32_t *desc_addr,
 	return 0;
 }
 
-static int jr_dequeue(void)
+static int jr_dequeue(int sec_idx)
 {
-	struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
-	int head = jr.head;
-	int tail = jr.tail;
+	struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
+	struct jobring *jr = &jr0[sec_idx];
+	int head = jr->head;
+	int tail = jr->tail;
 	int idx, i, found;
 	void (*callback)(uint32_t status, void *arg);
 	void *arg = NULL;
@@ -253,7 +271,8 @@ static int jr_dequeue(void)
 	uint32_t *addr;
 #endif
 
-	while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
+	while (sec_in32(&regs->orsf) && CIRC_CNT(jr->head, jr->tail,
+						 jr->size)) {
 
 		found = 0;
 
@@ -264,11 +283,11 @@ static int jr_dequeue(void)
 		 * depend on endianness of SEC block.
 		 */
 	#ifdef CONFIG_SYS_FSL_SEC_LE
-		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc);
-		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 	#elif defined(CONFIG_SYS_FSL_SEC_BE)
-		addr_hi = (uint32_t *)(&jr.output_ring[jr.tail].desc);
-		addr_lo = (uint32_t *)(&jr.output_ring[jr.tail].desc) + 1;
+		addr_hi = (uint32_t *)(&jr->output_ring[jr->tail].desc);
+		addr_lo = (uint32_t *)(&jr->output_ring[jr->tail].desc) + 1;
 	#endif /* ifdef CONFIG_SYS_FSL_SEC_LE */
 
 		op_desc = ((u64)sec_in32(addr_hi) << 32) |
@@ -276,15 +295,15 @@ static int jr_dequeue(void)
 
 	#else
 		/* Read the 32 bit Descriptor address from Output Ring. */
-		addr = (uint32_t *)&jr.output_ring[jr.tail].desc;
+		addr = (uint32_t *)&jr->output_ring[jr->tail].desc;
 		op_desc = sec_in32(addr);
 	#endif /* ifdef CONFIG_PHYS_64BIT */
 
-		uint32_t status = sec_in32(&jr.output_ring[jr.tail].status);
+		uint32_t status = sec_in32(&jr->output_ring[jr->tail].status);
 
-		for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
-			idx = (tail + i) & (jr.size - 1);
-			if (op_desc == jr.info[idx].desc_phys_addr) {
+		for (i = 0; CIRC_CNT(head, tail + i, jr->size) >= 1; i++) {
+			idx = (tail + i) & (jr->size - 1);
+			if (op_desc == jr->info[idx].desc_phys_addr) {
 				found = 1;
 				break;
 			}
@@ -294,9 +313,9 @@ static int jr_dequeue(void)
 		if (!found)
 			return -1;
 
-		jr.info[idx].op_done = 1;
-		callback = (void *)jr.info[idx].callback;
-		arg = jr.info[idx].arg;
+		jr->info[idx].op_done = 1;
+		callback = (void *)jr->info[idx].callback;
+		arg = jr->info[idx].arg;
 
 		/* When the job on tail idx gets done, increment
 		 * tail till the point where job completed out of oredr has
@@ -304,14 +323,14 @@ static int jr_dequeue(void)
 		 */
 		if (idx == tail)
 			do {
-				tail = (tail + 1) & (jr.size - 1);
-			} while (jr.info[tail].op_done);
+				tail = (tail + 1) & (jr->size - 1);
+			} while (jr->info[tail].op_done);
 
-		jr.tail = tail;
-		jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
+		jr->tail = tail;
+		jr->read_idx = (jr->read_idx + 1) & (jr->size - 1);
 
 		sec_out32(&regs->orjr, 1);
-		jr.info[idx].op_done = 0;
+		jr->info[idx].op_done = 0;
 
 		callback(status, arg);
 	}
@@ -327,7 +346,7 @@ static void desc_done(uint32_t status, void *arg)
 	x->done = 1;
 }
 
-int run_descriptor_jr(uint32_t *desc)
+static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx)
 {
 	unsigned long long timeval = get_ticks();
 	unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
@@ -336,7 +355,7 @@ int run_descriptor_jr(uint32_t *desc)
 
 	memset(&op, 0, sizeof(op));
 
-	ret = jr_enqueue(desc, desc_done, &op);
+	ret = jr_enqueue(desc, desc_done, &op, sec_idx);
 	if (ret) {
 		debug("Error in SEC enq\n");
 		ret = JQ_ENQ_ERR;
@@ -346,7 +365,7 @@ int run_descriptor_jr(uint32_t *desc)
 	timeval = get_ticks();
 	timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
 	while (op.done != 1) {
-		ret = jr_dequeue();
+		ret = jr_dequeue(sec_idx);
 		if (ret) {
 			debug("Error in SEC deq\n");
 			ret = JQ_DEQ_ERR;
@@ -368,20 +387,30 @@ out:
 	return ret;
 }
 
-int jr_reset(void)
+int run_descriptor_jr(uint32_t *desc)
+{
+	return run_descriptor_jr_idx(desc, 0);
+}
+
+static inline int jr_reset_sec(uint8_t sec_idx)
 {
-	if (jr_hw_reset() < 0)
+	if (jr_hw_reset(sec_idx) < 0)
 		return -1;
 
 	/* Clean up the jobring structure maintained by software */
-	jr_sw_cleanup();
+	jr_sw_cleanup(sec_idx);
 
 	return 0;
 }
 
-int sec_reset(void)
+int jr_reset(void)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	return jr_reset_sec(0);
+}
+
+static inline int sec_reset_idx(uint8_t sec_idx)
+{
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	uint32_t mcfgr = sec_in32(&sec->mcfgr);
 	uint32_t timeout = 100000;
 
@@ -408,14 +437,13 @@ int sec_reset(void)
 	return 0;
 }
 
-static int instantiate_rng(void)
+static int instantiate_rng(uint8_t sec_idx)
 {
 	struct result op;
 	u32 *desc;
 	u32 rdsta_val;
 	int ret = 0;
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -432,7 +460,7 @@ static int instantiate_rng(void)
 	flush_dcache_range((unsigned long)desc,
 			   (unsigned long)desc + size);
 
-	ret = run_descriptor_jr(desc);
+	ret = run_descriptor_jr_idx(desc, sec_idx);
 
 	if (ret)
 		printf("RNG: Instantiation failed with error %x\n", ret);
@@ -444,9 +472,14 @@ static int instantiate_rng(void)
 	return ret;
 }
 
-static u8 get_rng_vid(void)
+int sec_reset(void)
+{
+	return sec_reset_idx(0);
+}
+
+static u8 get_rng_vid(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	u32 cha_vid = sec_in32(&sec->chavid_ls);
 
 	return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
@@ -456,10 +489,9 @@ static u8 get_rng_vid(void)
  * By default, the TRNG runs for 200 clocks per sample;
  * 1200 clocks per sample generates better entropy.
  */
-static void kick_trng(int ent_delay)
+static void kick_trng(int ent_delay, uint8_t sec_idx)
 {
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 	u32 val;
@@ -486,11 +518,10 @@ static void kick_trng(int ent_delay)
 	sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
 }
 
-static int rng_init(void)
+static int rng_init(uint8_t sec_idx)
 {
 	int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
-	ccsr_sec_t __iomem *sec =
-			(ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx);
 	struct rng4tst __iomem *rng =
 			(struct rng4tst __iomem *)&sec->rng;
 
@@ -509,7 +540,7 @@ static int rng_init(void)
 		 * Also, if a handle was instantiated, do not change
 		 * the TRNG parameters.
 		 */
-		kick_trng(ent_delay);
+		kick_trng(ent_delay, sec_idx);
 		ent_delay += 400;
 		/*
 		 * if instantiate_rng(...) fails, the loop will rerun
@@ -518,7 +549,7 @@ static int rng_init(void)
 		 * interval, leading to a sucessful initialization of
 		 * the RNG.
 		 */
-		ret = instantiate_rng();
+		ret = instantiate_rng(sec_idx);
 	} while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
 	if (ret) {
 		printf("RNG: Failed to instantiate RNG\n");
@@ -531,9 +562,9 @@ static int rng_init(void)
 	return ret;
 }
 
-int sec_init(void)
+int sec_init_idx(uint8_t sec_idx)
 {
-	ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+	ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
 	uint32_t mcr = sec_in32(&sec->mcfgr);
 	int ret = 0;
 
@@ -543,6 +574,11 @@ int sec_init(void)
 	uint32_t liodn_s;
 #endif
 
+	if (!(sec_idx < CONFIG_SYS_FSL_MAX_NUM_OF_SEC)) {
+		printf("SEC initialization failed\n");
+		return -1;
+	}
+
 	/*
 	 * Modifying CAAM Read/Write Attributes
 	 * For LS2080A
@@ -568,7 +604,7 @@ int sec_init(void)
 	liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
 #endif
 
-	ret = jr_init();
+	ret = jr_init(sec_idx);
 	if (ret < 0) {
 		printf("SEC initialization failed\n");
 		return -1;
@@ -582,13 +618,18 @@ int sec_init(void)
 	pamu_enable();
 #endif
 
-	if (get_rng_vid() >= 4) {
-		if (rng_init() < 0) {
-			printf("RNG instantiation failed\n");
+	if (get_rng_vid(sec_idx) >= 4) {
+		if (rng_init(sec_idx) < 0) {
+			printf("SEC%u: RNG instantiation failed\n", sec_idx);
 			return -1;
 		}
-		printf("SEC: RNG instantiated\n");
+		printf("SEC%u: RNG instantiated\n", sec_idx);
 	}
 
 	return ret;
 }
+
+int sec_init(void)
+{
+	return sec_init_idx(0);
+}
diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h
index 1642dbbf4c..d897e572d6 100644
--- a/drivers/crypto/fsl/jr.h
+++ b/drivers/crypto/fsl/jr.h
@@ -90,6 +90,9 @@ struct jobring {
 	/* This ring can be on the stack */
 	struct jr_info info[JR_SIZE];
 	struct op_ring *output_ring;
+	/* Offset in CCSR to the SEC engine to which this JR belongs */
+	uint32_t sec_offset;
+
 };
 
 struct result {
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 9073917914..1d5cec662c 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 14)
+		| ((wr_lat & 0x10) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 	/* Per FSL Application Note: AN2805 */
 	ss_en = 1;
 #endif
-	clk_adjust = popts->clk_adjust;
+	if (fsl_ddr_get_version(0) >= 0x40701) {
+		/* clk_adjust in 5-bits on T-series and LS-series */
+		clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+	} else {
+		/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+		clk_adjust = (popts->clk_adjust & 0xF) << 23;
+	}
+
 	ddr->ddr_sdram_clk_cntl = (0
 				   | ((ss_en & 0x1) << 31)
-				   | ((clk_adjust & 0xF) << 23)
+				   | clk_adjust
 				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 608810d4e2..d37e2474c9 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};	/* for range 2 */
 	u32 *vref_seq = vref_seq1;
 #endif
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
+	defined(CONFIG_SYS_FSL_ERRATUM_A010165)
 	ulong ddr_freq;
 	u32 tmp;
 #endif
@@ -205,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 	/* part 1 of 2 */
-	if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-		ddr_out32(&ddr->ddr_sdram_rcw_2,
-			  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+	if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+			ddr_out32(&ddr->ddr_sdram_rcw_2,
+				  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+		}
+		ddr_out32(&ddr->err_disable, regs->err_disable |
+			  DDR_ERR_DISABLE_APED);
 	}
-
-	ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -240,8 +243,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		/* Disable DRAM VRef training */
 		ddr_out32(&ddr->ddr_cdr2,
 			  regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
-		/* Disable deskew */
-		ddr_out32(&ddr->debug[28], 0x400);
+		/* disable transmit bit deskew */
+		temp32 = ddr_in32(&ddr->debug[28]);
+		temp32 |= DDR_TX_BD_DIS;
+		ddr_out32(&ddr->debug[28], temp32);
 		/* Disable D_INIT */
 		ddr_out32(&ddr->sdram_cfg_2,
 			  regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
@@ -249,6 +254,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	}
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009801
+	temp32 = ddr_in32(&ddr->debug[25]);
+	temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
+	temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
+	ddr_out32(&ddr->debug[25], temp32);
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
 	tmp = ddr_in32(&ddr->debug[28]);
@@ -262,6 +274,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
+	ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+	if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+		tmp = ddr_in32(&ddr->debug[28]);
+		ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+	}
+#endif
 	/*
 	 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
 	 * deasserted. Clocks start when any chip select is enabled and clock
@@ -358,7 +377,9 @@ step2:
 			debug("MR6 = 0x%08x\n", temp32);
 		}
 		ddr_out32(&ddr->sdram_md_cntl, 0);
-		ddr_out32(&ddr->debug[28], 0);		/* Enable deskew */
+		temp32 = ddr_in32(&ddr->debug[28]);
+		temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+		ddr_out32(&ddr->debug[28], temp32);
 		ddr_out32(&ddr->debug[1], 0x400);	/* restart deskew */
 		/* wait for idle */
 		timeout = 40;
@@ -376,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-		/* if it's RDIMM */
-		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-					continue;
-				set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-							MD_CNTL_MD_EN |
-							MD_CNTL_CS_SEL(i) |
-							0x070000ed,
-							MD_CNTL_MD_EN);
-				udelay(1);
+		if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+			/* if it's RDIMM */
+			if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+				for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+					if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+						continue;
+					set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+								MD_CNTL_MD_EN |
+								MD_CNTL_CS_SEL(i) |
+								0x070000ed,
+								MD_CNTL_MD_EN);
+					udelay(1);
+				}
 			}
-		}
 
-		ddr_out32(&ddr->err_disable,
-			  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+			ddr_out32(&ddr->err_disable,
+				  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+		}
 #endif
 	}
 #endif
diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index d0075ff1fd..793d12aabb 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -886,7 +886,8 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 	} else
 		popts->ecc_mode = 1;
 #endif
-	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+	/* 1 = use memory controler to init data */
+	popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
 
 	/*
 	 * Choose DQS config
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index a9754922e8..9fb874c0bc 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -25,7 +25,7 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 	loff_t start, lim;
 	size_t count, actual;
 	int ret;
-	nand_info_t *nand;
+	struct mtd_info *mtd;
 
 	/* if buf == NULL return total size of the area */
 	if (buf == NULL) {
@@ -39,16 +39,16 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	    !nand_info[nand_curr_device]->name) {
 		printf("%s: invalid nand device\n", __func__);
 		return -1;
 	}
 
-	nand = &nand_info[nand_curr_device];
+	mtd = nand_info[nand_curr_device];
 
 	if (op == DFU_OP_READ) {
-		ret = nand_read_skip_bad(nand, start, &count, &actual,
-				lim, buf);
+		ret = nand_read_skip_bad(mtd, start, &count, &actual,
+					 lim, buf);
 	} else {
 		nand_erase_options_t opts;
 
@@ -59,12 +59,12 @@ static int nand_block_op(enum dfu_op op, struct dfu_entity *dfu,
 		opts.quiet = 1;
 		opts.lim = lim;
 		/* first erase */
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		if (ret)
 			return ret;
 		/* then write */
-		ret = nand_write_skip_bad(nand, start, &count, &actual,
-				lim, buf, WITH_WR_VERIFY);
+		ret = nand_write_skip_bad(mtd, start, &count, &actual,
+					  lim, buf, WITH_WR_VERIFY);
 	}
 
 	if (ret != 0) {
@@ -139,27 +139,37 @@ static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf,
 static int dfu_flush_medium_nand(struct dfu_entity *dfu)
 {
 	int ret = 0;
+	u64 off;
 
 	/* in case of ubi partition, erase rest of the partition */
 	if (dfu->data.nand.ubi) {
-		nand_info_t *nand;
+		struct mtd_info *mtd;
 		nand_erase_options_t opts;
 
 		if (nand_curr_device < 0 ||
 		    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-		    !nand_info[nand_curr_device].name) {
+		    !nand_info[nand_curr_device]->name) {
 			printf("%s: invalid nand device\n", __func__);
 			return -1;
 		}
 
-		nand = &nand_info[nand_curr_device];
+		mtd = nand_info[nand_curr_device];
 
 		memset(&opts, 0, sizeof(opts));
-		opts.offset = dfu->data.nand.start + dfu->offset +
+		off = dfu->offset;
+		if ((off & (mtd->erasesize - 1)) != 0) {
+			/*
+			 * last write ended with unaligned length
+			 * sector is erased, jump to next
+			 */
+			off = off & ~((mtd->erasesize - 1));
+			off += mtd->erasesize;
+		}
+		opts.offset = dfu->data.nand.start + off +
 				dfu->bad_skip;
 		opts.length = dfu->data.nand.start +
 				dfu->data.nand.size - opts.offset;
-		ret = nand_erase_opts(nand, &opts);
+		ret = nand_erase_opts(mtd, &opts);
 		if (ret != 0)
 			printf("Failure erase: %d\n", ret);
 	}
diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c
index d94eb5cc25..7e2f3e17a7 100644
--- a/drivers/fpga/fpga.c
+++ b/drivers/fpga/fpga.c
@@ -120,7 +120,7 @@ static int fpga_dev_info(int devnum)
 }
 
 /*
- * fgpa_init is usually called from misc_init_r() and MUST be called
+ * fpga_init is usually called from misc_init_r() and MUST be called
  * before any of the other fpga functions are used.
  */
 void fpga_init(void)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93a7e8c6c2..73b862dc0b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,6 +109,21 @@ config SANDBOX_GPIO_COUNT
 	  of 'anonymous' GPIOs that do not belong to any device or bank.
 	  Select a suitable value depending on your needs.
 
+config TEGRA_GPIO
+	bool "Tegra20..210 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra20 through
+	  Tegra210.
+
+config TEGRA186_GPIO
+	bool "Tegra186 GPIO driver"
+	depends on DM_GPIO
+	help
+	  Support for the GPIO controller contained in NVIDIA Tegra186. This
+	  covers both the "main" and "AON" controller instances, even though
+	  they have slightly different register layout.
+
 config GPIO_UNIPHIER
 	bool "UniPhier GPIO"
 	depends on ARCH_UNIPHIER
@@ -173,4 +188,30 @@ config DM_PCA953X
 
 	  Now, max 24 bits chips and PCA953X compatible chips are
 	  supported
+
+config MPC85XX_GPIO
+	bool "Freescale MPC85XX GPIO driver"
+	depends on DM_GPIO
+	help
+	  This driver supports the built-in GPIO controller of MPC85XX CPUs.
+	  Each GPIO bank is identified by its own entry in the device tree,
+	  i.e.
+
+	  gpio-controller@fc00 {
+		#gpio-cells = <2>;
+		compatible = "fsl,pq3-gpio";
+		reg = <0xfc00 0x100>
+	  }
+
+	  By default, each bank is assumed to have 32 GPIOs, but the ngpios
+	  setting is honored, so the number of GPIOs for each bank is
+	  configurable to match the actual GPIO count of the SoC (e.g. the
+	  32/32/23 banks of the P1022 SoC).
+
+	  Aside from the standard functions of input/output mode, and output
+	  value setting, the open-drain feature, which can configure individual
+	  GPIOs to work as open-drain outputs, is supported.
+
+	  The driver has been tested on MPC85XX, but it is likely that other
+	  PowerQUICC III devices will work as well.
 endmenu
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index ddec1ef8de..792d19186a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -31,10 +31,12 @@ obj-$(CONFIG_S5P)		+= s5p_gpio.o
 obj-$(CONFIG_SANDBOX_GPIO)	+= sandbox.o
 obj-$(CONFIG_SPEAR_GPIO)	+= spear_gpio.o
 obj-$(CONFIG_TEGRA_GPIO)	+= tegra_gpio.o
+obj-$(CONFIG_TEGRA186_GPIO)	+= tegra186_gpio.o
 obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
+obj-$(CONFIG_MPC85XX_GPIO)	+= mpc85xx_gpio.o
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 732b6c2afa..4559739d61 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -367,6 +367,38 @@ int dm_gpio_set_value(const struct gpio_desc *desc, int value)
 	return 0;
 }
 
+int dm_gpio_get_open_drain(struct gpio_desc *desc)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "get_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		return ops->get_open_drain(desc->dev, desc->offset);
+	else
+		return -ENOSYS;
+}
+
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value)
+{
+	struct dm_gpio_ops *ops = gpio_get_ops(desc->dev);
+	int ret;
+
+	ret = check_reserved(desc, "set_open_drain");
+	if (ret)
+		return ret;
+
+	if (ops->set_open_drain)
+		ret = ops->set_open_drain(desc->dev, desc->offset, value);
+	else
+		return 0; /* feature not supported -> ignore setting */
+
+	return ret;
+}
+
 int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)
 {
 	struct udevice *dev = desc->dev;
diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c
new file mode 100644
index 0000000000..04773e2b31
--- /dev/null
+++ b/drivers/gpio/mpc85xx_gpio.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2016
+ * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
+ *
+ * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
+ *
+ * Copyright 2010 eXMeritus, A Boeing Company
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <mapmem.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ccsr_gpio {
+	u32	gpdir;
+	u32	gpodr;
+	u32	gpdat;
+	u32	gpier;
+	u32	gpimr;
+	u32	gpicr;
+};
+
+struct mpc85xx_gpio_data {
+	/* The bank's register base in memory */
+	struct ccsr_gpio __iomem *base;
+	/* The address of the registers; used to identify the bank */
+	ulong addr;
+	/* The GPIO count of the bank */
+	uint gpio_count;
+	/* The GPDAT register cannot be used to determine the value of output
+	 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
+	 * for output pins */
+	u32 dat_shadow;
+};
+
+inline u32 gpio_mask(unsigned gpio) {
+	return (1U << (31 - (gpio)));
+}
+
+static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpdat) & mask;
+}
+
+static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpdir) & mask;
+}
+
+static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
+{
+	clrbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 0 -> input */
+	clrbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
+{
+	clrbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be32(&base->gpdir, gpios);
+}
+
+static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
+{
+	setbits_be32(&base->gpdat, gpios);
+	/* GPDIR register 1 -> output */
+	setbits_be32(&base->gpdir, gpios);
+}
+
+static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
+{
+	return in_be32(&base->gpodr) & mask;
+}
+
+static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
+					      gpios)
+{
+	/* GPODR register 1 -> open drain on */
+	setbits_be32(&base->gpodr, gpios);
+}
+
+static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
+					       u32 gpios)
+{
+	/* GPODR register 0 -> open drain off (actively driven) */
+	clrbits_be32(&base->gpodr, gpios);
+}
+
+static int mpc85xx_gpio_direction_input(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
+	return 0;
+}
+
+static int mpc85xx_gpio_set_value(struct udevice *dev, unsigned gpio,
+				  int value)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (value) {
+		data->dat_shadow |= gpio_mask(gpio);
+		mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
+	} else {
+		data->dat_shadow &= ~gpio_mask(gpio);
+		mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
+	}
+	return 0;
+}
+
+static int mpc85xx_gpio_direction_output(struct udevice *dev, unsigned gpio,
+					 int value)
+{
+	return mpc85xx_gpio_set_value(dev, gpio, value);
+}
+
+static int mpc85xx_gpio_get_value(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
+		/* Output -> use shadowed value */
+		return !!(data->dat_shadow & gpio_mask(gpio));
+	} else {
+		/* Input -> read value from GPDAT register */
+		return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
+	}
+}
+
+static int mpc85xx_gpio_get_open_drain(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
+}
+
+static int mpc85xx_gpio_set_open_drain(struct udevice *dev, unsigned gpio,
+				       int value)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+
+	if (value) {
+		mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
+	} else {
+		mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
+	}
+	return 0;
+}
+
+static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio)
+{
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	int dir;
+
+	dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
+	return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
+}
+
+static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) {
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	fdt_addr_t addr;
+	fdt_size_t size;
+
+	addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+						  "reg", 0, &size);
+
+	data->addr = addr;
+	data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
+
+	if (!data->base)
+		return -ENOMEM;
+
+	data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					  "ngpios", 32);
+	data->dat_shadow = 0;
+
+	return 0;
+}
+
+static int mpc85xx_gpio_probe(struct udevice *dev)
+{
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct mpc85xx_gpio_data *data = dev_get_priv(dev);
+	char name[32], *str;
+
+	snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+	str = strdup(name);
+
+	if (!str)
+		return -ENOMEM;
+
+	uc_priv->bank_name = str;
+	uc_priv->gpio_count = data->gpio_count;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops gpio_mpc85xx_ops = {
+	.direction_input	= mpc85xx_gpio_direction_input,
+	.direction_output	= mpc85xx_gpio_direction_output,
+	.get_value		= mpc85xx_gpio_get_value,
+	.set_value		= mpc85xx_gpio_set_value,
+	.get_open_drain		= mpc85xx_gpio_get_open_drain,
+	.set_open_drain		= mpc85xx_gpio_set_open_drain,
+	.get_function 		= mpc85xx_gpio_get_function,
+};
+
+static const struct udevice_id mpc85xx_gpio_ids[] = {
+	{ .compatible = "fsl,pq3-gpio" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(gpio_mpc85xx) = {
+	.name	= "gpio_mpc85xx",
+	.id	= UCLASS_GPIO,
+	.ops	= &gpio_mpc85xx_ops,
+	.ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
+	.of_match = mpc85xx_gpio_ids,
+	.probe	= mpc85xx_gpio_probe,
+	.priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),
+};
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index b54a10b493..c25b4c1c2e 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <asm/errno.h>
 #include <asm/io.h>
 #include <asm/arch/iomux.h>
diff --git a/drivers/gpio/pca953x_gpio.c b/drivers/gpio/pca953x_gpio.c
index 987d10e967..065b181bd2 100644
--- a/drivers/gpio/pca953x_gpio.c
+++ b/drivers/gpio/pca953x_gpio.c
@@ -16,8 +16,8 @@
  *
  * TODO:
  * 1. Support PCA957X_TYPE
- * 2. Support max 40 gpio pins
- * 3. Support Plolarity Inversion
+ * 2. Support 24 gpio pins
+ * 3. Support Polarity Inversion
  */
 
 #include <common.h>
@@ -47,7 +47,7 @@ enum {
 	PCA953X_DIRECTION_OUT,
 };
 
-#define MAX_BANK 3
+#define MAX_BANK 5
 #define BANK_SZ 8
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -121,6 +121,9 @@ static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
 		ret = dm_i2c_read(dev, reg, val, 1);
 	} else if (info->gpio_count <= 16) {
 		ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
+	} else if (info->gpio_count == 40) {
+		/* Auto increment */
+		ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
 	} else {
 		dev_err(dev, "Unsupported now\n");
 		return -EINVAL;
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
index fefe3ca203..64abcbaa0a 100644
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -8,7 +8,6 @@
  */
 
 #include <common.h>
-#include <clk.h>
 #include <dm.h>
 #include <syscon.h>
 #include <asm/errno.h>
diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c
index a9b1efcd06..f6435a0543 100644
--- a/drivers/gpio/sandbox.c
+++ b/drivers/gpio/sandbox.c
@@ -15,6 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Flags for each GPIO */
 #define GPIOF_OUTPUT	(1 << 0)	/* Currently set as an output */
 #define GPIOF_HIGH	(1 << 1)	/* Currently set high */
+#define GPIOF_ODR	(1 << 2)	/* Currently set to open drain mode */
 
 struct gpio_state {
 	const char *label;	/* label given by requester */
@@ -70,6 +71,16 @@ int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
 }
 
+int sandbox_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	return get_gpio_flag(dev, offset, GPIOF_ODR);
+}
+
+int sandbox_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	return set_gpio_flag(dev, offset, GPIOF_ODR, value);
+}
+
 int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
 {
 	return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
@@ -124,6 +135,28 @@ static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
 	return sandbox_gpio_set_value(dev, offset, value);
 }
 
+/* read GPIO ODR value of port 'offset' */
+static int sb_gpio_get_open_drain(struct udevice *dev, unsigned offset)
+{
+	debug("%s: offset:%u\n", __func__, offset);
+
+	return sandbox_gpio_get_open_drain(dev, offset);
+}
+
+/* write GPIO ODR value to port 'offset' */
+static int sb_gpio_set_open_drain(struct udevice *dev, unsigned offset, int value)
+{
+	debug("%s: offset:%u, value = %d\n", __func__, offset, value);
+
+	if (!sandbox_gpio_get_direction(dev, offset)) {
+		printf("sandbox_gpio: error: set_open_drain on input gpio %u\n",
+		       offset);
+		return -1;
+	}
+
+	return sandbox_gpio_set_open_drain(dev, offset, value);
+}
+
 static int sb_gpio_get_function(struct udevice *dev, unsigned offset)
 {
 	if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
@@ -154,6 +187,8 @@ static const struct dm_gpio_ops gpio_sandbox_ops = {
 	.direction_output	= sb_gpio_direction_output,
 	.get_value		= sb_gpio_get_value,
 	.set_value		= sb_gpio_set_value,
+	.get_open_drain		= sb_gpio_get_open_drain,
+	.set_open_drain		= sb_gpio_set_open_drain,
 	.get_function		= sb_gpio_get_function,
 	.xlate			= sb_gpio_xlate,
 };
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index a7cec18d57..94abbeb39a 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -258,43 +258,30 @@ static int gpio_sunxi_probe(struct udevice *dev)
 
 	return 0;
 }
+
+struct sunxi_gpio_soc_data {
+	int start;
+	int no_banks;
+};
+
 /**
  * We have a top-level GPIO device with no actual GPIOs. It has a child
  * device for each Sunxi bank.
  */
 static int gpio_sunxi_bind(struct udevice *parent)
 {
+	struct sunxi_gpio_soc_data *soc_data =
+		(struct sunxi_gpio_soc_data *)dev_get_driver_data(parent);
 	struct sunxi_gpio_platdata *plat = parent->platdata;
 	struct sunxi_gpio_reg *ctlr;
-	int bank, no_banks, ret, start;
+	int bank, ret;
 
 	/* If this is a child device, there is nothing to do here */
 	if (plat)
 		return 0;
 
-	if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun6i-a31-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 2; /* L & M */
-	} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-a23-r-pinctrl") == 0 ||
-		   fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-a83t-r-pinctrl") == 0 ||
-		   fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun8i-h3-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 1; /* L only */
-	} else if (fdt_node_check_compatible(gd->fdt_blob, parent->of_offset,
-				"allwinner,sun9i-a80-r-pinctrl") == 0) {
-		start = 'L' - 'A';
-		no_banks = 3; /* L, M & N */
-	} else {
-		start = 0;
-		no_banks = SUNXI_GPIO_BANKS;
-	}
-
 	ctlr = (struct sunxi_gpio_reg *)dev_get_addr(parent);
-	for (bank = 0; bank < no_banks; bank++) {
+	for (bank = 0; bank < soc_data->no_banks; bank++) {
 		struct sunxi_gpio_platdata *plat;
 		struct udevice *dev;
 
@@ -302,7 +289,7 @@ static int gpio_sunxi_bind(struct udevice *parent)
 		if (!plat)
 			return -ENOMEM;
 		plat->regs = &ctlr->gpio_bank[bank];
-		plat->bank_name = gpio_bank_name(start + bank);
+		plat->bank_name = gpio_bank_name(soc_data->start + bank);
 		plat->gpio_count = SUNXI_GPIOS_PER_BANK;
 
 		ret = device_bind(parent, parent->driver,
@@ -315,23 +302,46 @@ static int gpio_sunxi_bind(struct udevice *parent)
 	return 0;
 }
 
+static const struct sunxi_gpio_soc_data soc_data_a_all = {
+	.start = 0,
+	.no_banks = SUNXI_GPIO_BANKS,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_1 = {
+	.start = 'L' - 'A',
+	.no_banks = 1,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_2 = {
+	.start = 'L' - 'A',
+	.no_banks = 2,
+};
+
+static const struct sunxi_gpio_soc_data soc_data_l_3 = {
+	.start = 'L' - 'A',
+	.no_banks = 3,
+};
+
+#define ID(_compat_, _soc_data_) \
+	{ .compatible = _compat_, .data = (ulong)&soc_data_##_soc_data_ }
+
 static const struct udevice_id sunxi_gpio_ids[] = {
-	{ .compatible = "allwinner,sun4i-a10-pinctrl" },
-	{ .compatible = "allwinner,sun5i-a10s-pinctrl" },
-	{ .compatible = "allwinner,sun5i-a13-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31s-pinctrl" },
-	{ .compatible = "allwinner,sun7i-a20-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a23-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a33-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a83t-pinctrl", },
-	{ .compatible = "allwinner,sun8i-h3-pinctrl" },
-	{ .compatible = "allwinner,sun9i-a80-pinctrl" },
-	{ .compatible = "allwinner,sun6i-a31-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a23-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-a83t-r-pinctrl" },
-	{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
-	{ .compatible = "allwinner,sun9i-a80-r-pinctrl", },
+	ID("allwinner,sun4i-a10-pinctrl",	a_all),
+	ID("allwinner,sun5i-a10s-pinctrl",	a_all),
+	ID("allwinner,sun5i-a13-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31s-pinctrl",	a_all),
+	ID("allwinner,sun7i-a20-pinctrl",	a_all),
+	ID("allwinner,sun8i-a23-pinctrl",	a_all),
+	ID("allwinner,sun8i-a33-pinctrl",	a_all),
+	ID("allwinner,sun8i-a83t-pinctrl",	a_all),
+	ID("allwinner,sun8i-h3-pinctrl",	a_all),
+	ID("allwinner,sun9i-a80-pinctrl",	a_all),
+	ID("allwinner,sun6i-a31-r-pinctrl",	l_2),
+	ID("allwinner,sun8i-a23-r-pinctrl",	l_1),
+	ID("allwinner,sun8i-a83t-r-pinctrl",	l_1),
+	ID("allwinner,sun8i-h3-r-pinctrl",	l_1),
+	ID("allwinner,sun9i-a80-r-pinctrl",	l_3),
 	{ }
 };
 
diff --git a/drivers/gpio/tegra186_gpio.c b/drivers/gpio/tegra186_gpio.c
new file mode 100644
index 0000000000..1c681514db
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION.
+ * (based on tegra_gpio.c)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+#include <asm/gpio.h>
+#include <dm/device-internal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "tegra186_gpio_priv.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct tegra186_gpio_port_data {
+	const char *name;
+	uint32_t offset;
+};
+
+struct tegra186_gpio_ctlr_data {
+	const struct tegra186_gpio_port_data *ports;
+	uint32_t port_count;
+};
+
+struct tegra186_gpio_platdata {
+	const char *name;
+	uint32_t *regs;
+};
+
+static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
+				   uint32_t gpio)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
+
+	return &(plat->regs[index]);
+}
+
+static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
+				 bool output)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
+	rval = readl(reg);
+	if (output)
+		rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	else
+		rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
+	writel(rval, reg);
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (output)
+		rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	else
+		rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
+	rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
+	rval = readl(reg);
+	if (val)
+		rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	else
+		rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
+	writel(rval, reg);
+
+	return 0;
+}
+
+static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+	return tegra186_gpio_set_out(dev, offset, false);
+}
+
+static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
+				       int value)
+{
+	int ret;
+
+	ret = tegra186_gpio_set_val(dev, offset, value != 0);
+	if (ret)
+		return ret;
+	return tegra186_gpio_set_out(dev, offset, true);
+}
+
+static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
+					offset);
+	else
+		reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
+
+	rval = readl(reg);
+	return !!rval;
+}
+
+static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
+				   int value)
+{
+	return tegra186_gpio_set_val(dev, offset, value != 0);
+}
+
+static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	uint32_t *reg;
+	uint32_t rval;
+
+	reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
+	rval = readl(reg);
+	if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
+static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+			    struct fdtdec_phandle_args *args)
+{
+	int gpio, port, ret;
+
+	gpio = args->args[0];
+	port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
+	ret = device_get_child(dev, port, &desc->dev);
+	if (ret)
+		return ret;
+	desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
+	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+	return 0;
+}
+
+static const struct dm_gpio_ops tegra186_gpio_ops = {
+	.direction_input	= tegra186_gpio_direction_input,
+	.direction_output	= tegra186_gpio_direction_output,
+	.get_value		= tegra186_gpio_get_value,
+	.set_value		= tegra186_gpio_set_value,
+	.get_function		= tegra186_gpio_get_function,
+	.xlate			= tegra186_gpio_xlate,
+};
+
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child device
+ * for each port within the controller.
+ */
+static int tegra186_gpio_bind(struct udevice *parent)
+{
+	struct tegra186_gpio_platdata *parent_plat = parent->platdata;
+	struct tegra186_gpio_ctlr_data *ctlr_data =
+		(struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
+	uint32_t *regs;
+	int port, ret;
+
+	/* If this is a child device, there is nothing to do here */
+	if (parent_plat)
+		return 0;
+
+	regs = (uint32_t *)dev_get_addr_name(parent, "gpio");
+	if (regs == (uint32_t *)FDT_ADDR_T_NONE)
+		return -ENODEV;
+
+	for (port = 0; port < ctlr_data->port_count; port++) {
+		struct tegra186_gpio_platdata *plat;
+		struct udevice *dev;
+
+		plat = calloc(1, sizeof(*plat));
+		if (!plat)
+			return -ENOMEM;
+		plat->name = ctlr_data->ports[port].name;
+		plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
+
+		ret = device_bind(parent, parent->driver, plat->name, plat,
+				  -1, &dev);
+		if (ret)
+			return ret;
+		dev->of_offset = parent->of_offset;
+	}
+
+	return 0;
+}
+
+static int tegra186_gpio_probe(struct udevice *dev)
+{
+	struct tegra186_gpio_platdata *plat = dev->platdata;
+	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	/* Only child devices have ports */
+	if (!plat)
+		return 0;
+
+	uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
+	uc_priv->bank_name = plat->name;
+
+	return 0;
+}
+
+static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
+	{"A",  0x2000},
+	{"B",  0x3000},
+	{"C",  0x3200},
+	{"D",  0x3400},
+	{"E",  0x2200},
+	{"F",  0x2400},
+	{"G",  0x4200},
+	{"H",  0x1000},
+	{"I",  0x0800},
+	{"J",  0x5000},
+	{"K",  0x5200},
+	{"L",  0x1200},
+	{"M",  0x5600},
+	{"N",  0x0000},
+	{"O",  0x0200},
+	{"P",  0x4000},
+	{"Q",  0x0400},
+	{"R",  0x0a00},
+	{"T",  0x0600},
+	{"X",  0x1400},
+	{"Y",  0x1600},
+	{"BB", 0x2600},
+	{"CC", 0x5400},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
+	.ports = tegra186_gpio_main_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
+};
+
+static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
+	{"S",  0x0200},
+	{"U",  0x0400},
+	{"V",  0x0800},
+	{"W",  0x0a00},
+	{"Z",  0x0e00},
+	{"AA", 0x0c00},
+	{"EE", 0x0600},
+	{"FF", 0x0000},
+};
+
+static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
+	.ports = tegra186_gpio_aon_ports,
+	.port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
+};
+
+static const struct udevice_id tegra186_gpio_ids[] = {
+	{
+		.compatible = "nvidia,tegra186-gpio",
+		.data = (ulong)&tegra186_gpio_main_data,
+	},
+	{
+		.compatible = "nvidia,tegra186-gpio-aon",
+		.data = (ulong)&tegra186_gpio_aon_data,
+	},
+	{ }
+};
+
+U_BOOT_DRIVER(tegra186_gpio) = {
+	.name = "tegra186_gpio",
+	.id = UCLASS_GPIO,
+	.of_match = tegra186_gpio_ids,
+	.bind = tegra186_gpio_bind,
+	.probe = tegra186_gpio_probe,
+	.ops = &tegra186_gpio_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/gpio/tegra186_gpio_priv.h b/drivers/gpio/tegra186_gpio_priv.h
new file mode 100644
index 0000000000..9e85a4343b
--- /dev/null
+++ b/drivers/gpio/tegra186_gpio_priv.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_GPIO_PRIV_H_
+#define _TEGRA186_GPIO_PRIV_H_
+
+/*
+ * For each GPIO, there are a set of registers than affect it, all packed
+ * back-to-back.
+ */
+#define TEGRA186_GPIO_ENABLE_CONFIG				0x00
+#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE			BIT(0)
+#define TEGRA186_GPIO_ENABLE_CONFIG_OUT				BIT(1)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT		2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK		3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE		0
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL		1
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE	2
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE	3
+#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING	BIT(4)
+#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE		BIT(5)
+#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE		BIT(6)
+#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE		BIT(7)
+
+#define TEGRA186_GPIO_DEBOUNCE_THRESHOLD			0x04
+
+#define TEGRA186_GPIO_INPUT					0x08
+
+#define TEGRA186_GPIO_OUTPUT_CONTROL				0x0c
+#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED			BIT(0)
+
+#define TEGRA186_GPIO_OUTPUT_VALUE				0x10
+#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH				1
+
+#define TEGRA186_GPIO_INTERRUPT_CLEAR				0x14
+
+/*
+ * 8 GPIOs are packed into a port. Their registers appear back-to-back in the
+ * port's address space.
+ */
+#define TEGRA186_GPIO_PER_GPIO_STRIDE				0x20
+#define TEGRA186_GPIO_PER_GPIO_COUNT				8
+
+/*
+ * Per-port registers are packed immediately following all of a port's
+ * per-GPIO registers.
+ */
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G			0x100
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE			4
+#define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT			8
+
+/*
+ * The registers for multiple ports are packed together back-to-back to form
+ * the overall controller.
+ */
+#define TEGRA186_GPIO_PER_PORT_STRIDE				0x200
+
+#endif
diff --git a/drivers/gpio/zynq_gpio.c b/drivers/gpio/zynq_gpio.c
index 3a995f610c..4ab2356081 100644
--- a/drivers/gpio/zynq_gpio.c
+++ b/drivers/gpio/zynq_gpio.c
@@ -299,11 +299,33 @@ static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
 	return 0;
 }
 
+static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+	u32 reg;
+	unsigned int bank_num, bank_pin_num;
+	struct zynq_gpio_privdata *priv = dev_get_priv(dev);
+
+	if (check_gpio(offset, dev) < 0)
+		return -1;
+
+	zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
+
+	/* set the GPIO pin as output */
+	reg = readl(priv->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
+	reg &= BIT(bank_pin_num);
+	if (reg)
+		return GPIOF_OUTPUT;
+	else
+		return GPIOF_INPUT;
+}
+
 static const struct dm_gpio_ops gpio_zynq_ops = {
 	.direction_input	= zynq_gpio_direction_input,
 	.direction_output	= zynq_gpio_direction_output,
 	.get_value		= zynq_gpio_get_value,
 	.set_value		= zynq_gpio_set_value,
+	.get_function		= zynq_gpio_get_function,
+
 };
 
 static const struct udevice_id zynq_gpio_ids[] = {
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
new file mode 100644
index 0000000000..9087512390
--- /dev/null
+++ b/drivers/mailbox/Kconfig
@@ -0,0 +1,20 @@
+menu "Mailbox Controller Support"
+
+config DM_MAILBOX
+	bool "Enable mailbox controllers using Driver Model"
+	depends on DM && OF_CONTROL
+	help
+	  Enable support for the mailbox driver class. Mailboxes provide the
+	  ability to transfer small messages and/or notifications from one
+	  CPU to another CPU, or sometimes to dedicated HW modules. They form
+	  the basis of a variety of inter-process/inter-CPU communication
+	  protocols.
+
+config SANDBOX_MBOX
+	bool "Enable the sandbox mailbox test driver"
+	depends on DM_MAILBOX && SANDBOX
+	help
+	  Enable support for a test mailbox implementation, which simply echos
+	  back a modified version of any message that is sent.
+
+endmenu
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
new file mode 100644
index 0000000000..bbae4def6d
--- /dev/null
+++ b/drivers/mailbox/Makefile
@@ -0,0 +1,7 @@
+# Copyright (c) 2016, NVIDIA CORPORATION.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_DM_MAILBOX) += mailbox-uclass.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o
+obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o
diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c
new file mode 100644
index 0000000000..73fa32874a
--- /dev/null
+++ b/drivers/mailbox/mailbox-uclass.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <mailbox_client.h>
+#include <mailbox_uclass.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static inline struct mbox_ops *mbox_dev_ops(struct udevice *dev)
+{
+	return (struct mbox_ops *)dev->driver->ops;
+}
+
+static int mbox_of_xlate_default(struct mbox_chan *chan,
+				 struct fdtdec_phandle_args *args)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (args->args_count != 1) {
+		debug("Invaild args_count: %d\n", args->args_count);
+		return -EINVAL;
+	}
+
+	chan->id = args->args[0];
+
+	return 0;
+}
+
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan)
+{
+	struct fdtdec_phandle_args args;
+	int ret;
+	struct udevice *dev_mbox;
+	struct mbox_ops *ops;
+
+	debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
+
+	ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+					     "mboxes", "#mbox-cells", 0,
+					     index, &args);
+	if (ret) {
+		debug("%s: fdtdec_parse_phandle_with_args failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device_by_of_offset(UCLASS_MAILBOX, args.node,
+					     &dev_mbox);
+	if (ret) {
+		debug("%s: uclass_get_device_by_of_offset failed: %d\n",
+		      __func__, ret);
+		return ret;
+	}
+	ops = mbox_dev_ops(dev_mbox);
+
+	chan->dev = dev_mbox;
+	if (ops->of_xlate)
+		ret = ops->of_xlate(chan, &args);
+	else
+		ret = mbox_of_xlate_default(chan, &args);
+	if (ret) {
+		debug("of_xlate() failed: %d\n", ret);
+		return ret;
+	}
+
+	ret = ops->request(chan);
+	if (ret) {
+		debug("ops->request() failed: %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan)
+{
+	int index;
+
+	debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
+
+	index = fdt_find_string(gd->fdt_blob, dev->of_offset, "mbox-names",
+				name);
+	if (index < 0) {
+		debug("fdt_find_string() failed: %d\n", index);
+		return index;
+	}
+
+	return mbox_get_by_index(dev, index, chan);
+}
+
+int mbox_free(struct mbox_chan *chan)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return ops->free(chan);
+}
+
+int mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	return ops->send(chan, data);
+}
+
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us)
+{
+	struct mbox_ops *ops = mbox_dev_ops(chan->dev);
+	ulong start_time;
+	int ret;
+
+	debug("%s(chan=%p, data=%p, timeout_us=%ld)\n", __func__, chan, data,
+	      timeout_us);
+
+	start_time = timer_get_us();
+	/*
+	 * Account for partial us ticks, but if timeout_us is 0, ensure we
+	 * still don't wait at all.
+	 */
+	if (timeout_us)
+		timeout_us++;
+
+	for (;;) {
+		ret = ops->recv(chan, data);
+		if (ret != -ENODATA)
+			return ret;
+		if ((timer_get_us() - start_time) >= timeout_us)
+			return -ETIMEDOUT;
+	}
+}
+
+UCLASS_DRIVER(mailbox) = {
+	.id		= UCLASS_MAILBOX,
+	.name		= "mailbox",
+};
diff --git a/drivers/mailbox/sandbox-mbox-test.c b/drivers/mailbox/sandbox-mbox-test.c
new file mode 100644
index 0000000000..02d161aada
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox-test.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_client.h>
+#include <asm/io.h>
+
+struct sandbox_mbox_test {
+	struct mbox_chan chan;
+};
+
+int sandbox_mbox_test_get(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_get_by_name(dev, "test", &sbmt->chan);
+}
+
+int sandbox_mbox_test_send(struct udevice *dev, uint32_t msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_send(&sbmt->chan, &msg);
+}
+
+int sandbox_mbox_test_recv(struct udevice *dev, uint32_t *msg)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_recv(&sbmt->chan, msg, 100);
+}
+
+int sandbox_mbox_test_free(struct udevice *dev)
+{
+	struct sandbox_mbox_test *sbmt = dev_get_priv(dev);
+
+	return mbox_free(&sbmt->chan);
+}
+
+static const struct udevice_id sandbox_mbox_test_ids[] = {
+	{ .compatible = "sandbox,mbox-test" },
+	{ }
+};
+
+U_BOOT_DRIVER(sandbox_mbox_test) = {
+	.name = "sandbox_mbox_test",
+	.id = UCLASS_MISC,
+	.of_match = sandbox_mbox_test_ids,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox_test),
+};
diff --git a/drivers/mailbox/sandbox-mbox.c b/drivers/mailbox/sandbox-mbox.c
new file mode 100644
index 0000000000..1b7ac231cb
--- /dev/null
+++ b/drivers/mailbox/sandbox-mbox.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <mailbox_uclass.h>
+#include <asm/io.h>
+#include <asm/mbox.h>
+
+#define SANDBOX_MBOX_CHANNELS 2
+
+struct sandbox_mbox_chan {
+	bool rx_msg_valid;
+	uint32_t rx_msg;
+};
+
+struct sandbox_mbox {
+	struct sandbox_mbox_chan chans[SANDBOX_MBOX_CHANNELS];
+};
+
+static int sandbox_mbox_request(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	if (chan->id >= SANDBOX_MBOX_CHANNELS)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int sandbox_mbox_free(struct mbox_chan *chan)
+{
+	debug("%s(chan=%p)\n", __func__, chan);
+
+	return 0;
+}
+
+static int sandbox_mbox_send(struct mbox_chan *chan, const void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	const uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	sbm->chans[chan->id].rx_msg = *pmsg ^ SANDBOX_MBOX_PING_XOR;
+	sbm->chans[chan->id].rx_msg_valid = true;
+
+	return 0;
+}
+
+static int sandbox_mbox_recv(struct mbox_chan *chan, void *data)
+{
+	struct sandbox_mbox *sbm = dev_get_priv(chan->dev);
+	uint32_t *pmsg = data;
+
+	debug("%s(chan=%p, data=%p)\n", __func__, chan, data);
+
+	if (!sbm->chans[chan->id].rx_msg_valid)
+		return -ENODATA;
+
+	*pmsg = sbm->chans[chan->id].rx_msg;
+	sbm->chans[chan->id].rx_msg_valid = false;
+
+	return 0;
+}
+
+static int sandbox_mbox_bind(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static int sandbox_mbox_probe(struct udevice *dev)
+{
+	debug("%s(dev=%p)\n", __func__, dev);
+
+	return 0;
+}
+
+static const struct udevice_id sandbox_mbox_ids[] = {
+	{ .compatible = "sandbox,mbox" },
+	{ }
+};
+
+struct mbox_ops sandbox_mbox_mbox_ops = {
+	.request = sandbox_mbox_request,
+	.free = sandbox_mbox_free,
+	.send = sandbox_mbox_send,
+	.recv = sandbox_mbox_recv,
+};
+
+U_BOOT_DRIVER(sandbox_mbox) = {
+	.name = "sandbox_mbox",
+	.id = UCLASS_MAILBOX,
+	.of_match = sandbox_mbox_ids,
+	.bind = sandbox_mbox_bind,
+	.probe = sandbox_mbox_probe,
+	.priv_auto_alloc_size = sizeof(struct sandbox_mbox),
+	.ops = &sandbox_mbox_mbox_ops,
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index af8667f030..2373037685 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -121,13 +121,13 @@ config PCA9551_I2C_ADDR
 	help
 	  The I2C address of the PCA9551 LED controller.
 
-config RESET
-	bool "Enable support for reset drivers"
+config SYSRESET
+	bool "Enable support for system reset drivers"
 	depends on DM
 	help
-	  Enable reset drivers which can be used to reset the CPU or board.
-	  Each driver can provide a reset method which will be called to
-	  effect a reset. The uclass will try all available drivers when
+	  Enable system reset drivers which can be used to reset the CPU or
+	  board. Each driver can provide a reset method which will be called
+	  to effect a reset. The uclass will try all available drivers when
 	  reset_walk() is called.
 
 config WINBOND_W83627
@@ -138,4 +138,10 @@ config WINBOND_W83627
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QFW
+	bool
+	help
+	  Hidden option to enable QEMU fw_cfg interface. This will be selected by
+	  either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 5969d34444..066639ba1f 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_PDSP188x) += pdsp188x.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
-obj-$(CONFIG_SANDBOX) += reset_sandbox.o
+obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 ifdef CONFIG_DM_I2C
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
@@ -40,6 +40,7 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
-obj-$(CONFIG_RESET) += reset-uclass.o
+obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
+obj-$(CONFIG_QFW) += qfw.o
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/drivers/misc/qfw.c
index 2e2794ebd7..d43d1d300a 100644
--- a/arch/x86/cpu/qemu/fw_cfg.c
+++ b/drivers/misc/qfw.c
@@ -8,220 +8,20 @@
 #include <command.h>
 #include <errno.h>
 #include <malloc.h>
+#include <qfw.h>
 #include <asm/io.h>
-#include <asm/fw_cfg.h>
+#ifdef CONFIG_GENERATE_ACPI_TABLE
 #include <asm/tables.h>
-#include <asm/e820.h>
+#endif
 #include <linux/list.h>
-#include <memalign.h>
 
 static bool fwcfg_present;
 static bool fwcfg_dma_present;
+static struct fw_cfg_arch_ops *fwcfg_arch_ops;
 
 static LIST_HEAD(fw_list);
 
-/* Read configuration item using fw_cfg PIO interface */
-static void qemu_fwcfg_read_entry_pio(uint16_t entry,
-		uint32_t size, void *address)
-{
-	uint32_t i = 0;
-	uint8_t *data = address;
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		outw(entry, FW_CONTROL_PORT);
-	while (size--)
-		data[i++] = inb(FW_DATA_PORT);
-}
-
-/* Read configuration item using fw_cfg DMA interface */
-static void qemu_fwcfg_read_entry_dma(uint16_t entry,
-		uint32_t size, void *address)
-{
-	struct fw_cfg_dma_access dma;
-
-	dma.length = cpu_to_be32(size);
-	dma.address = cpu_to_be64((uintptr_t)address);
-	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
-
-	/*
-	 * writting FW_CFG_INVALID will cause read operation to resume at
-	 * last offset, otherwise read will start at offset 0
-	 */
-	if (entry != FW_CFG_INVALID)
-		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
-
-	barrier();
-
-	debug("qemu_fwcfg_dma_read_entry: addr %p, length %u control 0x%x\n",
-	      address, size, be32_to_cpu(dma.control));
-
-	outl(cpu_to_be32((uint32_t)&dma), FW_DMA_PORT_HIGH);
-
-	while (be32_to_cpu(dma.control) & ~FW_CFG_DMA_ERROR)
-		__asm__ __volatile__ ("pause");
-}
-
-static bool qemu_fwcfg_present(void)
-{
-	uint32_t qemu;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
-	return be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE;
-}
-
-static bool qemu_fwcfg_dma_present(void)
-{
-	uint8_t dma_enabled;
-
-	qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
-	if (dma_enabled & FW_CFG_DMA_ENABLED)
-		return true;
-
-	return false;
-}
-
-static void qemu_fwcfg_read_entry(uint16_t entry,
-		uint32_t length, void *address)
-{
-	if (fwcfg_dma_present)
-		qemu_fwcfg_read_entry_dma(entry, length, address);
-	else
-		qemu_fwcfg_read_entry_pio(entry, length, address);
-}
-
-int qemu_fwcfg_online_cpus(void)
-{
-	uint16_t nb_cpus;
-
-	if (!fwcfg_present)
-		return -ENODEV;
-
-	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
-
-	return le16_to_cpu(nb_cpus);
-}
-
-/*
- * This function prepares kernel for zboot. It loads kernel data
- * to 'load_addr', initrd to 'initrd_addr' and kernel command
- * line using qemu fw_cfg interface.
- */
-static int qemu_fwcfg_setup_kernel(void *load_addr, void *initrd_addr)
-{
-	char *data_addr;
-	uint32_t setup_size, kernel_size, cmdline_size, initrd_size;
-
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_SIZE, 4, &setup_size);
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_SIZE, 4, &kernel_size);
-
-	if (setup_size == 0 || kernel_size == 0) {
-		printf("warning: no kernel available\n");
-		return -1;
-	}
-
-	data_addr = load_addr;
-	qemu_fwcfg_read_entry(FW_CFG_SETUP_DATA,
-			      le32_to_cpu(setup_size), data_addr);
-	data_addr += le32_to_cpu(setup_size);
-
-	qemu_fwcfg_read_entry(FW_CFG_KERNEL_DATA,
-			      le32_to_cpu(kernel_size), data_addr);
-	data_addr += le32_to_cpu(kernel_size);
-
-	data_addr = initrd_addr;
-	qemu_fwcfg_read_entry(FW_CFG_INITRD_SIZE, 4, &initrd_size);
-	if (initrd_size == 0) {
-		printf("warning: no initrd available\n");
-	} else {
-		qemu_fwcfg_read_entry(FW_CFG_INITRD_DATA,
-				      le32_to_cpu(initrd_size), data_addr);
-		data_addr += le32_to_cpu(initrd_size);
-	}
-
-	qemu_fwcfg_read_entry(FW_CFG_CMDLINE_SIZE, 4, &cmdline_size);
-	if (cmdline_size) {
-		qemu_fwcfg_read_entry(FW_CFG_CMDLINE_DATA,
-				      le32_to_cpu(cmdline_size), data_addr);
-		/*
-		 * if kernel cmdline only contains '\0', (e.g. no -append
-		 * when invoking qemu), do not update bootargs
-		 */
-		if (*data_addr != '\0') {
-			if (setenv("bootargs", data_addr) < 0)
-				printf("warning: unable to change bootargs\n");
-		}
-	}
-
-	printf("loading kernel to address %p size %x", load_addr,
-	       le32_to_cpu(kernel_size));
-	if (initrd_size)
-		printf(" initrd %p size %x\n",
-		       initrd_addr,
-		       le32_to_cpu(initrd_size));
-	else
-		printf("\n");
-
-	return 0;
-}
-
-static int qemu_fwcfg_read_firmware_list(void)
-{
-	int i;
-	uint32_t count;
-	struct fw_file *file;
-	struct list_head *entry;
-
-	/* don't read it twice */
-	if (!list_empty(&fw_list))
-		return 0;
-
-	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
-	if (!count)
-		return 0;
-
-	count = be32_to_cpu(count);
-	for (i = 0; i < count; i++) {
-		file = malloc(sizeof(*file));
-		if (!file) {
-			printf("error: allocating resource\n");
-			goto err;
-		}
-		qemu_fwcfg_read_entry(FW_CFG_INVALID,
-				      sizeof(struct fw_cfg_file), &file->cfg);
-		file->addr = 0;
-		list_add_tail(&file->list, &fw_list);
-	}
-
-	return 0;
-
-err:
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		free(file);
-	}
-
-	return -ENOMEM;
-}
-
-#ifdef CONFIG_QEMU_ACPI_TABLE
-static struct fw_file *qemu_fwcfg_find_file(const char *name)
-{
-	struct list_head *entry;
-	struct fw_file *file;
-
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		if (!strcmp(file->cfg.name, name))
-			return file;
-	}
-
-	return NULL;
-}
-
+#ifdef CONFIG_GENERATE_ACPI_TABLE
 /*
  * This function allocates memory for ACPI tables
  *
@@ -346,41 +146,6 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry)
 	return 0;
 }
 
-unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
-{
-	entries[0].addr = 0;
-	entries[0].size = ISA_START_ADDRESS;
-	entries[0].type = E820_RAM;
-
-	entries[1].addr = ISA_START_ADDRESS;
-	entries[1].size = ISA_END_ADDRESS - ISA_START_ADDRESS;
-	entries[1].type = E820_RESERVED;
-
-	/*
-	 * since we use memalign(malloc) to allocate high memory for
-	 * storing ACPI tables, we need to reserve them in e820 tables,
-	 * otherwise kernel will reclaim them and data will be corrupted
-	 */
-	entries[2].addr = ISA_END_ADDRESS;
-	entries[2].size = gd->relocaddr - TOTAL_MALLOC_LEN - ISA_END_ADDRESS;
-	entries[2].type = E820_RAM;
-
-	/* for simplicity, reserve entire malloc space */
-	entries[3].addr = gd->relocaddr - TOTAL_MALLOC_LEN;
-	entries[3].size = TOTAL_MALLOC_LEN;
-	entries[3].type = E820_RESERVED;
-
-	entries[4].addr = gd->relocaddr;
-	entries[4].size = gd->ram_size - gd->relocaddr;
-	entries[4].type = E820_RESERVED;
-
-	entries[5].addr = CONFIG_PCIE_ECAM_BASE;
-	entries[5].size = CONFIG_PCIE_ECAM_SIZE;
-	entries[5].type = E820_RESERVED;
-
-	return 6;
-}
-
 /* This function loads and patches ACPI tables provided by QEMU */
 u32 write_acpi_tables(u32 addr)
 {
@@ -389,7 +154,6 @@ u32 write_acpi_tables(u32 addr)
 	struct bios_linker_entry *table_loader;
 	struct bios_linker_entry *entry;
 	uint32_t size;
-	struct list_head *list;
 
 	/* make sure fw_list is loaded */
 	ret = qemu_fwcfg_read_firmware_list();
@@ -444,10 +208,14 @@ u32 write_acpi_tables(u32 addr)
 
 out:
 	if (ret) {
-		list_for_each(list, &fw_list) {
-			file = list_entry(list, struct fw_file, list);
-			if (file->addr)
+		struct fw_cfg_file_iter iter;
+		for (file = qemu_fwcfg_file_iter_init(&iter);
+		     !qemu_fwcfg_file_iter_end(&iter);
+		     file = qemu_fwcfg_file_iter_next(&iter)) {
+			if (file->addr) {
 				free((void *)file->addr);
+				file->addr = 0;
+			}
 		}
 	}
 
@@ -456,115 +224,163 @@ out:
 }
 #endif
 
-static int qemu_fwcfg_list_firmware(void)
+/* Read configuration item using fw_cfg PIO interface */
+static void qemu_fwcfg_read_entry_pio(uint16_t entry,
+		uint32_t size, void *address)
 {
-	int ret;
-	struct list_head *entry;
-	struct fw_file *file;
+	debug("qemu_fwcfg_read_entry_pio: entry 0x%x, size %u address %p\n",
+	      entry, size, address);
 
-	/* make sure fw_list is loaded */
-	ret = qemu_fwcfg_read_firmware_list();
-	if (ret)
-		return ret;
+	return fwcfg_arch_ops->arch_read_pio(entry, size, address);
+}
 
-	list_for_each(entry, &fw_list) {
-		file = list_entry(entry, struct fw_file, list);
-		printf("%-56s\n", file->cfg.name);
-	}
+/* Read configuration item using fw_cfg DMA interface */
+static void qemu_fwcfg_read_entry_dma(uint16_t entry,
+		uint32_t size, void *address)
+{
+	struct fw_cfg_dma_access dma;
 
-	return 0;
+	dma.length = cpu_to_be32(size);
+	dma.address = cpu_to_be64((uintptr_t)address);
+	dma.control = cpu_to_be32(FW_CFG_DMA_READ);
+
+	/*
+	 * writting FW_CFG_INVALID will cause read operation to resume at
+	 * last offset, otherwise read will start at offset 0
+	 */
+	if (entry != FW_CFG_INVALID)
+		dma.control |= cpu_to_be32(FW_CFG_DMA_SELECT | (entry << 16));
+
+	barrier();
+
+	debug("qemu_fwcfg_read_entry_dma: entry 0x%x, size %u address %p, control 0x%x\n",
+	      entry, size, address, be32_to_cpu(dma.control));
+
+	fwcfg_arch_ops->arch_read_dma(&dma);
 }
 
-void qemu_fwcfg_init(void)
+bool qemu_fwcfg_present(void)
 {
-	fwcfg_present = qemu_fwcfg_present();
-	if (fwcfg_present)
-		fwcfg_dma_present = qemu_fwcfg_dma_present();
+	return fwcfg_present;
 }
 
-static int qemu_fwcfg_do_list(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+bool qemu_fwcfg_dma_present(void)
 {
-	if (qemu_fwcfg_list_firmware() < 0)
-		return CMD_RET_FAILURE;
+	return fwcfg_dma_present;
+}
 
-	return 0;
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address)
+{
+	if (fwcfg_dma_present)
+		qemu_fwcfg_read_entry_dma(entry, length, address);
+	else
+		qemu_fwcfg_read_entry_pio(entry, length, address);
 }
 
-static int qemu_fwcfg_do_cpus(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+int qemu_fwcfg_online_cpus(void)
 {
-	int ret = qemu_fwcfg_online_cpus();
-	if (ret < 0) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_FAILURE;
-	}
+	uint16_t nb_cpus;
 
-	printf("%d cpu(s) online\n", qemu_fwcfg_online_cpus());
+	if (!fwcfg_present)
+		return -ENODEV;
 
-	return 0;
+	qemu_fwcfg_read_entry(FW_CFG_NB_CPUS, 2, &nb_cpus);
+
+	return le16_to_cpu(nb_cpus);
 }
 
-static int qemu_fwcfg_do_load(cmd_tbl_t *cmdtp, int flag,
-		int argc, char * const argv[])
+int qemu_fwcfg_read_firmware_list(void)
 {
-	char *env;
-	void *load_addr;
-	void *initrd_addr;
-
-	env = getenv("loadaddr");
-	load_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_LOADADDR;
-
-	env = getenv("ramdiskaddr");
-	initrd_addr = env ?
-		(void *)simple_strtoul(env, NULL, 16) :
-		(void *)CONFIG_RAMDISK_ADDR;
-
-	if (argc == 2) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
-		initrd_addr = (void *)simple_strtoul(argv[1], NULL, 16);
-	} else if (argc == 1) {
-		load_addr = (void *)simple_strtoul(argv[0], NULL, 16);
+	int i;
+	uint32_t count;
+	struct fw_file *file;
+	struct list_head *entry;
+
+	/* don't read it twice */
+	if (!list_empty(&fw_list))
+		return 0;
+
+	qemu_fwcfg_read_entry(FW_CFG_FILE_DIR, 4, &count);
+	if (!count)
+		return 0;
+
+	count = be32_to_cpu(count);
+	for (i = 0; i < count; i++) {
+		file = malloc(sizeof(*file));
+		if (!file) {
+			printf("error: allocating resource\n");
+			goto err;
+		}
+		qemu_fwcfg_read_entry(FW_CFG_INVALID,
+				      sizeof(struct fw_cfg_file), &file->cfg);
+		file->addr = 0;
+		list_add_tail(&file->list, &fw_list);
 	}
 
-	return qemu_fwcfg_setup_kernel(load_addr, initrd_addr);
-}
+	return 0;
 
-static cmd_tbl_t fwcfg_commands[] = {
-	U_BOOT_CMD_MKENT(list, 0, 1, qemu_fwcfg_do_list, "", ""),
-	U_BOOT_CMD_MKENT(cpus, 0, 1, qemu_fwcfg_do_cpus, "", ""),
-	U_BOOT_CMD_MKENT(load, 2, 1, qemu_fwcfg_do_load, "", ""),
-};
+err:
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		free(file);
+	}
+
+	return -ENOMEM;
+}
 
-static int do_qemu_fw(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+struct fw_file *qemu_fwcfg_find_file(const char *name)
 {
-	int ret;
-	cmd_tbl_t *fwcfg_cmd;
+	struct list_head *entry;
+	struct fw_file *file;
 
-	if (!fwcfg_present) {
-		printf("QEMU fw_cfg interface not found\n");
-		return CMD_RET_USAGE;
+	list_for_each(entry, &fw_list) {
+		file = list_entry(entry, struct fw_file, list);
+		if (!strcmp(file->cfg.name, name))
+			return file;
 	}
 
-	fwcfg_cmd = find_cmd_tbl(argv[1], fwcfg_commands,
-				 ARRAY_SIZE(fwcfg_commands));
-	argc -= 2;
-	argv += 2;
-	if (!fwcfg_cmd || argc > fwcfg_cmd->maxargs)
-		return CMD_RET_USAGE;
+	return NULL;
+}
 
-	ret = fwcfg_cmd->cmd(fwcfg_cmd, flag, argc, argv);
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = fw_list.next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
+
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter)
+{
+	iter->entry = ((struct list_head *)iter->entry)->next;
+	return list_entry((struct list_head *)iter->entry,
+			  struct fw_file, list);
+}
 
-	return cmd_process_error(fwcfg_cmd, ret);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter)
+{
+	return iter->entry == &fw_list;
 }
 
-U_BOOT_CMD(
-	qfw,	4,	1,	do_qemu_fw,
-	"QEMU firmware interface",
-	"<command>\n"
-	"    - list                             : print firmware(s) currently loaded\n"
-	"    - cpus                             : print online cpu number\n"
-	"    - load <kernel addr> <initrd addr> : load kernel and initrd (if any), and setup for zboot\n"
-)
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops)
+{
+	uint32_t qemu;
+	uint32_t dma_enabled;
+
+	fwcfg_present = false;
+	fwcfg_dma_present = false;
+	fwcfg_arch_ops = NULL;
+
+	if (!ops || !ops->arch_read_pio || !ops->arch_read_dma)
+		return;
+	fwcfg_arch_ops = ops;
+
+	qemu_fwcfg_read_entry_pio(FW_CFG_SIGNATURE, 4, &qemu);
+	if (be32_to_cpu(qemu) == QEMU_FW_CFG_SIGNATURE)
+		fwcfg_present = true;
+
+	if (fwcfg_present) {
+		qemu_fwcfg_read_entry_pio(FW_CFG_ID, 1, &dma_enabled);
+		if (dma_enabled & FW_CFG_DMA_ENABLED)
+			fwcfg_dma_present = true;
+	}
+}
diff --git a/drivers/misc/reset_sandbox.c b/drivers/misc/reset_sandbox.c
deleted file mode 100644
index 2691bb031a..0000000000
--- a/drivers/misc/reset_sandbox.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int sandbox_warm_reset_request(struct udevice *dev, enum reset_t type)
-{
-	struct sandbox_state *state = state_get_current();
-
-	switch (type) {
-	case RESET_WARM:
-		state->last_reset = type;
-		break;
-	default:
-		return -ENOSYS;
-	}
-	if (!state->reset_allowed[type])
-		return -EACCES;
-
-	return -EINPROGRESS;
-}
-
-static int sandbox_reset_request(struct udevice *dev, enum reset_t type)
-{
-	struct sandbox_state *state = state_get_current();
-
-	/*
-	 * If we have a device tree, the device we created from platform data
-	 * (see the U_BOOT_DEVICE() declaration below) should not do anything.
-	 * If we are that device, return an error.
-	 */
-	if (state->fdt_fname && dev->of_offset == -1)
-		return -ENODEV;
-
-	switch (type) {
-	case RESET_COLD:
-		state->last_reset = type;
-		break;
-	case RESET_POWER:
-		state->last_reset = type;
-		if (!state->reset_allowed[type])
-			return -EACCES;
-		sandbox_exit();
-		break;
-	default:
-		return -ENOSYS;
-	}
-	if (!state->reset_allowed[type])
-		return -EACCES;
-
-	return -EINPROGRESS;
-}
-
-static struct reset_ops sandbox_reset_ops = {
-	.request	= sandbox_reset_request,
-};
-
-static const struct udevice_id sandbox_reset_ids[] = {
-	{ .compatible = "sandbox,reset" },
-	{ }
-};
-
-U_BOOT_DRIVER(reset_sandbox) = {
-	.name		= "reset_sandbox",
-	.id		= UCLASS_RESET,
-	.of_match	= sandbox_reset_ids,
-	.ops		= &sandbox_reset_ops,
-};
-
-static struct reset_ops sandbox_warm_reset_ops = {
-	.request	= sandbox_warm_reset_request,
-};
-
-static const struct udevice_id sandbox_warm_reset_ids[] = {
-	{ .compatible = "sandbox,warm-reset" },
-	{ }
-};
-
-U_BOOT_DRIVER(warm_reset_sandbox) = {
-	.name		= "warm_reset_sandbox",
-	.id		= UCLASS_RESET,
-	.of_match	= sandbox_warm_reset_ids,
-	.ops		= &sandbox_warm_reset_ops,
-};
-
-/* This is here in case we don't have a device tree */
-U_BOOT_DEVICE(reset_sandbox_non_fdt) = {
-	.name = "reset_sandbox",
-};
diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/sysreset-uclass.c
index fdb5c6fcff..3566d17fb1 100644
--- a/drivers/misc/reset-uclass.c
+++ b/drivers/misc/sysreset-uclass.c
@@ -6,7 +6,7 @@
  */
 
 #include <common.h>
-#include <reset.h>
+#include <sysreset.h>
 #include <dm.h>
 #include <errno.h>
 #include <regmap.h>
@@ -15,9 +15,9 @@
 #include <dm/root.h>
 #include <linux/err.h>
 
-int reset_request(struct udevice *dev, enum reset_t type)
+int sysreset_request(struct udevice *dev, enum sysreset_t type)
 {
-	struct reset_ops *ops = reset_get_ops(dev);
+	struct sysreset_ops *ops = sysreset_get_ops(dev);
 
 	if (!ops->request)
 		return -ENOSYS;
@@ -25,16 +25,16 @@ int reset_request(struct udevice *dev, enum reset_t type)
 	return ops->request(dev, type);
 }
 
-int reset_walk(enum reset_t type)
+int sysreset_walk(enum sysreset_t type)
 {
 	struct udevice *dev;
 	int ret = -ENOSYS;
 
-	while (ret != -EINPROGRESS && type < RESET_COUNT) {
-		for (uclass_first_device(UCLASS_RESET, &dev);
+	while (ret != -EINPROGRESS && type < SYSRESET_COUNT) {
+		for (uclass_first_device(UCLASS_SYSRESET, &dev);
 		     dev;
 		     uclass_next_device(&dev)) {
-			ret = reset_request(dev, type);
+			ret = sysreset_request(dev, type);
 			if (ret == -EINPROGRESS)
 				break;
 		}
@@ -44,38 +44,38 @@ int reset_walk(enum reset_t type)
 	return ret;
 }
 
-void reset_walk_halt(enum reset_t type)
+void sysreset_walk_halt(enum sysreset_t type)
 {
 	int ret;
 
-	ret = reset_walk(type);
+	ret = sysreset_walk(type);
 
 	/* Wait for the reset to take effect */
 	if (ret == -EINPROGRESS)
 		mdelay(100);
 
 	/* Still no reset? Give up */
-	printf("Reset not supported on this platform\n");
+	debug("System reset not supported on this platform\n");
 	hang();
 }
 
 /**
- * reset_cpu() - calls reset_walk(RESET_WARM)
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
  */
 void reset_cpu(ulong addr)
 {
-	reset_walk_halt(RESET_WARM);
+	sysreset_walk_halt(SYSRESET_WARM);
 }
 
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
-	reset_walk_halt(RESET_WARM);
+	sysreset_walk_halt(SYSRESET_WARM);
 
 	return 0;
 }
 
-UCLASS_DRIVER(reset) = {
-	.id		= UCLASS_RESET,
-	.name		= "reset",
+UCLASS_DRIVER(sysreset) = {
+	.id		= UCLASS_SYSRESET,
+	.name		= "sysreset",
 };
diff --git a/drivers/misc/sysreset_sandbox.c b/drivers/misc/sysreset_sandbox.c
new file mode 100644
index 0000000000..7ae7f386ee
--- /dev/null
+++ b/drivers/misc/sysreset_sandbox.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_warm_sysreset_request(struct udevice *dev,
+					 enum sysreset_t type)
+{
+	struct sandbox_state *state = state_get_current();
+
+	switch (type) {
+	case SYSRESET_WARM:
+		state->last_sysreset = type;
+		break;
+	default:
+		return -ENOSYS;
+	}
+	if (!state->sysreset_allowed[type])
+		return -EACCES;
+
+	return -EINPROGRESS;
+}
+
+static int sandbox_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct sandbox_state *state = state_get_current();
+
+	/*
+	 * If we have a device tree, the device we created from platform data
+	 * (see the U_BOOT_DEVICE() declaration below) should not do anything.
+	 * If we are that device, return an error.
+	 */
+	if (state->fdt_fname && dev->of_offset == -1)
+		return -ENODEV;
+
+	switch (type) {
+	case SYSRESET_COLD:
+		state->last_sysreset = type;
+		break;
+	case SYSRESET_POWER:
+		state->last_sysreset = type;
+		if (!state->sysreset_allowed[type])
+			return -EACCES;
+		sandbox_exit();
+		break;
+	default:
+		return -ENOSYS;
+	}
+	if (!state->sysreset_allowed[type])
+		return -EACCES;
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops sandbox_sysreset_ops = {
+	.request	= sandbox_sysreset_request,
+};
+
+static const struct udevice_id sandbox_sysreset_ids[] = {
+	{ .compatible = "sandbox,reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_sandbox) = {
+	.name		= "sysreset_sandbox",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= sandbox_sysreset_ids,
+	.ops		= &sandbox_sysreset_ops,
+};
+
+static struct sysreset_ops sandbox_warm_sysreset_ops = {
+	.request	= sandbox_warm_sysreset_request,
+};
+
+static const struct udevice_id sandbox_warm_sysreset_ids[] = {
+	{ .compatible = "sandbox,warm-reset" },
+	{ }
+};
+
+U_BOOT_DRIVER(warm_sysreset_sandbox) = {
+	.name		= "warm_sysreset_sandbox",
+	.id		= UCLASS_SYSRESET,
+	.of_match	= sandbox_warm_sysreset_ids,
+	.ops		= &sandbox_warm_sysreset_ops,
+};
+
+/* This is here in case we don't have a device tree */
+U_BOOT_DEVICE(sysreset_sandbox_non_fdt) = {
+	.name = "sysreset_sandbox",
+};
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7329f40d34..74a2663c8b 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -454,27 +454,40 @@ static const struct mmc_ops dwmci_ops = {
 	.init		= dwmci_init,
 };
 
-int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		     uint caps, u32 max_clk, u32 min_clk)
 {
-	host->cfg.name = host->name;
-	host->cfg.ops = &dwmci_ops;
-	host->cfg.f_min = min_clk;
-	host->cfg.f_max = max_clk;
+	cfg->name = name;
+	cfg->ops = &dwmci_ops;
+	cfg->f_min = min_clk;
+	cfg->f_max = max_clk;
 
-	host->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 
-	host->cfg.host_caps = host->caps;
+	cfg->host_caps = caps;
 
-	if (host->buswidth == 8) {
-		host->cfg.host_caps |= MMC_MODE_8BIT;
-		host->cfg.host_caps &= ~MMC_MODE_4BIT;
+	if (buswidth == 8) {
+		cfg->host_caps |= MMC_MODE_8BIT;
+		cfg->host_caps &= ~MMC_MODE_4BIT;
 	} else {
-		host->cfg.host_caps |= MMC_MODE_4BIT;
-		host->cfg.host_caps &= ~MMC_MODE_8BIT;
+		cfg->host_caps |= MMC_MODE_4BIT;
+		cfg->host_caps &= ~MMC_MODE_8BIT;
 	}
-	host->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
+
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+}
 
-	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+#ifdef CONFIG_BLK
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
+{
+	return mmc_bind(dev, mmc, cfg);
+}
+#else
+int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
+{
+	dwmci_setup_cfg(&host->cfg, host->name, host->buswidth, host->caps,
+			max_clk, min_clk);
 
 	host->mmc = mmc_create(&host->cfg, host);
 	if (host->mmc == NULL)
@@ -482,3 +495,4 @@ int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
 
 	return 0;
 }
+#endif
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 3acf9e8820..57ad9754f5 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -308,14 +308,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
 	(struct mmc_cmd *cmd,
 	 struct mmc_data *data) {
-#ifdef CONFIG_FSL_LAYERSCAPE
 	unsigned start = 0;
-#else
-	unsigned start = (unsigned)data->dest ;
-#endif
+	unsigned end = 0;
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
-	unsigned end = start+size ;
 #ifdef CONFIG_FSL_LAYERSCAPE
 	dma_addr_t addr;
 
@@ -324,7 +320,10 @@ static void check_and_invalidate_dcache_range
 		printf("Error found for upper 32 bits\n");
 	else
 		start = lower_32_bits(addr);
+#else
+	start = (unsigned)data->dest;
 #endif
+	end = start + size;
 	invalidate_dcache_range(start, end);
 }
 
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 74b3d68f87..758655850b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -155,8 +155,6 @@ int mmc_send_status(struct mmc *mmc, int timeout)
 #endif
 		return TIMEOUT;
 	}
-	if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
-		return SWITCH_ERR;
 
 	return 0;
 }
@@ -516,7 +514,7 @@ static int mmc_change_freq(struct mmc *mmc)
 	err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
 
 	if (err)
-		return err == SWITCH_ERR ? 0 : err;
+		return err;
 
 	/* Now check to see that it worked */
 	err = mmc_send_ext_csd(mmc, ext_csd);
@@ -984,7 +982,7 @@ static const int fbase[] = {
 /* Multiplier values for TRAN_SPEED.  Multiplied by 10 to be nice
  * to platforms without floating point.
  */
-static const int multipliers[] = {
+static const u8 multipliers[] = {
 	0,	/* reserved */
 	10,
 	12,
@@ -1531,15 +1529,6 @@ static int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
-/* not used any more */
-int __deprecated mmc_register(struct mmc *mmc)
-{
-#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
-	printf("%s is deprecated! use mmc_create() instead.\n", __func__);
-#endif
-	return -1;
-}
-
 #ifdef CONFIG_BLK
 int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 {
@@ -1566,7 +1555,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
 	bdesc->removable = 1;
 
 	/* setup initial part type */
-	bdesc->part_type = mmc->cfg->part_type;
+	bdesc->part_type = cfg->part_type;
 	mmc->dev = dev;
 
 	return 0;
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index 27b9e5f56f..9f0d5c2384 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -37,6 +37,19 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
 
 /* SPL will never write or erase, declare dummies to reduce code size. */
 
+#ifdef CONFIG_BLK
+static inline unsigned long mmc_berase(struct udevice *dev,
+				       lbaint_t start, lbaint_t blkcnt)
+{
+	return 0;
+}
+
+static inline ulong mmc_bwrite(struct udevice *dev, lbaint_t start,
+			       lbaint_t blkcnt, const void *src)
+{
+	return 0;
+}
+#else
 static inline unsigned long mmc_berase(struct blk_desc *block_dev,
 				       lbaint_t start, lbaint_t blkcnt)
 {
@@ -48,6 +61,7 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start,
 {
 	return 0;
 }
+#endif
 
 #endif /* CONFIG_SPL_BUILD */
 
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index be34057ea2..d007b56293 100644
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -701,6 +701,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 		priv_data->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
 	defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) || \
+	defined(CONFIG_AM33XX) || \
 	defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
 		defined(CONFIG_HSMMC2_8BIT)
 		/* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 0a261c51a8..750ab9f8c5 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -18,6 +18,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct rockchip_mmc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
 struct rockchip_dwmmc_priv {
 	struct udevice *clk;
 	int periph;
@@ -62,6 +67,9 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
 
 static int rockchip_dwmmc_probe(struct udevice *dev)
 {
+#ifdef CONFIG_BLK
+	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+#endif
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
 	struct dwmci_host *host = &priv->host;
@@ -100,16 +108,37 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
 			return ret;
 	}
 #endif
+#ifdef CONFIG_BLK
+	dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps,
+			minmax[1], minmax[0]);
+	host->mmc = &plat->mmc;
+#else
 	ret = add_dwmci(host, minmax[1], minmax[0]);
 	if (ret)
 		return ret;
 
+#endif
+	host->mmc->priv = &priv->host;
 	host->mmc->dev = dev;
 	upriv->mmc = host->mmc;
 
 	return 0;
 }
 
+static int rockchip_dwmmc_bind(struct udevice *dev)
+{
+#ifdef CONFIG_BLK
+	struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
+	int ret;
+
+	ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
 static const struct udevice_id rockchip_dwmmc_ids[] = {
 	{ .compatible = "rockchip,rk3288-dw-mshc" },
 	{ }
@@ -120,8 +149,10 @@ U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
 	.id		= UCLASS_MMC,
 	.of_match	= rockchip_dwmmc_ids,
 	.ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
+	.bind		= rockchip_dwmmc_bind,
 	.probe		= rockchip_dwmmc_probe,
 	.priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
+	.platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
 };
 
 #ifdef CONFIG_PWRSEQ
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index ef7e6150f9..5c71ab8d05 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -137,7 +137,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 	int trans_bytes = 0, is_aligned = 1;
 	u32 mask, flags, mode;
 	unsigned int time = 0, start_addr = 0;
-	int mmc_dev = mmc->block_dev.devnum;
+	int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 	unsigned start = get_timer(0);
 
 	/* Timeout unit - ms */
diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c
index 573819a01e..c9d9432e5e 100644
--- a/drivers/mmc/tegra_mmc.c
+++ b/drivers/mmc/tegra_mmc.c
@@ -11,8 +11,10 @@
 #include <common.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#ifndef CONFIG_TEGRA186
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/clk_rst.h>
+#endif
 #include <asm/arch-tegra/mmc.h>
 #include <asm/arch-tegra/tegra_mmc.h>
 #include <mmc.h>
@@ -357,8 +359,12 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
 	 */
 	if (clock == 0)
 		goto out;
+#ifndef CONFIG_TEGRA186
 	clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
 				    &div);
+#else
+	div = (20000000 + clock - 1) / clock;
+#endif
 	debug("div = %d\n", div);
 
 	writew(0, &host->reg->clkcon);
@@ -543,7 +549,9 @@ static int do_mmc_init(int dev_index, bool removable)
 	      gpio_get_number(&host->cd_gpio));
 
 	host->clock = 0;
+#ifndef CONFIG_TEGRA186
 	clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
+#endif
 
 	if (dm_gpio_is_valid(&host->pwr_gpio))
 		dm_gpio_set_value(&host->pwr_gpio, 1);
@@ -568,7 +576,11 @@ static int do_mmc_init(int dev_index, bool removable)
 	 *  (actually 52MHz)
 	 */
 	host->cfg.f_min = 375000;
+#ifndef CONFIG_TEGRA186
 	host->cfg.f_max = 48000000;
+#else
+	host->cfg.f_max = 375000;
+#endif
 
 	host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
@@ -600,11 +612,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 		return -FDT_ERR_NOTFOUND;
 	}
 
+#ifndef CONFIG_TEGRA186
 	host->mmc_id = clock_decode_periph_id(blob, node);
 	if (host->mmc_id == PERIPH_ID_NONE) {
 		debug("%s: could not decode periph id\n", __func__);
 		return -FDT_ERR_NOTFOUND;
 	}
+#endif
 
 	/*
 	 * NOTE: mmc->bus_width is determined by mmc.c dynamically.
@@ -624,7 +638,13 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host,
 	*removablep = !fdtdec_get_bool(blob, node, "non-removable");
 
 	debug("%s: found controller at %p, width = %d, periph_id = %d\n",
-		__func__, host->reg, host->width, host->mmc_id);
+		__func__, host->reg, host->width,
+#ifndef CONFIG_TEGRA186
+		host->mmc_id
+#else
+		-1
+#endif
+	);
 	return 0;
 }
 
@@ -668,6 +688,16 @@ void tegra_mmc_init(void)
 	const void *blob = gd->fdt_blob;
 	debug("%s entry\n", __func__);
 
+	/* See if any Tegra186 MMC controllers are present */
+	count = fdtdec_find_aliases_for_id(blob, "sdhci",
+		COMPAT_NVIDIA_TEGRA186_SDMMC, node_list,
+		CONFIG_SYS_MMC_MAX_DEVICE);
+	debug("%s: count of Tegra186 sdhci nodes is %d\n", __func__, count);
+	if (process_nodes(blob, node_list, count)) {
+		printf("%s: Error processing T186 mmc node(s)!\n", __func__);
+		return;
+	}
+
 	/* See if any Tegra210 MMC controllers are present */
 	count = fdtdec_find_aliases_for_id(blob, "sdhci",
 		COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 6fb37182d5..837d397bda 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -13,7 +13,6 @@ endif
 
 obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
 obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
-obj-$(CONFIG_SPL_NAND_DOCG4) += docg4_spl.o
 obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
 obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
 obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
@@ -50,7 +49,6 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
-obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
@@ -68,7 +66,6 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
 obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
 obj-$(CONFIG_NAND_PLAT) += nand_plat.o
-obj-$(CONFIG_NAND_DOCG4) += docg4.o
 
 else  # minimal SPL drivers
 
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c
index bf8b2ee16a..f8770e0ad8 100644
--- a/drivers/mtd/nand/am335x_spl_bch.c
+++ b/drivers/mtd/nand/am335x_spl_bch.c
@@ -16,7 +16,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-nand_info_t nand_info[1];
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -30,12 +30,12 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&nand_info[0]))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Emulate NAND_CMD_READOOB */
@@ -45,11 +45,11 @@ static int nand_command(int block, int page, uint32_t offs,
 	}
 
 	/* Begin command latch cycle */
-	hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_RESET) {
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-		while (!this->dev_ready(&nand_info[0]))
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		while (!this->dev_ready(mtd))
 			;
 		return 0;
 	}
@@ -60,39 +60,39 @@ static int nand_command(int block, int page, uint32_t offs,
 
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	hwctrl(&nand_info[0], offs & 0xff,
+	hwctrl(mtd, offs & 0xff,
 		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-	hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
 	if (cmd != NAND_CMD_RNDOUT) {
-		hwctrl(&nand_info[0], (page_addr & 0xff),
+		hwctrl(mtd, (page_addr & 0xff),
 		       NAND_CTRL_ALE); /* A[19:12] */
-		hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff),
+		hwctrl(mtd, ((page_addr >> 8) & 0xff),
 		       NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 		/* One more address cycle for devices > 128MiB */
-		hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f,
+		hwctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
 	}
 
-	hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	if (cmd == NAND_CMD_READ0) {
 		/* Latch in address */
-		hwctrl(&nand_info[0], NAND_CMD_READSTART,
+		hwctrl(mtd, NAND_CMD_READSTART,
 			   NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 		/*
 		 * Wait a while for the data to be ready
 		 */
-		while (!this->dev_ready(&nand_info[0]))
+		while (!this->dev_ready(mtd))
 			;
 	} else if (cmd == NAND_CMD_RNDOUT) {
-		hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
+		hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
 					NAND_CTRL_CHANGE);
-		hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+		hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 	}
 
 	return 0;
@@ -100,7 +100,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
 		NAND_CMD_READOOB);
@@ -121,7 +121,7 @@ static int nand_is_bad_block(int block)
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = nand_info[0].priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -137,15 +137,15 @@ static int nand_read_page(int block, int page, void *dst)
 	nand_command(block, page, 0, NAND_CMD_READ0);
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		this->ecc.hwctl(&nand_info[0], NAND_ECC_READ);
+		this->ecc.hwctl(mtd, NAND_ECC_READ);
 		nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
 
-		this->read_buf(&nand_info[0], p, eccsize);
+		this->read_buf(mtd, p, eccsize);
 
 		nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
 
-		this->read_buf(&nand_info[0], oob, eccbytes);
-		this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]);
+		this->read_buf(mtd, oob, eccbytes);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		data_pos += eccsize;
 		oob_pos += eccbytes;
@@ -164,7 +164,7 @@ static int nand_read_page(int block, int page, void *dst)
 		 * from correct_data(). We just hope that all possible errors
 		 * are corrected by this routine.
 		 */
-		this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -173,7 +173,7 @@ static int nand_read_page(int block, int page, void *dst)
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 {
 	unsigned int block, lastblock;
-	unsigned int page;
+	unsigned int page, page_offset;
 
 	/*
 	 * offs has to be aligned to a page address!
@@ -181,6 +181,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 	block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
 	lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
 	page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
+	page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
 
 	while (block <= lastblock) {
 		if (!nand_is_bad_block(block)) {
@@ -189,6 +190,18 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 			 */
 			while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
 				nand_read_page(block, page, dst);
+				/*
+				 * When offs is not aligned to page address the
+				 * extra offset is copied to dst as well. Copy
+				 * the image such that its first byte will be
+				 * at the dst.
+				 */
+				if (unlikely(page_offset)) {
+					memmove(dst, dst + page_offset,
+						CONFIG_SYS_NAND_PAGE_SIZE);
+					dst = (void *)((int)dst - page_offset);
+					page_offset = 0;
+				}
 				dst += CONFIG_SYS_NAND_PAGE_SIZE;
 				page++;
 			}
@@ -210,13 +223,13 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	nand_info[0].priv = &nand_chip;
+	mtd = &nand_chip.mtd;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&nand_info[0], 0);
+		nand_chip.select_chip(mtd, 0);
 
 	/* NAND chip may require reset after power-on */
 	nand_command(0, 0, 0, NAND_CMD_RESET);
@@ -226,5 +239,5 @@ void nand_init(void)
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&nand_info[0], -1);
+		nand_chip.select_chip(mtd, -1);
 }
diff --git a/drivers/mtd/nand/arasan_nfc.c b/drivers/mtd/nand/arasan_nfc.c
index 2d73a05e75..320cbaa859 100644
--- a/drivers/mtd/nand/arasan_nfc.c
+++ b/drivers/mtd/nand/arasan_nfc.c
@@ -230,7 +230,7 @@ static void arasan_nand_enable_ecc(void)
 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 {
 	u8 addrcycles;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	switch (curr_cmd->addr_cycles) {
 	case NAND_ADDR_CYCL_NONE:
@@ -264,7 +264,7 @@ static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
 
 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 reg_val, i, pktsize, pktnum;
 	u32 *bufptr = (u32 *)buf;
 	u32 timeout;
@@ -433,7 +433,8 @@ static void arasan_nand_fill_tx(const u8 *buf, int len)
 }
 
 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, const u8 *buf, int oob_required)
+		struct nand_chip *chip, const u8 *buf, int oob_required,
+		int page)
 {
 	u32 reg_val, i, pktsize, pktnum;
 	const u32 *bufptr = (const u32 *)buf;
@@ -441,7 +442,7 @@ static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
 	u32 size = mtd->writesize;
 	u32 rdcount = 0;
 	u8 column_addr_cycles;
-	struct arasan_nand_info *nand = chip->priv;
+	struct arasan_nand_info *nand = nand_get_controller_data(chip);
 
 	if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
 		pktsize = ARASAN_NAND_PKTSIZE_1K;
@@ -944,7 +945,7 @@ static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
 
 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 size;
 	u8 val;
 	struct nand_onfi_params *p;
@@ -976,8 +977,8 @@ static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
 				     int column, int page_addr)
 {
 	u32 i, ret = 0;
-	struct nand_chip *chip = mtd->priv;
-	struct arasan_nand_info *nand = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct arasan_nand_info *nand = nand_get_controller_data(chip);
 
 	curr_cmd = NULL;
 	writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
@@ -1033,7 +1034,7 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 {
 	int found = -1;
 	u32 regval, eccpos_start, i;
-	struct nand_chip *nand_chip = mtd->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 
 	nand_chip->ecc.mode = NAND_ECC_HW;
 	nand_chip->ecc.hwctl = NULL;
@@ -1058,20 +1059,20 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	if (found < 0)
 		return 1;
 
-	regval = ecc_matrix[i].eccaddr |
-		 (ecc_matrix[i].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
-		 (ecc_matrix[i].bch << ARASAN_NAND_ECC_BCH_SHIFT);
+	regval = ecc_matrix[found].eccaddr |
+		 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
+		 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
 	writel(regval, &arasan_nand_base->ecc_reg);
 
-	if (ecc_matrix[i].bch) {
+	if (ecc_matrix[found].bch) {
 		regval = readl(&arasan_nand_base->memadr_reg2);
 		regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
-		regval |= (ecc_matrix[i].bchval <<
+		regval |= (ecc_matrix[found].bchval <<
 			   ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
 		writel(regval, &arasan_nand_base->memadr_reg2);
 	}
 
-	nand_oob.eccbytes = ecc_matrix[i].eccsize;
+	nand_oob.eccbytes = ecc_matrix[found].eccsize;
 	eccpos_start = mtd->oobsize - nand_oob.eccbytes;
 
 	for (i = 0; i < nand_oob.eccbytes; i++)
@@ -1080,9 +1081,9 @@ static int arasan_nand_ecc_init(struct mtd_info *mtd)
 	nand_oob.oobfree[0].offset = 2;
 	nand_oob.oobfree[0].length = eccpos_start - 2;
 
-	nand_chip->ecc.size = ecc_matrix[i].ecc_codeword_size;
-	nand_chip->ecc.strength = ecc_matrix[i].eccbits;
-	nand_chip->ecc.bytes = ecc_matrix[i].eccsize;
+	nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
+	nand_chip->ecc.strength = ecc_matrix[found].eccbits;
+	nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
 	nand_chip->ecc.layout = &nand_oob;
 
 	return 0;
@@ -1101,9 +1102,8 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 	}
 
 	nand->nand_base = arasan_nand_base;
-	mtd = &nand_info[0];
-	nand_chip->priv = nand;
-	mtd->priv = nand_chip;
+	mtd = nand_to_mtd(nand_chip);
+	nand_set_controller_data(nand_chip, nand);
 
 	/* Set the driver entry points for MTD */
 	nand_chip->cmdfunc = arasan_nand_cmd_function;
@@ -1134,7 +1134,7 @@ static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
 		goto fail;
 	}
 
-	if (nand_register(devnum)) {
+	if (nand_register(devnum, mtd)) {
 		printf("Nand Register Fail\n");
 		goto fail;
 	}
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 7cc1de0313..75e830724c 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -160,8 +160,8 @@ static int pmecc_data_alloc(struct atmel_nand_host *host)
 
 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i;
 	uint32_t value;
 
@@ -177,8 +177,8 @@ static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
 
 static void pmecc_substitute(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int16_t __iomem *alpha_to = host->pmecc_alpha_to;
 	int16_t __iomem *index_of = host->pmecc_index_of;
 	int16_t *partial_syn = host->pmecc_partial_syn;
@@ -227,8 +227,8 @@ static void pmecc_substitute(struct mtd_info *mtd)
  */
 static void pmecc_get_sigma(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 
 	int16_t *lmu = host->pmecc_lmu;
 	int16_t *si = host->pmecc_si;
@@ -383,8 +383,8 @@ static void pmecc_get_sigma(struct mtd_info *mtd)
 
 static int pmecc_err_location(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	const int cap = host->pmecc_corr_cap;
 	const int num = 2 * cap + 1;
 	int sector_size = host->pmecc_sector_size;
@@ -437,8 +437,8 @@ static int pmecc_err_location(struct mtd_info *mtd)
 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 		int sector_num, int extra_bytes, int err_nbr)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i = 0;
 	int byte_pos, bit_pos, sector_size, pos;
 	uint32_t tmp;
@@ -483,8 +483,8 @@ static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
 	u8 *ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	int i, err_nbr, eccbytes;
 	uint8_t *buf_pos;
 
@@ -513,7 +513,7 @@ normal_check:
 			if (err_nbr == -1) {
 				dev_err(host->dev, "PMECC: Too many errors\n");
 				mtd->ecc_stats.failed++;
-				return -EIO;
+				return -EBADMSG;
 			} else {
 				pmecc_correct_data(mtd, buf_pos, ecc, i,
 					host->pmecc_bytes_per_sector, err_nbr);
@@ -529,7 +529,7 @@ normal_check:
 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
 {
-	struct atmel_nand_host *host = chip->priv;
+	struct atmel_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	uint8_t *oob = chip->oob_poi;
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
@@ -562,16 +562,16 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 	stat = pmecc_readl(host->pmecc, isr);
 	if (stat != 0)
 		if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
-			return -EIO;
+			return -EBADMSG;
 
 	return 0;
 }
 
 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 		struct nand_chip *chip, const uint8_t *buf,
-		int oob_required)
+		int oob_required, int page)
 {
-	struct atmel_nand_host *host = chip->priv;
+	struct atmel_nand_host *host = nand_get_controller_data(chip);
 	uint32_t *eccpos = chip->ecc.layout->eccpos;
 	int i, j;
 	int timeout = PMECC_MAX_TIMEOUT_US;
@@ -615,8 +615,8 @@ out:
 
 static void atmel_pmecc_core_init(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct atmel_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
 	uint32_t val = 0;
 	struct nand_ecclayout *ecc_layout;
 
@@ -808,7 +808,8 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
 	struct atmel_nand_host *host;
 	int cap, sector_size;
 
-	host = nand->priv = &pmecc_host;
+	host = &pmecc_host;
+	nand_set_controller_data(nand, host);
 
 	nand->ecc.mode = NAND_ECC_HW;
 	nand->ecc.calculate = NULL;
@@ -1080,7 +1081,7 @@ static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		u_char *read_ecc, u_char *isnull)
 {
-	struct nand_chip *nand_chip = mtd->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
 	unsigned int ecc_status;
 	unsigned int ecc_word, ecc_bit;
 
@@ -1111,7 +1112,7 @@ static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
 		 * We can't correct so many errors */
 		dev_warn(host->dev, "atmel_nand : multiple errors detected."
 				" Unable to correct.\n");
-		return -EIO;
+		return -EBADMSG;
 	}
 
 	/* if there's a single bit error : we can correct it */
@@ -1207,7 +1208,7 @@ int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
 static void at91_nand_hwcontrol(struct mtd_info *mtd,
 					 int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
@@ -1238,17 +1239,17 @@ static int at91_nand_ready(struct mtd_info *mtd)
 
 #ifdef CONFIG_SPL_BUILD
 /* The following code is for SPL */
-static nand_info_t mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	if (cmd == NAND_CMD_READOOB) {
@@ -1256,24 +1257,24 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 		cmd = NAND_CMD_READ0;
 	}
 
-	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
 	if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
 		offs >>= 1;
 
-	hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
+	hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
+	hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
+	hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
 #endif
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -1281,7 +1282,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd)
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
 
@@ -1304,7 +1305,7 @@ static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
 
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -1317,11 +1318,11 @@ static int nand_read_page(int block, int page, void *dst)
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		if (this->ecc.mode != NAND_ECC_SOFT)
-			this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+			this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 	}
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 
 	for (i = 0; i < ECCTOTAL; i++)
 		ecc_code[i] = oob_data[nand_ecc_pos[i]];
@@ -1330,35 +1331,35 @@ static int nand_read_page(int block, int page, void *dst)
 	p = dst;
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 
 	return 0;
 }
 
 int spl_nand_erase_one(int block, int page)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 	int page_addr;
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 
 	page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
-	hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, ((page_addr >> 8) & 0xff),
 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	hwctrl(mtd, (page_addr >> 16) & 0x0f,
 	       NAND_CTRL_ALE | NAND_CTRL_CHANGE);
 #endif
-	hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	nand_deselect();
@@ -1368,10 +1369,10 @@ int spl_nand_erase_one(int block, int page)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	nand_command(block, page, 0, NAND_CMD_READ0);
-	atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
+	atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
 
 	return 0;
 }
@@ -1407,7 +1408,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
 
 int at91_nand_wait_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	udelay(this->chip_delay);
 
@@ -1438,7 +1439,7 @@ int board_nand_init(struct nand_chip *nand)
 
 #ifdef CONFIG_ATMEL_NAND_HWECC
 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
-	ret = atmel_pmecc_nand_init_params(nand, &mtd);
+	ret = atmel_pmecc_nand_init_params(nand, mtd);
 #endif
 #endif
 
@@ -1447,9 +1448,9 @@ int board_nand_init(struct nand_chip *nand)
 
 void nand_init(void)
 {
-	mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
-	mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
+	mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
+	mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
 	nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
@@ -1462,13 +1463,13 @@ void nand_init(void)
 #endif
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 }
 
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, -1);
+		nand_chip.select_chip(mtd, -1);
 }
 
 #else
@@ -1482,10 +1483,9 @@ static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
 int atmel_nand_chip_init(int devnum, ulong base_addr)
 {
 	int ret;
-	struct mtd_info *mtd = &nand_info[devnum];
 	struct nand_chip *nand = &nand_chip[devnum];
+	struct mtd_info *mtd = nand_to_mtd(nand);
 
-	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
 
 #ifdef CONFIG_NAND_ECC_BCH
@@ -1521,7 +1521,7 @@ int atmel_nand_chip_init(int devnum, ulong base_addr)
 
 	ret = nand_scan_tail(mtd);
 	if (!ret)
-		nand_register(devnum);
+		nand_register(devnum, mtd);
 
 	return ret;
 }
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index a3970745c9..48a8ca78e7 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -54,7 +54,7 @@
  */
 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	const u32 *nand = chip->IO_ADDR_R;
 
 	/* Make sure that buf is 32 bit aligned */
@@ -99,7 +99,7 @@ static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 				   int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	const u32 *nand = chip->IO_ADDR_W;
 
 	/* Make sure that buf is 32 bit aligned */
@@ -144,7 +144,7 @@ static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
 		unsigned int ctrl)
 {
-	struct		nand_chip *this = mtd->priv;
+	struct		nand_chip *this = mtd_to_nand(mtd);
 	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
@@ -223,7 +223,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 		u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
 					  (read_ecc[2] << 16);
 	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
@@ -243,7 +243,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 					 "%d\n", find_byte, find_bit);
 				return 1;
 			} else {
-				return -1;
+				return -EBADMSG;
 			}
 		} else if (!(diff & (diff - 1))) {
 			/* Single bit ECC error in the ECC itself,
@@ -254,7 +254,7 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
 		} else {
 			/* Uncorrectable error */
 			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
-			return -1;
+			return -EBADMSG;
 		}
 	}
 	return 0;
@@ -380,10 +380,13 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 	chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 
-	if (unlikely(raw))
-		status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
-	else
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+	if (unlikely(raw)) {
+		status = chip->ecc.write_page_raw(mtd, chip, buf,
+						  oob_required, page);
+	} else {
+		status = chip->ecc.write_page(mtd, chip, buf,
+					      oob_required, page);
+	}
 
 	if (status < 0) {
 		ret = status;
@@ -698,7 +701,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		return 0;
 	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
 		val = __raw_readl(&davinci_emif_regs->nanderrval1);
-		return -1;
+		return -EBADMSG;
 	}
 
 	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 5894fcc4a8..601e744a08 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -48,7 +48,10 @@ static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
  * this macro allows us to convert from an MTD structure to our own
  * device context (denali) structure.
  */
-#define mtd_to_denali(m) container_of(m->priv, struct denali_nand_info, nand)
+static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
+{
+	return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
+}
 
 /*
  * These constants are defined by the driver to enable common driver
@@ -865,7 +868,7 @@ static int write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * by write_page above.
  */
 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required, int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -889,7 +892,8 @@ static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  * write_page() function above.
  */
 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-					const uint8_t *buf, int oob_required)
+				 const uint8_t *buf, int oob_required,
+				 int page)
 {
 	struct denali_nand_info *denali = mtd_to_denali(mtd);
 
@@ -988,7 +992,7 @@ static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 			debug("  ECC error cause by erased block\n");
 			/* false alarm, return the 0xFF */
 		} else {
-			return -EIO;
+			return -EBADMSG;
 		}
 	}
 	memcpy(buf, denali->buf.dma_buf, mtd->writesize);
@@ -1173,13 +1177,13 @@ static struct nand_ecclayout nand_oob;
 
 static int denali_init(struct denali_nand_info *denali)
 {
+	struct mtd_info *mtd = nand_to_mtd(&denali->nand);
 	int ret;
 
 	denali_hw_init(denali);
 
-	denali->mtd->name = "denali-nand";
-	denali->mtd->owner = THIS_MODULE;
-	denali->mtd->priv = &denali->nand;
+	mtd->name = "denali-nand";
+	mtd->owner = THIS_MODULE;
 
 	/* register the driver with the NAND core subsystem */
 	denali->nand.select_chip = denali_select_chip;
@@ -1193,7 +1197,7 @@ static int denali_init(struct denali_nand_info *denali)
 	 * this is the first stage in a two step process to register
 	 * with the nand subsystem
 	 */
-	if (nand_scan_ident(denali->mtd, denali->max_banks, NULL)) {
+	if (nand_scan_ident(mtd, denali->max_banks, NULL)) {
 		ret = -ENXIO;
 		goto fail;
 	}
@@ -1239,13 +1243,13 @@ static int denali_init(struct denali_nand_info *denali)
 	nand_oob.eccbytes = denali->nand.ecc.bytes;
 	denali->nand.ecc.layout = &nand_oob;
 
-	writel(denali->mtd->erasesize / denali->mtd->writesize,
+	writel(mtd->erasesize / mtd->writesize,
 	       denali->flash_reg + PAGES_PER_BLOCK);
 	writel(denali->nand.options & NAND_BUSWIDTH_16 ? 1 : 0,
 	       denali->flash_reg + DEVICE_WIDTH);
-	writel(denali->mtd->writesize,
+	writel(mtd->writesize,
 	       denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
-	writel(denali->mtd->oobsize,
+	writel(mtd->oobsize,
 	       denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
 	if (readl(denali->flash_reg + DEVICES_CONNECTED) == 0)
 		writel(1, denali->flash_reg + DEVICES_CONNECTED);
@@ -1258,12 +1262,12 @@ static int denali_init(struct denali_nand_info *denali)
 	denali->nand.ecc.read_oob = denali_read_oob;
 	denali->nand.ecc.write_oob = denali_write_oob;
 
-	if (nand_scan_tail(denali->mtd)) {
+	if (nand_scan_tail(mtd)) {
 		ret = -ENXIO;
 		goto fail;
 	}
 
-	ret = nand_register(0);
+	ret = nand_register(0, mtd);
 
 fail:
 	return ret;
@@ -1278,13 +1282,6 @@ static int __board_nand_init(void)
 		return -ENOMEM;
 
 	/*
-	 * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
-	 * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
-	 * still provides a "struct mtd_info nand_info" instance.
-	 */
-	denali->mtd = &nand_info[0];
-
-	/*
 	 * In the future, these base addresses should be taken from
 	 * Device Tree or platform data.
 	 */
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index db1457a680..0e098bddf1 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -436,7 +436,6 @@ struct nand_buf {
 #define DT		3
 
 struct denali_nand_info {
-	struct mtd_info *mtd;
 	struct nand_chip nand;
 	int flash_bank; /* currently selected chip */
 	int status;
diff --git a/drivers/mtd/nand/denali_spl.c b/drivers/mtd/nand/denali_spl.c
index 1587413540..c693032530 100644
--- a/drivers/mtd/nand/denali_spl.c
+++ b/drivers/mtd/nand/denali_spl.c
@@ -41,7 +41,7 @@ static int wait_for_irq(uint32_t irq_mask)
 
 		if (intr_status & INTR_STATUS__ECC_UNCOR_ERR) {
 			debug("Uncorrected ECC detected\n");
-			return -EIO;
+			return -EBADMSG;
 		}
 
 		if (intr_status & irq_mask)
diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
deleted file mode 100644
index c1c1ff876a..0000000000
--- a/drivers/mtd/nand/docg4.c
+++ /dev/null
@@ -1,1030 +0,0 @@
-/*
- * drivers/mtd/nand/docg4.c
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * mtd nand driver for M-Systems DiskOnChip G4
- *
- * Tested on the Palm Treo 680.  The G4 is also present on Toshiba Portege, Asus
- * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
- * Should work on these as well.  Let me know!
- *
- * TODO:
- *
- *  Mechanism for management of password-protected areas
- *
- *  Hamming ecc when reading oob only
- *
- *  According to the M-Sys documentation, this device is also available in a
- *  "dual-die" configuration having a 256MB capacity, but no mechanism for
- *  detecting this variant is documented.  Currently this driver assumes 128MB
- *  capacity.
- *
- *  Support for multiple cascaded devices ("floors").  Not sure which gadgets
- *  contain multiple G4s in a cascaded configuration, if any.
- */
-
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <asm/bitops.h>
-#include <asm/errno.h>
-#include <malloc.h>
-#include <nand.h>
-#include <linux/bch.h>
-#include <linux/bitrev.h>
-#include <linux/mtd/docg4.h>
-
-/*
- * The device has a nop register which M-Sys claims is for the purpose of
- * inserting precise delays.  But beware; at least some operations fail if the
- * nop writes are replaced with a generic delay!
- */
-static inline void write_nop(void __iomem *docptr)
-{
-	writew(0, docptr + DOC_NOP);
-}
-
-
-static int poll_status(void __iomem *docptr)
-{
-	/*
-	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
-	 * register.  Operations known to take a long time (e.g., block erase)
-	 * should sleep for a while before calling this.
-	 */
-
-	uint8_t flash_status;
-
-	/* hardware quirk requires reading twice initially */
-	flash_status = readb(docptr + DOC_FLASHCONTROL);
-
-	do {
-		flash_status = readb(docptr + DOC_FLASHCONTROL);
-	} while (!(flash_status & DOC_CTRL_FLASHREADY));
-
-	return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* write the four address bytes packed in docg4_addr to the device */
-
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-/*
- * This is a module parameter in the linux kernel version of this driver.  It is
- * hard-coded to 'off' for u-boot.  This driver uses oob to mark bad blocks.
- * This can be problematic when dealing with data not intended for the mtd/nand
- * subsystem.  For example, on boards that boot from the docg4 and use the IPL
- * to load an spl + u-boot image, the blocks containing the image will be
- * reported as "bad" because the oob of the first page of each block contains a
- * magic number that the IPL looks for, which causes the badblock scan to
- * erroneously add them to the bad block table.  To erase such a block, use
- * u-boot's 'nand scrub'.  scrub is safe for the docg4.  The device does have a
- * factory bad block table, but it is read-only, and is used in conjunction with
- * oob bad block markers that are written by mtd/nand when a block is deemed to
- * be bad.  To read data from "bad" blocks, use 'read.raw'.  Unfortunately,
- * read.raw does not use ecc, which would still work fine on such misidentified
- * bad blocks.  TODO: u-boot nand utilities need the ability to ignore bad
- * blocks.
- */
-static const int ignore_badblocks; /* remains false */
-
-struct docg4_priv {
-	int status;
-	struct {
-		unsigned int command;
-		int column;
-		int page;
-	} last_command;
-	uint8_t oob_buf[16];
-	uint8_t ecc_buf[7];
-	int oob_page;
-	struct bch_control *bch;
-};
-/*
- * Oob bytes 0 - 6 are available to the user.
- * Byte 7 is hamming ecc for first 7 bytes.  Bytes 8 - 14 are hw-generated ecc.
- * Byte 15 (the last) is used by the driver as a "page written" flag.
- */
-static struct nand_ecclayout docg4_oobinfo = {
-	.eccbytes = 9,
-	.eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
-	.oobavail = 7,
-	.oobfree = { {0, 7} }
-};
-
-static void reset(void __iomem *docptr)
-{
-	/* full device reset */
-
-	writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN, docptr + DOC_ASICMODE);
-	writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
-	       docptr + DOC_ASICMODECONFIRM);
-	write_nop(docptr);
-
-	writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
-	       docptr + DOC_ASICMODE);
-	writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
-	       docptr + DOC_ASICMODECONFIRM);
-
-	writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
-
-	poll_status(docptr);
-}
-
-static void docg4_select_chip(struct mtd_info *mtd, int chip)
-{
-	/*
-	 * Select among multiple cascaded chips ("floors").  Multiple floors are
-	 * not yet supported, so the only valid non-negative value is 0.
-	 */
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-
-	if (chip < 0)
-		return;		/* deselected */
-
-	if (chip > 0)
-		printf("multiple floors currently unsupported\n");
-
-	writew(0, docptr + DOC_DEVICESELECT);
-}
-
-static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
-{
-	/* read the 7 hw-generated ecc bytes */
-
-	int i;
-	for (i = 0; i < 7; i++) { /* hw quirk; read twice */
-		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-		ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
-	}
-}
-
-static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
-{
-	/*
-	 * Called after a page read when hardware reports bitflips.
-	 * Up to four bitflips can be corrected.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	int i, numerrs;
-	unsigned int errpos[4];
-	const uint8_t blank_read_hwecc[8] = {
-		0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
-
-	read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
-
-	/* check if read error is due to a blank page */
-	if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
-		return 0;	/* yes */
-
-	/* skip additional check of "written flag" if ignore_badblocks */
-	if (!ignore_badblocks) {
-		/*
-		 * If the hw ecc bytes are not those of a blank page, there's
-		 * still a chance that the page is blank, but was read with
-		 * errors.  Check the "written flag" in last oob byte, which
-		 * is set to zero when a page is written.  If more than half
-		 * the bits are set, assume a blank page.  Unfortunately, the
-		 * bit flips(s) are not reported in stats.
-		 */
-
-		if (doc->oob_buf[15]) {
-			int bit, numsetbits = 0;
-			unsigned long written_flag = doc->oob_buf[15];
-
-			for (bit = 0; bit < 8; bit++) {
-				if (written_flag & 0x01)
-					numsetbits++;
-				written_flag >>= 1;
-			}
-			if (numsetbits > 4) { /* assume blank */
-				printf("errors in blank page at offset %08x\n",
-				       page * DOCG4_PAGE_SIZE);
-				return 0;
-			}
-		}
-	}
-
-	/*
-	 * The hardware ecc unit produces oob_ecc ^ calc_ecc.  The kernel's bch
-	 * algorithm is used to decode this.  However the hw operates on page
-	 * data in a bit order that is the reverse of that of the bch alg,
-	 * requiring that the bits be reversed on the result.  Thanks to Ivan
-	 * Djelic for his analysis!
-	 */
-	for (i = 0; i < 7; i++)
-		doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
-
-	numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
-			     doc->ecc_buf, NULL, errpos);
-
-	if (numerrs == -EBADMSG) {
-		printf("uncorrectable errors at offset %08x\n",
-		       page * DOCG4_PAGE_SIZE);
-		return -EBADMSG;
-	}
-
-	BUG_ON(numerrs < 0);	/* -EINVAL, or anything other than -EBADMSG */
-
-	/* undo last step in BCH alg (modulo mirroring not needed) */
-	for (i = 0; i < numerrs; i++)
-		errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
-
-	/* fix the errors */
-	for (i = 0; i < numerrs; i++) {
-		/* ignore if error within oob ecc bytes */
-		if (errpos[i] > DOCG4_USERDATA_LEN * 8)
-			continue;
-
-		/* if error within oob area preceeding ecc bytes... */
-		if (errpos[i] > DOCG4_PAGE_SIZE * 8)
-			__change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
-				     (unsigned long *)doc->oob_buf);
-
-		else    /* error in page data */
-			__change_bit(errpos[i], (unsigned long *)buf);
-	}
-
-	printf("%d error(s) corrected at offset %08x\n",
-	       numerrs, page * DOCG4_PAGE_SIZE);
-
-	return numerrs;
-}
-
-static int read_progstatus(struct docg4_priv *doc, void __iomem *docptr)
-{
-	/*
-	 * This apparently checks the status of programming.  Done after an
-	 * erasure, and after page data is written.  On error, the status is
-	 * saved, to be later retrieved by the nand infrastructure code.
-	 */
-
-	/* status is read from the I/O reg */
-	uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
-	uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
-	uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s: %02x %02x %02x\n",
-	    __func__, status1, status2, status3);
-
-	if (status1 != DOCG4_PROGSTATUS_GOOD ||
-	    status2 != DOCG4_PROGSTATUS_GOOD_2 ||
-	    status3 != DOCG4_PROGSTATUS_GOOD_2) {
-		doc->status = NAND_STATUS_FAIL;
-		printf("read_progstatus failed: %02x, %02x, %02x\n",
-		       status1, status2, status3);
-		return -EIO;
-	}
-	return 0;
-}
-
-static int pageprog(struct mtd_info *mtd)
-{
-	/*
-	 * Final step in writing a page.  Writes the contents of its
-	 * internal buffer out to the flash array, or some such.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	int retval = 0;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "docg4: %s\n", __func__);
-
-	writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* Just busy-wait; usleep_range() slows things down noticeably. */
-	poll_status(docptr);
-
-	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	retval = read_progstatus(doc, docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-
-	return retval;
-}
-
-static void sequence_reset(void __iomem *docptr)
-{
-	/* common starting sequence for all operations */
-
-	writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
-	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-}
-
-static void read_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* first step in reading a page */
-
-	sequence_reset(docptr);
-
-	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	write_addr(docptr, docg4_addr);
-
-	write_nop(docptr);
-	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	poll_status(docptr);
-}
-
-static void write_page_prologue(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* first step in writing a page */
-
-	sequence_reset(docptr);
-	writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_addr(docptr, docg4_addr);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-}
-
-static uint32_t mtd_to_docg4_address(int page, int column)
-{
-	/*
-	 * Convert mtd address to format used by the device, 32 bit packed.
-	 *
-	 * Some notes on G4 addressing... The M-Sys documentation on this device
-	 * claims that pages are 2K in length, and indeed, the format of the
-	 * address used by the device reflects that.  But within each page are
-	 * four 512 byte "sub-pages", each with its own oob data that is
-	 * read/written immediately after the 512 bytes of page data.  This oob
-	 * data contains the ecc bytes for the preceeding 512 bytes.
-	 *
-	 * Rather than tell the mtd nand infrastructure that page size is 2k,
-	 * with four sub-pages each, we engage in a little subterfuge and tell
-	 * the infrastructure code that pages are 512 bytes in size.  This is
-	 * done because during the course of reverse-engineering the device, I
-	 * never observed an instance where an entire 2K "page" was read or
-	 * written as a unit.  Each "sub-page" is always addressed individually,
-	 * its data read/written, and ecc handled before the next "sub-page" is
-	 * addressed.
-	 *
-	 * This requires us to convert addresses passed by the mtd nand
-	 * infrastructure code to those used by the device.
-	 *
-	 * The address that is written to the device consists of four bytes: the
-	 * first two are the 2k page number, and the second is the index into
-	 * the page.  The index is in terms of 16-bit half-words and includes
-	 * the preceeding oob data, so e.g., the index into the second
-	 * "sub-page" is 0x108, and the full device address of the start of mtd
-	 * page 0x201 is 0x00800108.
-	 */
-	int g4_page = page / 4;	                      /* device's 2K page */
-	int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
-	return (g4_page << 16) | g4_index;	      /* pack */
-}
-
-static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
-			  int page_addr)
-{
-	/* handle standard nand commands */
-
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s %x, page_addr=%x, column=%x\n",
-	    __func__, command, page_addr, column);
-
-	/*
-	 * Save the command and its arguments.  This enables emulation of
-	 * standard flash devices, and also some optimizations.
-	 */
-	doc->last_command.command = command;
-	doc->last_command.column = column;
-	doc->last_command.page = page_addr;
-
-	switch (command) {
-	case NAND_CMD_RESET:
-		reset(CONFIG_SYS_NAND_BASE);
-		break;
-
-	case NAND_CMD_READ0:
-		read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-		break;
-
-	case NAND_CMD_STATUS:
-		/* next call to read_byte() will expect a status */
-		break;
-
-	case NAND_CMD_SEQIN:
-		write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-
-		/* hack for deferred write of oob bytes */
-		if (doc->oob_page == page_addr)
-			memcpy(nand->oob_poi, doc->oob_buf, 16);
-		break;
-
-	case NAND_CMD_PAGEPROG:
-		pageprog(mtd);
-		break;
-
-	/* we don't expect these, based on review of nand_base.c */
-	case NAND_CMD_READOOB:
-	case NAND_CMD_READID:
-	case NAND_CMD_ERASE1:
-	case NAND_CMD_ERASE2:
-		printf("docg4_command: unexpected nand command 0x%x\n",
-		       command);
-		break;
-	}
-}
-
-static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *nand = mtd->priv;
-	uint16_t *p = (uint16_t *)buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++)
-		p[i] = readw(nand->IO_ADDR_R);
-}
-
-static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
-			  int page)
-{
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t status;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %x\n", __func__, page);
-
-	/*
-	 * Oob bytes are read as part of a normal page read.  If the previous
-	 * nand command was a read of the page whose oob is now being read, just
-	 * copy the oob bytes that we saved in a local buffer and avoid a
-	 * separate oob read.
-	 */
-	if (doc->last_command.command == NAND_CMD_READ0 &&
-	    doc->last_command.page == page) {
-		memcpy(nand->oob_poi, doc->oob_buf, 16);
-		return 0;
-	}
-
-	/*
-	 * Separate read of oob data only.
-	 */
-	docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
-
-	writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* the 1st byte from the I/O reg is a status; the rest is oob data */
-	status = readw(docptr + DOC_IOSPACE_DATA);
-	if (status & DOCG4_READ_ERROR) {
-		printf("docg4_read_oob failed: status = 0x%02x\n", status);
-		return -EIO;
-	}
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: status = 0x%x\n", __func__, status);
-
-	docg4_read_buf(mtd, nand->oob_poi, 16);
-
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-
-	return 0;
-}
-
-static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
-			   int page)
-{
-	/*
-	 * Writing oob-only is not really supported, because MLC nand must write
-	 * oob bytes at the same time as page data.  Nonetheless, we save the
-	 * oob buffer contents here, and then write it along with the page data
-	 * if the same page is subsequently written.  This allows user space
-	 * utilities that write the oob data prior to the page data to work
-	 * (e.g., nandwrite).  The disdvantage is that, if the intention was to
-	 * write oob only, the operation is quietly ignored.  Also, oob can get
-	 * corrupted if two concurrent processes are running nandwrite.
-	 */
-
-	/* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
-	struct docg4_priv *doc = nand->priv;
-	doc->oob_page = page;
-	memcpy(doc->oob_buf, nand->oob_poi, 16);
-	return 0;
-}
-
-static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
-{
-	/* only called when module_param ignore_badblocks is set */
-	return 0;
-}
-
-static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
-	int i;
-	struct nand_chip *nand = mtd->priv;
-	uint16_t *p = (uint16_t *)buf;
-	len >>= 1;
-
-	for (i = 0; i < len; i++)
-		writew(p[i], nand->IO_ADDR_W);
-}
-
-static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
-		       const uint8_t *buf, int use_ecc)
-{
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint8_t ecc_buf[8];
-
-	writew(DOC_ECCCONF0_ECC_ENABLE |
-	       DOC_ECCCONF0_UNKNOWN |
-	       DOCG4_BCH_SIZE,
-	       docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-
-	/* write the page data */
-	docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
-
-	/* oob bytes 0 through 5 are written to I/O reg */
-	docg4_write_buf16(mtd, nand->oob_poi, 6);
-
-	/* oob byte 6 written to a separate reg */
-	writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
-
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* write hw-generated ecc bytes to oob */
-	if (likely(use_ecc)) {
-		/* oob byte 7 is hamming code */
-		uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
-		hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
-		writew(hamming, docptr + DOCG4_OOB_6_7);
-		write_nop(docptr);
-
-		/* read the 7 bch bytes from ecc regs */
-		read_hw_ecc(docptr, ecc_buf);
-		ecc_buf[7] = 0;         /* clear the "page written" flag */
-	}
-
-	/* write user-supplied bytes to oob */
-	else {
-		writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
-		write_nop(docptr);
-		memcpy(ecc_buf, &nand->oob_poi[8], 8);
-	}
-
-	docg4_write_buf16(mtd, ecc_buf, 8);
-	write_nop(docptr);
-	write_nop(docptr);
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-
-	return 0;
-}
-
-static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-				 const uint8_t *buf, int oob_required)
-{
-	return write_page(mtd, nand, buf, 0);
-}
-
-static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
-			     const uint8_t *buf, int oob_required)
-{
-	return write_page(mtd, nand, buf, 1);
-}
-
-static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
-		     uint8_t *buf, int page, int use_ecc)
-{
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t status, edc_err, *buf16;
-
-	writew(DOC_ECCCONF0_READ_MODE |
-	       DOC_ECCCONF0_ECC_ENABLE |
-	       DOC_ECCCONF0_UNKNOWN |
-	       DOCG4_BCH_SIZE,
-	       docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* the 1st byte from the I/O reg is a status; the rest is page data */
-	status = readw(docptr + DOC_IOSPACE_DATA);
-	if (status & DOCG4_READ_ERROR) {
-		printf("docg4_read_page: bad status: 0x%02x\n", status);
-		writew(0, docptr + DOC_DATAEND);
-		return -EIO;
-	}
-
-	docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
-
-	/* first 14 oob bytes read from I/O reg */
-	docg4_read_buf(mtd, nand->oob_poi, 14);
-
-	/* last 2 read from another reg */
-	buf16 = (uint16_t *)(nand->oob_poi + 14);
-	*buf16 = readw(docptr + DOCG4_MYSTERY_REG);
-
-	/*
-	 * Diskonchips read oob immediately after a page read.  Mtd
-	 * infrastructure issues a separate command for reading oob after the
-	 * page is read.  So we save the oob bytes in a local buffer and just
-	 * copy it if the next command reads oob from the same page.
-	 */
-	memcpy(doc->oob_buf, nand->oob_poi, 16);
-
-	write_nop(docptr);
-
-	if (likely(use_ecc)) {
-		/* read the register that tells us if bitflip(s) detected  */
-		edc_err = readw(docptr + DOC_ECCCONF1);
-		edc_err = readw(docptr + DOC_ECCCONF1);
-
-		/* If bitflips are reported, attempt to correct with ecc */
-		if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
-			int bits_corrected = correct_data(mtd, buf, page);
-			if (bits_corrected == -EBADMSG)
-				mtd->ecc_stats.failed++;
-			else
-				mtd->ecc_stats.corrected += bits_corrected;
-		}
-	}
-
-	writew(0, docptr + DOC_DATAEND);
-	return 0;
-}
-
-
-static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
-			       uint8_t *buf, int oob_required, int page)
-{
-	return read_page(mtd, nand, buf, page, 0);
-}
-
-static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
-			   uint8_t *buf, int oob_required, int page)
-{
-	return read_page(mtd, nand, buf, page, 1);
-}
-
-static int docg4_erase_block(struct mtd_info *mtd, int page)
-{
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-	void __iomem *docptr = CONFIG_SYS_NAND_BASE;
-	uint16_t g4_page;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: page %04x\n", __func__, page);
-
-	sequence_reset(docptr);
-
-	writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	/* only 2 bytes of address are written to specify erase block */
-	g4_page = (uint16_t)(page / 4);  /* to g4's 2k page addressing */
-	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-	g4_page >>= 8;
-	writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
-	write_nop(docptr);
-
-	/* start the erasure */
-	writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	poll_status(docptr);
-	writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	read_progstatus(doc, docptr);
-
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-
-	return nand->waitfunc(mtd, nand);
-}
-
-static int read_factory_bbt(struct mtd_info *mtd)
-{
-	/*
-	 * The device contains a read-only factory bad block table.  Read it and
-	 * update the memory-based bbt accordingly.
-	 */
-
-	struct nand_chip *nand = mtd->priv;
-	uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
-	uint8_t *buf;
-	int i, block, status;
-
-	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-	if (buf == NULL)
-		return -ENOMEM;
-
-	read_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-	status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
-	if (status)
-		goto exit;
-
-	/*
-	 * If no memory-based bbt was created, exit.  This will happen if module
-	 * parameter ignore_badblocks is set.  Then why even call this function?
-	 * For an unknown reason, block erase always fails if it's the first
-	 * operation after device power-up.  The above read ensures it never is.
-	 * Ugly, I know.
-	 */
-	if (nand->bbt == NULL)  /* no memory-based bbt */
-		goto exit;
-
-	/*
-	 * Parse factory bbt and update memory-based bbt.  Factory bbt format is
-	 * simple: one bit per block, block numbers increase left to right (msb
-	 * to lsb).  Bit clear means bad block.
-	 */
-	for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
-		int bitnum;
-		uint8_t mask;
-		for (bitnum = 0, mask = 0x80;
-		     bitnum < 8; bitnum++, mask >>= 1) {
-			if (!(buf[i] & mask)) {
-				int badblock = block + bitnum;
-				nand->bbt[badblock / 4] |=
-					0x03 << ((badblock % 4) * 2);
-				mtd->ecc_stats.badblocks++;
-				printf("factory-marked bad block: %d\n",
-				       badblock);
-			}
-		}
-	}
- exit:
-	kfree(buf);
-	return status;
-}
-
-static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
-	/*
-	 * Mark a block as bad.  Bad blocks are marked in the oob area of the
-	 * first page of the block.  The default scan_bbt() in the nand
-	 * infrastructure code works fine for building the memory-based bbt
-	 * during initialization, as does the nand infrastructure function that
-	 * checks if a block is bad by reading the bbt.  This function replaces
-	 * the nand default because writes to oob-only are not supported.
-	 */
-
-	int ret, i;
-	uint8_t *buf;
-	struct nand_chip *nand = mtd->priv;
-	struct nand_bbt_descr *bbtd = nand->badblock_pattern;
-	int block = (int)(ofs >> nand->bbt_erase_shift);
-	int page = (int)(ofs >> nand->page_shift);
-	uint32_t g4_addr = mtd_to_docg4_address(page, 0);
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s: %08llx\n", __func__, ofs);
-
-	if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
-		printf("%s: ofs %llx not start of block!\n",
-		       __func__, ofs);
-
-	/* allocate blank buffer for page data */
-	buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
-	if (buf == NULL)
-		return -ENOMEM;
-
-	/* update bbt in memory */
-	nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
-
-	/* write bit-wise negation of pattern to oob buffer */
-	memset(nand->oob_poi, 0xff, mtd->oobsize);
-	for (i = 0; i < bbtd->len; i++)
-		nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
-
-	/* write first page of block */
-	write_page_prologue(CONFIG_SYS_NAND_BASE, g4_addr);
-	docg4_write_page(mtd, nand, buf, 1);
-	ret = pageprog(mtd);
-	if (!ret)
-		mtd->ecc_stats.badblocks++;
-
-	kfree(buf);
-
-	return ret;
-}
-
-static uint8_t docg4_read_byte(struct mtd_info *mtd)
-{
-	struct nand_chip *nand = mtd->priv;
-	struct docg4_priv *doc = nand->priv;
-
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __func__);
-
-	if (doc->last_command.command == NAND_CMD_STATUS) {
-		int status;
-
-		/*
-		 * Previous nand command was status request, so nand
-		 * infrastructure code expects to read the status here.  If an
-		 * error occurred in a previous operation, report it.
-		 */
-		doc->last_command.command = 0;
-
-		if (doc->status) {
-			status = doc->status;
-			doc->status = 0;
-		}
-
-		/* why is NAND_STATUS_WP inverse logic?? */
-		else
-			status = NAND_STATUS_WP | NAND_STATUS_READY;
-
-		return status;
-	}
-
-	printf("unexpectd call to read_byte()\n");
-
-	return 0;
-}
-
-static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
-{
-	struct docg4_priv *doc = nand->priv;
-	int status = NAND_STATUS_WP;       /* inverse logic?? */
-	MTDDEBUG(MTD_DEBUG_LEVEL3, "%s...\n", __func__);
-
-	/* report any previously unreported error */
-	if (doc->status) {
-		status |= doc->status;
-		doc->status = 0;
-		return status;
-	}
-
-	status |= poll_status(CONFIG_SYS_NAND_BASE);
-	return status;
-}
-
-int docg4_nand_init(struct mtd_info *mtd, struct nand_chip *nand, int devnum)
-{
-	uint16_t id1, id2;
-	struct docg4_priv *docg4;
-	int retval;
-
-	docg4 = kzalloc(sizeof(*docg4), GFP_KERNEL);
-	if (!docg4)
-		return -1;
-
-	mtd->priv = nand;
-	nand->priv = docg4;
-
-	/* These must be initialized here because the docg4 is non-standard
-	 * and doesn't produce an id that the nand code can use to look up
-	 * these values (nand_scan_ident() not called).
-	 */
-	mtd->size = DOCG4_CHIP_SIZE;
-	mtd->name = "Msys_Diskonchip_G4";
-	mtd->writesize = DOCG4_PAGE_SIZE;
-	mtd->erasesize = DOCG4_BLOCK_SIZE;
-	mtd->oobsize = DOCG4_OOB_SIZE;
-
-	nand->IO_ADDR_R =
-		(void __iomem *)CONFIG_SYS_NAND_BASE + DOC_IOSPACE_DATA;
-	nand->IO_ADDR_W = nand->IO_ADDR_R;
-	nand->chipsize = DOCG4_CHIP_SIZE;
-	nand->chip_shift = DOCG4_CHIP_SHIFT;
-	nand->bbt_erase_shift = DOCG4_ERASE_SHIFT;
-	nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
-	nand->chip_delay = 20;
-	nand->page_shift = DOCG4_PAGE_SHIFT;
-	nand->pagemask = 0x3ffff;
-	nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
-	nand->badblockbits = 8;
-	nand->ecc.layout = &docg4_oobinfo;
-	nand->ecc.mode = NAND_ECC_HW_SYNDROME;
-	nand->ecc.size = DOCG4_PAGE_SIZE;
-	nand->ecc.prepad = 8;
-	nand->ecc.bytes	= 8;
-	nand->ecc.strength = DOCG4_T;
-	nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
-	nand->controller = &nand->hwcontrol;
-
-	/* methods */
-	nand->cmdfunc = docg4_command;
-	nand->waitfunc = docg4_wait;
-	nand->select_chip = docg4_select_chip;
-	nand->read_byte = docg4_read_byte;
-	nand->block_markbad = docg4_block_markbad;
-	nand->read_buf = docg4_read_buf;
-	nand->write_buf = docg4_write_buf16;
-	nand->scan_bbt = nand_default_bbt;
-	nand->erase = docg4_erase_block;
-	nand->ecc.read_page = docg4_read_page;
-	nand->ecc.write_page = docg4_write_page;
-	nand->ecc.read_page_raw = docg4_read_page_raw;
-	nand->ecc.write_page_raw = docg4_write_page_raw;
-	nand->ecc.read_oob = docg4_read_oob;
-	nand->ecc.write_oob = docg4_write_oob;
-
-	/*
-	 * The way the nand infrastructure code is written, a memory-based bbt
-	 * is not created if NAND_SKIP_BBTSCAN is set.  With no memory bbt,
-	 * nand->block_bad() is used.  So when ignoring bad blocks, we skip the
-	 * scan and define a dummy block_bad() which always returns 0.
-	 */
-	if (ignore_badblocks) {
-		nand->options |= NAND_SKIP_BBTSCAN;
-		nand->block_bad	= docg4_block_neverbad;
-	}
-
-	reset(CONFIG_SYS_NAND_BASE);
-
-	/* check for presence of g4 chip by reading id registers */
-	id1 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID);
-	id1 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
-	id2 = readw(CONFIG_SYS_NAND_BASE + DOC_CHIPID_INV);
-	id2 = readw(CONFIG_SYS_NAND_BASE + DOCG4_MYSTERY_REG);
-	if (id1 != DOCG4_IDREG1_VALUE || id2 != DOCG4_IDREG2_VALUE)
-		return -1;
-
-	/* initialize bch algorithm */
-	docg4->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
-	if (docg4->bch == NULL)
-		return -1;
-
-	retval = nand_scan_tail(mtd);
-	if (retval)
-		return -1;
-
-	/*
-	 * Scan for bad blocks and create bbt here, then add the factory-marked
-	 * bad blocks to the bbt.
-	 */
-	nand->scan_bbt(mtd);
-	nand->options |= NAND_BBT_SCANNED;
-	retval = read_factory_bbt(mtd);
-	if (retval)
-		return -1;
-
-	retval = nand_register(devnum);
-	if (retval)
-		return -1;
-
-	return 0;
-}
diff --git a/drivers/mtd/nand/docg4_spl.c b/drivers/mtd/nand/docg4_spl.c
deleted file mode 100644
index 351b75a090..0000000000
--- a/drivers/mtd/nand/docg4_spl.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * SPL driver for Diskonchip G4 nand flash
- *
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * This driver basically mimics the load functionality of a typical IPL (initial
- * program loader) resident in the 2k NOR-like region of the docg4 that is
- * mapped to the reset vector.  It allows the u-boot SPL to continue loading if
- * the IPL loads a fixed number of flash blocks that is insufficient to contain
- * the entire u-boot image.  In this case, a concatenated spl + u-boot image is
- * written at the flash offset from which the IPL loads an image, and when the
- * IPL jumps to the SPL, the SPL resumes loading where the IPL left off.  See
- * the palmtreo680 for an example.
- *
- * This driver assumes that the data was written to the flash using the device's
- * "reliable" mode, and also assumes that each 512 byte page is stored
- * redundantly in the subsequent page.  This storage format is likely to be used
- * by all boards that boot from the docg4.  The format compensates for the lack
- * of ecc in the IPL.
- *
- * Reliable mode reduces the capacity of a block by half, and the redundant
- * pages reduce it by half again.  As a result, the normal 256k capacity of a
- * block is reduced to 64k for the purposes of the IPL/SPL.
- */
-
-#include <asm/io.h>
-#include <linux/mtd/docg4.h>
-
-/* forward declarations */
-static inline void write_nop(void __iomem *docptr);
-static int poll_status(void __iomem *docptr);
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr);
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
-			     void __iomem *docptr);
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr);
-
-int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
-{
-	void *load_addr = dst;
-	uint32_t flash_offset = offs;
-	const unsigned int block_count =
-		(size + DOCG4_BLOCK_CAPACITY_SPL - 1)
-		/ DOCG4_BLOCK_CAPACITY_SPL;
-	int i;
-
-	for (i = 0; i < block_count; i++) {
-		int ret = docg4_load_block_reliable(flash_offset, load_addr);
-		if (ret)
-			return ret;
-		load_addr += DOCG4_BLOCK_CAPACITY_SPL;
-		flash_offset += DOCG4_BLOCK_SIZE;
-	}
-	return 0;
-}
-
-static inline void write_nop(void __iomem *docptr)
-{
-	writew(0, docptr + DOC_NOP);
-}
-
-static int poll_status(void __iomem *docptr)
-{
-	/*
-	 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
-	 * register.  Operations known to take a long time (e.g., block erase)
-	 * should sleep for a while before calling this.
-	 */
-
-	uint8_t flash_status;
-
-	/* hardware quirk requires reading twice initially */
-	flash_status = readb(docptr + DOC_FLASHCONTROL);
-
-	do {
-		flash_status = readb(docptr + DOC_FLASHCONTROL);
-	} while (!(flash_status & DOC_CTRL_FLASHREADY));
-
-	return 0;
-}
-
-static void write_addr(void __iomem *docptr, uint32_t docg4_addr)
-{
-	/* write the four address bytes packed in docg4_addr to the device */
-
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-	docg4_addr >>= 8;
-	writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
-}
-
-static void address_sequence(unsigned int g4_page, unsigned int g4_index,
-			     void __iomem *docptr)
-{
-	writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
-	writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_addr(docptr, ((uint32_t)g4_page << 16) | g4_index);
-	write_nop(docptr);
-}
-
-static int docg4_load_block_reliable(uint32_t flash_offset, void *dest_addr)
-{
-	void __iomem *docptr = (void *)CONFIG_SYS_NAND_BASE;
-	unsigned int g4_page = flash_offset >> 11; /* 2k page */
-	const unsigned int last_g4_page = g4_page + 0x80; /* last in block */
-	int g4_index = 0;
-	uint16_t flash_status;
-	uint16_t *buf;
-
-	/* flash_offset must be aligned to the start of a block */
-	if (flash_offset & 0x3ffff)
-		return -1;
-
-	writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
-	writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	write_nop(docptr);
-	writew(0x45, docptr + DOC_FLASHSEQUENCE);
-	writew(0xa3, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	writew(0x22, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-
-	/* read 1st 4 oob bytes of first subpage of block */
-	address_sequence(g4_page, 0x0100, docptr); /* index at oob */
-	write_nop(docptr);
-	flash_status = readw(docptr + DOC_FLASHCONTROL);
-	flash_status = readw(docptr + DOC_FLASHCONTROL);
-	if (flash_status & 0x06) /* sequence or protection errors */
-		return -1;
-	writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
-	write_nop(docptr);
-	write_nop(docptr);
-	poll_status(docptr);
-	writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/*
-	 * Here we read the first four oob bytes of the first page of the block.
-	 * The IPL on the palmtreo680 requires that this contain a 32 bit magic
-	 * number, or the load aborts.  We'll ignore it.
-	 */
-	readw(docptr + 0x103c); /* hw quirk; 1st read discarded */
-	readw(docptr + 0x103c);	/* lower 16 bits of magic number */
-	readw(docptr + DOCG4_MYSTERY_REG); /* upper 16 bits of magic number */
-	writew(0, docptr + DOC_DATAEND);
-	write_nop(docptr);
-	write_nop(docptr);
-
-	/* load contents of block to memory */
-	buf = (uint16_t *)dest_addr;
-	do {
-		int i;
-
-		address_sequence(g4_page, g4_index, docptr);
-		writew(DOCG4_CMD_READ2,
-		       docptr + DOC_FLASHCOMMAND);
-		write_nop(docptr);
-		write_nop(docptr);
-		poll_status(docptr);
-		writew(DOC_ECCCONF0_READ_MODE |
-		       DOC_ECCCONF0_ECC_ENABLE |
-		       DOCG4_BCH_SIZE,
-		       docptr + DOC_ECCCONF0);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-		write_nop(docptr);
-
-		/* read the 512 bytes of page data, 2 bytes at a time */
-		readw(docptr + 0x103c); /* hw quirk */
-		for (i = 0; i < 256; i++)
-			*buf++ = readw(docptr + 0x103c);
-
-		/* read oob, but discard it */
-		for (i = 0; i < 7; i++)
-			readw(docptr + 0x103c);
-		readw(docptr + DOCG4_OOB_6_7);
-		readw(docptr + DOCG4_OOB_6_7);
-
-		writew(0, docptr + DOC_DATAEND);
-		write_nop(docptr);
-		write_nop(docptr);
-
-		if (!(g4_index & 0x100)) {
-			/* not redundant subpage read; check for ecc error */
-			write_nop(docptr);
-			flash_status = readw(docptr + DOC_ECCCONF1);
-			flash_status = readw(docptr + DOC_ECCCONF1);
-			if (flash_status & 0x80) { /* ecc error */
-				g4_index += 0x108; /* read redundant subpage */
-				buf -= 256;        /* back up ram ptr */
-				continue;
-			} else                       /* no ecc error */
-				g4_index += 0x210; /* skip redundant subpage */
-		} else  /* redundant page was just read; skip ecc error check */
-			g4_index += 0x108;
-
-		if (g4_index == 0x420) { /* finished with 2k page */
-			g4_index = 0;
-			g4_page += 2; /* odd-numbered 2k pages skipped */
-		}
-
-	} while (g4_page != last_g4_page); /* while still on same block */
-
-	return 0;
-}
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index d457d53574..f621f14122 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -154,8 +154,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
  */
 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 	int buf_num;
@@ -194,8 +194,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  */
 static int fsl_elbc_run_command(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -246,7 +246,7 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
 
 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 {
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -279,8 +279,8 @@ static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -489,8 +489,8 @@ static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
  */
 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
 
@@ -526,8 +526,8 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  */
 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 
 	/* If there are still bytes in the FCM, then use the next byte. */
@@ -543,8 +543,8 @@ static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
  */
 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	int avail;
 
@@ -566,7 +566,7 @@ static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  */
 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
-	struct fsl_elbc_mtd *priv = chip->priv;
+	struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 	fsl_lbc_t *lbc = ctrl->regs;
 
@@ -611,7 +611,8 @@ static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * waitfunc.
  */
 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required,
+				int page)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -626,7 +627,7 @@ static struct fsl_elbc_ctrl *elbc_ctrl;
  */
 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 				uint32_t offset, uint32_t data_len,
-				const uint8_t *buf, int oob_required)
+				const uint8_t *buf, int oob_required, int page)
 {
 	fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 	fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -656,7 +657,7 @@ static void fsl_elbc_ctrl_init(void)
 
 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *nand;
 	struct fsl_elbc_mtd *priv;
 	uint32_t br = 0, or = 0;
@@ -697,7 +698,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	elbc_ctrl->chips[priv->bank] = priv;
 
@@ -719,7 +720,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	nand->bbt_options = NAND_BBT_USE_FLASH;
 
 	nand->controller = &elbc_ctrl->controller;
-	nand->priv = priv;
+	nand_set_controller_data(nand, priv);
 
 	nand->ecc.read_page = fsl_elbc_read_page;
 	nand->ecc.write_page = fsl_elbc_write_page;
@@ -787,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, mtd);
 	if (ret)
 		return ret;
 
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 975b0d4613..7001cbd62d 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -222,8 +222,8 @@ static struct nand_bbt_descr bbt_mirror_descr = {
  */
 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	int buf_num;
@@ -247,8 +247,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
 		    unsigned int bufnum)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
 	u32 __iomem *main = (u32 *)addr;
 	u8 __iomem *oob = addr + mtd->writesize;
@@ -286,8 +286,8 @@ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  */
 static int fsl_ifc_run_command(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
@@ -367,7 +367,7 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 			    int oob,
 			    struct mtd_info *mtd)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
@@ -404,8 +404,8 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 
@@ -607,8 +607,8 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  */
 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	unsigned int bufsize = mtd->writesize + mtd->oobsize;
 
@@ -635,8 +635,8 @@ static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  */
 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	unsigned int offset;
 
@@ -659,8 +659,8 @@ static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  */
 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	uint16_t data;
 
@@ -683,8 +683,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  */
 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	int avail;
 
@@ -706,7 +706,7 @@ static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  */
 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
 	u32 nand_fsr;
@@ -739,7 +739,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 			     uint8_t *buf, int oob_required, int page)
 {
-	struct fsl_ifc_mtd *priv = chip->priv;
+	struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 
 	fsl_ifc_read_buf(mtd, buf, mtd->writesize);
@@ -755,7 +755,7 @@ static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * waitfunc.
  */
 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			       const uint8_t *buf, int oob_required)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	fsl_ifc_write_buf(mtd, buf, mtd->writesize);
 	fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -880,7 +880,7 @@ static int fsl_ifc_sram_init(uint32_t ver)
 
 static int fsl_ifc_chip_init(int devnum, u8 *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *nand;
 	struct fsl_ifc_mtd *priv;
 	struct nand_ecclayout *layout;
@@ -925,7 +925,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand = &priv->chip;
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	ifc_ctrl->chips[priv->bank] = priv;
 
@@ -954,7 +954,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	}
 
 	nand->controller = &ifc_ctrl->controller;
-	nand->priv = priv;
+	nand_set_controller_data(nand, priv);
 
 	nand->ecc.read_page = fsl_ifc_read_page;
 	nand->ecc.write_page = fsl_ifc_write_page;
@@ -1044,7 +1044,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, mtd);
 	if (ret)
 		return ret;
 	return 0;
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 5426c32114..d2b388197b 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -64,8 +64,8 @@ static void fun_wait(struct fsl_upm_nand *fun)
 #if CONFIG_SYS_NAND_MAX_CHIPS > 1
 static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	if (chip_nr >= 0) {
 		fun->chip_nr = chip_nr;
@@ -79,8 +79,8 @@ static void fun_select_chip(struct mtd_info *mtd, int chip_nr)
 
 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 	void __iomem *io_addr;
 	u32 mar;
 
@@ -123,7 +123,7 @@ static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
 static u8 upm_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	return in_8(chip->IO_ADDR_R);
 }
@@ -131,8 +131,8 @@ static u8 upm_nand_read_byte(struct mtd_info *mtd)
 static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	for (i = 0; i < len; i++) {
 		out_8(chip->IO_ADDR_W, buf[i]);
@@ -147,7 +147,7 @@ static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++)
 		buf[i] = in_8(chip->IO_ADDR_R);
@@ -155,8 +155,8 @@ static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 
 static int nand_dev_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct fsl_upm_nand *fun = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct fsl_upm_nand *fun = nand_get_controller_data(chip);
 
 	return fun->dev_ready(fun->chip_nr);
 }
@@ -168,7 +168,7 @@ int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun)
 
 	fun->last_ctrl = NAND_CLE;
 
-	chip->priv = fun;
+	nand_set_controller_data(chip, fun);
 	chip->chip_delay = fun->chip_delay;
 	chip->ecc.mode = NAND_ECC_SOFT;
 	chip->cmd_ctrl = fun_cmd_ctrl;
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c
index e0e9e1ebd0..a1f2cbae33 100644
--- a/drivers/mtd/nand/fsmc_nand.c
+++ b/drivers/mtd/nand/fsmc_nand.c
@@ -165,7 +165,7 @@ static int count_written_bits(uint8_t *buff, int size, int max_bits)
 
 static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong IO_ADDR_W;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
@@ -409,8 +409,8 @@ int fsmc_nand_switch_ecc(uint32_t eccstrength)
 	 * Nomadik SoC is currently supporting this fsmc_nand_switch_ecc()
 	 * function, as it doesn't need to switch to a different ECC layout.
 	 */
-	mtd = &nand_info[nand_curr_device];
-	nand = mtd->priv;
+	mtd = nand_info[nand_curr_device];
+	nand = mtd_to_nand(mtd);
 
 	/* Setup the ecc configurations again */
 	if (eccstrength == 1) {
@@ -443,7 +443,6 @@ int fsmc_nand_init(struct nand_chip *nand)
 {
 	static int chip_nr;
 	struct mtd_info *mtd;
-	int i;
 	u32 peripid2 = readl(&fsmc_regs_p->peripid2);
 
 	fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) &
@@ -480,8 +479,7 @@ int fsmc_nand_init(struct nand_chip *nand)
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	nand->badblockbits = 7;
 
-	mtd = &nand_info[chip_nr++];
-	mtd->priv = nand;
+	mtd = nand_to_mtd(nand);
 
 	switch (fsmc_version) {
 	case FSMC_VER8:
@@ -514,9 +512,8 @@ int fsmc_nand_init(struct nand_chip *nand)
 	if (nand_scan_tail(mtd))
 		return -ENXIO;
 
-	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		if (nand_register(i))
-			return -ENXIO;
+	if (nand_register(chip_nr++, mtd))
+		return -ENXIO;
 
 	return 0;
 }
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
deleted file mode 100644
index abcedc2102..0000000000
--- a/drivers/mtd/nand/jz4740_nand.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Platform independend driver for JZ4740.
- *
- * Copyright (c) 2007 Ingenic Semiconductor Inc.
- * Author: <jlwei@ingenic.cn>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#include <common.h>
-
-#include <nand.h>
-#include <asm/io.h>
-#include <asm/jz4740.h>
-
-#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
-#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
-#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
-
-#define JZ_NAND_ECC_CTRL_ENCODING	BIT(3)
-#define JZ_NAND_ECC_CTRL_RS		BIT(2)
-#define JZ_NAND_ECC_CTRL_RESET		BIT(1)
-#define JZ_NAND_ECC_CTRL_ENABLE		BIT(0)
-
-#define EMC_SMCR1_OPT_NAND	0x094c4400
-/* Optimize the timing of nand */
-
-static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
-
-static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
-	.eccbytes = 72,
-	.eccpos = {
-		12, 13, 14, 15, 16, 17, 18, 19,
-		20, 21, 22, 23, 24, 25, 26, 27,
-		28, 29, 30, 31, 32, 33, 34, 35,
-		36, 37, 38, 39, 40, 41, 42, 43,
-		44, 45, 46, 47, 48, 49, 50, 51,
-		52, 53, 54, 55, 56, 57, 58, 59,
-		60, 61, 62, 63, 64, 65, 66, 67,
-		68, 69, 70, 71, 72, 73, 74, 75,
-		76, 77, 78, 79, 80, 81, 82, 83 },
-	.oobfree = {
-		{.offset = 2,
-		 .length = 10 },
-		{.offset = 84,
-		 .length = 44 } }
-};
-
-static int is_reading;
-
-static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	uint32_t reg;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if (ctrl & NAND_ALE)
-			this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
-		else if (ctrl & NAND_CLE)
-			this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
-		else
-			this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
-
-		reg = readl(&emc->nfcsr);
-		if (ctrl & NAND_NCE)
-			reg |= EMC_NFCSR_NFCE1;
-		else
-			reg &= ~EMC_NFCSR_NFCE1;
-		writel(reg, &emc->nfcsr);
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-static int jz_nand_device_ready(struct mtd_info *mtd)
-{
-	return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
-}
-
-void board_nand_select_device(struct nand_chip *nand, int chip)
-{
-	/*
-	 * Don't use "chip" to address the NAND device,
-	 * generate the cs from the address where it is encoded.
-	 */
-}
-
-static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
-				u_char *ecc_code)
-{
-	uint32_t status;
-	int i;
-
-	if (is_reading)
-		return 0;
-
-	do {
-		status = readl(&emc->nfints);
-	} while (!(status & EMC_NFINTS_ENCF));
-
-	/* disable ecc */
-	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
-	for (i = 0; i < 9; i++)
-		ecc_code[i] = readb(&emc->nfpar[i]);
-
-	return 0;
-}
-
-static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
-{
-	uint32_t reg;
-
-	writel(0, &emc->nfints);
-	reg = readl(&emc->nfecr);
-	reg |= JZ_NAND_ECC_CTRL_RESET;
-	reg |= JZ_NAND_ECC_CTRL_ENABLE;
-	reg |= JZ_NAND_ECC_CTRL_RS;
-
-	switch (mode) {
-	case NAND_ECC_READ:
-		reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
-		is_reading = 1;
-		break;
-	case NAND_ECC_WRITE:
-		reg |= JZ_NAND_ECC_CTRL_ENCODING;
-		is_reading = 0;
-		break;
-	default:
-		break;
-	}
-
-	writel(reg, &emc->nfecr);
-}
-
-/* Correct 1~9-bit errors in 512-bytes data */
-static void jz_rs_correct(unsigned char *dat, int idx, int mask)
-{
-	int i;
-
-	idx--;
-
-	i = idx + (idx >> 3);
-	if (i >= 512)
-		return;
-
-	mask <<= (idx & 0x7);
-
-	dat[i] ^= mask & 0xff;
-	if (i < 511)
-		dat[i + 1] ^= (mask >> 8) & 0xff;
-}
-
-static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
-				   u_char *read_ecc, u_char *calc_ecc)
-{
-	int k;
-	uint32_t errcnt, index, mask, status;
-
-	/* Set PAR values */
-	const uint8_t all_ff_ecc[] = {
-		0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
-
-	if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
-	    read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
-	    read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
-	    read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
-	    read_ecc[8] == 0xff) {
-		for (k = 0; k < 9; k++)
-			writeb(all_ff_ecc[k], &emc->nfpar[k]);
-	} else {
-		for (k = 0; k < 9; k++)
-			writeb(read_ecc[k], &emc->nfpar[k]);
-	}
-	/* Set PRDY */
-	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
-
-	/* Wait for completion */
-	do {
-		status = readl(&emc->nfints);
-	} while (!(status & EMC_NFINTS_DECF));
-
-	/* disable ecc */
-	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
-
-	/* Check decoding */
-	if (!(status & EMC_NFINTS_ERR))
-		return 0;
-
-	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
-		return -1;
-	}
-
-	errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
-
-	switch (errcnt) {
-	case 4:
-		index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 3:
-		index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 2:
-		index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	case 1:
-		index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
-			EMC_NFERR_INDEX_BIT;
-		mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
-			EMC_NFERR_MASK_BIT;
-		jz_rs_correct(dat, index, mask);
-	default:
-		break;
-	}
-
-	return errcnt;
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
-	uint32_t reg;
-
-	reg = readl(&emc->nfcsr);
-	reg |= EMC_NFCSR_NFE1;	/* EMC setup, Set NFE bit */
-	writel(reg, &emc->nfcsr);
-
-	writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
-
-	nand->IO_ADDR_R		= JZ_NAND_DATA_ADDR;
-	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
-	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
-	nand->dev_ready		= jz_nand_device_ready;
-	nand->ecc.hwctl		= jz_nand_hwctl;
-	nand->ecc.correct	= jz_nand_rs_correct_data;
-	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;
-	nand->ecc.mode		= NAND_ECC_HW_OOB_FIRST;
-	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
-	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
-	nand->ecc.strength	= 4;
-	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
-	nand->chip_delay	= 50;
-	nand->bbt_options	|= NAND_BBT_USE_FLASH;
-
-	return 0;
-}
diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c
index 22c5625407..e978cf8c82 100644
--- a/drivers/mtd/nand/kb9202_nand.c
+++ b/drivers/mtd/nand/kb9202_nand.c
@@ -35,7 +35,7 @@
  */
 static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c
index d734113f64..d0a68bdcb9 100644
--- a/drivers/mtd/nand/kirkwood_nand.c
+++ b/drivers/mtd/nand/kirkwood_nand.c
@@ -33,7 +33,7 @@ static u32 nand_mpp_backup[9] = { 0 };
 static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 			      unsigned int ctrl)
 {
-	struct nand_chip *nc = mtd->priv;
+	struct nand_chip *nc = mtd_to_nand(mtd);
 	u32 offs;
 
 	if (cmd == NAND_CMD_NONE)
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c b/drivers/mtd/nand/lpc32xx_nand_mlc.c
index 8156fe9613..4262029819 100644
--- a/drivers/mtd/nand/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -378,7 +378,8 @@ static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  */
 
 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
 	unsigned int i, status, timeout;
 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
@@ -435,7 +436,8 @@ static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
  */
 
 static int lpc32xx_write_page_raw(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
 	unsigned int i;
 	struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
@@ -539,11 +541,7 @@ static struct nand_chip lpc32xx_chip;
 
 void board_nand_init(void)
 {
-	/* we have only one device anyway */
-	struct mtd_info *mtd = &nand_info[0];
-	/* chip is struct nand_chip, and is now provided by the driver. */
-	mtd->priv = &lpc32xx_chip;
-	/* to store return status in case we need to print it */
+	struct mtd_info *mtd = &lpc32xx_chip.mtd;
 	int ret;
 
 	/* Set all BOARDSPECIFIC (actually core-specific) fields  */
@@ -597,7 +595,7 @@ void board_nand_init(void)
 	}
 
 	/* chip is good, register it */
-	ret = nand_register(0);
+	ret = nand_register(0, mtd);
 	if (ret)
 		error("nand_register returned %i", ret);
 }
diff --git a/drivers/mtd/nand/lpc32xx_nand_slc.c b/drivers/mtd/nand/lpc32xx_nand_slc.c
index 4e1be36654..daa1e7a501 100644
--- a/drivers/mtd/nand/lpc32xx_nand_slc.c
+++ b/drivers/mtd/nand/lpc32xx_nand_slc.c
@@ -291,7 +291,7 @@ static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
 static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
 			      int len, int read)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 config;
 	int ret;
 
@@ -486,7 +486,8 @@ static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 /* Reuse the logic from "nand_write_page_hwecc()" */
 static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
 				    struct nand_chip *chip,
-				    const uint8_t *buf, int oob_required)
+				    const uint8_t *buf, int oob_required,
+				    int page)
 {
 	int i;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index e621c3665e..8a8775c4c5 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -100,7 +100,6 @@
 #define NFC_WPC_UNLOCK		(1 << 2)
 
 struct mpc5121_nfc_prv {
-	struct mtd_info mtd;
 	struct nand_chip chip;
 	int irq;
 	void __iomem *regs;
@@ -117,8 +116,8 @@ static void mpc5121_nfc_done(struct mtd_info *mtd);
 /* Read NFC register */
 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	return in_be16(prv->regs + reg);
 }
@@ -126,8 +125,8 @@ static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
 /* Write NFC register */
 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	out_be16(prv->regs + reg, val);
 }
@@ -211,7 +210,7 @@ static void mpc5121_nfc_done(struct mtd_info *mtd)
 /* Do address cycle(s) */
 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 pagemask = chip->pagemask;
 
 	if (column != -1) {
@@ -283,8 +282,8 @@ static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
 static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
 				int column, int page)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 
 	prv->column = (column >= 0) ? column : 0;
 	prv->spareonly = 0;
@@ -357,8 +356,8 @@ static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 				   u8 * buffer, uint size, int wr)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mpc5121_nfc_prv *prv = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(nand);
 	uint o, s, sbsize, blksize;
 
 	/*
@@ -410,8 +409,8 @@ static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char * buf, int len,
 				 int wr)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mpc5121_nfc_prv *prv = nand_get_controller_data(chip);
 	uint c = prv->column;
 	uint l;
 
@@ -489,7 +488,7 @@ static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
 {
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint rcw_pagesize = 0;
 	uint rcw_sparesize = 0;
 	uint rcw_width;
@@ -549,7 +548,6 @@ int board_nand_init(struct nand_chip *chip)
 	int resettime = 0;
 	int retval = 0;
 	int rev;
-	static int chip_nr = 0;
 
 	/*
 	 * Check SoC revision. This driver supports only NFC
@@ -568,9 +566,8 @@ int board_nand_init(struct nand_chip *chip)
 		return -ENOMEM;
 	}
 
-	mtd = &nand_info[chip_nr++];
-	mtd->priv = chip;
-	chip->priv = prv;
+	mtd = &chip->mtd;
+	nand_set_controller_data(chip, prv);
 
 	/* Read NFC configuration from Reset Config Word */
 	retval = mpc5121_nfc_read_hw_config(mtd);
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index f12b07e7ad..7221d0ba0d 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -19,7 +19,6 @@
 #define DRIVER_NAME "mxc_nand"
 
 struct mxc_nand_host {
-	struct mtd_info			mtd;
 	struct nand_chip		*nand;
 
 	struct mxc_nand_regs __iomem	*regs;
@@ -351,8 +350,8 @@ static int mxc_nand_dev_ready(struct mtd_info *mtd)
 
 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 	uint16_t tmp = readnfc(&host->regs->config1);
 
@@ -386,7 +385,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 				      struct nand_chip *chip,
 				      int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	uint8_t *buf = chip->oob_poi;
 	int length = mtd->oobsize;
 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -441,7 +440,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 					   int oob_required,
 					   int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -486,7 +485,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 				       int oob_required,
 				       int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int n, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -550,7 +549,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 				       struct nand_chip *chip, int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 	int length = mtd->oobsize;
 	int i, len, status, steps = chip->ecc.steps;
@@ -576,9 +575,9 @@ static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					     struct nand_chip *chip,
 					     const uint8_t *buf,
-					     int oob_required)
+					     int oob_required, int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -616,9 +615,9 @@ static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 					 struct nand_chip *chip,
 					 const uint8_t *buf,
-					 int oob_required)
+					 int oob_required, int page)
 {
-	struct mxc_nand_host *host = chip->priv;
+	struct mxc_nand_host *host = nand_get_controller_data(chip);
 	int i, n, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
@@ -661,8 +660,8 @@ static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				 u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 	int subpages = mtd->writesize / nand_chip->subpagesize;
 	int pg2blk_shift = nand_chip->phys_erase_shift -
@@ -681,7 +680,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				       mtd->writesize / nand_chip->subpagesize
 					    - subpages);
 			}
-			return -1;
+			return -EBADMSG;
 		}
 		ecc_status >>= 4;
 		subpages--;
@@ -700,8 +699,8 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 				 u_char *read_ecc, u_char *calc_ecc)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	/*
 	 * 1-Bit errors are automatically corrected in HW.  No need for
@@ -713,7 +712,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 	if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 		MTDDEBUG(MTD_DEBUG_LEVEL0,
 		      "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
-		return -1;
+		return -EBADMSG;
 	}
 
 	return 0;
@@ -729,8 +728,8 @@ static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 
 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint8_t ret = 0;
 	uint16_t col;
 	uint16_t __iomem *main_buf =
@@ -769,8 +768,8 @@ static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 
 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	uint16_t col, ret;
 	uint16_t __iomem *p;
 
@@ -821,8 +820,8 @@ static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 static void mxc_nand_write_buf(struct mtd_info *mtd,
 				const u_char *buf, int len)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	int n, col, i = 0;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -895,8 +894,8 @@ static void mxc_nand_write_buf(struct mtd_info *mtd,
  */
 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 	int n, col, i = 0;
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
@@ -955,8 +954,8 @@ static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  */
 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	switch (chip) {
 	case -1:
@@ -982,8 +981,8 @@ static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 				int column, int page_addr)
 {
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
+	struct nand_chip *nand_chip = mtd_to_nand(mtd);
+	struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 
 	MTDDEBUG(MTD_DEBUG_LEVEL3,
 	      "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
@@ -1164,14 +1163,13 @@ int board_nand_init(struct nand_chip *this)
 #endif
 
 	/* structures must be linked */
-	mtd = &host->mtd;
-	mtd->priv = this;
+	mtd = &this->mtd;
 	host->nand = this;
 
 	/* 5 us command delay time */
 	this->chip_delay = 5;
 
-	this->priv = host;
+	nand_set_controller_data(this, host);
 	this->dev_ready = mxc_nand_dev_ready;
 	this->cmdfunc = mxc_nand_command;
 	this->select_chip = mxc_nand_select_chip;
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c
index 6ac2c96eeb..841fb5bd96 100644
--- a/drivers/mtd/nand/mxc_nand_spl.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -232,7 +232,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
 	nfc_nand_read_page(page_address);
 
 	if (nfc_nand_check_ecc())
-		return -1;
+		return -EBADMSG;
 
 	src = (u32 *)&nfc->main_area[0][0];
 	dst = (u32 *)buf;
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 5528d4b45b..c90a3a7bd2 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -264,8 +264,8 @@ static int mxs_nand_wait_for_bch_complete(void)
  */
 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -343,8 +343,8 @@ static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
  */
 static int mxs_nand_device_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	struct mxs_gpmi_regs *gpmi_regs =
 		(struct mxs_gpmi_regs *)MXS_GPMI_BASE;
 	uint32_t tmp;
@@ -360,8 +360,8 @@ static int mxs_nand_device_ready(struct mtd_info *mtd)
  */
 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 
 	nand_info->cur_chip = chip;
 }
@@ -410,8 +410,8 @@ static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
  */
 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -494,8 +494,8 @@ rtn:
 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 				int length)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -559,7 +559,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
 					uint8_t *buf, int oob_required,
 					int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	uint32_t corrected = 0, failed = 0;
@@ -707,9 +707,9 @@ rtn:
  */
 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
 				struct nand_chip *nand, const uint8_t *buf,
-				int oob_required)
+				int oob_required, int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_dma_desc *d;
 	uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
 	int ret;
@@ -775,8 +775,8 @@ rtn:
 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
 					struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	if (ops->mode == MTD_OPS_RAW)
@@ -800,8 +800,8 @@ static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
 					struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	if (ops->mode == MTD_OPS_RAW)
@@ -824,8 +824,8 @@ static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
  */
 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct mxs_nand_info *nand_info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
 	int ret;
 
 	nand_info->marking_block_bad = 1;
@@ -884,7 +884,7 @@ static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
 				int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 
 	/*
 	 * First, fill in the OOB buffer. If we're doing a raw read, we need to
@@ -919,7 +919,7 @@ static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
 					int page)
 {
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	uint8_t block_mark = 0;
 
 	/*
@@ -961,7 +961,7 @@ static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
  * Thus, this function is only called when we want *all* blocks to look good,
  * so it *always* return success.
  */
-static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
 	return 0;
 }
@@ -982,8 +982,8 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  */
 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 {
-	struct nand_chip *nand = mtd->priv;
-	struct mxs_nand_info *nand_info = nand->priv;
+	struct nand_chip *nand = mtd_to_nand(mtd);
+	struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
 	struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
 	uint32_t tmp;
 
@@ -1175,7 +1175,7 @@ int board_nand_init(struct nand_chip *nand)
 
 	memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
 
-	nand->priv = nand_info;
+	nand_set_controller_data(nand, nand_info);
 	nand->options |= NAND_NO_SUBPAGE_WRITE;
 
 	nand->cmd_ctrl		= mxs_nand_cmd_ctrl;
diff --git a/drivers/mtd/nand/mxs_nand_spl.c b/drivers/mtd/nand/mxs_nand_spl.c
index 0e7c364a22..a8a3084d03 100644
--- a/drivers/mtd/nand/mxs_nand_spl.c
+++ b/drivers/mtd/nand/mxs_nand_spl.c
@@ -8,13 +8,13 @@
 #include <nand.h>
 #include <malloc.h>
 
-static nand_info_t mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 			     int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 timeo, time_start;
 
 	/* write out the command to the device */
@@ -51,7 +51,7 @@ static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
 
 static int mxs_flash_ident(struct mtd_info *mtd)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int i;
 	u8 mfg_id, dev_id;
 	u8 id_data[8];
@@ -111,7 +111,7 @@ static int mxs_flash_ident(struct mtd_info *mtd)
 
 static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret;
 
 	chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
@@ -125,7 +125,7 @@ static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
 
 static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	unsigned int block = offs >> chip->phys_erase_shift;
 	unsigned int page = offs >> chip->page_shift;
 
@@ -147,14 +147,14 @@ static int mxs_nand_init(void)
 
 	/* init mxs nand driver */
 	board_nand_init(&nand_chip);
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
 	/* set mtd functions */
 	nand_chip.cmdfunc = mxs_nand_command;
 	nand_chip.numchips = 1;
 
 	/* identify flash device */
 	puts("NAND : ");
-	if (mxs_flash_ident(&mtd)) {
+	if (mxs_flash_ident(mtd)) {
 		printf("Failed to identify\n");
 		return -1;
 	}
@@ -162,12 +162,12 @@ static int mxs_nand_init(void)
 	/* allocate and initialize buffers */
 	nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
 				     sizeof(*nand_chip.buffers));
-	nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+	nand_chip.oob_poi = nand_chip.buffers->databuf + mtd->writesize;
 	/* setup flash layout (does not scan as we override that) */
-	mtd.size = nand_chip.chipsize;
-	nand_chip.scan_bbt(&mtd);
+	mtd->size = nand_chip.chipsize;
+	nand_chip.scan_bbt(mtd);
 
-	printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+	printf("%llu MiB\n", (mtd->size / (1024 * 1024)));
 	return 0;
 }
 
@@ -180,20 +180,20 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 
 	if (mxs_nand_init())
 		return -ENODEV;
-	chip = mtd.priv;
+	chip = mtd_to_nand(mtd);
 	page = offs >> chip->page_shift;
-	nand_page_per_block = mtd.erasesize / mtd.writesize;
+	nand_page_per_block = mtd->erasesize / mtd->writesize;
 
 	debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
 
-	size = roundup(size, mtd.writesize);
+	size = roundup(size, mtd->writesize);
 	while (sz < size) {
-		if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+		if (mxs_read_page_ecc(mtd, buf, page) < 0)
 			return -1;
-		sz += mtd.writesize;
-		offs += mtd.writesize;
+		sz += mtd->writesize;
+		offs += mtd->writesize;
 		page++;
-		buf += mtd.writesize;
+		buf += mtd->writesize;
 
 		/*
 		 * Check if we have crossed a block boundary, and if so
@@ -204,10 +204,10 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
 			 * Yes, new block. See if this block is good. If not,
 			 * loop until we find a good block.
 			 */
-			while (is_badblock(&mtd, offs, 1)) {
+			while (is_badblock(mtd, offs, 1)) {
 				page = page + nand_page_per_block;
 				/* Check i we've reached the end of flash. */
-				if (page >= mtd.size >> chip->page_shift)
+				if (page >= mtd->size >> chip->page_shift)
 					return -ENOMEM;
 			}
 		}
diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c
index 8f0a9210ec..05512412b9 100644
--- a/drivers/mtd/nand/nand.c
+++ b/drivers/mtd/nand/nand.c
@@ -9,6 +9,7 @@
 #include <common.h>
 #include <nand.h>
 #include <errno.h>
+#include <linux/mtd/concat.h>
 
 #ifndef CONFIG_SYS_NAND_BASE_LIST
 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
@@ -19,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 int nand_curr_device = -1;
 
 
-nand_info_t nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
 
 #ifndef CONFIG_SYS_NAND_SELF_INIT
 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
@@ -30,15 +31,25 @@ static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
 
 static unsigned long total_nand_size; /* in kiB */
 
-/* Register an initialized NAND mtd device with the U-Boot NAND command. */
-int nand_register(int devnum)
+int nand_mtd_to_devnum(struct mtd_info *mtd)
 {
-	struct mtd_info *mtd;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(nand_info); i++) {
+		if (mtd && nand_info[i] == mtd)
+			return i;
+	}
+
+	return -ENODEV;
+}
 
+/* Register an initialized NAND mtd device with the U-Boot NAND command. */
+int nand_register(int devnum, struct mtd_info *mtd)
+{
 	if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
 		return -EINVAL;
 
-	mtd = &nand_info[devnum];
+	nand_info[devnum] = mtd;
 
 	sprintf(dev_name[devnum], "nand%d", devnum);
 	mtd->name = dev_name[devnum];
@@ -62,15 +73,14 @@ int nand_register(int devnum)
 #ifndef CONFIG_SYS_NAND_SELF_INIT
 static void nand_init_chip(int i)
 {
-	struct mtd_info *mtd = &nand_info[i];
 	struct nand_chip *nand = &nand_chip[i];
+	struct mtd_info *mtd = nand_to_mtd(nand);
 	ulong base_addr = base_address[i];
 	int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
 
 	if (maxchips < 1)
 		maxchips = 1;
 
-	mtd->priv = nand;
 	nand->IO_ADDR_R = nand->IO_ADDR_W = (void  __iomem *)base_addr;
 
 	if (board_nand_init(nand))
@@ -79,7 +89,45 @@ static void nand_init_chip(int i)
 	if (nand_scan(mtd, maxchips))
 		return;
 
-	nand_register(i);
+	nand_register(i, mtd);
+}
+#endif
+
+#ifdef CONFIG_MTD_CONCAT
+static void create_mtd_concat(void)
+{
+	struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE];
+	int nand_devices_found = 0;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
+		if (nand_info[i] != NULL) {
+			nand_info_list[nand_devices_found] = nand_info[i];
+			nand_devices_found++;
+		}
+	}
+	if (nand_devices_found > 1) {
+		struct mtd_info *mtd;
+		char c_mtd_name[16];
+
+		/*
+		 * We detected multiple devices. Concatenate them together.
+		 */
+		sprintf(c_mtd_name, "nand%d", nand_devices_found);
+		mtd = mtd_concat_create(nand_info_list, nand_devices_found,
+					c_mtd_name);
+
+		if (mtd == NULL)
+			return;
+
+		nand_register(nand_devices_found, mtd);
+	}
+
+	return;
+}
+#else
+static void create_mtd_concat(void)
+{
 }
 #endif
 
@@ -100,6 +148,9 @@ void nand_init(void)
 	/*
 	 * Select the chip in the board/cpu specific driver
 	 */
-	board_nand_select_device(nand_info[nand_curr_device].priv, nand_curr_device);
+	board_nand_select_device(mtd_to_nand(nand_info[nand_curr_device]),
+				 nand_curr_device);
 #endif
+
+	create_mtd_concat();
 }
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 9e8fc1ffe2..74c563c495 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nand.c
- *
  *  Overview:
  *   This is the generic MTD driver for NAND flash devices. It should be
  *   capable of working with almost all NAND chips currently available.
@@ -45,8 +43,6 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
-static bool is_module_text_address(unsigned long addr) {return 0;}
-
 /* Define default oob placement schemes for large and small page devices */
 static struct nand_ecclayout nand_oob_8 = {
 	.eccbytes = 3,
@@ -105,7 +101,7 @@ DEFINE_LED_TRIGGER(nand_led_trigger);
 static int check_offs_len(struct mtd_info *mtd,
 					loff_t ofs, uint64_t len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret = 0;
 
 	/* Start address must align on block boundary */
@@ -131,7 +127,7 @@ static int check_offs_len(struct mtd_info *mtd,
  */
 static void nand_release_device(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* De-select the NAND device */
 	chip->select_chip(mtd, -1);
@@ -145,7 +141,7 @@ static void nand_release_device(struct mtd_info *mtd)
  */
 uint8_t nand_read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return readb(chip->IO_ADDR_R);
 }
 
@@ -158,7 +154,7 @@ uint8_t nand_read_byte(struct mtd_info *mtd)
  */
 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 }
 
@@ -170,7 +166,7 @@ static uint8_t nand_read_byte16(struct mtd_info *mtd)
  */
 static u16 nand_read_word(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	return readw(chip->IO_ADDR_R);
 }
 
@@ -183,7 +179,7 @@ static u16 nand_read_word(struct mtd_info *mtd)
  */
 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	switch (chipnr) {
 	case -1:
@@ -206,7 +202,7 @@ static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  */
 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	chip->write_buf(mtd, &byte, 1);
 }
@@ -220,7 +216,7 @@ static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  */
 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint16_t word = byte;
 
 	/*
@@ -287,7 +283,7 @@ static void iowrite16_rep(void *addr, void *buf, int len)
  */
 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	iowrite8_rep(chip->IO_ADDR_W, buf, len);
 }
@@ -302,7 +298,7 @@ void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  */
 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	ioread8_rep(chip->IO_ADDR_R, buf, len);
 }
@@ -317,7 +313,7 @@ void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  */
 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 *p = (u16 *) buf;
 
 	iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
@@ -333,7 +329,7 @@ void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  */
 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 *p = (u16 *) buf;
 
 	ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
@@ -343,14 +339,13 @@ void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  * @mtd: MTD device structure
  * @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
  *
  * Check, if the block is bad.
  */
-static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
 {
-	int page, chipnr, res = 0, i = 0;
-	struct nand_chip *chip = mtd->priv;
+	int page, res = 0, i = 0;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	u16 bad;
 
 	if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
@@ -358,15 +353,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 
 	page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 
-	if (getchip) {
-		chipnr = (int)(ofs >> chip->chip_shift);
-
-		nand_get_device(mtd, FL_READING);
-
-		/* Select the NAND device */
-		chip->select_chip(mtd, chipnr);
-	}
-
 	do {
 		if (chip->options & NAND_BUSWIDTH_16) {
 			chip->cmdfunc(mtd, NAND_CMD_READOOB,
@@ -391,11 +377,6 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 		i++;
 	} while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 
-	if (getchip) {
-		chip->select_chip(mtd, -1);
-		nand_release_device(mtd);
-	}
-
 	return res;
 }
 
@@ -410,7 +391,7 @@ static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
  */
 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_oob_ops ops;
 	uint8_t buf[2] = { 0, 0 };
 	int ret = 0, res, i = 0;
@@ -460,7 +441,7 @@ static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 */
 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int res, ret = 0;
 
 	if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
@@ -501,7 +482,7 @@ static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  */
 static int nand_check_wp(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* Broken xD cards report WP despite being writable */
 	if (chip->options & NAND_BROKEN_XD)
@@ -521,7 +502,7 @@ static int nand_check_wp(struct mtd_info *mtd)
  */
 static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (!chip->bbt)
 		return 0;
@@ -533,16 +514,14 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  * @mtd: MTD device structure
  * @ofs: offset from device start
- * @getchip: 0, if the chip is already selected
  * @allowbbt: 1, if its allowed to access the bbt area
  *
  * Check, if the block is bad. Either by reading the bad block table or
  * calling of the scan function.
  */
-static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
-			       int allowbbt)
+static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (!(chip->options & NAND_SKIP_BBTSCAN) &&
 	    !(chip->options & NAND_BBT_SCANNED)) {
@@ -551,17 +530,22 @@ static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 	}
 
 	if (!chip->bbt)
-		return chip->block_bad(mtd, ofs, getchip);
+		return chip->block_bad(mtd, ofs);
 
 	/* Return info from the table */
 	return nand_isbad_bbt(mtd, ofs, allowbbt);
 }
 
-/* Wait for the ready pin, after a command. The timeout is caught later. */
+/**
+ * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
+ * @mtd: MTD device structure
+ *
+ * Wait for the ready pin after a command, and warn if a timeout occurs.
+ */
 void nand_wait_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
 	u32 time_start;
 
 	time_start = get_timer(0);
@@ -571,6 +555,9 @@ void nand_wait_ready(struct mtd_info *mtd)
 			if (chip->dev_ready(mtd))
 				break;
 	}
+
+	if (!chip->dev_ready(mtd))
+		pr_warn("timeout while waiting for chip to become ready\n");
 }
 EXPORT_SYMBOL_GPL(nand_wait_ready);
 
@@ -583,7 +570,7 @@ EXPORT_SYMBOL_GPL(nand_wait_ready);
  */
 static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	u32 time_start;
 
 	timeo = (CONFIG_SYS_HZ * timeo) / 1000;
@@ -608,7 +595,7 @@ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
 static void nand_command(struct mtd_info *mtd, unsigned int command,
 			 int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 	int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 
 	/* Write out the command to the device */
@@ -711,7 +698,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 			    int column, int page_addr)
 {
-	register struct nand_chip *chip = mtd->priv;
+	register struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* Emulate NAND_CMD_READOOB */
 	if (command == NAND_CMD_READOOB) {
@@ -835,7 +822,7 @@ static void panic_nand_get_device(struct nand_chip *chip,
 static int
 nand_get_device(struct mtd_info *mtd, int new_state)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	chip->state = new_state;
 	return 0;
 }
@@ -871,15 +858,13 @@ static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  * @mtd: MTD device structure
  * @chip: NAND chip structure
  *
- * Wait for command done. This applies to erase and program only. Erase can
- * take up to 400ms and program up to 20ms according to general NAND and
- * SmartMedia specs.
+ * Wait for command done. This applies to erase and program only.
  */
 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 {
 
-	int status, state = chip->state;
-	unsigned long timeo = (state == FL_ERASING ? 400 : 20);
+	int status;
+	unsigned long timeo = 400;
 
 	led_trigger_event(nand_led_trigger, LED_FULL);
 
@@ -912,6 +897,135 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	return status;
 }
 
+#define BITS_PER_BYTE 8
+
+/**
+ * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
+ * @buf: buffer to test
+ * @len: buffer length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a buffer contains only 0xff, which means the underlying region
+ * has been erased and is ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region is not erased.
+ * Note: The logic of this function has been extracted from the memweight
+ * implementation, except that nand_check_erased_buf function exit before
+ * testing the whole buffer if the number of bitflips exceed the
+ * bitflips_threshold value.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold.
+ */
+static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
+{
+	const unsigned char *bitmap = buf;
+	int bitflips = 0;
+	int weight;
+
+	for (; len && ((uintptr_t)bitmap) % sizeof(long);
+	     len--, bitmap++) {
+		weight = hweight8(*bitmap);
+		bitflips += BITS_PER_BYTE - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	for (; len >= 4; len -= 4, bitmap += 4) {
+		weight = hweight32(*((u32 *)bitmap));
+		bitflips += 32 - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	for (; len > 0; len--, bitmap++) {
+		weight = hweight8(*bitmap);
+		bitflips += BITS_PER_BYTE - weight;
+		if (unlikely(bitflips > bitflips_threshold))
+			return -EBADMSG;
+	}
+
+	return bitflips;
+}
+
+/**
+ * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
+ *				 0xff data
+ * @data: data buffer to test
+ * @datalen: data length
+ * @ecc: ECC buffer
+ * @ecclen: ECC length
+ * @extraoob: extra OOB buffer
+ * @extraooblen: extra OOB length
+ * @bitflips_threshold: maximum number of bitflips
+ *
+ * Check if a data buffer and its associated ECC and OOB data contains only
+ * 0xff pattern, which means the underlying region has been erased and is
+ * ready to be programmed.
+ * The bitflips_threshold specify the maximum number of bitflips before
+ * considering the region as not erased.
+ *
+ * Note:
+ * 1/ ECC algorithms are working on pre-defined block sizes which are usually
+ *    different from the NAND page size. When fixing bitflips, ECC engines will
+ *    report the number of errors per chunk, and the NAND core infrastructure
+ *    expect you to return the maximum number of bitflips for the whole page.
+ *    This is why you should always use this function on a single chunk and
+ *    not on the whole page. After checking each chunk you should update your
+ *    max_bitflips value accordingly.
+ * 2/ When checking for bitflips in erased pages you should not only check
+ *    the payload data but also their associated ECC data, because a user might
+ *    have programmed almost all bits to 1 but a few. In this case, we
+ *    shouldn't consider the chunk as erased, and checking ECC bytes prevent
+ *    this case.
+ * 3/ The extraoob argument is optional, and should be used if some of your OOB
+ *    data are protected by the ECC engine.
+ *    It could also be used if you support subpages and want to attach some
+ *    extra OOB data to an ECC chunk.
+ *
+ * Returns a positive number of bitflips less than or equal to
+ * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
+ * threshold. In case of success, the passed buffers are filled with 0xff.
+ */
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+				void *ecc, int ecclen,
+				void *extraoob, int extraooblen,
+				int bitflips_threshold)
+{
+	int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
+
+	data_bitflips = nand_check_erased_buf(data, datalen,
+					      bitflips_threshold);
+	if (data_bitflips < 0)
+		return data_bitflips;
+
+	bitflips_threshold -= data_bitflips;
+
+	ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
+	if (ecc_bitflips < 0)
+		return ecc_bitflips;
+
+	bitflips_threshold -= ecc_bitflips;
+
+	extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
+						  bitflips_threshold);
+	if (extraoob_bitflips < 0)
+		return extraoob_bitflips;
+
+	if (data_bitflips)
+		memset(data, 0xff, datalen);
+
+	if (ecc_bitflips)
+		memset(ecc, 0xff, ecclen);
+
+	if (extraoob_bitflips)
+		memset(extraoob, 0xff, extraooblen);
+
+	return data_bitflips + ecc_bitflips + extraoob_bitflips;
+}
+EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
+
 /**
  * nand_read_page_raw - [INTERN] read raw page data without ecc
  * @mtd: mtd info structure
@@ -1103,6 +1217,16 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 
 		stat = chip->ecc.correct(mtd, p,
 			&chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+						&chip->buffers->ecccode[i],
+						chip->ecc.bytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1152,6 +1276,15 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 		int stat;
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, eccsize,
+						&ecc_code[i], eccbytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1204,6 +1337,15 @@ static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
 		chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 
 		stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, eccsize,
+						&ecc_code[i], eccbytes,
+						NULL, 0,
+						chip->ecc.strength);
+		}
+
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
 		} else {
@@ -1231,6 +1373,7 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
 	int eccsteps = chip->ecc.steps;
+	int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 	uint8_t *p = buf;
 	uint8_t *oob = chip->oob_poi;
 	unsigned int max_bitflips = 0;
@@ -1250,19 +1393,29 @@ static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 		chip->read_buf(mtd, oob, eccbytes);
 		stat = chip->ecc.correct(mtd, p, oob, NULL);
 
-		if (stat < 0) {
-			mtd->ecc_stats.failed++;
-		} else {
-			mtd->ecc_stats.corrected += stat;
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
-		}
-
 		oob += eccbytes;
 
 		if (chip->ecc.postpad) {
 			chip->read_buf(mtd, oob, chip->ecc.postpad);
 			oob += chip->ecc.postpad;
 		}
+
+		if (stat == -EBADMSG &&
+		    (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
+			/* check for empty pages with bitflips */
+			stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
+							   oob - eccpadbytes,
+							   eccpadbytes,
+							   NULL, 0,
+							   chip->ecc.strength);
+		}
+
+		if (stat < 0) {
+			mtd->ecc_stats.failed++;
+		} else {
+			mtd->ecc_stats.corrected += stat;
+			max_bitflips = max_t(unsigned int, max_bitflips, stat);
+		}
 	}
 
 	/* Calculate remaining oob bytes */
@@ -1332,7 +1485,7 @@ static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  */
 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	pr_debug("setting READ RETRY mode %d\n", retry_mode);
 
@@ -1357,12 +1510,11 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
 	int chipnr, page, realpage, col, bytes, aligned, oob_required;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int ret = 0;
 	uint32_t readlen = ops->len;
 	uint32_t oobreadlen = ops->ooblen;
-	uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
-		mtd->oobavail : mtd->oobsize;
+	uint32_t max_oobsize = mtd_oobavail(mtd, ops);
 
 	uint8_t *bufpoi, *oob, *buf;
 	int use_bufpoi;
@@ -1700,7 +1852,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 			    struct mtd_oob_ops *ops)
 {
 	int page, realpage, chipnr;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_ecc_stats stats;
 	int readlen = ops->ooblen;
 	int len;
@@ -1712,10 +1864,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
 
 	stats = mtd->ecc_stats;
 
-	if (ops->mode == MTD_OPS_AUTO_OOB)
-		len = chip->ecc.layout->oobavail;
-	else
-		len = mtd->oobsize;
+	len = mtd_oobavail(mtd, ops);
 
 	if (unlikely(ops->ooboffs >= len)) {
 		pr_debug("%s: attempt to start read outside oob\n",
@@ -1840,11 +1989,12 @@ out:
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * Not for syndrome calculating ECC controllers, which use a special oob layout.
  */
 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
-				const uint8_t *buf, int oob_required)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	if (oob_required)
@@ -1859,12 +2009,14 @@ static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * We need a special oob layout and handling even when ECC isn't checked.
  */
 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
 					struct nand_chip *chip,
-					const uint8_t *buf, int oob_required)
+					const uint8_t *buf, int oob_required,
+					int page)
 {
 	int eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1901,9 +2053,11 @@ static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf, int oob_required)
+				 const uint8_t *buf, int oob_required,
+				 int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1919,7 +2073,7 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 	for (i = 0; i < chip->ecc.total; i++)
 		chip->oob_poi[eccpos[i]] = ecc_calc[i];
 
-	return chip->ecc.write_page_raw(mtd, chip, buf, 1);
+	return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
 }
 
 /**
@@ -1928,9 +2082,11 @@ static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
-				  const uint8_t *buf, int oob_required)
+				  const uint8_t *buf, int oob_required,
+				  int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -1962,11 +2118,12 @@ static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  * @data_len:	data length
  * @buf:	data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  */
 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
 				struct nand_chip *chip, uint32_t offset,
 				uint32_t data_len, const uint8_t *buf,
-				int oob_required)
+				int oob_required, int page)
 {
 	uint8_t *oob_buf  = chip->oob_poi;
 	uint8_t *ecc_calc = chip->buffers->ecccalc;
@@ -2021,13 +2178,15 @@ static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  * @chip: nand chip info structure
  * @buf: data buffer
  * @oob_required: must write chip->oob_poi to OOB
+ * @page: page number to write
  *
  * The hw generator calculates the error syndrome automatically. Therefore we
  * need a special oob layout and handling.
  */
 static int nand_write_page_syndrome(struct mtd_info *mtd,
 				    struct nand_chip *chip,
-				    const uint8_t *buf, int oob_required)
+				    const uint8_t *buf, int oob_required,
+				    int page)
 {
 	int i, eccsize = chip->ecc.size;
 	int eccbytes = chip->ecc.bytes;
@@ -2091,12 +2250,13 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 
 	if (unlikely(raw))
 		status = chip->ecc.write_page_raw(mtd, chip, buf,
-							oob_required);
+						  oob_required, page);
 	else if (subpage)
 		status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
-							 buf, oob_required);
+						 buf, oob_required, page);
 	else
-		status = chip->ecc.write_page(mtd, chip, buf, oob_required);
+		status = chip->ecc.write_page(mtd, chip, buf, oob_required,
+					      page);
 
 	if (status < 0)
 		return status;
@@ -2139,7 +2299,7 @@ static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
 			      struct mtd_oob_ops *ops)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/*
 	 * Initialise to all 0xFF, to avoid the possibility of left over OOB
@@ -2199,12 +2359,11 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
 	int chipnr, realpage, page, blockmask, column;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint32_t writelen = ops->len;
 
 	uint32_t oobwritelen = ops->ooblen;
-	uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
-				mtd->oobavail : mtd->oobsize;
+	uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
 
 	uint8_t *oob = ops->oobbuf;
 	uint8_t *buf = ops->datbuf;
@@ -2328,7 +2487,7 @@ err_out:
 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
 			    size_t *retlen, const uint8_t *buf)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct mtd_oob_ops ops;
 	int ret;
 
@@ -2388,15 +2547,12 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 			     struct mtd_oob_ops *ops)
 {
 	int chipnr, page, status, len;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	pr_debug("%s: to = 0x%08x, len = %i\n",
 			 __func__, (unsigned int)to, (int)ops->ooblen);
 
-	if (ops->mode == MTD_OPS_AUTO_OOB)
-		len = chip->ecc.layout->oobavail;
-	else
-		len = mtd->oobsize;
+	len = mtd_oobavail(mtd, ops);
 
 	/* Do not allow write past end of page */
 	if ((ops->ooboffs + ops->ooblen) > len) {
@@ -2513,7 +2669,7 @@ out:
  */
 static int single_erase(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	/* Send commands to erase a block */
 	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
 	chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
@@ -2545,7 +2701,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 		    int allowbbt)
 {
 	int page, status, pages_per_block, ret, chipnr;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	loff_t len;
 
 	pr_debug("%s: start = 0x%012llx, len = %llu\n",
@@ -2586,7 +2742,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 
 		/* Check if we have a bad block, we do not erase bad blocks! */
 		if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
-					chip->page_shift, 0, allowbbt)) {
+					chip->page_shift, allowbbt)) {
 			pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
 				    __func__, page);
 			instr->state = MTD_ERASE_FAILED;
@@ -2673,7 +2829,20 @@ static void nand_sync(struct mtd_info *mtd)
  */
 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
 {
-	return nand_block_checkbad(mtd, offs, 1, 0);
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	int chipnr = (int)(offs >> chip->chip_shift);
+	int ret;
+
+	/* Select the NAND device */
+	nand_get_device(mtd, FL_READING);
+	chip->select_chip(mtd, chipnr);
+
+	ret = nand_block_checkbad(mtd, offs, 0);
+
+	chip->select_chip(mtd, -1);
+	nand_release_device(mtd);
+
+	return ret;
 }
 
 /**
@@ -2745,9 +2914,6 @@ static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EINVAL;
 #endif
 
-	/* clear the sub feature parameters */
-	memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
-
 	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
 	for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
 		*subfeature_param++ = chip->read_byte(mtd);
@@ -2908,7 +3074,7 @@ ext_out:
 
 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
 
 	return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
@@ -3480,7 +3646,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 			if (find_full_id_nand(mtd, chip, type, id_data, &busw))
 				goto ident_done;
 		} else if (*dev_id == type->dev_id) {
-				break;
+			break;
 		}
 	}
 
@@ -3503,10 +3669,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 
 	chip->chipsize = (uint64_t)type->chipsize << 20;
 
-	if (!type->pagesize && chip->init_size) {
-		/* Set the pagesize, oobsize, erasesize by the driver */
-		busw = chip->init_size(mtd, chip, id_data);
-	} else if (!type->pagesize) {
+	if (!type->pagesize) {
 		/* Decode parameters from extended ID */
 		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
@@ -3610,13 +3773,12 @@ ident_done:
  * This is the first phase of the normal nand_scan() function. It reads the
  * flash ID and sets up MTD fields accordingly.
  *
- * The mtd->owner field must be set to the module of the caller.
  */
 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
 		    struct nand_flash_dev *table)
 {
 	int i, nand_maf_id, nand_dev_id;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_flash_dev *type;
 
 	/* Set the default functions */
@@ -3680,7 +3842,7 @@ EXPORT_SYMBOL(nand_scan_ident);
  */
 static bool nand_ecc_strength_good(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int corr, ds_corr;
 
@@ -3709,7 +3871,7 @@ static bool nand_ecc_strength_good(struct mtd_info *mtd)
 int nand_scan_tail(struct mtd_info *mtd)
 {
 	int i;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	struct nand_buffers *nbuf;
 
@@ -3786,7 +3948,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 			ecc->write_oob = nand_write_oob_std;
 		if (!ecc->read_subpage)
 			ecc->read_subpage = nand_read_subpage;
-		if (!ecc->write_subpage)
+		if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
 			ecc->write_subpage = nand_write_subpage_hwecc;
 
 	case NAND_ECC_HW_SYNDROME:
@@ -3864,10 +4026,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 		}
 
 		/* See nand_bch_init() for details. */
-		ecc->bytes = DIV_ROUND_UP(
-				ecc->strength * fls(8 * ecc->size), 8);
-		ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
-					       &ecc->layout);
+		ecc->bytes = 0;
+		ecc->priv = nand_bch_init(mtd);
 		if (!ecc->priv) {
 			pr_warn("BCH ECC initialization failed!\n");
 			BUG();
@@ -3902,11 +4062,11 @@ int nand_scan_tail(struct mtd_info *mtd)
 	 * The number of bytes available for a client to place data into
 	 * the out of band area.
 	 */
-	ecc->layout->oobavail = 0;
-	for (i = 0; ecc->layout->oobfree[i].length
-			&& i < ARRAY_SIZE(ecc->layout->oobfree); i++)
-		ecc->layout->oobavail += ecc->layout->oobfree[i].length;
-	mtd->oobavail = ecc->layout->oobavail;
+	mtd->oobavail = 0;
+	if (ecc->layout) {
+		for (i = 0; ecc->layout->oobfree[i].length; i++)
+			mtd->oobavail += ecc->layout->oobfree[i].length;
+	}
 
 	/* ECC sanity check: warn if it's too weak */
 	if (!nand_ecc_strength_good(mtd))
@@ -3991,18 +4151,6 @@ int nand_scan_tail(struct mtd_info *mtd)
 }
 EXPORT_SYMBOL(nand_scan_tail);
 
-/*
- * is_module_text_address() isn't exported, and it's mostly a pointless
- * test if this is a module _anyway_ -- they'd have to try _really_ hard
- * to call us from in-kernel code if the core NAND support is modular.
- */
-#ifdef MODULE
-#define caller_is_module() (1)
-#else
-#define caller_is_module() \
-	is_module_text_address((unsigned long)__builtin_return_address(0))
-#endif
-
 /**
  * nand_scan - [NAND Interface] Scan for the NAND device
  * @mtd: MTD device structure
@@ -4010,19 +4158,12 @@ EXPORT_SYMBOL(nand_scan_tail);
  *
  * This fills out all the uninitialized function pointers with the defaults.
  * The flash ID is read and the mtd/chip structures are filled with the
- * appropriate values. The mtd->owner field must be set to the module of the
- * caller.
+ * appropriate values.
  */
 int nand_scan(struct mtd_info *mtd, int maxchips)
 {
 	int ret;
 
-	/* Many callers got this wrong, so check for it for a while... */
-	if (!mtd->owner && caller_is_module()) {
-		pr_crit("%s called with NULL mtd->owner!\n", __func__);
-		BUG();
-	}
-
 	ret = nand_scan_ident(mtd, maxchips, NULL);
 	if (!ret)
 		ret = nand_scan_tail(mtd);
@@ -4030,9 +4171,6 @@ int nand_scan(struct mtd_info *mtd, int maxchips)
 }
 EXPORT_SYMBOL(nand_scan);
 
-module_init(nand_base_init);
-module_exit(nand_base_exit);
-
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 00f28a4157..74c4c9a3c8 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nand_bbt.c
- *
  *  Overview:
  *   Bad block table support for the NAND driver
  *
@@ -65,7 +63,6 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/bbm.h>
 #include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
 #include <linux/bitops.h>
 #include <linux/string.h>
 
@@ -173,7 +170,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
 		struct nand_bbt_descr *td, int offs)
 {
 	int res, ret = 0, i, j, act = 0;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	size_t retlen, len, totlen;
 	loff_t from;
 	int bits = td->options & NAND_BBT_NRBITS_MSK;
@@ -264,7 +261,7 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num,
  */
 static int read_abs_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td, int chip)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int res = 0, i;
 
 	if (td->options & NAND_BBT_PERCHIP) {
@@ -389,7 +386,7 @@ static u32 bbt_get_ver_offs(struct mtd_info *mtd, struct nand_bbt_descr *td)
 static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
 			  struct nand_bbt_descr *td, struct nand_bbt_descr *md)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	/* Read the primary version, if available */
 	if (td->options & NAND_BBT_VERSION) {
@@ -455,7 +452,7 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
 static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
 	struct nand_bbt_descr *bd, int chip)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, numblocks, numpages;
 	int startblock;
 	loff_t from;
@@ -524,7 +521,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
  */
 static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *td)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, chips;
 	int startblock, block, dir;
 	int scanlen = mtd->writesize + mtd->oobsize;
@@ -619,7 +616,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		     struct nand_bbt_descr *td, struct nand_bbt_descr *md,
 		     int chipsel)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	struct erase_info einfo;
 	int i, res, chip = 0;
 	int bits, startblock, dir, page, offs, numblocks, sft, sftmsk;
@@ -718,7 +715,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
 		/* Must we save the block contents? */
 		if (td->options & NAND_BBT_SAVECONTENT) {
 			/* Make it block aligned */
-			to &= ~((loff_t)((1 << this->bbt_erase_shift) - 1));
+			to &= ~(((loff_t)1 << this->bbt_erase_shift) - 1);
 			len = 1 << this->bbt_erase_shift;
 			res = mtd_read(mtd, to, len, &retlen, buf);
 			if (res < 0) {
@@ -820,7 +817,7 @@ static int write_bbt(struct mtd_info *mtd, uint8_t *buf,
  */
 static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	return create_bbt(mtd, this->buffers->databuf, bd, -1);
 }
@@ -839,7 +836,7 @@ static inline int nand_memory_bbt(struct mtd_info *mtd, struct nand_bbt_descr *b
 static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr *bd)
 {
 	int i, chips, writeops, create, chipsel, res, res2;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 	struct nand_bbt_descr *rd, *rd2;
@@ -963,7 +960,7 @@ static int check_create(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_desc
  */
 static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int i, j, chips, block, nrblocks, update;
 	uint8_t oldval;
 
@@ -1023,7 +1020,7 @@ static void mark_bbt_region(struct mtd_info *mtd, struct nand_bbt_descr *td)
  */
 static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u32 pattern_len;
 	u32 bits;
 	u32 table_size;
@@ -1073,15 +1070,15 @@ static void verify_bbt_descr(struct mtd_info *mtd, struct nand_bbt_descr *bd)
  * The bad block table memory is allocated here. It must be freed by calling
  * the nand_free_bbt function.
  */
-int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
+static int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 {
-	struct nand_chip *this = mtd->priv;
-	int len, res = 0;
+	struct nand_chip *this = mtd_to_nand(mtd);
+	int len, res;
 	uint8_t *buf;
 	struct nand_bbt_descr *td = this->bbt_td;
 	struct nand_bbt_descr *md = this->bbt_md;
 
-	len = mtd->size >> (this->bbt_erase_shift + 2);
+	len = (mtd->size >> (this->bbt_erase_shift + 2)) ? : 1;
 	/*
 	 * Allocate memory (2bit per block) and clear the memory bad block
 	 * table.
@@ -1097,10 +1094,9 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	if (!td) {
 		if ((res = nand_memory_bbt(mtd, bd))) {
 			pr_err("nand_bbt: can't scan flash and build the RAM-based BBT\n");
-			kfree(this->bbt);
-			this->bbt = NULL;
+			goto err;
 		}
-		return res;
+		return 0;
 	}
 	verify_bbt_descr(mtd, td);
 	verify_bbt_descr(mtd, md);
@@ -1110,9 +1106,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	len += (len >> this->page_shift) * mtd->oobsize;
 	buf = vmalloc(len);
 	if (!buf) {
-		kfree(this->bbt);
-		this->bbt = NULL;
-		return -ENOMEM;
+		res = -ENOMEM;
+		goto err;
 	}
 
 	/* Is the bbt at a given page? */
@@ -1124,6 +1119,8 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 	}
 
 	res = check_create(mtd, buf, bd);
+	if (res)
+		goto err;
 
 	/* Prevent the bbt regions from erasing / writing */
 	mark_bbt_region(mtd, td);
@@ -1131,6 +1128,11 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
 		mark_bbt_region(mtd, md);
 
 	vfree(buf);
+	return 0;
+
+err:
+	kfree(this->bbt);
+	this->bbt = NULL;
 	return res;
 }
 
@@ -1143,7 +1145,7 @@ int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd)
  */
 static int nand_update_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int len, res = 0;
 	int chip, chipsel;
 	uint8_t *buf;
@@ -1277,7 +1279,7 @@ static int nand_create_badblock_pattern(struct nand_chip *this)
  */
 int nand_default_bbt(struct mtd_info *mtd)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int ret;
 
 	/* Is a flash based bad block table requested? */
@@ -1313,7 +1315,7 @@ int nand_default_bbt(struct mtd_info *mtd)
  */
 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block;
 
 	block = (int)(offs >> this->bbt_erase_shift);
@@ -1328,7 +1330,7 @@ int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs)
  */
 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block, res;
 
 	block = (int)(offs >> this->bbt_erase_shift);
@@ -1355,7 +1357,7 @@ int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt)
  */
 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int block, ret = 0;
 
 	block = (int)(offs >> this->bbt_erase_shift);
@@ -1369,5 +1371,3 @@ int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
 
 	return ret;
 }
-
-EXPORT_SYMBOL(nand_scan_bbt);
diff --git a/drivers/mtd/nand/nand_bch.c b/drivers/mtd/nand/nand_bch.c
index 35d2140dab..c14520380e 100644
--- a/drivers/mtd/nand/nand_bch.c
+++ b/drivers/mtd/nand/nand_bch.c
@@ -41,7 +41,7 @@ struct nand_bch_control {
 int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
 			   unsigned char *code)
 {
-	const struct nand_chip *chip = mtd->priv;
+	const struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_bch_control *nbc = chip->ecc.priv;
 	unsigned int i;
 
@@ -67,7 +67,7 @@ int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
 int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 			  unsigned char *read_ecc, unsigned char *calc_ecc)
 {
-	const struct nand_chip *chip = mtd->priv;
+	const struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_bch_control *nbc = chip->ecc.priv;
 	unsigned int *errloc = nbc->errloc;
 	int i, count;
@@ -86,7 +86,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 		}
 	} else if (count < 0) {
 		printk(KERN_ERR "ecc unrecoverable error\n");
-		count = -1;
+		count = -EBADMSG;
 	}
 	return count;
 }
@@ -94,9 +94,6 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 /**
  * nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
  * @mtd:	MTD block structure
- * @eccsize:	ecc block size in bytes
- * @eccbytes:	ecc length in bytes
- * @ecclayout:	output default layout
  *
  * Returns:
  *  a pointer to a new NAND BCH control structure, or NULL upon failure
@@ -110,14 +107,21 @@ int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
  * @eccsize = 512  (thus, m=13 is the smallest integer such that 2^m-1 > 512*8)
  * @eccbytes = 7   (7 bytes are required to store m*t = 13*4 = 52 bits)
  */
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
-	      struct nand_ecclayout **ecclayout)
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
 {
+	struct nand_chip *nand = mtd_to_nand(mtd);
 	unsigned int m, t, eccsteps, i;
-	struct nand_ecclayout *layout;
+	struct nand_ecclayout *layout = nand->ecc.layout;
 	struct nand_bch_control *nbc = NULL;
 	unsigned char *erased_page;
+	unsigned int eccsize = nand->ecc.size;
+	unsigned int eccbytes = nand->ecc.bytes;
+	unsigned int eccstrength = nand->ecc.strength;
+
+	if (!eccbytes && eccstrength) {
+		eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8);
+		nand->ecc.bytes = eccbytes;
+	}
 
 	if (!eccsize || !eccbytes) {
 		printk(KERN_WARNING "ecc parameters not supplied\n");
@@ -145,7 +149,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 	eccsteps = mtd->writesize/eccsize;
 
 	/* if no ecc placement scheme was provided, build one */
-	if (!*ecclayout) {
+	if (!layout) {
 
 		/* handle large page devices only */
 		if (mtd->oobsize < 64) {
@@ -171,7 +175,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 		layout->oobfree[0].offset = 2;
 		layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
 
-		*ecclayout = layout;
+		nand->ecc.layout = layout;
 	}
 
 	/* sanity checks */
@@ -179,7 +183,7 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 		printk(KERN_WARNING "eccsize %u is too large\n", eccsize);
 		goto fail;
 	}
-	if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) {
+	if (layout->eccbytes != (eccsteps*eccbytes)) {
 		printk(KERN_WARNING "invalid ecc layout\n");
 		goto fail;
 	}
@@ -203,6 +207,9 @@ nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
 	for (i = 0; i < eccbytes; i++)
 		nbc->eccmask[i] ^= 0xff;
 
+	if (!eccstrength)
+		nand->ecc.strength = (eccbytes * 8) / fls(8 * eccsize);
+
 	return nbc;
 fail:
 	nand_bch_free(nbc);
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index fdd00741dc..561d2cd63b 100644
--- a/drivers/mtd/nand/nand_ids.c
+++ b/drivers/mtd/nand/nand_ids.c
@@ -1,6 +1,4 @@
 /*
- *  drivers/mtd/nandids.c
- *
  *  Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -41,6 +39,10 @@ struct nand_flash_dev nand_flash_ids[] = {
 	 * listed by full ID. We list them first so that we can easily identify
 	 * the most specific match.
 	 */
+	{"TC58NVG0S3E 1G 3.3V 8-bit",
+		{ .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
+		  SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
+		  2 },
 	{"TC58NVG2S0F 4G 3.3V 8-bit",
 		{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
 		  SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
@@ -58,8 +60,8 @@ struct nand_flash_dev nand_flash_ids[] = {
 		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
 	{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
-		  SZ_8K, SZ_8K, SZ_2M, 0, 6, 640, NAND_ECC_INFO(40, SZ_1K),
-		  4 },
+		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+		  NAND_ECC_INFO(40, SZ_1K), 4 },
 
 	LEGACY_ID_NAND("NAND 4MiB 5V 8-bit",   0x6B, 4, SZ_8K, SP_OPTIONS),
 	LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c
index 37a0206ad6..335c3e3471 100644
--- a/drivers/mtd/nand/nand_plat.c
+++ b/drivers/mtd/nand/nand_plat.c
@@ -25,7 +25,7 @@
 
 static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	if (cmd == NAND_CMD_NONE)
 		return;
@@ -39,7 +39,7 @@ static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 #ifdef NAND_PLAT_DEV_READY
 static int plat_dev_ready(struct mtd_info *mtd)
 {
-	return NAND_PLAT_DEV_READY((struct nand_chip *)mtd->priv);
+	return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd));
 }
 #else
 # define plat_dev_ready NULL
diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c
index e69f66226d..b023e00313 100644
--- a/drivers/mtd/nand/nand_spl_simple.c
+++ b/drivers/mtd/nand/nand_spl_simple.c
@@ -11,7 +11,7 @@
 #include <linux/mtd/nand_ecc.h>
 
 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-static nand_info_t mtd;
+static struct mtd_info *mtd;
 static struct nand_chip nand_chip;
 
 #define ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
@@ -26,32 +26,32 @@ static struct nand_chip nand_chip;
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Begin command latch cycle */
-	this->cmd_ctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	this->cmd_ctrl(&mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-	this->cmd_ctrl(&mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
-	this->cmd_ctrl(&mtd, (page_addr >> 8) & 0xff,
+	this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+	this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
 		       NAND_CTRL_ALE); /* A[24:17] */
 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
 	/* One more address cycle for devices > 32MiB */
-	this->cmd_ctrl(&mtd, (page_addr >> 16) & 0x0f,
+	this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[28:25] */
 #endif
 	/* Latch in address */
-	this->cmd_ctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * Wait a while for the data to be ready
 	 */
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -63,12 +63,12 @@ static int nand_command(int block, int page, uint32_t offs,
 static int nand_command(int block, int page, uint32_t offs,
 	u8 cmd)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
 	void (*hwctrl)(struct mtd_info *mtd, int cmd,
 			unsigned int ctrl) = this->cmd_ctrl;
 
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	/* Emulate NAND_CMD_READOOB */
@@ -82,30 +82,30 @@ static int nand_command(int block, int page, uint32_t offs,
 		offs >>= 1;
 
 	/* Begin command latch cycle */
-	hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 	/* Set ALE and clear CLE to start address cycle */
 	/* Column address */
-	hwctrl(&mtd, offs & 0xff,
-		       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-	hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
+	hwctrl(mtd, offs & 0xff,
+		    NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
+	hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
 	/* Row address */
-	hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
-	hwctrl(&mtd, ((page_addr >> 8) & 0xff),
-		       NAND_CTRL_ALE); /* A[27:20] */
+	hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+	hwctrl(mtd, ((page_addr >> 8) & 0xff),
+		    NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
 	/* One more address cycle for devices > 128MiB */
-	hwctrl(&mtd, (page_addr >> 16) & 0x0f,
+	hwctrl(mtd, (page_addr >> 16) & 0x0f,
 		       NAND_CTRL_ALE); /* A[31:28] */
 #endif
 	/* Latch in address */
-	hwctrl(&mtd, NAND_CMD_READSTART,
-		       NAND_CTRL_CLE | NAND_CTRL_CHANGE);
-	hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_READSTART,
+		    NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+	hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 
 	/*
 	 * Wait a while for the data to be ready
 	 */
-	while (!this->dev_ready(&mtd))
+	while (!this->dev_ready(mtd))
 		;
 
 	return 0;
@@ -114,7 +114,7 @@ static int nand_command(int block, int page, uint32_t offs,
 
 static int nand_is_bad_block(int block)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char bb_data[2];
 
 	nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
@@ -124,11 +124,11 @@ static int nand_is_bad_block(int block)
 	 * Read one byte (or two if it's a 16 bit chip).
 	 */
 	if (this->options & NAND_BUSWIDTH_16) {
-		this->read_buf(&mtd, bb_data, 2);
+		this->read_buf(mtd, bb_data, 2);
 		if (bb_data[0] != 0xff || bb_data[1] != 0xff)
 			return 1;
 	} else {
-		this->read_buf(&mtd, bb_data, 1);
+		this->read_buf(mtd, bb_data, 1);
 		if (bb_data[0] != 0xff)
 			return 1;
 	}
@@ -139,7 +139,7 @@ static int nand_is_bad_block(int block)
 #if defined(CONFIG_SYS_NAND_HW_ECC_OOBFIRST)
 static int nand_read_page(int block, int page, uchar *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -150,7 +150,7 @@ static int nand_read_page(int block, int page, uchar *dst)
 	uint8_t *p = dst;
 
 	nand_command(block, page, 0, NAND_CMD_READOOB);
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 	nand_command(block, page, 0, NAND_CMD_READ0);
 
 	/* Pick the ECC bytes out of the oob data */
@@ -159,10 +159,10 @@ static int nand_read_page(int block, int page, uchar *dst)
 
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
-		this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -170,7 +170,7 @@ static int nand_read_page(int block, int page, uchar *dst)
 #else
 static int nand_read_page(int block, int page, void *dst)
 {
-	struct nand_chip *this = mtd.priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	u_char ecc_calc[ECCTOTAL];
 	u_char ecc_code[ECCTOTAL];
 	u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
@@ -184,11 +184,11 @@ static int nand_read_page(int block, int page, void *dst)
 
 	for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 		if (this->ecc.mode != NAND_ECC_SOFT)
-			this->ecc.hwctl(&mtd, NAND_ECC_READ);
-		this->read_buf(&mtd, p, eccsize);
-		this->ecc.calculate(&mtd, p, &ecc_calc[i]);
+			this->ecc.hwctl(mtd, NAND_ECC_READ);
+		this->read_buf(mtd, p, eccsize);
+		this->ecc.calculate(mtd, p, &ecc_calc[i]);
 	}
-	this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
+	this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
 
 	/* Pick the ECC bytes out of the oob data */
 	for (i = 0; i < ECCTOTAL; i++)
@@ -202,7 +202,7 @@ static int nand_read_page(int block, int page, void *dst)
 		 * from correct_data(). We just hope that all possible errors
 		 * are corrected by this routine.
 		 */
-		this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
+		this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 	}
 
 	return 0;
@@ -249,7 +249,7 @@ void nand_init(void)
 	/*
 	 * Init board specific nand support
 	 */
-	mtd.priv = &nand_chip;
+	mtd = &nand_chip.mtd;
 	nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
 		(void  __iomem *)CONFIG_SYS_NAND_BASE;
 	board_nand_init(&nand_chip);
@@ -262,12 +262,12 @@ void nand_init(void)
 #endif
 
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, 0);
+		nand_chip.select_chip(mtd, 0);
 }
 
 /* Unselect after operation */
 void nand_deselect(void)
 {
 	if (nand_chip.select_chip)
-		nand_chip.select_chip(&mtd, -1);
+		nand_chip.select_chip(mtd, -1);
 }
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 71285b6669..5bba66a728 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -42,25 +42,26 @@ typedef struct mtd_info		mtd_info_t;
  * nand_erase_opts: - erase NAND flash with support for various options
  *		      (jffs2 formatting)
  *
- * @param meminfo	NAND device to erase
+ * @param mtd		nand mtd instance to erase
  * @param opts		options,  @see struct nand_erase_options
  * @return		0 in case of success
  *
  * This code is ported from flash_eraseall.c from Linux mtd utils by
  * Arcom Control System Ltd.
  */
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
+int nand_erase_opts(struct mtd_info *mtd,
+		    const nand_erase_options_t *opts)
 {
 	struct jffs2_unknown_node cleanmarker;
 	erase_info_t erase;
 	unsigned long erase_length, erased_length; /* in blocks */
 	int result;
 	int percent_complete = -1;
-	const char *mtd_device = meminfo->name;
+	const char *mtd_device = mtd->name;
 	struct mtd_oob_ops oob_opts;
-	struct nand_chip *chip = meminfo->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
-	if ((opts->offset & (meminfo->erasesize - 1)) != 0) {
+	if ((opts->offset & (mtd->erasesize - 1)) != 0) {
 		printf("Attempt to erase non block-aligned data\n");
 		return -1;
 	}
@@ -68,11 +69,11 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 	memset(&erase, 0, sizeof(erase));
 	memset(&oob_opts, 0, sizeof(oob_opts));
 
-	erase.mtd = meminfo;
-	erase.len  = meminfo->erasesize;
+	erase.mtd = mtd;
+	erase.len = mtd->erasesize;
 	erase.addr = opts->offset;
-	erase_length = lldiv(opts->length + meminfo->erasesize - 1,
-			     meminfo->erasesize);
+	erase_length = lldiv(opts->length + mtd->erasesize - 1,
+			     mtd->erasesize);
 
 	cleanmarker.magic = cpu_to_je16(JFFS2_MAGIC_BITMASK);
 	cleanmarker.nodetype = cpu_to_je16(JFFS2_NODETYPE_CLEANMARKER);
@@ -97,7 +98,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 	for (erased_length = 0;
 	     erased_length < erase_length;
-	     erase.addr += meminfo->erasesize) {
+	     erase.addr += mtd->erasesize) {
 
 		WATCHDOG_RESET();
 
@@ -106,7 +107,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			return -EFBIG;
 		}
 		if (!opts->scrub) {
-			int ret = mtd_block_isbad(meminfo, erase.addr);
+			int ret = mtd_block_isbad(mtd, erase.addr);
 			if (ret > 0) {
 				if (!opts->quiet)
 					printf("\rSkipping bad block at  "
@@ -129,7 +130,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 
 		erased_length++;
 
-		result = mtd_erase(meminfo, &erase);
+		result = mtd_erase(mtd, &erase);
 		if (result != 0) {
 			printf("\n%s: MTD Erase failure: %d\n",
 			       mtd_device, result);
@@ -145,9 +146,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			ops.ooboffs = 0;
 			ops.mode = MTD_OPS_AUTO_OOB;
 
-			result = mtd_write_oob(meminfo,
-						    erase.addr,
-						    &ops);
+			result = mtd_write_oob(mtd, erase.addr, &ops);
 			if (result != 0) {
 				printf("\n%s: MTD writeoob failure: %d\n",
 				       mtd_device, result);
@@ -218,7 +217,7 @@ int nand_lock(struct mtd_info *mtd, int tight)
 {
 	int ret = 0;
 	int status;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* select the NAND device */
 	chip->select_chip(mtd, 0);
@@ -268,7 +267,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
 	int ret = 0;
 	int chipnr;
 	int page;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/* select the NAND device */
 	chipnr = (int)(offset >> chip->chip_shift);
@@ -303,7 +302,7 @@ int nand_get_lock_status(struct mtd_info *mtd, loff_t offset)
  * @param mtd		nand mtd instance
  * @param start		start byte address
  * @param length	number of bytes to unlock (must be a multiple of
- *			page size nand->writesize)
+ *			page size mtd->writesize)
  * @param allexcept	if set, unlock everything not selected
  *
  * @return		0 on success, -1 in case of error
@@ -315,7 +314,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
 	int chipnr;
 	int status;
 	int page;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	debug("nand_unlock%s: start: %08llx, length: %zd!\n",
 		allexcept ? " (allexcept)" : "", start, length);
@@ -399,7 +398,7 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
  * Check if there are any bad blocks, and whether length including bad
  * blocks fits into device
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @param length image length
  * @param used length of flash needed for the requested length
@@ -407,8 +406,8 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
  *         1 if the image fits, but there are bad blocks
  *        -1 if the image does not fit
  */
-static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
-		size_t *used)
+static int check_skip_len(struct mtd_info *mtd, loff_t offset, size_t length,
+			  size_t *used)
 {
 	size_t len_excl_bad = 0;
 	int ret = 0;
@@ -417,14 +416,14 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
 		size_t block_len, block_off;
 		loff_t block_start;
 
-		if (offset >= nand->size)
+		if (offset >= mtd->size)
 			return -1;
 
-		block_start = offset & ~(loff_t)(nand->erasesize - 1);
-		block_off = offset & (nand->erasesize - 1);
-		block_len = nand->erasesize - block_off;
+		block_start = offset & ~(loff_t)(mtd->erasesize - 1);
+		block_off = offset & (mtd->erasesize - 1);
+		block_len = mtd->erasesize - block_off;
 
-		if (!nand_block_isbad(nand, block_start))
+		if (!nand_block_isbad(mtd, block_start))
 			len_excl_bad += block_len;
 		else
 			ret = 1;
@@ -441,7 +440,7 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length,
 }
 
 #ifdef CONFIG_CMD_NAND_TRIMFFS
-static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
+static size_t drop_ffs(const struct mtd_info *mtd, const u_char *buf,
 			const size_t *len)
 {
 	size_t l = *len;
@@ -453,8 +452,8 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
 
 	/* The resulting length must be aligned to the minimum flash I/O size */
 	l = i + 1;
-	l = (l + nand->writesize - 1) / nand->writesize;
-	l *=  nand->writesize;
+	l = (l + mtd->writesize - 1) / mtd->writesize;
+	l *=  mtd->writesize;
 
 	/*
 	 * since the input length may be unaligned, prevent access past the end
@@ -471,16 +470,17 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf,
  * Reads page of NAND and verifies the contents and OOB against the
  * values in ops.
  *
- * @param nand		NAND device
+ * @param mtd		nand mtd instance
  * @param ops		MTD operations, including data to verify
  * @param ofs		offset in flash
  * @return		0 in case of success
  */
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+			 loff_t ofs)
 {
 	int rval;
 	struct mtd_oob_ops vops;
-	size_t verlen = nand->writesize + nand->oobsize;
+	size_t verlen = mtd->writesize + mtd->oobsize;
 
 	memcpy(&vops, ops, sizeof(vops));
 
@@ -489,9 +489,9 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
 	if (!vops.datbuf)
 		return -ENOMEM;
 
-	vops.oobbuf = vops.datbuf + nand->writesize;
+	vops.oobbuf = vops.datbuf + mtd->writesize;
 
-	rval = mtd_read_oob(nand, ofs, &vops);
+	rval = mtd_read_oob(mtd, ofs, &vops);
 	if (!rval)
 		rval = memcmp(ops->datbuf, vops.datbuf, vops.len);
 	if (!rval)
@@ -510,17 +510,17 @@ int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops, loff_t ofs)
  * the contents of a buffer.  The offset into the NAND must be
  * page-aligned, and the function doesn't handle skipping bad blocks.
  *
- * @param nand		NAND device
+ * @param mtd		nand mtd instance
  * @param ofs		offset in flash
  * @param len		buffer length
  * @param buf		buffer to read from
  * @return		0 in case of success
  */
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf)
 {
 	int rval = 0;
 	size_t verofs;
-	size_t verlen = nand->writesize;
+	size_t verlen = mtd->writesize;
 	uint8_t *verbuf = memalign(ARCH_DMA_MINALIGN, verlen);
 
 	if (!verbuf)
@@ -529,8 +529,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
 	/* Read the NAND back in page-size groups to limit malloc size */
 	for (verofs = ofs; verofs < ofs + len;
 	     verofs += verlen, buf += verlen) {
-		verlen = min(nand->writesize, (uint32_t)(ofs + len - verofs));
-		rval = nand_read(nand, verofs, &verlen, verbuf);
+		verlen = min(mtd->writesize, (uint32_t)(ofs + len - verofs));
+		rval = nand_read(mtd, verofs, &verlen, verbuf);
 		if (!rval || (rval == -EUCLEAN))
 			rval = memcmp(buf, verbuf, verlen);
 
@@ -558,7 +558,7 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
  * beyond the limit we are passed, length is set to 0 and actual is set
  * to the required length.
  *
- * @param nand  	NAND device
+ * @param mtd		nand mtd instance
  * @param offset	offset in flash
  * @param length	buffer length
  * @param actual	set to size required to write length worth of
@@ -569,8 +569,8 @@ int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf)
  * @param flags		flags modifying the behaviour of the write to NAND
  * @return		0 in case of success
  */
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		size_t *actual, loff_t lim, u_char *buffer, int flags)
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+			size_t *actual, loff_t lim, u_char *buffer, int flags)
 {
 	int rval = 0, blocksize;
 	size_t left_to_write = *length;
@@ -581,7 +581,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	if (actual)
 		*actual = 0;
 
-	blocksize = nand->erasesize;
+	blocksize = mtd->erasesize;
 
 	/*
 	 * nand_write() handles unaligned, partial page writes.
@@ -594,13 +594,13 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	 * you should only start a block skipping access at a
 	 * partition boundary).  So don't try to handle that.
 	 */
-	if ((offset & (nand->writesize - 1)) != 0) {
+	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf("Attempt to write non page-aligned data\n");
 		*length = 0;
 		return -EINVAL;
 	}
 
-	need_skip = check_skip_len(nand, offset, *length, &used_for_write);
+	need_skip = check_skip_len(mtd, offset, *length, &used_for_write);
 
 	if (actual)
 		*actual = used_for_write;
@@ -618,10 +618,10 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	if (!need_skip && !(flags & WITH_DROP_FFS)) {
-		rval = nand_write(nand, offset, length, buffer);
+		rval = nand_write(mtd, offset, length, buffer);
 
 		if ((flags & WITH_WR_VERIFY) && !rval)
-			rval = nand_verify(nand, offset, *length, buffer);
+			rval = nand_verify(mtd, offset, *length, buffer);
 
 		if (rval == 0)
 			return 0;
@@ -633,15 +633,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	while (left_to_write > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t block_offset = offset & (mtd->erasesize - 1);
 		size_t write_size, truncated_write_size;
 
 		WATCHDOG_RESET();
 
-		if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+		if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
 			printf("Skip bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
+				offset & ~(mtd->erasesize - 1));
+			offset += mtd->erasesize - block_offset;
 			continue;
 		}
 
@@ -653,15 +653,15 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		truncated_write_size = write_size;
 #ifdef CONFIG_CMD_NAND_TRIMFFS
 		if (flags & WITH_DROP_FFS)
-			truncated_write_size = drop_ffs(nand, p_buffer,
+			truncated_write_size = drop_ffs(mtd, p_buffer,
 					&write_size);
 #endif
 
-		rval = nand_write(nand, offset, &truncated_write_size,
+		rval = nand_write(mtd, offset, &truncated_write_size,
 				p_buffer);
 
 		if ((flags & WITH_WR_VERIFY) && !rval)
-			rval = nand_verify(nand, offset,
+			rval = nand_verify(mtd, offset,
 				truncated_write_size, p_buffer);
 
 		offset += write_size;
@@ -693,7 +693,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
  * the limit we are passed, length is set to 0 and actual is set to the
  * required length.
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @param length buffer length, on return holds number of read bytes
  * @param actual set to size required to read length worth of buffer or 0
@@ -703,8 +703,8 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
  * @param buffer buffer to write to
  * @return 0 in case of success
  */
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
-		size_t *actual, loff_t lim, u_char *buffer)
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
+		       size_t *actual, loff_t lim, u_char *buffer)
 {
 	int rval;
 	size_t left_to_read = *length;
@@ -712,7 +712,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	u_char *p_buffer = buffer;
 	int need_skip;
 
-	if ((offset & (nand->writesize - 1)) != 0) {
+	if ((offset & (mtd->writesize - 1)) != 0) {
 		printf("Attempt to read non page-aligned data\n");
 		*length = 0;
 		if (actual)
@@ -720,7 +720,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 		return -EINVAL;
 	}
 
-	need_skip = check_skip_len(nand, offset, *length, &used_for_read);
+	need_skip = check_skip_len(mtd, offset, *length, &used_for_read);
 
 	if (actual)
 		*actual = used_for_read;
@@ -738,7 +738,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	if (!need_skip) {
-		rval = nand_read(nand, offset, length, buffer);
+		rval = nand_read(mtd, offset, length, buffer);
 		if (!rval || rval == -EUCLEAN)
 			return 0;
 
@@ -749,24 +749,24 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
 	}
 
 	while (left_to_read > 0) {
-		size_t block_offset = offset & (nand->erasesize - 1);
+		size_t block_offset = offset & (mtd->erasesize - 1);
 		size_t read_length;
 
 		WATCHDOG_RESET();
 
-		if (nand_block_isbad(nand, offset & ~(nand->erasesize - 1))) {
+		if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
 			printf("Skipping bad block 0x%08llx\n",
-				offset & ~(nand->erasesize - 1));
-			offset += nand->erasesize - block_offset;
+				offset & ~(mtd->erasesize - 1));
+			offset += mtd->erasesize - block_offset;
 			continue;
 		}
 
-		if (left_to_read < (nand->erasesize - block_offset))
+		if (left_to_read < (mtd->erasesize - block_offset))
 			read_length = left_to_read;
 		else
-			read_length = nand->erasesize - block_offset;
+			read_length = mtd->erasesize - block_offset;
 
-		rval = nand_read(nand, offset, &read_length, p_buffer);
+		rval = nand_read(mtd, offset, &read_length, p_buffer);
 		if (rval && rval != -EUCLEAN) {
 			printf("NAND read from offset %llx failed %d\n",
 				offset, rval);
@@ -812,57 +812,57 @@ static int check_pattern(const u_char *buf, u_char patt, int size)
  * This is useful to determine if a block that caused a write error is still
  * good or should be marked as bad.
  *
- * @param nand NAND device
+ * @param mtd nand mtd instance
  * @param offset offset in flash
  * @return 0 if the block is still good
  */
-int nand_torture(nand_info_t *nand, loff_t offset)
+int nand_torture(struct mtd_info *mtd, loff_t offset)
 {
 	u_char patterns[] = {0xa5, 0x5a, 0x00};
 	struct erase_info instr = {
 		.mtd = nand,
 		.addr = offset,
-		.len = nand->erasesize,
+		.len = mtd->erasesize,
 	};
 	size_t retlen;
 	int err, ret = -1, i, patt_count;
 	u_char *buf;
 
-	if ((offset & (nand->erasesize - 1)) != 0) {
+	if ((offset & (mtd->erasesize - 1)) != 0) {
 		puts("Attempt to torture a block at a non block-aligned offset\n");
 		return -EINVAL;
 	}
 
-	if (offset + nand->erasesize > nand->size) {
+	if (offset + mtd->erasesize > mtd->size) {
 		puts("Attempt to torture a block outside the flash area\n");
 		return -EINVAL;
 	}
 
 	patt_count = ARRAY_SIZE(patterns);
 
-	buf = malloc_cache_aligned(nand->erasesize);
+	buf = malloc_cache_aligned(mtd->erasesize);
 	if (buf == NULL) {
 		puts("Out of memory for erase block buffer\n");
 		return -ENOMEM;
 	}
 
 	for (i = 0; i < patt_count; i++) {
-		err = nand->erase(nand, &instr);
+		err = mtd_erase(mtd, &instr);
 		if (err) {
 			printf("%s: erase() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
 		/* Make sure the block contains only 0xff bytes */
-		err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
-		if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+		err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
+		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = check_pattern(buf, 0xff, nand->erasesize);
+		err = check_pattern(buf, 0xff, mtd->erasesize);
 		if (!err) {
 			printf("Erased block at 0x%llx, but a non-0xff byte was found\n",
 				offset);
@@ -871,22 +871,22 @@ int nand_torture(nand_info_t *nand, loff_t offset)
 		}
 
 		/* Write a pattern and check it */
-		memset(buf, patterns[i], nand->erasesize);
-		err = nand->write(nand, offset, nand->erasesize, &retlen, buf);
-		if (err || retlen != nand->erasesize) {
+		memset(buf, patterns[i], mtd->erasesize);
+		err = mtd_write(mtd, offset, mtd->erasesize, &retlen, buf);
+		if (err || retlen != mtd->erasesize) {
 			printf("%s: write() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = nand->read(nand, offset, nand->erasesize, &retlen, buf);
-		if ((err && err != -EUCLEAN) || retlen != nand->erasesize) {
+		err = mtd_read(mtd, offset, mtd->erasesize, &retlen, buf);
+		if ((err && err != -EUCLEAN) || retlen != mtd->erasesize) {
 			printf("%s: read() failed for block at 0x%llx: %d\n",
-				nand->name, instr.addr, err);
+				mtd->name, instr.addr, err);
 			goto out;
 		}
 
-		err = check_pattern(buf, patterns[i], nand->erasesize);
+		err = check_pattern(buf, patterns[i], mtd->erasesize);
 		if (!err) {
 			printf("Pattern 0x%.2x checking failed for block at "
 					"0x%llx\n", patterns[i], offset);
diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c
index 8a68cb0a67..0a9849e9bc 100644
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -1,6 +1,6 @@
 /*
  * Overview:
- *   Platform independend driver for NDFC (NanD Flash Controller)
+ *   Platform independent driver for NDFC (NanD Flash Controller)
  *   integrated into IBM/AMCC PPC4xx cores
  *
  * (C) Copyright 2006-2009
@@ -37,7 +37,7 @@ static int ndfc_cs[NDFC_MAX_BANKS];
 
 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 
 	if (cmd == NAND_CMD_NONE)
@@ -51,7 +51,7 @@ static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 
 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 
 	return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
@@ -59,7 +59,7 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
 
 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	u32 ccr;
 
@@ -71,7 +71,7 @@ static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
 			      const u_char *dat, u_char *ecc_code)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	u32 ecc;
 	u8 *p = (u8 *)&ecc;
@@ -96,7 +96,7 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
  */
 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	uint32_t *p = (uint32_t *) buf;
 
@@ -110,7 +110,7 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
  */
 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
-	struct nand_chip *this = mtdinfo->priv;
+	struct nand_chip *this = mtd_to_nand(mtdinfo);
 	ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
 	uint32_t *p = (uint32_t *) buf;
 
@@ -124,7 +124,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
 static uint8_t ndfc_read_byte(struct mtd_info *mtd)
 {
 
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
 	return (uint8_t) readw(chip->IO_ADDR_R);
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 6a45d28a72..67f293dcd0 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -58,8 +58,8 @@ static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 				uint32_t ctrl)
 {
-	register struct nand_chip *this = mtd->priv;
-	struct omap_nand_info *info = this->priv;
+	register struct nand_chip *this = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(this);
 	int cs = info->cs;
 
 	/*
@@ -85,8 +85,8 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
 /* Check wait pin as dev ready indicator */
 static int omap_dev_ready(struct mtd_info *mtd)
 {
-	register struct nand_chip *this = mtd->priv;
-	struct omap_nand_info *info = this->priv;
+	register struct nand_chip *this = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(this);
 	return gpmc_cfg->status & (1 << (8 + info->ws));
 }
 
@@ -163,7 +163,7 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 				return 0;
 			printf("Error: Bad compare! failed\n");
 			/* detected 2 bit error */
-			return -1;
+			return -EBADMSG;
 		}
 	}
 	return 0;
@@ -177,8 +177,8 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 __maybe_unused
 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 {
-	struct nand_chip	*nand	= mtd->priv;
-	struct omap_nand_info	*info	= nand->priv;
+	struct nand_chip	*nand	= mtd_to_nand(mtd);
+	struct omap_nand_info	*info	= nand_get_controller_data(nand);
 	unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 	unsigned int ecc_algo = 0;
 	unsigned int bch_type = 0;
@@ -262,8 +262,8 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 				uint8_t *ecc_code)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 	uint32_t *ptr, val = 0;
 	int8_t i = 0, j;
 
@@ -392,7 +392,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 {
 	int ret;
 	uint32_t cnt;
-	struct omap_nand_info *info = chip->priv;
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 	if (ret < 0)
@@ -417,7 +417,7 @@ static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int le
 
 static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	if (chip->options & NAND_BUSWIDTH_16)
 		nand_read_buf16(mtd, buf, len);
@@ -429,7 +429,7 @@ static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int ret;
 	uint32_t head, tail;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	/*
 	 * If the destination buffer is unaligned, start with reading
@@ -491,8 +491,8 @@ static void omap_reverse_list(u8 *list, unsigned int length)
 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 				uint8_t *read_ecc, uint8_t *calc_ecc)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	uint32_t error_count = 0, error_max;
 	uint32_t error_loc[ELM_MAX_ERROR_COUNT];
@@ -652,8 +652,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 	int i, count;
 	/* cannot correct more than 8 errors */
 	unsigned int errloc[8];
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 							NULL, errloc);
@@ -691,8 +691,8 @@ static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
  */
 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
-	struct omap_nand_info *info = chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct omap_nand_info *info = nand_get_controller_data(chip);
 
 	if (info->control) {
 		free_bch(info->control);
@@ -710,7 +710,7 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
  */
 static int omap_select_ecc_scheme(struct nand_chip *nand,
 	enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
-	struct omap_nand_info	*info		= nand->priv;
+	struct omap_nand_info	*info		= nand_get_controller_data(nand);
 	struct nand_ecclayout	*ecclayout	= &omap_ecclayout;
 	int eccsteps = pagesize / SECTOR_BYTES;
 	int i;
@@ -898,13 +898,13 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 
 	if (nand_curr_device < 0 ||
 	    nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
-	    !nand_info[nand_curr_device].name) {
+	    !nand_info[nand_curr_device]->name) {
 		printf("nand: error: no NAND devices found\n");
 		return -ENODEV;
 	}
 
-	mtd = &nand_info[nand_curr_device];
-	nand = mtd->priv;
+	mtd = nand_info[nand_curr_device];
+	nand = mtd_to_nand(mtd);
 	nand->options |= NAND_OWN_BUFFERS;
 	nand->options &= ~NAND_SUBPAGE_READ;
 	/* Setup the ecc configurations again */
@@ -917,6 +917,10 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 			err = omap_select_ecc_scheme(nand,
 					OMAP_ECC_BCH8_CODE_HW,
 					mtd->writesize, mtd->oobsize);
+		} else if (eccstrength == 16) {
+			err = omap_select_ecc_scheme(nand,
+					OMAP_ECC_BCH16_CODE_HW,
+					mtd->writesize, mtd->oobsize);
 		} else {
 			printf("nand: error: unsupported ECC scheme\n");
 			return -EINVAL;
@@ -994,7 +998,7 @@ int board_nand_init(struct nand_chip *nand)
 	omap_nand_info[cs].control = NULL;
 	omap_nand_info[cs].cs = cs;
 	omap_nand_info[cs].ws = wscfg[cs];
-	nand->priv	= &omap_nand_info[cs];
+	nand_set_controller_data(nand, &omap_nand_info[cs]);
 	nand->cmd_ctrl	= omap_nand_hwcontrol;
 	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
 	nand->chip_delay = 100;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d529467ebc..d3ac5391f1 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -900,7 +900,8 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
 static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 			 int column, int page_addr)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int exec_cmd;
 
@@ -960,7 +961,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd,
 				  const unsigned command,
 				  int column, int page_addr)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int exec_cmd, ext_cmd_type;
 
@@ -1079,7 +1081,8 @@ static void nand_cmdfunc_extended(struct mtd_info *mtd,
 }
 
 static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, const uint8_t *buf, int oob_required)
+		struct nand_chip *chip, const uint8_t *buf, int oob_required,
+		int page)
 {
 	chip->write_buf(mtd, buf, mtd->writesize);
 	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -1091,7 +1094,7 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, uint8_t *buf, int oob_required,
 		int page)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 
 	chip->read_buf(mtd, buf, mtd->writesize);
@@ -1117,7 +1120,8 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 
 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	char retval = 0xFF;
 
@@ -1130,7 +1134,8 @@ static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 
 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	u16 retval = 0xFFFF;
 
@@ -1143,7 +1148,8 @@ static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 
 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
@@ -1154,7 +1160,8 @@ static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 		const uint8_t *buf, int len)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
 
@@ -1169,7 +1176,8 @@ static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
 
 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 
 	if (info->need_wait) {
@@ -1210,7 +1218,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
 {
 	struct pxa3xx_nand_host *host = info->host[info->cs];
 	struct mtd_info *mtd = host->mtd;
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 
 	info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 	info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
@@ -1262,7 +1270,7 @@ static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
 	int ret;
 
 	mtd = info->host[info->cs]->mtd;
-	chip = mtd->priv;
+	chip = mtd_to_nand(mtd);
 
 	/* configure default flash values */
 	info->reg_ndcr = 0x0; /* enable all interrupts */
@@ -1354,10 +1362,10 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info,
 
 static int pxa3xx_nand_scan(struct mtd_info *mtd)
 {
-	struct pxa3xx_nand_host *host = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
 	struct pxa3xx_nand_info *info = host->info_data;
 	struct pxa3xx_nand_platform_data *pdata = info->pdata;
-	struct nand_chip *chip = mtd->priv;
 	int ret;
 	uint16_t ecc_strength, ecc_step;
 
@@ -1477,16 +1485,15 @@ static int alloc_nand_resource(struct pxa3xx_nand_info *info)
 
 	info->variant = pxa3xx_nand_get_variant();
 	for (cs = 0; cs < pdata->num_cs; cs++) {
-		mtd = &nand_info[cs];
 		chip = (struct nand_chip *)
 			((u8 *)&info[1] + sizeof(*host) * cs);
+		mtd = nand_to_mtd(chip);
 		host = (struct pxa3xx_nand_host *)chip;
 		info->host[cs] = host;
 		host->mtd = mtd;
 		host->cs = cs;
 		host->info_data = info;
 		host->read_id_bytes = 4;
-		mtd->priv = host;
 		mtd->owner = THIS_MODULE;
 
 		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
@@ -1573,8 +1580,10 @@ static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
 			continue;
 		}
 
-		if (!ret)
-			probe_success = 1;
+		if (nand_register(cs, mtd))
+			continue;
+
+		probe_success = 1;
 	}
 
 	if (!probe_success)
@@ -1601,6 +1610,4 @@ void board_nand_init(void)
 	ret = pxa3xx_nand_probe(info);
 	if (ret)
 		return;
-
-	nand_register(0);
 }
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index b3a2a60bb2..dd742a6351 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -31,7 +31,7 @@
 static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 {
 	int i;
-	struct nand_chip *this = mtd->priv;
+	struct nand_chip *this = mtd_to_nand(mtd);
 
 	for (i = 0; i < len; i++)
 		buf[i] = readb(this->IO_ADDR_R);
@@ -40,7 +40,7 @@ static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 
 static void s3c24x0_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct s3c24x0_nand *nand = s3c24x0_get_base_nand();
 
 	debug("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
@@ -104,7 +104,7 @@ static int s3c24x0_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	printf("s3c24x0_nand_correct_data: not implemented\n");
-	return -1;
+	return -EBADMSG;
 }
 #endif
 
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index a77db7b65d..2032f65812 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -143,10 +143,10 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr *reg)
  */
 static uint8_t read_byte(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID,
 	       &info->reg->command);
@@ -169,8 +169,8 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	int i, s;
 	unsigned int reg;
-	struct nand_chip *chip = mtd->priv;
-	struct nand_drv *info = (struct nand_drv *)chip->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
+	struct nand_drv *info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	for (i = 0; i < len; i += 4) {
 		s = (len - i) > 4 ? 4 : len - i;
@@ -194,11 +194,11 @@ static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  */
 static int nand_dev_ready(struct mtd_info *mtd)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	int reg_val;
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	reg_val = readl(&info->reg->status);
 	if (reg_val & STATUS_RBSY0)
@@ -245,10 +245,10 @@ static void nand_clear_interrupt_status(struct nand_ctlr *reg)
 static void nand_command(struct mtd_info *mtd, unsigned int command,
 	int column, int page_addr)
 {
-	struct nand_chip *chip = mtd->priv;
+	struct nand_chip *chip = mtd_to_nand(mtd);
 	struct nand_drv *info;
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 
 	/*
 	 * Write out the command to the device.
@@ -512,7 +512,7 @@ static int nand_rw_page(struct mtd_info *mtd, struct nand_chip *chip,
 		return -EINVAL;
 	}
 
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 	config = &info->config;
 	if (set_bus_width_page_size(config, &reg_val))
 		return -EINVAL;
@@ -657,16 +657,9 @@ static int nand_read_page_hwecc(struct mtd_info *mtd,
  * @param buf	data buffer
  */
 static int nand_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
+	struct nand_chip *chip, const uint8_t *buf, int oob_required,
+	int page)
 {
-	int page;
-	struct nand_drv *info;
-
-	info = (struct nand_drv *)chip->priv;
-
-	page = (readl(&info->reg->addr_reg1) >> 16) |
-		(readl(&info->reg->addr_reg2) << 16);
-
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 1, 1);
 	return 0;
 }
@@ -697,15 +690,9 @@ static int nand_read_page_raw(struct mtd_info *mtd,
  * @param buf	data buffer
  */
 static int nand_write_page_raw(struct mtd_info *mtd,
-		struct nand_chip *chip,	const uint8_t *buf, int oob_required)
+		struct nand_chip *chip,	const uint8_t *buf,
+		int oob_required, int page)
 {
-	int page;
-	struct nand_drv *info;
-
-	info = (struct nand_drv *)chip->priv;
-	page = (readl(&info->reg->addr_reg1) >> 16) |
-		(readl(&info->reg->addr_reg2) << 16);
-
 	nand_rw_page(mtd, chip, (uint8_t *)buf, page, 0, 1);
 	return 0;
 }
@@ -734,7 +721,7 @@ static int nand_rw_oob(struct mtd_info *mtd, struct nand_chip *chip,
 
 	if (((int)chip->oob_poi) & 0x03)
 		return -EINVAL;
-	info = (struct nand_drv *)chip->priv;
+	info = (struct nand_drv *)nand_get_controller_data(chip);
 	if (set_bus_width_page_size(&info->config, &reg_val))
 		return -EINVAL;
 
@@ -963,7 +950,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 	nand->ecc.strength = 1;
 	nand->select_chip = nand_select_chip;
 	nand->dev_ready  = nand_dev_ready;
-	nand->priv = &nand_ctrl;
+	nand_set_controller_data(nand, &nand_ctrl);
 
 	/* Disable subpage writes as we do not provide ecc->hwctl */
 	nand->options |= NAND_NO_SUBPAGE_WRITE;
@@ -976,8 +963,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 
 	dm_gpio_set_value(&config->wp_gpio, 1);
 
-	our_mtd = &nand_info[devnum];
-	our_mtd->priv = nand;
+	our_mtd = nand_to_mtd(nand);
 	ret = nand_scan_ident(our_mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
 	if (ret)
 		return ret;
@@ -989,7 +975,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 	if (ret)
 		return ret;
 
-	ret = nand_register(devnum);
+	ret = nand_register(devnum, our_mtd);
 	if (ret)
 		return ret;
 
diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 1faec5e1f2..f99bdaf94d 100644
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -146,7 +146,6 @@ enum vf610_nfc_alt_buf {
 };
 
 struct vf610_nfc {
-	struct mtd_info *mtd;
 	struct nand_chip chip;
 	void __iomem *regs;
 	uint buf_offset;
@@ -155,8 +154,7 @@ struct vf610_nfc {
 	enum vf610_nfc_alt_buf alt_buf;
 };
 
-#define mtd_to_nfc(_mtd) \
-	(struct vf610_nfc *)((struct nand_chip *)_mtd->priv)->priv
+#define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
 
 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
 #define ECC_HW_MODE ECC_45_BYTE
@@ -608,7 +606,7 @@ static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  * ECC will be calculated automatically
  */
 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
-			       const uint8_t *buf, int oob_required)
+			       const uint8_t *buf, int oob_required, int page)
 {
 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
 
@@ -630,7 +628,7 @@ struct vf610_nfc_config {
 
 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 {
-	struct mtd_info *mtd = &nand_info[devnum];
+	struct mtd_info *mtd;
 	struct nand_chip *chip;
 	struct vf610_nfc *nfc;
 	int err = 0;
@@ -653,8 +651,8 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 	chip = &nfc->chip;
 	nfc->regs = addr;
 
-	mtd->priv = chip;
-	chip->priv = nfc;
+	mtd = nand_to_mtd(chip);
+	nand_set_controller_data(chip, nfc);
 
 	if (cfg.width == 16)
 		chip->options |= NAND_BUSWIDTH_16;
@@ -753,7 +751,7 @@ static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
 	if (err)
 		return err;
 
-	err = nand_register(devnum);
+	err = nand_register(devnum, mtd);
 	if (err)
 		return err;
 
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 007a5a085c..da2bb7b5d2 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -127,6 +127,11 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf);
 #endif
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+/* Used for Spansion S25FS-S family flash only. */
+#define CMD_SPANSION_RDAR	0x65 /* Read any device register */
+#define CMD_SPANSION_WRAR	0x71 /* Write any device register */
+#endif
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 4f37e33eb0..c577d9ed6c 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,		     WR_QPP},
 	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,                   WR_QPP},
 	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,		     WR_QPP},
 	{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5451725689..64d4e0f947 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -971,6 +971,43 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
+{
+	u8 cmd[4];
+	u32 offset = 0x800004; /* CR3V register offset */
+	u8 cr3v;
+	int ret;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	cmd[1] = offset >> 16;
+	cmd[2] = offset >> 8;
+	cmd[3] = offset >> 0;
+
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	/* CR3V bit3: 4-KB Erase */
+	if (cr3v & 0x8)
+		return 0;
+
+	cmd[0] = CMD_SPANSION_WRAR;
+	cr3v |= 0x8;
+	ret = spi_flash_cmd_write(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+
+	cmd[0] = CMD_SPANSION_RDAR;
+	ret = spi_flash_cmd_read(spi, cmd, 4, &cr3v, 1);
+	if (ret)
+		return -EIO;
+	if (!(cr3v & 0x8))
+		return -EFAULT;
+
+	return 0;
+}
+#endif
+
 int spi_flash_scan(struct spi_flash *flash)
 {
 	struct spi_slave *spi = flash->spi;
@@ -1021,6 +1058,42 @@ int spi_flash_scan(struct spi_flash *flash)
 		return -EPROTONOSUPPORT;
 	}
 
+#ifdef CONFIG_SPI_FLASH_SPANSION
+	/*
+	 * The S25FS-S family physical sectors may be configured as a
+	 * hybrid combination of eight 4-kB parameter sectors
+	 * at the top or bottom of the address space with all
+	 * but one of the remaining sectors being uniform size.
+	 * The Parameter Sector Erase commands (20h or 21h) must
+	 * be used to erase the 4-kB parameter sectors individually.
+	 * The Sector (uniform sector) Erase commands (D8h or DCh)
+	 * must be used to erase any of the remaining
+	 * sectors, including the portion of highest or lowest address
+	 * sector that is not overlaid by the parameter sectors.
+	 * The uniform sector erase command has no effect on parameter sectors.
+	 */
+	if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+	    (ext_jedec & 0xff00) == 0x4d00) {
+		int ret;
+		u8 id[6];
+
+		/* Read the ID codes again, 6 bytes */
+		ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
+		if (ret)
+			return -EIO;
+
+		ret = memcmp(id, idcode, 5);
+		if (ret)
+			return -EIO;
+
+		/* 0x81: S25FS-S family 0x80: S25FL-S family */
+		if (id[5] == 0x81) {
+			ret = spansion_s25fss_disable_4KB_erase(spi);
+			if (ret)
+				return ret;
+		}
+	}
+#endif
 	/* Flash powers up read-only, so clear BP# bits */
 	if (idcode[0] == SPI_FLASH_CFI_MFR_ATMEL ||
 	    idcode[0] == SPI_FLASH_CFI_MFR_MACRONIX ||
@@ -1074,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * have 256b pages.
 	 */
 	if (ext_jedec == 0x4d00) {
-		if ((jedec == 0x0215) || (jedec == 0x216))
+		if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
 			flash->page_size = 256;
 		else
 			flash->page_size = 512;
diff --git a/drivers/mtd/spi/spi_spl_load.c b/drivers/mtd/spi/spi_spl_load.c
index 46c98a9cee..bac1e85af3 100644
--- a/drivers/mtd/spi/spi_spl_load.c
+++ b/drivers/mtd/spi/spi_spl_load.c
@@ -48,6 +48,18 @@ static int spi_load_image_os(struct spi_flash *flash,
 }
 #endif
 
+static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector,
+			      ulong count, void *buf)
+{
+	struct spi_flash *flash = load->dev;
+	ulong ret;
+
+	ret = spi_flash_read(flash, sector, count, buf);
+	if (!ret)
+		return count;
+	else
+		return 0;
+}
 /*
  * The main entry for SPI booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -85,11 +97,26 @@ int spl_spi_load_image(void)
 		if (err)
 			return err;
 
-		err = spl_parse_image_header(header);
-		if (err)
-			return err;
-		err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
-			       spl_image.size, (void *)spl_image.load_addr);
+		if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) {
+			struct spl_load_info load;
+
+			debug("Found FIT\n");
+			load.dev = flash;
+			load.priv = NULL;
+			load.filename = NULL;
+			load.bl_len = 1;
+			load.read = spl_spi_fit_read;
+			err = spl_load_simple_fit(&load,
+						  CONFIG_SYS_SPI_U_BOOT_OFFS,
+						  header);
+		} else {
+			err = spl_parse_image_header(header);
+			if (err)
+				return err;
+			err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
+					     spl_image.size,
+					     (void *)spl_image.load_addr);
+		}
 	}
 
 	return err;
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 91b7690972..c1cb689ccf 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -46,6 +46,15 @@ menuconfig NETDEVICES
 
 if NETDEVICES
 
+config AG7XXX
+	bool "Atheros AG7xxx Ethernet MAC support"
+	depends on DM_ETH && ARCH_ATH79
+	select PHYLIB
+	help
+	  This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
+	  present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.
+
+
 config ALTERA_TSE
 	bool "Altera Triple-Speed Ethernet MAC support"
 	depends on DM_ETH
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index fbedd04f7a..5702592169 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -7,6 +7,7 @@
 
 obj-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
+obj-$(CONFIG_AG7XXX) += ag7xxx.o
 obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
 obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
 obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
@@ -59,7 +60,7 @@ obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
-obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
+obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
 obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
 obj-$(CONFIG_ULI526X) += uli526x.o
diff --git a/drivers/net/ag7xxx.c b/drivers/net/ag7xxx.c
new file mode 100644
index 0000000000..346f138caf
--- /dev/null
+++ b/drivers/net/ag7xxx.c
@@ -0,0 +1,980 @@
+/*
+ * Atheros AR71xx / AR9xxx GMAC driver
+ *
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <linux/compiler.h>
+#include <linux/err.h>
+#include <linux/mii.h>
+#include <wait_bit.h>
+#include <asm/io.h>
+
+#include <mach/ath79.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum ag7xxx_model {
+	AG7XXX_MODEL_AG933X,
+	AG7XXX_MODEL_AG934X,
+};
+
+#define AG7XXX_ETH_CFG1				0x00
+#define AG7XXX_ETH_CFG1_SOFT_RST		BIT(31)
+#define AG7XXX_ETH_CFG1_RX_RST			BIT(19)
+#define AG7XXX_ETH_CFG1_TX_RST			BIT(18)
+#define AG7XXX_ETH_CFG1_LOOPBACK		BIT(8)
+#define AG7XXX_ETH_CFG1_RX_EN			BIT(2)
+#define AG7XXX_ETH_CFG1_TX_EN			BIT(0)
+
+#define AG7XXX_ETH_CFG2				0x04
+#define AG7XXX_ETH_CFG2_IF_1000			BIT(9)
+#define AG7XXX_ETH_CFG2_IF_10_100		BIT(8)
+#define AG7XXX_ETH_CFG2_IF_SPEED_MASK		(3 << 8)
+#define AG7XXX_ETH_CFG2_HUGE_FRAME_EN		BIT(5)
+#define AG7XXX_ETH_CFG2_LEN_CHECK		BIT(4)
+#define AG7XXX_ETH_CFG2_PAD_CRC_EN		BIT(2)
+#define AG7XXX_ETH_CFG2_FDX			BIT(0)
+
+#define AG7XXX_ETH_MII_MGMT_CFG			0x20
+#define AG7XXX_ETH_MII_MGMT_CFG_RESET		BIT(31)
+
+#define AG7XXX_ETH_MII_MGMT_CMD			0x24
+#define AG7XXX_ETH_MII_MGMT_CMD_READ		0x1
+
+#define AG7XXX_ETH_MII_MGMT_ADDRESS		0x28
+#define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT	8
+
+#define AG7XXX_ETH_MII_MGMT_CTRL		0x2c
+
+#define AG7XXX_ETH_MII_MGMT_STATUS		0x30
+
+#define AG7XXX_ETH_MII_MGMT_IND			0x34
+#define AG7XXX_ETH_MII_MGMT_IND_INVALID		BIT(2)
+#define AG7XXX_ETH_MII_MGMT_IND_BUSY		BIT(0)
+
+#define AG7XXX_ETH_ADDR1			0x40
+#define AG7XXX_ETH_ADDR2			0x44
+
+#define AG7XXX_ETH_FIFO_CFG_0			0x48
+#define AG7XXX_ETH_FIFO_CFG_1			0x4c
+#define AG7XXX_ETH_FIFO_CFG_2			0x50
+#define AG7XXX_ETH_FIFO_CFG_3			0x54
+#define AG7XXX_ETH_FIFO_CFG_4			0x58
+#define AG7XXX_ETH_FIFO_CFG_5			0x5c
+
+#define AG7XXX_ETH_DMA_TX_CTRL			0x180
+#define AG7XXX_ETH_DMA_TX_CTRL_TXE		BIT(0)
+
+#define AG7XXX_ETH_DMA_TX_DESC			0x184
+
+#define AG7XXX_ETH_DMA_TX_STATUS		0x188
+
+#define AG7XXX_ETH_DMA_RX_CTRL			0x18c
+#define AG7XXX_ETH_DMA_RX_CTRL_RXE		BIT(0)
+
+#define AG7XXX_ETH_DMA_RX_DESC			0x190
+
+#define AG7XXX_ETH_DMA_RX_STATUS		0x194
+
+/* Custom register at 0x18070000 */
+#define AG7XXX_GMAC_ETH_CFG			0x00
+#define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP		BIT(8)
+#define AG7XXX_ETH_CFG_SW_PHY_SWAP		BIT(7)
+#define AG7XXX_ETH_CFG_SW_ONLY_MODE		BIT(6)
+#define AG7XXX_ETH_CFG_GE0_ERR_EN		BIT(5)
+#define AG7XXX_ETH_CFG_MII_GE0_SLAVE		BIT(4)
+#define AG7XXX_ETH_CFG_MII_GE0_MASTER		BIT(3)
+#define AG7XXX_ETH_CFG_GMII_GE0			BIT(2)
+#define AG7XXX_ETH_CFG_MII_GE0			BIT(1)
+#define AG7XXX_ETH_CFG_RGMII_GE0		BIT(0)
+
+#define CONFIG_TX_DESCR_NUM	8
+#define CONFIG_RX_DESCR_NUM	8
+#define CONFIG_ETH_BUFSIZE	2048
+#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+/* DMA descriptor. */
+struct ag7xxx_dma_desc {
+	u32	data_addr;
+#define AG7XXX_DMADESC_IS_EMPTY			BIT(31)
+#define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET	16
+#define AG7XXX_DMADESC_PKT_SIZE_OFFSET		0
+#define AG7XXX_DMADESC_PKT_SIZE_MASK		0xfff
+	u32	config;
+	u32	next_desc;
+	u32	_pad[5];
+};
+
+struct ar7xxx_eth_priv {
+	struct ag7xxx_dma_desc	tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+	struct ag7xxx_dma_desc	rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+	char		txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+	char		rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+
+	void __iomem		*regs;
+	void __iomem		*phyregs;
+
+	struct eth_device	*dev;
+	struct phy_device	*phydev;
+	struct mii_dev		*bus;
+
+	u32			interface;
+	u32			tx_currdescnum;
+	u32			rx_currdescnum;
+	enum ag7xxx_model	model;
+};
+
+/*
+ * Switch and MDIO access
+ */
+static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	void __iomem *regs = priv->phyregs;
+	int ret;
+
+	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+	writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
+	       regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+	if (ret)
+		return ret;
+
+	*val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
+	writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
+
+	return 0;
+}
+
+static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	void __iomem *regs = priv->phyregs;
+	int ret;
+
+	writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
+	       regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
+	writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
+
+	ret = wait_for_bit("ag7xxx", regs + AG7XXX_ETH_MII_MGMT_IND,
+			   AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
+
+	return ret;
+}
+
+static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	u32 phy_addr;
+	u32 reg_addr;
+	u32 phy_temp;
+	u32 reg_temp;
+	u16 rv = 0;
+	int ret;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		phy_addr = 0x1f;
+		reg_addr = 0x10;
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		phy_addr = 0x18;
+		reg_addr = 0x00;
+	} else
+		return -EINVAL;
+
+	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+	if (ret)
+		return ret;
+
+	phy_temp = ((reg >> 6) & 0x7) | 0x10;
+	reg_temp = (reg >> 1) & 0x1e;
+	*val = 0;
+
+	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
+	if (ret < 0)
+		return ret;
+	*val |= rv;
+
+	ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
+	if (ret < 0)
+		return ret;
+	*val |= (rv << 16);
+
+	return 0;
+}
+
+static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
+{
+	struct ar7xxx_eth_priv *priv = bus->priv;
+	u32 phy_addr;
+	u32 reg_addr;
+	u32 phy_temp;
+	u32 reg_temp;
+	int ret;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		phy_addr = 0x1f;
+		reg_addr = 0x10;
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		phy_addr = 0x18;
+		reg_addr = 0x00;
+	} else
+		return -EINVAL;
+
+	ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
+	if (ret)
+		return ret;
+
+	phy_temp = ((reg >> 6) & 0x7) | 0x10;
+	reg_temp = (reg >> 1) & 0x1e;
+
+	/*
+	 * The switch on AR933x has some special register behavior, which
+	 * expects particular write order of their nibbles:
+	 *   0x40 ..... MSB first, LSB second
+	 *   0x50 ..... MSB first, LSB second
+	 *   0x98 ..... LSB first, MSB second
+	 *   others ... don't care
+	 */
+	if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+		if (ret < 0)
+			return ret;
+
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+		if (ret < 0)
+			return ret;
+	} else {
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
+		if (ret < 0)
+			return ret;
+
+		ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static u16 ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
+{
+	u32 data;
+
+	/* Dummy read followed by PHY read/write command. */
+	ag7xxx_switch_reg_read(bus, 0x98, &data);
+	data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
+	ag7xxx_switch_reg_write(bus, 0x98, data);
+
+	/* Wait for operation to finish */
+	do {
+		ag7xxx_switch_reg_read(bus, 0x98, &data);
+	} while (data & BIT(31));
+
+	return data & 0xffff;
+}
+
+static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+	return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
+}
+
+static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+			     u16 val)
+{
+	ag7xxx_mdio_rw(bus, addr, reg, val);
+	return 0;
+}
+
+/*
+ * DMA ring handlers
+ */
+static void ag7xxx_dma_clean_tx(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr, *next;
+	u32 start, end;
+	int i;
+
+	for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
+		curr = &priv->tx_mac_descrtable[i];
+		next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
+
+		curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->config = AG7XXX_DMADESC_IS_EMPTY;
+		curr->next_desc = virt_to_phys(next);
+	}
+
+	priv->tx_currdescnum = 0;
+
+	/* Cache: Flush descriptors, don't care about buffers. */
+	start = (u32)(&priv->tx_mac_descrtable[0]);
+	end = start + sizeof(priv->tx_mac_descrtable);
+	flush_dcache_range(start, end);
+}
+
+static void ag7xxx_dma_clean_rx(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr, *next;
+	u32 start, end;
+	int i;
+
+	for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
+		curr = &priv->rx_mac_descrtable[i];
+		next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
+
+		curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
+		curr->config = AG7XXX_DMADESC_IS_EMPTY;
+		curr->next_desc = virt_to_phys(next);
+	}
+
+	priv->rx_currdescnum = 0;
+
+	/* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
+	start = (u32)(&priv->rx_mac_descrtable[0]);
+	end = start + sizeof(priv->rx_mac_descrtable);
+	flush_dcache_range(start, end);
+	invalidate_dcache_range(start, end);
+
+	start = (u32)&priv->rxbuffs;
+	end = start + sizeof(priv->rxbuffs);
+	invalidate_dcache_range(start, end);
+}
+
+/*
+ * Ethernet I/O
+ */
+static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end;
+
+	curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
+
+	/* Cache: Invalidate descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	invalidate_dcache_range(start, end);
+
+	if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
+		printf("ag7xxx: Out of TX DMA descriptors!\n");
+		return -EPERM;
+	}
+
+	/* Copy the packet into the data buffer. */
+	memcpy(phys_to_virt(curr->data_addr), packet, length);
+	curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+	/* Cache: Flush descriptor, Flush buffer. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	flush_dcache_range(start, end);
+	start = (u32)phys_to_virt(curr->data_addr);
+	end = start + length;
+	flush_dcache_range(start, end);
+
+	/* Load the DMA descriptor and start TX DMA. */
+	writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
+	       priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+
+	/* Switch to next TX descriptor. */
+	priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
+
+	return 0;
+}
+
+static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end, length;
+
+	curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+	/* Cache: Invalidate descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	invalidate_dcache_range(start, end);
+
+	/* No packets received. */
+	if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
+		return -EAGAIN;
+
+	length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
+
+	/* Cache: Invalidate buffer. */
+	start = (u32)phys_to_virt(curr->data_addr);
+	end = start + length;
+	invalidate_dcache_range(start, end);
+
+	/* Receive one packet and return length. */
+	*packetp = phys_to_virt(curr->data_addr);
+	return length;
+}
+
+static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
+				   int length)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct ag7xxx_dma_desc *curr;
+	u32 start, end;
+
+	curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
+
+	curr->config = AG7XXX_DMADESC_IS_EMPTY;
+
+	/* Cache: Flush descriptor. */
+	start = (u32)curr;
+	end = start + sizeof(*curr);
+	flush_dcache_range(start, end);
+
+	/* Switch to next RX descriptor. */
+	priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
+
+	return 0;
+}
+
+static int ag7xxx_eth_start(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* FIXME: Check if link up */
+
+	/* Clear the DMA rings. */
+	ag7xxx_dma_clean_tx(dev);
+	ag7xxx_dma_clean_rx(dev);
+
+	/* Load DMA descriptors and start the RX DMA. */
+	writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
+	       priv->regs + AG7XXX_ETH_DMA_TX_DESC);
+	writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
+	       priv->regs + AG7XXX_ETH_DMA_RX_DESC);
+	writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
+	       priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+
+	return 0;
+}
+
+static void ag7xxx_eth_stop(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* Stop the TX DMA. */
+	writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
+	wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
+		     1000, 0);
+
+	/* Stop the RX DMA. */
+	writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
+	wait_for_bit("ag7xxx", priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
+		     1000, 0);
+}
+
+/*
+ * Hardware setup
+ */
+static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	unsigned char *mac = pdata->enetaddr;
+	u32 macid_lo, macid_hi;
+
+	macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
+	macid_lo = (mac[5] << 16) | (mac[4] << 24);
+
+	writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
+	writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
+
+	return 0;
+}
+
+static void ag7xxx_hw_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	u32 speed;
+
+	setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
+		     AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
+		     AG7XXX_ETH_CFG1_SOFT_RST);
+
+	mdelay(10);
+
+	writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
+	       priv->regs + AG7XXX_ETH_CFG1);
+
+	if (priv->interface == PHY_INTERFACE_MODE_RMII)
+		speed = AG7XXX_ETH_CFG2_IF_10_100;
+	else
+		speed = AG7XXX_ETH_CFG2_IF_1000;
+
+	clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
+			AG7XXX_ETH_CFG2_IF_SPEED_MASK,
+			speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
+			AG7XXX_ETH_CFG2_LEN_CHECK);
+
+	writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+	writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+
+	writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
+	setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
+	writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
+	writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
+	writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
+	writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
+}
+
+static int ag7xxx_mii_get_div(void)
+{
+	ulong freq = get_bus_freq(0);
+
+	switch (freq / 1000000) {
+	case 150:	return 0x7;
+	case 175:	return 0x5;
+	case 200:	return 0x4;
+	case 210:	return 0x9;
+	case 220:	return 0x9;
+	default:	return 0x7;
+	}
+}
+
+static int ag7xxx_mii_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret, div = ag7xxx_mii_get_div();
+	u32 reg;
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		/* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
+		if (priv->interface == PHY_INTERFACE_MODE_RMII)
+			return 0;
+	}
+
+	if (priv->model == AG7XXX_MODEL_AG934X) {
+		writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | 0x4,
+		       priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		writel(0x4, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		return 0;
+	}
+
+	for (i = 0; i < 10; i++) {
+		writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
+		       priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+		writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
+
+		/* Check the switch */
+		ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
+		if (ret)
+			continue;
+
+		if (reg != 0x18007fff)
+			continue;
+
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+static int ag933x_phy_setup_wan(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	/* Configure switch port 4 (GMAC0) */
+	return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
+}
+
+static int ag933x_phy_setup_lan(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret;
+	u32 reg;
+
+	/* Reset the switch */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+	if (ret)
+		return ret;
+	reg |= BIT(31);
+	ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
+	if (ret)
+		return ret;
+
+	do {
+		ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+		if (ret)
+			return ret;
+	} while (reg & BIT(31));
+
+	/* Configure switch ports 0...3 (GMAC1) */
+	for (i = 0; i < 4; i++) {
+		ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
+		if (ret)
+			return ret;
+	}
+
+	/* Enable CPU port */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
+	if (ret)
+		return ret;
+
+	for (i = 0; i < 4; i++) {
+		ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
+		if (ret)
+			return ret;
+	}
+
+	/* QM Control */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
+	if (ret)
+		return ret;
+
+	/* Disable Atheros header */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
+	if (ret)
+		return ret;
+
+	/* Tag priority mapping */
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
+	if (ret)
+		return ret;
+
+	/* Enable ARP packets to the CPU */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
+	if (ret)
+		return ret;
+	reg |= 0x100000;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
+				ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
+				ADVERTISE_PAUSE_ASYM);
+	if (ret)
+		return ret;
+
+	if (priv->model == AG7XXX_MODEL_AG934X) {
+		ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
+					ADVERTISE_1000FULL);
+		if (ret)
+			return ret;
+	}
+
+	return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
+				 BMCR_ANENABLE | BMCR_RESET);
+}
+
+static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	do {
+		ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
+		if (ret < 0)
+			return ret;
+		mdelay(10);
+	} while (ret & BMCR_RESET);
+
+	return 0;
+}
+
+static int ag933x_phy_setup_common(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret, phymax;
+
+	if (priv->model == AG7XXX_MODEL_AG933X)
+		phymax = 4;
+	else if (priv->model == AG7XXX_MODEL_AG934X)
+		phymax = 5;
+	else
+		return -EINVAL;
+
+	if (priv->interface == PHY_INTERFACE_MODE_RMII) {
+		ret = ag933x_phy_setup_reset_set(dev, phymax);
+		if (ret)
+			return ret;
+
+		ret = ag933x_phy_setup_reset_fin(dev, phymax);
+		if (ret)
+			return ret;
+
+		/* Read out link status */
+		ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
+		if (ret < 0)
+			return ret;
+
+		return 0;
+	}
+
+	/* Switch ports */
+	for (i = 0; i < phymax; i++) {
+		ret = ag933x_phy_setup_reset_set(dev, i);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < phymax; i++) {
+		ret = ag933x_phy_setup_reset_fin(dev, i);
+		if (ret)
+			return ret;
+	}
+
+	for (i = 0; i < phymax; i++) {
+		/* Read out link status */
+		ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ag934x_phy_setup(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int i, ret;
+	u32 reg;
+
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
+	if (ret)
+		return ret;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
+	if (ret)
+		return ret;
+
+	/* AR8327/AR8328 v1.0 fixup */
+	ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
+	if (ret)
+		return ret;
+	if ((reg & 0xffff) == 0x1201) {
+		for (i = 0; i < 5; i++) {
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
+			if (ret)
+				return ret;
+			ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
+			if (ret)
+				return ret;
+		}
+	}
+
+	ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
+	if (ret)
+		return ret;
+	reg &= ~0x70000;
+	ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ag7xxx_mac_probe(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ag7xxx_hw_setup(dev);
+	ret = ag7xxx_mii_setup(dev);
+	if (ret)
+		return ret;
+
+	ag7xxx_eth_write_hwaddr(dev);
+
+	if (priv->model == AG7XXX_MODEL_AG933X) {
+		if (priv->interface == PHY_INTERFACE_MODE_RMII)
+			ret = ag933x_phy_setup_wan(dev);
+		else
+			ret = ag933x_phy_setup_lan(dev);
+	} else if (priv->model == AG7XXX_MODEL_AG934X) {
+		ret = ag934x_phy_setup(dev);
+	} else {
+		return -EINVAL;
+	}
+
+	if (ret)
+		return ret;
+
+	return ag933x_phy_setup_common(dev);
+}
+
+static int ag7xxx_mdio_probe(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	struct mii_dev *bus = mdio_alloc();
+
+	if (!bus)
+		return -ENOMEM;
+
+	bus->read = ag7xxx_mdio_read;
+	bus->write = ag7xxx_mdio_write;
+	snprintf(bus->name, sizeof(bus->name), dev->name);
+
+	bus->priv = (void *)priv;
+
+	return mdio_register(bus);
+}
+
+static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
+{
+	int offset;
+
+	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy");
+	if (offset <= 0) {
+		debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
+		return -EINVAL;
+	}
+
+	offset = fdt_parent_offset(gd->fdt_blob, offset);
+	if (offset <= 0) {
+		debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
+		      __func__, offset);
+		return -EINVAL;
+	}
+
+	offset = fdt_parent_offset(gd->fdt_blob, offset);
+	if (offset <= 0) {
+		debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
+		      __func__, offset);
+		return -EINVAL;
+	}
+
+	return offset;
+}
+
+static int ag7xxx_eth_probe(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+	void __iomem *iobase, *phyiobase;
+	int ret, phyreg;
+
+	/* Decoding of convoluted PHY wiring on Atheros MIPS. */
+	ret = ag7xxx_get_phy_iface_offset(dev);
+	if (ret <= 0)
+		return ret;
+	phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
+
+	iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
+	phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
+
+	debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
+	      __func__, iobase, phyiobase, priv);
+	priv->regs = iobase;
+	priv->phyregs = phyiobase;
+	priv->interface = pdata->phy_interface;
+	priv->model = dev_get_driver_data(dev);
+
+	ret = ag7xxx_mdio_probe(dev);
+	if (ret)
+		return ret;
+
+	priv->bus = miiphy_get_dev_by_name(dev->name);
+
+	ret = ag7xxx_mac_probe(dev);
+	debug("%s, ret=%d\n", __func__, ret);
+
+	return ret;
+}
+
+static int ag7xxx_eth_remove(struct udevice *dev)
+{
+	struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
+
+	free(priv->phydev);
+	mdio_unregister(priv->bus);
+	mdio_free(priv->bus);
+
+	return 0;
+}
+
+static const struct eth_ops ag7xxx_eth_ops = {
+	.start			= ag7xxx_eth_start,
+	.send			= ag7xxx_eth_send,
+	.recv			= ag7xxx_eth_recv,
+	.free_pkt		= ag7xxx_eth_free_pkt,
+	.stop			= ag7xxx_eth_stop,
+	.write_hwaddr		= ag7xxx_eth_write_hwaddr,
+};
+
+static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	const char *phy_mode;
+	int ret;
+
+	pdata->iobase = dev_get_addr(dev);
+	pdata->phy_interface = -1;
+
+	/* Decoding of convoluted PHY wiring on Atheros MIPS. */
+	ret = ag7xxx_get_phy_iface_offset(dev);
+	if (ret <= 0)
+		return ret;
+
+	phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
+	if (phy_mode)
+		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
+	if (pdata->phy_interface == -1) {
+		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static const struct udevice_id ag7xxx_eth_ids[] = {
+	{ .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
+	{ .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_ag7xxx) = {
+	.name		= "eth_ag7xxx",
+	.id		= UCLASS_ETH,
+	.of_match	= ag7xxx_eth_ids,
+	.ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
+	.probe		= ag7xxx_eth_probe,
+	.remove		= ag7xxx_eth_remove,
+	.ops		= &ag7xxx_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
+};
diff --git a/drivers/net/cpsw-common.c b/drivers/net/cpsw-common.c
new file mode 100644
index 0000000000..e828e85d8b
--- /dev/null
+++ b/drivers/net/cpsw-common.c
@@ -0,0 +1,121 @@
+/*
+ * CPSW common - libs used across TI ethernet devices.
+ *
+ * Copyright (C) 2016, Texas Instruments, Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <cpsw.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CTRL_MAC_REG(offset, id) ((offset) + 0x8 * (id))
+
+static int davinci_emac_3517_get_macid(struct udevice *dev, u16 offset,
+				       int slave, u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lsb;
+	u32 macid_msb;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lsb = readl(addr);
+	macid_msb = readl(addr + 4);
+
+	mac_addr[0] = (macid_msb >> 16) & 0xff;
+	mac_addr[1] = (macid_msb >> 8)  & 0xff;
+	mac_addr[2] = macid_msb & 0xff;
+	mac_addr[3] = (macid_lsb >> 16) & 0xff;
+	mac_addr[4] = (macid_lsb >> 8)  & 0xff;
+	mac_addr[5] = macid_lsb & 0xff;
+
+	return 0;
+}
+
+static int cpsw_am33xx_cm_get_macid(struct udevice *dev, u16 offset, int slave,
+				    u8 *mac_addr)
+{
+	void *fdt = (void *)gd->fdt_blob;
+	int node = dev->of_offset;
+	u32 macid_lo;
+	u32 macid_hi;
+	fdt32_t gmii = 0;
+	int syscon;
+	u32 addr;
+
+	syscon = fdtdec_lookup_phandle(fdt, node, "syscon");
+	if (syscon < 0) {
+		error("Syscon offset not found\n");
+		return -ENOENT;
+	}
+
+	addr = (u32)map_physmem(fdt_translate_address(fdt, syscon, &gmii),
+				sizeof(u32), MAP_NOCACHE);
+	if (addr == FDT_ADDR_T_NONE) {
+		error("Not able to get syscon address to get mac efuse address\n");
+		return -ENOENT;
+	}
+
+	addr += CTRL_MAC_REG(offset, slave);
+
+	/* try reading mac address from efuse */
+	macid_lo = readl(addr);
+	macid_hi = readl(addr + 4);
+
+	mac_addr[5] = (macid_lo >> 8) & 0xff;
+	mac_addr[4] = macid_lo & 0xff;
+	mac_addr[3] = (macid_hi >> 24) & 0xff;
+	mac_addr[2] = (macid_hi >> 16) & 0xff;
+	mac_addr[1] = (macid_hi >> 8) & 0xff;
+	mac_addr[0] = macid_hi & 0xff;
+
+	return 0;
+}
+
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr)
+{
+	if (of_machine_is_compatible("ti,dm8148"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am33xx"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,am3517-emac"))
+		return davinci_emac_3517_get_macid(dev, 0x110, slave, mac_addr);
+
+	if (of_device_is_compatible(dev, "ti,dm816-emac"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x30, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,am4372"))
+		return cpsw_am33xx_cm_get_macid(dev, 0x630, slave, mac_addr);
+
+	if (of_machine_is_compatible("ti,dra7"))
+		return davinci_emac_3517_get_macid(dev, 0x514, slave, mac_addr);
+
+	dev_err(dev, "incompatible machine/device type for reading mac address\n");
+	return -ENOENT;
+}
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 7104754463..2ce4ec69f1 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -26,6 +26,7 @@
 #include <phy.h>
 #include <asm/arch/cpu.h>
 #include <dm.h>
+#include <fdt_support.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -965,6 +966,11 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
 	phydev->supported &= supported;
 	phydev->advertising = phydev->supported;
 
+#ifdef CONFIG_DM_ETH
+	if (slave->data->phy_of_handle)
+		phydev->dev->of_offset = slave->data->phy_of_handle;
+#endif
+
 	priv->phydev = phydev;
 	phy_config(phydev);
 
@@ -1137,6 +1143,11 @@ static const struct eth_ops cpsw_eth_ops = {
 	.stop		= cpsw_eth_stop,
 };
 
+static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node)
+{
+	return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL);
+}
+
 static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -1146,9 +1157,8 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 	int node = dev->of_offset;
 	int subnode;
 	int slave_index = 0;
-	uint32_t mac_hi, mac_lo;
-	fdt32_t gmii = 0;
 	int active_slave;
+	int ret;
 
 	pdata->iobase = dev_get_addr(dev);
 	priv->data.version = CPSW_CTRL_VERSION_2;
@@ -1202,29 +1212,52 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 
 		name = fdt_get_name(fdt, subnode, &len);
 		if (!strncmp(name, "mdio", 4)) {
-			priv->data.mdio_base = fdtdec_get_addr(fdt, subnode,
-							       "reg");
+			u32 mdio_base;
+
+			mdio_base = cpsw_get_addr_by_node(fdt, subnode);
+			if (mdio_base == FDT_ADDR_T_NONE) {
+				error("Not able to get MDIO address space\n");
+				return -ENOENT;
+			}
+			priv->data.mdio_base = mdio_base;
 		}
 
 		if (!strncmp(name, "slave", 5)) {
 			u32 phy_id[2];
 
-			if (slave_index >= priv->data.slaves) {
-				printf("error: num slaves and slave nodes did not match\n");
-				return -EINVAL;
-			}
+			if (slave_index >= priv->data.slaves)
+				continue;
 			phy_mode = fdt_getprop(fdt, subnode, "phy-mode", NULL);
 			if (phy_mode)
 				priv->data.slave_data[slave_index].phy_if =
 					phy_get_interface_by_name(phy_mode);
-			fdtdec_get_int_array(fdt, subnode, "phy_id", phy_id, 2);
-			priv->data.slave_data[slave_index].phy_addr = phy_id[1];
+
+			priv->data.slave_data[slave_index].phy_of_handle =
+				fdtdec_lookup_phandle(fdt, subnode,
+						      "phy-handle");
+
+			if (priv->data.slave_data[slave_index].phy_of_handle >= 0) {
+				priv->data.slave_data[slave_index].phy_addr =
+						fdtdec_get_int(gd->fdt_blob,
+							       priv->data.slave_data[slave_index].phy_of_handle,
+							       "reg", -1);
+			} else {
+				fdtdec_get_int_array(fdt, subnode, "phy_id",
+						     phy_id, 2);
+				priv->data.slave_data[slave_index].phy_addr =
+						phy_id[1];
+			}
 			slave_index++;
 		}
 
 		if (!strncmp(name, "cpsw-phy-sel", 12)) {
-			priv->data.gmii_sel = fdtdec_get_addr(fdt, subnode,
-							      "reg");
+			priv->data.gmii_sel = cpsw_get_addr_by_node(fdt,
+								    subnode);
+
+			if (priv->data.gmii_sel == FDT_ADDR_T_NONE) {
+				error("Not able to get gmii_sel reg address\n");
+				return -ENOENT;
+			}
 		}
 	}
 
@@ -1236,20 +1269,11 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		priv->data.slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET;
 	}
 
-	subnode = fdtdec_lookup_phandle(fdt, node, "syscon");
-	priv->data.mac_id = fdt_translate_address((void *)fdt, subnode, &gmii);
-	priv->data.mac_id += AM335X_GMII_SEL_OFFSET;
-	priv->data.mac_id += active_slave * 8;
-
-	/* try reading mac address from efuse */
-	mac_lo = readl(priv->data.mac_id);
-	mac_hi = readl(priv->data.mac_id + 4);
-	pdata->enetaddr[0] = mac_hi & 0xFF;
-	pdata->enetaddr[1] = (mac_hi & 0xFF00) >> 8;
-	pdata->enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
-	pdata->enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
-	pdata->enetaddr[4] = mac_lo & 0xFF;
-	pdata->enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+	ret = ti_cm_get_macid(dev, active_slave, pdata->enetaddr);
+	if (ret < 0) {
+		error("cpsw read efuse mac failed\n");
+		return ret;
+	}
 
 	pdata->phy_interface = priv->data.slave_data[active_slave].phy_if;
 	if (pdata->phy_interface == -1) {
@@ -1270,6 +1294,7 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev)
 		writel(RGMII_MODE_ENABLE, priv->data.gmii_sel);
 		break;
 	}
+
 	return 0;
 }
 
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index ca58f34f13..8858f0768a 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -24,7 +24,12 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 {
+#ifdef CONFIG_DM_ETH
+	struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
 	struct eth_mac_regs *mac_p = bus->priv;
+#endif
 	ulong start;
 	u16 miiaddr;
 	int timeout = CONFIG_MDIO_TIMEOUT;
@@ -47,7 +52,12 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 			u16 val)
 {
+#ifdef CONFIG_DM_ETH
+	struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+#else
 	struct eth_mac_regs *mac_p = bus->priv;
+#endif
 	ulong start;
 	u16 miiaddr;
 	int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
@@ -70,7 +80,41 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
 	return ret;
 }
 
-static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
+#if CONFIG_DM_ETH
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+	struct udevice *dev = bus->priv;
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	struct dw_eth_pdata *pdata = dev_get_platdata(dev);
+	int ret;
+
+	if (!dm_gpio_is_valid(&priv->reset_gpio))
+		return 0;
+
+	/* reset the phy */
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[0]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[1]);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret)
+		return ret;
+
+	udelay(pdata->reset_delays[2]);
+
+	return 0;
+}
+#endif
+
+static int dw_mdio_init(const char *name, void *priv)
 {
 	struct mii_dev *bus = mdio_alloc();
 
@@ -82,8 +126,11 @@ static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
 	bus->read = dw_mdio_read;
 	bus->write = dw_mdio_write;
 	snprintf(bus->name, sizeof(bus->name), "%s", name);
+#ifdef CONFIG_DM_ETH
+	bus->reset = dw_mdio_reset;
+#endif
 
-	bus->priv = (void *)mac_regs_p;
+	bus->priv = priv;
 
 	return mdio_register(bus);
 }
@@ -98,8 +145,8 @@ static void tx_descs_init(struct dw_eth_dev *priv)
 
 	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
-		desc_p->dmamac_next = &desc_table_p[idx + 1];
+		desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 #if defined(CONFIG_DW_ALTDESCRIPTOR)
 		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
@@ -117,11 +164,11 @@ static void tx_descs_init(struct dw_eth_dev *priv)
 	}
 
 	/* Correcting the last pointer of the chain */
-	desc_p->dmamac_next = &desc_table_p[0];
+	desc_p->dmamac_next = (ulong)&desc_table_p[0];
 
 	/* Flush all Tx buffer descriptors at once */
-	flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
-			   (unsigned int)priv->tx_mac_descrtable +
+	flush_dcache_range((ulong)priv->tx_mac_descrtable,
+			   (ulong)priv->tx_mac_descrtable +
 			   sizeof(priv->tx_mac_descrtable));
 
 	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
@@ -142,13 +189,12 @@ static void rx_descs_init(struct dw_eth_dev *priv)
 	 * Otherwise there's a chance to get some of them flushed in RAM when
 	 * GMAC is already pushing data to RAM via DMA. This way incoming from
 	 * GMAC data will be corrupted. */
-	flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
-			   RX_TOTAL_BUFSIZE);
+	flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
 
 	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
 		desc_p = &desc_table_p[idx];
-		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
-		desc_p->dmamac_next = &desc_table_p[idx + 1];
+		desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
 
 		desc_p->dmamac_cntl =
 			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
@@ -158,11 +204,11 @@ static void rx_descs_init(struct dw_eth_dev *priv)
 	}
 
 	/* Correcting the last pointer of the chain */
-	desc_p->dmamac_next = &desc_table_p[0];
+	desc_p->dmamac_next = (ulong)&desc_table_p[0];
 
 	/* Flush all Rx buffer descriptors at once */
-	flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
-			   (unsigned int)priv->rx_mac_descrtable +
+	flush_dcache_range((ulong)priv->rx_mac_descrtable,
+			   (ulong)priv->rx_mac_descrtable +
 			   sizeof(priv->rx_mac_descrtable));
 
 	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
@@ -290,12 +336,11 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 	struct eth_dma_regs *dma_p = priv->dma_regs_p;
 	u32 desc_num = priv->tx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
-	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
-	uint32_t data_end = data_start +
-		roundup(length, ARCH_DMA_MINALIGN);
+	ulong data_start = desc_p->dmamac_addr;
+	ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
 	/*
 	 * Strictly we only need to invalidate the "txrx_status" field
 	 * for the following check, but on some platforms we cannot
@@ -312,7 +357,7 @@ static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
 		return -EPERM;
 	}
 
-	memcpy(desc_p->dmamac_addr, packet, length);
+	memcpy((void *)data_start, packet, length);
 
 	/* Flush data to be sent */
 	flush_dcache_range(data_start, data_end);
@@ -352,11 +397,11 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
 	u32 status, desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
 	int length = -EAGAIN;
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
-	uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
-	uint32_t data_end;
+	ulong data_start = desc_p->dmamac_addr;
+	ulong data_end;
 
 	/* Invalidate entire buffer descriptor */
 	invalidate_dcache_range(desc_start, desc_end);
@@ -372,7 +417,7 @@ static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
 		/* Invalidate received data */
 		data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
 		invalidate_dcache_range(data_start, data_end);
-		*packetp = desc_p->dmamac_addr;
+		*packetp = (uchar *)(ulong)desc_p->dmamac_addr;
 	}
 
 	return length;
@@ -382,8 +427,8 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
 {
 	u32 desc_num = priv->rx_currdescnum;
 	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
-	uint32_t desc_start = (uint32_t)desc_p;
-	uint32_t desc_end = desc_start +
+	ulong desc_start = (ulong)desc_p;
+	ulong desc_end = desc_start +
 		roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
 
 	/*
@@ -488,6 +533,11 @@ int designware_initialize(ulong base_addr, u32 interface)
 		return -ENOMEM;
 	}
 
+	if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
+		printf("designware: buffers are outside DMA memory\n");
+		return -EINVAL;
+	}
+
 	memset(dev, 0, sizeof(struct eth_device));
 	memset(priv, 0, sizeof(struct dw_eth_dev));
 
@@ -583,6 +633,7 @@ static int designware_eth_probe(struct udevice *dev)
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct dw_eth_dev *priv = dev_get_priv(dev);
 	u32 iobase = pdata->iobase;
+	ulong ioaddr;
 	int ret;
 
 #ifdef CONFIG_DM_PCI
@@ -601,12 +652,13 @@ static int designware_eth_probe(struct udevice *dev)
 #endif
 
 	debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
-	priv->mac_regs_p = (struct eth_mac_regs *)iobase;
-	priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
+	ioaddr = iobase;
+	priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
+	priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
 	priv->interface = pdata->phy_interface;
 	priv->max_speed = pdata->max_speed;
 
-	dw_mdio_init(dev->name, priv->mac_regs_p);
+	dw_mdio_init(dev->name, dev);
 	priv->bus = miiphy_get_dev_by_name(dev->name);
 
 	ret = dw_phy_init(priv, dev);
@@ -637,9 +689,13 @@ static const struct eth_ops designware_eth_ops = {
 
 static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 {
-	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	struct eth_pdata *pdata = &dw_pdata->eth_pdata;
 	const char *phy_mode;
 	const fdt32_t *cell;
+	int reset_flags = GPIOD_IS_OUT;
+	int ret = 0;
 
 	pdata->iobase = dev_get_addr(dev);
 	pdata->phy_interface = -1;
@@ -656,7 +712,20 @@ static int designware_eth_ofdata_to_platdata(struct udevice *dev)
 	if (cell)
 		pdata->max_speed = fdt32_to_cpu(*cell);
 
-	return 0;
+	if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+			    "snps,reset-active-low"))
+		reset_flags |= GPIOD_ACTIVE_LOW;
+
+	ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
+		&priv->reset_gpio, reset_flags);
+	if (ret == 0) {
+		ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+			"snps,reset-delays-us", dw_pdata->reset_delays, 3);
+	} else if (ret == -ENOENT) {
+		ret = 0;
+	}
+
+	return ret;
 }
 
 static const struct udevice_id designware_eth_ids[] = {
@@ -675,7 +744,7 @@ U_BOOT_DRIVER(eth_designware) = {
 	.remove	= designware_eth_remove,
 	.ops	= &designware_eth_ops,
 	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
-	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+	.platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
 	.flags = DM_FLAG_ALLOC_PRIV_DMA,
 };
 
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index ed6344cc28..51ba769cfb 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -8,6 +8,8 @@
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
+#include <asm/gpio.h>
+
 #define CONFIG_TX_DESCR_NUM	16
 #define CONFIG_RX_DESCR_NUM	16
 #define CONFIG_ETH_BUFSIZE	2048
@@ -110,8 +112,8 @@ struct eth_dma_regs {
 struct dmamacdescr {
 	u32 txrx_status;
 	u32 dmamac_cntl;
-	void *dmamac_addr;
-	struct dmamacdescr *dmamac_next;
+	u32 dmamac_addr;
+	u32 dmamac_next;
 } __aligned(ARCH_DMA_MINALIGN);
 
 /*
@@ -232,8 +234,16 @@ struct dw_eth_dev {
 #ifndef CONFIG_DM_ETH
 	struct eth_device *dev;
 #endif
+	struct gpio_desc reset_gpio;
 	struct phy_device *phydev;
 	struct mii_dev *bus;
 };
 
+#ifdef CONFIG_DM_ETH
+struct dw_eth_pdata {
+	struct eth_pdata eth_pdata;
+	u32 reset_delays[3];
+};
+#endif
+
 #endif
diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c
index e2a8ed3919..00cdfd47b8 100644
--- a/drivers/net/fm/fm.c
+++ b/drivers/net/fm/fm.c
@@ -360,7 +360,7 @@ int fm_init_common(int index, struct ccsr_fman *reg)
 	size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
 	void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
 
-	rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
+	rc = nand_read(nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
 		       &fw_length, (u_char *)addr);
 	if (rc == -EUCLEAN) {
 		printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c
index ae5aca4bb4..70887fa45f 100644
--- a/drivers/net/fm/t4240.c
+++ b/drivers/net/fm/t4240.c
@@ -74,7 +74,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
 	if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
 	    ((is_serdes_configured(XFI_FM1_MAC9)) ||
 	     (is_serdes_configured(XFI_FM1_MAC10))))
-		return PHY_INTERFACE_MODE_XGMII;
+		return PHY_INTERFACE_MODE_NONE;
 
 	if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
 	    ((is_serdes_configured(XAUI_FM2_MAC9))	||
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index 16a7512b0c..1da9996986 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -135,14 +135,11 @@ static void pcnet_halt (struct eth_device *dev);
 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
 
 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
-						void *addr, bool uncached)
+						void *addr)
 {
-	pci_dev_t devbusfn = (pci_dev_t)dev->priv;
+	pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
 	void *virt_addr = addr;
 
-	if (uncached)
-		virt_addr = (void *)CKSEG0ADDR(addr);
-
 	return pci_virt_to_mem(devbusfn, virt_addr);
 }
 
@@ -158,6 +155,7 @@ int pcnet_initialize(bd_t *bis)
 	struct eth_device *dev;
 	u16 command, status;
 	int dev_nr = 0;
+	u32 bar;
 
 	PCNET_DEBUG1("\npcnet_initialize...\n");
 
@@ -179,19 +177,18 @@ int pcnet_initialize(bd_t *bis)
 			break;
 		}
 		memset(dev, 0, sizeof(*dev));
-		dev->priv = (void *)devbusfn;
+		dev->priv = (void *)(unsigned long)devbusfn;
 		sprintf(dev->name, "pcnet#%d", dev_nr);
 
 		/*
 		 * Setup the PCI device.
 		 */
-		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0,
-				      (unsigned int *)&dev->iobase);
-		dev->iobase = pci_io_to_phys(devbusfn, dev->iobase);
+		pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);
+		dev->iobase = pci_io_to_phys(devbusfn, bar);
 		dev->iobase &= ~0xf;
 
-		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
-			     dev->name, devbusfn, dev->iobase);
+		PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
+			     dev->name, devbusfn, (unsigned long)dev->iobase);
 
 		command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
 		pci_write_config_word(devbusfn, PCI_COMMAND, command);
@@ -298,7 +295,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 {
 	struct pcnet_uncached_priv *uc;
 	int i, val;
-	u32 addr;
+	unsigned long addr;
 
 	PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
 
@@ -336,16 +333,18 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 * must be aligned on 16-byte boundaries.
 	 */
 	if (lp == NULL) {
-		addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10);
+		addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
 		addr = (addr + 0xf) & ~0xf;
 		lp = (pcnet_priv_t *)addr;
 
-		addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc));
+		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+					       sizeof(*lp->uc));
 		flush_dcache_range(addr, addr + sizeof(*lp->uc));
 		addr = UNCACHED_SDRAM(addr);
 		lp->uc = (struct pcnet_uncached_priv *)addr;
 
-		addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf));
+		addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
+					       sizeof(*lp->rx_buf));
 		flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
 		lp->rx_buf = (void *)addr;
 	}
@@ -361,7 +360,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 */
 	lp->cur_rx = 0;
 	for (i = 0; i < RX_RING_SIZE; i++) {
-		addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false);
+		addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
 		uc->rx_ring[i].base = cpu_to_le32(addr);
 		uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
 		uc->rx_ring[i].status = cpu_to_le16(0x8000);
@@ -393,9 +392,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 
 	uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
 					       RX_RING_LEN_BITS);
-	addr = pcnet_virt_to_mem(dev, uc->rx_ring, true);
+	addr = pcnet_virt_to_mem(dev, uc->rx_ring);
 	uc->init_block.rx_ring = cpu_to_le32(addr);
-	addr = pcnet_virt_to_mem(dev, uc->tx_ring, true);
+	addr = pcnet_virt_to_mem(dev, uc->tx_ring);
 	uc->init_block.tx_ring = cpu_to_le32(addr);
 
 	PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
@@ -406,7 +405,7 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis)
 	 * Tell the controller where the Init Block is located.
 	 */
 	barrier();
-	addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true);
+	addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
 	pcnet_write_csr(dev, 1, addr & 0xffff);
 	pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
 
@@ -464,7 +463,7 @@ static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
 	 * Setup Tx ring. Caution: the write order is important here,
 	 * set the status with the "ownership" bits last.
 	 */
-	addr = pcnet_virt_to_mem(dev, packet, false);
+	addr = pcnet_virt_to_mem(dev, packet);
 	writew(-pkt_len, &entry->length);
 	writel(0, &entry->misc);
 	writel(addr, &entry->base);
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 4b2808eff0..9871cc3edd 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -84,11 +84,14 @@ static int bcm54xx_parse_status(struct phy_device *phydev)
 
 static int bcm54xx_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	bcm54xx_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return bcm54xx_parse_status(phydev);
 }
 
 /* Broadcom BCM5482S */
@@ -139,11 +142,14 @@ static int bcm5482_config(struct phy_device *phydev)
 
 static int bcm_cygnus_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return genphy_parse_link(phydev);
 }
 
 static int bcm_cygnus_config(struct phy_device *phydev)
@@ -239,17 +245,21 @@ static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
  */
 static int bcm5482_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	if (bcm5482_is_serdes(phydev)) {
 		bcm5482_parse_serdes_sr(phydev);
 		phydev->port = PORT_FIBRE;
-	} else {
-		/* Wait for auto-negotiation to complete or fail */
-		genphy_update_link(phydev);
-		/* Parse BCM54xx copper aux status register */
-		bcm54xx_parse_status(phydev);
+		return 0;
 	}
 
-	return 0;
+	/* Wait for auto-negotiation to complete or fail */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	/* Parse BCM54xx copper aux status register */
+	return bcm54xx_parse_status(phydev);
 }
 
 static struct phy_driver BCM5461S_driver = {
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index f975fd8209..fd130d5b82 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -139,8 +139,8 @@ void cs4340_upload_firmware(struct phy_device *phydev)
 	size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
 
 	addr = malloc(CONFIG_CORTINA_FW_LENGTH);
-	ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
-		       &fw_length, (u_char *)addr);
+	ret = nand_read(nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
+			&fw_length, (u_char *)addr);
 	if (ret == -EUCLEAN) {
 		printf("NAND read of Cortina firmware at 0x%x failed %d\n",
 		       CONFIG_CORTINA_FW_ADDR, ret);
diff --git a/drivers/net/phy/davicom.c b/drivers/net/phy/davicom.c
index 0c039fe79f..0a6e4107ba 100644
--- a/drivers/net/phy/davicom.c
+++ b/drivers/net/phy/davicom.c
@@ -60,10 +60,13 @@ static int dm9161_parse_status(struct phy_device *phydev)
 
 static int dm9161_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dm9161_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dm9161_parse_status(phydev);
 }
 
 static struct phy_driver DM9161_driver = {
diff --git a/drivers/net/phy/et1011c.c b/drivers/net/phy/et1011c.c
index 70c15e2f20..2fe01327fa 100644
--- a/drivers/net/phy/et1011c.c
+++ b/drivers/net/phy/et1011c.c
@@ -79,9 +79,13 @@ static int et1011c_parse_status(struct phy_device *phydev)
 
 static int et1011c_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	et1011c_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return et1011c_parse_status(phydev);
 }
 
 static struct phy_driver et1011c_driver = {
diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c
index 91838ce5ea..9abc2a84f9 100644
--- a/drivers/net/phy/lxt.c
+++ b/drivers/net/phy/lxt.c
@@ -49,10 +49,13 @@ static int lxt971_parse_status(struct phy_device *phydev)
 
 static int lxt971_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	lxt971_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return lxt971_parse_status(phydev);
 }
 
 static struct phy_driver LXT971_driver = {
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index b8b1157a0a..d2e68d492a 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -103,7 +103,7 @@ static int m88e1011s_config(struct phy_device *phydev)
 /* Parse the 88E1011's status register for speed and duplex
  * information
  */
-static uint m88e1xxx_parse_status(struct phy_device *phydev)
+static int m88e1xxx_parse_status(struct phy_device *phydev)
 {
 	unsigned int speed;
 	unsigned int mii_reg;
@@ -120,7 +120,7 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev)
 			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 				puts(" TIMEOUT !\n");
 				phydev->link = 0;
-				break;
+				return -ETIMEDOUT;
 			}
 
 			if ((i++ % 1000) == 0)
@@ -162,10 +162,13 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev)
 
 static int m88e1011s_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1111S */
@@ -349,22 +352,21 @@ static int m88e1118_config(struct phy_device *phydev)
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_config_aneg(phydev);
-
-	phy_reset(phydev);
-
-	return 0;
+	return genphy_config_aneg(phydev);
 }
 
 static int m88e1118_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Change Page Number */
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
 
-	genphy_update_link(phydev);
-	m88e1xxx_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1121R */
@@ -421,12 +423,15 @@ static int m88e1145_config(struct phy_device *phydev)
 
 static int m88e1145_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
 			MIIM_88E1145_PHY_LED_DIRECT);
-	m88e1xxx_parse_status(phydev);
-
-	return 0;
+	return m88e1xxx_parse_status(phydev);
 }
 
 /* Marvell 88E1149S */
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 8fcf737cb8..b08788a2b0 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -181,7 +181,12 @@ static struct phy_driver KS8721_driver = {
 static int ksz90xx_startup(struct phy_device *phydev)
 {
 	unsigned phy_ctl;
-	genphy_update_link(phydev);
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
 	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
 
 	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
index 302abe86c6..74d56098b5 100644
--- a/drivers/net/phy/mv88e61xx.c
+++ b/drivers/net/phy/mv88e61xx.c
@@ -1,4 +1,9 @@
 /*
+ * (C) Copyright 2015
+ * Elecsys Corporation <www.elecsyscorp.com>
+ * Kevin Smith <kevin.smith@elecsyscorp.com>
+ *
+ * Original driver:
  * (C) Copyright 2009
  * Marvell Semiconductor <www.marvell.com>
  * Prafulla Wadaskar <prafulla@marvell.com>
@@ -6,532 +11,1007 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+/*
+ * PHY driver for mv88e61xx ethernet switches.
+ *
+ * This driver configures the mv88e61xx for basic use as a PHY.  The switch
+ * supports a VLAN configuration that determines how traffic will be routed
+ * between the ports.  This driver uses a simple configuration that routes
+ * traffic from each PHY port only to the CPU port, and from the CPU port to
+ * any PHY port.
+ *
+ * The configuration determines which PHY ports to activate using the
+ * CONFIG_MV88E61XX_PHY_PORTS bitmask.  Setting bit 0 will activate port 0, bit
+ * 1 activates port 1, etc.  Do not set the bit for the port the CPU is
+ * connected to unless it is connected over a PHY interface (not MII).
+ *
+ * This driver was written for and tested on the mv88e6176 with an SGMII
+ * connection.  Other configurations should be supported, but some additions or
+ * changes may be required.
+ */
+
 #include <common.h>
+
+#include <bitfield.h>
+#include <errno.h>
+#include <malloc.h>
+#include <miiphy.h>
 #include <netdev.h>
-#include "mv88e61xx.h"
+
+#define PHY_AUTONEGOTIATE_TIMEOUT	5000
+
+#define PORT_COUNT			7
+#define PORT_MASK			((1 << PORT_COUNT) - 1)
+
+/* Device addresses */
+#define DEVADDR_PHY(p)			(p)
+#define DEVADDR_PORT(p)			(0x10 + (p))
+#define DEVADDR_SERDES			0x0F
+#define DEVADDR_GLOBAL_1		0x1B
+#define DEVADDR_GLOBAL_2		0x1C
+
+/* SMI indirection registers for multichip addressing mode */
+#define SMI_CMD_REG			0x00
+#define SMI_DATA_REG			0x01
+
+/* Global registers */
+#define GLOBAL1_STATUS			0x00
+#define GLOBAL1_CTRL			0x04
+#define GLOBAL1_MON_CTRL		0x1A
+
+/* Global 2 registers */
+#define GLOBAL2_REG_PHY_CMD		0x18
+#define GLOBAL2_REG_PHY_DATA		0x19
+
+/* Port registers */
+#define PORT_REG_STATUS			0x00
+#define PORT_REG_PHYS_CTRL		0x01
+#define PORT_REG_SWITCH_ID		0x03
+#define PORT_REG_CTRL			0x04
+#define PORT_REG_VLAN_MAP		0x06
+#define PORT_REG_VLAN_ID		0x07
+
+/* Phy registers */
+#define PHY_REG_CTRL1			0x10
+#define PHY_REG_STATUS1			0x11
+#define PHY_REG_PAGE			0x16
+
+/* Serdes registers */
+#define SERDES_REG_CTRL_1		0x10
+
+/* Phy page numbers */
+#define PHY_PAGE_COPPER			0
+#define PHY_PAGE_SERDES			1
+
+/* Register fields */
+#define GLOBAL1_CTRL_SWRESET		BIT(15)
+
+#define GLOBAL1_MON_CTRL_CPUDEST_SHIFT	4
+#define GLOBAL1_MON_CTRL_CPUDEST_WIDTH	4
+
+#define PORT_REG_STATUS_LINK		BIT(11)
+#define PORT_REG_STATUS_DUPLEX		BIT(10)
+
+#define PORT_REG_STATUS_SPEED_SHIFT	8
+#define PORT_REG_STATUS_SPEED_WIDTH	2
+#define PORT_REG_STATUS_SPEED_10	0
+#define PORT_REG_STATUS_SPEED_100	1
+#define PORT_REG_STATUS_SPEED_1000	2
+
+#define PORT_REG_STATUS_CMODE_MASK		0xF
+#define PORT_REG_STATUS_CMODE_100BASE_X		0x8
+#define PORT_REG_STATUS_CMODE_1000BASE_X	0x9
+#define PORT_REG_STATUS_CMODE_SGMII		0xa
+
+#define PORT_REG_PHYS_CTRL_LINK_VALUE	BIT(5)
+#define PORT_REG_PHYS_CTRL_LINK_FORCE	BIT(4)
+
+#define PORT_REG_CTRL_PSTATE_SHIFT	0
+#define PORT_REG_CTRL_PSTATE_WIDTH	2
+
+#define PORT_REG_VLAN_ID_DEF_VID_SHIFT	0
+#define PORT_REG_VLAN_ID_DEF_VID_WIDTH	12
+
+#define PORT_REG_VLAN_MAP_TABLE_SHIFT	0
+#define PORT_REG_VLAN_MAP_TABLE_WIDTH	11
+
+#define SERDES_REG_CTRL_1_FORCE_LINK	BIT(10)
+
+#define PHY_REG_CTRL1_ENERGY_DET_SHIFT	8
+#define PHY_REG_CTRL1_ENERGY_DET_WIDTH	2
+
+/* Field values */
+#define PORT_REG_CTRL_PSTATE_DISABLED	0
+#define PORT_REG_CTRL_PSTATE_FORWARD	3
+
+#define PHY_REG_CTRL1_ENERGY_DET_OFF	0
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY	2
+#define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT	3
+
+/* PHY Status Register */
+#define PHY_REG_STATUS1_SPEED		0xc000
+#define PHY_REG_STATUS1_GBIT		0x8000
+#define PHY_REG_STATUS1_100		0x4000
+#define PHY_REG_STATUS1_DUPLEX		0x2000
+#define PHY_REG_STATUS1_SPDDONE		0x0800
+#define PHY_REG_STATUS1_LINK		0x0400
+#define PHY_REG_STATUS1_ENERGY		0x0010
 
 /*
- * Uncomment either of the following line for local debug control;
- * otherwise global debug control will apply.
+ * Macros for building commands for indirect addressing modes.  These are valid
+ * for both the indirect multichip addressing mode and the PHY indirection
+ * required for the writes to any PHY register.
  */
+#define SMI_BUSY			BIT(15)
+#define SMI_CMD_CLAUSE_22		BIT(12)
+#define SMI_CMD_CLAUSE_22_OP_READ	(2 << 10)
+#define SMI_CMD_CLAUSE_22_OP_WRITE	(1 << 10)
+
+#define SMI_CMD_READ			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_READ)
+#define SMI_CMD_WRITE			(SMI_BUSY | SMI_CMD_CLAUSE_22 | \
+					 SMI_CMD_CLAUSE_22_OP_WRITE)
+
+#define SMI_CMD_ADDR_SHIFT		5
+#define SMI_CMD_ADDR_WIDTH		5
+#define SMI_CMD_REG_SHIFT		0
+#define SMI_CMD_REG_WIDTH		5
+
+/* Check for required macros */
+#ifndef CONFIG_MV88E61XX_PHY_PORTS
+#error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
+	to activate
+#endif
+#ifndef CONFIG_MV88E61XX_CPU_PORT
+#error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
+#endif
 
-/* #undef DEBUG */
-/* #define DEBUG */
+/* ID register values for different switch models */
+#define PORT_SWITCH_ID_6172		0x1720
+#define PORT_SWITCH_ID_6176		0x1760
+#define PORT_SWITCH_ID_6240		0x2400
+#define PORT_SWITCH_ID_6352		0x3520
 
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-/* Chip Address mode
- * The Switch support two modes of operation
- * 1. single chip mode and
- * 2. Multi-chip mode
- * Refer section 9.2 &9.3 in chip datasheet-02 for more details
- *
- * By default single chip mode is configured
- * multichip mode operation can be configured in board header
- */
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr)
+struct mv88e61xx_phy_priv {
+	struct mii_dev *mdio_bus;
+	int smi_addr;
+	int id;
+};
+
+static inline int smi_cmd(int cmd, int addr, int reg)
 {
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
+	cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
+			       addr);
+	cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
+	return cmd;
+}
 
-	/* Poll till SMIBusy bit is clear */
-	do {
-		miiphy_read(name, devaddr, 0x0, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & (1 << 15));
-	return 0;
+static inline int smi_cmd_read(int addr, int reg)
+{
+	return smi_cmd(SMI_CMD_READ, addr, reg);
 }
 
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
+static inline int smi_cmd_write(int addr, int reg)
 {
-	u16 mii_dev_addr;
+	return smi_cmd(SMI_CMD_WRITE, addr, reg);
+}
 
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write data to Switch indirect data register */
-	miiphy_write(name, mii_dev_addr, 0x1, data);
-	/* Write command to Switch indirect command register (write) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 <<
-									 15));
+__weak int mv88e61xx_hw_reset(struct phy_device *phydev)
+{
+	return 0;
 }
 
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
+/* Wait for the current SMI indirect command to complete */
+static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
 {
-	u16 mii_dev_addr;
+	int val;
+	u32 timeout = 100;
 
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) {
-		printf("Error..could not read PHY dev address\n");
-		return;
-	}
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Write command to Switch indirect command register (read) */
-	miiphy_write(name, mii_dev_addr, 0x0,
-		     reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 <<
-									 15));
-	mv88e61xx_busychk_multic(name, mii_dev_addr);
-	/* Read data from Switch indirect data register */
-	miiphy_read(name, mii_dev_addr, 0x1, data);
+	do {
+		val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
+
+		mdelay(1);
+	} while (--timeout);
+
+	puts("SMI busy timeout\n");
+	return -ETIMEDOUT;
 }
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
 
 /*
- * Convenience macros for switch device/port reads/writes
- * These macros output valid 'mv88e61xx' U_BOOT_CMDs
+ * The mv88e61xx has three types of addresses: the smi bus address, the device
+ * address, and the register address.  The smi bus address distinguishes it on
+ * the smi bus from other PHYs or switches.  The device address determines
+ * which on-chip register set you are reading/writing (the various PHYs, their
+ * associated ports, or global configuration registers).  The register address
+ * is the offset of the register you are reading/writing.
+ *
+ * When the mv88e61xx is hardware configured to have address zero, it behaves in
+ * single-chip addressing mode, where it responds to all SMI addresses, using
+ * the smi address as its device address.  This obviously only works when this
+ * is the only chip on the SMI bus.  This allows the driver to access device
+ * registers without using indirection.  When the chip is configured to a
+ * non-zero address, it only responds to that SMI address and requires indirect
+ * writes to access the different device addresses.
  */
-
-#ifndef DEBUG
-#define WR_SWITCH_REG wr_switch_reg
-#define RD_SWITCH_REG rd_switch_reg
-#define WR_SWITCH_PORT_REG(n, p, r, d) \
-	WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#define RD_SWITCH_PORT_REG(n, p, r, d) \
-	RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d)
-#else
-static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data)
+static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
 {
-	printf("mv88e61xx %s dev %02x reg %02x write %04x\n",
-		name, dev_adr, reg_ofs, data);
-	wr_switch_reg(name, dev_adr, reg_ofs, data);
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
+
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0)
+		return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
+
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Issue the read command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+			 smi_cmd_read(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for the read command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Read the data */
+	res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
+	if (res < 0)
+		return res;
+
+	return bitfield_extract(res, 0, 16);
 }
-static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data)
+
+/* See the comment above mv88e61xx_reg_read */
+static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
+			       u16 val)
 {
-	rd_switch_reg(name, dev_adr, reg_ofs, data);
-	printf("mv88e61xx %s dev %02x reg %02x read %04x\n",
-		name, dev_adr, reg_ofs, *data);
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+	struct mii_dev *mdio_bus = priv->mdio_bus;
+	int smi_addr = priv->smi_addr;
+	int res;
+
+	/* In single-chip mode, the device can be addressed directly */
+	if (smi_addr == 0) {
+		return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
+				val);
+	}
+
+	/* Wait for the bus to become free */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	/* Set the data to write */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
+				SMI_DATA_REG, val);
+	if (res < 0)
+		return res;
+
+	/* Issue the write command */
+	res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
+				smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for the write command to complete */
+	res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
+	if (res < 0)
+		return res;
+
+	return 0;
 }
-static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 data)
+
+static int mv88e61xx_phy_wait(struct phy_device *phydev)
 {
-	printf("mv88e61xx %s port %02x reg %02x write %04x\n",
-		name, prt_adr, reg_ofs, data);
-	wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
+	int val;
+	u32 timeout = 100;
+
+	do {
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+					 GLOBAL2_REG_PHY_CMD);
+		if (val >= 0 && (val & SMI_BUSY) == 0)
+			return 0;
+
+		mdelay(1);
+	} while (--timeout);
+
+	return -ETIMEDOUT;
 }
-static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs,
-	u16 *data)
+
+static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg)
 {
-	rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data);
-	printf("mv88e61xx %s port %02x reg %02x read %04x\n",
-		name, prt_adr, reg_ofs, *data);
+	struct phy_device *phydev;
+	int res;
+
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Issue command to read */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_read(dev, reg));
+
+	/* Wait for data to be read */
+	res = mv88e61xx_phy_wait(phydev);
+	if (res < 0)
+		return res;
+
+	/* Read retrieved data */
+	return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA);
 }
-#endif
 
-/*
- * Local functions to read/write registers on the switch PHYs.
- * NOTE! This goes through switch, not direct miiphy, writes and reads!
- */
+static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
+		int devad, int reg, u16 data)
+{
+	struct phy_device *phydev;
+	int res;
+
+	phydev = (struct phy_device *)smi_wrapper->priv;
+
+	/* Set the data to write */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_DATA, data);
+	if (res < 0)
+		return res;
+	/* Issue the write command */
+	res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2,
+				  GLOBAL2_REG_PHY_CMD,
+				  smi_cmd_write(dev, reg));
+	if (res < 0)
+		return res;
+
+	/* Wait for command to complete */
+	return mv88e61xx_phy_wait(phydev);
+}
 
-/*
- * Make sure SMIBusy bit cleared before another
- * SMI operation can take place
- */
-static int mv88e61xx_busychk(char *name)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
 {
-	u16 reg = 0;
-	u32 timeout = MV88E61XX_PHY_TIMEOUT;
-	do {
-		rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR,
-		       MV88E61XX_PHY_CMD, &reg);
-		if (timeout-- == 0) {
-			printf("SMI busy timeout\n");
-			return -1;
-		}
-	} while (reg & 1 << 15);	/* busy mask */
-	return 0;
+	return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
+					   MDIO_DEVAD_NONE, reg);
 }
 
-static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy,
-	u32 reg, u16 data)
+/* Wrapper function to make calls to phy_read_indirect simpler */
+static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
+		int reg, u16 val)
 {
-	/* write switch data reg then cmd reg then check completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA,
-		data);
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_WRITE_CMD | (phy << 5)  | reg));
-	return mv88e61xx_busychk(name);
+	return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
+					    MDIO_DEVAD_NONE, reg, val);
 }
 
-static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy,
-	u32 reg, u16 *data)
+static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
 {
-	/* write switch cmd reg, check for completion */
-	wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD,
-		(MV88E61XX_PHY_READ_CMD | (phy << 5)  | reg));
-	if (mv88e61xx_busychk(name))
-		return -1;
-	/* read switch data reg and return success */
-	rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data);
-	return 0;
+	return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg);
 }
 
-/*
- * Convenience macros for switch PHY reads/writes
- */
+static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
+								u16 val)
+{
+	return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val);
+}
 
-#ifndef DEBUG
-#define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write
-#define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read
-#else
-static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data)
-{
-	int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x write %04x\n",
-			name, phy_adr, reg_ofs, data);
-	return r;
+static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
+{
+	return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
 }
-static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data)
+
+static int mv88e61xx_get_switch_id(struct phy_device *phydev)
 {
-	int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data);
-	if (r)
-		printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n",
-			name, phy_adr, reg_ofs);
-	else
-		printf("mv88e61xx %s phy %02x reg %02x read %04x\n",
-			name, phy_adr, reg_ofs, *data);
-	return r;
+	int res;
+
+	res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
+	if (res < 0)
+		return res;
+	return res & 0xfff0;
 }
-#endif
 
-static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig)
-{
-	u32 prt;
-	u16 reg;
-	char *name = swconfig->name;
-	u32 port_mask = swconfig->ports_enabled;
-
-	/* apply internal vlan config */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		/* only for enabled ports */
-		if ((1 << prt) & port_mask) {
-			/* take vlan map from swconfig */
-			u8 vlanmap = swconfig->vlancfg[prt];
-			/* remove disabled ports from vlan map */
-			vlanmap &= swconfig->ports_enabled;
-			/* apply vlan map to port */
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, &reg);
-			reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1);
-			reg |= vlanmap;
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VMAP_REG, reg);
-		}
+static bool mv88e61xx_6352_family(struct phy_device *phydev)
+{
+	struct mv88e61xx_phy_priv *priv = phydev->priv;
+
+	switch (priv->id) {
+	case PORT_SWITCH_ID_6172:
+	case PORT_SWITCH_ID_6176:
+	case PORT_SWITCH_ID_6240:
+	case PORT_SWITCH_ID_6352:
+		return true;
 	}
+	return false;
 }
 
-/*
- * Power up the specified port and reset PHY
- */
-static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
 {
-	char *name = swconfig->name;
+	int res;
 
-	/* Write Copper Specific control reg1 (0x10) for-
-	 * Enable Phy power up
-	 * Energy Detect on (sense&Xmit NLP Periodically
-	 * reset other settings default
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360))
-		return -1;
+	res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (res < 0)
+		return res;
+	return res & PORT_REG_STATUS_CMODE_MASK;
+}
 
-	/* Write PHY ctrl reg (0x0) to apply
-	 * Phy reset (set bit 15 low)
-	 * reset other default values
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140))
-		return -1;
+static int mv88e61xx_parse_status(struct phy_device *phydev)
+{
+	unsigned int speed;
+	unsigned int mii_reg;
+
+	mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
+
+	if ((mii_reg & PHY_REG_STATUS1_LINK) &&
+	    !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+		int i = 0;
+
+		puts("Waiting for PHY realtime link");
+		while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
+			/* Timeout reached ? */
+			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+				puts(" TIMEOUT !\n");
+				phydev->link = 0;
+				break;
+			}
+
+			if ((i++ % 1000) == 0)
+				putc('.');
+			udelay(1000);
+			mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
+					PHY_REG_STATUS1);
+		}
+		puts(" done\n");
+		udelay(500000);	/* another 500 ms (results in faster booting) */
+	} else {
+		if (mii_reg & PHY_REG_STATUS1_LINK)
+			phydev->link = 1;
+		else
+			phydev->link = 0;
+	}
+
+	if (mii_reg & PHY_REG_STATUS1_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
+
+	speed = mii_reg & PHY_REG_STATUS1_SPEED;
+
+	switch (speed) {
+	case PHY_REG_STATUS1_GBIT:
+		phydev->speed = SPEED_1000;
+		break;
+	case PHY_REG_STATUS1_100:
+		phydev->speed = SPEED_100;
+		break;
+	default:
+		phydev->speed = SPEED_10;
+		break;
+	}
 
 	return 0;
 }
 
-/*
- * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3)
- * is set to "On-1000Mb/s Link, Off Else"
- * This function sets it to "On-Link, Blink-Activity, Off-NoLink"
- *
- * This is optional settings may be needed on some boards
- * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s
- * Link status
- */
-static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_switch_reset(struct phy_device *phydev)
 {
-	char *name = swconfig->name;
+	int time;
+	int val;
+	u8 port;
+
+	/* Disable all ports */
+	for (port = 0; port < PORT_COUNT; port++) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+		if (val < 0)
+			return val;
+		val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+				       PORT_REG_CTRL_PSTATE_WIDTH,
+				       PORT_REG_CTRL_PSTATE_DISABLED);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+		if (val < 0)
+			return val;
+	}
 
-	if (swconfig->led_init != MV88E61XX_LED_INIT_EN)
-		return 0;
+	/* Wait 2 ms for queues to drain */
+	udelay(2000);
+
+	/* Reset switch */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL);
+	if (val < 0)
+		return val;
+	val |= GLOBAL1_CTRL_SWRESET;
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_CTRL, val);
+	if (val < 0)
+		return val;
+
+	/* Wait up to 1 second for switch reset complete */
+	for (time = 1000; time; time--) {
+		val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1,
+					    GLOBAL1_CTRL);
+		if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
+			break;
+		udelay(1000);
+	}
+	if (!time)
+		return -ETIMEDOUT;
 
-	/* set page address to 3 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003))
-		return -1;
+	return 0;
+}
 
-	/*
-	 * set LED Func Ctrl reg
-	 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink
-	 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001))
-		return -1;
+static int mv88e61xx_serdes_init(struct phy_device *phydev)
+{
+	int val;
 
-	/* set page address to 0 */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000))
-		return -1;
+	val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
+	if (val < 0)
+		return val;
+
+	/* Power up serdes module */
+	val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
+	if (val < 0)
+		return val;
 
 	return 0;
 }
 
-/*
- * Reverse Transmit polarity for Media Dependent Interface
- * Pins (MDIP) bits in Copper Specific Control Register 3
- * (Page 0, Reg 20 for each phy (except cpu port)
- * Reference: Section 1.1 Switch datasheet-3
- *
- * This is optional settings may be needed on some boards
- * for PHY<->magnetics h/w tuning
- */
-static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy)
+static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
 {
-	char *name = swconfig->name;
+	int val;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
+			       PORT_REG_CTRL_PSTATE_WIDTH,
+			       PORT_REG_CTRL_PSTATE_FORWARD);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
+	if (val < 0)
+		return val;
 
-	if (swconfig->mdip != MV88E61XX_MDIP_REVERSE)
-		return 0;
+	return 0;
+}
 
-	/*Reverse MDIP/N[3:0] bits */
-	if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f))
-		return -1;
+static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
+							u8 mask)
+{
+	int val;
+
+	/* Set VID to port number plus one */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
+			       PORT_REG_VLAN_ID_DEF_VID_WIDTH,
+			       port + 1);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
+	if (val < 0)
+		return val;
+
+	/* Set VID mask */
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
+			       PORT_REG_VLAN_MAP_TABLE_WIDTH,
+			       mask);
+	val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
+	if (val < 0)
+		return val;
 
 	return 0;
 }
 
-/*
- * Marvell 88E61XX Switch initialization
- */
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig)
+static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
 {
-	u32 prt;
-	u16 reg;
-	char *idstr;
-	char *name = swconfig->name;
-	int time;
-
-	if (miiphy_set_current_dev(name)) {
-		printf("%s failed\n", __FUNCTION__);
-		return -1;
+	int res;
+	int val;
+	bool forced = false;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
+	if (val < 0)
+		return val;
+	if (!(val & PORT_REG_STATUS_LINK)) {
+		/* Temporarily force link to read port configuration */
+		u32 timeout = 100;
+		forced = true;
+
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
+
+		/* Wait for status register to reflect forced link */
+		do {
+			val = mv88e61xx_port_read(phydev, port,
+						  PORT_REG_STATUS);
+			if (val < 0)
+				goto unforce;
+			if (val & PORT_REG_STATUS_LINK)
+				break;
+		} while (--timeout);
+
+		if (timeout == 0) {
+			res = -ETIMEDOUT;
+			goto unforce;
+		}
 	}
 
-	if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) {
-		swconfig->cpuport = (1 << 5);
-		printf("Invalid cpu port config, using default port5\n");
-	}
+	if (val & PORT_REG_STATUS_DUPLEX)
+		phydev->duplex = DUPLEX_FULL;
+	else
+		phydev->duplex = DUPLEX_HALF;
 
-	RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, &reg);
-	switch (reg &= 0xfff0) {
-	case 0x1610:
-		idstr = "88E6161";
-		break;
-	case 0x1650:
-		idstr = "88E6165";
+	val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
+			       PORT_REG_STATUS_SPEED_WIDTH);
+	switch (val) {
+	case PORT_REG_STATUS_SPEED_1000:
+		phydev->speed = SPEED_1000;
 		break;
-	case 0x1210:
-		idstr = "88E6123";
-		/* ports 2,3,4 not available */
-		swconfig->ports_enabled &= 0x023;
+	case PORT_REG_STATUS_SPEED_100:
+		phydev->speed = SPEED_100;
 		break;
 	default:
-		/* Could not detect switch id */
-		idstr = "88E61??";
+		phydev->speed = SPEED_10;
 		break;
 	}
 
-	/* be sure all ports are disabled */
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-		RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, &reg);
-		reg &= ~0x3;
-		WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg);
+	res = 0;
+
+unforce:
+	if (forced) {
+		val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+		if (val < 0)
+			return val;
+		val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
+				PORT_REG_PHYS_CTRL_LINK_VALUE);
+		val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+					   val);
+		if (val < 0)
+			return val;
 	}
 
-	/* wait 2 ms for queues to drain */
-	udelay(2000);
-
-	/* reset switch */
-	RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, &reg);
-	reg |= 0x8000;
-	WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg);
+	return res;
+}
 
-	/* wait up to 1 second for switch reset complete */
-	for (time = 1000; time; time--) {
-		RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR,
-			&reg);
-		if ((reg & 0xc800) == 0xc800)
-			break;
-		udelay(1000);
-	}
-	if (!time)
-		return -1;
-
-	/* Port based VLANs configuration */
-	mv88e61xx_port_vlan_config(swconfig);
-
-	if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) {
-		/*
-		 * Enable RGMII delay on Tx and Rx for CPU port
-		 * Ref: sec 9.5 of chip datasheet-02
-		 */
-		/*Force port link down */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10);
-		/* configure port RGMII delay */
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7);
-		RD_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, 5,
-			MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18);
-		WR_SWITCH_PORT_REG(name, 4,
-			MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7);
-		/* Force port to RGMII FDX 1000Base then up */
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e);
-		WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e);
+static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
+{
+	int val;
+
+	/* Set CPUDest */
+	val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
+			       GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
+			       CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1,
+				     GLOBAL1_MON_CTRL, val);
+	if (val < 0)
+		return val;
+
+	/* Allow CPU to route to any port */
+	val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
+	val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
+	if (val < 0)
+		return val;
+
+	/* Enable CPU port */
+	val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	/* If CPU is connected to serdes, initialize serdes */
+	if (mv88e61xx_6352_family(phydev)) {
+		val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
+		if (val < 0)
+			return val;
+		if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_1000BASE_X ||
+		    val == PORT_REG_STATUS_CMODE_SGMII) {
+			val = mv88e61xx_serdes_init(phydev);
+			if (val < 0)
+				return val;
+		}
 	}
 
-	for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) {
-
-		/* configure port's PHY */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			/* port 4 has phy 6, not 4 */
-			int phy = (prt == 4) ? 6 : prt;
-			if (mv88361xx_powerup(swconfig, phy))
-				return -1;
-			if (mv88361xx_reverse_mdipn(swconfig, phy))
-				return -1;
-			if (mv88361xx_led_init(swconfig, phy))
-				return -1;
-		}
+	return 0;
+}
 
-		/* set port VID to port+1 except for cpu port */
-		if (!((1 << prt) & swconfig->cpuport)) {
-			RD_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG, &reg);
-			WR_SWITCH_PORT_REG(name, prt,
-				MV88E61XX_PRT_VID_REG,
-				(reg & ~1023) | (prt+1));
-		}
+static int mv88e61xx_switch_init(struct phy_device *phydev)
+{
+	static int init;
+	int res;
 
-		/*Program port state */
-		RD_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG, &reg);
-		WR_SWITCH_PORT_REG(name, prt,
-			MV88E61XX_PRT_CTRL_REG,
-			reg | (swconfig->portstate & 0x03));
+	if (init)
+		return 0;
 
-	}
+	res = mv88e61xx_switch_reset(phydev);
+	if (res < 0)
+		return res;
+
+	res = mv88e61xx_set_cpu_port(phydev);
+	if (res < 0)
+		return res;
+
+	init = 1;
 
-	printf("%s Initialized on %s\n", idstr, name);
 	return 0;
 }
 
-#ifdef CONFIG_MV88E61XX_CMD
-static int
-do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
 {
-	char *name, *endp;
-	int write = 0;
-	enum { dev, prt, phy } target = dev;
-	u32 addrlo, addrhi, addr;
-	u32 reglo, reghi, reg;
-	u16 data, rdata;
+	int val;
 
-	if (argc < 7)
-		return -1;
+	val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
+	if (val < 0)
+		return val;
+	val &= ~(BMCR_PDOWN);
+	val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
+	if (val < 0)
+		return val;
 
-	name = argv[1];
+	return 0;
+}
 
-	if (strcmp(argv[2], "phy") == 0)
-		target = phy;
-	else if (strcmp(argv[2], "port") == 0)
-		target = prt;
-	else if (strcmp(argv[2], "dev") != 0)
-		return 1;
+static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
+{
+	int val;
 
-	addrlo = simple_strtoul(argv[3], &endp, 16);
+	/*
+	 * Enable energy-detect sensing on PHY, used to determine when a PHY
+	 * port is physically connected
+	 */
+	val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
+	if (val < 0)
+		return val;
+	val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT,
+			       PHY_REG_CTRL1_ENERGY_DET_WIDTH,
+			       PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT);
+	val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
+	if (val < 0)
+		return val;
 
-	if (!*endp) {
-		addrhi = addrlo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		addrhi = simple_strtoul(endp, NULL, 16);
-	}
+	return 0;
+}
 
-	reglo = simple_strtoul(argv[5], &endp, 16);
-	if (!*endp) {
-		reghi = reglo;
-	} else {
-		while (*endp < '0' || *endp > '9')
-			endp++;
-		reghi = simple_strtoul(endp, NULL, 16);
+static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
+{
+	int val;
+
+	val = mv88e61xx_port_enable(phydev, phy);
+	if (val < 0)
+		return val;
+
+	val = mv88e61xx_port_set_vlan(phydev, phy,
+			1 << CONFIG_MV88E61XX_CPU_PORT);
+	if (val < 0)
+		return val;
+
+	return 0;
+}
+
+static int mv88e61xx_probe(struct phy_device *phydev)
+{
+	struct mii_dev *smi_wrapper;
+	struct mv88e61xx_phy_priv *priv;
+	int res;
+
+	res = mv88e61xx_hw_reset(phydev);
+	if (res < 0)
+		return res;
+
+	priv = malloc(sizeof(*priv));
+	if (!priv)
+		return -ENOMEM;
+
+	memset(priv, 0, sizeof(*priv));
+
+	/*
+	 * This device requires indirect reads/writes to the PHY registers
+	 * which the generic PHY code can't handle.  Make a wrapper MII device
+	 * to handle reads/writes
+	 */
+	smi_wrapper = mdio_alloc();
+	if (!smi_wrapper) {
+		free(priv);
+		return -ENOMEM;
 	}
 
-	if (strcmp(argv[6], "write") == 0)
-		write = 1;
-	else if (strcmp(argv[6], "read") != 0)
-		return 1;
-
-	data = simple_strtoul(argv[7], NULL, 16);
-
-	for (addr = addrlo; addr <= addrhi; addr++) {
-		for (reg = reglo; reg <= reghi; reg++) {
-			if (write) {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_write(
-						name, addr, reg, data);
-				else if (target == prt)
-					wr_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, data);
-				else
-					wr_switch_reg(name, addr, reg, data);
-			} else {
-				if (target == phy)
-					mv88e61xx_switch_miiphy_read(
-						name, addr, reg, &rdata);
-				else if (target == prt)
-					rd_switch_reg(name,
-						addr+MV88E61XX_PRT_OFST,
-						reg, &rdata);
-				else
-					rd_switch_reg(name, addr, reg, &rdata);
-				printf("%s %s %s %02x %s %02x %s %04x\n",
-					argv[0], argv[1], argv[2], addr,
-					argv[4], reg, argv[6], rdata);
-				if (write && argc == 7 && rdata != data)
-					return 1;
+	/*
+	 * Store the mdio bus in the private data, as we are going to replace
+	 * the bus with the wrapper bus
+	 */
+	priv->mdio_bus = phydev->bus;
+
+	/*
+	 * Store the smi bus address in private data.  This lets us use the
+	 * phydev addr field for device address instead, as the genphy code
+	 * expects.
+	 */
+	priv->smi_addr = phydev->addr;
+
+	/*
+	 * Store the phy_device in the wrapper mii device. This lets us get it
+	 * back when genphy functions call phy_read/phy_write.
+	 */
+	smi_wrapper->priv = phydev;
+	strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
+	smi_wrapper->read = mv88e61xx_phy_read_indirect;
+	smi_wrapper->write = mv88e61xx_phy_write_indirect;
+
+	/* Replace the bus with the wrapper device */
+	phydev->bus = smi_wrapper;
+
+	phydev->priv = priv;
+
+	priv->id = mv88e61xx_get_switch_id(phydev);
+
+	return 0;
+}
+
+static int mv88e61xx_phy_config(struct phy_device *phydev)
+{
+	int res;
+	int i;
+	int ret = -1;
+
+	res = mv88e61xx_switch_init(phydev);
+	if (res < 0)
+		return res;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+
+			res = mv88e61xx_phy_enable(phydev, i);
+			if (res < 0) {
+				printf("Error enabling PHY %i\n", i);
+				continue;
+			}
+			res = mv88e61xx_phy_setup(phydev, i);
+			if (res < 0) {
+				printf("Error setting up PHY %i\n", i);
+				continue;
 			}
+			res = mv88e61xx_phy_config_port(phydev, i);
+			if (res < 0) {
+				printf("Error configuring PHY %i\n", i);
+				continue;
+			}
+
+			res = genphy_config_aneg(phydev);
+			if (res < 0) {
+				printf("Error setting PHY %i autoneg\n", i);
+				continue;
+			}
+			res = phy_reset(phydev);
+			if (res < 0) {
+				printf("Error resetting PHY %i\n", i);
+				continue;
+			}
+
+			/* Return success if any PHY succeeds */
+			ret = 0;
 		}
 	}
+
+	return ret;
+}
+
+static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
+{
+	int val;
+
+	val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
+	if (val < 0)
+		return 0;
+
+	/*
+	 * After reset, the energy detect signal remains high for a few seconds
+	 * regardless of whether a cable is connected.  This function will
+	 * return false positives during this time.
+	 */
+	return (val & PHY_REG_STATUS1_ENERGY) == 0;
+}
+
+static int mv88e61xx_phy_startup(struct phy_device *phydev)
+{
+	int i;
+	int link = 0;
+	int res;
+	int speed = phydev->speed;
+	int duplex = phydev->duplex;
+
+	for (i = 0; i < PORT_COUNT; i++) {
+		if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
+			phydev->addr = i;
+			if (!mv88e61xx_phy_is_connected(phydev))
+				continue;
+			res = genphy_update_link(phydev);
+			if (res < 0)
+				continue;
+			res = mv88e61xx_parse_status(phydev);
+			if (res < 0)
+				continue;
+			link = (link || phydev->link);
+		}
+	}
+	phydev->link = link;
+
+	/* Restore CPU interface speed and duplex after it was changed for
+	 * other ports */
+	phydev->speed = speed;
+	phydev->duplex = duplex;
+
+	return 0;
+}
+
+static struct phy_driver mv88e61xx_driver = {
+	.name = "Marvell MV88E61xx",
+	.uid = 0x01410eb1,
+	.mask = 0xfffffff0,
+	.features = PHY_GBIT_FEATURES,
+	.probe = mv88e61xx_probe,
+	.config = mv88e61xx_phy_config,
+	.startup = mv88e61xx_phy_startup,
+	.shutdown = &genphy_shutdown,
+};
+
+int phy_mv88e61xx_init(void)
+{
+	phy_register(&mv88e61xx_driver);
+
 	return 0;
 }
 
-U_BOOT_CMD(mv88e61xx, 8, 0, do_switch,
-	"Read or write mv88e61xx switch registers",
-	"<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n"
-	"<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n"
-	"    - read/write switch device, port or phy at (addr,reg)\n"
-	"      addr=0..0x1C for dev, 0..5 for port or phy.\n"
-	"      reg=0..0x1F.\n"
-	"      data=0..0xFFFF (tested if present against actual read).\n"
-	"      All numeric parameters are assumed to be hex.\n"
-	"      <addr> and <<reg> arguments can be ranges (x..y)"
-);
-#endif /* CONFIG_MV88E61XX_CMD */
+/*
+ * Overload weak get_phy_id definition since we need non-standard functions
+ * to read PHY registers
+ */
+int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
+{
+	struct phy_device temp_phy;
+	struct mv88e61xx_phy_priv temp_priv;
+	struct mii_dev temp_mii;
+	int val;
+
+	/*
+	 * Buid temporary data structures that the chip reading code needs to
+	 * read the ID
+	 */
+	temp_priv.mdio_bus = bus;
+	temp_priv.smi_addr = smi_addr;
+	temp_phy.priv = &temp_priv;
+	temp_mii.priv = &temp_phy;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id = val << 16;
+
+	val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
+	if (val < 0)
+		return -EIO;
+
+	*phy_id |= (val & 0xffff);
+
+	return 0;
+}
diff --git a/drivers/net/phy/mv88e61xx.h b/drivers/net/phy/mv88e61xx.h
deleted file mode 100644
index 9c62e4a775..0000000000
--- a/drivers/net/phy/mv88e61xx.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _MV88E61XX_H
-#define _MV88E61XX_H
-
-#include <miiphy.h>
-
-#define MV88E61XX_CPU_PORT		0x5
-
-#define MV88E61XX_PHY_TIMEOUT		100000
-
-/* port dev-addr (= port + 0x10) */
-#define MV88E61XX_PRT_OFST		0x10
-/* port registers */
-#define MV88E61XX_PCS_CTRL_REG		0x1
-#define MV88E61XX_PRT_CTRL_REG		0x4
-#define MV88E61XX_PRT_VMAP_REG		0x6
-#define MV88E61XX_PRT_VID_REG		0x7
-#define MV88E61XX_RGMII_TIMECTRL_REG	0x1A
-
-/* global registers dev-addr */
-#define MV88E61XX_GLBREG_DEVADR	0x1B
-/* global registers */
-#define MV88E61XX_SGSR			0x00
-#define MV88E61XX_SGCR			0x04
-
-/* global 2 registers dev-addr */
-#define MV88E61XX_GLB2REG_DEVADR	0x1C
-/* global 2 registers */
-#define MV88E61XX_PHY_CMD		0x18
-#define MV88E61XX_PHY_DATA		0x19
-/* global 2 phy commands */
-#define MV88E61XX_PHY_WRITE_CMD		0x9400
-#define MV88E61XX_PHY_READ_CMD		0x9800
-
-#define MV88E61XX_BUSY_OFST		15
-#define MV88E61XX_MODE_OFST		12
-#define MV88E61XX_OP_OFST		10
-#define MV88E61XX_ADDR_OFST		5
-
-#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
-static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
-static void mv88e61xx_switch_write(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 data);
-static void mv88e61xx_switch_read(char *name, u32 phy_adr,
-	u32 reg_ofs, u16 *data);
-#define wr_switch_reg mv88e61xx_switch_write
-#define rd_switch_reg mv88e61xx_switch_read
-#else
-/* switch appears a s simple PHY and can thus use miiphy */
-#define wr_switch_reg miiphy_write
-#define rd_switch_reg miiphy_read
-#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
-
-#endif /* _MV88E61XX_H */
diff --git a/drivers/net/phy/natsemi.c b/drivers/net/phy/natsemi.c
index d2e4c3c487..1592e9b7b9 100644
--- a/drivers/net/phy/natsemi.c
+++ b/drivers/net/phy/natsemi.c
@@ -93,10 +93,13 @@ static int dp83865_parse_status(struct phy_device *phydev)
 
 static int dp83865_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83865_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83865_parse_status(phydev);
 }
 
 
@@ -134,10 +137,13 @@ static int dp83848_parse_status(struct phy_device *phydev)
 
 static int dp83848_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	dp83848_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return dp83848_parse_status(phydev);
 }
 
 static struct phy_driver DP83848_driver = {
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 23c82bb36e..80bdfb6d9d 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -248,7 +248,7 @@ int genphy_update_link(struct phy_device *phydev)
 			if (i > PHY_ANEG_TIMEOUT) {
 				printf(" TIMEOUT !\n");
 				phydev->link = 0;
-				return 0;
+				return -ETIMEDOUT;
 			}
 
 			if (ctrlc()) {
@@ -431,10 +431,13 @@ int genphy_config(struct phy_device *phydev)
 
 int genphy_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 int genphy_shutdown(struct phy_device *phydev)
@@ -458,6 +461,9 @@ static LIST_HEAD(phy_drivers);
 
 int phy_init(void)
 {
+#ifdef CONFIG_MV88E61XX_SWITCH
+	phy_mv88e61xx_init();
+#endif
 #ifdef CONFIG_PHY_AQUANTIA
 	phy_aquantia_init();
 #endif
@@ -876,9 +882,7 @@ __weak int board_phy_config(struct phy_device *phydev)
 int phy_config(struct phy_device *phydev)
 {
 	/* Invoke an optional board-specific helper */
-	board_phy_config(phydev);
-
-	return 0;
+	return board_phy_config(phydev);
 }
 
 int phy_shutdown(struct phy_device *phydev)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 9d7f55bdae..7a99cb0234 100644
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -208,28 +208,38 @@ static int rtl8211f_parse_status(struct phy_device *phydev)
 
 static int rtl8211x_startup(struct phy_device *phydev)
 {
+	int ret;
+
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211x_parse_status(phydev);
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 
-	return 0;
+	return rtl8211x_parse_status(phydev);
 }
 
 static int rtl8211e_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	genphy_parse_link(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return genphy_parse_link(phydev);
 }
 
 static int rtl8211f_startup(struct phy_device *phydev)
 {
+	int ret;
+
+	/* Read the Status (2x to make sure link is right) */
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
 	/* Read the Status (2x to make sure link is right) */
-	genphy_update_link(phydev);
-	rtl8211f_parse_status(phydev);
 
-	return 0;
+	return rtl8211f_parse_status(phydev);
 }
 
 /* Support for RTL8211B PHY */
diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index 34986a29fc..313fcdfdc5 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -34,9 +34,13 @@ static int smsc_parse_status(struct phy_device *phydev)
 
 static int smsc_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	smsc_parse_status(phydev);
-	return 0;
+	int ret;
+
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+
+	return smsc_parse_status(phydev);
 }
 
 static struct phy_driver lan8700_driver = {
diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c
index 937426bc85..c55dd973f4 100644
--- a/drivers/net/phy/ti.c
+++ b/drivers/net/phy/ti.c
@@ -6,6 +6,14 @@
  */
 #include <common.h>
 #include <phy.h>
+#include <linux/compat.h>
+#include <malloc.h>
+
+#include <fdtdec.h>
+#include <dm.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* TI DP83867 */
 #define DP83867_DEVADDR		0x1f
@@ -71,6 +79,17 @@
 #define MII_MMD_CTRL_INCR_RDWT	0x8000 /* post increment on reads & writes */
 #define MII_MMD_CTRL_INCR_ON_WT	0xC000 /* post increment on writes only */
 
+/* User setting - can be taken from DTS */
+#define DEFAULT_RX_ID_DELAY	DP83867_RGMIIDCTL_2_25_NS
+#define DEFAULT_TX_ID_DELAY	DP83867_RGMIIDCTL_2_75_NS
+#define DEFAULT_FIFO_DEPTH	DP83867_PHYCR_FIFO_DEPTH_4_B_NIB
+
+struct dp83867_private {
+	int rx_id_delay;
+	int tx_id_delay;
+	int fifo_depth;
+};
+
 /**
  * phy_read_mmd_indirect - reads data from the MMD registers
  * @phydev: The PHY device bus
@@ -137,27 +156,60 @@ void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
 	phy_write(phydev, addr, MII_MMD_DATA, data);
 }
 
+#if defined(CONFIG_DM_ETH)
 /**
- * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
- * is RGMII (all variants)
+ * dp83867_data_init - Convenience function for setting PHY specific data
+ *
  * @phydev: the phy_device struct
  */
-static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+static int dp83867_of_init(struct phy_device *phydev)
 {
-	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
-		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+	struct dp83867_private *dp83867 = phydev->priv;
+	struct udevice *dev = phydev->dev;
+
+	dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,rx-internal-delay", -1);
+
+	dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,tx-internal-delay", -1);
+
+	dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+				 "ti,fifo-depth", -1);
+
+	return 0;
 }
+#else
+static int dp83867_of_init(struct phy_device *phydev)
+{
+	struct dp83867_private *dp83867 = phydev->priv;
 
-/* User setting - can be taken from DTS */
-#define RX_ID_DELAY	8
-#define TX_ID_DELAY	0xa
-#define FIFO_DEPTH	1
+	dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY;
+	dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY;
+	dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
+
+	return 0;
+}
+#endif
 
 static int dp83867_config(struct phy_device *phydev)
 {
+	struct dp83867_private *dp83867;
 	unsigned int val, delay, cfg2;
 	int ret;
 
+	if (!phydev->priv) {
+		dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL);
+		if (!dp83867)
+			return -ENOMEM;
+
+		phydev->priv = dp83867;
+		ret = dp83867_of_init(phydev);
+		if (ret)
+			goto err_out;
+	} else {
+		dp83867 = (struct dp83867_private *)phydev->priv;
+	}
+
 	/* Restart the PHY.  */
 	val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL);
 	phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL,
@@ -166,10 +218,10 @@ static int dp83867_config(struct phy_device *phydev)
 	if (phy_interface_is_rgmii(phydev)) {
 		ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL,
 			(DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) |
-			(FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
+			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
 		if (ret)
-			return ret;
-	} else {
+			goto err_out;
+	} else if (phy_interface_is_sgmii(phydev)) {
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
 			  (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000));
 
@@ -189,8 +241,8 @@ static int dp83867_config(struct phy_device *phydev)
 			  DP83867_PHYCTRL_SGMIIEN |
 			  (DP83867_MDI_CROSSOVER_MDIX <<
 			  DP83867_MDI_CROSSOVER) |
-			  (FIFO_DEPTH << DP83867_PHYCTRL_RXFIFO_SHIFT) |
-			  (FIFO_DEPTH  << DP83867_PHYCTRL_TXFIFO_SHIFT));
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) |
+			  (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT));
 		phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0);
 	}
 
@@ -212,8 +264,8 @@ static int dp83867_config(struct phy_device *phydev)
 		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 				       DP83867_DEVADDR, phydev->addr, val);
 
-		delay = (RX_ID_DELAY |
-			 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
+		delay = (dp83867->rx_id_delay |
+			 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 
 		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 				       DP83867_DEVADDR, phydev->addr, delay);
@@ -221,6 +273,10 @@ static int dp83867_config(struct phy_device *phydev)
 
 	genphy_config_aneg(phydev);
 	return 0;
+
+err_out:
+	kfree(dp83867);
+	return ret;
 }
 
 static struct phy_driver DP83867_driver = {
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 941d0760b5..2635b821e9 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -112,10 +112,12 @@ static int vitesse_parse_status(struct phy_device *phydev)
 
 static int vitesse_startup(struct phy_device *phydev)
 {
-	genphy_update_link(phydev);
-	vitesse_parse_status(phydev);
+	int ret;
 
-	return 0;
+	ret = genphy_update_link(phydev);
+	if (ret)
+		return ret;
+	return vitesse_parse_status(phydev);
 }
 
 static int cis8204_config(struct phy_device *phydev)
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 5862bf0a7e..7b85aa0463 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -250,7 +250,7 @@ static void emaclite_stop(struct udevice *dev)
 
 static int setup_phy(struct udevice *dev)
 {
-	int i;
+	int i, ret;
 	u16 phyreg;
 	struct xemaclite *emaclite = dev_get_priv(dev);
 	struct phy_device *phydev;
@@ -302,7 +302,9 @@ static int setup_phy(struct udevice *dev)
 	phydev->advertising = supported;
 	emaclite->phydev = phydev;
 	phy_config(phydev);
-	phy_startup(phydev);
+	ret = phy_startup(phydev);
+	if (ret)
+		return ret;
 
 	if (!phydev->link) {
 		printf("%s: No link.\n", phydev->dev->name);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index aec8077f10..519699d8ff 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -179,6 +179,7 @@ struct zynq_gem_priv {
 	struct zynq_gem_regs *iobase;
 	phy_interface_t interface;
 	struct phy_device *phydev;
+	int phy_of_handle;
 	struct mii_dev *bus;
 };
 
@@ -352,14 +353,17 @@ static int zynq_phy_init(struct udevice *dev)
 	priv->phydev->supported = supported | ADVERTISED_Pause |
 				  ADVERTISED_Asym_Pause;
 	priv->phydev->advertising = priv->phydev->supported;
-	phy_config(priv->phydev);
 
-	return 0;
+	if (priv->phy_of_handle > 0)
+		priv->phydev->dev->of_offset = priv->phy_of_handle;
+
+	return phy_config(priv->phydev);
 }
 
 static int zynq_gem_init(struct udevice *dev)
 {
 	u32 i, nwconfig;
+	int ret;
 	unsigned long clk_rate = 0;
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
 	struct zynq_gem_regs *regs = priv->iobase;
@@ -427,7 +431,9 @@ static int zynq_gem_init(struct udevice *dev)
 		priv->init++;
 	}
 
-	phy_startup(priv->phydev);
+	ret = phy_startup(priv->phydev);
+	if (ret)
+		return ret;
 
 	if (!priv->phydev->link) {
 		printf("%s: No link.\n", priv->phydev->dev->name);
@@ -675,7 +681,6 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 {
 	struct eth_pdata *pdata = dev_get_platdata(dev);
 	struct zynq_gem_priv *priv = dev_get_priv(dev);
-	int offset = 0;
 	const char *phy_mode;
 
 	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
@@ -684,10 +689,11 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
 	priv->emio = 0;
 	priv->phyaddr = -1;
 
-	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
-				       "phy-handle");
-	if (offset > 0)
-		priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
+	priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
+					dev->of_offset, "phy-handle");
+	if (priv->phy_of_handle > 0)
+		priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
+					priv->phy_of_handle, "reg", -1);
 
 	phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
 	if (phy_mode)
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 0ba960e248..2e6b986dbc 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -569,7 +569,7 @@ static void fdt_fixup_pcie(void *blob)
 	unsigned char header_type;
 	int index;
 	u32 streamid;
-	pci_dev_t dev;
+	pci_dev_t dev, bdf;
 	int bus;
 	unsigned short id;
 	struct pci_controller *hose;
@@ -611,12 +611,15 @@ static void fdt_fixup_pcie(void *blob)
 					continue;
 				}
 
+				/* the DT fixup must be relative to the hose first_busno */
+				bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
+
 				/* map PCI b.d.f to streamID in LUT */
-				ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+				ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
 							streamid);
 
 				/* update msi-map in device tree */
-				fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+				fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 							   streamid);
 			}
 		}
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 567b7662d0..1785e3b28c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -163,5 +163,6 @@ endif
 
 source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/uniphier/Kconfig"
+source "drivers/pinctrl/exynos/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index b99ed2f191..7f946814d3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PINCTRL_SANDBOX)	+= pinctrl-sandbox.o
 
 obj-$(CONFIG_PINCTRL_UNIPHIER)	+= uniphier/
 obj-$(CONFIG_PIC32_PINCTRL)	+= pinctrl_pic32.o
+obj-$(CONFIG_PINCTRL_EXYNOS)	+= exynos/
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
new file mode 100644
index 0000000000..84b6aaae09
--- /dev/null
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -0,0 +1,10 @@
+config PINCTRL_EXYNOS
+	bool
+
+config PINCTRL_EXYNOS7420
+	bool "Samsung Exynos7420 pinctrl driver"
+	depends on ARCH_EXYNOS && PINCTRL_FULL
+	select PINCTRL_EXYNOS
+	help
+	  Support pin multiplexing and pin configuration control on
+	  Samsung's Exynos7420 SoC.
diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile
new file mode 100644
index 0000000000..d9b941ac67
--- /dev/null
+++ b/drivers/pinctrl/exynos/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Samsung Electronics
+# Thomas Abraham <thomas.ab@samsung.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_PINCTRL_EXYNOS)		+= pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_EXYNOS7420)	+= pinctrl-exynos7420.o
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c
new file mode 100644
index 0000000000..a28405fc15
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.c
@@ -0,0 +1,141 @@
+/*
+ * Exynos pinctrl driver common code.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * exynos_pinctrl_setup_peri: setup pinctrl for a peripheral.
+ * conf: soc specific pin configuration data array
+ * num_conf: number of configurations in the conf array.
+ * base: base address of the pin controller.
+ */
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+		unsigned int num_conf, unsigned long base)
+{
+	unsigned int idx, val;
+
+	for (idx = 0; idx < num_conf; idx++) {
+		val = readl(base + conf[idx].offset);
+		val &= ~(conf[idx].mask);
+		val |= conf[idx].value;
+		writel(val, base + conf[idx].offset);
+	}
+}
+
+/* given a pin-name, return the address of pin config registers */
+static unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
+						u32 *pin)
+{
+	struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+	const struct samsung_pin_ctrl *pin_ctrl = priv->pin_ctrl;
+	const struct samsung_pin_bank_data *bank_data = pin_ctrl->pin_banks;
+	u32 nr_banks = pin_ctrl->nr_banks, idx = 0;
+	char bank[10];
+
+	/*
+	 * The format of the pin name is <bank name>-<pin_number>.
+	 * Example: gpa0-4 (gpa0 is the bank name and 4 is the pin number.
+	 */
+	while (pin_name[idx] != '-') {
+		bank[idx] = pin_name[idx];
+		idx++;
+	}
+	bank[idx] = '\0';
+	*pin = pin_name[++idx] - '0';
+
+	/* lookup the pin bank data using the pin bank name */
+	for (idx = 0; idx < nr_banks; idx++)
+		if (!strcmp(bank, bank_data[idx].name))
+			break;
+
+	return priv->base + bank_data[idx].offset;
+}
+
+/**
+ * exynos_pinctrl_set_state: configure a pin state.
+ * dev: the pinctrl device to be configured.
+ * config: the state to be configured.
+ */
+int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+	const void *fdt = gd->fdt_blob;
+	int node = config->of_offset;
+	unsigned int count, idx, pin_num, ret;
+	unsigned int pinfunc, pinpud, pindrv;
+	unsigned long reg, value;
+	const char *name;
+
+	/*
+	 * refer to the following document for the pinctrl bindings
+	 * linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
+	 */
+	count = fdt_count_strings(fdt, node, "samsung,pins");
+	if (count <= 0)
+		return -EINVAL;
+
+	pinfunc = fdtdec_get_int(fdt, node, "samsung,pin-function", -1);
+	pinpud = fdtdec_get_int(fdt, node, "samsung,pin-pud", -1);
+	pindrv = fdtdec_get_int(fdt, node, "samsung,pin-drv", -1);
+
+	for (idx = 0; idx < count; idx++) {
+		ret = fdt_get_string_index(fdt, node, "samsung,pins",
+						idx, &name);
+		if (ret < 0)
+			continue;
+		reg = pin_to_bank_base(dev, name, &pin_num);
+
+		if (pinfunc != -1) {
+			value = readl(reg + PIN_CON);
+			value &= ~(0xf << (pin_num << 2));
+			value |= (pinfunc << (pin_num << 2));
+			writel(value, reg + PIN_CON);
+		}
+
+		if (pinpud != -1) {
+			value = readl(reg + PIN_PUD);
+			value &= ~(0x3 << (pin_num << 1));
+			value |= (pinpud << (pin_num << 1));
+			writel(value, reg + PIN_PUD);
+		}
+
+		if (pindrv != -1) {
+			value = readl(reg + PIN_DRV);
+			value &= ~(0x3 << (pin_num << 1));
+			value |= (pindrv << (pin_num << 1));
+			writel(value, reg + PIN_DRV);
+		}
+	}
+
+	return 0;
+}
+
+int exynos_pinctrl_probe(struct udevice *dev)
+{
+	struct exynos_pinctrl_priv *priv;
+	fdt_addr_t base;
+
+	priv = dev_get_priv(dev);
+	if (!priv)
+		return -EINVAL;
+
+	base = dev_get_addr(dev);
+	if (base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = base;
+	priv->pin_ctrl = (struct samsung_pin_ctrl *)dev_get_driver_data(dev) +
+				dev->req_seq;
+
+	return 0;
+}
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h
new file mode 100644
index 0000000000..abd582d318
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos.h
@@ -0,0 +1,77 @@
+/*
+ * Exynos pinctrl driver header.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PINCTRL_EXYNOS_H_
+#define __PINCTRL_EXYNOS__H_
+
+#define PIN_CON		0x00	/* Offset of pin function register */
+#define PIN_DAT		0x04	/* Offset of pin data register */
+#define PIN_PUD		0x08	/* Offset of pin pull up/down config register */
+#define PIN_DRV		0x0C	/* Offset of pin drive strength register */
+
+/**
+ * struct samsung_pin_bank_data: represent a controller pin-bank data.
+ * @offset: starting offset of the pin-bank registers.
+ * @nr_pins: number of pins included in this bank.
+ * @name: name to be prefixed for each pin in this pin bank.
+ */
+struct samsung_pin_bank_data {
+	u32		offset;
+	u8		nr_pins;
+	const char	*name;
+};
+
+#define EXYNOS_PIN_BANK(pins, reg, id)			\
+	{						\
+		.offset	= reg,				\
+		.nr_pins	= pins,			\
+		.name		= id			\
+	}
+
+/**
+ * struct samsung_pin_ctrl: represent a pin controller.
+ * @pin_banks: list of pin banks included in this controller.
+ * @nr_banks: number of pin banks.
+ */
+struct samsung_pin_ctrl {
+	const struct samsung_pin_bank_data *pin_banks;
+	u32 nr_banks;
+};
+
+/**
+ * struct exynos_pinctrl_priv: exynos pin controller driver private data
+ * @pin_ctrl: pin controller bank information.
+ * @base: base address of the pin controller instance.
+ * @num_banks: number of pin banks included in the pin controller.
+ */
+struct exynos_pinctrl_priv {
+	const struct samsung_pin_ctrl *pin_ctrl;
+	unsigned long base;
+	int num_banks;
+};
+
+/**
+ * struct exynos_pinctrl_config_data: configuration for a peripheral.
+ * @offset: offset of the config registers in the controller.
+ * @mask: value of the register to be masked with.
+ * @value: new value to be programmed.
+ */
+struct exynos_pinctrl_config_data {
+	const unsigned int	offset;
+	const unsigned int	mask;
+	const unsigned int	value;
+};
+
+
+void exynos_pinctrl_setup_peri(struct exynos_pinctrl_config_data *conf,
+		unsigned int num_conf, unsigned long base);
+int exynos_pinctrl_set_state(struct udevice *dev,
+		struct udevice *config);
+int exynos_pinctrl_probe(struct udevice *dev);
+
+#endif /* __PINCTRL_EXYNOS_H_ */
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos7420.c b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
new file mode 100644
index 0000000000..8ae5ce776a
--- /dev/null
+++ b/drivers/pinctrl/exynos/pinctrl-exynos7420.c
@@ -0,0 +1,120 @@
+/*
+ * Exynos7420 pinctrl driver.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <dm/pinctrl.h>
+#include <dm/root.h>
+#include <fdtdec.h>
+#include <asm/arch/pinmux.h>
+#include "pinctrl-exynos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	GPD1_OFFSET	0xc0
+
+static struct exynos_pinctrl_config_data serial2_conf[] = {
+	{
+		.offset	= GPD1_OFFSET + PIN_CON,
+		.mask	= 0x00ff0000,
+		.value	= 0x00220000,
+	}, {
+		.offset	= GPD1_OFFSET + PIN_PUD,
+		.mask	= 0x00000f00,
+		.value	= 0x00000f00,
+	},
+};
+
+static int exynos7420_pinctrl_request(struct udevice *dev, int peripheral,
+						int flags)
+{
+	struct exynos_pinctrl_priv *priv = dev_get_priv(dev);
+	unsigned long base = priv->base;
+
+	switch (PERIPH_ID_UART2) {
+	case PERIPH_ID_UART2:
+		exynos_pinctrl_setup_peri(serial2_conf,
+					  ARRAY_SIZE(serial2_conf), base);
+		break;
+	default:
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static struct pinctrl_ops exynos7420_pinctrl_ops = {
+	.set_state	= exynos_pinctrl_set_state,
+	.request	= exynos7420_pinctrl_request,
+};
+
+/* pin banks of Exynos7420 pin-controller - BUS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks0[] = {
+	EXYNOS_PIN_BANK(5, 0x000, "gpb0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpc0"),
+	EXYNOS_PIN_BANK(2, 0x040, "gpc1"),
+	EXYNOS_PIN_BANK(6, 0x060, "gpc2"),
+	EXYNOS_PIN_BANK(8, 0x080, "gpc3"),
+	EXYNOS_PIN_BANK(4, 0x0a0, "gpd0"),
+	EXYNOS_PIN_BANK(6, 0x0c0, "gpd1"),
+	EXYNOS_PIN_BANK(8, 0x0e0, "gpd2"),
+	EXYNOS_PIN_BANK(5, 0x100, "gpd4"),
+	EXYNOS_PIN_BANK(4, 0x120, "gpd5"),
+	EXYNOS_PIN_BANK(6, 0x140, "gpd6"),
+	EXYNOS_PIN_BANK(3, 0x160, "gpd7"),
+	EXYNOS_PIN_BANK(2, 0x180, "gpd8"),
+	EXYNOS_PIN_BANK(2, 0x1a0, "gpg0"),
+	EXYNOS_PIN_BANK(4, 0x1c0, "gpg3"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS0 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks1[] = {
+	EXYNOS_PIN_BANK(7, 0x000, "gpr4"),
+};
+
+/* pin banks of Exynos7420 pin-controller - FSYS1 */
+static const struct samsung_pin_bank_data exynos7420_pin_banks2[] = {
+	EXYNOS_PIN_BANK(4, 0x000, "gpr0"),
+	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
+	EXYNOS_PIN_BANK(5, 0x040, "gpr2"),
+	EXYNOS_PIN_BANK(8, 0x060, "gpr3"),
+};
+
+const struct samsung_pin_ctrl exynos7420_pin_ctrl[] = {
+	{
+		/* pin-controller instance BUS0 data */
+		.pin_banks	= exynos7420_pin_banks0,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks0),
+	}, {
+		/* pin-controller instance FSYS0 data */
+		.pin_banks	= exynos7420_pin_banks1,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks1),
+	}, {
+		/* pin-controller instance FSYS1 data */
+		.pin_banks	= exynos7420_pin_banks2,
+		.nr_banks	= ARRAY_SIZE(exynos7420_pin_banks2),
+	},
+};
+
+static const struct udevice_id exynos7420_pinctrl_ids[] = {
+	{ .compatible = "samsung,exynos7420-pinctrl",
+		.data = (ulong)exynos7420_pin_ctrl },
+	{ }
+};
+
+U_BOOT_DRIVER(pinctrl_exynos7420) = {
+	.name		= "pinctrl_exynos7420",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= exynos7420_pinctrl_ids,
+	.priv_auto_alloc_size = sizeof(struct exynos_pinctrl_priv),
+	.ops		= &exynos7420_pinctrl_ops,
+	.probe		= exynos_pinctrl_probe,
+	.flags		= DM_FLAG_PRE_RELOC
+};
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index ccc5d309d6..fd04b26454 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -287,5 +287,6 @@ static int pinctrl_post_bind(struct udevice *dev)
 UCLASS_DRIVER(pinctrl) = {
 	.id = UCLASS_PINCTRL,
 	.post_bind = pinctrl_post_bind,
+	.flags = DM_UC_FLAG_SEQ_ALIAS,
 	.name = "pinctrl",
 };
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
index 7c769bdb01..1fa1daa939 100644
--- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -623,7 +623,7 @@ static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
 {
 	const void *blob = gd->fdt_blob;
 	int pcfg_node, ret, flags, count, i;
-	u32 cell[40], *ptr;
+	u32 cell[60], *ptr;
 
 	debug("%s: %s %s\n", __func__, dev->name, config->name);
 	ret = fdtdec_get_int_array_count(blob, config->of_offset,
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 3c41bca32a..3c44167805 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -41,9 +41,17 @@ config AXP221_POWER
 	Select this to enable support for the axp221/axp223 pmic found on most
 	A23 and A31 boards.
 
+config AXP809_POWER
+	boolean "axp809 pmic support"
+	depends on MACH_SUN9I
+	select CMD_POWEROFF
+	---help---
+	Say y here to enable support for the axp809 pmic found on A80 boards.
+
 config AXP818_POWER
 	boolean "axp818 pmic support"
 	depends on MACH_SUN8I_A83T
+	select CMD_POWEROFF
 	---help---
 	Say y here to enable support for the axp818 pmic found on
 	A83T dev board.
@@ -59,36 +67,39 @@ endchoice
 
 config AXP_DCDC1_VOLT
 	int "axp pmic dcdc1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 3300 if AXP818_POWER
-	default 3000 if MACH_SUN6I || MACH_SUN8I
+	default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to
 	disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for
 	generic 3.3V IO voltage for external devices like the lcd-panal and
 	sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
-	safe battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
-	dcdc1 is used for VCC-IO, nand, usb0, sd , etc.
+	save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
+	dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally
+	powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG.
 
 config AXP_DCDC2_VOLT
 	int "axp pmic dcdc2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 900 if AXP818_POWER
 	default 1400 if AXP152_POWER || AXP209_POWER
 	default 1200 if MACH_SUN6I
 	default 1100 if MACH_SUN8I
+	default 0 if MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to
 	disable dcdc2.
 	On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
 	On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
 	On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
+	On A80 boards dcdc2 powers the GPU and can be left off.
 	On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 
 config AXP_DCDC3_VOLT
 	int "axp pmic dcdc3 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
-	default 900 if AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 900 if AXP809_POWER || AXP818_POWER
 	default 1500 if AXP152_POWER
 	default 1250 if AXP209_POWER
 	default 1200 if MACH_SUN6I || MACH_SUN8I
@@ -99,51 +110,55 @@ config AXP_DCDC3_VOLT
 	should be 1.25V.
 	On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
 	On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
+	On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V.
 	On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V.
 
 config AXP_DCDC4_VOLT
 	int "axp pmic dcdc4 voltage"
-	depends on AXP152_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 1250 if AXP152_POWER
 	default 1200 if MACH_SUN6I
 	default 0 if MACH_SUN8I
+	default 900 if MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to
 	disable dcdc4.
 	On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V.
 	On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V.
 	On A23 / A33 boards dcdc4 is unused and should be disabled.
+	On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V.
 	On A83T boards dcdc4 is used for VDD-GPU.
 
 config AXP_DCDC5_VOLT
 	int "axp pmic dcdc5 voltage"
-	depends on AXP221_POWER || AXP818_POWER
-	default 1500 if MACH_SUN6I || MACH_SUN8I
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to
 	disable dcdc5.
-	On A23 / A31 / A33 / A83T boards dcdc5 is VCC-DRAM and should be 1.5V,
-	1.35V if DDR3L is used.
+	On A23 / A31 / A33 / A80 / A83T boards dcdc5 is VCC-DRAM and
+	should be 1.5V, 1.35V if DDR3L is used.
 
 config AXP_ALDO1_VOLT
 	int "axp pmic (a)ldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0 if MACH_SUN6I
 	default 1800 if MACH_SUN8I_A83T
-	default 3000 if MACH_SUN8I
+	default 3000 if MACH_SUN8I || MACH_SUN9I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to
 	disable aldo1.
 	On A31 boards aldo1 is often used to power the wifi module.
 	On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
+	On A80 boards aldo1 powers the USB hosts and should be 3.0V.
 	On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and
 	should be 1.8V.
 
 config AXP_ALDO2_VOLT
 	int "axp pmic (a)ldo2 voltage"
-	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP818_POWER
+	depends on AXP152_POWER || AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 3000 if AXP152_POWER || AXP209_POWER
-	default 0 if MACH_SUN6I
+	default 0 if MACH_SUN6I || MACH_SUN9I
 	default 1800 if MACH_SUN8I_A83T
 	default 2500 if MACH_SUN8I
 	---help---
@@ -153,19 +168,21 @@ config AXP_ALDO2_VOLT
 	On A31 boards aldo2 is typically unused and should be disabled.
 	On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
 	On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V.
+	On A80 boards aldo2 powers PB pingroup and camera IO and can be left off.
 	On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC,
 	LPDDR2, and the codec. It should be 1.8V.
 
 config AXP_ALDO3_VOLT
 	int "axp pmic (a)ldo3 voltage"
-	depends on AXP209_POWER || AXP221_POWER || AXP818_POWER
-	default 0 if AXP209_POWER
+	depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 0 if AXP209_POWER || MACH_SUN9I
 	default 3000 if MACH_SUN6I || MACH_SUN8I
 	---help---
 	Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to
 	disable aldo3.
 	On A10(s) / A13 / A20 boards aldo3 should be 2.8V.
 	On A23 / A31 / A33 boards aldo3 is VCC-PLL and AVCC and should be 3.0V.
+	On A80 boards aldo3 is normally not used.
 	On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
 	3.0V.
 
@@ -180,21 +197,23 @@ config AXP_ALDO4_VOLT
 
 config AXP_DLDO1_VOLT
 	int "axp pmic dldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to
 	disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used
-	to power the ethernet phy. On sun8i (A23) boards this is often used to
-	power the wifi.
+	to power the ethernet phy. On A23, A33 and A80 boards this is often
+	used to power the wifi.
 
 config AXP_DLDO2_VOLT
 	int "axp pmic dldo2 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 3000 if MACH_SUN9I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to
 	disable dldo2.
+	On A80 boards dldo2 normally powers the PL pins and should be 3.0V.
 
 config AXP_DLDO3_VOLT
 	int "axp pmic dldo3 voltage"
@@ -214,7 +233,7 @@ config AXP_DLDO4_VOLT
 
 config AXP_ELDO1_VOLT
 	int "axp pmic eldo1 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to
@@ -222,7 +241,7 @@ config AXP_ELDO1_VOLT
 
 config AXP_ELDO2_VOLT
 	int "axp pmic eldo2 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to
@@ -230,13 +249,15 @@ config AXP_ELDO2_VOLT
 
 config AXP_ELDO3_VOLT
 	int "axp pmic eldo3 voltage"
-	depends on AXP221_POWER || AXP818_POWER
+	depends on AXP221_POWER || AXP809_POWER || AXP818_POWER
+	default 3000 if MACH_SUN9I
 	default 0
 	---help---
 	Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to
 	disable eldo3. On some A31(s) tablets it might be used to supply
 	1.2V for the SSD2828 chip (converter of parallel LCD interface
 	into MIPI DSI).
+	On A80 boards it powers the PM pingroup and should be 3.0V.
 
 config AXP_FLDO1_VOLT
 	int "axp pmic fldo1 voltage"
@@ -249,7 +270,7 @@ config AXP_FLDO1_VOLT
 	used.
 
 config AXP_FLDO2_VOLT
-	int "axp pmic eldo2 voltage"
+	int "axp pmic fldo2 voltage"
 	depends on AXP818_POWER
 	default 900 if MACH_SUN8I_A83T
 	---help---
@@ -265,6 +286,13 @@ config AXP_FLDO3_VOLT
 	Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to
 	disable fldo3.
 
+config AXP_SW_ON
+	bool "axp pmic sw on"
+	depends on AXP809_POWER || AXP818_POWER
+	default n
+	---help---
+	Enable to turn on axp pmic sw.
+
 config SY8106A_VOUT1_VOLT
 	int "SY8106A pmic VOUT1 voltage"
 	depends on SY8106A_POWER
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 690faa0f5e..b43523e628 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_AS3722_POWER)	+= as3722.o
 obj-$(CONFIG_AXP152_POWER)	+= axp152.o
 obj-$(CONFIG_AXP209_POWER)	+= axp209.o
 obj-$(CONFIG_AXP221_POWER)	+= axp221.o
+obj-$(CONFIG_AXP809_POWER)	+= axp809.o
 obj-$(CONFIG_AXP818_POWER)	+= axp818.o
 obj-$(CONFIG_EXYNOS_TMU)	+= exynos-tmu.o
 obj-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
index cb1f88b185..727ab09806 100644
--- a/drivers/power/axp221.c
+++ b/drivers/power/axp221.c
@@ -191,33 +191,20 @@ int axp_set_eldo(int eldo_num, unsigned int mvolt)
 {
 	int ret;
 	u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
-	u8 addr, bits;
-
-	switch (eldo_num) {
-	case 3:
-		addr = AXP221_ELDO3_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO3_EN;
-		break;
-	case 2:
-		addr = AXP221_ELDO2_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO2_EN;
-		break;
-	case 1:
-		addr = AXP221_ELDO1_CTRL;
-		bits = AXP221_OUTPUT_CTRL2_ELDO1_EN;
-		break;
-	default:
+
+	if (eldo_num < 1 || eldo_num > 3)
 		return -EINVAL;
-	}
 
 	if (mvolt == 0)
-		return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2, bits);
+		return pmic_bus_clrbits(AXP221_OUTPUT_CTRL2,
+				AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
 
-	ret = pmic_bus_write(addr, cfg);
+	ret = pmic_bus_write(AXP221_ELDO1_CTRL + (eldo_num - 1), cfg);
 	if (ret)
 		return ret;
 
-	return pmic_bus_setbits(AXP221_OUTPUT_CTRL2, bits);
+	return pmic_bus_setbits(AXP221_OUTPUT_CTRL2,
+				AXP221_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
 }
 
 int axp_init(void)
diff --git a/drivers/power/axp809.c b/drivers/power/axp809.c
new file mode 100644
index 0000000000..c8b76cf9b7
--- /dev/null
+++ b/drivers/power/axp809.c
@@ -0,0 +1,238 @@
+/*
+ * AXP809 driver based on AXP221 driver
+ *
+ *
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on axp221.c
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pmic_bus.h>
+#include <axp_pmic.h>
+
+static u8 axp809_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+	if (mvolt < min)
+		mvolt = min;
+	else if (mvolt > max)
+		mvolt = max;
+
+	return (mvolt - min) / div;
+}
+
+int axp_set_dcdc1(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC1_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC1_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	ret = pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+			       AXP809_OUTPUT_CTRL2_DC1SW_EN);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC1_EN);
+}
+
+int axp_set_dcdc2(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC2_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC2_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC2_EN);
+}
+
+int axp_set_dcdc3(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1860, 20);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC3_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC3_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC3_EN);
+}
+
+int axp_set_dcdc4(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+	if (mvolt >= 1540)
+		cfg = 0x30 + axp809_mvolt_to_cfg(mvolt, 1800, 2600, 100);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC4_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC4_EN);
+}
+
+int axp_set_dcdc5(unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 1000, 2550, 50);
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+					AXP809_OUTPUT_CTRL1_DCDC5_EN);
+
+	ret = pmic_bus_write(AXP809_DCDC5_CTRL, cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_DCDC5_EN);
+}
+
+int axp_set_aldo(int aldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg;
+
+	if (aldo_num < 1 || aldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0 && aldo_num == 3)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_ALDO3_EN);
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+
+	cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	ret = pmic_bus_write(AXP809_ALDO1_CTRL + (aldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	if (aldo_num == 3)
+		return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_ALDO3_EN);
+	return pmic_bus_clrbits(AXP809_OUTPUT_CTRL1,
+				AXP809_OUTPUT_CTRL1_ALDO1_EN << (aldo_num - 1));
+}
+
+/* TODO: re-work other AXP drivers to consolidate ALDO functions. */
+int axp_set_aldo1(unsigned int mvolt)
+{
+	return axp_set_aldo(1, mvolt);
+}
+
+int axp_set_aldo2(unsigned int mvolt)
+{
+	return axp_set_aldo(2, mvolt);
+}
+
+int axp_set_aldo3(unsigned int mvolt)
+{
+	return axp_set_aldo(3, mvolt);
+}
+
+int axp_set_dldo(int dldo_num, unsigned int mvolt)
+{
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+	int ret;
+
+	if (dldo_num < 1 || dldo_num > 2)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+
+	if (dldo_num == 1 && mvolt > 3300)
+		cfg += 1 + axp809_mvolt_to_cfg(mvolt, 3400, 4200, 200);
+	ret = pmic_bus_write(AXP809_DLDO1_CTRL + (dldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_DLDO1_EN << (dldo_num - 1));
+}
+
+int axp_set_eldo(int eldo_num, unsigned int mvolt)
+{
+	int ret;
+	u8 cfg = axp809_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+	if (eldo_num < 1 || eldo_num > 3)
+		return -EINVAL;
+
+	if (mvolt == 0)
+		return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+
+	ret = pmic_bus_write(AXP809_ELDO1_CTRL + (eldo_num - 1), cfg);
+	if (ret)
+		return ret;
+
+	return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_ELDO1_EN << (eldo_num - 1));
+}
+
+int axp_set_sw(bool on)
+{
+	if (on)
+		return pmic_bus_setbits(AXP809_OUTPUT_CTRL2,
+					AXP809_OUTPUT_CTRL2_SWOUT_EN);
+
+	return pmic_bus_clrbits(AXP809_OUTPUT_CTRL2,
+				AXP809_OUTPUT_CTRL2_SWOUT_EN);
+}
+
+int axp_init(void)
+{
+	int ret;
+
+	ret = pmic_bus_init();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmic_bus_write(AXP809_SHUTDOWN, AXP809_SHUTDOWN_POWEROFF);
+
+	/* infinite loop during shutdown */
+	while (1) {}
+
+	/* not reached */
+	return 0;
+}
diff --git a/drivers/power/axp818.c b/drivers/power/axp818.c
index 3ac05ffefe..af4d7a6903 100644
--- a/drivers/power/axp818.c
+++ b/drivers/power/axp818.c
@@ -225,6 +225,16 @@ int axp_set_fldo(int fldo_num, unsigned int mvolt)
 				AXP818_OUTPUT_CTRL3_FLDO1_EN << (fldo_num - 1));
 }
 
+int axp_set_sw(bool on)
+{
+	if (on)
+		return pmic_bus_setbits(AXP818_OUTPUT_CTRL2,
+					AXP818_OUTPUT_CTRL2_SW_EN);
+
+	return pmic_bus_clrbits(AXP818_OUTPUT_CTRL2,
+				AXP818_OUTPUT_CTRL2_SW_EN);
+}
+
 int axp_init(void)
 {
 	u8 axp_chip_id;
@@ -245,3 +255,14 @@ int axp_init(void)
 
 	return 0;
 }
+
+int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	pmic_bus_write(AXP818_SHUTDOWN, AXP818_SHUTDOWN_POWEROFF);
+
+	/* infinite loop during shutdown */
+	while (1) {}
+
+	/* not reached */
+	return 0;
+}
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 6f0d61e7ab..37ea2b88ea 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -9,6 +9,15 @@ config DM_PWM
 	  frequency/period can be controlled along with the proportion of that
 	  time that the signal is high.
 
+config PWM_EXYNOS
+	bool "Enable support for the Exynos PWM"
+	depends on DM_PWM
+	help
+	  This PWM is found on Samsung Exynos 5250 and other Samsung SoCs. It
+	  supports a programmable period and duty cycle. A 32-bit counter is
+	  used. It provides 5 channels which can be independently
+	  programmed. Channel 4 (the last) is normally used as a timer.
+
 config PWM_ROCKCHIP
 	bool "Enable support for the Rockchip PWM"
 	depends on DM_PWM
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index fd414b1893..af39347aac 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
 obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
 ifdef CONFIG_DM_PWM
 obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
+obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
 endif
diff --git a/drivers/pwm/exynos_pwm.c b/drivers/pwm/exynos_pwm.c
new file mode 100644
index 0000000000..a0edafce40
--- /dev/null
+++ b/drivers/pwm/exynos_pwm.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2016 Google Inc.
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pwm.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/pwm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct exynos_pwm_priv {
+	struct s5p_timer *regs;
+};
+
+static int exynos_pwm_set_config(struct udevice *dev, uint channel,
+				uint period_ns, uint duty_ns)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	unsigned int offset, prescaler;
+	uint div = 4, rate, rate_ns;
+	u32 val;
+	u32 tcnt, tcmp, tcon;
+
+	if (channel >= 5)
+		return -EINVAL;
+	debug("%s: Configure '%s' channel %u, period_ns %u, duty_ns %u\n",
+	      __func__, dev->name, channel, period_ns, duty_ns);
+
+	val = readl(&regs->tcfg0);
+	prescaler = (channel < 2 ? val : (val >> 8)) & 0xff;
+	div = (readl(&regs->tcfg1) >> MUX_DIV_SHIFT(channel)) & 0xf;
+
+	rate = get_pwm_clk() / ((prescaler + 1) * (1 << div));
+	debug("%s: pwm_clk %lu, rate %u\n", __func__, get_pwm_clk(), rate);
+
+	if (channel < 4) {
+		rate_ns = 1000000000 / rate;
+		tcnt = period_ns / rate_ns;
+		tcmp = duty_ns / rate_ns;
+		debug("%s: tcnt %u, tcmp %u\n", __func__, tcnt, tcmp);
+		offset = channel * 3;
+		writel(tcnt, &regs->tcntb0 + offset);
+		writel(tcmp, &regs->tcmpb0 + offset);
+	}
+
+	tcon = readl(&regs->tcon);
+	tcon |= TCON_UPDATE(channel);
+	if (channel < 4)
+		tcon |= TCON_AUTO_RELOAD(channel);
+	else
+		tcon |= TCON4_AUTO_RELOAD;
+	writel(tcon, &regs->tcon);
+
+	tcon &= ~TCON_UPDATE(channel);
+	writel(tcon, &regs->tcon);
+
+	return 0;
+}
+
+static int exynos_pwm_set_enable(struct udevice *dev, uint channel,
+				 bool enable)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+	u32 mask;
+
+	if (channel >= 4)
+		return -EINVAL;
+	debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
+	mask = TCON_START(channel);
+	clrsetbits_le32(&regs->tcon, mask, enable ? mask : 0);
+
+	return 0;
+}
+
+static int exynos_pwm_probe(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+	struct s5p_timer *regs = priv->regs;
+
+	writel(PRESCALER_0 | PRESCALER_1 << 8, &regs->tcfg0);
+
+	return 0;
+}
+
+static int exynos_pwm_ofdata_to_platdata(struct udevice *dev)
+{
+	struct exynos_pwm_priv *priv = dev_get_priv(dev);
+
+	priv->regs = (struct s5p_timer *)dev_get_addr(dev);
+
+	return 0;
+}
+
+static const struct pwm_ops exynos_pwm_ops = {
+	.set_config	= exynos_pwm_set_config,
+	.set_enable	= exynos_pwm_set_enable,
+};
+
+static const struct udevice_id exynos_channels[] = {
+	{ .compatible = "samsung,exynos4210-pwm" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_pwm) = {
+	.name	= "exynos_pwm",
+	.id	= UCLASS_PWM,
+	.of_match = exynos_channels,
+	.ops	= &exynos_pwm_ops,
+	.probe	= exynos_pwm_probe,
+	.ofdata_to_platdata	= exynos_pwm_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_pwm_priv),
+};
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2497ae90a0..0e3890391b 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -121,6 +121,14 @@ config DEBUG_UART_S5P
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 
+config DEBUG_UART_MESON
+	bool "Amlogic Meson"
+	depends on MESON_SERIAL
+	help
+	  Select this to enable a debug UART using the serial_meson driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver-model serial is running.
+
 config DEBUG_UART_UARTLITE
 	bool "Xilinx Uartlite"
 	help
@@ -338,6 +346,13 @@ config XILINX_UARTLITE
 	  If you have a Xilinx based board and want to use the uartlite
 	  serial ports, say Y to this option. If unsure, say N.
 
+config MESON_SERIAL
+	bool "Support for Amlogic Meson UART"
+	depends on DM_SERIAL && ARCH_MESON
+	help
+	  If you have an Amlogic Meson based board and want to use the on-chip
+	  serial ports, say Y to this option. If unsure, say N.
+
 config MSM_SERIAL
 	bool "Qualcomm on-chip UART"
 	depends on DM_SERIAL
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 9def128e89..e1e28ded30 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_SYS_NS16550) += ns16550.o
 obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
+obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
 obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
 obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 28da9ddfd8..c6cb3eb500 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -54,12 +54,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_NS16550_IER  0x00
 #endif /* CONFIG_SYS_NS16550_IER */
 
-#ifdef CONFIG_DM_SERIAL
-
-#ifndef CONFIG_SYS_NS16550_CLK
-#define CONFIG_SYS_NS16550_CLK  0
-#endif
-
 static inline void serial_out_shift(void *addr, int shift, int value)
 {
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
@@ -94,13 +88,20 @@ static inline int serial_in_shift(void *addr, int shift)
 #endif
 }
 
+#ifdef CONFIG_DM_SERIAL
+
+#ifndef CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_CLK  0
+#endif
+
 static void ns16550_writeb(NS16550_t port, int offset, int value)
 {
 	struct ns16550_platdata *plat = port->plat;
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+	addr = (unsigned char *)plat->base + offset;
+
 	/*
 	 * As far as we know it doesn't make sense to support selection of
 	 * these options at run-time, so use the existing CONFIG options.
@@ -114,7 +115,7 @@ static int ns16550_readb(NS16550_t port, int offset)
 	unsigned char *addr;
 
 	offset *= 1 << plat->reg_shift;
-	addr = map_physmem(plat->base, 0, MAP_NOCACHE) + offset;
+	addr = (unsigned char *)plat->base + offset;
 
 	return serial_in_shift(addr + plat->reg_offset, plat->reg_shift);
 }
@@ -128,27 +129,13 @@ static int ns16550_readb(NS16550_t port, int offset)
 		(unsigned char *)addr - (unsigned char *)com_port)
 #endif
 
-static inline int calc_divisor(NS16550_t port, int clock, int baudrate)
+int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
 {
 	const unsigned int mode_x_div = 16;
 
 	return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
 }
 
-int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
-{
-#ifdef CONFIG_OMAP1510
-	/* If can't cleanly clock 115200 set div to 1 */
-	if ((clock == 12000000) && (baudrate == 115200)) {
-		port->osc_12m_sel = OSC_12M_SEL;  /* enable 6.5 * divisor */
-		return 1;			/* return 1 for base divisor */
-	}
-	port->osc_12m_sel = 0;			/* clear if previsouly set */
-#endif
-
-	return calc_divisor(port, clock, baudrate);
-}
-
 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
 {
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
@@ -271,8 +258,8 @@ static inline void _debug_uart_init(void)
 	 * feasible. The better fix is to move all users of this driver to
 	 * driver model.
 	 */
-	baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
-				    CONFIG_BAUDRATE);
+	baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
+					    CONFIG_BAUDRATE);
 	serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
 	serial_dout(&com_port->mcr, UART_MCRVAL);
 	serial_dout(&com_port->fcr, UART_FCRVAL);
@@ -400,7 +387,12 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
+#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 	plat->base = addr;
+#else
+	plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
+#endif
+
 	plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
 				     "reg-offset", 0);
 	plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
new file mode 100644
index 0000000000..1b494265ce
--- /dev/null
+++ b/drivers/serial/serial_meson.c
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/compiler.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct meson_uart {
+	u32 wfifo;
+	u32 rfifo;
+	u32 control;
+	u32 status;
+	u32 misc;
+};
+
+struct meson_serial_platdata {
+	struct meson_uart *reg;
+};
+
+/* AML_UART_STATUS bits */
+#define AML_UART_PARITY_ERR		BIT(16)
+#define AML_UART_FRAME_ERR		BIT(17)
+#define AML_UART_TX_FIFO_WERR		BIT(18)
+#define AML_UART_RX_EMPTY		BIT(20)
+#define AML_UART_TX_FULL		BIT(21)
+#define AML_UART_TX_EMPTY		BIT(22)
+#define AML_UART_XMIT_BUSY		BIT(25)
+#define AML_UART_ERR			(AML_UART_PARITY_ERR | \
+					 AML_UART_FRAME_ERR  | \
+					 AML_UART_TX_FIFO_WERR)
+
+/* AML_UART_CONTROL bits */
+#define AML_UART_TX_EN			BIT(12)
+#define AML_UART_RX_EN			BIT(13)
+#define AML_UART_TX_RST			BIT(22)
+#define AML_UART_RX_RST			BIT(23)
+#define AML_UART_CLR_ERR		BIT(24)
+
+static void meson_serial_init(struct meson_uart *uart)
+{
+	u32 val;
+
+	val = readl(&uart->control);
+	val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, &uart->control);
+	val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR);
+	writel(val, &uart->control);
+	val |= (AML_UART_RX_EN | AML_UART_TX_EN);
+	writel(val, &uart->control);
+}
+
+static int meson_serial_probe(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	meson_serial_init(uart);
+
+	return 0;
+}
+
+static int meson_serial_getc(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	if (readl(&uart->status) & AML_UART_RX_EMPTY)
+		return -EAGAIN;
+
+	return readl(&uart->rfifo) & 0xff;
+}
+
+static int meson_serial_putc(struct udevice *dev, const char ch)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+
+	if (readl(&uart->status) & AML_UART_TX_FULL)
+		return -EAGAIN;
+
+	writel(ch, &uart->wfifo);
+
+	return 0;
+}
+
+static int meson_serial_pending(struct udevice *dev, bool input)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	struct meson_uart *const uart = plat->reg;
+	uint32_t status = readl(&uart->status);
+
+	if (input)
+		return !(status & AML_UART_RX_EMPTY);
+	else
+		return !(status & AML_UART_TX_FULL);
+}
+
+static int meson_serial_ofdata_to_platdata(struct udevice *dev)
+{
+	struct meson_serial_platdata *plat = dev->platdata;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	plat->reg = (struct meson_uart *)addr;
+
+	return 0;
+}
+
+static const struct dm_serial_ops meson_serial_ops = {
+	.putc = meson_serial_putc,
+	.pending = meson_serial_pending,
+	.getc = meson_serial_getc,
+};
+
+static const struct udevice_id meson_serial_ids[] = {
+	{ .compatible = "amlogic,meson-uart" },
+	{ }
+};
+
+U_BOOT_DRIVER(serial_meson) = {
+	.name		= "serial_meson",
+	.id		= UCLASS_SERIAL,
+	.of_match	= meson_serial_ids,
+	.probe		= meson_serial_probe,
+	.ops		= &meson_serial_ops,
+	.flags		= DM_FLAG_PRE_RELOC,
+	.ofdata_to_platdata = meson_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct meson_serial_platdata),
+};
+
+#ifdef CONFIG_DEBUG_UART_MESON
+
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct meson_uart *regs = (struct meson_uart *)CONFIG_DEBUG_UART_BASE;
+
+	while (readl(&regs->status) & AML_UART_TX_FULL)
+		;
+
+	writel(ch, &regs->wfifo);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index feba467d80..cb55c5ab71 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -17,6 +17,7 @@
 #include <asm/arch/clk.h>
 #include <asm/arch/uart.h>
 #include <serial.h>
+#include <clk.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -90,7 +91,19 @@ int s5p_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct s5p_serial_platdata *plat = dev->platdata;
 	struct s5p_uart *const uart = plat->reg;
-	u32 uclk = get_uart_clk(plat->port_id);
+	u32 uclk;
+
+#ifdef CONFIG_CLK_EXYNOS
+	struct udevice *clk_dev;
+	u32 ret;
+
+	ret = clk_get_by_index(dev, 1, &clk_dev);
+	if (ret < 0)
+		return ret;
+	uclk = clk_get_periph_rate(clk_dev, ret);
+#else
+	uclk = get_uart_clk(plat->port_id);
+#endif
 
 	s5p_serial_baud(uart, uclk, baudrate);
 
@@ -174,8 +187,8 @@ static int s5p_serial_ofdata_to_platdata(struct udevice *dev)
 		return -EINVAL;
 
 	plat->reg = (struct s5p_uart *)addr;
-	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "id", -1);
-
+	plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					"id", dev->seq);
 	return 0;
 }
 
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index cb8d929d07..75cbab2676 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -44,6 +44,8 @@ DECLARE_GLOBAL_DATA_PTR;
 #define SEQID_RDEAR		11
 #define SEQID_WREAR		12
 #endif
+#define SEQID_WRAR		13
+#define SEQID_RDAR		14
 
 /* QSPI CMD */
 #define QSPI_CMD_PP		0x02	/* Page program (up to 256 bytes) */
@@ -63,6 +65,10 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	QSPI_CMD_BRRD		0x16	/* Bank register read */
 #define	QSPI_CMD_BRWR		0x17	/* Bank register write */
 
+/* Used for Spansion S25FS-S family flash only. */
+#define QSPI_CMD_RDAR		0x65	/* Read any device register */
+#define QSPI_CMD_WRAR		0x71	/* Write any device register */
+
 /* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
 #define QSPI_CMD_FAST_READ_4B	0x0c    /* Read data bytes (high frequency) */
 #define QSPI_CMD_PP_4B		0x12    /* Page program (up to 256 bytes) */
@@ -92,9 +98,9 @@ DECLARE_GLOBAL_DATA_PTR;
 struct fsl_qspi_platdata {
 	u32 flags;
 	u32 speed_hz;
-	u32 reg_base;
-	u32 amba_base;
-	u32 amba_total_size;
+	fdt_addr_t reg_base;
+	fdt_addr_t amba_base;
+	fdt_size_t amba_total_size;
 	u32 flash_num;
 	u32 num_chipselect;
 };
@@ -317,6 +323,33 @@ static void qspi_set_lut(struct fsl_qspi_priv *priv)
 		     PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
 		     PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
 #endif
+
+	/*
+	 * Read any device register.
+	 * Used for Spansion S25FS-S family flash only.
+	 */
+	lut_base = SEQID_RDAR * 4;
+	qspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(QSPI_CMD_RDAR) | PAD0(LUT_PAD1) |
+		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
+		     OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
+		     OPRND1(1) | PAD1(LUT_PAD1) |
+		     INSTR1(LUT_READ));
+
+	/*
+	 * Write any device register.
+	 * Used for Spansion S25FS-S family flash only.
+	 */
+	lut_base = SEQID_WRAR * 4;
+	qspi_write32(priv->flags, &regs->lut[lut_base],
+		     OPRND0(QSPI_CMD_WRAR) | PAD0(LUT_PAD1) |
+		     INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+		     PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+	qspi_write32(priv->flags, &regs->lut[lut_base + 1],
+		     OPRND0(1) | PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+
 	/* Lock the LUT */
 	qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
 	qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
@@ -510,7 +543,6 @@ static void qspi_op_rdid(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
 
-#ifndef CONFIG_SYS_FSL_QSPI_AHB
 /* If not use AHB read, read data from ip interface */
 static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 {
@@ -518,6 +550,12 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 	u32 mcr_reg, data;
 	int i, size;
 	u32 to_or_from;
+	u32 seqid;
+
+	if (priv->cur_seqid == QSPI_CMD_RDAR)
+		seqid = SEQID_RDAR;
+	else
+		seqid = SEQID_FAST_READ;
 
 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);
 	qspi_write32(priv->flags, &regs->mcr,
@@ -536,7 +574,7 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 			RX_BUFFER_SIZE : len;
 
 		qspi_write32(priv->flags, &regs->ipcr,
-			     (SEQID_FAST_READ << QSPI_IPCR_SEQID_SHIFT) |
+			     (seqid << QSPI_IPCR_SEQID_SHIFT) |
 			     size);
 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
 			;
@@ -548,7 +586,10 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 		while ((RX_BUFFER_SIZE >= size) && (size > 0)) {
 			data = qspi_read32(priv->flags, &regs->rbdr[i]);
 			data = qspi_endian_xchg(data);
-			memcpy(rxbuf, &data, 4);
+			if (size < 4)
+				memcpy(rxbuf, &data, size);
+			else
+				memcpy(rxbuf, &data, 4);
 			rxbuf++;
 			size -= 4;
 			i++;
@@ -560,7 +601,6 @@ static void qspi_op_read(struct fsl_qspi_priv *priv, u32 *rxbuf, u32 len)
 
 	qspi_write32(priv->flags, &regs->mcr, mcr_reg);
 }
-#endif
 
 static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 {
@@ -601,6 +641,8 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len)
 
 	/* Default is page programming */
 	seqid = SEQID_PP;
+	if (priv->cur_seqid == QSPI_CMD_WRAR)
+		seqid = SEQID_WRAR;
 #ifdef CONFIG_SPI_FLASH_BAR
 	if (priv->cur_seqid == QSPI_CMD_BRWR)
 		seqid = SEQID_BRWR;
@@ -725,13 +767,15 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 			return 0;
 		}
 
-		if (priv->cur_seqid == QSPI_CMD_FAST_READ) {
+		if (priv->cur_seqid == QSPI_CMD_FAST_READ ||
+		    priv->cur_seqid == QSPI_CMD_RDAR) {
 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 		} else if ((priv->cur_seqid == QSPI_CMD_SE) ||
 			   (priv->cur_seqid == QSPI_CMD_BE_4K)) {
 			priv->sf_addr = swab32(txbuf) & OFFSET_BITS_MASK;
 			qspi_op_erase(priv);
-		} else if (priv->cur_seqid == QSPI_CMD_PP) {
+		} else if (priv->cur_seqid == QSPI_CMD_PP ||
+			   priv->cur_seqid == QSPI_CMD_WRAR) {
 			wr_sfaddr = swab32(txbuf) & OFFSET_BITS_MASK;
 		} else if ((priv->cur_seqid == QSPI_CMD_BRWR) ||
 			 (priv->cur_seqid == QSPI_CMD_WREAR)) {
@@ -748,6 +792,8 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
 #else
 			qspi_op_read(priv, din, bytes);
 #endif
+		} else if (priv->cur_seqid == QSPI_CMD_RDAR) {
+			qspi_op_read(priv, din, bytes);
 		} else if (priv->cur_seqid == QSPI_CMD_RDID)
 			qspi_op_rdid(priv, din, bytes);
 		else if (priv->cur_seqid == QSPI_CMD_RDSR)
@@ -927,10 +973,11 @@ static int fsl_qspi_child_pre_probe(struct udevice *dev)
 
 static int fsl_qspi_probe(struct udevice *bus)
 {
-	u32 total_size;
+	u32 amba_size_per_chip;
 	struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
 	struct fsl_qspi_priv *priv = dev_get_priv(bus);
 	struct dm_spi_bus *dm_spi_bus;
+	int i;
 
 	dm_spi_bus = bus->uclass_priv;
 
@@ -940,8 +987,13 @@ static int fsl_qspi_probe(struct udevice *bus)
 	priv->flags = plat->flags;
 
 	priv->speed_hz = plat->speed_hz;
-	priv->amba_base[0] = plat->amba_base;
-	priv->amba_total_size = plat->amba_total_size;
+	/*
+	 * QSPI SFADR width is 32bits, the max dest addr is 4GB-1.
+	 * AMBA memory zone should be located on the 0~4GB space
+	 * even on a 64bits cpu.
+	 */
+	priv->amba_base[0] = (u32)plat->amba_base;
+	priv->amba_total_size = (u32)plat->amba_total_size;
 	priv->flash_num = plat->flash_num;
 	priv->num_chipselect = plat->num_chipselect;
 
@@ -951,7 +1003,22 @@ static int fsl_qspi_probe(struct udevice *bus)
 	qspi_cfg_smpr(priv, ~(QSPI_SMPR_FSDLY_MASK | QSPI_SMPR_DDRSMP_MASK |
 		QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0);
 
-	total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
+	/*
+	 * Assign AMBA memory zone for every chipselect
+	 * QuadSPI has two channels, every channel has two chipselects.
+	 * If the property 'num-cs' in dts is 2, the AMBA memory will be divided
+	 * into two parts and assign to every channel. This indicate that every
+	 * channel only has one valid chipselect.
+	 * If the property 'num-cs' in dts is 4, the AMBA memory will be divided
+	 * into four parts and assign to every chipselect.
+	 * Every channel will has two valid chipselects.
+	 */
+	amba_size_per_chip = priv->amba_total_size >>
+			     (priv->num_chipselect >> 1);
+	for (i = 1 ; i < priv->num_chipselect ; i++)
+		priv->amba_base[i] =
+			amba_size_per_chip + priv->amba_base[i - 1];
+
 	/*
 	 * Any read access to non-implemented addresses will provide
 	 * undefined results.
@@ -962,14 +1029,30 @@ static int fsl_qspi_probe(struct udevice *bus)
 	 * setting the size of these devices to 0.  This would ensure
 	 * that the complete memory map is assigned to only one flash device.
 	 */
-	qspi_write32(priv->flags, &priv->regs->sfa1ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfa2ad,
-		     FSL_QSPI_FLASH_SIZE | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb1ad,
-		     total_size | priv->amba_base[0]);
-	qspi_write32(priv->flags, &priv->regs->sfb2ad,
-		     total_size | priv->amba_base[0]);
+	qspi_write32(priv->flags, &priv->regs->sfa1ad, priv->amba_base[1]);
+	switch (priv->num_chipselect) {
+	case 2:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[1]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[1] + amba_size_per_chip);
+		break;
+	case 4:
+		qspi_write32(priv->flags, &priv->regs->sfa2ad,
+			     priv->amba_base[2]);
+		qspi_write32(priv->flags, &priv->regs->sfb1ad,
+			     priv->amba_base[3]);
+		qspi_write32(priv->flags, &priv->regs->sfb2ad,
+			     priv->amba_base[3] + amba_size_per_chip);
+		break;
+	default:
+		debug("Error: Unsupported chipselect number %u!\n",
+		      priv->num_chipselect);
+		qspi_module_disable(priv, 1);
+		return -EINVAL;
+	}
 
 	qspi_set_lut(priv);
 
@@ -984,10 +1067,7 @@ static int fsl_qspi_probe(struct udevice *bus)
 
 static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 {
-	struct reg_data {
-		u32 addr;
-		u32 size;
-	} regs_data[2];
+	struct fdt_resource res_regs, res_mem;
 	struct fsl_qspi_platdata *plat = bus->platdata;
 	const void *blob = gd->fdt_blob;
 	int node = bus->of_offset;
@@ -996,10 +1076,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	if (fdtdec_get_bool(blob, node, "big-endian"))
 		plat->flags |= QSPI_FLAG_REGMAP_ENDIAN_BIG;
 
-	ret = fdtdec_get_int_array(blob, node, "reg", (u32 *)regs_data,
-				   sizeof(regs_data)/sizeof(u32));
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI", &res_regs);
+	if (ret) {
+		debug("Error: can't get regs base addresses(ret = %d)!\n", ret);
+		return -ENOMEM;
+	}
+	ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
+				     "QuadSPI-memory", &res_mem);
 	if (ret) {
-		debug("Error: can't get base addresses (ret = %d)!\n", ret);
+		debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret);
 		return -ENOMEM;
 	}
 
@@ -1017,16 +1103,16 @@ static int fsl_qspi_ofdata_to_platdata(struct udevice *bus)
 	plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs",
 					      FSL_QSPI_MAX_CHIPSELECT_NUM);
 
-	plat->reg_base = regs_data[0].addr;
-	plat->amba_base = regs_data[1].addr;
-	plat->amba_total_size = regs_data[1].size;
+	plat->reg_base = res_regs.start;
+	plat->amba_base = res_mem.start;
+	plat->amba_total_size = res_mem.end - res_mem.start + 1;
 	plat->flash_num = flash_num;
 
-	debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianess=%s\n",
+	debug("%s: regs=<0x%llx> <0x%llx, 0x%llx>, max-frequency=%d, endianess=%s\n",
 	      __func__,
-	      plat->reg_base,
-	      plat->amba_base,
-	      plat->amba_total_size,
+	      (u64)plat->reg_base,
+	      (u64)plat->amba_base,
+	      (u64)plat->amba_total_size,
 	      plat->speed_hz,
 	      plat->flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le"
 	      );
@@ -1055,8 +1141,7 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
 	bus = dev->parent;
 	priv = dev_get_priv(bus);
 
-	priv->cur_amba_base =
-		priv->amba_base[0] + FSL_QSPI_FLASH_SIZE * slave_plat->cs;
+	priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
 	qspi_module_disable(priv, 0);
 
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 0cd73020a7..2964bae0d8 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_USB_DWC3)			+= dwc3.o
 
 dwc3-y					:= core.o
 
-dwc3-y					+= gadget.o ep0.o
+obj-$(CONFIG_USB_DWC3_GADGET)		+= gadget.o ep0.o
 
 obj-$(CONFIG_USB_DWC3_OMAP)		+= dwc3-omap.o
 obj-$(CONFIG_USB_DWC3_PHY_OMAP)		+= ti_usb_phy.o
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d2363c8067..89580cc31f 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -9,12 +9,6 @@ config USB_XHCI_HCD
 	  The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
 	  "SuperSpeed" host controller hardware.
 
-config USB_XHCI
-	bool
-	default USB_XHCI_HCD
-	---help---
-	  TODO: rename after most boards switch to Kconfig
-
 if USB_XHCI_HCD
 
 config USB_XHCI_UNIPHIER
@@ -24,6 +18,12 @@ config USB_XHCI_UNIPHIER
 	---help---
 	  Enables support for the on-chip xHCI controller on UniPhier SoCs.
 
+config USB_XHCI_DWC3
+	bool "DesignWare USB3 DRD Core Support"
+	help
+	  Say Y or if your system has a Dual Role SuperSpeed
+	  USB controller based on the DesignWare USB3 IP Core.
+
 endif
 
 config USB_OHCI_GENERIC
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 507519ea72..620d114795 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -54,7 +54,7 @@ obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
 obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
 
 # xhci
-obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
+obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
 obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
 obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
 obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c
index f9069c7f9c..1993da16ea 100644
--- a/drivers/usb/phy/omap_usb_phy.c
+++ b/drivers/usb/phy/omap_usb_phy.c
@@ -23,7 +23,7 @@
 #include "../host/xhci.h"
 
 #ifdef CONFIG_OMAP_USB3PHY1_HOST
-struct usb_dpll_params {
+struct usb3_dpll_params {
 	u16	m;
 	u8	n;
 	u8	freq:3;
@@ -31,17 +31,39 @@ struct usb_dpll_params {
 	u32	mf;
 };
 
-#define	NUM_USB_CLKS		6
+struct usb3_dpll_map {
+	unsigned long rate;
+	struct usb3_dpll_params params;
+	struct usb3_dpll_map *dpll_map;
+};
 
-static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
-	{1250, 5, 4, 20, 0},		/* 12 MHz */
-	{3125, 20, 4, 20, 0},		/* 16.8 MHz */
-	{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
-	{1250, 12, 4, 20, 0},		/* 26 MHz */
-	{3125, 47, 4, 20, 92843},	/* 38.4 MHz */
-	{1000, 7, 4, 10, 0},        /* 20 MHz */
+static struct usb3_dpll_map dpll_map_usb[] = {
+	{12000000, {1250, 5, 4, 20, 0} },	/* 12 MHz */
+	{16800000, {3125, 20, 4, 20, 0} },	/* 16.8 MHz */
+	{19200000, {1172, 8, 4, 20, 65537} },	/* 19.2 MHz */
+	{20000000, {1000, 7, 4, 10, 0} },	/* 20 MHz */
+	{26000000, {1250, 12, 4, 20, 0} },	/* 26 MHz */
+	{38400000, {3125, 47, 4, 20, 92843} },	/* 38.4 MHz */
+	{ },					/* Terminator */
 };
 
+static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
+{
+	unsigned long rate;
+	struct usb3_dpll_map *dpll_map = dpll_map_usb;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
+
+	return NULL;
+}
+
 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
 {
 	u32 val;
@@ -56,32 +78,36 @@ static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
 
 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
 {
-	u32 clk_index = get_sys_clk_index();
+	struct usb3_dpll_params	*dpll_params;
 	u32 val;
 
+	dpll_params = omap_usb3_get_dpll_params();
+	if (!dpll_params)
+		return;
+
 	val = readl(&phy_regs->pll_config_1);
 	val &= ~PLL_REGN_MASK;
-	val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
 	writel(val, &phy_regs->pll_config_1);
 
 	val = readl(&phy_regs->pll_config_2);
 	val &= ~PLL_SELFREQDCO_MASK;
-	val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 	writel(val, &phy_regs->pll_config_2);
 
 	val = readl(&phy_regs->pll_config_1);
 	val &= ~PLL_REGM_MASK;
-	val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
 	writel(val, &phy_regs->pll_config_1);
 
 	val = readl(&phy_regs->pll_config_4);
 	val &= ~PLL_REGM_F_MASK;
-	val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 	writel(val, &phy_regs->pll_config_4);
 
 	val = readl(&phy_regs->pll_config_3);
 	val &= ~PLL_SD_MASK;
-	val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
 	writel(val, &phy_regs->pll_config_3);
 
 	omap_usb_dpll_relock(phy_regs);
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2fd0891e5d..3f045fe578 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -25,11 +25,6 @@ obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
 obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
-obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
-obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
-obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
-				exynos_mipi_dsi_lowlevel.o
-obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
 obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
 obj-$(CONFIG_L5F31188) += l5f31188.o
@@ -68,6 +63,7 @@ obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
+obj-${CONFIG_EXYNOS_FB} += exynos/
 obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
 
 obj-y += bridge/
diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile
new file mode 100644
index 0000000000..001a80fa04
--- /dev/null
+++ b/drivers/video/exynos/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o
+obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o
+obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \
+				exynos_mipi_dsi_lowlevel.o
+obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o
diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos/exynos_dp.c
index 0d5d090d0e..fc39f2c562 100644
--- a/drivers/video/exynos_dp.c
+++ b/drivers/video/exynos/exynos_dp.c
@@ -7,27 +7,26 @@
  */
 
 #include <config.h>
+#include <dm.h>
 #include <common.h>
+#include <display.h>
+#include <fdtdec.h>
+#include <libfdt.h>
 #include <malloc.h>
+#include <video_bridge.h>
 #include <linux/compat.h>
 #include <linux/err.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/dp_info.h>
 #include <asm/arch/dp.h>
-#include <fdtdec.h>
-#include <libfdt.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/power.h>
 
 #include "exynos_dp_lowlevel.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void __exynos_set_dp_phy(unsigned int onoff)
-{
-}
-void exynos_set_dp_phy(unsigned int onoff)
-	__attribute__((weak, alias("__exynos_set_dp_phy")));
-
 static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 {
 	disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
@@ -38,20 +37,20 @@ static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
 	return;
 }
 
-static int exynos_dp_init_dp(void)
+static int exynos_dp_init_dp(struct exynos_dp *regs)
 {
 	int ret;
-	exynos_dp_reset();
+	exynos_dp_reset(regs);
 
 	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_func(DP_ENABLE);
+	exynos_dp_enable_sw_func(regs, DP_ENABLE);
 
-	ret = exynos_dp_init_analog_func();
+	ret = exynos_dp_init_analog_func(regs);
 	if (ret != EXYNOS_DP_SUCCESS)
 		return ret;
 
-	exynos_dp_init_hpd();
-	exynos_dp_init_aux();
+	exynos_dp_init_hpd(regs);
+	exynos_dp_init_aux(regs);
 
 	return ret;
 }
@@ -67,7 +66,7 @@ static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
 	return sum;
 }
 
-static unsigned int exynos_dp_read_edid(void)
+static unsigned int exynos_dp_read_edid(struct exynos_dp *regs)
 {
 	unsigned char edid[EDID_BLOCK_LENGTH * 2];
 	unsigned int extend_block = 0;
@@ -82,14 +81,15 @@ static unsigned int exynos_dp_read_edid(void)
 	 */
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	exynos_dp_read_byte_from_i2c(I2C_EDID_DEVICE_ADDR, EDID_EXTENSION_FLAG,
-			&extend_block);
+	exynos_dp_read_byte_from_i2c(regs, I2C_EDID_DEVICE_ADDR,
+				     EDID_EXTENSION_FLAG, &extend_block);
 
 	if (extend_block > 0) {
 		printf("DP EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -104,7 +104,8 @@ static unsigned int exynos_dp_read_edid(void)
 		}
 
 		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_BLOCK_LENGTH,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_BLOCK_LENGTH]);
@@ -118,19 +119,22 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
-					&test_vector);
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
+					      &test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
+			exynos_dp_write_byte_to_dpcd(regs,
+				DPCD_TEST_EDID_CHECKSUM,
 				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	} else {
 		debug("DP EDID data does not include any extensions.\n");
 
 		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(I2C_EDID_DEVICE_ADDR,
+		retval = exynos_dp_read_bytes_from_i2c(regs,
+				I2C_EDID_DEVICE_ADDR,
 				EDID_HEADER_PATTERN,
 				EDID_BLOCK_LENGTH,
 				&edid[EDID_HEADER_PATTERN]);
@@ -145,12 +149,13 @@ static unsigned int exynos_dp_read_edid(void)
 			return -1;
 		}
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TEST_REQUEST,
+		exynos_dp_read_byte_from_dpcd(regs, DPCD_TEST_REQUEST,
 			&test_vector);
 		if (test_vector & DPCD_TEST_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(DPCD_TEST_RESPONSE,
+			exynos_dp_write_byte_to_dpcd(regs,
+				DPCD_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
+			exynos_dp_write_byte_to_dpcd(regs,
+				DPCD_TEST_RESPONSE,
 				DPCD_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
@@ -160,7 +165,8 @@ static unsigned int exynos_dp_read_edid(void)
 	return 0;
 }
 
-static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_handle_edid(struct exynos_dp *regs,
+					  struct exynos_dp_priv *priv)
 {
 	unsigned char buf[12];
 	unsigned int ret;
@@ -178,8 +184,8 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	retry_cnt = 5;
 	while (retry_cnt) {
 		/* Read DPCD 0x0000-0x000b */
-		ret = exynos_dp_read_bytes_from_dpcd(DPCD_DPCD_REV, 12,
-				buf);
+		ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_DPCD_REV, 12,
+						     buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			if (retry_cnt == 0) {
 				printf("DP read_byte_from_dpcd() failed\n");
@@ -193,7 +199,7 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	/* */
 	temp = buf[DPCD_DPCD_REV];
 	if (temp == DP_DPCD_REV_10 || temp == DP_DPCD_REV_11)
-		edp_info->dpcd_rev = temp;
+		priv->dpcd_rev = temp;
 	else {
 		printf("DP Wrong DPCD Rev : %x\n", temp);
 		return -ENODEV;
@@ -201,33 +207,33 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 
 	temp = buf[DPCD_MAX_LINK_RATE];
 	if (temp == DP_LANE_BW_1_62 || temp == DP_LANE_BW_2_70)
-		edp_info->lane_bw = temp;
+		priv->lane_bw = temp;
 	else {
 		printf("DP Wrong MAX LINK RATE : %x\n", temp);
 		return -EINVAL;
 	}
 
 	/* Refer VESA Display Port Standard Ver1.1a Page 120 */
-	if (edp_info->dpcd_rev == DP_DPCD_REV_11) {
+	if (priv->dpcd_rev == DP_DPCD_REV_11) {
 		temp = buf[DPCD_MAX_LANE_COUNT] & 0x1f;
 		if (buf[DPCD_MAX_LANE_COUNT] & 0x80)
-			edp_info->dpcd_efc = 1;
+			priv->dpcd_efc = 1;
 		else
-			edp_info->dpcd_efc = 0;
+			priv->dpcd_efc = 0;
 	} else {
 		temp = buf[DPCD_MAX_LANE_COUNT];
-		edp_info->dpcd_efc = 0;
+		priv->dpcd_efc = 0;
 	}
 
 	if (temp == DP_LANE_CNT_1 || temp == DP_LANE_CNT_2 ||
 			temp == DP_LANE_CNT_4) {
-		edp_info->lane_cnt = temp;
+		priv->lane_cnt = temp;
 	} else {
 		printf("DP Wrong MAX LANE COUNT : %x\n", temp);
 		return -EINVAL;
 	}
 
-	ret = exynos_dp_read_edid();
+	ret = exynos_dp_read_edid(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_read_edid() failed\n");
 		return -EINVAL;
@@ -236,60 +242,60 @@ static unsigned int exynos_dp_handle_edid(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static void exynos_dp_init_training(void)
+static void exynos_dp_init_training(struct exynos_dp *regs)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
 	 * the DP inter pair skew issue for at least 10 us
 	 */
-	exynos_dp_reset_macro();
+	exynos_dp_reset_macro(regs);
 
 	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(POWER_ALL, 0);
+	exynos_dp_set_analog_power_down(regs, POWER_ALL, 0);
 }
 
-static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_link_start(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv)
 {
 	unsigned char buf[5];
 	unsigned int ret = 0;
 
 	debug("DP: %s was called\n", __func__);
 
-	edp_info->lt_info.lt_status = DP_LT_CR;
-	edp_info->lt_info.ep_loop = 0;
-	edp_info->lt_info.cr_loop[0] = 0;
-	edp_info->lt_info.cr_loop[1] = 0;
-	edp_info->lt_info.cr_loop[2] = 0;
-	edp_info->lt_info.cr_loop[3] = 0;
+	priv->lt_info.lt_status = DP_LT_CR;
+	priv->lt_info.ep_loop = 0;
+	priv->lt_info.cr_loop[0] = 0;
+	priv->lt_info.cr_loop[1] = 0;
+	priv->lt_info.cr_loop[2] = 0;
+	priv->lt_info.cr_loop[3] = 0;
 
 		/* Set sink to D0 (Sink Not Ready) mode. */
-		ret = exynos_dp_write_byte_to_dpcd(DPCD_SINK_POWER_STATE,
-				DPCD_SET_POWER_STATE_D0);
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_SINK_POWER_STATE,
+					   DPCD_SET_POWER_STATE_D0);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
 	/* Set link rate and count as you want to establish */
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
+	exynos_dp_set_lane_count(regs, priv->lane_cnt);
 
 	/* Setup RX configuration */
-	buf[0] = edp_info->lane_bw;
-	buf[1] = edp_info->lane_cnt;
+	buf[0] = priv->lane_bw;
+	buf[1] = priv->lane_cnt;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_LINK_BW_SET, 2,
-			buf);
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_LINK_BW_SET, 2, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
 	}
 
-	exynos_dp_set_lane_pre_emphasis(PRE_EMPHASIS_LEVEL_0,
-			edp_info->lane_cnt);
+	exynos_dp_set_lane_pre_emphasis(regs, PRE_EMPHASIS_LEVEL_0,
+			priv->lane_cnt);
 
 	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(TRAINING_PTN1);
+	exynos_dp_set_training_pattern(regs, TRAINING_PTN1);
 
 	/* Set RX training pattern */
 	buf[0] = DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1;
@@ -303,8 +309,8 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	buf[4] = DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 |
 		DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0;
 
-	ret = exynos_dp_write_bytes_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			5, buf);
+	ret = exynos_dp_write_bytes_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
+					    5, buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP write_dpcd_byte failed\n");
 		return ret;
@@ -313,14 +319,14 @@ static unsigned int exynos_dp_link_start(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_training_pattern_dis(void)
+static unsigned int exynos_dp_training_pattern_dis(struct exynos_dp *regs)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	exynos_dp_set_training_pattern(DP_NONE);
+	exynos_dp_set_training_pattern(regs, DP_NONE);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
-			DPCD_TRAINING_PATTERN_DISABLED);
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
+					   DPCD_TRAINING_PATTERN_DISABLED);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP request_link_training_req failed\n");
 		return -EAGAIN;
@@ -329,13 +335,14 @@ static unsigned int exynos_dp_training_pattern_dis(void)
 	return ret;
 }
 
-static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
+static unsigned int exynos_dp_enable_rx_to_enhanced_mode(
+		struct exynos_dp *regs, unsigned char enable)
 {
 	unsigned char data;
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_read_byte_from_dpcd(DPCD_LANE_COUNT_SET,
-			&data);
+	ret = exynos_dp_read_byte_from_dpcd(regs, DPCD_LANE_COUNT_SET,
+					    &data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read_from_dpcd failed\n");
 		return -EAGAIN;
@@ -346,8 +353,7 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	else
 		data = DPCD_LN_COUNT_SET(data);
 
-	ret = exynos_dp_write_byte_to_dpcd(DPCD_LANE_COUNT_SET,
-			data);
+	ret = exynos_dp_write_byte_to_dpcd(regs, DPCD_LANE_COUNT_SET, data);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write_to_dpcd failed\n");
 			return -EAGAIN;
@@ -357,23 +363,25 @@ static unsigned int exynos_dp_enable_rx_to_enhanced_mode(unsigned char enable)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_enhanced_mode(unsigned char enhance_mode)
+static unsigned int exynos_dp_set_enhanced_mode(struct exynos_dp *regs,
+						unsigned char enhance_mode)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 
-	ret = exynos_dp_enable_rx_to_enhanced_mode(enhance_mode);
+	ret = exynos_dp_enable_rx_to_enhanced_mode(regs, enhance_mode);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP rx_enhance_mode failed\n");
 		return -EAGAIN;
 	}
 
-	exynos_dp_enable_enhanced_mode(enhance_mode);
+	exynos_dp_enable_enhanced_mode(regs, enhance_mode);
 
 	return ret;
 }
 
-static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
-		unsigned char *status)
+static int exynos_dp_read_dpcd_lane_stat(struct exynos_dp *regs,
+					 struct exynos_dp_priv *priv,
+					 unsigned char *status)
 {
 	unsigned int ret, i;
 	unsigned char buf[2];
@@ -385,13 +393,14 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	shift_val[2] = 0;
 	shift_val[3] = 4;
 
-	ret = exynos_dp_read_bytes_from_dpcd(DPCD_LANE0_1_STATUS, 2, buf);
+	ret = exynos_dp_read_bytes_from_dpcd(regs, DPCD_LANE0_1_STATUS, 2,
+					     buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
 		return ret;
 	}
 
-	for (i = 0; i < edp_info->lane_cnt; i++) {
+	for (i = 0; i < priv->lane_cnt; i++) {
 		lane_stat[i] = (buf[(i / 2)] >> shift_val[i]) & 0x0f;
 		if (lane_stat[0] != lane_stat[i]) {
 			printf("Wrong lane status\n");
@@ -404,8 +413,8 @@ static int exynos_dp_read_dpcd_lane_stat(struct edp_device_info *edp_info,
 	return ret;
 }
 
-static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
-		unsigned char *sw, unsigned char *em)
+static unsigned int exynos_dp_read_dpcd_adj_req(struct exynos_dp *regs,
+		unsigned char lane_num, unsigned char *sw, unsigned char *em)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char buf;
@@ -415,7 +424,7 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	/* lane_num value is used as array index, so this range 0 ~ 3 */
 	dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2);
 
-	ret = exynos_dp_read_byte_from_dpcd(dpcd_addr, &buf);
+	ret = exynos_dp_read_byte_from_dpcd(regs, dpcd_addr, &buf);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read adjust request failed\n");
 		return -EAGAIN;
@@ -427,51 +436,53 @@ static unsigned int exynos_dp_read_dpcd_adj_req(unsigned char lane_num,
 	return ret;
 }
 
-static int exynos_dp_equalizer_err_link(struct edp_device_info *edp_info)
+static int exynos_dp_equalizer_err_link(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	ret = exynos_dp_training_pattern_dis();
+	ret = exynos_dp_training_pattern_dis(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP training_pattern_disable() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
-	ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+	ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP set_enhanced_mode() failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static int exynos_dp_reduce_link_rate(struct edp_device_info *edp_info)
+static int exynos_dp_reduce_link_rate(struct exynos_dp *regs,
+				      struct exynos_dp_priv *priv)
 {
 	int ret;
 
-	if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		edp_info->lane_bw = DP_LANE_BW_1_62;
+	if (priv->lane_bw == DP_LANE_BW_2_70) {
+		priv->lane_bw = DP_LANE_BW_1_62;
 		printf("DP Change lane bw to 1.62Gbps\n");
-		edp_info->lt_info.lt_status = DP_LT_START;
+		priv->lt_info.lt_status = DP_LT_START;
 		ret = EXYNOS_DP_SUCCESS;
 	} else {
-		ret = exynos_dp_training_pattern_dis();
+		ret = exynos_dp_training_pattern_dis(regs);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP training_patter_disable() failed\n");
 
-		ret = exynos_dp_set_enhanced_mode(edp_info->dpcd_efc);
+		ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc);
 		if (ret != EXYNOS_DP_SUCCESS)
 			printf("DP set_enhanced_mode() failed\n");
 
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
-							*edp_info)
+static unsigned int exynos_dp_process_clock_recovery(struct exynos_dp *regs,
+					struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat;
@@ -484,22 +495,22 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	debug("DP: %s was called\n", __func__);
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP read lane status failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 	}
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
 		debug("DP clock Recovery training succeed\n");
-		exynos_dp_set_training_pattern(TRAINING_PTN2);
+		exynos_dp_set_training_pattern(regs, TRAINING_PTN2);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i, &adj_req_sw,
-					&adj_req_em);
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
+						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 
@@ -511,7 +522,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(regs,
+							 lt_ctl_val[i], i);
 		}
 
 		buf[0] =  DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2;
@@ -520,37 +532,39 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 		buf[3] = lt_ctl_val[2];
 		buf[4] = lt_ctl_val[3];
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_PATTERN_SET, 5, buf);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern1 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		} else
-			edp_info->lt_info.lt_status = DP_LT_ET;
+			priv->lt_info.lt_status = DP_LT_ET;
 	} else {
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(i);
-				ret = exynos_dp_read_dpcd_adj_req(i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			lt_ctl_val[i] = exynos_dp_get_lanex_pre_emphasis(
+						regs, i);
+				ret = exynos_dp_read_dpcd_adj_req(regs, i,
 						&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 				return ret;
 			}
 
 			if ((adj_req_sw == VOLTAGE_LEVEL_3) ||
 					(adj_req_em == PRE_EMPHASIS_LEVEL_3))
-				ret = exynos_dp_reduce_link_rate(edp_info);
+				ret = exynos_dp_reduce_link_rate(regs,
+								 priv);
 
 			if ((DRIVE_CURRENT_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_sw) &&
 				(PRE_EMPHASIS_SET_0_GET(lt_ctl_val[i]) ==
 						adj_req_em)) {
-				edp_info->lt_info.cr_loop[i]++;
-				if (edp_info->lt_info.cr_loop[i] == MAX_CR_LOOP)
+				priv->lt_info.cr_loop[i]++;
+				if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP)
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							regs, priv);
 			}
 
 			lt_ctl_val[i] = 0;
@@ -561,14 +575,15 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 				lt_ctl_val[i] |= MAX_DRIVE_CURRENT_REACH_3 |
 					MAX_PRE_EMPHASIS_REACH_3;
 			}
-			exynos_dp_set_lanex_pre_emphasis(lt_ctl_val[i], i);
+			exynos_dp_set_lanex_pre_emphasis(regs,
+							 lt_ctl_val[i], i);
 		}
 
-		ret = exynos_dp_write_bytes_to_dpcd(
+		ret = exynos_dp_write_bytes_to_dpcd(regs,
 				DPCD_TRAINING_LANE0_SET, 4, lt_ctl_val);
 		if (ret != EXYNOS_DP_SUCCESS) {
 			printf("DP write training pattern2 failed\n");
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 			return ret;
 		}
 	}
@@ -576,8 +591,8 @@ static unsigned int exynos_dp_process_clock_recovery(struct edp_device_info
 	return ret;
 }
 
-static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
-		*edp_info)
+static unsigned int exynos_dp_process_equalizer_training(
+		struct exynos_dp *regs, struct exynos_dp_priv *priv)
 {
 	unsigned int ret = EXYNOS_DP_SUCCESS;
 	unsigned char lane_stat, adj_req_sw, adj_req_em, i;
@@ -589,32 +604,33 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 
 	mdelay(1);
 
-	ret = exynos_dp_read_dpcd_lane_stat(edp_info, &lane_stat);
+	ret = exynos_dp_read_dpcd_lane_stat(regs, priv, &lane_stat);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP read lane status failed\n");
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
+		priv->lt_info.lt_status = DP_LT_FAIL;
 		return ret;
 	}
 
 	debug("DP lane stat : %x\n", lane_stat);
 
 	if (lane_stat & DP_LANE_STAT_CR_DONE) {
-		ret = exynos_dp_read_byte_from_dpcd(DPCD_LN_ALIGN_UPDATED,
-				&sink_stat);
+		ret = exynos_dp_read_byte_from_dpcd(regs,
+						    DPCD_LN_ALIGN_UPDATED,
+						    &sink_stat);
 		if (ret != EXYNOS_DP_SUCCESS) {
-			edp_info->lt_info.lt_status = DP_LT_FAIL;
+			priv->lt_info.lt_status = DP_LT_FAIL;
 
 			return ret;
 		}
 
 		interlane_aligned = (sink_stat & DPCD_INTERLANE_ALIGN_DONE);
 
-		for (i = 0; i < edp_info->lane_cnt; i++) {
-			ret = exynos_dp_read_dpcd_adj_req(i,
+		for (i = 0; i < priv->lane_cnt; i++) {
+			ret = exynos_dp_read_dpcd_adj_req(regs, i,
 					&adj_req_sw, &adj_req_em);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP read adj req 1 failed\n");
-				edp_info->lt_info.lt_status = DP_LT_FAIL;
+				priv->lt_info.lt_status = DP_LT_FAIL;
 
 				return ret;
 			}
@@ -634,86 +650,91 @@ static unsigned int exynos_dp_process_equalizer_training(struct edp_device_info
 			&& (interlane_aligned == DPCD_INTERLANE_ALIGN_DONE)) {
 			debug("DP Equalizer training succeed\n");
 
-			f_bw = exynos_dp_get_link_bandwidth();
-			f_lane_cnt = exynos_dp_get_lane_count();
+			f_bw = exynos_dp_get_link_bandwidth(regs);
+			f_lane_cnt = exynos_dp_get_lane_count(regs);
 
 			debug("DP final BandWidth : %x\n", f_bw);
 			debug("DP final Lane Count : %x\n", f_lane_cnt);
 
-			edp_info->lt_info.lt_status = DP_LT_FINISHED;
+			priv->lt_info.lt_status = DP_LT_FINISHED;
 
-			exynos_dp_equalizer_err_link(edp_info);
+			exynos_dp_equalizer_err_link(regs, priv);
 
 		} else {
-			edp_info->lt_info.ep_loop++;
+			priv->lt_info.ep_loop++;
 
-			if (edp_info->lt_info.ep_loop > MAX_EQ_LOOP) {
-				if (edp_info->lane_bw == DP_LANE_BW_2_70) {
+			if (priv->lt_info.ep_loop > MAX_EQ_LOOP) {
+				if (priv->lane_bw == DP_LANE_BW_2_70) {
 					ret = exynos_dp_reduce_link_rate(
-							edp_info);
+							regs, priv);
 				} else {
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			} else {
-				for (i = 0; i < edp_info->lane_cnt; i++)
+				for (i = 0; i < priv->lane_cnt; i++)
 					exynos_dp_set_lanex_pre_emphasis(
-							lt_ctl_val[i], i);
+						regs, lt_ctl_val[i], i);
 
-				ret = exynos_dp_write_bytes_to_dpcd(
-					DPCD_TRAINING_LANE0_SET,
-					4, lt_ctl_val);
+				ret = exynos_dp_write_bytes_to_dpcd(regs,
+						DPCD_TRAINING_LANE0_SET,
+						4, lt_ctl_val);
 				if (ret != EXYNOS_DP_SUCCESS) {
 					printf("DP set lt pattern failed\n");
-					edp_info->lt_info.lt_status =
+					priv->lt_info.lt_status =
 								DP_LT_FAIL;
-					exynos_dp_equalizer_err_link(edp_info);
+					exynos_dp_equalizer_err_link(regs,
+								     priv);
 				}
 			}
 		}
-	} else if (edp_info->lane_bw == DP_LANE_BW_2_70) {
-		ret = exynos_dp_reduce_link_rate(edp_info);
+	} else if (priv->lane_bw == DP_LANE_BW_2_70) {
+		ret = exynos_dp_reduce_link_rate(regs, priv);
 	} else {
-		edp_info->lt_info.lt_status = DP_LT_FAIL;
-		exynos_dp_equalizer_err_link(edp_info);
+		priv->lt_info.lt_status = DP_LT_FAIL;
+		exynos_dp_equalizer_err_link(regs, priv);
 	}
 
 	return ret;
 }
 
-static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_sw_link_training(struct exynos_dp *regs,
+					       struct exynos_dp_priv *priv)
 {
 	unsigned int ret = 0;
 	int training_finished;
 
 	/* Turn off unnecessary lane */
-	if (edp_info->lane_cnt == 1)
-		exynos_dp_set_analog_power_down(CH1_BLOCK, 1);
+	if (priv->lane_cnt == 1)
+		exynos_dp_set_analog_power_down(regs, CH1_BLOCK, 1);
 
 	training_finished = 0;
 
-	edp_info->lt_info.lt_status = DP_LT_START;
+	priv->lt_info.lt_status = DP_LT_START;
 
 	/* Process here */
 	while (!training_finished) {
-		switch (edp_info->lt_info.lt_status) {
+		switch (priv->lt_info.lt_status) {
 		case DP_LT_START:
-			ret = exynos_dp_link_start(edp_info);
+			ret = exynos_dp_link_start(regs, priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:link start failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_CR:
-			ret = exynos_dp_process_clock_recovery(edp_info);
+			ret = exynos_dp_process_clock_recovery(regs,
+							       priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:clock recovery failed\n");
 				return ret;
 			}
 			break;
 		case DP_LT_ET:
-			ret = exynos_dp_process_equalizer_training(edp_info);
+			ret = exynos_dp_process_equalizer_training(regs,
+								   priv);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				printf("DP LT:equalizer training failed\n");
 				return ret;
@@ -730,71 +751,75 @@ static unsigned int exynos_dp_sw_link_training(struct edp_device_info *edp_info)
 	return ret;
 }
 
-static unsigned int exynos_dp_set_link_train(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_set_link_train(struct exynos_dp *regs,
+					     struct exynos_dp_priv *priv)
 {
 	unsigned int ret;
 
-	exynos_dp_init_training();
+	exynos_dp_init_training(regs);
 
-	ret = exynos_dp_sw_link_training(edp_info);
+	ret = exynos_dp_sw_link_training(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS)
 		printf("DP dp_sw_link_training() failed\n");
 
 	return ret;
 }
 
-static void exynos_dp_enable_scramble(unsigned int enable)
+static void exynos_dp_enable_scramble(struct exynos_dp *regs,
+				      unsigned int enable)
 {
 	unsigned char data;
 
 	if (enable) {
-		exynos_dp_enable_scrambling(DP_ENABLE);
+		exynos_dp_enable_scrambling(regs, DP_ENABLE);
 
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_read_byte_from_dpcd(regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 	} else {
-		exynos_dp_enable_scrambling(DP_DISABLE);
-		exynos_dp_read_byte_from_dpcd(DPCD_TRAINING_PATTERN_SET,
-				&data);
-		exynos_dp_write_byte_to_dpcd(DPCD_TRAINING_PATTERN_SET,
+		exynos_dp_enable_scrambling(regs, DP_DISABLE);
+		exynos_dp_read_byte_from_dpcd(regs,
+					      DPCD_TRAINING_PATTERN_SET, &data);
+		exynos_dp_write_byte_to_dpcd(regs, DPCD_TRAINING_PATTERN_SET,
 			(u8)(data | DPCD_SCRAMBLING_DISABLED));
 	}
 }
 
-static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
+static unsigned int exynos_dp_config_video(struct exynos_dp *regs,
+					   struct exynos_dp_priv *priv)
 {
 	unsigned int ret = 0;
 	unsigned int retry_cnt;
 
 	mdelay(1);
 
-	if (edp_info->video_info.master_mode) {
+	if (priv->video_info.master_mode) {
 		printf("DP does not support master mode\n");
 		return -ENODEV;
 	} else {
 		/* debug slave */
-		exynos_dp_config_video_slave_mode(&edp_info->video_info);
+		exynos_dp_config_video_slave_mode(regs,
+						  &priv->video_info);
 	}
 
-	exynos_dp_set_video_color_format(&edp_info->video_info);
+	exynos_dp_set_video_color_format(regs, &priv->video_info);
 
-	if (edp_info->video_info.bist_mode) {
-		if (exynos_dp_config_video_bist(edp_info) != 0)
+	if (priv->video_info.bist_mode) {
+		if (exynos_dp_config_video_bist(regs, priv) != 0)
 			return -1;
 	}
 
-	ret = exynos_dp_get_pll_lock_status();
+	ret = exynos_dp_get_pll_lock_status(regs);
 	if (ret != PLL_LOCKED) {
 		printf("DP PLL is not locked yet\n");
 		return -EIO;
 	}
 
-	if (edp_info->video_info.master_mode == 0) {
+	if (priv->video_info.master_mode == 0) {
 		retry_cnt = 10;
 		while (retry_cnt) {
-			ret = exynos_dp_is_slave_video_stream_clock_on();
+			ret = exynos_dp_is_slave_video_stream_clock_on(regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP stream_clock_on failed\n");
@@ -808,32 +833,34 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	}
 
 	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(CALCULATED_M, 0, 0);
+	exynos_dp_set_video_cr_mn(regs, CALCULATED_M, 0, 0);
 
 	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(VIDEO_TIMING_FROM_CAPTURE);
+	exynos_dp_set_video_timing_mode(regs, VIDEO_TIMING_FROM_CAPTURE);
 
 	/* Enable video bist */
-	if (edp_info->video_info.bist_pattern != COLOR_RAMP &&
-		edp_info->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
-		edp_info->video_info.bist_pattern != COLOR_SQUARE)
-		exynos_dp_enable_video_bist(edp_info->video_info.bist_mode);
+	if (priv->video_info.bist_pattern != COLOR_RAMP &&
+		priv->video_info.bist_pattern != BALCK_WHITE_V_LINES &&
+		priv->video_info.bist_pattern != COLOR_SQUARE)
+		exynos_dp_enable_video_bist(regs,
+					    priv->video_info.bist_mode);
 	else
-		exynos_dp_enable_video_bist(DP_DISABLE);
+		exynos_dp_enable_video_bist(regs, DP_DISABLE);
 
 	/* Disable video mute */
-	exynos_dp_enable_video_mute(DP_DISABLE);
+	exynos_dp_enable_video_mute(regs, DP_DISABLE);
 
 	/* Configure video Master or Slave mode */
-	exynos_dp_enable_video_master(edp_info->video_info.master_mode);
+	exynos_dp_enable_video_master(regs,
+				      priv->video_info.master_mode);
 
 	/* Enable video */
-	exynos_dp_start_video();
+	exynos_dp_start_video(regs);
 
-	if (edp_info->video_info.master_mode == 0) {
+	if (priv->video_info.master_mode == 0) {
 		retry_cnt = 100;
 		while (retry_cnt) {
-			ret = exynos_dp_is_video_stream_on();
+			ret = exynos_dp_is_video_stream_on(regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Timeout of video stream\n");
@@ -849,107 +876,184 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
 	return ret;
 }
 
-int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
+static int exynos_dp_ofdata_to_platdata(struct udevice *dev)
 {
-	unsigned int node = fdtdec_next_compatible(blob, 0,
-						COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0) {
-		debug("exynos_dp: Can't get device node for dp\n");
-		return -ENODEV;
+	struct exynos_dp_priv *priv = dev_get_priv(dev);
+	const void *blob = gd->fdt_blob;
+	unsigned int node = dev->of_offset;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("Can't get the DP base address\n");
+		return -EINVAL;
 	}
-
-	edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
+	priv->regs = (struct exynos_dp *)addr;
+	priv->disp_info.h_res = fdtdec_get_int(blob, node,
 							"samsung,h-res", 0);
-	edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
+	priv->disp_info.h_sync_width = fdtdec_get_int(blob, node,
 						"samsung,h-sync-width", 0);
-	edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.h_back_porch = fdtdec_get_int(blob, node,
 						"samsung,h-back-porch", 0);
-	edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.h_front_porch = fdtdec_get_int(blob, node,
 						"samsung,h-front-porch", 0);
-	edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
+	priv->disp_info.v_res = fdtdec_get_int(blob, node,
 						"samsung,v-res", 0);
-	edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
+	priv->disp_info.v_sync_width = fdtdec_get_int(blob, node,
 						"samsung,v-sync-width", 0);
-	edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.v_back_porch = fdtdec_get_int(blob, node,
 						"samsung,v-back-porch", 0);
-	edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
+	priv->disp_info.v_front_porch = fdtdec_get_int(blob, node,
 						"samsung,v-front-porch", 0);
-	edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
+	priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
 						"samsung,v-sync-rate", 0);
 
-	edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
+	priv->lt_info.lt_status = fdtdec_get_int(blob, node,
 						"samsung,lt-status", 0);
 
-	edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
+	priv->video_info.master_mode = fdtdec_get_int(blob, node,
 						"samsung,master-mode", 0);
-	edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
+	priv->video_info.bist_mode = fdtdec_get_int(blob, node,
 						"samsung,bist-mode", 0);
-	edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
+	priv->video_info.bist_pattern = fdtdec_get_int(blob, node,
 						"samsung,bist-pattern", 0);
-	edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
+	priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
 						"samsung,h-sync-polarity", 0);
-	edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
+	priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
 						"samsung,v-sync-polarity", 0);
-	edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
+	priv->video_info.interlaced = fdtdec_get_int(blob, node,
 						"samsung,interlaced", 0);
-	edp_info->video_info.color_space = fdtdec_get_int(blob, node,
+	priv->video_info.color_space = fdtdec_get_int(blob, node,
 						"samsung,color-space", 0);
-	edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
+	priv->video_info.dynamic_range = fdtdec_get_int(blob, node,
 						"samsung,dynamic-range", 0);
-	edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
+	priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
 						"samsung,ycbcr-coeff", 0);
-	edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
+	priv->video_info.color_depth = fdtdec_get_int(blob, node,
 						"samsung,color-depth", 0);
 	return 0;
 }
 
-unsigned int exynos_init_dp(void)
+static int exynos_dp_bridge_init(struct udevice *dev)
 {
-	unsigned int ret;
-	struct edp_device_info *edp_info;
+	const int max_tries = 10;
+	int num_tries;
+	int ret;
+
+	debug("%s\n", __func__);
+	ret = video_bridge_attach(dev);
+	if (ret) {
+		debug("video bridge init failed: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * We need to wait for 90ms after bringing up the bridge since there
+	 * is a phantom "high" on the HPD chip during its bootup.  The phantom
+	 * high comes within 7ms of de-asserting PD and persists for at least
+	 * 15ms.  The real high comes roughly 50ms after PD is de-asserted. The
+	 * phantom high makes it hard for us to know when the NXP chip is up.
+	 */
+	mdelay(90);
+
+	for (num_tries = 0; num_tries < max_tries; num_tries++) {
+		/* Check HPD. If it's high, or we don't have it, all is well */
+		ret = video_bridge_check_attached(dev);
+		if (!ret || ret == -ENOENT)
+			return 0;
+
+		debug("%s: eDP bridge failed to come up; try %d of %d\n",
+		      __func__, num_tries, max_tries);
+	}
+
+	/* Immediately go into bridge reset if the hp line is not high */
+	return -EIO;
+}
+
+static int exynos_dp_bridge_setup(const void *blob)
+{
+	const int max_tries = 2;
+	int num_tries;
+	struct udevice *dev;
+	int ret;
 
-	edp_info = kzalloc(sizeof(struct edp_device_info), GFP_KERNEL);
-	if (!edp_info) {
-		debug("failed to allocate edp device object.\n");
-		return -EFAULT;
+	/* Configure I2C registers for Parade bridge */
+	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
+	if (ret) {
+		debug("video bridge init failed: %d\n", ret);
+		return ret;
 	}
 
-	if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
-		debug("unable to parse DP DT node\n");
+	if (strncmp(dev->driver->name, "parade", 6)) {
+		/* Mux HPHPD to the special hotplug detect mode */
+		exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
+	}
 
-	exynos_dp_set_base_addr();
+	for (num_tries = 0; num_tries < max_tries; num_tries++) {
+		ret = exynos_dp_bridge_init(dev);
+		if (!ret)
+			return 0;
+		if (num_tries == max_tries - 1)
+			break;
 
-	exynos_dp_disp_info(&edp_info->disp_info);
+		/*
+		* If we're here, the bridge chip failed to initialise.
+		* Power down the bridge in an attempt to reset.
+		*/
+		video_bridge_set_active(dev, false);
+
+		/*
+		* Arbitrarily wait 300ms here with DP_N low.  Don't know for
+		* sure how long we should wait, but we're being paranoid.
+		*/
+		mdelay(300);
+	}
 
-	exynos_set_dp_phy(1);
+	return ret;
+}
+int exynos_dp_enable(struct udevice *dev, int panel_bpp,
+		     const struct display_timing *timing)
+{
+	struct exynos_dp_priv *priv = dev_get_priv(dev);
+	struct exynos_dp *regs = priv->regs;
+	unsigned int ret;
+
+	debug("%s: start\n", __func__);
+	exynos_dp_disp_info(&priv->disp_info);
+
+	ret = exynos_dp_bridge_setup(gd->fdt_blob);
+	if (ret && ret != -ENODEV)
+		printf("LCD bridge failed to enable: %d\n", ret);
 
-	ret = exynos_dp_init_dp();
+	exynos_dp_phy_ctrl(1);
+
+	ret = exynos_dp_init_dp(regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP exynos_dp_init_dp() failed\n");
 		return ret;
 	}
 
-	ret = exynos_dp_handle_edid(edp_info);
+	ret = exynos_dp_handle_edid(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("EDP handle_edid fail\n");
 		return ret;
 	}
 
-	ret = exynos_dp_set_link_train(edp_info);
+	ret = exynos_dp_set_link_train(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP link training fail\n");
 		return ret;
 	}
 
-	exynos_dp_enable_scramble(DP_ENABLE);
-	exynos_dp_enable_rx_to_enhanced_mode(DP_ENABLE);
-	exynos_dp_enable_enhanced_mode(DP_ENABLE);
+	exynos_dp_enable_scramble(regs, DP_ENABLE);
+	exynos_dp_enable_rx_to_enhanced_mode(regs, DP_ENABLE);
+	exynos_dp_enable_enhanced_mode(regs, DP_ENABLE);
 
-	exynos_dp_set_link_bandwidth(edp_info->lane_bw);
-	exynos_dp_set_lane_count(edp_info->lane_cnt);
+	exynos_dp_set_link_bandwidth(regs, priv->lane_bw);
+	exynos_dp_set_lane_count(regs, priv->lane_cnt);
 
-	exynos_dp_init_video();
-	ret = exynos_dp_config_video(edp_info);
+	exynos_dp_init_video(regs);
+	ret = exynos_dp_config_video(regs, priv);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("Exynos DP init failed\n");
 		return ret;
@@ -959,3 +1063,22 @@ unsigned int exynos_init_dp(void)
 
 	return ret;
 }
+
+
+static const struct dm_display_ops exynos_dp_ops = {
+	.enable = exynos_dp_enable,
+};
+
+static const struct udevice_id exynos_dp_ids[] = {
+	{ .compatible = "samsung,exynos5-dp" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_dp) = {
+	.name	= "eexynos_dp",
+	.id	= UCLASS_DISPLAY,
+	.of_match = exynos_dp_ids,
+	.ops	= &exynos_dp_ops,
+	.ofdata_to_platdata	= exynos_dp_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_dp_priv),
+};
diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos/exynos_dp_lowlevel.c
index acb5bc8eb7..f9784738bb 100644
--- a/drivers/video/exynos_dp_lowlevel.c
+++ b/drivers/video/exynos/exynos_dp_lowlevel.c
@@ -14,30 +14,13 @@
 #include <asm/arch/dp.h>
 #include <fdtdec.h>
 #include <libfdt.h>
+#include "exynos_dp_lowlevel.h"
 
 /* Declare global data pointer */
 DECLARE_GLOBAL_DATA_PTR;
 
-struct exynos_dp *dp_regs;
-
-void exynos_dp_set_base_addr(void)
-{
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS5_DP);
-	if (node <= 0)
-		debug("exynos_dp: Can't get device node for dp\n");
-
-	dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-	if (dp_regs == NULL)
-		debug("Can't get the DP base address\n");
-#else
-	dp_regs = (struct exynos_dp *)samsung_get_base_dp();
-#endif
-}
-
-static void exynos_dp_enable_video_input(unsigned int enable)
+static void exynos_dp_enable_video_input(struct exynos_dp *dp_regs,
+					 unsigned int enable)
 {
 	unsigned int reg;
 
@@ -53,7 +36,7 @@ static void exynos_dp_enable_video_input(unsigned int enable)
 	return;
 }
 
-void exynos_dp_enable_video_bist(unsigned int enable)
+void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	/* enable video bist */
 	unsigned int reg;
@@ -70,7 +53,7 @@ void exynos_dp_enable_video_bist(unsigned int enable)
 	return;
 }
 
-void exynos_dp_enable_video_mute(unsigned int enable)
+void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -85,7 +68,7 @@ void exynos_dp_enable_video_mute(unsigned int enable)
 }
 
 
-static void exynos_dp_init_analog_param(void)
+static void exynos_dp_init_analog_param(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -134,7 +117,7 @@ static void exynos_dp_init_analog_param(void)
 	writel(reg, &dp_regs->pll_ctl);
 }
 
-static void exynos_dp_init_interrupt(void)
+static void exynos_dp_init_interrupt(struct exynos_dp *dp_regs)
 {
 	/* Set interrupt registers to initial states */
 
@@ -161,16 +144,16 @@ static void exynos_dp_init_interrupt(void)
 	writel(0x00, &dp_regs->int_sta_mask);
 }
 
-void exynos_dp_reset(void)
+void exynos_dp_reset(struct exynos_dp *dp_regs)
 {
 	unsigned int reg_func_1;
 
 	/* dp tx sw reset */
 	writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
 
-	exynos_dp_enable_video_input(DP_DISABLE);
-	exynos_dp_enable_video_bist(DP_DISABLE);
-	exynos_dp_enable_video_mute(DP_DISABLE);
+	exynos_dp_enable_video_input(dp_regs, DP_DISABLE);
+	exynos_dp_enable_video_bist(dp_regs, DP_DISABLE);
+	exynos_dp_enable_video_mute(dp_regs, DP_DISABLE);
 
 	/* software reset */
 	reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
@@ -182,13 +165,13 @@ void exynos_dp_reset(void)
 
 	mdelay(1);
 
-	exynos_dp_init_analog_param();
-	exynos_dp_init_interrupt();
+	exynos_dp_init_analog_param(dp_regs);
+	exynos_dp_init_interrupt(dp_regs);
 
 	return;
 }
 
-void exynos_dp_enable_sw_func(unsigned int enable)
+void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -203,7 +186,8 @@ void exynos_dp_enable_sw_func(unsigned int enable)
 	return;
 }
 
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
+unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
+					     unsigned int block, u32 enable)
 {
 	unsigned int reg;
 
@@ -256,7 +240,7 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
 	return 0;
 }
 
-unsigned int exynos_dp_get_pll_lock_status(void)
+unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -268,7 +252,8 @@ unsigned int exynos_dp_get_pll_lock_status(void)
 		return PLL_UNLOCKED;
 }
 
-static void exynos_dp_set_pll_power(unsigned int enable)
+static void exynos_dp_set_pll_power(struct exynos_dp *dp_regs,
+				    unsigned int enable)
 {
 	unsigned int reg;
 
@@ -281,14 +266,14 @@ static void exynos_dp_set_pll_power(unsigned int enable)
 	writel(reg, &dp_regs->pll_ctl);
 }
 
-int exynos_dp_init_analog_func(void)
+int exynos_dp_init_analog_func(struct exynos_dp *dp_regs)
 {
 	int ret = EXYNOS_DP_SUCCESS;
 	unsigned int retry_cnt = 10;
 	unsigned int reg;
 
 	/* Power On All Analog block */
-	exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
+	exynos_dp_set_analog_power_down(dp_regs, POWER_ALL, DP_DISABLE);
 
 	reg = PLL_LOCK_CHG;
 	writel(reg, &dp_regs->common_int_sta1);
@@ -309,9 +294,9 @@ int exynos_dp_init_analog_func(void)
 	reg &= ~(DP_PLL_RESET);
 	writel(reg, &dp_regs->pll_ctl);
 
-	exynos_dp_set_pll_power(DP_ENABLE);
+	exynos_dp_set_pll_power(dp_regs, DP_ENABLE);
 
-	while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) {
+	while (exynos_dp_get_pll_lock_status(dp_regs) == PLL_UNLOCKED) {
 		mdelay(1);
 		retry_cnt--;
 		if (retry_cnt == 0) {
@@ -332,7 +317,7 @@ int exynos_dp_init_analog_func(void)
 	return ret;
 }
 
-void exynos_dp_init_hpd(void)
+void exynos_dp_init_hpd(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -350,7 +335,7 @@ void exynos_dp_init_hpd(void)
 	return;
 }
 
-static inline void exynos_dp_reset_aux(void)
+static inline void exynos_dp_reset_aux(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -362,7 +347,7 @@ static inline void exynos_dp_reset_aux(void)
 	return;
 }
 
-void exynos_dp_init_aux(void)
+void exynos_dp_init_aux(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -370,7 +355,7 @@ void exynos_dp_init_aux(void)
 	reg = RPLY_RECEIV | AUX_ERR;
 	writel(reg, &dp_regs->int_sta);
 
-	exynos_dp_reset_aux();
+	exynos_dp_reset_aux(dp_regs);
 
 	/* Disable AUX transaction H/W retry */
 	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)|
@@ -389,7 +374,7 @@ void exynos_dp_init_aux(void)
 	return;
 }
 
-void exynos_dp_config_interrupt(void)
+void exynos_dp_config_interrupt(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -412,7 +397,7 @@ void exynos_dp_config_interrupt(void)
 	return;
 }
 
-unsigned int exynos_dp_get_plug_in_status(void)
+unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -423,13 +408,13 @@ unsigned int exynos_dp_get_plug_in_status(void)
 	return -1;
 }
 
-unsigned int exynos_dp_detect_hpd(void)
+unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs)
 {
 	int timeout_loop = DP_TIMEOUT_LOOP_COUNT;
 
 	mdelay(2);
 
-	while (exynos_dp_get_plug_in_status() != 0) {
+	while (exynos_dp_get_plug_in_status(dp_regs) != 0) {
 		if (timeout_loop == 0)
 			return -EINVAL;
 		mdelay(10);
@@ -439,7 +424,7 @@ unsigned int exynos_dp_detect_hpd(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-unsigned int exynos_dp_start_aux_transaction(void)
+unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 	unsigned int ret = 0;
@@ -488,8 +473,9 @@ unsigned int exynos_dp_start_aux_transaction(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data)
+unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
+					  unsigned int reg_addr,
+					  unsigned char data)
 {
 	unsigned int reg, ret;
 
@@ -518,7 +504,7 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	ret = exynos_dp_start_aux_transaction();
+	ret = exynos_dp_start_aux_transaction(dp_regs);
 	if (ret != EXYNOS_DP_SUCCESS) {
 		printf("DP Aux transaction failed\n");
 		return ret;
@@ -527,8 +513,9 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data)
+unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned char *data)
 {
 	unsigned int reg;
 	int retval;
@@ -554,7 +541,7 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
+	retval = exynos_dp_start_aux_transaction(dp_regs);
 	if (!retval)
 		debug("DP Aux Transaction fail!\n");
 
@@ -565,9 +552,10 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
 	return retval;
 }
 
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned int count,
+					   unsigned char data[])
 {
 	unsigned int reg;
 	unsigned int start_offset;
@@ -614,7 +602,7 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
 			writel(reg, &dp_regs->aux_ch_ctl1);
 
 			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
+			ret = exynos_dp_start_aux_transaction(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Aux Transaction failed\n");
@@ -630,9 +618,10 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
+					    unsigned int reg_addr,
+					    unsigned int count,
+					    unsigned char data[])
 {
 	unsigned int reg;
 	unsigned int start_offset;
@@ -672,7 +661,7 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
 			writel(reg, &dp_regs->aux_ch_ctl1);
 
 			/* Start AUX transaction */
-			ret = exynos_dp_start_aux_transaction();
+			ret = exynos_dp_start_aux_transaction(dp_regs);
 			if (ret != EXYNOS_DP_SUCCESS) {
 				if (retry_cnt == 0) {
 					printf("DP Aux Transaction failed\n");
@@ -696,8 +685,8 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
 	return ret;
 }
 
-int exynos_dp_select_i2c_device(unsigned int device_addr,
-				unsigned int reg_addr)
+int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
+				unsigned int device_addr, unsigned int reg_addr)
 {
 	unsigned int reg;
 	int retval;
@@ -721,16 +710,16 @@ int exynos_dp_select_i2c_device(unsigned int device_addr,
 	writel(reg, &dp_regs->aux_ch_ctl1);
 
 	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction();
+	retval = exynos_dp_start_aux_transaction(dp_regs);
 	if (retval != 0)
 		printf("%s: DP Aux Transaction fail!\n", __func__);
 
 	return retval;
 }
 
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
+				 unsigned int device_addr,
+				 unsigned int reg_addr, unsigned int *data)
 {
 	unsigned int reg;
 	int i;
@@ -742,7 +731,8 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 		writel(reg, &dp_regs->buffer_data_ctl);
 
 		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(device_addr, reg_addr);
+		retval = exynos_dp_select_i2c_device(dp_regs, device_addr,
+						     reg_addr);
 		if (retval != 0) {
 			printf("DP Select EDID device fail. retry !\n");
 			continue;
@@ -758,7 +748,7 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 		writel(reg, &dp_regs->aux_ch_ctl1);
 
 		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction();
+		retval = exynos_dp_start_aux_transaction(dp_regs);
 		if (retval != EXYNOS_DP_SUCCESS)
 			printf("%s: DP Aux Transaction fail!\n", __func__);
 	}
@@ -770,8 +760,10 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
 	return retval;
 }
 
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count, unsigned char edid[])
+int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
+				  unsigned int device_addr,
+				  unsigned int reg_addr, unsigned int count,
+				  unsigned char edid[])
 {
 	unsigned int reg;
 	unsigned int i, j;
@@ -795,9 +787,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 			 * request without sending addres
 			 */
 			if (!defer)
-				retval =
-					exynos_dp_select_i2c_device(device_addr,
-							reg_addr + i);
+				retval = exynos_dp_select_i2c_device(
+					dp_regs, device_addr, reg_addr + i);
 			else
 				defer = 0;
 
@@ -813,7 +804,8 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 				writel(reg, &dp_regs->aux_ch_ctl1);
 
 				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction();
+				retval = exynos_dp_start_aux_transaction(
+							dp_regs);
 				if (retval == 0)
 					break;
 				else
@@ -838,7 +830,7 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
 	return retval;
 }
 
-void exynos_dp_reset_macro(void)
+void exynos_dp_reset_macro(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -853,7 +845,8 @@ void exynos_dp_reset_macro(void)
 	writel(reg, &dp_regs->phy_test);
 }
 
-void exynos_dp_set_link_bandwidth(unsigned char bwtype)
+void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
+				  unsigned char bwtype)
 {
 	unsigned int reg;
 
@@ -864,7 +857,7 @@ void exynos_dp_set_link_bandwidth(unsigned char bwtype)
 		writel(reg, &dp_regs->link_bw_set);
 }
 
-unsigned char exynos_dp_get_link_bandwidth(void)
+unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs)
 {
 	unsigned char ret;
 	unsigned int reg;
@@ -875,7 +868,7 @@ unsigned char exynos_dp_get_link_bandwidth(void)
 	return ret;
 }
 
-void exynos_dp_set_lane_count(unsigned char count)
+void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count)
 {
 	unsigned int reg;
 
@@ -886,7 +879,7 @@ void exynos_dp_set_lane_count(unsigned char count)
 		writel(reg, &dp_regs->lane_count_set);
 }
 
-unsigned int exynos_dp_get_lane_count(void)
+unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -895,7 +888,8 @@ unsigned int exynos_dp_get_lane_count(void)
 	return reg;
 }
 
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
+unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+					       unsigned char lanecnt)
 {
 	unsigned int reg_list[DP_LANE_CNT_4] = {
 		(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -907,8 +901,9 @@ unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
 	return readl(reg_list[lanecnt]);
 }
 
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt)
+void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+				      unsigned char request_val,
+				      unsigned char lanecnt)
 {
 	unsigned int reg_list[DP_LANE_CNT_4] = {
 		(unsigned int)&dp_regs->ln0_link_training_ctl,
@@ -920,7 +915,8 @@ void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
 	writel(request_val, reg_list[lanecnt]);
 }
 
-void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
+void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
+				     unsigned int level, unsigned char lanecnt)
 {
 	unsigned char i;
 	unsigned int reg;
@@ -943,7 +939,8 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
 	}
 }
 
-void exynos_dp_set_training_pattern(unsigned int pattern)
+void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
+				    unsigned int pattern)
 {
 	unsigned int reg = 0;
 
@@ -971,7 +968,8 @@ void exynos_dp_set_training_pattern(unsigned int pattern)
 	writel(reg, &dp_regs->training_ptn_set);
 }
 
-void exynos_dp_enable_enhanced_mode(unsigned char enable)
+void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
+				    unsigned char enable)
 {
 	unsigned int reg;
 
@@ -984,7 +982,7 @@ void exynos_dp_enable_enhanced_mode(unsigned char enable)
 	writel(reg, &dp_regs->sys_ctl4);
 }
 
-void exynos_dp_enable_scrambling(unsigned int enable)
+void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, unsigned int enable)
 {
 	unsigned int reg;
 
@@ -997,7 +995,7 @@ void exynos_dp_enable_scrambling(unsigned int enable)
 	writel(reg, &dp_regs->training_ptn_set);
 }
 
-int exynos_dp_init_video(void)
+int exynos_dp_init_video(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1012,7 +1010,8 @@ int exynos_dp_init_video(void)
 	return 0;
 }
 
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
+void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
+				       struct edp_video_info *video_info)
 {
 	unsigned int reg;
 
@@ -1045,7 +1044,8 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
 	writel(reg, &dp_regs->soc_general_ctl);
 }
 
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
+void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
+				      struct edp_video_info *video_info)
 {
 	unsigned int reg;
 
@@ -1065,49 +1065,47 @@ void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
 	writel(reg, &dp_regs->video_ctl3);
 }
 
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
+int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
+				struct exynos_dp_priv *priv)
 {
 	unsigned int reg;
 	unsigned int bist_type = 0;
-	struct edp_video_info video_info = edp_info->video_info;
+	struct edp_video_info video_info = priv->video_info;
 
 	/* For master mode, you don't need to set the video format */
 	if (video_info.master_mode == 0) {
-		writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_l);
-		writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total),
-				&dp_regs->total_ln_cfg_h);
-		writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_l);
-		writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res),
-				&dp_regs->active_ln_cfg_h);
-		writel(edp_info->disp_info.v_sync_width,
-				&dp_regs->vsw_cfg);
-		writel(edp_info->disp_info.v_back_porch,
-				&dp_regs->vbp_cfg);
-		writel(edp_info->disp_info.v_front_porch,
-				&dp_regs->vfp_cfg);
-
-		writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_l);
-		writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total),
-				&dp_regs->total_pix_cfg_h);
-		writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_l);
-		writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res),
-				&dp_regs->active_pix_cfg_h);
-		writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_l);
-		writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch),
-				&dp_regs->hfp_cfg_h);
-		writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_l);
-		writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width),
-				&dp_regs->hsw_cfg_h);
-		writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_l);
-		writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch),
-				&dp_regs->hbp_cfg_h);
+		writel(TOTAL_LINE_CFG_L(priv->disp_info.v_total),
+		       &dp_regs->total_ln_cfg_l);
+		writel(TOTAL_LINE_CFG_H(priv->disp_info.v_total),
+		       &dp_regs->total_ln_cfg_h);
+		writel(ACTIVE_LINE_CFG_L(priv->disp_info.v_res),
+		       &dp_regs->active_ln_cfg_l);
+		writel(ACTIVE_LINE_CFG_H(priv->disp_info.v_res),
+		       &dp_regs->active_ln_cfg_h);
+		writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg);
+		writel(priv->disp_info.v_back_porch, &dp_regs->vbp_cfg);
+		writel(priv->disp_info.v_front_porch, &dp_regs->vfp_cfg);
+
+		writel(TOTAL_PIXEL_CFG_L(priv->disp_info.h_total),
+		       &dp_regs->total_pix_cfg_l);
+		writel(TOTAL_PIXEL_CFG_H(priv->disp_info.h_total),
+		       &dp_regs->total_pix_cfg_h);
+		writel(ACTIVE_PIXEL_CFG_L(priv->disp_info.h_res),
+		       &dp_regs->active_pix_cfg_l);
+		writel(ACTIVE_PIXEL_CFG_H(priv->disp_info.h_res),
+		       &dp_regs->active_pix_cfg_h);
+		writel(H_F_PORCH_CFG_L(priv->disp_info.h_front_porch),
+		       &dp_regs->hfp_cfg_l);
+		writel(H_F_PORCH_CFG_H(priv->disp_info.h_front_porch),
+		       &dp_regs->hfp_cfg_h);
+		writel(H_SYNC_PORCH_CFG_L(priv->disp_info.h_sync_width),
+		       &dp_regs->hsw_cfg_l);
+		writel(H_SYNC_PORCH_CFG_H(priv->disp_info.h_sync_width),
+		       &dp_regs->hsw_cfg_h);
+		writel(H_B_PORCH_CFG_L(priv->disp_info.h_back_porch),
+		       &dp_regs->hbp_cfg_l);
+		writel(H_B_PORCH_CFG_H(priv->disp_info.h_back_porch),
+		       &dp_regs->hbp_cfg_h);
 
 		/*
 		 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1],
@@ -1155,7 +1153,7 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
 	return 0;
 }
 
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
+unsigned int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1173,8 +1171,8 @@ unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
 	return EXYNOS_DP_SUCCESS;
 }
 
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value)
+void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
+			       unsigned int m_value, unsigned int n_value)
 {
 	unsigned int reg;
 
@@ -1202,7 +1200,8 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
 	}
 }
 
-void exynos_dp_set_video_timing_mode(unsigned int type)
+void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
+				     unsigned int type)
 {
 	unsigned int reg;
 
@@ -1215,7 +1214,8 @@ void exynos_dp_set_video_timing_mode(unsigned int type)
 	writel(reg, &dp_regs->video_ctl10);
 }
 
-void exynos_dp_enable_video_master(unsigned int enable)
+void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
+				   unsigned int enable)
 {
 	unsigned int reg;
 
@@ -1231,7 +1231,7 @@ void exynos_dp_enable_video_master(unsigned int enable)
 	writel(reg, &dp_regs->soc_general_ctl);
 }
 
-void exynos_dp_start_video(void)
+void exynos_dp_start_video(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
@@ -1241,7 +1241,7 @@ void exynos_dp_start_video(void)
 	writel(reg, &dp_regs->video_ctl1);
 }
 
-unsigned int exynos_dp_is_video_stream_on(void)
+unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs)
 {
 	unsigned int reg;
 
diff --git a/drivers/video/exynos/exynos_dp_lowlevel.h b/drivers/video/exynos/exynos_dp_lowlevel.h
new file mode 100644
index 0000000000..e4c867eef0
--- /dev/null
+++ b/drivers/video/exynos/exynos_dp_lowlevel.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_EDP_LOWLEVEL_H
+#define _EXYNOS_EDP_LOWLEVEL_H
+
+void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+void exynos_dp_reset(struct exynos_dp *dp_regs);
+void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable);
+unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs,
+					     unsigned int block, u32 enable);
+unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs);
+int exynos_dp_init_analog_func(struct exynos_dp *dp_regs);
+void exynos_dp_init_hpd(struct exynos_dp *dp_regs);
+void exynos_dp_init_aux(struct exynos_dp *dp_regs);
+void exynos_dp_config_interrupt(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs,
+					  unsigned int reg_addr,
+					  unsigned char data);
+unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned char *data);
+unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs,
+					   unsigned int reg_addr,
+					   unsigned int count,
+					   unsigned char data[]);
+unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs,
+					    unsigned int reg_addr,
+					    unsigned int count,
+					    unsigned char data[]);
+int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs,
+				 unsigned int device_addr,
+				 unsigned int reg_addr, unsigned int *data);
+int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs,
+				  unsigned int device_addr,
+				  unsigned int reg_addr, unsigned int count,
+				  unsigned char edid[]);
+void exynos_dp_reset_macro(struct exynos_dp *dp_regs);
+void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs,
+				  unsigned char bwtype);
+unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs);
+void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count);
+unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs);
+unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+					       unsigned char lanecnt);
+void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs,
+				     unsigned int level, unsigned char lanecnt);
+void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs,
+				      unsigned char request_val,
+				      unsigned char lanecnt);
+void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs,
+				    unsigned int pattern);
+void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs,
+				    unsigned char enable);
+void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs,
+				 unsigned int enable);
+int exynos_dp_init_video(struct exynos_dp *dp_regs);
+void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs,
+				       struct edp_video_info *video_info);
+void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs,
+				      struct edp_video_info *video_info);
+int exynos_dp_config_video_bist(struct exynos_dp *dp_regs,
+				struct exynos_dp_priv *priv);
+unsigned int exynos_dp_is_slave_video_stream_clock_on(
+					struct exynos_dp *dp_regs);
+void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type,
+			       unsigned int m_value, unsigned int n_value);
+void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs,
+				     unsigned int type);
+void exynos_dp_enable_video_master(struct exynos_dp *dp_regs,
+				   unsigned int enable);
+void exynos_dp_start_video(struct exynos_dp *dp_regs);
+unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs);
+
+#endif /* _EXYNOS_DP_LOWLEVEL_H */
diff --git a/drivers/video/exynos/exynos_fb.c b/drivers/video/exynos/exynos_fb.c
new file mode 100644
index 0000000000..97228cd3cc
--- /dev/null
+++ b/drivers/video/exynos/exynos_fb.c
@@ -0,0 +1,720 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * Author: InKi Dae <inki.dae@samsung.com>
+ * Author: Donghwa Lee <dh09.lee@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <display.h>
+#include <div64.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <panel.h>
+#include <video.h>
+#include <video_bridge.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/mipi_dsim.h>
+#include <asm/arch/dp_info.h>
+#include <asm/arch/fb.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/system.h>
+#include <asm/gpio.h>
+#include <asm-generic/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+struct exynos_fb_priv {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_rot;		/* Rotation of Display (0, 1, 2, 3) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+	struct exynos_fb *reg;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
+};
+
+static void exynos_fimd_set_dualrgb(struct exynos_fb_priv *priv, bool enabled)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	if (enabled) {
+		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
+			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
+
+		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+		cfg |= EXYNOS_DUALRGB_SUB_CNT(priv->vl_col / 2) |
+			EXYNOS_DUALRGB_MAIN_CNT(0);
+	}
+
+	writel(cfg, &reg->dualrgb);
+}
+
+static void exynos_fimd_set_dp_clkcon(struct exynos_fb_priv *priv,
+				      unsigned int enabled)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	if (enabled)
+		cfg = EXYNOS_DP_CLK_ENABLE;
+
+	writel(cfg, &reg->dp_mie_clkcon);
+}
+
+static void exynos_fimd_set_par(struct exynos_fb_priv *priv,
+				unsigned int win_id)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	/* set window control */
+	cfg = readl((unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
+		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
+		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
+		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
+
+	/* DATAPATH is DMA */
+	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
+
+	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
+
+	/* dma burst is 16 */
+	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
+
+	switch (priv->vl_bpix) {
+	case 4:
+		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
+		break;
+	default:
+		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+		break;
+	}
+
+	writel(cfg, (unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	/* set window position to x=0, y=0*/
+	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
+	writel(cfg, (unsigned int)&reg->vidosd0a +
+			EXYNOS_VIDOSD(win_id));
+
+	cfg = EXYNOS_VIDOSD_RIGHT_X(priv->vl_col - 1) |
+		EXYNOS_VIDOSD_BOTTOM_Y(priv->vl_row - 1) |
+		EXYNOS_VIDOSD_RIGHT_X_E(1) |
+		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
+
+	writel(cfg, (unsigned int)&reg->vidosd0b +
+			EXYNOS_VIDOSD(win_id));
+
+	/* set window size for window0*/
+	cfg = EXYNOS_VIDOSD_SIZE(priv->vl_col * priv->vl_row);
+	writel(cfg, (unsigned int)&reg->vidosd0c +
+			EXYNOS_VIDOSD(win_id));
+}
+
+static void exynos_fimd_set_buffer_address(struct exynos_fb_priv *priv,
+					   unsigned int win_id,
+					   ulong lcd_base_addr)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned long start_addr, end_addr;
+
+	start_addr = lcd_base_addr;
+	end_addr = start_addr + ((priv->vl_col * (VNBITS(priv->vl_bpix) / 8)) *
+				priv->vl_row);
+
+	writel(start_addr, (unsigned int)&reg->vidw00add0b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+	writel(end_addr, (unsigned int)&reg->vidw00add1b0 +
+			EXYNOS_BUFFER_OFFSET(win_id));
+}
+
+static void exynos_fimd_set_clock(struct exynos_fb_priv *priv)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0, div = 0, remainder, remainder_div;
+	unsigned long pixel_clock;
+	unsigned long long src_clock;
+
+	if (priv->dual_lcd_enabled) {
+		pixel_clock = priv->vl_freq *
+				(priv->vl_hspw + priv->vl_hfpd +
+				 priv->vl_hbpd + priv->vl_col / 2) *
+				(priv->vl_vspw + priv->vl_vfpd +
+				 priv->vl_vbpd + priv->vl_row);
+	} else if (priv->interface_mode == FIMD_CPU_INTERFACE) {
+		pixel_clock = priv->vl_freq *
+				priv->vl_width * priv->vl_height *
+				(priv->cs_setup + priv->wr_setup +
+				 priv->wr_act + priv->wr_hold + 1);
+	} else {
+		pixel_clock = priv->vl_freq *
+				(priv->vl_hspw + priv->vl_hfpd +
+				 priv->vl_hbpd + priv->vl_col) *
+				(priv->vl_vspw + priv->vl_vfpd +
+				 priv->vl_vbpd + priv->vl_row);
+	}
+
+	cfg = readl(&reg->vidcon0);
+	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
+		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
+		EXYNOS_VIDCON0_CLKDIR_MASK);
+	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
+		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
+
+	src_clock = (unsigned long long) get_lcd_clk();
+
+	/* get quotient and remainder. */
+	remainder = do_div(src_clock, pixel_clock);
+	div = src_clock;
+
+	remainder *= 10;
+	remainder_div = remainder / pixel_clock;
+
+	/* round about one places of decimals. */
+	if (remainder_div >= 5)
+		div++;
+
+	/* in case of dual lcd mode. */
+	if (priv->dual_lcd_enabled)
+		div--;
+
+	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
+	writel(cfg, &reg->vidcon0);
+}
+
+void exynos_set_trigger(struct exynos_fb_priv *priv)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	cfg = readl(&reg->trigcon);
+
+	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
+
+	writel(cfg, &reg->trigcon);
+}
+
+int exynos_is_i80_frame_done(struct exynos_fb_priv *priv)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+	int status;
+
+	cfg = readl(&reg->trigcon);
+
+	/* frame done func is valid only when TRIMODE[0] is set to 1. */
+	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
+			EXYNOS_I80STATUS_TRIG_DONE;
+
+	return status;
+}
+
+static void exynos_fimd_lcd_on(struct exynos_fb_priv *priv)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	/* display on */
+	cfg = readl(&reg->vidcon0);
+	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
+	writel(cfg, &reg->vidcon0);
+}
+
+static void exynos_fimd_window_on(struct exynos_fb_priv *priv,
+				  unsigned int win_id)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	/* enable window */
+	cfg = readl((unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
+	writel(cfg, (unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&reg->winshmap);
+	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
+	writel(cfg, &reg->winshmap);
+}
+
+void exynos_fimd_lcd_off(struct exynos_fb_priv *priv)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	cfg = readl(&reg->vidcon0);
+	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
+	writel(cfg, &reg->vidcon0);
+}
+
+void exynos_fimd_window_off(struct exynos_fb_priv *priv, unsigned int win_id)
+{
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0;
+
+	cfg = readl((unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
+	writel(cfg, (unsigned int)&reg->wincon0 +
+			EXYNOS_WINCON(win_id));
+
+	cfg = readl(&reg->winshmap);
+	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
+	writel(cfg, &reg->winshmap);
+}
+
+/*
+* The reset value for FIMD SYSMMU register MMU_CTRL is 3
+* on Exynos5420 and newer versions.
+* This means FIMD SYSMMU is on by default on Exynos5420
+* and newer versions.
+* Since in u-boot we don't use SYSMMU, we should disable
+* those FIMD SYSMMU.
+* Note that there are 2 SYSMMU for FIMD: m0 and m1.
+* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
+* We disable both of them here.
+*/
+void exynos_fimd_disable_sysmmu(void)
+{
+	u32 *sysmmufimd;
+	unsigned int node;
+	int node_list[2];
+	int count;
+	int i;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
+				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
+	for (i = 0; i < count; i++) {
+		node = node_list[i];
+		if (node <= 0) {
+			debug("Can't get device node for fimd sysmmu\n");
+			return;
+		}
+
+		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
+		if (!sysmmufimd) {
+			debug("Can't get base address for sysmmu fimdm0");
+			return;
+		}
+
+		writel(0x0, sysmmufimd);
+	}
+}
+
+void exynos_fimd_lcd_init(struct udevice *dev)
+{
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+	struct exynos_fb *reg = priv->reg;
+	unsigned int cfg = 0, rgb_mode;
+	unsigned int offset;
+	unsigned int node;
+
+	node = dev->of_offset;
+	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
+		exynos_fimd_disable_sysmmu();
+
+	offset = exynos_fimd_get_base_offset();
+
+	rgb_mode = priv->rgb_mode;
+
+	if (priv->interface_mode == FIMD_RGB_INTERFACE) {
+		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
+		writel(cfg, &reg->vidcon0);
+
+		cfg = readl(&reg->vidcon2);
+		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
+			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
+		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
+		writel(cfg, &reg->vidcon2);
+
+		/* set polarity */
+		cfg = 0;
+		if (!priv->vl_clkp)
+			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
+		if (!priv->vl_hsp)
+			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
+		if (!priv->vl_vsp)
+			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
+		if (!priv->vl_dp)
+			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
+
+		writel(cfg, (unsigned int)&reg->vidcon1 + offset);
+
+		/* set timing */
+		cfg = EXYNOS_VIDTCON0_VFPD(priv->vl_vfpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VBPD(priv->vl_vbpd - 1);
+		cfg |= EXYNOS_VIDTCON0_VSPW(priv->vl_vspw - 1);
+		writel(cfg, (unsigned int)&reg->vidtcon0 + offset);
+
+		cfg = EXYNOS_VIDTCON1_HFPD(priv->vl_hfpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HBPD(priv->vl_hbpd - 1);
+		cfg |= EXYNOS_VIDTCON1_HSPW(priv->vl_hspw - 1);
+
+		writel(cfg, (unsigned int)&reg->vidtcon1 + offset);
+
+		/* set lcd size */
+		cfg = EXYNOS_VIDTCON2_HOZVAL(priv->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL(priv->vl_row - 1) |
+			EXYNOS_VIDTCON2_HOZVAL_E(priv->vl_col - 1) |
+			EXYNOS_VIDTCON2_LINEVAL_E(priv->vl_row - 1);
+
+		writel(cfg, (unsigned int)&reg->vidtcon2 + offset);
+	}
+
+	/* set display mode */
+	cfg = readl(&reg->vidcon0);
+	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
+	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
+	writel(cfg, &reg->vidcon0);
+
+	/* set par */
+	exynos_fimd_set_par(priv, priv->win_id);
+
+	/* set memory address */
+	exynos_fimd_set_buffer_address(priv, priv->win_id, plat->base);
+
+	/* set buffer size */
+	cfg = EXYNOS_VIDADDR_PAGEWIDTH(priv->vl_col *
+			VNBITS(priv->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_PAGEWIDTH_E(priv->vl_col *
+			VNBITS(priv->vl_bpix) / 8) |
+		EXYNOS_VIDADDR_OFFSIZE(0) |
+		EXYNOS_VIDADDR_OFFSIZE_E(0);
+
+	writel(cfg, (unsigned int)&reg->vidw00add2 +
+					EXYNOS_BUFFER_SIZE(priv->win_id));
+
+	/* set clock */
+	exynos_fimd_set_clock(priv);
+
+	/* set rgb mode to dual lcd. */
+	exynos_fimd_set_dualrgb(priv, priv->dual_lcd_enabled);
+
+	/* display on */
+	exynos_fimd_lcd_on(priv);
+
+	/* window on */
+	exynos_fimd_window_on(priv, priv->win_id);
+
+	exynos_fimd_set_dp_clkcon(priv, priv->dp_enabled);
+}
+
+unsigned long exynos_fimd_calc_fbsize(struct exynos_fb_priv *priv)
+{
+	return priv->vl_col * priv->vl_row * (VNBITS(priv->vl_bpix) / 8);
+}
+
+int exynos_fb_ofdata_to_platdata(struct udevice *dev)
+{
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	unsigned int node = dev->of_offset;
+	const void *blob = gd->fdt_blob;
+	fdt_addr_t addr;
+
+	addr = dev_get_addr(dev);
+	if (addr == FDT_ADDR_T_NONE) {
+		debug("Can't get the FIMD base address\n");
+		return -EINVAL;
+	}
+	priv->reg = (struct exynos_fb *)addr;
+
+	priv->vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
+	if (priv->vl_col == 0) {
+		debug("Can't get XRES\n");
+		return -ENXIO;
+	}
+
+	priv->vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
+	if (priv->vl_row == 0) {
+		debug("Can't get YRES\n");
+		return -ENXIO;
+	}
+
+	priv->vl_width = fdtdec_get_int(blob, node,
+						"samsung,vl-width", 0);
+
+	priv->vl_height = fdtdec_get_int(blob, node,
+						"samsung,vl-height", 0);
+
+	priv->vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
+	if (priv->vl_freq == 0) {
+		debug("Can't get refresh rate\n");
+		return -ENXIO;
+	}
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
+		priv->vl_clkp = VIDEO_ACTIVE_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
+		priv->vl_oep = VIDEO_ACTIVE_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
+		priv->vl_hsp = VIDEO_ACTIVE_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
+		priv->vl_vsp = VIDEO_ACTIVE_LOW;
+
+	if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
+		priv->vl_dp = VIDEO_ACTIVE_LOW;
+
+	priv->vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
+	if (priv->vl_bpix == 0) {
+		debug("Can't get bits per pixel\n");
+		return -ENXIO;
+	}
+
+	priv->vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
+	if (priv->vl_hspw == 0) {
+		debug("Can't get hsync width\n");
+		return -ENXIO;
+	}
+
+	priv->vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
+	if (priv->vl_hfpd == 0) {
+		debug("Can't get right margin\n");
+		return -ENXIO;
+	}
+
+	priv->vl_hbpd = (u_char)fdtdec_get_int(blob, node,
+							"samsung,vl-hbpd", 0);
+	if (priv->vl_hbpd == 0) {
+		debug("Can't get left margin\n");
+		return -ENXIO;
+	}
+
+	priv->vl_vspw = (u_char)fdtdec_get_int(blob, node,
+							"samsung,vl-vspw", 0);
+	if (priv->vl_vspw == 0) {
+		debug("Can't get vsync width\n");
+		return -ENXIO;
+	}
+
+	priv->vl_vfpd = fdtdec_get_int(blob, node,
+							"samsung,vl-vfpd", 0);
+	if (priv->vl_vfpd == 0) {
+		debug("Can't get lower margin\n");
+		return -ENXIO;
+	}
+
+	priv->vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
+	if (priv->vl_vbpd == 0) {
+		debug("Can't get upper margin\n");
+		return -ENXIO;
+	}
+
+	priv->vl_cmd_allow_len = fdtdec_get_int(blob, node,
+						"samsung,vl-cmd-allow-len", 0);
+
+	priv->win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
+	priv->init_delay = fdtdec_get_int(blob, node,
+						"samsung,init-delay", 0);
+	priv->power_on_delay = fdtdec_get_int(blob, node,
+						"samsung,power-on-delay", 0);
+	priv->reset_delay = fdtdec_get_int(blob, node,
+						"samsung,reset-delay", 0);
+	priv->interface_mode = fdtdec_get_int(blob, node,
+						"samsung,interface-mode", 0);
+	priv->mipi_enabled = fdtdec_get_int(blob, node,
+						"samsung,mipi-enabled", 0);
+	priv->dp_enabled = fdtdec_get_int(blob, node,
+						"samsung,dp-enabled", 0);
+	priv->cs_setup = fdtdec_get_int(blob, node,
+						"samsung,cs-setup", 0);
+	priv->wr_setup = fdtdec_get_int(blob, node,
+						"samsung,wr-setup", 0);
+	priv->wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
+	priv->wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
+
+	priv->logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
+	if (priv->logo_on) {
+		priv->logo_width = fdtdec_get_int(blob, node,
+						"samsung,logo-width", 0);
+		priv->logo_height = fdtdec_get_int(blob, node,
+						"samsung,logo-height", 0);
+		priv->logo_addr = fdtdec_get_int(blob, node,
+						"samsung,logo-addr", 0);
+	}
+
+	priv->rgb_mode = fdtdec_get_int(blob, node,
+						"samsung,rgb-mode", 0);
+	priv->pclk_name = fdtdec_get_int(blob, node,
+						"samsung,pclk-name", 0);
+	priv->sclk_div = fdtdec_get_int(blob, node,
+						"samsung,sclk-div", 0);
+	priv->dual_lcd_enabled = fdtdec_get_int(blob, node,
+						"samsung,dual-lcd-enabled", 0);
+
+	return 0;
+}
+
+static int exynos_fb_probe(struct udevice *dev)
+{
+	struct video_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct exynos_fb_priv *priv = dev_get_priv(dev);
+	struct udevice *panel, *bridge;
+	struct udevice *dp;
+	int ret;
+
+	debug("%s: start\n", __func__);
+	set_system_display_ctrl();
+	set_lcd_clk();
+
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
+	exynos_init_dsim_platform_data(&panel_info);
+#endif
+	exynos_fimd_lcd_init(dev);
+
+	ret = uclass_first_device(UCLASS_PANEL, &panel);
+	if (ret) {
+		printf("LCD panel failed to probe\n");
+		return ret;
+	}
+	if (!panel) {
+		printf("LCD panel not found\n");
+		return -ENODEV;
+	}
+
+	ret = uclass_first_device(UCLASS_DISPLAY, &dp);
+	if (ret) {
+		debug("%s: Display device error %d\n", __func__, ret);
+		return ret;
+	}
+	if (!dev) {
+		debug("%s: Display device missing\n", __func__);
+		return -ENODEV;
+	}
+	ret = display_enable(dp, 18, NULL);
+	if (ret) {
+		debug("%s: Display enable error %d\n", __func__, ret);
+		return ret;
+	}
+
+	/* backlight / pwm */
+	ret = panel_enable_backlight(panel);
+	if (ret) {
+		debug("%s: backlight error: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
+	if (!ret)
+		ret = video_bridge_set_backlight(bridge, 80);
+	if (ret) {
+		debug("%s: No video bridge, or no backlight on bridge\n",
+		      __func__);
+		exynos_pinmux_config(PERIPH_ID_PWM0, 0);
+	}
+
+	uc_priv->xsize = priv->vl_col;
+	uc_priv->ysize = priv->vl_row;
+	uc_priv->bpix = priv->vl_bpix;
+
+	/* Enable flushing after LCD writes if requested */
+	video_set_flush_dcache(dev, true);
+
+	return 0;
+}
+
+static int exynos_fb_bind(struct udevice *dev)
+{
+	struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
+
+	/* This is the maximum panel size we expect to see */
+	plat->size = 1920 * 1080 * 2;
+
+	return 0;
+}
+
+static const struct video_ops exynos_fb_ops = {
+};
+
+static const struct udevice_id exynos_fb_ids[] = {
+	{ .compatible = "samsung,exynos-fimd" },
+	{ }
+};
+
+U_BOOT_DRIVER(exynos_fb) = {
+	.name	= "exynos_fb",
+	.id	= UCLASS_VIDEO,
+	.of_match = exynos_fb_ids,
+	.ops	= &exynos_fb_ops,
+	.bind	= exynos_fb_bind,
+	.probe	= exynos_fb_probe,
+	.ofdata_to_platdata	= exynos_fb_ofdata_to_platdata,
+	.priv_auto_alloc_size	= sizeof(struct exynos_fb_priv),
+};
diff --git a/drivers/video/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c
index b597accf3d..a5d9b59218 100644
--- a/drivers/video/exynos_mipi_dsi.c
+++ b/drivers/video/exynos/exynos_mipi_dsi.c
@@ -27,13 +27,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct exynos_platform_mipi_dsim *dsim_pd;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-static struct mipi_dsim_config dsim_config_dt;
-static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
-static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
-#endif
-
 struct mipi_dsim_ddi {
 	int				bus_id;
 	struct list_head		list;
@@ -178,7 +171,7 @@ static struct mipi_dsim_master_ops master_ops = {
 	.clear_dsim_frame_done		= exynos_mipi_dsi_clear_frame_done,
 };
 
-int exynos_mipi_dsi_init(void)
+int exynos_mipi_dsi_init(struct exynos_platform_mipi_dsim *dsim_pd)
 {
 	struct mipi_dsim_device *dsim;
 	struct mipi_dsim_config *dsim_config;
@@ -239,18 +232,8 @@ int exynos_mipi_dsi_init(void)
 	return 0;
 }
 
-void exynos_set_dsim_platform_data(struct exynos_platform_mipi_dsim *pd)
-{
-	if (pd == NULL) {
-		debug("pd is NULL\n");
-		return;
-	}
-
-	dsim_pd = pd;
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int exynos_dsim_config_parse_dt(const void *blob)
+int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt,
+				struct mipi_dsim_lcd_device *lcd_dt)
 {
 	int node;
 
@@ -260,59 +243,59 @@ int exynos_dsim_config_parse_dt(const void *blob)
 		return -ENODEV;
 	}
 
-	dsim_config_dt.e_interface = fdtdec_get_int(blob, node,
+	dt->e_interface = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-interface", 0);
 
-	dsim_config_dt.e_virtual_ch = fdtdec_get_int(blob, node,
+	dt->e_virtual_ch = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-virtual-ch", 0);
 
-	dsim_config_dt.e_pixel_format = fdtdec_get_int(blob, node,
+	dt->e_pixel_format = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-pixel-format", 0);
 
-	dsim_config_dt.e_burst_mode = fdtdec_get_int(blob, node,
+	dt->e_burst_mode = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-burst-mode", 0);
 
-	dsim_config_dt.e_no_data_lane = fdtdec_get_int(blob, node,
+	dt->e_no_data_lane = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-no-data-lane", 0);
 
-	dsim_config_dt.e_byte_clk = fdtdec_get_int(blob, node,
+	dt->e_byte_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-e-byte-clk", 0);
 
-	dsim_config_dt.hfp = fdtdec_get_int(blob, node,
+	dt->hfp = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-hfp", 0);
 
-	dsim_config_dt.p = fdtdec_get_int(blob, node,
+	dt->p = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-p", 0);
-	dsim_config_dt.m = fdtdec_get_int(blob, node,
+	dt->m = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-m", 0);
-	dsim_config_dt.s = fdtdec_get_int(blob, node,
+	dt->s = fdtdec_get_int(blob, node,
 					  "samsung,dsim-config-s", 0);
 
-	dsim_config_dt.pll_stable_time = fdtdec_get_int(blob, node,
+	dt->pll_stable_time = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-pll-stable-time", 0);
 
-	dsim_config_dt.esc_clk = fdtdec_get_int(blob, node,
+	dt->esc_clk = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-esc-clk", 0);
 
-	dsim_config_dt.stop_holding_cnt = fdtdec_get_int(blob, node,
+	dt->stop_holding_cnt = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-stop-holding-cnt", 0);
 
-	dsim_config_dt.bta_timeout = fdtdec_get_int(blob, node,
+	dt->bta_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-bta-timeout", 0);
 
-	dsim_config_dt.rx_timeout = fdtdec_get_int(blob, node,
+	dt->rx_timeout = fdtdec_get_int(blob, node,
 				"samsung,dsim-config-rx-timeout", 0);
 
-	mipi_lcd_device_dt.name = fdtdec_get_config_string(blob,
+	lcd_dt->name = fdtdec_get_config_string(blob,
 				"samsung,dsim-device-name");
 
-	mipi_lcd_device_dt.id = fdtdec_get_int(blob, node,
+	lcd_dt->id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-id", 0);
 
-	mipi_lcd_device_dt.bus_id = fdtdec_get_int(blob, node,
+	lcd_dt->bus_id = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-bus_id", 0);
 
-	mipi_lcd_device_dt.reverse_panel = fdtdec_get_int(blob, node,
+	lcd_dt->reverse_panel = fdtdec_get_int(blob, node,
 				"samsung,dsim-device-reverse-panel", 0);
 
 	return 0;
@@ -320,7 +303,12 @@ int exynos_dsim_config_parse_dt(const void *blob)
 
 void exynos_init_dsim_platform_data(vidinfo_t *vid)
 {
-	if (exynos_dsim_config_parse_dt(gd->fdt_blob))
+	static struct mipi_dsim_config dsim_config_dt;
+	static struct exynos_platform_mipi_dsim dsim_platform_data_dt;
+	static struct mipi_dsim_lcd_device mipi_lcd_device_dt;
+
+	if (exynos_dsim_config_parse_dt(gd->fdt_blob, &dsim_config_dt,
+					&mipi_lcd_device_dt))
 		debug("Can't get proper dsim config.\n");
 
 	strcpy(dsim_platform_data_dt.lcd_panel_name, mipi_lcd_device_dt.name);
@@ -332,6 +320,5 @@ void exynos_init_dsim_platform_data(vidinfo_t *vid)
 	mipi_lcd_device_dt.platform_data = (void *)&dsim_platform_data_dt;
 	exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device_dt);
 
-	dsim_pd = &dsim_platform_data_dt;
+	vid->dsim_platform_data_dt = &dsim_platform_data_dt;
 }
-#endif
diff --git a/drivers/video/exynos_mipi_dsi_common.c b/drivers/video/exynos/exynos_mipi_dsi_common.c
index 925d51500a..85c5e0de93 100644
--- a/drivers/video/exynos_mipi_dsi_common.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.c
@@ -465,7 +465,7 @@ int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
 }
 
 static void convert_to_fb_videomode(struct fb_videomode *mode1,
-				vidinfo_t *mode2)
+				    struct vidinfo *mode2)
 {
 	mode1->xres = mode2->vl_width;
 	mode1->yres = mode2->vl_height;
@@ -482,10 +482,10 @@ int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
 {
 	struct exynos_platform_mipi_dsim *dsim_pd;
 	struct fb_videomode lcd_video;
-	vidinfo_t *vid;
+	struct vidinfo *vid;
 
 	dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
-	vid = (vidinfo_t *)dsim_pd->lcd_panel_info;
+	vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
 
 	convert_to_fb_videomode(&lcd_video, vid);
 
diff --git a/drivers/video/exynos_mipi_dsi_common.h b/drivers/video/exynos/exynos_mipi_dsi_common.h
index 98eb78e5f0..98eb78e5f0 100644
--- a/drivers/video/exynos_mipi_dsi_common.h
+++ b/drivers/video/exynos/exynos_mipi_dsi_common.h
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.c b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
index fcfdc8d120..fcfdc8d120 100644
--- a/drivers/video/exynos_mipi_dsi_lowlevel.c
+++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.c
diff --git a/drivers/video/exynos_mipi_dsi_lowlevel.h b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
index 0bede25e4d..0bede25e4d 100644
--- a/drivers/video/exynos_mipi_dsi_lowlevel.h
+++ b/drivers/video/exynos/exynos_mipi_dsi_lowlevel.h
diff --git a/drivers/video/exynos_pwm_bl.c b/drivers/video/exynos/exynos_pwm_bl.c
index a6890daf20..a6890daf20 100644
--- a/drivers/video/exynos_pwm_bl.c
+++ b/drivers/video/exynos/exynos_pwm_bl.c
diff --git a/drivers/video/exynos_dp_lowlevel.h b/drivers/video/exynos_dp_lowlevel.h
deleted file mode 100644
index 8651681520..0000000000
--- a/drivers/video/exynos_dp_lowlevel.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_EDP_LOWLEVEL_H
-#define _EXYNOS_EDP_LOWLEVEL_H
-
-void exynos_dp_enable_video_bist(unsigned int enable);
-void exynos_dp_enable_video_mute(unsigned int enable);
-void exynos_dp_reset(void);
-void exynos_dp_enable_sw_func(unsigned int enable);
-unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable);
-unsigned int exynos_dp_get_pll_lock_status(void);
-int exynos_dp_init_analog_func(void);
-void exynos_dp_init_hpd(void);
-void exynos_dp_init_aux(void);
-void exynos_dp_config_interrupt(void);
-unsigned int exynos_dp_get_plug_in_status(void);
-unsigned int exynos_dp_detect_hpd(void);
-unsigned int exynos_dp_start_aux_transaction(void);
-unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
-				unsigned char data);
-unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
-		unsigned char *data);
-unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-unsigned int exynos_dp_read_bytes_from_dpcd( unsigned int reg_addr,
-		unsigned int count,
-		unsigned char data[]);
-int exynos_dp_select_i2c_device( unsigned int device_addr,
-		unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
-		unsigned int reg_addr, unsigned int count,
-		unsigned char edid[]);
-void exynos_dp_reset_macro(void);
-void exynos_dp_set_link_bandwidth(unsigned char bwtype);
-unsigned char exynos_dp_get_link_bandwidth(void);
-void exynos_dp_set_lane_count(unsigned char count);
-unsigned int exynos_dp_get_lane_count(void);
-unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt);
-void exynos_dp_set_lane_pre_emphasis(unsigned int level,
-		unsigned char lanecnt);
-void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
-		unsigned char lanecnt);
-void exynos_dp_set_training_pattern(unsigned int pattern);
-void exynos_dp_enable_enhanced_mode(unsigned char enable);
-void exynos_dp_enable_scrambling(unsigned int enable);
-int exynos_dp_init_video(void);
-void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info);
-void exynos_dp_set_video_color_format(struct edp_video_info *video_info);
-int exynos_dp_config_video_bist(struct edp_device_info *edp_info);
-unsigned int exynos_dp_is_slave_video_stream_clock_on(void);
-void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
-		unsigned int n_value);
-void exynos_dp_set_video_timing_mode(unsigned int type);
-void exynos_dp_enable_video_master(unsigned int enable);
-void exynos_dp_start_video(void);
-unsigned int exynos_dp_is_video_stream_on(void);
-void exynos_dp_set_base_addr(void);
-
-#endif /* _EXYNOS_DP_LOWLEVEL_H */
diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c
deleted file mode 100644
index 69edc3a3a4..0000000000
--- a/drivers/video/exynos_fb.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <lcd.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <asm/io.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/mipi_dsim.h>
-#include <asm/arch/dp_info.h>
-#include <asm/arch/system.h>
-#include <asm/gpio.h>
-#include <asm-generic/errno.h>
-
-#include "exynos_fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned int panel_width, panel_height;
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-vidinfo_t panel_info  = {
-	/*
-	 * Insert a value here so that we don't end up in the BSS
-	 * Reference: drivers/video/tegra.c
-	 */
-	.vl_col = -1,
-};
-#endif
-
-ushort *configuration_get_cmap(void)
-{
-#if defined(CONFIG_LCD_LOGO)
-	return bmp_logo_palette;
-#else
-	return NULL;
-#endif
-}
-
-static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
-{
-	unsigned long palette_size;
-	unsigned int fb_size;
-
-	fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3);
-
-	palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
-
-	exynos_fimd_lcd_init_mem((unsigned long)lcdbase,
-			(unsigned long)fb_size, palette_size);
-}
-
-static void exynos_lcd_init(vidinfo_t *vid)
-{
-	exynos_fimd_lcd_init(vid);
-
-	/* Enable flushing after LCD writes if requested */
-	lcd_set_flush_dcache(1);
-}
-
-__weak void exynos_cfg_lcd_gpio(void)
-{
-}
-
-__weak void exynos_backlight_on(unsigned int onoff)
-{
-}
-
-__weak void exynos_reset_lcd(void)
-{
-}
-
-__weak void exynos_lcd_power_on(void)
-{
-}
-
-__weak void exynos_cfg_ldo(void)
-{
-}
-
-__weak void exynos_enable_ldo(unsigned int onoff)
-{
-}
-
-__weak void exynos_backlight_reset(void)
-{
-}
-
-__weak int exynos_lcd_misc_init(vidinfo_t *vid)
-{
-	return 0;
-}
-
-static void lcd_panel_on(vidinfo_t *vid)
-{
-	struct gpio_desc pwm_out_gpio;
-	struct gpio_desc bl_en_gpio;
-	unsigned int node;
-
-	udelay(vid->init_delay);
-
-	exynos_backlight_reset();
-
-	exynos_cfg_lcd_gpio();
-
-	exynos_lcd_power_on();
-
-	udelay(vid->power_on_delay);
-
-	if (vid->dp_enabled)
-		exynos_init_dp();
-
-	exynos_reset_lcd();
-
-	udelay(vid->reset_delay);
-
-	exynos_backlight_on(1);
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	node = fdtdec_next_compatible(gd->fdt_blob, 0,
-						COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("FIMD: Can't get device node for FIMD\n");
-		return;
-	}
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,pwm-out-gpio",
-				   0, &pwm_out_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-	gpio_request_by_name_nodev(gd->fdt_blob, node, "samsung,bl-en-gpio", 0,
-				   &bl_en_gpio,
-				   GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-
-#endif
-	exynos_cfg_ldo();
-
-	exynos_enable_ldo(1);
-
-	if (vid->mipi_enabled)
-		exynos_mipi_dsi_init();
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-int exynos_lcd_early_init(const void *blob)
-{
-	unsigned int node;
-	node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0) {
-		debug("exynos_fb: Can't get device node for fimd\n");
-		return -ENODEV;
-	}
-
-	panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
-	if (panel_info.vl_col == 0) {
-		debug("Can't get XRES\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
-	if (panel_info.vl_row == 0) {
-		debug("Can't get YRES\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_width = fdtdec_get_int(blob, node,
-						"samsung,vl-width", 0);
-
-	panel_info.vl_height = fdtdec_get_int(blob, node,
-						"samsung,vl-height", 0);
-
-	panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
-	if (panel_info.vl_freq == 0) {
-		debug("Can't get refresh rate\n");
-		return -ENXIO;
-	}
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
-		panel_info.vl_clkp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
-		panel_info.vl_oep = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
-		panel_info.vl_hsp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
-		panel_info.vl_vsp = CONFIG_SYS_LOW;
-
-	if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
-		panel_info.vl_dp = CONFIG_SYS_LOW;
-
-	panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
-	if (panel_info.vl_bpix == 0) {
-		debug("Can't get bits per pixel\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
-	if (panel_info.vl_hspw == 0) {
-		debug("Can't get hsync width\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
-	if (panel_info.vl_hfpd == 0) {
-		debug("Can't get right margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
-							"samsung,vl-hbpd", 0);
-	if (panel_info.vl_hbpd == 0) {
-		debug("Can't get left margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
-							"samsung,vl-vspw", 0);
-	if (panel_info.vl_vspw == 0) {
-		debug("Can't get vsync width\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vfpd = fdtdec_get_int(blob, node,
-							"samsung,vl-vfpd", 0);
-	if (panel_info.vl_vfpd == 0) {
-		debug("Can't get lower margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
-	if (panel_info.vl_vbpd == 0) {
-		debug("Can't get upper margin\n");
-		return -ENXIO;
-	}
-
-	panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
-						"samsung,vl-cmd-allow-len", 0);
-
-	panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
-	panel_info.init_delay = fdtdec_get_int(blob, node,
-						"samsung,init-delay", 0);
-	panel_info.power_on_delay = fdtdec_get_int(blob, node,
-						"samsung,power-on-delay", 0);
-	panel_info.reset_delay = fdtdec_get_int(blob, node,
-						"samsung,reset-delay", 0);
-	panel_info.interface_mode = fdtdec_get_int(blob, node,
-						"samsung,interface-mode", 0);
-	panel_info.mipi_enabled = fdtdec_get_int(blob, node,
-						"samsung,mipi-enabled", 0);
-	panel_info.dp_enabled = fdtdec_get_int(blob, node,
-						"samsung,dp-enabled", 0);
-	panel_info.cs_setup = fdtdec_get_int(blob, node,
-						"samsung,cs-setup", 0);
-	panel_info.wr_setup = fdtdec_get_int(blob, node,
-						"samsung,wr-setup", 0);
-	panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
-	panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
-
-	panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
-	if (panel_info.logo_on) {
-		panel_info.logo_width = fdtdec_get_int(blob, node,
-						"samsung,logo-width", 0);
-		panel_info.logo_height = fdtdec_get_int(blob, node,
-						"samsung,logo-height", 0);
-		panel_info.logo_addr = fdtdec_get_int(blob, node,
-						"samsung,logo-addr", 0);
-	}
-
-	panel_info.rgb_mode = fdtdec_get_int(blob, node,
-						"samsung,rgb-mode", 0);
-	panel_info.pclk_name = fdtdec_get_int(blob, node,
-						"samsung,pclk-name", 0);
-	panel_info.sclk_div = fdtdec_get_int(blob, node,
-						"samsung,sclk-div", 0);
-	panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
-						"samsung,dual-lcd-enabled", 0);
-
-	return 0;
-}
-#endif
-
-void lcd_ctrl_init(void *lcdbase)
-{
-	set_system_display_ctrl();
-	set_lcd_clk();
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-#ifdef CONFIG_EXYNOS_MIPI_DSIM
-	exynos_init_dsim_platform_data(&panel_info);
-#endif
-	exynos_lcd_misc_init(&panel_info);
-#else
-	/* initialize parameters which is specific to panel. */
-	init_panel_info(&panel_info);
-#endif
-
-	panel_width = panel_info.vl_width;
-	panel_height = panel_info.vl_height;
-
-	exynos_lcd_init_mem(lcdbase, &panel_info);
-
-	exynos_lcd_init(&panel_info);
-}
-
-void lcd_enable(void)
-{
-	if (panel_info.logo_on) {
-		memset((void *) gd->fb_base, 0, panel_width * panel_height *
-				(NBITS(panel_info.vl_bpix) >> 3));
-	}
-
-	lcd_panel_on(&panel_info);
-}
-
-/* dummy function */
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-	return;
-}
diff --git a/drivers/video/exynos_fb.h b/drivers/video/exynos_fb.h
deleted file mode 100644
index 2c2f94bd03..0000000000
--- a/drivers/video/exynos_fb.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _EXYNOS_FB_H_
-#define _EXYNOS_FB_H_
-
-#include <asm/arch/fb.h>
-
-#define MAX_CLOCK	(86 * 1000000)
-
-enum exynos_cpu_auto_cmd_rate {
-	DISABLE_AUTO_FRM,
-	PER_TWO_FRM,
-	PER_FOUR_FRM,
-	PER_SIX_FRM,
-	PER_EIGHT_FRM,
-	PER_TEN_FRM,
-	PER_TWELVE_FRM,
-	PER_FOURTEEN_FRM,
-	PER_SIXTEEN_FRM,
-	PER_EIGHTEEN_FRM,
-	PER_TWENTY_FRM,
-	PER_TWENTY_TWO_FRM,
-	PER_TWENTY_FOUR_FRM,
-	PER_TWENTY_SIX_FRM,
-	PER_TWENTY_EIGHT_FRM,
-	PER_THIRTY_FRM,
-};
-
-void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
-	unsigned long palette_size);
-void exynos_fimd_lcd_init(vidinfo_t *vid);
-unsigned long exynos_fimd_calc_fbsize(void);
-
-#endif
diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
deleted file mode 100644
index ac001a801e..0000000000
--- a/drivers/video/exynos_fimd.c
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics
- *
- * Author: InKi Dae <inki.dae@samsung.com>
- * Author: Donghwa Lee <dh09.lee@samsung.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <lcd.h>
-#include <div64.h>
-#include <fdtdec.h>
-#include <libfdt.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cpu.h>
-#include "exynos_fb.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static unsigned long *lcd_base_addr;
-static vidinfo_t *pvid;
-static struct exynos_fb *fimd_ctrl;
-
-void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
-		u_long palette_size)
-{
-	lcd_base_addr = (unsigned long *)screen_base;
-}
-
-static void exynos_fimd_set_dualrgb(unsigned int enabled)
-{
-	unsigned int cfg = 0;
-
-	if (enabled) {
-		cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
-			EXYNOS_DUALRGB_VDEN_EN_ENABLE;
-
-		/* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
-		cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
-			EXYNOS_DUALRGB_MAIN_CNT(0);
-	}
-
-	writel(cfg, &fimd_ctrl->dualrgb);
-}
-
-static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
-{
-	unsigned int cfg = 0;
-
-	if (enabled)
-		cfg = EXYNOS_DP_CLK_ENABLE;
-
-	writel(cfg, &fimd_ctrl->dp_mie_clkcon);
-}
-
-static void exynos_fimd_set_par(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	/* set window control */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
-		EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
-		EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
-		EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
-
-	/* DATAPATH is DMA */
-	cfg |= EXYNOS_WINCON_DATAPATH_DMA;
-
-	cfg |= EXYNOS_WINCON_HAWSWP_ENABLE;
-
-	/* dma burst is 16 */
-	cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
-
-	switch (pvid->vl_bpix) {
-	case 4:
-		cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565;
-		break;
-	default:
-		cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
-		break;
-	}
-
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	/* set window position to x=0, y=0*/
-	cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a +
-			EXYNOS_VIDOSD(win_id));
-
-	cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
-		EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1) |
-		EXYNOS_VIDOSD_RIGHT_X_E(1) |
-		EXYNOS_VIDOSD_BOTTOM_Y_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b +
-			EXYNOS_VIDOSD(win_id));
-
-	/* set window size for window0*/
-	cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
-	writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c +
-			EXYNOS_VIDOSD(win_id));
-}
-
-static void exynos_fimd_set_buffer_address(unsigned int win_id)
-{
-	unsigned long start_addr, end_addr;
-
-	start_addr = (unsigned long)lcd_base_addr;
-	end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
-				pvid->vl_row);
-
-	writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-	writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
-			EXYNOS_BUFFER_OFFSET(win_id));
-}
-
-static void exynos_fimd_set_clock(vidinfo_t *pvid)
-{
-	unsigned int cfg = 0, div = 0, remainder, remainder_div;
-	unsigned long pixel_clock;
-	unsigned long long src_clock;
-
-	if (pvid->dual_lcd_enabled) {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col / 2) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	} else if (pvid->interface_mode == FIMD_CPU_INTERFACE) {
-		pixel_clock = pvid->vl_freq *
-				pvid->vl_width * pvid->vl_height *
-				(pvid->cs_setup + pvid->wr_setup +
-				 pvid->wr_act + pvid->wr_hold + 1);
-	} else {
-		pixel_clock = pvid->vl_freq *
-				(pvid->vl_hspw + pvid->vl_hfpd +
-				 pvid->vl_hbpd + pvid->vl_col) *
-				(pvid->vl_vspw + pvid->vl_vfpd +
-				 pvid->vl_vbpd + pvid->vl_row);
-	}
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
-		EXYNOS_VIDCON0_CLKVAL_F(0xFF) | EXYNOS_VIDCON0_VCLKEN_MASK |
-		EXYNOS_VIDCON0_CLKDIR_MASK);
-	cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
-		EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
-
-	src_clock = (unsigned long long) get_lcd_clk();
-
-	/* get quotient and remainder. */
-	remainder = do_div(src_clock, pixel_clock);
-	div = src_clock;
-
-	remainder *= 10;
-	remainder_div = remainder / pixel_clock;
-
-	/* round about one places of decimals. */
-	if (remainder_div >= 5)
-		div++;
-
-	/* in case of dual lcd mode. */
-	if (pvid->dual_lcd_enabled)
-		div--;
-
-	cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_set_trigger(void)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	cfg |= (EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG);
-
-	writel(cfg, &fimd_ctrl->trigcon);
-}
-
-int exynos_is_i80_frame_done(void)
-{
-	unsigned int cfg = 0;
-	int status;
-
-	cfg = readl(&fimd_ctrl->trigcon);
-
-	/* frame done func is valid only when TRIMODE[0] is set to 1. */
-	status = (cfg & EXYNOS_I80STATUS_TRIG_DONE) ==
-			EXYNOS_I80STATUS_TRIG_DONE;
-
-	return status;
-}
-
-static void exynos_fimd_lcd_on(void)
-{
-	unsigned int cfg = 0;
-
-	/* display on */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg |= (EXYNOS_VIDCON0_ENVID_ENABLE | EXYNOS_VIDCON0_ENVID_F_ENABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-static void exynos_fimd_window_on(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	/* enable window */
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg |= EXYNOS_WINCON_ENWIN_ENABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg |= EXYNOS_WINSHMAP_CH_ENABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-void exynos_fimd_lcd_off(void)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
-	writel(cfg, &fimd_ctrl->vidcon0);
-}
-
-void exynos_fimd_window_off(unsigned int win_id)
-{
-	unsigned int cfg = 0;
-
-	cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-	cfg &= EXYNOS_WINCON_ENWIN_DISABLE;
-	writel(cfg, (unsigned int)&fimd_ctrl->wincon0 +
-			EXYNOS_WINCON(win_id));
-
-	cfg = readl(&fimd_ctrl->winshmap);
-	cfg &= ~EXYNOS_WINSHMAP_CH_DISABLE(win_id);
-	writel(cfg, &fimd_ctrl->winshmap);
-}
-
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-/*
-* The reset value for FIMD SYSMMU register MMU_CTRL is 3
-* on Exynos5420 and newer versions.
-* This means FIMD SYSMMU is on by default on Exynos5420
-* and newer versions.
-* Since in u-boot we don't use SYSMMU, we should disable
-* those FIMD SYSMMU.
-* Note that there are 2 SYSMMU for FIMD: m0 and m1.
-* m0 handles windows 0 and 4, and m1 handles windows 1, 2 and 3.
-* We disable both of them here.
-*/
-void exynos_fimd_disable_sysmmu(void)
-{
-	u32 *sysmmufimd;
-	unsigned int node;
-	int node_list[2];
-	int count;
-	int i;
-
-	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "fimd",
-				COMPAT_SAMSUNG_EXYNOS_SYSMMU, node_list, 2);
-	for (i = 0; i < count; i++) {
-		node = node_list[i];
-		if (node <= 0) {
-			debug("Can't get device node for fimd sysmmu\n");
-			return;
-		}
-
-		sysmmufimd = (u32 *)fdtdec_get_addr(gd->fdt_blob, node, "reg");
-		if (!sysmmufimd) {
-			debug("Can't get base address for sysmmu fimdm0");
-			return;
-		}
-
-		writel(0x0, sysmmufimd);
-	}
-}
-#endif
-
-void exynos_fimd_lcd_init(vidinfo_t *vid)
-{
-	unsigned int cfg = 0, rgb_mode;
-	unsigned int offset;
-#if CONFIG_IS_ENABLED(OF_CONTROL)
-	unsigned int node;
-
-	node = fdtdec_next_compatible(gd->fdt_blob,
-					0, COMPAT_SAMSUNG_EXYNOS_FIMD);
-	if (node <= 0)
-		debug("exynos_fb: Can't get device node for fimd\n");
-
-	fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
-								node, "reg");
-	if (fimd_ctrl == NULL)
-		debug("Can't get the FIMD base address\n");
-
-	if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
-		exynos_fimd_disable_sysmmu();
-
-#else
-	fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
-#endif
-
-	offset = exynos_fimd_get_base_offset();
-
-	/* store panel info to global variable */
-	pvid = vid;
-
-	rgb_mode = vid->rgb_mode;
-
-	if (vid->interface_mode == FIMD_RGB_INTERFACE) {
-		cfg |= EXYNOS_VIDCON0_VIDOUT_RGB;
-		writel(cfg, &fimd_ctrl->vidcon0);
-
-		cfg = readl(&fimd_ctrl->vidcon2);
-		cfg &= ~(EXYNOS_VIDCON2_WB_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_MASK |
-			EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK);
-		cfg |= EXYNOS_VIDCON2_WB_DISABLE;
-		writel(cfg, &fimd_ctrl->vidcon2);
-
-		/* set polarity */
-		cfg = 0;
-		if (!pvid->vl_clkp)
-			cfg |= EXYNOS_VIDCON1_IVCLK_RISING_EDGE;
-		if (!pvid->vl_hsp)
-			cfg |= EXYNOS_VIDCON1_IHSYNC_INVERT;
-		if (!pvid->vl_vsp)
-			cfg |= EXYNOS_VIDCON1_IVSYNC_INVERT;
-		if (!pvid->vl_dp)
-			cfg |= EXYNOS_VIDCON1_IVDEN_INVERT;
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidcon1 + offset);
-
-		/* set timing */
-		cfg = EXYNOS_VIDTCON0_VFPD(pvid->vl_vfpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VBPD(pvid->vl_vbpd - 1);
-		cfg |= EXYNOS_VIDTCON0_VSPW(pvid->vl_vspw - 1);
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon0 + offset);
-
-		cfg = EXYNOS_VIDTCON1_HFPD(pvid->vl_hfpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HBPD(pvid->vl_hbpd - 1);
-		cfg |= EXYNOS_VIDTCON1_HSPW(pvid->vl_hspw - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon1 + offset);
-
-		/* set lcd size */
-		cfg = EXYNOS_VIDTCON2_HOZVAL(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL(pvid->vl_row - 1) |
-			EXYNOS_VIDTCON2_HOZVAL_E(pvid->vl_col - 1) |
-			EXYNOS_VIDTCON2_LINEVAL_E(pvid->vl_row - 1);
-
-		writel(cfg, (unsigned int)&fimd_ctrl->vidtcon2 + offset);
-	}
-
-	/* set display mode */
-	cfg = readl(&fimd_ctrl->vidcon0);
-	cfg &= ~EXYNOS_VIDCON0_PNRMODE_MASK;
-	cfg |= (rgb_mode << EXYNOS_VIDCON0_PNRMODE_SHIFT);
-	writel(cfg, &fimd_ctrl->vidcon0);
-
-	/* set par */
-	exynos_fimd_set_par(pvid->win_id);
-
-	/* set memory address */
-	exynos_fimd_set_buffer_address(pvid->win_id);
-
-	/* set buffer size */
-	cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_PAGEWIDTH_E(pvid->vl_col * NBITS(pvid->vl_bpix) / 8) |
-		EXYNOS_VIDADDR_OFFSIZE(0) |
-		EXYNOS_VIDADDR_OFFSIZE_E(0);
-
-	writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 +
-					EXYNOS_BUFFER_SIZE(pvid->win_id));
-
-	/* set clock */
-	exynos_fimd_set_clock(pvid);
-
-	/* set rgb mode to dual lcd. */
-	exynos_fimd_set_dualrgb(pvid->dual_lcd_enabled);
-
-	/* display on */
-	exynos_fimd_lcd_on();
-
-	/* window on */
-	exynos_fimd_window_on(pvid->win_id);
-
-	exynos_fimd_set_dp_clkcon(pvid->dp_enabled);
-}
-
-unsigned long exynos_fimd_calc_fbsize(void)
-{
-	return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8);
-}
diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index a54af172ec..db09d9a41d 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -326,6 +326,7 @@ static int rk_vop_probe(struct udevice *dev)
 		if (!ret)
 			break;
 	}
+	video_set_flush_dcache(dev, 1);
 
 	return ret;
 }
diff --git a/drivers/video/s6e8ax0.c b/drivers/video/s6e8ax0.c
index 84948177e2..1bd49eef80 100644
--- a/drivers/video/s6e8ax0.c
+++ b/drivers/video/s6e8ax0.c
@@ -9,8 +9,8 @@
 #include <common.h>
 #include <asm/arch/mipi_dsim.h>
 
-#include "exynos_mipi_dsi_lowlevel.h"
-#include "exynos_mipi_dsi_common.h"
+#include "exynos/exynos_mipi_dsi_lowlevel.h"
+#include "exynos/exynos_mipi_dsi_common.h"
 
 static void s6e8ax0_panel_cond(struct mipi_dsim_device *dsim_dev)
 {
diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c
index 6219300097..b2fe345ce3 100644
--- a/drivers/video/simple_panel.c
+++ b/drivers/video/simple_panel.c
@@ -88,6 +88,8 @@ static const struct panel_ops simple_panel_ops = {
 static const struct udevice_id simple_panel_ids[] = {
 	{ .compatible = "simple-panel" },
 	{ .compatible = "auo,b133xtn01" },
+	{ .compatible = "auo,b116xw03" },
+	{ .compatible = "auo,b133htn01" },
 	{ }
 };
 
diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c
index ba038b1122..f771e94f91 100644
--- a/fs/jffs2/jffs2_1pass.c
+++ b/fs/jffs2/jffs2_1pass.c
@@ -195,7 +195,7 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf)
 			}
 
 			retlen = NAND_CACHE_SIZE;
-			if (nand_read(&nand_info[id->num], nand_cache_off,
+			if (nand_read(nand_info[id->num], nand_cache_off,
 						&retlen, nand_cache) != 0 ||
 					retlen != NAND_CACHE_SIZE) {
 				printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
diff --git a/fs/jffs2/jffs2_nand_1pass.c b/fs/jffs2/jffs2_nand_1pass.c
index 740f787dd2..d94c48f534 100644
--- a/fs/jffs2/jffs2_nand_1pass.c
+++ b/fs/jffs2/jffs2_nand_1pass.c
@@ -23,7 +23,7 @@
 # define DEBUGF(fmt,args...)
 #endif
 
-static nand_info_t *nand;
+static struct mtd_info *mtd;
 
 /* Compression names */
 static char *compr_names[] = {
@@ -304,7 +304,7 @@ jffs2_1pass_read_inode(struct b_lists *pL, u32 ino, char *dest,
 			len = sizeof(struct jffs2_raw_inode);
 			if (dest)
 				len += jNode->csize;
-			nand_read(nand, jNode->offset, &len, inode);
+			nand_read(mtd, jNode->offset, &len, inode);
 			/* ignore data behind latest known EOF */
 			if (inode->offset > totalSize)
 				continue;
@@ -450,7 +450,7 @@ dump_inode(struct b_lists *pL, struct b_dirent *d, struct b_inode *i)
 
 	if(!d || !i) return -1;
 	len = d->nsize;
-	nand_read(nand, d->offset + sizeof(struct jffs2_raw_dirent),
+	nand_read(mtd, d->offset + sizeof(struct jffs2_raw_dirent),
 		  &len, &fname);
 	fname[d->nsize] = '\0';
 
@@ -592,7 +592,9 @@ jffs2_1pass_resolve_inode(struct b_lists * pL, u32 ino)
 	for (jNode = (struct b_inode *)pL->frag.listHead; jNode; jNode = jNode->next) {
 		if (jNode->ino == jDirFoundIno) {
 			size_t len = jNode->csize;
-			nand_read(nand, jNode->offset + sizeof(struct jffs2_raw_inode), &len, &tmp);
+			nand_read(mtd,
+				  jNode->offset + sizeof(struct jffs2_raw_inode),
+				  &len, &tmp);
 			tmp[jNode->csize] = '\0';
 			break;
 		}
@@ -760,14 +762,14 @@ dump_dirents(struct b_lists *pL)
 #endif
 
 static int
-jffs2_fill_scan_buf(nand_info_t *nand, unsigned char *buf,
+jffs2_fill_scan_buf(struct mtd_info *mtd, unsigned char *buf,
 		    unsigned ofs, unsigned len)
 {
 	int ret;
 	unsigned olen;
 
 	olen = len;
-	ret = nand_read(nand, ofs, &olen, buf);
+	ret = nand_read(mtd, ofs, &olen, buf);
 	if (ret) {
 		printf("nand_read(0x%x bytes from 0x%x) returned %d\n", len, ofs, ret);
 		return ret;
@@ -794,7 +796,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	u32 counterN = 0;
 
 	struct mtdids *id = part->dev->id;
-	nand = nand_info + id->num;
+	mtd = nand_info[id->num];
 
 	/* if we are building a list we need to refresh the cache. */
 	jffs_init_1pass_list(part);
@@ -802,7 +804,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 	pL->partOffset = part->offset;
 	puts ("Scanning JFFS2 FS:   ");
 
-	sectorsize = nand->erasesize;
+	sectorsize = mtd->erasesize;
 	nr_blocks = part->size / sectorsize;
 	buf = malloc(sectorsize);
 	if (!buf)
@@ -813,10 +815,10 @@ jffs2_1pass_build_lists(struct part_info * part)
 
 		offset = part->offset + i * sectorsize;
 
-		if (nand_block_isbad(nand, offset))
+		if (nand_block_isbad(mtd, offset))
 			continue;
 
-		if (jffs2_fill_scan_buf(nand, buf, offset, EMPTY_SCAN_SIZE))
+		if (jffs2_fill_scan_buf(mtd, buf, offset, EMPTY_SCAN_SIZE))
 			return 0;
 
 		ofs = 0;
@@ -826,7 +828,7 @@ jffs2_1pass_build_lists(struct part_info * part)
 		if (ofs == EMPTY_SCAN_SIZE)
 			continue;
 
-		if (jffs2_fill_scan_buf(nand, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
+		if (jffs2_fill_scan_buf(mtd, buf + EMPTY_SCAN_SIZE, offset + EMPTY_SCAN_SIZE, sectorsize - EMPTY_SCAN_SIZE))
 			return 0;
 		offset += ofs;
 
diff --git a/fs/yaffs2/yaffs_uboot_glue.c b/fs/yaffs2/yaffs_uboot_glue.c
index 50000a135b..25aa6d1564 100644
--- a/fs/yaffs2/yaffs_uboot_glue.c
+++ b/fs/yaffs2/yaffs_uboot_glue.c
@@ -141,8 +141,6 @@ static const char *yaffs_error_str(void)
 	}
 }
 
-extern nand_info_t nand_info[];
-
 void cmd_yaffs_tracemask(unsigned set, unsigned mask)
 {
 	if (set)
@@ -171,7 +169,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev,
 	dev = calloc(1, sizeof(*dev));
 	mp = strdup(_mp);
 
-	mtd = &nand_info[flash_dev];
+	mtd = nand_info[flash_dev];
 
 	if (!dev || !mp) {
 		/* Alloc error */
@@ -192,7 +190,7 @@ void cmd_yaffs_devconfig(char *_mp, int flash_dev,
 		goto err;
 	}
 
-	chip =  mtd->priv;
+	chip =  mtd_to_nand(mtd);
 
 	/* Check for any conflicts */
 	yaffs_dev_rewind();
@@ -260,9 +258,7 @@ void cmd_yaffs_dev_ls(void)
 		dev = yaffs_next_dev();
 		if (!dev)
 			return;
-		flash_dev =
-			((unsigned) dev->driver_context - (unsigned) nand_info)/
-				sizeof(nand_info[0]);
+		flash_dev = nand_mtd_to_devnum(dev->driver_context);
 		printf("%-10s %5d 0x%05x 0x%05x %s",
 			dev->param.name, flash_dev,
 			dev->param.start_block, dev->param.end_block,
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index f2810a1bd7..0abcbe4c0b 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -141,5 +141,6 @@ typedef struct global_data {
 #define GD_FLG_SPL_INIT		0x00400	/* spl_init() has been called	   */
 #define GD_FLG_SKIP_RELOC	0x00800	/* Don't relocate */
 #define GD_FLG_RECORD		0x01000	/* Record console */
+#define GD_FLG_ENV_DEFAULT	0x02000 /* Default variable flag */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 2500c10450..4aa0004fab 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -251,6 +251,8 @@ struct dm_gpio_ops {
 				int value);
 	int (*get_value)(struct udevice *dev, unsigned offset);
 	int (*set_value)(struct udevice *dev, unsigned offset, int value);
+	int (*get_open_drain)(struct udevice *dev, unsigned offset);
+	int (*set_open_drain)(struct udevice *dev, unsigned offset, int value);
 	/**
 	 * get_function() Get the GPIO function
 	 *
@@ -550,6 +552,38 @@ int dm_gpio_get_value(const struct gpio_desc *desc);
 int dm_gpio_set_value(const struct gpio_desc *desc, int value);
 
 /**
+ * dm_gpio_get_open_drain() - Check if open-drain-mode of a GPIO is active
+ *
+ * This checks if open-drain-mode for a GPIO is enabled or not. This method is
+ * optional.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return Value of open drain mode for GPIO (0 for inactive, 1 for active) or
+ *	   -ve on error
+ */
+int dm_gpio_get_open_drain(struct gpio_desc *desc);
+
+/**
+ * dm_gpio_set_open_drain() - Switch open-drain-mode of a GPIO on or off
+ *
+ * This enables or disables open-drain mode for a GPIO. This method is
+ * optional; if the driver does not support it, nothing happens when the method
+ * is called.
+ *
+ * In open-drain mode, instead of actively driving the output (Push-pull
+ * output), the GPIO's pin is connected to the collector (for a NPN transistor)
+ * or the drain (for a MOSFET) of a transistor, respectively. The pin then
+ * either forms an open circuit or a connection to ground, depending on the
+ * state of the transistor.
+ *
+ * @desc:	GPIO description containing device, offset and flags,
+ *		previously returned by gpio_request_by_name()
+ * @return 0 if OK, -ve on error
+ */
+int dm_gpio_set_open_drain(struct gpio_desc *desc, int value);
+
+/**
  * dm_gpio_set_dir() - Set the direction for a GPIO
  *
  * This sets up the direction according tot the provided flags. It will do
diff --git a/include/axp809.h b/include/axp809.h
new file mode 100644
index 0000000000..d27fb978d2
--- /dev/null
+++ b/include/axp809.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * X-Powers AXP809 Power Management IC driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define AXP809_CHIP_ID		0x03
+
+#define AXP809_OUTPUT_CTRL1	0x10
+#define AXP809_OUTPUT_CTRL1_DC5LDO_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL1_DCDC1_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL1_DCDC2_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL1_DCDC3_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL1_DCDC4_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL1_DCDC5_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL1_ALDO1_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL1_ALDO2_EN	(1 << 7)
+#define AXP809_OUTPUT_CTRL2	0x12
+#define AXP809_OUTPUT_CTRL2_ELDO1_EN	(1 << 0)
+#define AXP809_OUTPUT_CTRL2_ELDO2_EN	(1 << 1)
+#define AXP809_OUTPUT_CTRL2_ELDO3_EN	(1 << 2)
+#define AXP809_OUTPUT_CTRL2_DLDO1_EN	(1 << 3)
+#define AXP809_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
+#define AXP809_OUTPUT_CTRL2_ALDO3_EN	(1 << 5)
+#define AXP809_OUTPUT_CTRL2_SWOUT_EN	(1 << 6)
+#define AXP809_OUTPUT_CTRL2_DC1SW_EN	(1 << 7)
+
+#define AXP809_DLDO1_CTRL	0x15
+#define AXP809_DLDO2_CTRL	0x16
+#define AXP809_ELDO1_CTRL	0x19
+#define AXP809_ELDO2_CTRL	0x1a
+#define AXP809_ELDO3_CTRL	0x1b
+#define AXP809_DC5LDO_CTRL	0x1c
+#define AXP809_DCDC1_CTRL	0x21
+#define AXP809_DCDC2_CTRL	0x22
+#define AXP809_DCDC3_CTRL	0x23
+#define AXP809_DCDC4_CTRL	0x24
+#define AXP809_DCDC5_CTRL	0x25
+#define AXP809_ALDO1_CTRL	0x28
+#define AXP809_ALDO2_CTRL	0x29
+#define AXP809_ALDO3_CTRL	0x2a
+#define AXP809_SHUTDOWN		0x32
+#define AXP809_SHUTDOWN_POWEROFF	(1 << 7)
+
+/* For axp_gpio.c */
+#define AXP_POWER_STATUS		0x00
+#define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
+#define AXP_VBUS_IPSOUT			0x30
+#define AXP_VBUS_IPSOUT_DRIVEBUS		(1 << 2)
+#define AXP_MISC_CTRL			0x8f
+#define AXP_MISC_CTRL_N_VBUSEN_FUNC		(1 << 4)
+#define AXP_GPIO0_CTRL			0x90
+#define AXP_GPIO1_CTRL			0x92
+#define AXP_GPIO_CTRL_OUTPUT_LOW	0x00 /* Drive pin low */
+#define AXP_GPIO_CTRL_OUTPUT_HIGH	0x01 /* Drive pin high */
+#define AXP_GPIO_CTRL_INPUT		0x02 /* Input */
+#define AXP_GPIO_STATE			0x94
+#define AXP_GPIO_STATE_OFFSET		0
diff --git a/include/axp818.h b/include/axp818.h
index 5630eed04d..959774c76f 100644
--- a/include/axp818.h
+++ b/include/axp818.h
@@ -24,6 +24,7 @@
 #define AXP818_OUTPUT_CTRL2_DLDO2_EN	(1 << 4)
 #define AXP818_OUTPUT_CTRL2_DLDO3_EN	(1 << 5)
 #define AXP818_OUTPUT_CTRL2_DLDO4_EN	(1 << 6)
+#define AXP818_OUTPUT_CTRL2_SW_EN	(1 << 7)
 #define AXP818_OUTPUT_CTRL3	0x13
 #define AXP818_OUTPUT_CTRL3_FLDO1_EN	(1 << 2)
 #define AXP818_OUTPUT_CTRL3_FLDO2_EN	(1 << 3)
@@ -54,6 +55,9 @@
 #define AXP818_ALDO2_CTRL	0x29
 #define AXP818_ALDO3_CTRL	0x2a
 
+#define AXP818_SHUTDOWN		0x32
+#define AXP818_SHUTDOWN_POWEROFF	(1 << 7)
+
 /* For axp_gpio.c */
 #define AXP_POWER_STATUS		0x00
 #define AXP_POWER_STATUS_VBUS_PRESENT		(1 << 5)
diff --git a/include/axp_pmic.h b/include/axp_pmic.h
index b203cc88dd..d789ad8086 100644
--- a/include/axp_pmic.h
+++ b/include/axp_pmic.h
@@ -16,6 +16,9 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
+#ifdef CONFIG_AXP809_POWER
+#include <axp809.h>
+#endif
 #ifdef CONFIG_AXP818_POWER
 #include <axp818.h>
 #endif
@@ -32,6 +35,7 @@ int axp_set_aldo4(unsigned int mvolt);
 int axp_set_dldo(int dldo_num, unsigned int mvolt);
 int axp_set_eldo(int eldo_num, unsigned int mvolt);
 int axp_set_fldo(int fldo_num, unsigned int mvolt);
+int axp_set_sw(bool on);
 int axp_init(void);
 int axp_get_sid(unsigned int *sid);
 
diff --git a/include/bootstage.h b/include/bootstage.h
index 97653602d3..a589be6316 100644
--- a/include/bootstage.h
+++ b/include/bootstage.h
@@ -198,6 +198,7 @@ enum bootstage_id {
 	BOOTSTAGE_ID_ACCUM_SCSI,
 	BOOTSTAGE_ID_ACCUM_SPI,
 	BOOTSTAGE_ID_ACCUM_DECOMP,
+	BOOTSTAGE_ID_FPGA_INIT,
 
 	/* a few spare for the user, from here */
 	BOOTSTAGE_ID_USER,
@@ -212,7 +213,9 @@ enum bootstage_id {
  */
 ulong timer_get_boot_us(void);
 
-#if !defined(CONFIG_SPL_BUILD) && !defined(USE_HOSTCC)
+#if defined(USE_HOSTCC)
+#define show_boot_progress(val) do {} while (0)
+#else
 /*
  * Board code can implement show_boot_progress() if needed.
  *
@@ -220,8 +223,6 @@ ulong timer_get_boot_us(void);
  *		has occurred.
  */
 void show_boot_progress(int val);
-#else
-#define show_boot_progress(val) do {} while (0)
 #endif
 
 #if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD) && \
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index 5a8d7f2708..4db6faa7bb 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -230,13 +230,58 @@
 #endif
 
 #if defined(CONFIG_CMD_DHCP)
+#if defined(CONFIG_EFI_LOADER)
+#if defined(CONFIG_ARM64)
+#define BOOTENV_EFI_PXE_ARCH "0xb"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00011:UNDI:003000"
+#elif defined(CONFIG_ARM)
+#define BOOTENV_EFI_PXE_ARCH "0xa"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00010:UNDI:003000"
+#elif defined(CONFIG_X86)
+/* Always assume we're running 64bit */
+#define BOOTENV_EFI_PXE_ARCH "0x7"
+#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00007:UNDI:003000"
+#else
+#error Please specify an EFI client identifier
+#endif
+
+/*
+ * Ask the dhcp server for an EFI binary. If we get one, check for a
+ * device tree in the same folder. Then boot everything. If the file was
+ * not an EFI binary, we just return from the bootefi command and continue.
+ */
+#define BOOTENV_EFI_RUN_DHCP \
+	"setenv efi_fdtfile ${fdtfile}; "                                 \
+	BOOTENV_EFI_SET_FDTFILE_FALLBACK                                  \
+	"setenv efi_old_vci ${bootp_vci};"                                \
+	"setenv efi_old_arch ${bootp_arch};"                              \
+	"setenv bootp_vci " BOOTENV_EFI_PXE_VCI ";"                       \
+	"setenv bootp_arch " BOOTENV_EFI_PXE_ARCH ";"                     \
+	"if dhcp ${kernel_addr_r}; then "                                 \
+		"tftpboot ${fdt_addr_r} dtb/${efi_fdtfile};"              \
+		"if fdt addr ${fdt_addr_r}; then "                        \
+			"bootefi ${kernel_addr_r} ${fdt_addr_r}; "        \
+		"else "                                                   \
+			"bootefi ${kernel_addr_r} ${fdtcontroladdr};"     \
+		"fi;"                                                     \
+	"fi;"                                                             \
+	"setenv bootp_vci ${efi_old_vci};"                                \
+	"setenv bootp_arch ${efi_old_arch};"                              \
+	"setenv efi_fdtfile;"                                             \
+	"setenv efi_old_arch;"                                            \
+	"setenv efi_old_vci;"
+#else
+#define BOOTENV_EFI_RUN_DHCP
+#endif
 #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
 	"bootcmd_dhcp=" \
 		BOOTENV_RUN_NET_USB_START \
 		BOOTENV_RUN_NET_PCI_ENUM \
 		"if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \
 			"source ${scriptaddr}; " \
-		"fi\0"
+		"fi;" \
+		BOOTENV_EFI_RUN_DHCP \
+		"\0"
 #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \
 	"dhcp "
 #else
diff --git a/include/config_distro_defaults.h b/include/config_distro_defaults.h
index 766a212b97..9244680452 100644
--- a/include/config_distro_defaults.h
+++ b/include/config_distro_defaults.h
@@ -20,27 +20,6 @@
 #define CONFIG_BOOTP_PXE
 #define CONFIG_BOOTP_SUBNETMASK
 
-#if defined(__arm__) || defined(__aarch64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
-#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.armv7"
-#endif
-#elif defined(__aarch64__)
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.armv8"
-#endif
-#else
-#if !defined(CONFIG_BOOTP_VCI_STRING)
-#define CONFIG_BOOTP_VCI_STRING         "U-Boot.arm"
-#endif
-#endif
-#elif defined(__i386__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x0
-#elif defined(__x86_64__)
-#define CONFIG_BOOTP_PXE_CLIENTARCH     0x9
-#endif
-
 #ifdef CONFIG_ARM64
 #define CONFIG_CMD_BOOTI
 #endif
@@ -48,7 +27,6 @@
 
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_BOOTDELAY     2
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_MENU
 #define CONFIG_DOS_PARTITION
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 5249751830..2c3c4ac093 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -802,7 +802,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h
index b092933757..0a9d8a64af 100644
--- a/include/configs/BSC9131RDB.h
+++ b/include/configs/BSC9131RDB.h
@@ -394,7 +394,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10 /* -1 disable auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
 	"netdev=eth0\0"						\
diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h
index aaddfca2cd..756beec61b 100644
--- a/include/configs/BSC9132QDS.h
+++ b/include/configs/BSC9132QDS.h
@@ -632,7 +632,6 @@ combinations. this should be removed later
 #define CONFIG_UBOOTPATH	"u-boot.bin"
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10 /* -1 disable auto-boot */
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_DEF_HWCONFIG	"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h
index 1e5b501ab1..69a9798540 100644
--- a/include/configs/C29XPCIE.h
+++ b/include/configs/C29XPCIE.h
@@ -517,7 +517,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE		115200
 
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index b60da5e166..c5c3a845e4 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -27,7 +27,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef	CONFIG_BOOTCOMMAND
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index b66b3ff7ef..db953b9b4a 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -31,7 +31,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef	CONFIG_BOOTCOMMAND
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 2b2e4e7a5a..b426c18b3b 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -59,7 +59,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 85b1c1544e..1e052b1b4b 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -82,7 +82,6 @@
 	""
 #endif
 
-#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
 /* LCD */
 #ifdef CONFIG_CMD_BMP
 #define CONFIG_LCD
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index bacd8e0f32..006222881a 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -76,7 +76,6 @@
 #define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_BOOTFILE		"u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_IPADDR	192.162.1.2
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 7c06fcea39..6c90700ccf 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -17,7 +17,6 @@
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
-#define CONFIG_BOOTDELAY	5
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index d14f979cdd..faad9703b7 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -18,7 +18,6 @@
 
 #undef CONFIG_WATCHDOG		/* disable watchdog */
 
-#define CONFIG_BOOTDELAY	5
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 0753dc3afa..a8589049fd 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -57,7 +57,6 @@
  * Command line configuration.
  */
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_MII		1
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 1709cccf89..1bdacbcdf8 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -104,7 +104,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x800000
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"bootm ffe40000"
 #define CONFIG_SYS_MEMTEST_START	0x400
 #define CONFIG_SYS_MEMTEST_END		0x380000
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 8131ea0ee1..62f25e9023 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -70,7 +70,6 @@
 #	endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
-#define CONFIG_BOOTDELAY	5
 #ifdef CONFIG_MCFFEC
 #	define CONFIG_IPADDR	192.162.1.2
 #	define CONFIG_NETMASK	255.255.255.0
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 81e28f0924..03c18da52e 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -79,7 +79,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY		1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 661063ce5d..fabbaf084d 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -73,7 +73,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index f0cf715ee2..8fb16bc294 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -73,7 +73,6 @@
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
 #define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index e10c3e1929..63b0a1e0ed 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -75,7 +75,6 @@
 #define CONFIG_SYS_FEC0_PHYADDR	0
 #define CONFIG_SYS_FEC1_PHYADDR	1
 
-#define CONFIG_BOOTDELAY		2	/* autoboot after 5 seconds */
 
 #ifdef	CONFIG_SYS_NAND_BOOT
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock2 rw rootfstype=jffs2 " \
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 00bdbd1824..599ffc7990 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -56,7 +56,6 @@
 #	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
 #	define MCFFEC_TOUT_LOOP 50000
 
-#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
 #	define CONFIG_ETHPRIME		"FEC0"
 #	define CONFIG_IPADDR		192.162.1.2
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index f32dd3660a..8301c4670f 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -61,7 +61,6 @@
 #	define MCFFEC_TOUT_LOOP 50000
 #	define CONFIG_HAS_ETH1
 
-#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
 #	define CONFIG_ETHPRIME		"FEC0"
 #	define CONFIG_IPADDR		192.162.1.2
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 5fa9683e2c..ccebc30e16 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -116,7 +116,6 @@
 #define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #ifdef CONFIG_MCFFEC
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 9a23e22bfa..7e9f978f6b 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -111,7 +111,6 @@
 #define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
 #endif
 
-#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
 #define CONFIG_UDP_CHECKSUM
 
 #define CONFIG_HOSTNAME		M548xEVB
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 75a26edb25..79027e214c 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -97,7 +97,6 @@
  * Environment definitions
  **************************************************************/
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
-#define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
index e3e3b4414d..578325cd05 100644
--- a/include/configs/MPC8308RDB.h
+++ b/include/configs/MPC8308RDB.h
@@ -514,7 +514,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index fda894e119..5613a4a0cd 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -649,7 +649,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 41b40cb2d1..7ce5f59937 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -602,7 +602,6 @@
 
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 5c40e5b3ea..13f954d00e 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -492,7 +492,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 4a1cebb5d6..fd482606ad 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -569,7 +569,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 3518b3fd3b..288b126d02 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -734,7 +734,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 115200
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index 8161903f80..2721255254 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -731,7 +731,6 @@ boards, we say we have two, but don't display a message if we find only one. */
 #define CONFIG_FDTFILE		"mpc8349emitxgp.dtb"
 #endif
 
-#define CONFIG_BOOTDELAY	6
 
 #define CONFIG_BOOTARGS \
 	"root=/dev/nfs rw" \
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 28ed9c03b9..921d5f399d 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -659,7 +659,6 @@ extern int board_pci_host_broken(void);
 
 #define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
 #undef CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index fa131e23fb..bb06e89b4e 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -679,7 +679,6 @@
 
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 03f17f9c35..7c19ff84bc 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -706,7 +706,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 38bd38c8f9..fae4b0c5c5 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -392,7 +392,6 @@
 
 #define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index d827d2ab0b..0c2afb5065 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -414,7 +414,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index f3036c1dc2..b9d97c1006 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -441,7 +441,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 5de8b19828..e73be48d51 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -540,7 +540,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index c68e1d83d1..fcd55c7743 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -409,7 +409,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index fb76dd1aea..4ed06c9ad4 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -434,7 +434,6 @@
 
 #define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 09e32ebcd7..39459ded28 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -433,7 +433,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 923159b904..192cc2ccf1 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -528,7 +528,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index bb7f38e34a..2e6989f816 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -646,7 +646,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index f6d45a9e40..81594932d7 100644
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -500,7 +500,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index 9b2623c726..f90f7f24a4 100644
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -666,7 +666,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h
index f4c9312843..80d8fcdd98 100644
--- a/include/configs/MigoR.h
+++ b/include/configs/MigoR.h
@@ -16,7 +16,6 @@
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f398b37f5b..5384584c18 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -822,14 +822,6 @@ extern unsigned long get_sdram_size(void);
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 
 /*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-/*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
@@ -858,7 +850,6 @@ extern unsigned long get_sdram_size(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 7457dfcd48..bdf0323bfc 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -715,7 +715,6 @@
 
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index a10310ec27..07a594d15d 100644
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -308,7 +308,6 @@ extern unsigned long get_clock_freq(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY -1	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b3fb38c63a..24e5431845 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -676,7 +676,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/PATI.h b/include/configs/PATI.h
index 9f3c037237..e96fbc5aac 100644
--- a/include/configs/PATI.h
+++ b/include/configs/PATI.h
@@ -44,11 +44,6 @@
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_IRQ
 
-#if 0
-#define CONFIG_BOOTDELAY	-1		/* autoboot disabled			*/
-#else
-#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds		*/
-#endif
 #define CONFIG_BOOTCOMMAND	""	/* autoboot command			*/
 
 #define CONFIG_BOOTARGS		""		/* */
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 4506d86eee..e7c7a990f4 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -89,7 +89,6 @@
  **************************************************************/
 #define CONFIG_BAUDRATE		9600	/* STD Baudrate */
 
-#define CONFIG_BOOTDELAY	5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
 /* #define CONFIG_BOOT_RETRY_TIME	-10	/XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check console even if bootdelay = 0 */
diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h
index 71a03756d4..558f3e2ba6 100644
--- a/include/configs/PLU405.h
+++ b/include/configs/PLU405.h
@@ -118,7 +118,6 @@
 
 #define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h
index a622578bd2..5f17d76744 100644
--- a/include/configs/PMC405DE.h
+++ b/include/configs/PMC405DE.h
@@ -21,7 +21,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef  CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index 005fa2a5c1..868ca84f99 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -229,7 +229,6 @@
 		"cp.b 200000 fff90000 70000\0"				\
 	""
 
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds     */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download  */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change        */
diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h
index ef2ede49b9..b151963502 100644
--- a/include/configs/T102xQDS.h
+++ b/include/configs/T102xQDS.h
@@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin" /* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 #define __USB_PHY_TYPE		utmi
 
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 778c64b3f0..06d1d0fc49 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -867,7 +867,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	u-boot.bin /* U-Boot image on TFTP server */
 #define CONFIG_LOADADDR		1000000 /* default location for tftp, bootm */
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 #define __USB_PHY_TYPE		utmi
 
diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
index be4ae712b5..9f5063c333 100644
--- a/include/configs/T1040QDS.h
+++ b/include/configs/T1040QDS.h
@@ -749,7 +749,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index ed3493b684..a8f4f742e6 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -832,7 +832,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/*-1 disables auto-boot*/
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index d8c57a833b..1f07a83a1a 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -291,6 +291,10 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_SHIFT		0
 #define QIXIS_LBMAP_DFLTBANK		0x00
 #define QIXIS_LBMAP_ALTBANK		0x04
+#define QIXIS_LBMAP_NAND		0x09
+#define QIXIS_LBMAP_SD			0x00
+#define QIXIS_RCW_SRC_NAND		0x104
+#define QIXIS_RCW_SRC_SD		0x040
 #define QIXIS_RST_CTL_RESET		0x83
 #define QIXIS_RST_FORCE_MEM		0x1
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
@@ -817,7 +821,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define __USB_PHY_TYPE		utmi
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index b6be46e004..0ded41e0dd 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -773,7 +773,6 @@ unsigned long get_board_ddr_clk(void);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 #define __USB_PHY_TYPE		utmi
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 276428f4df..f075dfb5f0 100644
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -545,7 +545,6 @@ unsigned long get_board_ddr_clk(void);
 	(!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define __USB_PHY_TYPE	utmi
 
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index ab838a8036..9ba69a1d12 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -738,7 +738,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SHA_HW_ACCEL
 #endif
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define __USB_PHY_TYPE	utmi
 
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 42ebcf04d1..0e4067a3a9 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -199,7 +199,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 395805ca04..c557ba1778 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -37,7 +37,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index ec366370ee..814740b71d 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -35,7 +35,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 2aac682a2c..90e8dd9dd9 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -481,7 +481,6 @@
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index 00c0cc3291..58fd8a4d71 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index ca2602492e..3a4f94c83a 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 39cf02e4c4..134076c73a 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index 30bfb8afdd..ad6f8f4bb3 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index abe49b9c92..b935f31100 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 48252c4f98..79248de015 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -30,7 +30,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index a73395a270..d360644c02 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -33,7 +33,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 3db6fa1740..5c6013b41f 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -33,7 +33,6 @@
 
 #define	CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index 76c8f7a499..c098f72c67 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -44,7 +44,6 @@
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h
index 88b97ab319..9d8a607b6f 100644
--- a/include/configs/TQM885D.h
+++ b/include/configs/TQM885D.h
@@ -40,7 +40,6 @@
 
 #define CONFIG_BOOTCOUNT_LIMIT
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_BOARD_TYPES	1	/* support board types		*/
 
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index 4ae61ca9cd..0c9e79f4a5 100644
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -590,7 +590,6 @@
 
 #if defined(CONFIG_DONGLE)
 
-#define CONFIG_BOOTDELAY 1	/* autoboot after 1 seconds */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run prog_spi_mbrbootcramfs\0"					\
 "bootfile=uImage\0"							\
@@ -720,7 +719,6 @@
 
 #if defined(CONFIG_UCP1020T1)
 
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0"	\
 "bootfile=uImage\0"							\
@@ -810,7 +808,6 @@
 
 #else /* For Arcturus Modules */
 
-#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 "bootcmd=run norkernel\0"						\
 "bootfile=uImage\0"							\
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index 4e349d5caa..968e1dfd64 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -115,7 +115,6 @@
 
 #define CONFIG_BAUDRATE			9600
 
-#define CONFIG_BOOTDELAY		5
 #define CONFIG_BOOT_RETRY_TIME		-1
 #define CONFIG_RESET_TO_RETRY
 #define CONFIG_ZERO_BOOTDELAY_CHECK
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index d401d3eedb..dde98f6e75 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -27,7 +27,6 @@
 #define CONFIG_SYS_CLK_FREQ	33330000 /* external frequency to pll	*/
 
 #define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
 
 #undef	CONFIG_BOOTARGS
 #undef  CONFIG_BOOTCOMMAND
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e0c92d0497..7ec404d548 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -321,7 +321,6 @@
  * Environment Configuration
  */
 
-#define CONFIG_BOOTDELAY	3	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h
index ee1bff858f..4e240c6b89 100644
--- a/include/configs/a4m072.h
+++ b/include/configs/a4m072.h
@@ -107,7 +107,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
 
 #define CONFIG_SYS_AUTOLOAD	"n"
 
diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h
index bcf6942235..699ac41d77 100644
--- a/include/configs/ac14xx.h
+++ b/include/configs/ac14xx.h
@@ -449,14 +449,6 @@
 
 #define CONFIG_HIGH_BATS		1	/* High BATs supported */
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD			0x01
-#define BOOTFLAG_WARM			0x02
-
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
 #endif
@@ -470,7 +462,6 @@
 /* default load addr for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	2	/* -1 disables auto-boot */
 
 /* the builtin environment and standard greeting */
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h
index 7b9470c801..c4e0a21b8d 100644
--- a/include/configs/adp-ag101p.h
+++ b/include/configs/adp-ag101p.h
@@ -97,7 +97,6 @@
  */
 #define CONFIG_FTMAC100
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * SD (MMC) controller
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 16935a105a..ba4c215463 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -91,6 +91,7 @@
 
 #define CONFIG_BOOTCOMMAND \
 	"run findfdt; " \
+	"run init_console; " \
 	"run envboot; " \
 	"run distro_bootcmd"
 
@@ -169,8 +170,16 @@
 			"setenv fdtfile am335x-evm.dtb; fi; " \
 		"if test $board_name = A335X_SK; then " \
 			"setenv fdtfile am335x-evmsk.dtb; fi; " \
+		"if test $board_name = A335_ICE; then " \
+			"setenv fdtfile am335x-icev2.dtb; fi; " \
 		"if test $fdtfile = undefined; then " \
 			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"init_console=" \
+		"if test $board_name = A335_ICE; then "\
+			"setenv console ttyO3,115200n8;" \
+		"else " \
+			"setenv console ttyO0,115200n8;" \
+		"fi;\0" \
 	NANDARGS \
 	NETARGS \
 	DFUARGS \
@@ -249,11 +258,6 @@
 					"8m(NAND.kernel)," \
 					"-(NAND.file-system)"
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x000c0000
-#undef CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET		0x001c0000
-#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
-#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 /* NAND: SPL related configs */
 #ifdef CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_AM33XX_BCH
@@ -415,7 +419,6 @@
 					"128k(u-boot-env2),3464k(kernel)," \
 					"-(rootfs)"
 #elif defined(CONFIG_EMMC_BOOT)
-#undef CONFIG_ENV_IS_NOWHERE
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SYS_MMC_ENV_DEV		1
@@ -423,6 +426,27 @@
 #define CONFIG_ENV_OFFSET		0x0
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#elif defined(CONFIG_NOR_BOOT)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
+#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
+#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
+#define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
+					"512k(u-boot)," \
+					"128k(u-boot-env1)," \
+					"128k(u-boot-env2)," \
+					"4m(kernel),-(rootfs)"
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_ENV_OFFSET		0x001c0000
+#define CONFIG_ENV_OFFSET_REDUND	0x001e0000
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#elif !defined(CONFIG_ENV_IS_NOWHERE)
+/* Not NAND, SPI, NOR or eMMC env, so put ENV in a file on FAT */
+#define CONFIG_ENV_IS_IN_FAT
+#define FAT_ENV_INTERFACE		"mmc"
+#define FAT_ENV_DEVICE_AND_PART		"0:1"
+#define FAT_ENV_FILE			"uboot.env"
 #endif
 
 /* SPI flash. */
@@ -458,19 +482,11 @@
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_SYS_FLASH_SIZE		0x01000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
-/* Reduce SPL size by removing unlikey targets */
-#ifdef CONFIG_NOR_BOOT
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE		(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		(512 << 10)	/* 512 KiB */
-#define CONFIG_ENV_OFFSET_REDUND	(768 << 10)	/* 768 KiB */
-#define MTDIDS_DEFAULT			"nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT		"mtdparts=physmap-flash.0:" \
-					"512k(u-boot)," \
-					"128k(u-boot-env1)," \
-					"128k(u-boot-env2)," \
-					"4m(kernel),-(rootfs)"
-#endif
 #endif  /* NOR support */
 
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
 #endif	/* ! __CONFIG_AM335X_EVM_H */
diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h
new file mode 100644
index 0000000000..f2484cb170
--- /dev/null
+++ b/include/configs/am335x_shc.h
@@ -0,0 +1,340 @@
+/*
+ * (C) Copyright 2016
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_AM335X_SHC_H
+#define __CONFIG_AM335X_SHC_H
+
+#include <configs/ti_am335x_common.h>
+
+/* settings we don;t want on this board */
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+#undef CONFIG_CMD_EXT4
+#undef CONFIG_CMD_EXT4_WRITE
+#undef CONFIG_CMD_MMC_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_PXE
+
+#define CONFIG_CMD_CACHE
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_BOSCH_SHC_B		9001
+#define MACH_TYPE_BOSCH_SHC_B2		9002
+#define MACH_TYPE_BOSCH_SHC_C		9003
+#define MACH_TYPE_BOSCH_SHC_C2		9004
+#define MACH_TYPE_BOSCH_SHC_C3		9005
+#define MACH_TYPE_BOSCH_SHC		9006
+#ifdef CONFIG_B_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_B
+#elif defined CONFIG_B2_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_B2
+#elif defined CONFIG_C_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C
+#elif defined CONFIG_C2_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C2
+#elif defined CONFIG_C3_SAMPLE
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC_C3
+#elif defined CONFIG_SERIES
+# define CONFIG_MACH_TYPE		MACH_TYPE_BOSCH_SHC
+#endif /* #ifdef CONFIG_B_SAMPLE */
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Clock Defines */
+#define V_OSCK				24000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_ENV_IS_IN_MMC		1
+
+/*
+ * in case of SD Card or Network boot we want to have a possibility to
+ * debrick the shc, therefore do not read environment from eMMC
+ */
+#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#else
+#define CONFIG_SYS_MMC_ENV_DEV		1
+#endif
+
+/*
+ * Info when using boot partitions: As environment resides within first
+ * 128 kB, MLO must start at 128 kB == 0x20000
+ * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1,
+ * 4..7=general0..3
+ */
+#define CONFIG_ENV_SIZE				0x1000 /* 4 KB */
+#define CONFIG_ENV_OFFSET			0x7000 /* 28 kB */
+
+#define CONFIG_HSMMC2_8BIT
+
+#define CONFIG_ENV_OFFSET_REDUND    0x9000 /* 36 kB */
+#define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
+
+/* Enhance our eMMC support / experience. */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_ISO_PARTITION
+#endif
+#ifndef CONFIG_SHC_ICT
+/*
+ * In builds other than ICT, reset to retry after timeout
+ * Define a timeout after which a stopped bootloader continues autoboot
+ * (only works with CONFIG_RESET_TO_RETRY)
+ */
+# define CONFIG_BOOT_RETRY_TIME 30
+# define CONFIG_RESET_TO_RETRY
+#endif
+
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"kloadaddr=0x84000000\0" \
+	"fdtaddr=0x85000000\0" \
+	"fdt_high=0xffffffff\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=uImage\0" \
+	"fdtfile=am335x-shc.dtb\0" \
+	"verify=no\0" \
+	"serverip=10.55.152.184\0" \
+	"rootpath=/srv/nfs/shc-rootfs\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=quiet\0" \
+	"mmcdev=1\0" \
+	"harakiri=0\0" \
+	"mmcpart=2\0" \
+	"active_root=root1\0" \
+	"inactive_root=root2\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"nfsopts=nolock\0" \
+	"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
+		"::off\0" \
+	"ip_method=none\0" \
+	"bootargs_defaults=setenv bootargs " \
+		"console=${console} " \
+		"${optargs}\0" \
+	"mmcargs=run bootargs_defaults;" \
+		"setenv bootargs ${bootargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype} ip=${ip_method}\0" \
+	"netargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=/dev/nfs " \
+		"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
+		"ip=dhcp\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \
+			"echo Loaded environment from ${bootenv}; " \
+			"run importbootenv; " \
+		"fi;\0" \
+	"importbootenv=echo Importing environment variables from uEnv.txt ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \
+	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \
+	"netloaduimage=tftp ${loadaddr} ${bootfile}\0" \
+	"netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
+	"mmcboot=echo Booting Linux from ${mmcdevice} ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${kloadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${kloadaddr}; " \
+		"fi; \0" \
+	"netboot=echo Booting from network ...; " \
+		"setenv autoload no; " \
+		"dhcp; " \
+		"run netloaduimage; " \
+		"run netargs; " \
+		"echo NFS path: ${serverip}:${rootpath};" \
+		"if run netloadfdt; then " \
+			"echo device tree detected; " \
+			"bootm ${loadaddr} - ${fdtaddr}; " \
+		"else " \
+			"bootm ${loadaddr}; " \
+		"fi; \0" \
+	"emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \
+	"mmcpart_gp=mmcpart gp 1 40; \0" \
+	"mmcpart_enhance=mmcpart enhance 0 64; \0" \
+	"mmcpart_rel_write=mmcpart rel_write 1f; \0" \
+	"mmcpart_commit=mmcpart commit 1; \0" \
+	"mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \
+	"led_success=gpio set 22; \0" \
+	"fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \
+	"uenv_exec=if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...; " \
+			"run uenvcmd; " \
+		"fi;\0" \
+	"sd_setup=echo SD/MMC-Card detected on device 0; " \
+		"setenv mmcdevice SD; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \
+	"emmc_setup=echo eMMC detected on device 1; " \
+		"setenv mmcdevice eMMC; " \
+		"setenv mmcdev 1; " \
+		"run emmc_erase; " \
+		"if test ${active_root} = root2; then " \
+			"echo Active root is partition 6 (root2); " \
+			"setenv mmcpart 6; " \
+		"else " \
+			"echo Active root is partition 5 (root1); " \
+			"setenv mmcpart 5; " \
+		"fi; " \
+		"setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0"
+#endif /* #ifndef CONFIG_SPL_BUILD */
+
+#if defined CONFIG_SHC_NETBOOT
+/* Network Boot */
+# define CONFIG_BOOTCOMMAND \
+	"run fusecmd; " \
+	"if run netboot; then " \
+		"echo Booting from network; " \
+	"else " \
+		"echo ERROR: Cannot boot from network!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */
+/* SD-Card Boot */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"echo Bootable SD/MMC-Card inserted, booting from it!; " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR: Unable to load uImage from SD/MMC-Card!; " \
+		"panic; " \
+	"fi; "
+
+#elif defined CONFIG_SHC_ICT
+/* ICT adapter boots only u-boot and does HW partitioning */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 0; mmc rescan; then " \
+		"run sd_setup; " \
+	"else " \
+		"echo ERROR: SD/MMC-Card not detected!; " \
+		"panic; " \
+	"fi; " \
+	"run fusecmd; "
+
+#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */
+/* Regular Boot from internal eMMC */
+# define CONFIG_BOOTCOMMAND \
+	"if mmc dev 1; mmc rescan; then " \
+		"run emmc_setup; " \
+	"else " \
+		"echo ERROR: eMMC device not detected!; " \
+		"panic; " \
+	"fi; " \
+	"if run loaduimage; then " \
+		"run mmcboot; " \
+	"else " \
+		"echo ERROR Unable to load uImage from eMMC!; " \
+		"echo Performing Rollback!; " \
+		"setenv _active_ ${active_root}; " \
+		"setenv _inactive_ ${inactive_root}; " \
+		"setenv active_root ${_inactive_}; " \
+		"setenv inactive_root ${_active_}; " \
+		"saveenv; " \
+		"reset; " \
+	"fi; "
+
+#endif /* Regular Boot */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_SYS_NS16550_COM3		0x48024000	/* UART2 */
+#define CONFIG_SYS_NS16550_COM4		0x481a6000	/* UART3 */
+#define CONFIG_SYS_NS16550_COM5		0x481a8000	/* UART4 */
+#define CONFIG_SYS_NS16550_COM6		0x481aa000	/* UART5 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_CONS_INDEX               1
+
+/* PMIC support */
+#define CONFIG_POWER_TPS65217
+
+/* SPL */
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+#endif
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_DRIVER_TI_CPSW
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_NET_RETRY_COUNT         10
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_SMSC
+
+/* I2C configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		1
+
+#define CONFIG_SHOW_BOOT_PROGRESS
+
+#if defined CONFIG_SHC_NETBOOT
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ETH_SUPPORT
+#define CONFIG_SPL_NET_VCI_STRING	"AM335x U-Boot SPL"
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_ENV_IS_IN_MMC
+#endif
+#endif
+#endif	/* ! __CONFIG_AM335X_SHC_H */
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index e9e971e511..8454872554 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -10,7 +10,6 @@
 #define __CONFIG_AM335X_EVM_H
 
 #include <configs/ti_am335x_common.h>
-#undef CONFIG_BOOTDELAY
 
 #ifndef CONFIG_SPL_BUILD
 # define CONFIG_TIMESTAMP
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 822e1c8edc..a65d1a884b 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -156,7 +156,6 @@
 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 6f83870868..4d88aac637 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -200,7 +200,6 @@
 #endif /* CONFIG_NAND */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index 5b49988db7..361704bfd4 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -9,8 +9,6 @@
 #ifndef __CONFIG_AM43XX_EVM_H
 #define __CONFIG_AM43XX_EVM_H
 
-#define CONFIG_AM43XX
-
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_SYS_CACHELINE_SIZE       32
@@ -39,17 +37,10 @@
 #define CONFIG_POWER_TPS62362
 
 /* SPL defines. */
-#ifdef CONFIG_SPL_USB_HOST_SUPPORT
-/*
- * For USB host boot, ROM uses DMA for copying MLO from USB storage
- * and ARM internal ram is not accessible for DMA, so SPL text base
- * should be in OCMC ram
- */
-#define CONFIG_SPL_TEXT_BASE		0x40300350
-#else
-#define CONFIG_SPL_TEXT_BASE		0x402F4000
-#endif
-#define CONFIG_SPL_MAX_SIZE		(220 << 10)	/* 220KB */
+#define CONFIG_SPL_TEXT_BASE		CONFIG_ISW_ENTRY_ADDR
+#define CONFIG_SPL_MAX_SIZE		(NON_SECURE_SRAM_END - \
+					CONFIG_PUB_ROM_DATA_SIZE - \
+					CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 					 (128 << 20))
 #define CONFIG_SPL_POWER_SUPPORT
@@ -108,8 +99,6 @@
 #if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_USB_FAT_BOOT_PARTITION		1
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
@@ -192,7 +181,9 @@
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-#define CONFIG_SYS_TEXT_BASE           0x30000000
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE		CONFIG_ISW_ENTRY_ADDR
+#endif
 #undef CONFIG_ENV_IS_IN_FAT
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
@@ -296,6 +287,8 @@
 			"setenv fdtfile am43x-epos-evm.dtb; fi; " \
 		"if test $board_name = AM43__GP; then " \
 			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
+		"if test $board_name = AM43XXHS; then " \
+			"setenv fdtfile am437x-gp-evm.dtb; fi; " \
 		"if test $board_name = AM43__SK; then " \
 			"setenv fdtfile am437x-sk-evm.dtb; fi; " \
 		"if test $board_name = AM43_IDK; then " \
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index d53b0fdd89..2db199db33 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -64,8 +64,6 @@
 
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index 9fa4d16243..2666ca6f69 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -60,7 +60,6 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size	*/
 #else
diff --git a/include/configs/amcore.h b/include/configs/amcore.h
index e819185f77..5667680230 100644
--- a/include/configs/amcore.h
+++ b/include/configs/amcore.h
@@ -18,7 +18,6 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOOTCOMMAND		"bootm ffc20000"
 
 #undef CONFIG_CMD_AES
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 2beffa4805..bf5746fcb8 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE            0x9f000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  200
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000
@@ -41,19 +34,18 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY                3
 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
 					"root=/dev/mtdblock2 " \
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f650000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
+					"6144k(rootfs),1600k(uImage)," \
 					"64k(NVRAM),64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 7b69e10be4..5d7e49e4a1 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE            0x9f000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  325
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000
@@ -45,20 +38,19 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY                3
 #define CONFIG_BOOTARGS                 "console=ttyS0,115200 " \
 					"root=/dev/mtdblock2 " \
 					"rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND              "sf probe;" \
 					"mtdparts default;" \
-					"bootm 0x9f300000"
+					"bootm 0x9f680000"
 #define CONFIG_LZMA
 
 #define MTDIDS_DEFAULT                  "nor0=spi-flash.0"
 #define MTDPARTS_DEFAULT                "mtdparts=spi-flash.0:" \
 					"256k(u-boot),64k(u-boot-env)," \
-					"2752k(rootfs),896k(uImage)," \
-					"64k(NVRAM),64k(ART)"
+					"6336k(rootfs),1472k(uImage)," \
+					"64k(ART)"
 
 #define CONFIG_ENV_SPI_MAX_HZ           25000000
 #define CONFIG_ENV_IS_IN_SPI_FLASH
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
index ae58ec8d2a..7dd24612f1 100644
--- a/include/configs/ap325rxa.h
+++ b/include/configs/ap325rxa.h
@@ -19,7 +19,6 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_BAUDRATE		38400
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,38400"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h
index be8feed124..37f2d3093a 100644
--- a/include/configs/ap_sh4a_4a.h
+++ b/include/configs/ap_sh4a_4a.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC4,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 2291647c64..f44f71cebe 100644
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -148,7 +148,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
 #define CONFIG_INITRD_TAG		/* send initrd params	*/
 
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
 #define CONFIG_BOOTARGS		"console=" __stringify(ACFG_CONSOLE_DEV) "," \
diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index bb29f3f5bc..50eaf609b5 100644
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -93,7 +93,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTCOMMAND		"run bootcmd_nand"
 #define CONFIG_LOADADDR			0x41000000
diff --git a/include/configs/arcangel4.h b/include/configs/arcangel4.h
index 8a860eef6a..d6081048fe 100644
--- a/include/configs/arcangel4.h
+++ b/include/configs/arcangel4.h
@@ -54,7 +54,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyARC0,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/aria.h b/include/configs/aria.h
index 2d32da1f94..cb506589d9 100644
--- a/include/configs/aria.h
+++ b/include/configs/aria.h
@@ -510,7 +510,6 @@
 
 #define CONFIG_LOADADDR			400000	/* default load addr */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 681b4e743e..522b287104 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -22,7 +22,6 @@
 #define BOARD_LATE_INIT
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		""
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index b08276f32d..e8dca0b2cc 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -149,19 +149,6 @@
 /* AUTOBOOT settings - booting images automatically by u-boot after power on */
 
 /*
- * used for autoboot, delay in seconds u-boot will wait before starting
- * defined (auto-)boot command, setting to -1 disables delay, setting to
- * 0 will too prevent access to u-boot command interface: u-boot then has
- * to be reflashed
- * beware - watchdog is not serviced during autoboot delay time!
- */
-#ifdef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_BOOTDELAY	1
-#else
-#define CONFIG_BOOTDELAY	1
-#endif
-
-/*
  * The following settings will be contained in the environment block ; if you
  * want to use a neutral environment all those settings can be manually set in
  * u-boot: 'set' command
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index dc955b2452..9257c5f029 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -34,7 +34,6 @@
 /* general purpose I/O */
 #define CONFIG_AT91_GPIO
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index 2979b25abc..c92ad85238 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -171,7 +171,6 @@
 /*
  * Boot option
  */
-#define CONFIG_BOOTDELAY		3
 
 /* default load address */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + SZ_16M
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 9db8d12868..c6d3295f34 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -61,7 +61,6 @@
 #define	CONFIG_RED_LED		AT91_PIN_PA9	/* this is the power led */
 #define	CONFIG_GREEN_LED	AT91_PIN_PA6	/* this is the user led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index b369624a2c..9c9461bc98 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -69,7 +69,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index f248049e54..e7bfd49450 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -76,7 +76,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PB8	/* the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PC29	/* the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 18eb01dc8c..290b039e11 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -59,7 +59,6 @@
 #define	CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
 #define	CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 2f8c377413..297938b93e 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -51,7 +51,6 @@
 #define CONFIG_ATMEL_LCD_RGB565
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * BOOTP options
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index d178d9d44b..a383de64bc 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -65,7 +65,6 @@
 #define	CONFIG_GREEN_LED	AT91_PIN_PD15	/* this is the user1 led */
 #define	CONFIG_YELLOW_LED	AT91_PIN_PD16	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * Command line configuration.
diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index 251094e60b..743fc397d1 100644
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -47,7 +47,6 @@
 #define CONFIG_ATMEL_LCD_RGB565
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index e6f6125dd2..a0f451b1a0 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -62,7 +62,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload; bootm"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h
index dfa2d93a90..4d9282a7bf 100644
--- a/include/configs/atngw100mkii.h
+++ b/include/configs/atngw100mkii.h
@@ -81,7 +81,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload 0x10400000 /uImage; bootm"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index 9a647d8446..9ddfff2b2c 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -79,7 +79,6 @@
 #define CONFIG_BOOTCOMMAND						\
 	"fsload; bootm $(fileaddr)"
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 05d2d45b25..c0b68e2277 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -119,7 +119,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index e95deac737..de60bb1035 100644
--- a/include/configs/bct-brettl2.h
+++ b/include/configs/bct-brettl2.h
@@ -117,7 +117,6 @@
 /*
  * Misc Settings
  */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_LOADADDR		0x800000
 #define CONFIG_MISC_INIT_R
 #define CONFIG_UART_CONSOLE	0
diff --git a/include/configs/bf525-ucr2.h b/include/configs/bf525-ucr2.h
index 66339ca971..f7a45e9fdd 100644
--- a/include/configs/bf525-ucr2.h
+++ b/include/configs/bf525-ucr2.h
@@ -85,7 +85,6 @@
 #define CONFIG_BFIN_SERIAL
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw"
 #define CONFIG_BOOTCOMMAND	"run sfboot"
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"sfboot=sf probe 1;" \
 		"sf read 0x1000000 0x20000 0x300000;" \
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 74c3464c4d..cf8ef8af75 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -125,7 +125,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index e2684735a7..c958a942ec 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -128,7 +128,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF522__) && !defined(__ADSPBF523__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h
index 43a90328fe..2c7972043a 100644
--- a/include/configs/bf537-minotaur.h
+++ b/include/configs/bf537-minotaur.h
@@ -129,12 +129,6 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_LOADS_ECHO		1
 
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h
index 70553662e7..6ad5682a19 100644
--- a/include/configs/bf537-srv1.h
+++ b/include/configs/bf537-srv1.h
@@ -129,15 +129,6 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_LOADS_ECHO		1
 
-#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-# define CONFIG_BOOTDELAY	-1
-#else
-# define CONFIG_BOOTDELAY	5
-#endif
-
-#ifdef CONFIG_BFIN_MAC
-#endif
-
 #define CONFIG_CMD_BOOTLDR
 #define CONFIG_CMD_DATE
 
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index 6830e4d7c9..be28ea33ad 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -151,7 +151,6 @@
  * USB Settings
  */
 #if !defined(__ADSPBF544__)
-#define CONFIG_USB
 #define CONFIG_USB_MUSB_HCD
 #define CONFIG_USB_BLACKFIN
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 88d2ae997e..13076072e4 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -99,9 +99,7 @@
  */
 #ifndef CONFIG_BOOTDELAY
 # if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
-#  define CONFIG_BOOTDELAY	-1
 # else
-#  define CONFIG_BOOTDELAY	5
 # endif
 #endif
 #ifndef CONFIG_BOOTCOMMAND
diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index 6a5bc126b0..e13f736a8f 100644
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -55,7 +55,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
 #define CONFIG_BOOTCOMMAND	"bootm"
diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h
index 6eb83a05a7..dc596fae3e 100644
--- a/include/configs/blackstamp.h
+++ b/include/configs/blackstamp.h
@@ -106,7 +106,6 @@
 #define CONFIG_CMD_CPLBINFO
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY     5
 #define CONFIG_BOOTCOMMAND   "run ramboot"
 #define CONFIG_BOOTARGS \
 	"root=/dev/mtdblock0 rw " \
diff --git a/include/configs/blackvme.h b/include/configs/blackvme.h
index ba90830a1e..d3dc216c5f 100644
--- a/include/configs/blackvme.h
+++ b/include/configs/blackvme.h
@@ -155,7 +155,6 @@
  * Default: boot from SPI flash.
  * "sfboot" is a composite command defined in extra settings
  */
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOTCOMMAND	"run sfboot"
 
 /*
diff --git a/include/configs/br4.h b/include/configs/br4.h
index 402f352fc5..16e4a1d4e2 100644
--- a/include/configs/br4.h
+++ b/include/configs/br4.h
@@ -119,7 +119,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
 
 /*
diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 506ad882c8..3b10360b5e 100644
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -214,7 +214,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS           ""
 #define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
-#define CONFIG_BOOTDELAY          0
 #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
 #define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
 #define CONFIG_RESET_TO_RETRY
diff --git a/include/configs/canmb.h b/include/configs/canmb.h
index 31fe5f6b81..b41666064c 100644
--- a/include/configs/canmb.h
+++ b/include/configs/canmb.h
@@ -65,7 +65,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 99182f4de3..0dd5e996b6 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -64,7 +64,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
 	"echo"
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index 0fb853002c..de1999d431 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -145,7 +145,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h
index 7c087c6f5d..87e41bfaba 100644
--- a/include/configs/cm_t3517.h
+++ b/include/configs/cm_t3517.h
@@ -152,7 +152,6 @@
 							/* devices */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index c2dbd31803..50765408db 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -61,9 +61,7 @@
 
 /* USB support */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_OMAP
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
 #define CONFIG_OMAP_USB_PHY
diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h
index ff63d7a775..68851ee90f 100644
--- a/include/configs/cm_t54.h
+++ b/include/configs/cm_t54.h
@@ -108,9 +108,7 @@
 #undef CONFIG_SYS_AUTOLOAD
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #undef CONFIG_BOOTCOMMAND
-#undef CONFIG_BOOTDELAY
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_SYS_AUTOLOAD		"no"
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 509c8b42fb..4396698b7f 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -149,7 +149,6 @@
 
 /*AUTOBOOT settings - booting images automatically by u-boot after power on*/
 
-#define CONFIG_BOOTDELAY	5		/* used for autoboot, delay in
 seconds u-boot will wait before starting defined (auto-)boot command, setting
 to -1 disables delay, setting to 0 will too prevent access to u-boot command
 interface: u-boot then has to reflashed */
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 5dffc9e186..ba8d93ce1f 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -37,7 +37,6 @@
 	"bootm 0xc0000;"
 #define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
 #define	CONFIG_TIMESTAMP
-#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_LZMA			/* LZMA compression support */
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 50f7c21ac2..58925952dd 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -89,7 +89,6 @@
 #define CONFIG_NETMASK		255.255.255.0
 #define CONFIG_SERVERIP		192.168.10.1
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_BOARD_LATE_INIT
 
 #define CONFIG_LOADADDR			0x80008000
diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index c60c644393..30c283185b 100644
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -417,7 +417,6 @@
 
 #ifdef CONFIG_TRAILBLAZER
 
-#define CONFIG_BOOTDELAY	0	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
@@ -432,7 +431,6 @@
 
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index a06bfe05ad..4a770b0546 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -682,7 +682,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 8b3c7153f0..686760d0a5 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -54,7 +54,6 @@
 #define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
 #define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 660646eb91..708d5f730d 100644
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -505,7 +505,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
 
 #define CONFIG_BAUDRATE	115200
 
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index af220febf4..3e4bba5587 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -278,7 +278,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		\
 	"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_EXTRA_ENV_SETTINGS	"hwconfig=dsp:wake=yes"
 
 /*
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index eb0a87cd59..dbd2bb3b09 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -37,7 +37,6 @@
 #endif
 #endif
 
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
 
 #define CONFIG_BAUDRATE		115200
 
@@ -139,12 +138,6 @@
 #define CONFIG_SYS_FLASH_CFI           1
 #define CONFIG_FLASH_CFI_DRIVER    1
 
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-#define CONFIG_SYS_TEXT_BASE		0xbfc00000
-/* RAM version */
-/* #define CONFIG_SYS_TEXT_BASE		0x80100000 */
-
 #define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
@@ -208,11 +201,4 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h
index 913b9481f2..73f53d4a2b 100644
--- a/include/configs/devkit3250.h
+++ b/include/configs/devkit3250.h
@@ -179,7 +179,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		1
 
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h
index 18804d43fd..1145e37639 100644
--- a/include/configs/digsy_mtc.h
+++ b/include/configs/digsy_mtc.h
@@ -117,7 +117,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	1
 
 #undef	CONFIG_BOOTARGS
 
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8a0cd66cd0..0d51aeb869 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -211,8 +211,6 @@
 
 /* USB xHCI HOST */
 #define CONFIG_USB_HOST
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_OMAP
 #define CONFIG_USB_STORAGE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
diff --git a/include/configs/draco.h b/include/configs/draco.h
index 8aee25b96a..889178c283 100644
--- a/include/configs/draco.h
+++ b/include/configs/draco.h
@@ -73,6 +73,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=draco\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
@@ -82,7 +83,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -94,7 +94,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/ds414.h b/include/configs/ds414.h
index 64c546cc82..23373cdb58 100644
--- a/include/configs/ds414.h
+++ b/include/configs/ds414.h
@@ -71,12 +71,11 @@
  * - USB init fails, controller does not respond in time */
 #if 0
 #undef CONFIG_DM_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_PCI
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
 #endif
 
-#if !defined(CONFIG_USB_XHCI)
+#if !defined(CONFIG_USB_XHCI_HCD)
 #define CONFIG_USB_EHCI
 #define CONFIG_USB_EHCI_MARVELL
 #define CONFIG_EHCI_IS_TDI
diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index d4f3cfa8e9..3f8578fd58 100644
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -137,7 +137,6 @@
 #define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 
 /*
  * U-Boot commands
diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h
index 521e3cf335..6d469a383c 100644
--- a/include/configs/eb_cpu5282.h
+++ b/include/configs/eb_cpu5282.h
@@ -69,7 +69,6 @@
 
 #define CONFIG_MCFTMR
 
-#define CONFIG_BOOTDELAY	5
 #define	CONFIG_SYS_LONGHELP	1
 
 #define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size	*/
diff --git a/include/configs/eco5pk.h b/include/configs/eco5pk.h
index bb5d7e581e..c7b0a389c9 100644
--- a/include/configs/eco5pk.h
+++ b/include/configs/eco5pk.h
@@ -31,7 +31,6 @@
 #define MACH_TYPE_ECO5_PK	4017
 #define CONFIG_MACH_TYPE	MACH_TYPE_ECO5_PK
 
-#define CONFIG_BOOTDELAY	10
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h
index 2ac7757b0c..706ad1d2a3 100644
--- a/include/configs/ecovec.h
+++ b/include/configs/ecovec.h
@@ -37,7 +37,6 @@
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
index 174cdf3302..f3f7549688 100644
--- a/include/configs/edb93xx.h
+++ b/include/configs/edb93xx.h
@@ -26,7 +26,6 @@
 #endif
 
 /* Initial environment and monitor configuration options. */
-#define CONFIG_BOOTDELAY		2
 #define CONFIG_CMDLINE_TAG		1
 #define CONFIG_INITRD_TAG		1
 #define CONFIG_SETUP_MEMORY_TAGS	1
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 99d16b06c0..f9d4683fcb 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -115,7 +115,6 @@
 #define CONFIG_SYS_FLASH_BASE		0xfff80000
 
 /* auto boot */
-#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h
new file mode 100644
index 0000000000..c6a756d2b9
--- /dev/null
+++ b/include/configs/espresso7420.h
@@ -0,0 +1,34 @@
+/*
+ * Configuration settings for the SAMSUNG ESPRESSO7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ESPRESSO7420_H
+#define __CONFIG_ESPRESSO7420_H
+
+#include <configs/exynos7420-common.h>
+
+#define CONFIG_BOARD_COMMON
+
+#define CONFIG_ESPRESSO7420
+#define CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_TEXT_BASE		0x43E00000
+#define CONFIG_SPL_STACK		CONFIG_IRAM_END
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_IRAM_END
+
+/* select serial console configuration */
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+#define CONFIG_IDENT_STRING	" for ESPRESSO7420"
+#define CONFIG_DEFAULT_CONSOLE	"console=ttySAC1,115200n8\0"
+
+/* DRAM Memory Banks */
+#define CONFIG_NR_DRAM_BANKS	8
+#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
+
+#endif	/* __CONFIG_ESPRESSO7420_H */
diff --git a/include/configs/espt.h b/include/configs/espt.h
index 3d67376498..86e726c63c 100644
--- a/include/configs/espt.h
+++ b/include/configs/espt.h
@@ -20,7 +20,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 
-#define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 
diff --git a/include/configs/etamin.h b/include/configs/etamin.h
new file mode 100644
index 0000000000..4919cfe353
--- /dev/null
+++ b/include/configs/etamin.h
@@ -0,0 +1,257 @@
+/*
+ * (C) Copyright 2013 Siemens Schweiz AG
+ * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * U-Boot file:/include/configs/am335x_evm.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ETAMIN_H
+#define __CONFIG_ETAMIN_H
+
+#include "siemens-am33x-common.h"
+/* NAND specific changes for etamin due to different page size */
+#undef CONFIG_SYS_NAND_PAGE_SIZE
+#undef CONFIG_SYS_NAND_OOBSIZE
+#undef CONFIG_SYS_NAND_BLOCK_SIZE
+#undef CONFIG_SYS_NAND_ECCPOS
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#undef CONFIG_SYS_ENV_SECT_SIZE
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_NAND_OMAP_ECCSCHEME
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
+
+#define CONFIG_ENV_OFFSET       0x980000
+#define CONFIG_SYS_ENV_SECT_SIZE       (512 << 10)     /* 512 KiB */
+#define CONFIG_SYS_NAND_PAGE_SIZE       4096
+#define CONFIG_SYS_NAND_OOBSIZE         224
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
+				10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
+				20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
+				30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
+				40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
+				50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
+				60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
+				70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
+				80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
+				90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
+			100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
+			110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
+			120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
+			130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
+			140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
+			150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
+			160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
+			170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
+			180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
+			190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
+			200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
+			}
+
+#undef CONFIG_SYS_NAND_ECCSIZE
+#undef CONFIG_SYS_NAND_ECCBYTES
+#define CONFIG_SYS_NAND_ECCSIZE 512
+#define CONFIG_SYS_NAND_ECCBYTES 26
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     0x200000
+
+#define CONFIG_SYS_NAND_MAX_CHIPS       1
+
+#undef CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_MAX_NAND_DEVICE      3
+#define CONFIG_SYS_NAND_BASE2           (0x18000000)    /* physical address */
+#define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
+					CONFIG_SYS_NAND_BASE2}
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_MPUCLK	300
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+/* FWD Button = 27
+ * SRV Button = 87 */
+#define BOARD_DFU_BUTTON_GPIO	27
+#define GPIO_LAN9303_NRST	88	/* GPIO2_24 = gpio88 */
+/* In dfu mode keep led1 on */
+#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	"button_dfu0=27\0" \
+	"button_dfu1=87\0" \
+	"led0=3,0,1\0" \
+	"led1=4,0,0\0" \
+	"led2=5,0,1\0" \
+	"led3=87,0,1\0" \
+	"led4=60,0,1\0" \
+	"led5=63,0,1\0"
+
+#undef CONFIG_DOS_PARTITION
+#undef CONFIG_CMD_FAT
+
+#define CONFIG_BOARD_LATE_INIT
+
+/* Physical Memory Map */
+#define CONFIG_MAX_RAM_BANK_SIZE       (1024 << 20)    /* 1GB */
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
+#define EEPROM_ADDR_DDR3 0x90
+#define EEPROM_ADDR_CHIP 0x120
+
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x300
+
+#undef CONFIG_SPL_NET_SUPPORT
+#undef CONFIG_SPL_NET_VCI_STRING
+#undef CONFIG_SPL_ETH_SUPPORT
+
+#undef CONFIG_MII
+#undef CONFIG_PHY_GIGE
+#define CONFIG_PHY_SMSC
+
+#define CONFIG_FACTORYSET
+
+/* use both define to compile a SPL compliance test  */
+/*
+#define CONFIG_SPL_CMT
+#define CONFIG_SPL_CMT_DEBUG
+*/
+
+/* nedded by compliance test in read mode */
+#if defined(CONFIG_SPL_CMT)
+#define CONFIG_SYS_DCACHE_OFF
+#endif
+
+/* Watchdog */
+#define CONFIG_OMAP_WATCHDOG
+
+/* Define own nand partitions */
+#define CONFIG_ENV_OFFSET_REDUND	0xB80000
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_RANGE		(4 * CONFIG_SYS_ENV_SECT_SIZE)
+
+
+
+#define CONFIG_DFU_MTD
+#undef COMMON_ENV_DFU_ARGS
+#define COMMON_ENV_DFU_ARGS	"dfu_args=run bootargs_defaults;" \
+				"setenv bootargs ${bootargs};" \
+				"mtdparts default;" \
+				"draco_led 1;" \
+				"dfu 0 mtd 0;" \
+				"draco_led 0;\0" \
+
+#undef DFU_ALT_INFO_NAND_V2
+#define DFU_ALT_INFO_NAND_V2 \
+	"spl mtddev;" \
+	"spl.backup1 mtddev;" \
+	"spl.backup2 mtddev;" \
+	"spl.backup3 mtddev;" \
+	"u-boot mtddev;" \
+	"u-boot.env0 mtddev;" \
+	"u-boot.env1 mtddev;" \
+	"rootfs mtddevubi" \
+
+#undef MTDIDS_NAME_STR
+#define MTDIDS_NAME_STR		"omap2-nand_concat"
+#undef MTDIDS_DEFAULT
+#define MTDIDS_DEFAULT		"nand2=" MTDIDS_NAME_STR
+
+#undef MTDPARTS_DEFAULT_V2
+#define MTDPARTS_DEFAULT_V2     "mtdparts=" MTDIDS_NAME_STR ":" \
+				"512k(spl)," \
+				"512k(spl.backup1)," \
+				"512k(spl.backup2)," \
+				"512k(spl.backup3)," \
+				"7680k(u-boot)," \
+				"2048k(u-boot.env0)," \
+				"2048k(u-boot.env1)," \
+				"2048k(mtdoops)," \
+				"-(rootfs)"
+
+#undef MTDPARTS_DEFAULT
+#define MTDPARTS_DEFAULT	MTDPARTS_DEFAULT_V2
+
+#undef CONFIG_ENV_SETTINGS_NAND_V2
+#define CONFIG_ENV_SETTINGS_NAND_V2 \
+	"nand_active_ubi_vol=rootfs_a\0" \
+	"rootfs_name=rootfs\0" \
+	"kernel_name=uImage\0"\
+	"nand_root_fs_type=ubifs rootwait=1\0" \
+	"nand_args=run bootargs_defaults;" \
+		"mtdparts default;" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_a;" \
+		"fi;" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${rootfs_name}_b;" \
+		"fi;" \
+		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
+		"ubi.mtd=rootfs,${ubi_off};" \
+		"setenv bootargs ${bootargs} " \
+		"root=${nand_root} noinitrd ${mtdparts} " \
+		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
+		"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
+		"=mtdoops\0" \
+	COMMON_ENV_DFU_ARGS \
+		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
+	COMMON_ENV_NAND_BOOT \
+		"ubi part rootfs ${ubi_off};" \
+		"ubifsmount ubi0:${nand_active_ubi_vol};" \
+		"ubifsload ${kloadaddr} boot/${kernel_name};" \
+		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	"nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \
+		"bootm ${kloadaddr} - ${loadaddr}\0" \
+	COMMON_ENV_NAND_CMDS
+
+#ifndef CONFIG_SPL_BUILD
+
+#define CONFIG_NAND_CS_INIT
+#define ETAMIN_NAND_GPMC_CONFIG1	0x00000800
+#define ETAMIN_NAND_GPMC_CONFIG2	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG3	0x001e1e00
+#define ETAMIN_NAND_GPMC_CONFIG4	0x16051807
+#define ETAMIN_NAND_GPMC_CONFIG5	0x00151e1e
+#define ETAMIN_NAND_GPMC_CONFIG6	0x16000f80
+#define CONFIG_MTD_CONCAT
+
+/* Default env settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"hostname=etamin\0" \
+	"ubi_off=4096\0"\
+	"nand_img_size=0x400000\0" \
+	"optargs=\0" \
+	"preboot=draco_led 0\0" \
+	CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \
+	CONFIG_ENV_SETTINGS_V2 \
+	CONFIG_ENV_SETTINGS_NAND_V2
+
+#ifndef CONFIG_RESTORE_FLASH
+
+#define CONFIG_BOOTCOMMAND \
+"if dfubutton; then " \
+	"run dfu_start; " \
+	"reset; " \
+"fi;" \
+"run nand_boot;" \
+"run nand_boot_backup;" \
+"reset;"
+
+
+#else
+#define CONFIG_BOOTCOMMAND			\
+	"setenv autoload no; "			\
+	"dhcp; "				\
+	"if tftp 80000000 debrick.scr; then "	\
+		"source 80000000; "		\
+	"fi"
+#endif
+#endif	/* CONFIG_SPL_BUILD */
+#endif	/* ! __CONFIG_ETAMIN_H */
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 94fee54ccd..bd32cdbf73 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -205,7 +205,6 @@
 #define CONFIG_RBTREE
 
 /* Boot command */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index b2ff4dd927..f2ed7982b4 100644
--- a/include/configs/exynos5-common.h
+++ b/include/configs/exynos5-common.h
@@ -60,7 +60,6 @@
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
 /* specific .lds file */
@@ -124,7 +123,6 @@
 #define CONFIG_SYS_I2C_S3C24X0
 #define CONFIG_SYS_I2C_S3C24X0_SPEED	100000		/* 100 Kbps */
 #define CONFIG_SYS_I2C_S3C24X0_SLAVE    0x0
-#define CONFIG_I2C_EDID
 
 /* SPI */
 #ifdef CONFIG_SPI_FLASH
@@ -157,7 +155,6 @@
 
 /* USB */
 #define CONFIG_USB_STORAGE
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 
diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h
index 8b61a52c5a..3d81f9457d 100644
--- a/include/configs/exynos5-dt-common.h
+++ b/include/configs/exynos5-dt-common.h
@@ -13,8 +13,8 @@
 #undef EXYNOS_DEVICE_SETTINGS
 #define EXYNOS_DEVICE_SETTINGS \
 		"stdin=serial,cros-ec-keyb\0" \
-		"stdout=serial,lcd\0" \
-		"stderr=serial,lcd\0"
+		"stdout=serial,vidconsole\0" \
+		"stderr=serial,vidconsole\0"
 
 #define CONFIG_EXYNOS5_DT
 
@@ -32,6 +32,7 @@
 #define CONFIG_EXYNOS_FB
 #define CONFIG_EXYNOS_DP
 #define LCD_BPP			LCD_COLOR16
+#define CONFIG_SYS_WHITE_ON_BLACK
 #endif
 
 /* Enable keyboard */
diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h
index cd86e06668..16153eb595 100644
--- a/include/configs/exynos5420-common.h
+++ b/include/configs/exynos5420-common.h
@@ -48,7 +48,6 @@
  */
 #define CONFIG_CORE_COUNT		0x8
 
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
 #endif	/* __CONFIG_EXYNOS5420_H */
diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h
new file mode 100644
index 0000000000..9e0396208a
--- /dev/null
+++ b/include/configs/exynos7420-common.h
@@ -0,0 +1,113 @@
+/*
+ * Configuration settings for the Espresso7420 board.
+ * Copyright (C) 2016 Samsung Electronics
+ * Thomas Abraham <thomas.ab@samsung.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_EXYNOS7420_COMMON_H
+#define __CONFIG_EXYNOS7420_COMMON_H
+
+/* High Level Configuration Options */
+#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
+#define CONFIG_EXYNOS7420		/* Exynos7 Family */
+#define CONFIG_S5P
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <linux/sizes.h>
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Size of malloc() pool before and after relocation */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		1024	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+/* Timer input clock frequency */
+#define COUNTER_FREQUENCY		24000000
+
+/* Device Tree */
+#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420"
+
+/* IRAM Layout */
+#define CONFIG_IRAM_BASE		0x02100000
+#define CONFIG_IRAM_SIZE		0x58000
+#define CONFIG_IRAM_END			(CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE)
+
+/* Number of CPUs available */
+#define CONFIG_CORE_COUNT		0x8
+
+/* select serial console configuration */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SILENT_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
+
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
+#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
+#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
+#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
+#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE
+
+/* Configuration of ENV Blocks */
+#define CONFIG_ENV_SIZE	(16 << 10) /* 16 KB */
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+
+#ifndef MEM_LAYOUT_ENV_SETTINGS
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0x10000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x43300000\0" \
+	"scriptaddr=0x50000000\0" \
+	"pxefile_addr_r=0x51000000\0"
+#endif
+
+#ifndef EXYNOS_DEVICE_SETTINGS
+#define EXYNOS_DEVICE_SETTINGS \
+	"stdin=serial\0" \
+	"stdout=serial\0" \
+	"stderr=serial\0"
+#endif
+
+#ifndef EXYNOS_FDTFILE_SETTING
+#define EXYNOS_FDTFILE_SETTING
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	EXYNOS_DEVICE_SETTINGS \
+	EXYNOS_FDTFILE_SETTING \
+	MEM_LAYOUT_ENV_SETTINGS
+
+#endif	/* __CONFIG_EXYNOS7420_COMMON_H */
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 7400870b21..824aca45b6 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -81,7 +81,6 @@
 
 #define CONFIG_NET_RETRY_COUNT	100
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 40334601a3..4de2460bc0 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -36,7 +36,6 @@
 
 #define CONFIG_SUPPORT_EMMC_BOOT
 
-#define CONFIG_BOOTDELAY               1
 
 #include "mx6_common.h"
 #include <linux/sizes.h>
diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h
index f3361d0255..8b573545cd 100644
--- a/include/configs/gr_cpci_ax2000.h
+++ b/include/configs/gr_cpci_ax2000.h
@@ -14,7 +14,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
@@ -66,7 +65,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h
index 94eb7acd77..4e7819912d 100644
--- a/include/configs/gr_ep2s60.h
+++ b/include/configs/gr_ep2s60.h
@@ -15,7 +15,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
@@ -68,7 +67,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h
index dcb72c92a1..36acf01631 100644
--- a/include/configs/gr_xc3s_1500.h
+++ b/include/configs/gr_xc3s_1500.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
@@ -47,7 +46,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h
index 83f1d73087..f1afdedb3c 100644
--- a/include/configs/grasshopper.h
+++ b/include/configs/grasshopper.h
@@ -74,7 +74,6 @@
 
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY		1
 
 /*
  * After booting the board for the first time, new ethernet addresses
diff --git a/include/configs/grsim.h b/include/configs/grsim.h
index 3e81f0d70d..c2656fbeb2 100644
--- a/include/configs/grsim.h
+++ b/include/configs/grsim.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
@@ -59,7 +58,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h
index ab1e11d1ae..59adbdc102 100644
--- a/include/configs/grsim_leon2.h
+++ b/include/configs/grsim_leon2.h
@@ -12,7 +12,6 @@
 #ifndef __CONFIG_H__
 #define __CONFIG_H__
 
-#define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*
@@ -54,7 +53,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
diff --git a/include/configs/h2200.h b/include/configs/h2200.h
index 3d510d6d88..3e419c6445 100644
--- a/include/configs/h2200.h
+++ b/include/configs/h2200.h
@@ -135,7 +135,6 @@
 #define CONFIG_USB_DEV_PULLUP_GPIO	33
 /* USB VBUS GPIO 3 */
 
-#define CONFIG_BOOTDELAY		2
 #define CONFIG_BOOTCOMMAND		\
 	"setenv downloaded 0 ; while test $downloaded -eq 0 ; do " \
 	"if bootp ; then setenv downloaded 1 ; fi ; done ; " \
diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h
index 9f02a654c3..6a8660b088 100644
--- a/include/configs/hrcon.h
+++ b/include/configs/hrcon.h
@@ -621,7 +621,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_HOSTNAME		hrcon
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h
index 04515ba80a..b750d72d35 100644
--- a/include/configs/ids8313.h
+++ b/include/configs/ids8313.h
@@ -25,7 +25,6 @@
 
 #define CONFIG_BOOT_RETRY_TIME		900
 #define CONFIG_BOOT_RETRY_MIN		30
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_RESET_TO_RETRY
 
 #define CONFIG_83XX_CLKIN		66000000	/* in Hz */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index b8ee44d868..80628ddaf3 100644
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -175,7 +175,6 @@
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NAND
 
-#define CONFIG_BOOTDELAY	5
 
 #define CONFIG_LOADADDR		0xa0800000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 94fc077539..50dfc11523 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -54,7 +54,6 @@
  ***********************************************************/
 #define CONFIG_CMD_EEPROM
 
-#define CONFIG_BOOTDELAY	3
 
 #define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:128k(uboot)ro," \
 					"1536k(kernel),-(root)"
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index 0d4f2925cd..3420a39ade 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -92,7 +92,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index a5a8819727..e7d058f7a8 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -31,7 +31,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS		"root=/dev/mtdblock0 console=ttyAM0 console=tty"
 #define CONFIG_BOOTCOMMAND	""
 
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h
index af69ad99c4..d0b6af8cad 100644
--- a/include/configs/integratorcp.h
+++ b/include/configs/integratorcp.h
@@ -31,7 +31,6 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_BOOTARGS	"root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0"
 #define CONFIG_BOOTCOMMAND "tftpboot ; bootm"
 #define CONFIG_SERVERIP 192.168.1.100
diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index b2a6e7fb05..b36b75dfb6 100644
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -223,7 +223,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \
 		"root=/dev/mtdblock5 rw noinitrd " \
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 55ed6569ef..eb4e3aea38 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -115,7 +115,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h
index 062820305d..65f53b7612 100644
--- a/include/configs/jupiter.h
+++ b/include/configs/jupiter.h
@@ -92,7 +92,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index 07f975bb37..7eaab875f2 100644
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2e-evm.dtb\0"					\
+	"name_fdt=keystone-k2e-evm.dtb\0"				\
 	"name_mon=skern-k2e.bin\0"					\
 	"name_ubi=k2e-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2e-evm.gph\0"				\
diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h
index 3f98510268..f8bba6710d 100644
--- a/include/configs/k2g_evm.h
+++ b/include/configs/k2g_evm.h
@@ -26,7 +26,7 @@
 	"addr_mon=0x0c040000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2g-evm.dtb\0"				\
+	"name_fdt=keystone-k2g-evm.dtb\0"				\
 	"name_mon=skern-k2g.bin\0"					\
 	"name_ubi=k2g-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2g-evm.gph\0"				\
diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index a268a86736..0256f0e567 100644
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c5f0000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0"	\
-	"name_fdt=k2hk-evm.dtb\0"				\
+	"name_fdt=keystone-k2hk-evm.dtb\0"				\
 	"name_mon=skern-k2hk.bin\0"					\
 	"name_ubi=k2hk-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2hk-evm.gph\0"				\
diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index f366e6703d..2322ab288d 100644
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -21,7 +21,7 @@
 	"addr_mon=0x0c140000\0"						\
 	"args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "	\
 	"root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0"	\
-	"name_fdt=k2l-evm.dtb\0"					\
+	"name_fdt=keystone-k2l-evm.dtb\0"				\
 	"name_mon=skern-k2l.bin\0"					\
 	"name_ubi=k2l-evm-ubifs.ubi\0"					\
 	"name_uboot=u-boot-spi-k2l-evm.gph\0"				\
diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h
index 9f76034e61..6f2773b88c 100644
--- a/include/configs/km/keymile-common.h
+++ b/include/configs/km/keymile-common.h
@@ -21,7 +21,6 @@
 
 #undef	CONFIG_WATCHDOG		/* disable platform specific watchdog */
 
-#define CONFIG_BOOTDELAY	2 /* autoboot after 2 seconds */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 /*
diff --git a/include/configs/kwb.h b/include/configs/kwb.h
index bcb9e7e8be..2bddc6b7df 100644
--- a/include/configs/kwb.h
+++ b/include/configs/kwb.h
@@ -103,7 +103,6 @@ BUR_COMMON_ENV \
 
 #define CONFIG_BOOTCOMMAND \
 	"run usbscript;"
-#define CONFIG_BOOTDELAY		0
 
 /* undefine command which we not need here */
 #undef CONFIG_BOOTM_NETBSD
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 710629b6bd..1b4c7d4388 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -31,7 +31,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
-#define CONFIG_BOOTDELAY 3
 
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 1aad97d970..f52750e591 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -168,7 +168,6 @@
 #define CONFIG_SERIAL_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_SETUP_INITRD_TAG
-#define CONFIG_BOOTDELAY	0
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan; then " \
diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
new file mode 100644
index 0000000000..fba2facfbd
--- /dev/null
+++ b/include/configs/ls1012a_common.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define	CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE		0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ/4	/* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		1000000
+#define CONFIG_ENV_SPI_MODE		0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
+					"$kernel_start $kernel_size && "\
+					"bootm $kernel_load"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
new file mode 100644
index 0000000000..ad81142dcd
--- /dev/null
+++ b/include/configs/ls1012afrdm.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
new file mode 100644
index 0000000000..fcf402c836
--- /dev/null
+++ b/include/configs/ls1012aqds.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_BRDCFG_REG		0x04
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0xf7
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x08
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED      10000000
+#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS        1
+#define CONFIG_SF_DEFAULT_CS         0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
new file mode 100644
index 0000000000..6046ab7895
--- /dev/null
+++ b/include/configs/ls1012ardb.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR	0x24
+#define __SW_BOOT_MASK		0xFC
+#define __SW_BOOT_EMU		0x10
+#define __SW_BOOT_BANK1		0x00
+#define __SW_BOOT_BANK2		0x01
+#define __SW_REV_MASK		0x07
+#define __SW_REV_A		0xF8
+#define __SW_REV_B		0xF0
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index f605ca6280..db684d2558 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -450,8 +450,6 @@ unsigned long get_board_ddr_clk(void);
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #endif
@@ -569,7 +567,6 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_FSL_DEVICE_DISABLE
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_SYS_QE_FW_ADDR     0x600c0000
 
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 32d2acc0cd..0fb28eff55 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -57,8 +57,6 @@
 
 #ifdef CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 #endif
@@ -418,7 +416,6 @@
 
 #define CONFIG_FSL_DEVICE_DISABLE
 
-#define CONFIG_BOOTDELAY		3
 
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS       \
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 54968b5231..b0d4a8d10a 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -257,9 +257,13 @@
 
 #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
 					"earlycon=uart8250,mmio,0x21c0500"
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
+#define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+					"e0000 f00000 && bootm $kernel_load"
+#else
 #define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
 					"$kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY		10
+#endif
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h
index af1f73dbaa..a19eaee5a9 100644
--- a/include/configs/ls1043aqds.h
+++ b/include/configs/ls1043aqds.h
@@ -388,9 +388,7 @@ unsigned long get_board_ddr_clk(void);
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 6d35be2e47..94ddfb1797 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -253,6 +253,7 @@
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
@@ -277,14 +278,33 @@
 /* USB */
 #define CONFIG_HAS_FSL_XHCI_USB
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		3
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
 #endif
 
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_CMD_SCSI
+#ifndef CONFIG_CMD_FAT
+#define CONFIG_CMD_FAT
+#endif
+#ifndef CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT2
+#endif
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		2
+#define CONFIG_SYS_SCSI_MAX_LUN			2
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define SCSI_VEND_ID 0x1b4b
+#define SCSI_DEV_ID  0x9170
+#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
+#define CONFIG_PCI
+
 #include <asm/fsl_secure_boot.h>
 
 #endif /* __LS1043ARDB_H__ */
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index a3aad1b99d..2bf524f69a 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -26,6 +26,8 @@
 /* We need architecture specific misc initializations */
 #define CONFIG_ARCH_MISC_INIT
 
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+
 /* Link Definitions */
 #ifdef CONFIG_SPL
 #define CONFIG_SYS_TEXT_BASE		0x80400000
@@ -253,7 +255,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_BOOTCOMMAND	"fsl_mc apply dpl 0x580700000 &&" \
 				" cp.b $kernel_start $kernel_load" \
 				" $kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY		10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
@@ -292,4 +293,10 @@ unsigned long long get_qixis_addr(void);
 
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+#define CONFIG_CMD_HASH
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
 #endif /* __LS2_COMMON_H */
diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h
index f4ace856b8..16e37bff4f 100644
--- a/include/configs/ls2080a_emu.h
+++ b/include/configs/ls2080a_emu.h
@@ -10,7 +10,6 @@
 #include "ls2080a_common.h"
 
 #define CONFIG_IDENT_STRING		" LS2080A-EMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.LS2080A-EMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index bc0d678bf4..7563aafbc6 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -10,7 +10,6 @@
 #include "ls2080a_common.h"
 
 #define CONFIG_IDENT_STRING		" LS2080A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.LS2080A-SIMU"
 
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index f8c9e51ae7..b44066c407 100644
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -374,7 +374,7 @@ unsigned long get_board_ddr_clk(void);
 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 
 #define CONFIG_MII		/* MII PHY management */
-#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
 
 #endif
@@ -383,9 +383,7 @@ unsigned long get_board_ddr_clk(void);
  * USB
  */
 #define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT		2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 4577919ca1..86a49a5cd8 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -316,9 +316,7 @@ unsigned long get_board_sys_clk(void);
  * USB
  */
 #define CONFIG_HAS_FSL_XHCI_USB
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_FSL
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
@@ -366,7 +364,7 @@ unsigned long get_board_sys_clk(void);
 #define AQR405_IRQ_MASK		0x36
 
 #define CONFIG_MII
-#define CONFIG_ETHPRIME		"DPNI1"
+#define CONFIG_ETHPRIME		"DPMAC1@xgmii"
 #define CONFIG_PHY_GIGE
 #define CONFIG_PHY_AQUANTIA
 #endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index d5082fa4cc..0abfb00ef0 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -340,7 +340,6 @@
 	""
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 428128d297..e7fd6395e0 100644
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -130,7 +130,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_BOOTCOMMAND	"run mmc_mmc"
diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index 4349357b54..781a1623dd 100644
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -226,7 +226,6 @@
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttymxc1,115200"
 #define CONFIG_LOADADDR		0x70800000
diff --git a/include/configs/ma5d4evk.h b/include/configs/ma5d4evk.h
index fb144637d5..b4bd6b0e1e 100644
--- a/include/configs/ma5d4evk.h
+++ b/include/configs/ma5d4evk.h
@@ -128,7 +128,6 @@
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_INITRD_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS3,115200"
 #define CONFIG_LOADADDR		0x20800000
diff --git a/include/configs/malta.h b/include/configs/malta.h
index 04dca71036..fc4baba7d7 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -37,17 +37,20 @@
 /*
  * Memory map
  */
-#define CONFIG_SYS_TEXT_BASE		0xbe000000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_SDRAM_BASE		0x80000000 /* Cached addr */
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_SDRAM_BASE		0xffffffff80000000
+#else
+# define CONFIG_SYS_SDRAM_BASE		0x80000000
+#endif
 #define CONFIG_SYS_MEM_SIZE		(256 * 1024 * 1024)
 
 #define CONFIG_SYS_INIT_SP_OFFSET	0x400000
 
-#define CONFIG_SYS_LOAD_ADDR		0x81000000
-#define CONFIG_SYS_MEMTEST_START	0x80100000
-#define CONFIG_SYS_MEMTEST_END		0x80800000
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x00100000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x00800000)
 
 #define CONFIG_SYS_MALLOC_LEN		(128 * 1024)
 #define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
@@ -65,18 +68,16 @@
  * Serial driver
  */
 #define CONFIG_BAUDRATE			115200
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(115200 * 16)
-#define CONFIG_SYS_NS16550_COM1		0xb80003f8
-#define CONFIG_SYS_NS16550_COM2		0xbb0003f8
-#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_PORT_MAPPED
 
 /*
  * Flash configuration
  */
-#define CONFIG_SYS_FLASH_BASE		0xbe000000
+#ifdef CONFIG_64BIT
+# define CONFIG_SYS_FLASH_BASE		0xffffffffbe000000
+#else
+# define CONFIG_SYS_FLASH_BASE		0xbe000000
+#endif
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_MAX_FLASH_SECT	128
 #define CONFIG_SYS_FLASH_CFI
diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h
index 8d4a8cd0c2..937febea21 100644
--- a/include/configs/manroland/common.h
+++ b/include/configs/manroland/common.h
@@ -37,7 +37,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"echo;" \
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/mcx.h b/include/configs/mcx.h
index 3dbd9204af..0c6e1117d4 100644
--- a/include/configs/mcx.h
+++ b/include/configs/mcx.h
@@ -149,7 +149,6 @@
 #define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
 
 /* Environment information */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
index 9262f72085..4211e72dba 100644
--- a/include/configs/mecp5123.h
+++ b/include/configs/mecp5123.h
@@ -362,7 +362,6 @@
 
 #define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
 
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index f71b66245f..fbcad4ac80 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -69,7 +69,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 /*
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index 801d674610..93fb166665 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -239,7 +239,6 @@
 /* default load address */
 #define	CONFIG_SYS_LOAD_ADDR	0
 
-#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
 #define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 674d1f602b..95ad1287f6 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -40,6 +40,6 @@
 #define CONFIG_X86EMU_RAW_IO
 
 #define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_OFFSET		0x007fe000
+#define CONFIG_ENV_OFFSET		0x006ef000
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 62919e9cf9..2a83c608b1 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -63,7 +63,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds */
 #undef CONFIG_BOOTARGS
 
 #define CONFIG_CMDLINE_EDITING		1	/* add command line history	*/
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index e0c9a98de7..3cdd0dcf62 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -516,7 +516,6 @@
 
 #define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE		115200
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h
index 66e1a45e16..57cb7956a4 100644
--- a/include/configs/mpc8308_p1m.h
+++ b/include/configs/mpc8308_p1m.h
@@ -474,7 +474,6 @@
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h
index f983f2d1b5..27e9c0a8f3 100644
--- a/include/configs/ms7722se.h
+++ b/include/configs/ms7722se.h
@@ -16,7 +16,6 @@
 #define CONFIG_CMD_SDRAM
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200 root=1f01"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h
index 025a4a6698..c0fb16d095 100644
--- a/include/configs/ms7750se.h
+++ b/include/configs/ms7750se.h
@@ -23,7 +23,6 @@
 #define CONFIG_CONS_SCIF1	1
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	-1
 #define CONFIG_BOOTARGS		"console=ttySC0,38400"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h
index 3073db9ff8..29564d758b 100644
--- a/include/configs/mt_ventoux.h
+++ b/include/configs/mt_ventoux.h
@@ -22,7 +22,6 @@
 #define MACH_TYPE_AM3517_MT_VENTOUX	3832
 #define CONFIG_MACH_TYPE	MACH_TYPE_AM3517_MT_VENTOUX
 
-#define CONFIG_BOOTDELAY	10
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_AUTO_COMPLETE
 
diff --git a/include/configs/munices.h b/include/configs/munices.h
index efbd44779e..3e4c062dbf 100644
--- a/include/configs/munices.h
+++ b/include/configs/munices.h
@@ -41,7 +41,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 #define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-#define CONFIG_BOOTDELAY	5   /* autoboot after 5 seconds */
 #undef	CONFIG_BOOTARGS
 
 #define CONFIG_PREBOOT	"echo;"	\
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 6d4bbd1f9a..62f4937c66 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -57,7 +57,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
 					  115200,230400, 460800, 921600 }
 /* auto boot */
-#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
 #define CONFIG_PREBOOT
 
 /*
diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index 1bdbe4bba9..774725871a 100644
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -57,7 +57,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index 542f1f42b8..3f9bb0ab46 100644
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -56,7 +56,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index c63887bb8c..ea0d605fe3 100644
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -117,7 +117,6 @@
 
 /* Ethernet Configs */
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x81000000	/* loadaddr env var */
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index b3c03b3bb3..068596f397 100644
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -137,7 +137,6 @@
 #endif
 
 /* Boot Linux */
-#define CONFIG_BOOTDELAY	1
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_LOADADDR		0x42000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index b9992deaab..8de9dec66f 100644
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -64,7 +64,6 @@
  ***********************************************************/
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 3f63007819..a81dd784c9 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -84,7 +84,6 @@
 
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	1
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index aed0939ce6..1d1178798e 100644
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -91,7 +91,6 @@
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index 23b8b46d8c..93ad048b11 100644
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -120,7 +120,6 @@
 
 #define CONFIG_CMD_DATE
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index e697261248..0419050354 100644
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -70,7 +70,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"smc911x"
 
diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index feb5580239..5e1c5977ea 100644
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -77,7 +77,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 8743ddce68..1b580f04c7 100644
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -87,7 +87,6 @@
 /* Command definition */
 #define CONFIG_SUPPORT_RAW_INITRD
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 9c76678b1c..632ebba35c 100644
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -64,7 +64,6 @@
 #define CONFIG_BAUDRATE			115200
 
 /* Command definition */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ETHPRIME		"FEC0"
 
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 17b6c48c1c..27f38f497e 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -60,7 +60,6 @@
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
 #ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY	3
 #endif
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h
index 3c9a794f81..5e5656d480 100644
--- a/include/configs/mx7_common.h
+++ b/include/configs/mx7_common.h
@@ -35,7 +35,6 @@
 #define CONFIG_SYS_TEXT_BASE            0x87800000
 
 #ifndef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY                3
 #endif
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 0fbbce6d02..cd154a4bbb 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -379,7 +379,6 @@ int rx51_kp_getc(struct stdio_dev *sdev);
 	"run attachboot;" \
 	"echo"
 
-#define CONFIG_BOOTDELAY 30
 #define CONFIG_MENU
 #define CONFIG_MENU_SHOW
 
diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h
index 16fa046687..891378420e 100644
--- a/include/configs/o2dnt-common.h
+++ b/include/configs/o2dnt-common.h
@@ -90,7 +90,6 @@
 #error "CONFIG_SYS_TEXT_BASE value is invalid"
 #endif
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
 
 #define CONFIG_PREBOOT	"run master"
 
diff --git a/include/configs/odroid-c2.h b/include/configs/odroid-c2.h
new file mode 100644
index 0000000000..37a5671ccb
--- /dev/null
+++ b/include/configs/odroid-c2.h
@@ -0,0 +1,51 @@
+/*
+ * Configuration for ODROID-C2
+ * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_CPU_ARMV8
+#define CONFIG_REMAKE_ELF
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_IS_NOWHERE		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_SYS_TEXT_BASE		0x01000000
+#define CONFIG_SYS_INIT_SP_ADDR		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0xc4301000
+#define GICC_BASE			0xc4302000
+
+#define CONFIG_IDENT_STRING		" odroid-c2"
+
+/* Serial setup */
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_CMD_ENV
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+
+#include <config_distro_defaults.h>
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index 3f777b6aeb..96c3c4b958 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -74,8 +74,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
 /* override default CONFIG_BOOTDELAY */
-#undef CONFIG_BOOTDELAY
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"machid=ffffffff\0" \
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 9dbca1c6f4..1726a3ed19 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -106,7 +106,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h
index a93a2fa0d6..b7d8765db5 100644
--- a/include/configs/omap3_evm_quick_mmc.h
+++ b/include/configs/omap3_evm_quick_mmc.h
@@ -55,7 +55,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"verify=no\0"			\
diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h
index bb908fad3e..da5d32517d 100644
--- a/include/configs/omap3_evm_quick_nand.h
+++ b/include/configs/omap3_evm_quick_nand.h
@@ -45,7 +45,6 @@
  * Default environment
  * -----------------------------------------------------------------------------
  */
-#define CONFIG_BOOTDELAY	0
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"verify=no\0"			\
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index f3287e3ad3..1f36d36f45 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -204,7 +204,6 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		"console=ttyS2,115200n8 root=/dev/mmcblk0p2 rw rootwait ip=off"
 #define CONFIG_BOOTCOMMAND	"if mmc rescan 0; then if fatload mmc 0 0xc0600000 boot.scr; then source 0xc0600000; else fatload mmc 0 0xc0700000 uImage; bootm c0700000; fi; else sf probe 0; sf read 0xc0700000 0x80000 0x220000; bootm 0xc0700000; fi"
-#define CONFIG_BOOTDELAY	3
 
 /*
  * U-Boot commands
diff --git a/include/configs/openrisc-generic.h b/include/configs/openrisc-generic.h
index dfb8d3a389..913256a02b 100644
--- a/include/configs/openrisc-generic.h
+++ b/include/configs/openrisc-generic.h
@@ -10,7 +10,6 @@
 /*
  * BOARD/CPU
  */
-
 #define CONFIG_SYS_CLK_FREQ		50000000
 #define CONFIG_SYS_RESET_ADDR		0x00000100
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 71b2fa9c07..4f22d12a3f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -944,7 +944,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 9b75afe92a..30bfbf44f5 100644
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -468,7 +468,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR	1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #define CONFIG_BOOTARGS	/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h
new file mode 100644
index 0000000000..257283f3b9
--- /dev/null
+++ b/include/configs/p2771-0000.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _P2771_0000_H
+#define _P2771_0000_H
+
+#include <linux/sizes.h>
+
+#include "tegra186-common.h"
+
+/* High-level configuration options */
+#define CONFIG_TEGRA_BOARD_STRING	"NVIDIA P2771-0000"
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART		2
+#define CONFIG_ENV_OFFSET		(-CONFIG_ENV_SIZE)
+
+#include "tegra-common-post.h"
+
+/* Crystal is 38.4MHz. clk_m runs at half that rate */
+#define COUNTER_FREQUENCY	19200000
+
+#endif
diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index caf75a6b26..a649991d1a 100644
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -31,7 +31,6 @@
 #endif
 #endif
 
-#define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
 
 #define CONFIG_BAUDRATE		115200
 
@@ -80,12 +79,6 @@
 #define PHYS_FLASH_1		0xbec00000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0xbfc00000 /* Flash Bank #2 */
 
-/* The following #defines are needed to get flash environment right */
-/* ROM version */
-/* #define CONFIG_SYS_TEXT_BASE		0xbfc00000 */
-/* SDRAM version */
-#define CONFIG_SYS_TEXT_BASE		0x83800000
-
 #define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define	CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
@@ -150,12 +143,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
 
 /*
  * BOOTP options
diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h
index 0007c50ad9..80d5d6c858 100644
--- a/include/configs/pcm030.h
+++ b/include/configs/pcm030.h
@@ -70,7 +70,6 @@ Serial console configuration
 /*-----------------------------------------------------------------------------
 Autobooting
 -----------------------------------------------------------------------------*/
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
 					/* even with bootdelay=0 */
 #undef	CONFIG_BOOTARGS
diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h
index 494524d065..74e22db151 100644
--- a/include/configs/pcm052.h
+++ b/include/configs/pcm052.h
@@ -113,7 +113,6 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 #define CONFIG_SYS_I2C_EEPROM_BUS 2
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_LOADADDR			0x82000000
 
diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h
index 3b6c7dc111..6d03d6908e 100644
--- a/include/configs/pdm360ng.h
+++ b/include/configs/pdm360ng.h
@@ -448,7 +448,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		400000
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo PDM360NG SAMPLE;" \
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index 108c6a2d62..49c98d81c4 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -10,7 +10,6 @@
 #define __PIC32MZDASK_CONFIG_H
 
 /* System Configuration */
-#define CONFIG_SYS_TEXT_BASE		0x9d004000 /* .text */
 #define CONFIG_DISPLAY_BOARDINFO
 
 /*--------------------------------------------
@@ -101,7 +100,6 @@
  * USB Configuration
  */
 #define CONFIG_USB_MUSB_PIO_ONLY
-#define CONFIG_SYS_CACHELINE_SIZE	16
 
 /*-----------------------------------------------------------------------
  * File System Configuration
@@ -127,7 +125,6 @@
  * Board boot configuration
  */
 #define CONFIG_TIMESTAMP	/* Print image info with timestamp */
-#define CONFIG_BOOTDELAY	5
 
 #define MEM_LAYOUT_ENV_SETTINGS					\
 	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0"	\
diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h
index 44ffd6d204..7d7315ea1c 100644
--- a/include/configs/picosam9g45.h
+++ b/include/configs/picosam9g45.h
@@ -61,7 +61,6 @@
 #define CONFIG_AT91_LED
 #define CONFIG_GREEN_LED	AT91_PIN_PD31	/* this is the user1 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index 39af5c0240..0abd84a147 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -168,7 +168,6 @@
 #define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
 #define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 111e0f50cd..b8ce17e807 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -182,7 +182,6 @@
 #define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
 #define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index facba3864d..0e944d871f 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -57,7 +57,6 @@
 #define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
 #define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * BOOTP options
diff --git a/include/configs/pr1.h b/include/configs/pr1.h
index 9b394ddb13..6804acb0cd 100644
--- a/include/configs/pr1.h
+++ b/include/configs/pr1.h
@@ -119,7 +119,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 #define CONFIG_BOOTCOMMAND	"run nandboot"
-#define CONFIG_BOOTDELAY	2
 #define CONFIG_LOADADDR		0x2000000
 
 /*
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 7450a1a42a..990fd84b32 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -61,6 +61,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=pxm2\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x500000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
@@ -92,7 +93,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 	"if dfubutton; then " \
@@ -118,7 +118,6 @@
 	"reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 702967c4e8..546c508d27 100644
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -17,7 +17,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 
 #define CONFIG_BAUDRATE		115200
 
@@ -107,7 +106,6 @@
  * FLASH and environment organization
  */
 /* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE		0xbfc00000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
@@ -133,11 +131,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 239454984a..6cab719203 100644
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -17,7 +17,6 @@
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MISC_INIT_R
 
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
 
 #define CONFIG_BAUDRATE		115200
 
@@ -107,7 +106,6 @@
  * FLASH and environment organization
  */
 /* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_TEXT_BASE		0xffffffffbfc00000 /* Rom version */
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(192 << 10)
 
@@ -133,11 +131,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #endif /* __CONFIG_H */
diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h
index 73b377155c..0b8640223f 100644
--- a/include/configs/qemu-ppce500.h
+++ b/include/configs/qemu-ppce500.h
@@ -179,7 +179,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
 
 #define CONFIG_BAUDRATE	115200
 
-#define CONFIG_BOOTDELAY        1
 #define CONFIG_BOOTCOMMAND		\
 	"test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0"
 
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index 437ea92a98..c5e57244ab 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -22,7 +22,6 @@
 #define CONFIG_CMD_ENV
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC3,115200"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h
index bf81d2b0ee..1fc919b6eb 100644
--- a/include/configs/r2dplus.h
+++ b/include/configs/r2dplus.h
@@ -22,7 +22,6 @@
 #define CONFIG_CONS_SCIF1	1
 #define CONFIG_BOARD_LATE_INIT
 
-#define CONFIG_BOOTDELAY	-1
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h
index 6097dc2ca8..c15580c582 100644
--- a/include/configs/r7780mp.h
+++ b/include/configs/r7780mp.h
@@ -28,7 +28,6 @@
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_CONS_SCIF0	1
 
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_ENV_OVERWRITE	1
 
diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h
index 47d23791c0..55be46bcf2 100644
--- a/include/configs/rastaban.h
+++ b/include/configs/rastaban.h
@@ -76,6 +76,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rastaban\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
@@ -85,7 +86,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -97,7 +97,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 337ba02a63..80313fc8c5 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -31,7 +31,6 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_BAUDRATE		38400
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		""
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/redwood.h b/include/configs/redwood.h
index 622b7c79e6..72fbf108fa 100644
--- a/include/configs/redwood.h
+++ b/include/configs/redwood.h
@@ -132,7 +132,6 @@
 
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 #define	CONFIG_IBM_EMAC4_V4	1
 #define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h
index 8a81397290..9d50d834db 100644
--- a/include/configs/rk3288_common.h
+++ b/include/configs/rk3288_common.h
@@ -69,7 +69,6 @@
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
 
 #define CONFIG_SPL_PINCTRL_SUPPORT
-#define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_RAM_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index af58182e7b..dbbb81efa9 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -106,6 +106,7 @@
 #define CONFIG_USB_STORAGE
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
 #define CONFIG_MISC_INIT_R
 #define CONFIG_USB_KEYBOARD
 #define CONFIG_SYS_USB_EVENT_POLL
@@ -213,6 +214,5 @@
 	ENV_MEM_LAYOUT_SETTINGS \
 	BOOTENV
 
-#define CONFIG_BOOTDELAY 2
 
 #endif
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index c60e233e9f..3f9fb7bc02 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC3,115200"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP	1	/* undef to save memory	*/
diff --git a/include/configs/rsk7269.h b/include/configs/rsk7269.h
index b4fbc9c17d..b7f361be25 100644
--- a/include/configs/rsk7269.h
+++ b/include/configs/rsk7269.h
@@ -16,7 +16,6 @@
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTARGS		"console=ttySC7,115200"
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 #define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
diff --git a/include/configs/rut.h b/include/configs/rut.h
index bf2cc2f2bb..aea8e217d0 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -56,6 +56,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rut\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x500000\0" \
 	"splashpos=m,m\0" \
 	"optargs=fixrtc --no-log consoleblank=0 \0" \
@@ -85,7 +86,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 	"if mmc rescan; then " \
@@ -107,7 +107,6 @@
 	"reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h
index bdb368ed33..99153067b2 100644
--- a/include/configs/s5pc210_universal.h
+++ b/include/configs/s5pc210_universal.h
@@ -217,9 +217,6 @@ int universal_spi_read(void);
 /*
  * LCD Settings
  */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_LD9040
 #define CONFIG_VIDEO_BMP_GZIP
diff --git a/include/configs/sama5d2_ptc.h b/include/configs/sama5d2_ptc.h
new file mode 100644
index 0000000000..d91d75eb40
--- /dev/null
+++ b/include/configs/sama5d2_ptc.h
@@ -0,0 +1,155 @@
+/*
+ * Configuration settings for the SAMA5D2 PTC Engineering board.
+ *
+ * Copyright (C) 2016 Atmel
+ *		      Wenyou Yang <wenyou.yang@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* No NOR flash, this definition should put before common header */
+#define CONFIG_SYS_NO_FLASH
+
+#include "at91-sama5_common.h"
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_UART0
+#define CONFIG_USART_ID			ATMEL_ID_UART0
+
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x210000
+#else
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR		0x22000000 /* load address */
+
+#undef CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_PIO4
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+
+/* SerialFlash */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_ATMEL
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		30000000
+#endif
+
+/* NAND flash */
+#define CONFIG_CMD_NAND
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_CMD_NAND_TRIMFFS
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	3
+#define CONFIG_USB_STORAGE
+#endif
+
+/* USB device */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_ATMEL_USBA
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_MANUFACTURER      "Atmel SAMA5D2_PTC"
+
+#if defined(CONFIG_CMD_USB)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* Ethernet Hardware */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_MACB_SEARCH_PHY
+
+#ifdef CONFIG_SYS_USE_NANDFLASH
+#undef CONFIG_ENV_OFFSET
+#undef CONFIG_ENV_OFFSET_REDUND
+#undef CONFIG_BOOTCOMMAND
+/* u-boot env in nand flash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x200000
+#define CONFIG_ENV_OFFSET_REDUND	0x400000
+#define CONFIG_BOOTCOMMAND		"nand read 0x21000000 0xb80000 0x80000;"	\
+					"nand read 0x22000000 0x600000 0x600000;"	\
+					"bootz 0x22000000 - 0x21000000"
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,57600 earlyprintk "				\
+	"mtdparts=atmel_nand:6M(bootstrap)ro, 6M(kernel)ro,-(rootfs) "	\
+	"rootfstype=ubifs ubi.mtd=2 root=ubi0:rootfs"
+
+/* SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x200000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
+
+#ifdef CONFIG_SYS_USE_SERIALFLASH
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8000
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_PMECC_CAP		8
+#define CONFIG_PMECC_SECTOR_SIZE	512
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x1000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_OOBSIZE		224
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x40000
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
+#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
+#endif
+
+#endif
diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index 0c8ecc181b..d58b9637f1 100644
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -28,7 +28,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_LOADADDR		0x42000000
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 6c0932a8df..567c4d588b 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -641,7 +641,6 @@
 				/* default location for tftp and bootm */
 #define CONFIG_LOADADDR		800000
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 115200
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h
index bbd1a63344..46766a6779 100644
--- a/include/configs/sbc8548.h
+++ b/include/configs/sbc8548.h
@@ -579,7 +579,6 @@
 
 #define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs*/
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index c9970f1f3e..248785db38 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -527,7 +527,6 @@
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000
 
-#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	115200
diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 42237d373e..b490b62c2d 100644
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -52,7 +52,6 @@
 #endif
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200"
 #define CONFIG_BOOTCOMMAND	"bootm"
diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h
index 80997a49bd..fb6e05fafc 100644
--- a/include/configs/sh7752evb.h
+++ b/include/configs/sh7752evb.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h
index 248435b9d1..64e9e52e70 100644
--- a/include/configs/sh7753evb.h
+++ b/include/configs/sh7753evb.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h
index 547b500308..f9a9a03ef4 100644
--- a/include/configs/sh7757lcr.h
+++ b/include/configs/sh7757lcr.h
@@ -24,7 +24,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_VERSION_VARIABLE
diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h
index 9f1e6d7fee..538ba98ae5 100644
--- a/include/configs/sh7763rdp.h
+++ b/include/configs/sh7763rdp.h
@@ -20,7 +20,6 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_JFFS2
 
-#define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index bd4c6bd13a..794c48c49a 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -22,7 +22,6 @@
 #define CONFIG_MAC_PARTITION
 
 #define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC1,115200 root=/dev/nfs ip=dhcp"
 
 #define CONFIG_EXTRA_ENV_SETTINGS					\
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index dfc928d33b..5969541de6 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -159,6 +159,7 @@
 #define CONFIG_SPL_NAND_BASE
 #define CONFIG_SPL_NAND_DRIVERS
 #define CONFIG_SPL_NAND_ECC
+#define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
 					 CONFIG_SYS_NAND_PAGE_SIZE)
@@ -288,6 +289,8 @@
 #define CONFIG_LZO
 #define CONFIG_CMD_UBI
 #define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT      1
 #endif
 
 /* Commen environment */
@@ -419,7 +422,7 @@
 			"setenv nand_src_addr ${nand_src_addr_B};" \
 		"fi;" \
 		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
-		"ubi.mtd=9,2048;" \
+		"ubi.mtd=9,${ubi_off};" \
 		"setenv bootargs ${bootargs} " \
 		"root=${nand_root} noinitrd ${mtdparts} " \
 		"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
@@ -511,7 +514,7 @@
 	COMMON_ENV_DFU_ARGS \
 		"dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \
 	COMMON_ENV_NAND_BOOT \
-		"ubi part rootfs 2048;" \
+		"ubi part rootfs ${ubi_off};" \
 		"ubifsmount ubi0:${nand_active_ubi_vol};" \
 		"ubifsload ${kloadaddr} boot/${kernel_name};" \
 		"ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 40b0cd2132..fc4153aba8 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -178,7 +178,6 @@
 #endif
 
 /* General Boot Parameter */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTCOMMAND		"run flashboot"
 #define CONFIG_SYS_CBSIZE		512
 #define CONFIG_SYS_PBSIZE \
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index c5c0c2cb96..f733c35024 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -80,7 +80,6 @@
 #define CONFIG_CMDLINE_EDITING
 
 /* autoboot */
-#define CONFIG_BOOTDELAY	5
 #define CONFIG_BOOT_RETRY_TIME	-1
 #define CONFIG_RESET_TO_RETRY
 #define CONFIG_ZERO_BOOTDELAY_CHECK
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index f66bb121f3..92a08332a3 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -13,6 +13,9 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON
diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h
index 9cf886c066..a46ca74166 100644
--- a/include/configs/smdk5420.h
+++ b/include/configs/smdk5420.h
@@ -13,6 +13,10 @@
 #include <configs/exynos5-dt-common.h>
 #include <configs/exynos5-common.h>
 
+#undef CONFIG_LCD
+#undef CONFIG_EXYNOS_FB
+#undef CONFIG_EXYNOS_DP
+
 #undef CONFIG_KEYBOARD
 
 #define CONFIG_BOARD_COMMON
@@ -31,7 +35,6 @@
 #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
 
 /* USB */
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_XHCI_EXYNOS
 
 /* DRAM Memory Banks */
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index 0f1a1ecc29..fe41d17149 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -71,7 +71,6 @@
 #define CONFIG_CMD_ONENAND
 #define CONFIG_CMD_MTDPARTS
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 16aefc25b4..7981a8d80b 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -117,7 +117,6 @@
 
 /* Boot options */
 #define CONFIG_SYS_LOAD_ADDR		0x23000000
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
 #define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h
index ca7f8a28b2..3b0b41612d 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index f6577668a1..1f8b7b3b80 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -324,9 +324,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MALLOC_SIMPLE
-#endif
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
@@ -349,9 +346,9 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #else
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	3
-#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0xa00 /* offset 2560 sect (1M+256k) */
-#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	800 /* 400 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x200 /* offset 512 sect (256k) */
+#define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 #endif
 
diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h
index a2da7d47c5..7ced6a68a6 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h
index fdddfa3cd2..6b9546e8f7 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h
index f0fb43a82f..d1b31c4cfa 100644
--- a/include/configs/socfpga_mcvevk.h
+++ b/include/configs/socfpga_mcvevk.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on MCV */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_PREBOOT		"run try_bootscript"
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 675f5d16e9..3fceb31df9 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"fitImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h
index 79c16ce91d..c9473df912 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -18,7 +18,6 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCrates */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index efa9e428ce..286e746a14 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -20,9 +20,8 @@
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
new file mode 100644
index 0000000000..1c7d45e4a8
--- /dev/null
+++ b/include/configs/socfpga_vining_fpga.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SAMTEC_VINING_FPGA_H__
+#define __CONFIG_SAMTEC_VINING_FPGA_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_LED
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on VINING_FPGA */
+
+/* Booting Linux */
+#define CONFIG_BOOTFILE		"openwrt-socfpga-socfpga_cyclone5_vining_fpga-fit-uImage.itb"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND	"run selboot"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_I2C_EEPROM_BUS		0
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	70
+#endif
+
+/*
+ * Status LEDs:
+ *   0 ... Top Green
+ *   1 ... Top Red
+ *   2 ... Bottom Green
+ *   3 ... Bottom Red
+ */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT		48
+#define STATUS_LED_STATE	STATUS_LED_OFF
+#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT1		53
+#define STATUS_LED_STATE1	STATUS_LED_OFF
+#define STATUS_LED_PERIOD1	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT2		54
+#define STATUS_LED_STATE2	STATUS_LED_OFF
+#define STATUS_LED_PERIOD2	(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BIT3		65
+#define STATUS_LED_STATE3	STATUS_LED_OFF
+#define STATUS_LED_PERIOD3	(CONFIG_SYS_HZ / 2)
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME			socfpga_vining_fpga
+
+/*
+ * Active LOW GPIO buttons:
+ * A: GPIO 77 ... the button between USB B and ethernet
+ * B: GPIO 78 ... the button between USB A ports
+ *
+ * The logic:
+ *  if button B is not pressed, boot normal Linux system immediatelly
+ *  if button B is pressed, wait $bootdelay and boot recovery system
+ */
+#define CONFIG_PREBOOT						\
+	"setenv hostname vining-${unit_serial} ; "		\
+	"setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; "	\
+	"if gpio input 78 ; then "			\
+		"setenv bootdelay 10 ; "		\
+		"setenv boottype rcvr ; "		\
+	"else "						\
+		"setenv bootdelay 5 ; "			\
+		"setenv boottype norm ; "		\
+	"fi"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"consdev=ttyS0\0"						\
+	"baudrate=115200\0"						\
+	"bootscript=boot.scr\0"						\
+	"ubimtdnr=5\0"							\
+	"ubimtd=rootfs\0"						\
+	"ubipart=ubi0:rootfs\0"						\
+	"ubisfcs=1\0"		/* Default is flash at CS#1 */		\
+	"netdev=eth0\0"							\
+	"hostname=vining_fpga\0"						\
+	"kernel_addr_r=0x10000000\0"					\
+	"mtdparts_0=ff705000.spi.0:"					\
+		"1m(u-boot),"						\
+		"64k(env1),"						\
+		"64k(env2),"						\
+		"256k(samtec1),"					\
+		"256k(samtec2),"					\
+		"-(rcvrfs)\0"	/* Recovery */				\
+	"mtdparts_1=ff705000.spi.1:"					\
+		"32m(rootfs),"						\
+		"-(userfs)\0"						\
+	"update_filename=u-boot-with-spl-dtb.sfp\0"			\
+	"update_qspi_offset=0x0\0"					\
+	"update_qspi="		/* Update the QSPI firmware */		\
+		"if sf probe ; then "					\
+		"if tftp ${update_filename} ; then "			\
+		"sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \
+		"fi ; "							\
+		"fi\0"							\
+	"fpga_filename=output_file.rbf\0"				\
+	"load_fpga="		/* Load FPGA bitstream */		\
+		"if tftp ${fpga_filename} ; then "			\
+		"fpga load 0 $loadaddr $filesize ; "			\
+		"bridge enable ; "					\
+		"fi\0"							\
+	"addcons="							\
+		"setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"addip="							\
+		"setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
+			"${netmask}:${hostname}:${netdev}:off\0"	\
+	"addmisc="							\
+		"setenv bootargs ${bootargs} ${miscargs}\0"		\
+	"addmtd="							\
+		"setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; "	\
+		"setenv bootargs ${bootargs} mtdparts=${mtdparts}\0"	\
+	"addargs=run addcons addmtd addmisc\0"				\
+	"ubiload="							\
+		"ubi part ${ubimtd} ; ubifsmount ${ubipart} ; "		\
+		"ubifsload ${kernel_addr_r} /boot/${bootfile}\0"	\
+	"netload="							\
+		"tftp ${kernel_addr_r} ${hostname}/${bootfile}\0"	\
+	"miscargs=nohlt panic=1\0"					\
+	"ubiargs="							\
+		"setenv bootargs ubi.mtd=${ubimtdnr} "			\
+		"root=${ubipart} rootfstype=ubifs\0"			\
+	"nfsargs="							\
+		"setenv bootargs root=/dev/nfs rw "			\
+			"nfsroot=${serverip}:${rootpath},v3,tcp\0"	\
+	"ubi_sfsel="							\
+		"if test \"${boottype}\" = \"rcvr\" ; then "		\
+			"setenv ubisfcs 0 ; "				\
+			"setenv ubimtd rcvrfs ; "			\
+			"setenv ubimtdnr 5 ; "				\
+			"setenv mtdparts mtdparts=${mtdparts_0} ; "	\
+			"setenv mtdids nor0=ff705000.spi.0 ; "		\
+			"setenv ubipart ubi0:rootfs ; "			\
+		"else "							\
+			"setenv ubisfcs 1 ; "				\
+			"setenv ubimtd rootfs ; "			\
+			"setenv ubimtdnr 6 ; "				\
+			"setenv mtdparts mtdparts=${mtdparts_1} ; "	\
+			"setenv mtdids nor0=ff705000.spi.1 ; "		\
+			"setenv ubipart ubi0:rootfs ; "			\
+		"fi ; "							\
+		"sf probe 0:${ubisfcs}\0"				\
+	"ubi_ubi="							\
+		"run ubi_sfsel ubiload ubiargs addargs ; "		\
+		"bootm ${kernel_addr_r}\0"				\
+	"ubi_nfs="							\
+		"run ubiload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_ubi="							\
+		"run netload ubiargs addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"net_nfs="							\
+		"run netload nfsargs addip addargs ; "			\
+		"bootm ${kernel_addr_r}\0"				\
+	"selboot="	/* Select from where to boot. */		\
+		"if test \"${bootmode}\" = \"qspi\" ; then "		\
+			"led all off ; "				\
+			"if test \"${boottype}\" = \"rcvr\" ; then "	\
+				"echo \"Booting recovery system\" ; "	\
+				"led 3 on ; "	/* Bottom RED */	\
+			"fi ; "						\
+			"led 1 on ; "		/* Top RED */		\
+			"run ubi_ubi ; "				\
+		"else echo \"Unsupported boot mode: \"${bootmode} ; "	\
+		"fi\0"							\
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define MTDPARTS_DEFAULT			\
+	"mtdparts=ff705000.spi.0:"		\
+		"1m(u-boot),"			\
+		"64k(env1),"			\
+		"64k(env2),"			\
+		"256k(samtec1),"		\
+		"256k(samtec2),"		\
+		"-(rcvrfs);"	/* Recovery */	\
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_LATE_INIT
+
+/* Enable DFU to SF and RAM */
+#define CONFIG_DFU_RAM
+#define CONFIG_DFU_SF
+
+/* Support changing the prompt string */
+#define CONFIG_CMDLINE_PS_SUPPORT
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SAMTEC_VINING_FPGA_H__ */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 4ed524b023..624cef712d 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -346,7 +346,6 @@
 
 #define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
 
-#define CONFIG_BOOTDELAY 1		/* -1 disables auto-boot	*/
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Welcome on the ABB Socrates Board;" \
diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h
index 7b2d262b4b..43ba84ab58 100644
--- a/include/configs/spear-common.h
+++ b/include/configs/spear-common.h
@@ -104,12 +104,6 @@
 /*
  * Default Environment Varible definitions
  */
-#if defined(CONFIG_SPEAR_USBTTY)
-#define CONFIG_BOOTDELAY			-1
-#else
-#define CONFIG_BOOTDELAY			1
-#endif
-
 #define CONFIG_ENV_OVERWRITE
 
 /*
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h
index d53f8c18a2..8bbe580ebf 100644
--- a/include/configs/stm32f429-discovery.h
+++ b/include/configs/stm32f429-discovery.h
@@ -82,7 +82,6 @@
 	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
 	"bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_AUTOBOOT
 
 /*
diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h
index 9d1f02ea15..e544a218dd 100644
--- a/include/configs/stm32f746-disco.h
+++ b/include/configs/stm32f746-disco.h
@@ -69,7 +69,6 @@
 	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
 	"bootm 0x08044000 - 0x08042000\0"
 
-#define CONFIG_BOOTDELAY		3
 
 /*
  * Command line configuration.
diff --git a/include/configs/strider.h b/include/configs/strider.h
index 5803b660bc..36561e0346 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -20,8 +20,12 @@
 
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
 
-#ifdef CONFIG_STRIDER_CPU
+#ifdef CONFIG_STRIDER_CPU_DP
+#define CONFIG_IDENT_STRING	" strider cpu dp 0.01"
+#elif defined(CONFIG_STRIDER_CPU)
 #define CONFIG_IDENT_STRING	" strider cpu 0.01"
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_IDENT_STRING	" strider con dp 0.01"
 #else
 #define CONFIG_IDENT_STRING	" strider con 0.01"
 #endif
@@ -225,15 +229,11 @@
 /*
  * FLASH on the Local Bus
  */
-#if 1
 #define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
 #define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
 #define CONFIG_FLASH_CFI_LEGACY
 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
-#else
-#define CONFIG_SYS_NO_FLASH
-#endif
 
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
@@ -341,6 +341,22 @@
 #define CONFIG_SYS_I2C_IHS_SPEED_3		50000
 #define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
 
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
+#endif
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -357,7 +373,7 @@
 #define I2C_SOFT_DECLARATIONS4
 #define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
-#ifdef CONFIG_STRIDER_CON
+#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
 #define I2C_SOFT_DECLARATIONS5
 #define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
@@ -371,6 +387,20 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
 #endif
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_SOFT_DECLARATIONS9
+#define CONFIG_SYS_I2C_SOFT_SPEED_9		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_9		0x7F
+#define I2C_SOFT_DECLARATIONS10
+#define CONFIG_SYS_I2C_SOFT_SPEED_10		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_10		0x7F
+#define I2C_SOFT_DECLARATIONS11
+#define CONFIG_SYS_I2C_SOFT_SPEED_11		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_11		0x7F
+#define I2C_SOFT_DECLARATIONS12
+#define CONFIG_SYS_I2C_SOFT_SPEED_12		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_12		0x7F
+#endif
 
 #ifdef CONFIG_STRIDER_CON
 #define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
@@ -379,6 +409,19 @@
 #define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
 #define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
 						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define CONFIG_SYS_ICS8N3QV01_I2C		{13, 14, 15, 16, 17, 18, 19, 20}
+#define CONFIG_SYS_CH7301_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_ADV7611_I2C			{1, 3, 5, 7}
+#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
+#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
+						  {12, 0x4c} }
+#elif defined(CONFIG_STRIDER_CPU_DP)
+#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#define CONFIG_STRIDER_FANS			{ {6, 0x4c}, {7, 0x4c}, \
+						  {8, 0x4c} }
 #else
 #define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
 #define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
@@ -391,6 +434,8 @@
 void fpga_gpio_set(unsigned int bus, int pin);
 void fpga_gpio_clear(unsigned int bus, int pin);
 int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
 #endif
 
 #ifdef CONFIG_STRIDER_CON
@@ -398,12 +443,28 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
 #define I2C_FPGA_IDX	((I2C_ADAP_HWNR > 3) ? \
 			 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
+#elif defined(CONFIG_STRIDER_CON_DP)
+#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
+#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
+#define I2C_FPGA_IDX	(I2C_ADAP_HWNR % 4)
 #else
 #define I2C_SDA_GPIO	0x0040
 #define I2C_SCL_GPIO	0x0020
 #define I2C_FPGA_IDX	I2C_ADAP_HWNR
 #endif
+
+#ifdef CONFIG_STRIDER_CON_DP
+#define I2C_ACTIVE \
+	do { \
+		if (I2C_ADAP_HWNR > 7) \
+			fpga_control_set(I2C_FPGA_IDX, 0x0004); \
+		else \
+			fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
+	} while (0)
+#else
 #define I2C_ACTIVE	{ }
+#endif
+
 #define I2C_TRISTATE	{ }
 #define I2C_READ \
 	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
@@ -436,6 +497,10 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_DP501_DIFFERENTIAL
 #define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
 
+#ifdef CONFIG_STRIDER_CON_DP
+#define CONFIG_SYS_OSD_DH
+#endif
+
 /*
  * General PCI
  * Addresses are mapped 1-1.
@@ -594,7 +659,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
 
 #define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 
 #define CONFIG_HOSTNAME		hrcon
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h
index d3704a4e2c..bfd1bd7192 100644
--- a/include/configs/stv0991.h
+++ b/include/configs/stv0991.h
@@ -66,7 +66,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CMDLINE_EDITING
 
-#define CONFIG_BOOTDELAY                       3
 #define CONFIG_BOOTCOMMAND                     "go 0x40040000"
 
 /*
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index ac2d93114b..b33cfb86f8 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -189,14 +189,14 @@
 #define CONFIG_SPL_BOARD_LOAD_IMAGE
 
 #if defined(CONFIG_MACH_SUN9I)
-#define CONFIG_SPL_TEXT_BASE		0x10020		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* ? KiB on sun9i */
+#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* ? KiB on sun9i */
 #elif defined(CONFIG_MACH_SUN50I)
-#define CONFIG_SPL_TEXT_BASE		0x10020		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x7fe0		/* 32 KiB on sun50i */
+#define CONFIG_SPL_TEXT_BASE		0x10040		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x7fc0		/* 32 KiB on sun50i */
 #else
-#define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
-#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
+#define CONFIG_SPL_TEXT_BASE		0x40		/* sram start+header */
+#define CONFIG_SPL_MAX_SIZE		0x5fc0		/* 24KB on sun4i/sun7i */
 #endif
 
 #define CONFIG_SPL_LIBDISK_SUPPORT
@@ -390,6 +390,23 @@ extern int soft_i2c_gpio_scl;
 #define CONFIG_PRE_CONSOLE_BUFFER
 #define CONFIG_PRE_CON_BUF_SZ		4096 /* Aprox 2 80*25 screens */
 
+#ifdef CONFIG_ARM64
+/*
+ * Boards seem to come with at least 512MB of DRAM.
+ * The kernel should go at 512K, which is the default text offset (that will
+ * be adjusted at runtime if needed).
+ * There is no compression for arm64 kernels (yet), so leave some space
+ * for really big kernels, say 256MB for now.
+ * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd.
+ * Align the initrd to a 2MB page.
+ */
+#define KERNEL_ADDR_R	__stringify(SDRAM_OFFSET(0080000))
+#define FDT_ADDR_R	__stringify(SDRAM_OFFSET(FA00000))
+#define SCRIPT_ADDR_R	__stringify(SDRAM_OFFSET(FC00000))
+#define PXEFILE_ADDR_R	__stringify(SDRAM_OFFSET(FD00000))
+#define RAMDISK_ADDR_R	__stringify(SDRAM_OFFSET(FE00000))
+
+#else
 /*
  * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc.
  * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
@@ -401,6 +418,7 @@ extern int soft_i2c_gpio_scl;
 #define SCRIPT_ADDR_R  __stringify(SDRAM_OFFSET(3100000))
 #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000))
 #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000))
+#endif
 
 #define MEM_LAYOUT_ENV_SETTINGS \
 	"bootm_size=0xa000000\0" \
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 4d66dd2407..6616d7396e 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -128,7 +128,6 @@
 							/* devices */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
 /* Environment information */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 321fb4756d..0b05289d07 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -60,7 +60,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY	3
 
 /*
  * Command line configuration.
diff --git a/include/configs/tb100.h b/include/configs/tb100.h
index 870406b208..39bb5b35da 100644
--- a/include/configs/tb100.h
+++ b/include/configs/tb100.h
@@ -79,7 +79,6 @@
 /*
  * Environment configuration
  */
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS0,115200n8"
 #define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index 92d4dd8e51..7b0940a7f2 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -111,7 +111,6 @@
 						CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_TEGRA_GPIO
 #define CONFIG_CMD_ENTERRCM
 
 /* Defines for SPL */
diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
new file mode 100644
index 0000000000..aa7b9d038a
--- /dev/null
+++ b/include/configs/tegra186-common.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2013-2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _TEGRA186_COMMON_H_
+#define _TEGRA186_COMMON_H_
+
+#include "tegra-common.h"
+
+/* Cortex-A57 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_STACKBASE	0x82800000	/* 40MB */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+
+#define CONFIG_SYS_TEXT_BASE	0x80080000
+
+/* Generic Interrupt Controller */
+#define CONFIG_GICV2
+
+/*
+ * Memory layout for where various images get loaded by boot scripts:
+ *
+ * scriptaddr can be pretty much anywhere that doesn't conflict with something
+ *   else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
+ * kernel_addr_r must be within the first 128M of RAM in order for the
+ *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
+ *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
+ *   should not overlap that area, or the kernel will have to copy itself
+ *   somewhere else before decompression. Similarly, the address of any other
+ *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
+ *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   compressed load address.
+ *
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
+ *   the compressed kernel to be up to 16M too.
+ *
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
+ */
+#define CONFIG_LOADADDR 0x80080000
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"scriptaddr=0x90000000\0" \
+	"pxefile_addr_r=0x90100000\0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"fdt_addr_r=0x82000000\0" \
+	"ramdisk_addr_r=0x82100000\0"
+
+/* Defines for SPL */
+#define CONFIG_SPL_TEXT_BASE		0x80108000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
+#define CONFIG_SPL_STACK		0x800ffffc
+
+#endif
diff --git a/include/configs/thuban.h b/include/configs/thuban.h
index 5fed55da1c..25ac2cba4b 100644
--- a/include/configs/thuban.h
+++ b/include/configs/thuban.h
@@ -69,6 +69,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=thuban\0" \
+	"ubi_off=2048\0"\
 	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	"preboot=draco_led 0\0" \
@@ -78,7 +79,6 @@
 
 #ifndef CONFIG_RESTORE_FLASH
 /* set to negative value for no autoboot */
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTCOMMAND \
 "if dfubutton; then " \
@@ -90,7 +90,6 @@
 "reset;"
 
 #else
-#define CONFIG_BOOTDELAY		0
 
 #define CONFIG_BOOTCOMMAND			\
 	"setenv autoload no; "			\
diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h
index 7c35d8cd46..5c3b3da73c 100644
--- a/include/configs/thunderx_88xx.h
+++ b/include/configs/thunderx_88xx.h
@@ -17,7 +17,6 @@
 
 #define CONFIG_IDENT_STRING	\
 	" for Cavium Thunder CN88XX ARM v8 Multi-Core"
-#define CONFIG_BOOTP_VCI_STRING		"Diagnostics"
 
 #define MEM_BASE			0x00500000
 
@@ -62,7 +61,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(MEM_BASE)
@@ -86,7 +84,6 @@
 					"earlycon=pl011,0x87e024000000 " \
 					"debug maxcpus=48 rootwait rw "\
 					"root=/dev/sda2 coherent_pool=16M"
-#define CONFIG_BOOTDELAY		5
 
 /* Do not preserve environment */
 #define CONFIG_ENV_IS_NOWHERE		1
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 09f8e8fe5c..3c058832e1 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -39,7 +39,6 @@
 /* commands to include */
 #define CONFIG_VERSION_VARIABLE
 
-#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
 #define CONFIG_ENV_VARS_UBOOT_CONFIG
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h
index 2e84dd27e4..05fd00fd5d 100644
--- a/include/configs/ti816x_evm.h
+++ b/include/configs/ti816x_evm.h
@@ -34,7 +34,6 @@
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_BOOTDELAY		3 /* set negative for no autoboot */
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"loadaddr=0x81000000\0"		\
 
diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h
index 7db08813e4..ba7cf15242 100644
--- a/include/configs/ti_armv7_common.h
+++ b/include/configs/ti_armv7_common.h
@@ -59,7 +59,7 @@
 #define DEFAULT_MMC_TI_ARGS \
 	"mmcdev=0\0" \
 	"mmcrootfstype=ext4 rootwait\0" \
-	"finduuid=part uuid mmc 0:2 uuid\0" \
+	"finduuid=part uuid mmc ${bootpart} uuid\0" \
 	"args_mmc=run finduuid;setenv bootargs console=${console} " \
 		"${optargs} " \
 		"root=PARTUUID=${uuid} rw " \
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h
index 2c9028c735..707106ffab 100644
--- a/include/configs/ti_armv7_keystone2.h
+++ b/include/configs/ti_armv7_keystone2.h
@@ -191,8 +191,6 @@
 					"-(ubifs)"
 
 /* USB Configuration */
-#define CONFIG_USB_XHCI
-#define CONFIG_USB_XHCI_DWC3
 #define CONFIG_USB_XHCI_KEYSTONE
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h
index b049be49ee..5c5a12d493 100644
--- a/include/configs/ti_omap5_common.h
+++ b/include/configs/ti_omap5_common.h
@@ -130,13 +130,35 @@
 
 /*
  * SPL related defines.  The Public RAM memory map the ROM defines the
- * area between 0x40300000 and 0x4031E000 as a download area for OMAP5
- * (dra7xx is larger, but we do not need to be larger at this time).  We
- * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
+ * area between 0x40300000 and 0x4031E000 as a download area for OMAP5.
+ * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000.
+ * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
  * print some information.
  */
-#define CONFIG_SPL_TEXT_BASE		0x40300000
-#define CONFIG_SPL_MAX_SIZE		(0x4031E000 - CONFIG_SPL_TEXT_BASE)
+#ifdef CONFIG_TI_SECURE_DEVICE
+/*
+ * For memory booting on HS parts, the first 4KB of the internal RAM is
+ * reserved for secure world use and the flash loader image is
+ * preceded by a secure certificate. The SPL will therefore run in internal
+ * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)).
+ */
+#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ	0x1000
+#define CONFIG_SPL_TEXT_BASE	0x40301350
+#else
+/*
+ * For all booting on GP parts, the flash loader image is
+ * downloaded into internal RAM at address 0x40300000.
+ */
+#define CONFIG_SPL_TEXT_BASE	0x40300000
+#endif
+
+/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+#define TI_ROM_BOOT_LOAD_END		0x4037E000
+#else
+#define TI_ROM_BOOT_LOAD_END		0x4031E000
+#endif
+#define CONFIG_SPL_MAX_SIZE     (TI_ROM_BOOT_LOAD_END - CONFIG_SPL_TEXT_BASE)
 #define CONFIG_SPL_DISPLAY_PRINT
 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
 #define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
@@ -153,6 +175,7 @@
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_DM_MMC
 #undef CONFIG_TIMER
+#undef CONFIG_DM_ETH
 #endif
 
 #endif /* __CONFIG_TI_OMAP5_COMMON_H */
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 2b9e92ed2b..74a9a098a0 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -7,8 +7,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_TEXT_BASE		0xa1000000
-
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -17,11 +15,6 @@
 #define CONFIG_SYS_MHZ			280
 #define CONFIG_SYS_MIPS_TIMER_FREQ	(CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		0x8000
-#define CONFIG_SYS_ICACHE_SIZE		0x10000
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN		0x40000
@@ -46,7 +39,6 @@
 #define CONFIG_SYS_BAUDRATE_TABLE \
 	{9600, 19200, 38400, 57600, 115200}
 
-#define CONFIG_BOOTDELAY		3
 #define CONFIG_BOOTARGS			\
 	"console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
 #define CONFIG_BOOTCOMMAND		\
@@ -85,8 +77,6 @@
 #define CONFIG_SYS_MEMTEST_END		0x83f00000
 #define CONFIG_CMD_MEMTEST
 
-#define CONFIG_USE_PRIVATE_LIBGCC
-
 #define CONFIG_CMD_MII
 #define CONFIG_PHY_GIGE
 
diff --git a/include/configs/trats.h b/include/configs/trats.h
index 0c875cb47f..22b0c90ee9 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -242,12 +242,8 @@
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 492a253d73..1febaaef51 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -222,12 +222,8 @@ int get_soft_i2c_sda_pin(void);
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 /* LCD */
-#define CONFIG_EXYNOS_FB
-#define CONFIG_LCD
-#define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
 #define CONFIG_FB_ADDR		0x52504000
-#define CONFIG_S6E8AX0
 #define CONFIG_EXYNOS_MIPI_DSIM
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 855d789c18..aed3931515 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -162,7 +162,6 @@
 
 /* Environment information (this is the common part) */
 
-#define CONFIG_BOOTDELAY		0
 
 /* hang() the board on panic() */
 #define CONFIG_PANIC_HANG
diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h
index 0db5ab55ef..252b3fc706 100644
--- a/include/configs/ts4800.h
+++ b/include/configs/ts4800.h
@@ -92,7 +92,6 @@
 
 /* Environment variables */
 
-#define CONFIG_BOOTDELAY	1
 
 #define CONFIG_LOADADDR		0x91000000	/* loadaddr env var */
 
diff --git a/include/configs/tseries.h b/include/configs/tseries.h
index b6a1ae0554..8ed9eb080d 100644
--- a/include/configs/tseries.h
+++ b/include/configs/tseries.h
@@ -195,7 +195,6 @@ MMCARGS
 
 #define CONFIG_BOOTCOMMAND \
 	"run defboot;"
-#define CONFIG_BOOTDELAY		0
 
 #ifdef CONFIG_NAND
 /*
diff --git a/include/configs/twister.h b/include/configs/twister.h
index 4f5560fec3..66f4680b7e 100644
--- a/include/configs/twister.h
+++ b/include/configs/twister.h
@@ -20,7 +20,6 @@
 #define CONFIG_TAM3517_SW3_SETTINGS
 #define CONFIG_XR16L2751
 
-#define CONFIG_BOOTDELAY	10
 
 #define CONFIG_BOOTFILE		"uImage"
 
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 18cb963844..9d14c2d59c 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -104,7 +104,11 @@
 #define COUNTER_FREQUENCY			50000000
 #define CONFIG_GICV3
 #define GICD_BASE				0x5fe00000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define GICR_BASE				0x5fe40000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define GICR_BASE				0x5fe80000
+#endif
 #else
 /* Time clock 1MHz */
 #define CONFIG_SYS_TIMER_RATE			1000000
@@ -144,7 +148,6 @@
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x01000000)
 
-#define CONFIG_BOOTDELAY			3
 #define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
 
 /*
@@ -241,7 +244,6 @@
 		"tftpboot $tmp_addr u-boot.bin\0"		\
 	"emmcupdate=mmcsetn &&"					\
 		"mmc partconf $mmc_first_dev 0 1 1 &&"		\
-		"mmc erase 0 800 &&"				\
 		"tftpboot u-boot-spl.bin &&"			\
 		"mmc write $loadaddr 0 80 &&"			\
 		"tftpboot u-boot.bin &&"			\
@@ -270,7 +272,9 @@
 #define CONFIG_SPL_TEXT_BASE		0x00100000
 #endif
 
-#if defined(CONFIG_ARCH_UNIPHIER_LD20)
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_STACK		(0x30014c00)
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define CONFIG_SPL_STACK		(0x3001c000)
 #else
 #define CONFIG_SPL_STACK		(0x00100000)
@@ -282,7 +286,9 @@
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NOR_SUPPORT
-#ifndef CONFIG_ARM64
+#ifdef CONFIG_ARM64
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+#else
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_MMC_SUPPORT
 #endif
@@ -301,7 +307,11 @@
 #define CONFIG_SPL_TARGET			"u-boot-with-spl.bin"
 #define CONFIG_SPL_MAX_FOOTPRINT		0x10000
 #define CONFIG_SPL_MAX_SIZE			0x10000
+#if defined(CONFIG_ARCH_UNIPHIER_LD11)
+#define CONFIG_SPL_BSS_START_ADDR		0x30012000
+#elif defined(CONFIG_ARCH_UNIPHIER_LD20)
 #define CONFIG_SPL_BSS_START_ADDR		0x30016000
+#endif
 #define CONFIG_SPL_BSS_MAX_SIZE			0x2000
 
 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index d118928ebd..ad54192194 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -46,7 +46,6 @@
 #define CONFIG_USART_ID			ATMEL_ID_SYS
 #define CONFIG_BAUDRATE			115200
 
-#define CONFIG_BOOTDELAY 3
 
 /*
  * BOOTP options
diff --git a/include/configs/v38b.h b/include/configs/v38b.h
index 9a113f4e32..28c748d074 100644
--- a/include/configs/v38b.h
+++ b/include/configs/v38b.h
@@ -102,7 +102,6 @@
 /*
  * Autobooting
  */
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
 
 #define CONFIG_PREBOOT	"echo;"	\
 	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
diff --git a/include/configs/vct.h b/include/configs/vct.h
index 6489e08173..2bc98a8e8a 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -32,7 +32,6 @@
 
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* SDRAM is initialized by the bootstrap code */
 
-#define CONFIG_SYS_TEXT_BASE		0x87000000
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(1 << 20)
@@ -205,13 +204,6 @@
 #endif /* CONFIG_VCT_ONENAND */
 
 /*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE		16384
-#define CONFIG_SYS_ICACHE_SIZE		16384
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
-/*
  * I2C/EEPROM
  */
 #define CONFIG_SYS_I2C
@@ -248,7 +240,6 @@ int vct_gpio_get(int pin);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 
 #define CONFIG_BOOTCOMMAND	"run test3"
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
 
 /*
  * UBI configuration
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
index 2425ebf669..83d0004f53 100644
--- a/include/configs/ve8313.h
+++ b/include/configs/ve8313.h
@@ -465,7 +465,6 @@
 #define CONFIG_HOSTNAME		ve8313
 #define CONFIG_UBOOTPATH	ve8313/u-boot.bin
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h
index 1b5fc2ee82..46cf83be02 100644
--- a/include/configs/vexpress_aemv8a.h
+++ b/include/configs/vexpress_aemv8a.h
@@ -23,7 +23,6 @@
 #define CONFIG_SYS_CACHELINE_SIZE	64
 
 #define CONFIG_IDENT_STRING		" vexpress_aemv8a"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.armv8.vexpress_aemv8a"
 
 /* Link Definitions */
 #if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \
@@ -146,7 +145,6 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_PXE
-#define CONFIG_BOOTP_PXE_CLIENTARCH	0x100
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x10000000)
@@ -218,7 +216,6 @@
 				"fi ; " \
 				"booti ${kernel_addr} ${initrd_param} ${fdt_addr}"
 
-#define CONFIG_BOOTDELAY		1
 
 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
 #define CONFIG_EXTRA_ENV_SETTINGS	\
@@ -243,7 +240,6 @@
 				"fdt chosen ${initrd_addr} ${initrd_end}; " \
 				"booti $kernel_addr - $fdt_addr"
 
-#define CONFIG_BOOTDELAY		1
 
 #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM
 #define CONFIG_EXTRA_ENV_SETTINGS	\
@@ -262,7 +258,6 @@
 
 #define CONFIG_BOOTCOMMAND	"booti $kernel_addr $initrd_addr $fdt_addr"
 
-#define CONFIG_BOOTDELAY		1
 
 #endif
 
diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h
index 883e58e660..b509a9cfd4 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA15X2_TC2_h
 
 #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca15x2_tc2"
 #include "vexpress_common.h"
 
 #define CONFIG_SYSFLAGS_ADDR	0x1c010030
diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h
index 43850272a6..20b92dc888 100644
--- a/include/configs/vexpress_ca5x2.h
+++ b/include/configs/vexpress_ca5x2.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA5X2_h
 
 #define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca5x2"
 #include "vexpress_common.h"
 
 #endif /* __VEXPRESS_CA5X2_h */
diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h
index 99be50a5bd..993398ccc6 100644
--- a/include/configs/vexpress_ca9x4.h
+++ b/include/configs/vexpress_ca9x4.h
@@ -12,7 +12,6 @@
 #define __VEXPRESS_CA9X4_H
 
 #define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
-#define CONFIG_BOOTP_VCI_STRING     "U-Boot.armv7.vexpress_ca9x4"
 #include "vexpress_common.h"
 
 #endif /* VEXPRESS_CA9X4_H */
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 6dc8f25b90..51898e623c 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -168,7 +168,6 @@
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR		(V2M_BASE + 0x8000)
 #define LINUX_BOOT_PARAM_ADDR		(V2M_BASE + 0x2000)
-#define CONFIG_BOOTDELAY		2
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		2
diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index b240613bb5..c4a1fd091a 100644
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -103,7 +103,6 @@
 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
 #define CONFIG_SYS_SPD_BUS_NUM		0
 
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_SYS_LOAD_ADDR		0x82000000
 
diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h
index 732d091583..60513df032 100644
--- a/include/configs/vme8349.h
+++ b/include/configs/vme8349.h
@@ -542,7 +542,6 @@
 
 #define CONFIG_LOADADDR		800000	/* def location for tftp and bootm */
 
-#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
 
 #define CONFIG_BAUDRATE	 9600
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 4dfcd28eaf..f112fa5f16 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -9,7 +9,6 @@
 #ifndef __WARP7_CONFIG_H
 #define __WARP7_CONFIG_H
 
-#define CONFIG_BOOTDELAY                1
 #include "mx7_common.h"
 
 #define PHYS_SDRAM_SIZE			SZ_512M
diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index a4ae304ade..153466a623 100644
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -97,7 +97,6 @@
 
 #define CONFIG_NET_RETRY_COUNT	100
 
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h
index b81b6ff1fa..ba222f936f 100644
--- a/include/configs/work_92105.h
+++ b/include/configs/work_92105.h
@@ -175,7 +175,6 @@
 #define CONFIG_INITRD_TAG
 
 #define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTDELAY		3
 
 #define CONFIG_BOOTFILE			"uImage"
 #define CONFIG_BOOTARGS			"console=ttyS2,115200n8"
diff --git a/include/configs/x600.h b/include/configs/x600.h
index 5fdd2bee04..71c0b45842 100644
--- a/include/configs/x600.h
+++ b/include/configs/x600.h
@@ -80,6 +80,8 @@
 #define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
 #define CONFIG_PHY_ADDR		0	/* PHY address */
 #define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
 
 #define CONFIG_SPEAR_GPIO
 
@@ -122,7 +124,6 @@
 #define CONFIG_SUPPORT_VFAT
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_BOOTDELAY			3
 
 /*
  * U-Boot Environment placing definitions.
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index b79f47baf3..fdefeaf24c 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -193,14 +193,19 @@
 #define CONFIG_HOSTNAME		x86
 #define CONFIG_BOOTFILE		"bzImage"
 #define CONFIG_LOADADDR		0x1000000
-#define CONFIG_RAMDISK_ADDR		0x4000000
+#define CONFIG_RAMDISK_ADDR	0x4000000
+#ifdef CONFIG_GENERATE_ACPI_TABLE
+#define CONFIG_OTHBOOTARGS	"othbootargs=\0"
+#else
+#define CONFIG_OTHBOOTARGS	"othbootargs=acpi=off\0"
+#endif
 
 #define CONFIG_EXTRA_ENV_SETTINGS			\
 	CONFIG_STD_DEVICES_SETTINGS			\
 	"pciconfighost=1\0"				\
 	"netdev=eth0\0"					\
 	"consoledev=ttyS0\0"				\
-	"othbootargs=acpi=off\0"			\
+	CONFIG_OTHBOOTARGS				\
 	"ramdiskaddr=0x4000000\0"			\
 	"ramdiskfile=initramfs.gz\0"
 
@@ -220,6 +225,5 @@
 	"tftpboot $loadaddr $bootfile;"			\
 	"zboot $loadaddr"
 
-#define CONFIG_BOOTDELAY	2
 
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 4d68c21ae0..69558fdfd2 100644
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -28,7 +28,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_BOOTARGS		"console=ttyAMA0,115200n8 "
 #define CONFIG_LOADADDR		0x42000000
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index 067cfa69f2..e97e9d0816 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -33,7 +33,6 @@
 #undef CONFIG_CMD_EEPROM
 
 /*Misc*/
-#define CONFIG_BOOTDELAY		5/* autoboot after 5 seconds     */
 #define CONFIG_SYS_LONGHELP		/* undef to save memory         */
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE		1024/* Console I/O Buffer Size      */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 6b8e3ea865..e776e32412 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -41,7 +41,7 @@
 # define CONFIG_IDENT_STRING		" Xilinx ZynqMP"
 #endif
 
-#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR		0xfffffffc
 
 /* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
 #if !defined(COUNTER_FREQUENCY)
@@ -65,6 +65,9 @@
 #define CONFIG_CMD_ENV
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_ISO_PARTITION
+#endif
 #define CONFIG_MP
 
 /* BOOTP options */
@@ -73,11 +76,23 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 #define CONFIG_BOOTP_MAY_FAIL
-#define CONFIG_BOOTP_SERVERIP
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_PXE
+#define CONFIG_BOOTP_SUBNETMASK
+
+/* Diff from config_distro_defaults.h */
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_AUTO_COMPLETE
+
+/* PXE */
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
 
 #if defined(CONFIG_ZYNQ_SDHCI)
 # define CONFIG_MMC
 # define CONFIG_GENERIC_MMC
+# define CONFIG_SUPPORT_EMMC_BOOT
 # define CONFIG_SDHCI
 # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ
 #  define CONFIG_ZYNQ_SDHCI_MAX_FREQ	200000000
@@ -89,7 +104,6 @@
 #endif
 
 #ifdef CONFIG_NAND_ARASAN
-# define CONFIG_CMD_NAND
 # define CONFIG_CMD_NAND_LOCK_UNLOCK
 # define CONFIG_SYS_MAX_NAND_DEVICE	1
 # define CONFIG_SYS_NAND_SELF_INIT
@@ -101,8 +115,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x8000000
 
 #if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_USB_XHCI_DWC3
-#define CONFIG_USB_XHCI
 #define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 #define CONFIG_USB_STORAGE
@@ -132,21 +144,6 @@
 # define DFU_ALT_INFO
 #endif
 
-/* Initial environment variables */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"kernel_addr=0x80000\0" \
-	"fdt_addr=0x7000000\0" \
-	"fdt_high=0x10000000\0" \
-	CONFIG_KERNEL_FDT_OFST_SIZE \
-	"sdbootdev=0\0"\
-	"sdboot=mmc dev $sdbootdev && mmcinfo && load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
-		"load mmc $sdbootdev:$partid $kernel_addr Image && " \
-		"booti $kernel_addr - $fdt_addr\0" \
-	DFU_ALT_INFO
-
-#define CONFIG_PREBOOT		"run bootargs"
-#define CONFIG_BOOTCOMMAND	"run $modeboot"
-#define CONFIG_BOOTDELAY	3
 
 #define CONFIG_BOARD_LATE_INIT
 
@@ -173,6 +170,8 @@
 # define CONFIG_PHY_NATSEMI
 # define CONFIG_PHY_TI
 # define CONFIG_PHY_GIGE
+# define CONFIG_PHY_VITESSE
+# define CONFIG_PHY_REALTEK
 # define PHY_ANEG_TIMEOUT       20000
 #endif
 
@@ -193,7 +192,8 @@
 # define CONFIG_SYS_EEPROM_SIZE			(64 * 1024)
 #endif
 
-#ifdef CONFIG_AHCI
+#ifdef CONFIG_SATA_CEVA
+#define CONFIG_AHCI
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
@@ -212,4 +212,85 @@
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_CLOCKS
 
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"fdt_high=10000000\0" \
+	"initrd_high=10000000\0" \
+	"fdt_addr_r=0x40000000\0" \
+	"pxefile_addr_r=0x10000000\0" \
+	"kernel_addr_r=0x18000000\0" \
+	"scriptaddr=0x02000000\0" \
+	"ramdisk_addr_r=0x02100000\0" \
+
+#if defined(CONFIG_ZYNQ_SDHCI)
+# define BOOT_TARGET_DEVICES_MMC(func)	func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+# define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#if defined(CONFIG_SATA_CEVA)
+# define BOOT_TARGET_DEVICES_SCSI(func)	func(SCSI, scsi, 0)
+#else
+# define BOOT_TARGET_DEVICES_SCSI(func)
+#endif
+
+#if defined(CONFIG_ZYNQMP_USB)
+# define BOOT_TARGET_DEVICES_USB(func)	func(USB, usb, 0) func(USB, usb, 1)
+#else
+# define BOOT_TARGET_DEVICES_USB(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func) \
+	BOOT_TARGET_DEVICES_USB(func) \
+	BOOT_TARGET_DEVICES_SCSI(func) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	ENV_MEM_LAYOUT_SETTINGS \
+	BOOTENV \
+	DFU_ALT_INFO
+#endif
+
+#define CONFIG_SPL_TEXT_BASE		0xfffc0000
+#define CONFIG_SPL_MAX_SIZE		0x20000
+
+/* Just random location in OCM */
+#define CONFIG_SPL_BSS_START_ADDR	0x1000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x2000000
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_RAM_DEVICE
+
+#define CONFIG_SPL_OS_BOOT
+/* u-boot is like dtb */
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"u-boot.bin"
+#define CONFIG_SYS_SPL_ARGS_ADDR	0x8000000
+
+/* ATF is my kernel image */
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"atf.ub"
+
+/* FIT load address for RAM boot */
+#define CONFIG_SPL_LOAD_FIT_ADDRESS	0x10000000
+
+/* MMC support */
+#ifdef CONFIG_ZYNQ_SDHCI
+# define CONFIG_SPL_MMC_SUPPORT
+# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	0 /* unused */
+# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR	0 /* unused */
+# define CONFIG_SPL_LIBDISK_SUPPORT
+# define CONFIG_SPL_FAT_SUPPORT
+# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"
+#endif
+
 #endif /* __XILINX_ZYNQMP_H */
diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h
index 9506355713..c5bd5da43c 100644
--- a/include/configs/xilinx_zynqmp_ep.h
+++ b/include/configs/xilinx_zynqmp_ep.h
@@ -22,13 +22,6 @@
 
 #define COUNTER_FREQUENCY	4000000
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=ep108\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_EP_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
index 3c0ba883db..c9f443207d 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm015_dc1.h
@@ -17,13 +17,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm015 dc1"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc1\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM015_DC1_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
index 83ea624c51..526d0bbe58 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm016_dc2.h
@@ -14,13 +14,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm016 dc2"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc2\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
new file mode 100644
index 0000000000..65277a64c3
--- /dev/null
+++ b/include/configs/xilinx_zynqmp_zc1751_xm018_dc4.h
@@ -0,0 +1,17 @@
+/*
+ * Configuration for Xilinx ZynqMP zc1751 XM018 DC4
+ *
+ * (C) Copyright 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+#define __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H
+
+#define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm018 dc4"
+
+#include <configs/xilinx_zynqmp.h>
+
+#endif /* __CONFIG_ZYNQMP_ZC1751_XM018_DC4_H */
diff --git a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
index 4f8f5c1053..76350d9579 100644
--- a/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
+++ b/include/configs/xilinx_zynqmp_zc1751_xm019_dc5.h
@@ -15,13 +15,6 @@
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZC1751 xm019 dc5"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x400000\0" \
-	"fdt_offset=0x2400000\0" \
-	"kernel_size=0x2000000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zc1751-dc5\0"
-
 #include <configs/xilinx_zynqmp.h>
 
 #endif /* __CONFIG_ZYNQMP_ZC1751_XM019_DC5_H */
diff --git a/include/configs/xilinx_zynqmp_zcu102.h b/include/configs/xilinx_zynqmp_zcu102.h
index 30db2e4532..7ceab3230b 100644
--- a/include/configs/xilinx_zynqmp_zcu102.h
+++ b/include/configs/xilinx_zynqmp_zcu102.h
@@ -41,19 +41,17 @@
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 
-#define CONFIG_AHCI
 #define CONFIG_SATA_CEVA
 
 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
 
 #define CONFIG_IDENT_STRING	" Xilinx ZynqMP ZCU102"
 
-#define CONFIG_KERNEL_FDT_OFST_SIZE \
-	"kernel_offset=0x180000\0" \
-	"fdt_offset=0x100000\0" \
-	"kernel_size=0x1e00000\0" \
-	"fdt_size=0x80000\0" \
-	"board=zcu102\0"
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_CMD_EEPROM
+#define CONFIG_ZYNQ_EEPROM_BUS		5
+#define CONFIG_ZYNQ_GEM_EEPROM_ADDR	0x54
+#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET	0x20
 
 #include <configs/xilinx_zynqmp.h>
 
diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h
index 9838fbfa2e..73c8d5b6fd 100644
--- a/include/configs/xpedite1000.h
+++ b/include/configs/xpedite1000.h
@@ -196,7 +196,6 @@ extern void out32(unsigned int, unsigned long);
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h
index 86c9b4c41f..9f3158d056 100644
--- a/include/configs/xpedite517x.h
+++ b/include/configs/xpedite517x.h
@@ -536,7 +536,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
 #define CONFIG_CMDLINE_EDITING	1		/* Command-line editing */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h
index d1847ac2e8..a418fc5c9e 100644
--- a/include/configs/xpedite520x.h
+++ b/include/configs/xpedite520x.h
@@ -319,7 +319,6 @@
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 6a06b0ab1c..36df6682b2 100644
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -391,7 +391,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 5b377e35ee..1794ba10a3 100644
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -375,7 +375,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMDLINE_EDITING	1		/* add command line history	*/
 #define CONFIG_AUTO_COMPLETE	1		/* add autocompletion support */
 #define CONFIG_LOADADDR		0x1000000	/* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY	3		/* -1 disables auto-boot */
 #define CONFIG_PANIC_HANG			/* do not reset board on panic */
 #define CONFIG_PREBOOT				/* enable preboot variable */
 #define CONFIG_INTEGRITY			/* support booting INTEGRITY OS */
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index fcd7772642..6e83cc9180 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -40,7 +40,6 @@
 #define	CONFIG_BOOTARGS							\
 	"console=tty0 console=ttyS2,115200 fbcon=rotate:3"
 #define	CONFIG_TIMESTAMP
-#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
 #define	CONFIG_CMDLINE_TAG
 #define	CONFIG_SETUP_MEMORY_TAGS
 #define	CONFIG_SYS_TEXT_BASE		0x0
diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 264bb63c06..ea1ead23b7 100644
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -137,7 +137,6 @@
 
 #define CONFIG_PREBOOT  ""
 
-#define CONFIG_BOOTDELAY	5
 
 /*
  * Size of malloc() pool
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index a3e4aecb57..8dbac8728f 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -236,7 +236,6 @@
 #endif
 
 #define CONFIG_BOOTCOMMAND		"run $modeboot"
-#define CONFIG_BOOTDELAY		3 /* -1 to Disable autoboot */
 #define CONFIG_SYS_LOAD_ADDR		0 /* default? */
 
 /* Miscellaneous configurable options */
@@ -315,11 +314,7 @@
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #define CONFIG_SPL_FAT_SUPPORT
-#ifdef CONFIG_OF_SEPARATE
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot-dtb.img"
-#else
-# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
-#endif
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME     "u-boot.img"
 #endif
 
 /* Disable dcache for SPL just for sure */
diff --git a/include/cpsw.h b/include/cpsw.h
index cf1d30bfdc..257d12a08d 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -21,6 +21,7 @@ struct cpsw_slave_data {
 	u32		sliver_reg_ofs;
 	int		phy_addr;
 	int		phy_if;
+	int		phy_of_handle;
 };
 
 enum {
@@ -51,5 +52,6 @@ struct cpsw_platform_data {
 };
 
 int cpsw_register(struct cpsw_platform_data *data);
+int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
 
 #endif /* _CPSW_H_  */
diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h
index b348ad5231..0bf8707493 100644
--- a/include/dm/device-internal.h
+++ b/include/dm/device-internal.h
@@ -39,6 +39,30 @@ int device_bind(struct udevice *parent, const struct driver *drv,
 		struct udevice **devp);
 
 /**
+ * device_bind_with_driver_data() - Create a device and bind it to a driver
+ *
+ * Called to set up a new device attached to a driver, in the case where the
+ * driver was matched to the device by means of a match table that provides
+ * driver_data.
+ *
+ * Once bound a device exists but is not yet active until device_probe() is
+ * called.
+ *
+ * @parent: Pointer to device's parent, under which this driver will exist
+ * @drv: Device's driver
+ * @name: Name of device (e.g. device tree node name)
+ * @driver_data: The driver_data field from the driver's match table.
+ * @of_offset: Offset of device tree node for this device. This is -1 for
+ * devices which don't use device tree.
+ * @devp: if non-NULL, returns a pointer to the bound device
+ * @return 0 if OK, -ve on error
+ */
+int device_bind_with_driver_data(struct udevice *parent,
+				 const struct driver *drv, const char *name,
+				 ulong driver_data, int of_offset,
+				 struct udevice **devp);
+
+/**
  * device_bind_by_name: Create a device and bind it to a driver
  *
  * This is a helper function used to bind devices which do not use device
diff --git a/include/dm/device.h b/include/dm/device.h
index e9a8ec72c9..f03bcd3b49 100644
--- a/include/dm/device.h
+++ b/include/dm/device.h
@@ -548,6 +548,29 @@ int device_set_name(struct udevice *dev, const char *name);
 void device_set_name_alloced(struct udevice *dev);
 
 /**
+ * of_device_is_compatible() - check if the device is compatible with the compat
+ *
+ * This allows to check whether the device is comaptible with the compat.
+ *
+ * @dev:	udevice pointer for which compatible needs to be verified.
+ * @compat:	Compatible string which needs to verified in the given
+ *		device
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_device_is_compatible(struct udevice *dev, const char *compat);
+
+/**
+ * of_machine_is_compatible() - check if the machine is compatible with
+ *				the compat
+ *
+ * This allows to check whether the machine is comaptible with the compat.
+ *
+ * @compat:	Compatible string which needs to verified
+ * @return true if OK, false if the compatible is not found
+ */
+bool of_machine_is_compatible(const char *compat);
+
+/**
  * device_is_on_pci_bus - Test if a device is on a PCI bus
  *
  * @dev:	device to test
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a5cf6e201c..0777cbe27e 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -44,6 +44,7 @@ enum uclass_id {
 	UCLASS_KEYBOARD,	/* Keyboard input device */
 	UCLASS_LED,		/* Light-emitting diode (LED) */
 	UCLASS_LPC,		/* x86 'low pin count' interface */
+	UCLASS_MAILBOX,		/* Mailbox controller */
 	UCLASS_MASS_STORAGE,	/* Mass storage device */
 	UCLASS_MISC,		/* Miscellaneous device */
 	UCLASS_MMC,		/* SD / MMC card or chip */
@@ -61,7 +62,6 @@ enum uclass_id {
 	UCLASS_PWM,		/* Pulse-width modulator */
 	UCLASS_PWRSEQ,		/* Power sequence device */
 	UCLASS_REGULATOR,	/* Regulator device */
-	UCLASS_RESET,		/* Reset device */
 	UCLASS_REMOTEPROC,	/* Remote Processor device */
 	UCLASS_RTC,		/* Real time clock device */
 	UCLASS_SERIAL,		/* Serial UART */
@@ -70,6 +70,7 @@ enum uclass_id {
 	UCLASS_SPI_FLASH,	/* SPI flash */
 	UCLASS_SPI_GENERIC,	/* Generic SPI flash target */
 	UCLASS_SYSCON,		/* System configuration device */
+	UCLASS_SYSRESET,	/* System reset device */
 	UCLASS_THERMAL,		/* Thermal sensor */
 	UCLASS_TIMER,		/* Timer device */
 	UCLASS_TPM,		/* Trusted Platform Module TIS interface */
diff --git a/include/dt-bindings/clock/exynos7420-clk.h b/include/dt-bindings/clock/exynos7420-clk.h
new file mode 100644
index 0000000000..10c5586110
--- /dev/null
+++ b/include/dt-bindings/clock/exynos7420-clk.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
+#define _DT_BINDINGS_CLOCK_EXYNOS7_H
+
+/* TOPC */
+#define DOUT_ACLK_PERIS			1
+#define DOUT_SCLK_BUS0_PLL		2
+#define DOUT_SCLK_BUS1_PLL		3
+#define DOUT_SCLK_CC_PLL		4
+#define DOUT_SCLK_MFC_PLL		5
+#define DOUT_ACLK_CCORE_133		6
+#define DOUT_ACLK_MSCL_532		7
+#define ACLK_MSCL_532			8
+#define DOUT_SCLK_AUD_PLL		9
+#define FOUT_AUD_PLL			10
+#define SCLK_AUD_PLL			11
+#define SCLK_MFC_PLL_B			12
+#define SCLK_MFC_PLL_A			13
+#define SCLK_BUS1_PLL_B			14
+#define SCLK_BUS1_PLL_A			15
+#define SCLK_BUS0_PLL_B			16
+#define SCLK_BUS0_PLL_A			17
+#define SCLK_CC_PLL_B			18
+#define SCLK_CC_PLL_A			19
+#define ACLK_CCORE_133			20
+#define ACLK_PERIS_66			21
+#define TOPC_NR_CLK			22
+
+/* TOP0 */
+#define DOUT_ACLK_PERIC1		1
+#define DOUT_ACLK_PERIC0		2
+#define CLK_SCLK_UART0			3
+#define CLK_SCLK_UART1			4
+#define CLK_SCLK_UART2			5
+#define CLK_SCLK_UART3			6
+#define CLK_SCLK_SPI0			7
+#define CLK_SCLK_SPI1			8
+#define CLK_SCLK_SPI2			9
+#define CLK_SCLK_SPI3			10
+#define CLK_SCLK_SPI4			11
+#define CLK_SCLK_SPDIF			12
+#define CLK_SCLK_PCM1			13
+#define CLK_SCLK_I2S1			14
+#define CLK_ACLK_PERIC0_66		15
+#define CLK_ACLK_PERIC1_66		16
+#define TOP0_NR_CLK			17
+
+/* TOP1 */
+#define DOUT_ACLK_FSYS1_200		1
+#define DOUT_ACLK_FSYS0_200		2
+#define DOUT_SCLK_MMC2			3
+#define DOUT_SCLK_MMC1			4
+#define DOUT_SCLK_MMC0			5
+#define CLK_SCLK_MMC2			6
+#define CLK_SCLK_MMC1			7
+#define CLK_SCLK_MMC0			8
+#define CLK_ACLK_FSYS0_200		9
+#define CLK_ACLK_FSYS1_200		10
+#define CLK_SCLK_PHY_FSYS1		11
+#define CLK_SCLK_PHY_FSYS1_26M		12
+#define MOUT_SCLK_UFSUNIPRO20		13
+#define DOUT_SCLK_UFSUNIPRO20		14
+#define CLK_SCLK_UFSUNIPRO20		15
+#define DOUT_SCLK_PHY_FSYS1		16
+#define DOUT_SCLK_PHY_FSYS1_26M		17
+#define TOP1_NR_CLK			18
+
+/* CCORE */
+#define PCLK_RTC			1
+#define CCORE_NR_CLK			2
+
+/* PERIC0 */
+#define PCLK_UART0			1
+#define SCLK_UART0			2
+#define PCLK_HSI2C0			3
+#define PCLK_HSI2C1			4
+#define PCLK_HSI2C4			5
+#define PCLK_HSI2C5			6
+#define PCLK_HSI2C9			7
+#define PCLK_HSI2C10			8
+#define PCLK_HSI2C11			9
+#define PCLK_PWM			10
+#define SCLK_PWM			11
+#define PCLK_ADCIF			12
+#define PERIC0_NR_CLK			13
+
+/* PERIC1 */
+#define PCLK_UART1			1
+#define PCLK_UART2			2
+#define PCLK_UART3			3
+#define SCLK_UART1			4
+#define SCLK_UART2			5
+#define SCLK_UART3			6
+#define PCLK_HSI2C2			7
+#define PCLK_HSI2C3			8
+#define PCLK_HSI2C6			9
+#define PCLK_HSI2C7			10
+#define PCLK_HSI2C8			11
+#define PCLK_SPI0			12
+#define PCLK_SPI1			13
+#define PCLK_SPI2			14
+#define PCLK_SPI3			15
+#define PCLK_SPI4			16
+#define SCLK_SPI0			17
+#define SCLK_SPI1			18
+#define SCLK_SPI2			19
+#define SCLK_SPI3			20
+#define SCLK_SPI4			21
+#define PCLK_I2S1			22
+#define PCLK_PCM1			23
+#define PCLK_SPDIF			24
+#define SCLK_I2S1			25
+#define SCLK_PCM1			26
+#define SCLK_SPDIF			27
+#define PERIC1_NR_CLK			28
+
+/* PERIS */
+#define PCLK_CHIPID			1
+#define SCLK_CHIPID			2
+#define PCLK_WDT			3
+#define PCLK_TMU			4
+#define SCLK_TMU			5
+#define PERIS_NR_CLK			6
+
+/* FSYS0 */
+#define ACLK_MMC2			1
+#define ACLK_AXIUS_USBDRD30X_FSYS0X	2
+#define ACLK_USBDRD300			3
+#define SCLK_USBDRD300_SUSPENDCLK	4
+#define SCLK_USBDRD300_REFCLK		5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER		6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER		7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY		8
+#define ACLK_PDMA0			9
+#define ACLK_PDMA1			10
+#define FSYS0_NR_CLK			11
+
+/* FSYS1 */
+#define ACLK_MMC1			1
+#define ACLK_MMC0			2
+#define PHYCLK_UFS20_TX0_SYMBOL		3
+#define PHYCLK_UFS20_RX0_SYMBOL		4
+#define PHYCLK_UFS20_RX1_SYMBOL		5
+#define ACLK_UFS20_LINK			6
+#define SCLK_UFSUNIPRO20_USER		7
+#define PHYCLK_UFS20_RX1_SYMBOL_USER	8
+#define PHYCLK_UFS20_RX0_SYMBOL_USER	9
+#define PHYCLK_UFS20_TX0_SYMBOL_USER	10
+#define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY	11
+#define SCLK_COMBO_PHY_EMBEDDED_26M	12
+#define DOUT_PCLK_FSYS1			13
+#define PCLK_GPIO_FSYS1			14
+#define MOUT_FSYS1_PHYCLK_SEL1		15
+#define FSYS1_NR_CLK			16
+
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532		1
+#define DOUT_PCLK_MSCL			2
+#define ACLK_MSCL_0			3
+#define ACLK_MSCL_1			4
+#define ACLK_JPEG			5
+#define ACLK_G2D			6
+#define ACLK_LH_ASYNC_SI_MSCL_0		7
+#define ACLK_LH_ASYNC_SI_MSCL_1		8
+#define ACLK_AXI2ACEL_BRIDGE		9
+#define ACLK_XIU_MSCLX_0		10
+#define ACLK_XIU_MSCLX_1		11
+#define ACLK_QE_MSCL_0			12
+#define ACLK_QE_MSCL_1			13
+#define ACLK_QE_JPEG			14
+#define ACLK_QE_G2D			15
+#define ACLK_PPMU_MSCL_0		16
+#define ACLK_PPMU_MSCL_1		17
+#define ACLK_MSCLNP_133			18
+#define ACLK_AHB2APB_MSCL0P		19
+#define ACLK_AHB2APB_MSCL1P		20
+
+#define PCLK_MSCL_0			21
+#define PCLK_MSCL_1			22
+#define PCLK_JPEG			23
+#define PCLK_G2D			24
+#define PCLK_QE_MSCL_0			25
+#define PCLK_QE_MSCL_1			26
+#define PCLK_QE_JPEG			27
+#define PCLK_QE_G2D			28
+#define PCLK_PPMU_MSCL_0		29
+#define PCLK_PPMU_MSCL_1		30
+#define PCLK_AXI2ACEL_BRIDGE		31
+#define PCLK_PMU_MSCL			32
+#define MSCL_NR_CLK			33
+
+/* AUD */
+#define SCLK_I2S			1
+#define SCLK_PCM			2
+#define PCLK_I2S			3
+#define PCLK_PCM			4
+#define ACLK_ADMA			5
+#define AUD_NR_CLK			6
+#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h
new file mode 100644
index 0000000000..997312edcb
--- /dev/null
+++ b/include/dt-bindings/clock/maxim,max77802.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants clocks for the Maxim 77802 PMIC.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H
+
+/* Fixed rate clocks. */
+
+#define MAX77802_CLK_32K_AP		0
+#define MAX77802_CLK_32K_CP		1
+
+/* Total number of clocks. */
+#define MAX77802_CLKS_NUM		(MAX77802_CLK_32K_CP + 1)
+
+#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */
diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h
index 197dc28b67..a1c09e88e8 100644
--- a/include/dt-bindings/gpio/tegra-gpio.h
+++ b/include/dt-bindings/gpio/tegra-gpio.h
@@ -12,40 +12,40 @@
 
 #include <dt-bindings/gpio/gpio.h>
 
-#define TEGRA_GPIO_BANK_ID_A 0
-#define TEGRA_GPIO_BANK_ID_B 1
-#define TEGRA_GPIO_BANK_ID_C 2
-#define TEGRA_GPIO_BANK_ID_D 3
-#define TEGRA_GPIO_BANK_ID_E 4
-#define TEGRA_GPIO_BANK_ID_F 5
-#define TEGRA_GPIO_BANK_ID_G 6
-#define TEGRA_GPIO_BANK_ID_H 7
-#define TEGRA_GPIO_BANK_ID_I 8
-#define TEGRA_GPIO_BANK_ID_J 9
-#define TEGRA_GPIO_BANK_ID_K 10
-#define TEGRA_GPIO_BANK_ID_L 11
-#define TEGRA_GPIO_BANK_ID_M 12
-#define TEGRA_GPIO_BANK_ID_N 13
-#define TEGRA_GPIO_BANK_ID_O 14
-#define TEGRA_GPIO_BANK_ID_P 15
-#define TEGRA_GPIO_BANK_ID_Q 16
-#define TEGRA_GPIO_BANK_ID_R 17
-#define TEGRA_GPIO_BANK_ID_S 18
-#define TEGRA_GPIO_BANK_ID_T 19
-#define TEGRA_GPIO_BANK_ID_U 20
-#define TEGRA_GPIO_BANK_ID_V 21
-#define TEGRA_GPIO_BANK_ID_W 22
-#define TEGRA_GPIO_BANK_ID_X 23
-#define TEGRA_GPIO_BANK_ID_Y 24
-#define TEGRA_GPIO_BANK_ID_Z 25
-#define TEGRA_GPIO_BANK_ID_AA 26
-#define TEGRA_GPIO_BANK_ID_BB 27
-#define TEGRA_GPIO_BANK_ID_CC 28
-#define TEGRA_GPIO_BANK_ID_DD 29
-#define TEGRA_GPIO_BANK_ID_EE 30
-#define TEGRA_GPIO_BANK_ID_FF 31
+#define TEGRA_GPIO_PORT_A 0
+#define TEGRA_GPIO_PORT_B 1
+#define TEGRA_GPIO_PORT_C 2
+#define TEGRA_GPIO_PORT_D 3
+#define TEGRA_GPIO_PORT_E 4
+#define TEGRA_GPIO_PORT_F 5
+#define TEGRA_GPIO_PORT_G 6
+#define TEGRA_GPIO_PORT_H 7
+#define TEGRA_GPIO_PORT_I 8
+#define TEGRA_GPIO_PORT_J 9
+#define TEGRA_GPIO_PORT_K 10
+#define TEGRA_GPIO_PORT_L 11
+#define TEGRA_GPIO_PORT_M 12
+#define TEGRA_GPIO_PORT_N 13
+#define TEGRA_GPIO_PORT_O 14
+#define TEGRA_GPIO_PORT_P 15
+#define TEGRA_GPIO_PORT_Q 16
+#define TEGRA_GPIO_PORT_R 17
+#define TEGRA_GPIO_PORT_S 18
+#define TEGRA_GPIO_PORT_T 19
+#define TEGRA_GPIO_PORT_U 20
+#define TEGRA_GPIO_PORT_V 21
+#define TEGRA_GPIO_PORT_W 22
+#define TEGRA_GPIO_PORT_X 23
+#define TEGRA_GPIO_PORT_Y 24
+#define TEGRA_GPIO_PORT_Z 25
+#define TEGRA_GPIO_PORT_AA 26
+#define TEGRA_GPIO_PORT_BB 27
+#define TEGRA_GPIO_PORT_CC 28
+#define TEGRA_GPIO_PORT_DD 29
+#define TEGRA_GPIO_PORT_EE 30
+#define TEGRA_GPIO_PORT_FF 31
 
-#define TEGRA_GPIO(bank, offset) \
-	((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+#define TEGRA_GPIO(port, offset) \
+	((TEGRA_GPIO_PORT_##port * 8) + offset)
 
 #endif
diff --git a/include/dt-bindings/gpio/tegra186-gpio.h b/include/dt-bindings/gpio/tegra186-gpio.h
new file mode 100644
index 0000000000..7e6fb95da1
--- /dev/null
+++ b/include/dt-bindings/gpio/tegra186-gpio.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ * This header provides constants for binding nvidia,tegra186-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_MAIN_GPIO_PORT_A 0
+#define TEGRA_MAIN_GPIO_PORT_B 1
+#define TEGRA_MAIN_GPIO_PORT_C 2
+#define TEGRA_MAIN_GPIO_PORT_D 3
+#define TEGRA_MAIN_GPIO_PORT_E 4
+#define TEGRA_MAIN_GPIO_PORT_F 5
+#define TEGRA_MAIN_GPIO_PORT_G 6
+#define TEGRA_MAIN_GPIO_PORT_H 7
+#define TEGRA_MAIN_GPIO_PORT_I 8
+#define TEGRA_MAIN_GPIO_PORT_J 9
+#define TEGRA_MAIN_GPIO_PORT_K 10
+#define TEGRA_MAIN_GPIO_PORT_L 11
+#define TEGRA_MAIN_GPIO_PORT_M 12
+#define TEGRA_MAIN_GPIO_PORT_N 13
+#define TEGRA_MAIN_GPIO_PORT_O 14
+#define TEGRA_MAIN_GPIO_PORT_P 15
+#define TEGRA_MAIN_GPIO_PORT_Q 16
+#define TEGRA_MAIN_GPIO_PORT_R 17
+#define TEGRA_MAIN_GPIO_PORT_T 18
+#define TEGRA_MAIN_GPIO_PORT_X 19
+#define TEGRA_MAIN_GPIO_PORT_Y 20
+#define TEGRA_MAIN_GPIO_PORT_BB 21
+#define TEGRA_MAIN_GPIO_PORT_CC 22
+
+#define TEGRA_MAIN_GPIO(port, offset) \
+	((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_AON_GPIO_PORT_S 0
+#define TEGRA_AON_GPIO_PORT_U 1
+#define TEGRA_AON_GPIO_PORT_V 2
+#define TEGRA_AON_GPIO_PORT_W 3
+#define TEGRA_AON_GPIO_PORT_Z 4
+#define TEGRA_AON_GPIO_PORT_AA 5
+#define TEGRA_AON_GPIO_PORT_EE 6
+#define TEGRA_AON_GPIO_PORT_FF 7
+
+#define TEGRA_AON_GPIO(port, offset) \
+	((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
+
+#endif
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
new file mode 100644
index 0000000000..1843757a5c
--- /dev/null
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -0,0 +1,35 @@
+/*
+ * TI DP83867 PHY drivers
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ */
+
+#ifndef _DT_BINDINGS_TI_DP83867_H
+#define _DT_BINDINGS_TI_DP83867_H
+
+/* PHY CTRL bits */
+#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB	0x00
+#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB	0x01
+#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB	0x02
+#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB	0x03
+
+/* RGMIIDCTL internal delay for rx and tx */
+#define DP83867_RGMIIDCTL_250_PS	0x0
+#define DP83867_RGMIIDCTL_500_PS	0x1
+#define DP83867_RGMIIDCTL_750_PS	0x2
+#define DP83867_RGMIIDCTL_1_NS		0x3
+#define DP83867_RGMIIDCTL_1_25_NS	0x4
+#define DP83867_RGMIIDCTL_1_50_NS	0x5
+#define DP83867_RGMIIDCTL_1_75_NS	0x6
+#define DP83867_RGMIIDCTL_2_00_NS	0x7
+#define DP83867_RGMIIDCTL_2_25_NS	0x8
+#define DP83867_RGMIIDCTL_2_50_NS	0x9
+#define DP83867_RGMIIDCTL_2_75_NS	0xa
+#define DP83867_RGMIIDCTL_3_00_NS	0xb
+#define DP83867_RGMIIDCTL_3_25_NS	0xc
+#define DP83867_RGMIIDCTL_3_50_NS	0xd
+#define DP83867_RGMIIDCTL_3_75_NS	0xe
+#define DP83867_RGMIIDCTL_4_00_NS	0xf
+
+#endif
diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h
index 720368782e..292c2ebf58 100644
--- a/include/dt-bindings/pinctrl/am43xx.h
+++ b/include/dt-bindings/pinctrl/am43xx.h
@@ -30,4 +30,10 @@
 #define PIN_INPUT_PULLUP	(INPUT_EN | PULL_UP)
 #define PIN_INPUT_PULLDOWN	(INPUT_EN)
 
+/*
+ * Macro to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define AM4372_IOPAD(pa, val)	(((pa) & 0xffff) - 0x0800) (val)
+
 #endif
diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h
index 1dd7636a69..672a1369af 100644
--- a/include/dt-bindings/pinctrl/omap.h
+++ b/include/dt-bindings/pinctrl/omap.h
@@ -53,5 +53,42 @@
 #define PIN_OFF_INPUT_PULLDOWN	(OFF_EN | OFF_PULL_EN)
 #define PIN_OFF_WAKEUPENABLE	WAKEUP_EN
 
+/*
+ * Macros to allow using the absolute physical address instead of the
+ * padconf registers instead of the offset from padconf base.
+ */
+#define OMAP_IOPAD_OFFSET(pa, offset)	(((pa) & 0xffff) - (offset))
+
+#define OMAP2420_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
+#define OMAP2430_CORE_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3_CORE1_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
+#define OMAP3430_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
+#define OMAP3630_CORE2_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
+#define OMAP3_WKUP_IOPAD(pa, val)	OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
+#define DM814X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define DM816X_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+#define AM33XX_IOPAD(pa, val)		OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
+
+/*
+ * Macros to allow using the offset from the padconf physical address
+ * instead  of the offset from padconf base.
+ */
+#define OMAP_PADCONF_OFFSET(offset, base_offset)	((offset) - (base_offset))
+
+#define OMAP4_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+#define OMAP5_IOPAD(offset, val)	OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
+
+/*
+ * Define some commonly used pins configured by the boards.
+ * Note that some boards use alternative pins, so check
+ * the schematics before using these.
+ */
+#define OMAP3_UART1_RX		0x152
+#define OMAP3_UART2_RX		0x14a
+#define OMAP3_UART3_RX		0x16e
+#define OMAP4_UART2_RX		0xdc
+#define OMAP4_UART3_RX		0x104
+#define OMAP4_UART4_RX		0x11c
+
 #endif
 
diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h
new file mode 100644
index 0000000000..cf28631d71
--- /dev/null
+++ b/include/dt-bindings/regulator/maxim,max77802.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Device Tree binding constants for the Maxim 77802 PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H
+
+/* Regulator operating modes */
+#define MAX77802_OPMODE_LP	1
+#define MAX77802_OPMODE_NORMAL	3
+
+#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */
diff --git a/include/dt-bindings/sound/tlv320aic31xx-micbias.h b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
new file mode 100644
index 0000000000..f5cb772ab9
--- /dev/null
+++ b/include/dt-bindings/sound/tlv320aic31xx-micbias.h
@@ -0,0 +1,8 @@
+#ifndef __DT_TLV320AIC31XX_MICBIAS_H
+#define __DT_TLV320AIC31XX_MICBIAS_H
+
+#define MICBIAS_2_0V		1
+#define MICBIAS_2_5V		2
+#define MICBIAS_AVDDV		3
+
+#endif /* __DT_TLV320AIC31XX_MICBIAS_H */
diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h
index 09ff8a74d6..7af2ad11e4 100644
--- a/include/dwc3-uboot.h
+++ b/include/dwc3-uboot.h
@@ -13,7 +13,7 @@
 #include <linux/usb/otg.h>
 
 struct dwc3_device {
-	int base;
+	unsigned long base;
 	enum usb_dr_mode dr_mode;
 	u32 maximum_speed;
 	unsigned tx_fifo_resize:1;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 05b0817fe1..335af51fdf 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -180,8 +180,9 @@ struct dwmci_host {
 	 * @freq:	Frequency the host is trying to achieve
 	 */
 	unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
-
+#ifndef CONFIG_BLK
 	struct mmc_config cfg;
+#endif
 
 	/* use fifo mode to read and write data */
 	bool fifo_mode;
@@ -223,5 +224,9 @@ static inline u8 dwmci_readb(struct dwmci_host *host, int reg)
 	return readb(host->ioaddr + reg);
 }
 
+void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
+		     uint caps, u32 max_clk, u32 min_clk);
+int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
+
 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
 #endif	/* __DWMMC_HW_H */
diff --git a/include/efi_api.h b/include/efi_api.h
index 51d7586e63..f572b88079 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -17,6 +17,10 @@
 
 #include <efi.h>
 
+#ifdef CONFIG_EFI_LOADER
+#include <asm/setjmp.h>
+#endif
+
 /* Types and defines for EFI CreateEvent */
 enum efi_event_type {
 	EFI_TIMER_STOP = 0,
@@ -239,6 +243,12 @@ struct efi_loaded_image {
 	unsigned int image_code_type;
 	unsigned int image_data_type;
 	unsigned long unload;
+
+	/* Below are efi loader private fields */
+#ifdef CONFIG_EFI_LOADER
+	efi_status_t exit_status;
+	struct jmp_buf_data exit_jmp;
+#endif
 };
 
 #define DEVICE_PATH_GUID \
@@ -412,4 +422,123 @@ struct efi_gop
 	struct efi_gop_mode *mode;
 };
 
+#define EFI_SIMPLE_NETWORK_GUID \
+	EFI_GUID(0xa19832b9, 0xac25, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_mac_address {
+	char mac_addr[32];
+};
+
+struct efi_ip_address {
+	u8 ip_addr[16];
+};
+
+enum efi_simple_network_state {
+	EFI_NETWORK_STOPPED,
+	EFI_NETWORK_STARTED,
+	EFI_NETWORK_INITIALIZED,
+};
+
+struct efi_simple_network_mode {
+	enum efi_simple_network_state state;
+	u32 hwaddr_size;
+	u32 media_header_size;
+	u32 max_packet_size;
+	u32 nvram_size;
+	u32 nvram_access_size;
+	u32 receive_filter_mask;
+	u32 receive_filter_setting;
+	u32 max_mcast_filter_count;
+	u32 mcast_filter_count;
+	struct efi_mac_address mcast_filter[16];
+	struct efi_mac_address current_address;
+	struct efi_mac_address broadcast_address;
+	struct efi_mac_address permanent_address;
+	u8 if_type;
+	u8 mac_changeable;
+	u8 multitx_supported;
+	u8 media_present_supported;
+	u8 media_present;
+};
+
+#define EFI_SIMPLE_NETWORK_RECEIVE_UNICAST               0x01,
+#define EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST             0x02,
+#define EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST             0x04,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS           0x08,
+#define EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST 0x10,
+
+struct efi_simple_network
+{
+	u64 revision;
+	efi_status_t (EFIAPI *start)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *stop)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *initialize)(struct efi_simple_network *this,
+			ulong extra_rx, ulong extra_tx);
+	efi_status_t (EFIAPI *reset)(struct efi_simple_network *this,
+			int extended_verification);
+	efi_status_t (EFIAPI *shutdown)(struct efi_simple_network *this);
+	efi_status_t (EFIAPI *receive_filters)(struct efi_simple_network *this,
+			u32 enable, u32 disable, int reset_mcast_filter,
+			ulong mcast_filter_count,
+			struct efi_mac_address *mcast_filter);
+	efi_status_t (EFIAPI *station_address)(struct efi_simple_network *this,
+			int reset, struct efi_mac_address *new_mac);
+	efi_status_t (EFIAPI *statistics)(struct efi_simple_network *this,
+			int reset, ulong *stat_size, void *stat_table);
+	efi_status_t (EFIAPI *mcastiptomac)(struct efi_simple_network *this,
+			int ipv6, struct efi_ip_address *ip,
+			struct efi_mac_address *mac);
+	efi_status_t (EFIAPI *nvdata)(struct efi_simple_network *this,
+			int read_write, ulong offset, ulong buffer_size,
+			char *buffer);
+	efi_status_t (EFIAPI *get_status)(struct efi_simple_network *this,
+			u32 *int_status, void **txbuf);
+	efi_status_t (EFIAPI *transmit)(struct efi_simple_network *this,
+			ulong header_size, ulong buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	efi_status_t (EFIAPI *receive)(struct efi_simple_network *this,
+			ulong *header_size, ulong *buffer_size, void *buffer,
+			struct efi_mac_address *src_addr,
+			struct efi_mac_address *dest_addr, u16 *protocol);
+	void (EFIAPI *waitforpacket)(void);
+	struct efi_simple_network_mode *mode;
+};
+
+#define EFI_PXE_GUID \
+	EFI_GUID(0x03c4e603, 0xac28, 0x11d3, \
+		 0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d)
+
+struct efi_pxe_packet {
+	u8 packet[1472];
+};
+
+struct efi_pxe_mode
+{
+	u8 unused[52];
+	struct efi_pxe_packet dhcp_discover;
+	struct efi_pxe_packet dhcp_ack;
+	struct efi_pxe_packet proxy_offer;
+	struct efi_pxe_packet pxe_discover;
+	struct efi_pxe_packet pxe_reply;
+};
+
+struct efi_pxe {
+	u64 rev;
+	void (EFIAPI *start)(void);
+	void (EFIAPI *stop)(void);
+	void (EFIAPI *dhcp)(void);
+	void (EFIAPI *discover)(void);
+	void (EFIAPI *mftp)(void);
+	void (EFIAPI *udpwrite)(void);
+	void (EFIAPI *udpread)(void);
+	void (EFIAPI *setipfilter)(void);
+	void (EFIAPI *arp)(void);
+	void (EFIAPI *setparams)(void);
+	void (EFIAPI *setstationip)(void);
+	void (EFIAPI *setpackets)(void);
+	struct efi_pxe_mode *mode;
+};
+
 #endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 88b8149b14..97388350eb 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -15,18 +15,10 @@
 
 #include <linux/list.h>
 
-/* #define DEBUG_EFI */
-
-#ifdef DEBUG_EFI
 #define EFI_ENTRY(format, ...) do { \
 	efi_restore_gd(); \
-	printf("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
+	debug("EFI: Entry %s(" format ")\n", __func__, ##__VA_ARGS__); \
 	} while(0)
-#else
-#define EFI_ENTRY(format, ...) do { \
-	efi_restore_gd(); \
-	} while(0)
-#endif
 
 #define EFI_EXIT(ret) efi_exit_func(ret);
 
@@ -91,6 +83,12 @@ extern struct list_head efi_obj_list;
 int efi_disk_register(void);
 /* Called by bootefi to make GOP (graphical) interface available */
 int efi_gop_register(void);
+/* Called by bootefi to make the network interface available */
+int efi_net_register(void **handle);
+
+/* Called by networking code to memorize the dhcp ack package */
+void efi_net_set_dhcp_ack(void *pkt, int len);
+
 /*
  * Stub implementation for a protocol opener that just returns the handle as
  * interface
@@ -133,8 +131,13 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 /* Called by board init to initialize the EFI memory map */
 int efi_memory_init(void);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+extern void *efi_bounce_buffer;
+#define EFI_LOADER_BOUNCE_BUFFER_SIZE (64 * 1024 * 1024)
+#endif
+
 /* Convert strings from normal C strings to uEFI strings */
-static inline void ascii2unicode(u16 *unicode, char *ascii)
+static inline void ascii2unicode(u16 *unicode, const char *ascii)
 {
 	while (*ascii)
 		*(unicode++) = *(ascii++);
@@ -157,5 +160,6 @@ static inline void ascii2unicode(u16 *unicode, char *ascii)
 static inline void efi_restore_gd(void) { }
 static inline void efi_set_bootdev(const char *dev, const char *devnr,
 				   const char *path) { }
+static inline void efi_net_set_dhcp_ack(void *pkt, int len) { }
 
 #endif
diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h
index 3969a6a066..ab92ffb72a 100644
--- a/include/exynos_lcd.h
+++ b/include/exynos_lcd.h
@@ -75,8 +75,8 @@ typedef struct vidinfo {
 	unsigned int sclk_div;
 
 	unsigned int dual_lcd_enabled;
+	struct exynos_fb *reg;
+	struct exynos_platform_mipi_dsim *dsim_platform_data_dt;
 } vidinfo_t;
 
-void init_panel_info(vidinfo_t *vid);
-
 #endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 37d482aba7..54e3d8139f 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -123,6 +123,7 @@ enum fdt_compat_id {
 	COMPAT_NVIDIA_TEGRA124_SOR,	/* Tegra 124 Serial Output Resource */
 	COMPAT_NVIDIA_TEGRA124_PMC,	/* Tegra 124 power mgmt controller */
 	COMPAT_NVIDIA_TEGRA20_DC,	/* Tegra 2 Display controller */
+	COMPAT_NVIDIA_TEGRA186_SDMMC,	/* Tegra186 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA210_SDMMC,	/* Tegra210 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA124_SDMMC,	/* Tegra124 SDMMC controller */
 	COMPAT_NVIDIA_TEGRA30_SDMMC,	/* Tegra30 SDMMC controller */
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index cf316a4665..486e47e508 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define WR_DATA_DELAY_SHIFT	10
 #endif
 
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS	0x07000000
+#define DDR_EOR_WD_REOD_DIS	0x00100000
+
 /* DDR_MD_CNTL */
 #define MD_CNTL_MD_EN		0x80000000
 #define MD_CNTL_CS_SEL_CS0	0x00000000
@@ -185,6 +189,13 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK	0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK	0x2 /* for DDR4-2400 */
 
+/* DEBUG_26 register */
+#define DDR_CAS_TO_PRE_SUB_MASK  0x0000f000 /* CAS to preamble subtract value */
+#define DDR_CAS_TO_PRE_SUB_SHIFT 12
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS	(1 << 10) /* Transmit Bit Deskew Disable */
+
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
 	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h
new file mode 100644
index 0000000000..281a819863
--- /dev/null
+++ b/include/fsl_mmdc.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING		0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0	0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1	0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2	0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC		0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT	0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY	0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL		0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY	0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION	0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL		0xa1390003
+
+#define	FORCE_ZQ_AUTO_CALIBRATION		(0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN				0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN				0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG	0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN	0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN			0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL	0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT	0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x103e8000
+
+#define START_REFRESH				0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
+
+#define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
+
+#define DISABLE_CFG_REQ		0x0
+#define CONFIGURATION_REQ	(0x1  << 15)
+#define WL_EN			(0x1  << 9)
+
+#define	CMD_NORMAL		(0x0 << 4)
+#define	CMD_PRECHARGE		(0x1 << 4)
+#define	CMD_AUTO_REFRESH	(0x2 << 4)
+#define	CMD_LOAD_MODE_REG	(0x3 << 4)
+#define	CMD_ZQ_CALIBRATION	(0x4 << 4)
+#define	CMD_PRECHARGE_BANK_OPEN	(0x5 << 4)
+#define	CMD_MRR			(0x6 << 4)
+
+#define CMD_BANK_ADDR_0		0x0
+#define CMD_BANK_ADDR_1		0x1
+#define CMD_BANK_ADDR_2		0x2
+#define CMD_BANK_ADDR_3		0x3
+#define CMD_BANK_ADDR_4		0x4
+#define CMD_BANK_ADDR_5		0x5
+#define CMD_BANK_ADDR_6		0x6
+#define CMD_BANK_ADDR_7		0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdmrr;
+	u32 mdcfg3lp;
+	u32 mdmr4;
+	u32 mdasp;
+	u32 res2[239];
+	u32 maarcr;
+	u32 mapsr;
+	u32 maexidr0;
+	u32 maexidr1;
+	u32 madpcr0;
+	u32 madpcr1;
+	u32 madpsr0;
+	u32 madpsr1;
+	u32 madpsr2;
+	u32 madpsr3;
+	u32 madpsr4;
+	u32 madpsr5;
+	u32 masbs0;
+	u32 masbs1;
+	u32 res3[2];
+	u32 magenp;
+	u32 res4[239];
+	u32 mpzqhwctrl;
+	u32 mpzqswctrl;
+	u32 mpwlgcr;
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 mpwldlst;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 res5[4];
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 mpdgdlst0;
+	u32 mprddlctl;
+	u32 mprddlst;
+	u32 mpwrdlctl;
+	u32 mpwrdlst;
+	u32 mpsdctrl;
+	u32 mpzqlp2ctl;
+	u32 mprddlhwctl;
+	u32 mpwrdlhwctl;
+	u32 mprddlhwst0;
+	u32 mprddlhwst1;
+	u32 mpwrdlhwst0;
+	u32 mpwrdlhwst1;
+	u32 mpwlhwerr;
+	u32 mpdghwst0;
+	u32 mpdghwst1;
+	u32 mpdghwst2;
+	u32 mpdghwst3;
+	u32 mppdcmpr1;
+	u32 mppdcmpr2;
+	u32 mpswdar0;
+	u32 mpswdrdr0;
+	u32 mpswdrdr1;
+	u32 mpswdrdr2;
+	u32 mpswdrdr3;
+	u32 mpswdrdr4;
+	u32 mpswdrdr5;
+	u32 mpswdrdr6;
+	u32 mpswdrdr7;
+	u32 mpmur0;
+	u32 mpwrcadl;
+	u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */
diff --git a/include/fsl_sec.h b/include/fsl_sec.h
index a52110a625..bffabc89b9 100644
--- a/include/fsl_sec.h
+++ b/include/fsl_sec.h
@@ -294,8 +294,6 @@ struct sg_entry {
 
 #endif
 
-int sec_init(void);
-
 /* blob_dek:
  * Encapsulates the src in a secure blob and stores it dst
  * @src: reference to the plaintext
@@ -305,6 +303,10 @@ int sec_init(void);
  */
 int blob_dek(const u8 *src, u8 *dst, u8 len);
 
+#if defined(CONFIG_PPC_C29X)
+int sec_init_idx(uint8_t);
+#endif
+int sec_init(void);
 #endif
 
 #endif /* __FSL_SEC_H */
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 3b8762df66..e1b9c64626 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -163,7 +163,7 @@ struct ihs_fpga {
 };
 #endif
 
-#ifdef CONFIG_HRCON
+#if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
 struct ihs_fpga {
 	u16 reflection_low;	/* 0x0000 */
 	u16 versions;		/* 0x0002 */
diff --git a/include/image.h b/include/image.h
index f9ee5649c5..a8f6bd16f6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -246,8 +246,10 @@ struct lmb;
 #define IH_TYPE_RKSD		24	/* Rockchip SD card		*/
 #define IH_TYPE_RKSPI		25	/* Rockchip SPI image		*/
 #define IH_TYPE_ZYNQIMAGE	26	/* Xilinx Zynq Boot Image */
+#define IH_TYPE_ZYNQMPIMAGE	27	/* Xilinx ZynqMP Boot Image */
+#define IH_TYPE_FPGA		28	/* FPGA Image */
 
-#define IH_TYPE_COUNT		27	/* Number of image types */
+#define IH_TYPE_COUNT		29	/* Number of image types */
 
 /*
  * Compression Types
@@ -494,6 +496,8 @@ int genimg_get_format(const void *img_addr);
 int genimg_has_config(bootm_headers_t *images);
 ulong genimg_get_image(ulong img_addr);
 
+int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
+		uint8_t arch, const ulong *ld_start, ulong * const ld_len);
 int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
 		uint8_t arch, ulong *rd_start, ulong *rd_end);
 
@@ -809,6 +813,7 @@ int bootz_setup(ulong image, ulong *start, ulong *end);
 #define FIT_LOADABLE_PROP	"loadables"
 #define FIT_DEFAULT_PROP	"default"
 #define FIT_SETUP_PROP		"setup"
+#define FIT_FPGA_PROP		"fpga"
 
 #define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
 
diff --git a/include/libtizen.h b/include/libtizen.h
index 6490fb52ba..55dccff715 100644
--- a/include/libtizen.h
+++ b/include/libtizen.h
@@ -10,6 +10,8 @@
 
 #define HD_RESOLUTION	0
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid);
+#endif
 
 #endif	/* _LIBTIZEN_H_ */
diff --git a/include/linux/mtd/docg4.h b/include/linux/mtd/docg4.h
deleted file mode 100644
index 741fc0db46..0000000000
--- a/include/linux/mtd/docg4.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __DOCG4_H__
-#define __DOCG4_H__
-
-#include <common.h>
-#include <linux/mtd/nand.h>
-
-extern int docg4_nand_init(struct mtd_info *mtd,
-			   struct nand_chip *nand, int devnum);
-
-/* SPL-related definitions */
-#define DOCG4_IPL_LOAD_BLOCK_COUNT 2  /* number of blocks that IPL loads */
-#define DOCG4_BLOCK_CAPACITY_SPL 0x10000 /* reliable mode; redundant pages */
-
-#define DOC_IOSPACE_DATA		0x0800
-
-/* register offsets */
-#define DOC_CHIPID			0x1000
-#define DOC_DEVICESELECT		0x100a
-#define DOC_ASICMODE			0x100c
-#define DOC_DATAEND			0x101e
-#define DOC_NOP				0x103e
-
-#define DOC_FLASHSEQUENCE		0x1032
-#define DOC_FLASHCOMMAND		0x1034
-#define DOC_FLASHADDRESS		0x1036
-#define DOC_FLASHCONTROL		0x1038
-#define DOC_ECCCONF0			0x1040
-#define DOC_ECCCONF1			0x1042
-#define DOC_HAMMINGPARITY		0x1046
-#define DOC_BCH_SYNDROM(idx)		(0x1048 + idx)
-
-#define DOC_ASICMODECONFIRM		0x1072
-#define DOC_CHIPID_INV			0x1074
-#define DOC_POWERMODE			0x107c
-
-#define DOCG4_MYSTERY_REG		0x1050
-
-/* apparently used only to write oob bytes 6 and 7 */
-#define DOCG4_OOB_6_7			0x1052
-
-/* DOC_FLASHSEQUENCE register commands */
-#define DOC_SEQ_RESET			0x00
-#define DOCG4_SEQ_PAGE_READ		0x03
-#define DOCG4_SEQ_FLUSH			0x29
-#define DOCG4_SEQ_PAGEWRITE		0x16
-#define DOCG4_SEQ_PAGEPROG		0x1e
-#define DOCG4_SEQ_BLOCKERASE		0x24
-
-/* DOC_FLASHCOMMAND register commands */
-#define DOCG4_CMD_PAGE_READ             0x00
-#define DOC_CMD_ERASECYCLE2		0xd0
-#define DOCG4_CMD_FLUSH                 0x70
-#define DOCG4_CMD_READ2                 0x30
-#define DOC_CMD_PROG_BLOCK_ADDR		0x60
-#define DOCG4_CMD_PAGEWRITE		0x80
-#define DOC_CMD_PROG_CYCLE2		0x10
-#define DOC_CMD_RESET			0xff
-
-/* DOC_POWERMODE register bits */
-#define DOC_POWERDOWN_READY		0x80
-
-/* DOC_FLASHCONTROL register bits */
-#define DOC_CTRL_CE			0x10
-#define DOC_CTRL_UNKNOWN		0x40
-#define DOC_CTRL_FLASHREADY		0x01
-
-/* DOC_ECCCONF0 register bits */
-#define DOC_ECCCONF0_READ_MODE		0x8000
-#define DOC_ECCCONF0_UNKNOWN		0x2000
-#define DOC_ECCCONF0_ECC_ENABLE	        0x1000
-#define DOC_ECCCONF0_DATA_BYTES_MASK	0x07ff
-
-/* DOC_ECCCONF1 register bits */
-#define DOC_ECCCONF1_BCH_SYNDROM_ERR	0x80
-#define DOC_ECCCONF1_ECC_ENABLE         0x07
-#define DOC_ECCCONF1_PAGE_IS_WRITTEN	0x20
-
-/* DOC_ASICMODE register bits */
-#define DOC_ASICMODE_RESET		0x00
-#define DOC_ASICMODE_NORMAL		0x01
-#define DOC_ASICMODE_POWERDOWN		0x02
-#define DOC_ASICMODE_MDWREN		0x04
-#define DOC_ASICMODE_BDETCT_RESET	0x08
-#define DOC_ASICMODE_RSTIN_RESET	0x10
-#define DOC_ASICMODE_RAM_WE		0x20
-
-/* good status values read after read/write/erase operations */
-#define DOCG4_PROGSTATUS_GOOD          0x51
-#define DOCG4_PROGSTATUS_GOOD_2        0xe0
-
-/*
- * On read operations (page and oob-only), the first byte read from I/O reg is a
- * status.  On error, it reads 0x73; otherwise, it reads either 0x71 (first read
- * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
- */
-#define DOCG4_READ_ERROR           0x02 /* bit 1 indicates read error */
-
-/* anatomy of the device */
-#define DOCG4_CHIP_SIZE        0x8000000
-#define DOCG4_PAGE_SIZE        0x200
-#define DOCG4_PAGES_PER_BLOCK  0x200
-#define DOCG4_BLOCK_SIZE       (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
-#define DOCG4_NUMBLOCKS        (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
-#define DOCG4_OOB_SIZE         0x10
-#define DOCG4_CHIP_SHIFT       27    /* log_2(DOCG4_CHIP_SIZE) */
-#define DOCG4_PAGE_SHIFT       9     /* log_2(DOCG4_PAGE_SIZE) */
-#define DOCG4_ERASE_SHIFT      18    /* log_2(DOCG4_BLOCK_SIZE) */
-
-/* all but the last byte is included in ecc calculation */
-#define DOCG4_BCH_SIZE         (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
-
-#define DOCG4_USERDATA_LEN     520 /* 512 byte page plus 8 oob avail to user */
-
-/* expected values from the ID registers */
-#define DOCG4_IDREG1_VALUE     0x0400
-#define DOCG4_IDREG2_VALUE     0xfbff
-
-/* primitive polynomial used to build the Galois field used by hw ecc gen */
-#define DOCG4_PRIMITIVE_POLY   0x4443
-
-#define DOCG4_M                14  /* Galois field is of order 2^14 */
-#define DOCG4_T                4   /* BCH alg corrects up to 4 bit errors */
-
-#define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
-
-#endif	/* __DOCG4_H__ */
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 9da77ec144..cf20674549 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -278,6 +278,11 @@ struct mtd_info {
 	int usecount;
 };
 
+static inline int mtd_oobavail(struct mtd_info *mtd, struct mtd_oob_ops *ops)
+{
+	return ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+}
+
 int mtd_erase(struct mtd_info *mtd, struct erase_info *instr);
 #ifndef __UBOOT__
 int mtd_point(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 23072fdfc3..b5a02c3382 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -25,6 +25,8 @@
 
 struct mtd_info;
 struct nand_flash_dev;
+struct device_node;
+
 /* Scan and identify a NAND device */
 extern int nand_scan(struct mtd_info *mtd, int max_chips);
 /*
@@ -144,6 +146,14 @@ typedef enum {
 /* Enable Hardware ECC before syndrome is read back from flash */
 #define NAND_ECC_READSYN	2
 
+/*
+ * Enable generic NAND 'page erased' check. This check is only done when
+ * ecc.correct() returns -EBADMSG.
+ * Set this flag if your implementation does not fix bitflips in erased
+ * pages and you want to rely on the default implementation.
+ */
+#define NAND_ECC_GENERIC_ERASED_CHECK	BIT(0)
+
 /* Bit mask for flags passed to do_nand_read_ecc */
 #define NAND_GET_DEVICE		0x80
 
@@ -179,6 +189,12 @@ typedef enum {
 /* Device supports subpage reads */
 #define NAND_SUBPAGE_READ	0x00001000
 
+/*
+ * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
+ * patterns.
+ */
+#define NAND_NEED_SCRAMBLING	0x00002000
+
 /* Options valid for Samsung large page devices */
 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
 
@@ -203,6 +219,11 @@ typedef enum {
  * before calling nand_scan_tail.
  */
 #define NAND_BUSWIDTH_AUTO      0x00080000
+/*
+ * This option could be defined by controller drivers to protect against
+ * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
+ */
+#define NAND_USE_BOUNCE_BUFFER	0x00100000
 
 /* Options set by nand scan */
 /* bbt has already been read */
@@ -292,15 +313,15 @@ struct nand_onfi_params {
 	__le16 t_r;
 	__le16 t_ccs;
 	__le16 src_sync_timing_mode;
-	__le16 src_ssync_features;
+	u8 src_ssync_features;
 	__le16 clk_pin_capacitance_typ;
 	__le16 io_pin_capacitance_typ;
 	__le16 input_pin_capacitance_typ;
 	u8 input_pin_capacitance_max;
 	u8 driver_strength_support;
 	__le16 t_int_r;
-	__le16 t_ald;
-	u8 reserved4[7];
+	__le16 t_adl;
+	u8 reserved4[8];
 
 	/* vendor */
 	__le16 vendor_revision;
@@ -423,7 +444,7 @@ struct nand_jedec_params {
 	__le16 input_pin_capacitance_typ;
 	__le16 clk_pin_capacitance_typ;
 	u8 driver_strength_support;
-	__le16 t_ald;
+	__le16 t_adl;
 	u8 reserved4[36];
 
 	/* ECC and endurance block */
@@ -466,12 +487,19 @@ struct nand_hw_control {
  * @total:	total number of ECC bytes per page
  * @prepad:	padding information for syndrome based ECC generators
  * @postpad:	padding information for syndrome based ECC generators
+ * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
  * @layout:	ECC layout control struct pointer
  * @priv:	pointer to private ECC control data
  * @hwctl:	function to control hardware ECC generator. Must only
  *		be provided if an hardware ECC is available
  * @calculate:	function for ECC calculation or readback from ECC hardware
- * @correct:	function for ECC correction, matching to ECC generator (sw/hw)
+ * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
+ *		Should return a positive number representing the number of
+ *		corrected bitflips, -EBADMSG if the number of bitflips exceed
+ *		ECC strength, or any other error code if the error is not
+ *		directly related to correction.
+ *		If -EBADMSG is returned the input buffers should be left
+ *		untouched.
  * @read_page_raw:	function to read a raw page without ECC. This function
  *			should hide the specific layout used by the ECC
  *			controller and always return contiguous in-band and
@@ -509,6 +537,7 @@ struct nand_ecc_ctrl {
 	int strength;
 	int prepad;
 	int postpad;
+	unsigned int options;
 	struct nand_ecclayout	*layout;
 	void *priv;
 	void (*hwctl)(struct mtd_info *mtd, int mode);
@@ -519,16 +548,16 @@ struct nand_ecc_ctrl {
 	int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf, int oob_required);
+			const uint8_t *buf, int oob_required, int page);
 	int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint8_t *buf, int oob_required, int page);
 	int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offs, uint32_t len, uint8_t *buf, int page);
 	int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 			uint32_t offset, uint32_t data_len,
-			const uint8_t *data_buf, int oob_required);
+			const uint8_t *data_buf, int oob_required, int page);
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
-			const uint8_t *buf, int oob_required);
+			const uint8_t *buf, int oob_required, int page);
 	int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 			int page);
 	int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
@@ -556,6 +585,7 @@ struct nand_buffers {
 
 /**
  * struct nand_chip - NAND Private Flash Chip Data
+ * @mtd:		MTD device registered to the MTD framework
  * @IO_ADDR_R:		[BOARDSPECIFIC] address to read the 8 I/O lines of the
  *			flash device
  * @IO_ADDR_W:		[BOARDSPECIFIC] address to write the 8 I/O lines of the
@@ -571,10 +601,6 @@ struct nand_buffers {
  * @block_markbad:	[REPLACEABLE] mark a block bad
  * @cmd_ctrl:		[BOARDSPECIFIC] hardwarespecific function for controlling
  *			ALE/CLE/nCE. Also used to write command and address
- * @init_size:		[BOARDSPECIFIC] hardwarespecific function for setting
- *			mtd->oobsize, mtd->writesize and so on.
- *			@id_data contains the 8 bytes values of NAND_CMD_READID.
- *			Return with the bus width.
  * @dev_ready:		[BOARDSPECIFIC] hardwarespecific function for accessing
  *			device ready/busy line. If set to NULL no access to
  *			ready/busy is available and the ready/busy information
@@ -659,6 +685,7 @@ struct nand_buffers {
  */
 
 struct nand_chip {
+	struct mtd_info mtd;
 	void __iomem *IO_ADDR_R;
 	void __iomem *IO_ADDR_W;
 
@@ -668,11 +695,9 @@ struct nand_chip {
 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 	void (*select_chip)(struct mtd_info *mtd, int chip);
-	int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
+	int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
 	int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
-	int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
-			u8 *id_data);
 	int (*dev_ready)(struct mtd_info *mtd);
 	void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 			int page_addr);
@@ -739,6 +764,26 @@ struct nand_chip {
 	void *priv;
 };
 
+static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
+{
+	return container_of(mtd, struct nand_chip, mtd);
+}
+
+static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
+{
+	return &chip->mtd;
+}
+
+static inline void *nand_get_controller_data(struct nand_chip *chip)
+{
+	return chip->priv;
+}
+
+static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
+{
+	chip->priv = priv;
+}
+
 /*
  * NAND Flash Manufacturer ID Codes
  */
@@ -852,7 +897,6 @@ struct nand_manufacturers {
 extern struct nand_flash_dev nand_flash_ids[];
 extern struct nand_manufacturers nand_manuf_ids[];
 
-extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 extern int nand_default_bbt(struct mtd_info *mtd);
 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
@@ -877,7 +921,6 @@ extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  * @chip_delay:		R/B delay value in us
  * @options:		Option flags, e.g. 16bit buswidth
  * @bbt_options:	BBT option flags, e.g. NAND_BBT_USE_FLASH
- * @ecclayout:		ECC layout info structure
  * @part_probe_types:	NULL-terminated array of probe types
  */
 struct platform_nand_chip {
@@ -885,7 +928,6 @@ struct platform_nand_chip {
 	int chip_offset;
 	int nr_partitions;
 	struct mtd_partition *partitions;
-	struct nand_ecclayout *ecclayout;
 	int chip_delay;
 	unsigned int options;
 	unsigned int bbt_options;
@@ -934,15 +976,6 @@ struct platform_nand_data {
 	struct platform_nand_ctrl ctrl;
 };
 
-/* Some helpers to access the data structures */
-static inline
-struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
-{
-	struct nand_chip *chip = mtd->priv;
-
-	return chip->priv;
-}
-
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
 /* return the supported features. */
 static inline int onfi_feature(struct nand_chip *chip)
@@ -1060,4 +1093,9 @@ struct nand_sdr_timings {
 
 /* get timing characteristics from ONFI timing mode. */
 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
+
+int nand_check_erased_ecc_chunk(void *data, int datalen,
+				void *ecc, int ecclen,
+				void *extraoob, int extraooblen,
+				int threshold);
 #endif /* __LINUX_MTD_NAND_H */
diff --git a/include/linux/mtd/nand_bch.h b/include/linux/mtd/nand_bch.h
index d8754dd8c8..8ea6b04cc3 100644
--- a/include/linux/mtd/nand_bch.h
+++ b/include/linux/mtd/nand_bch.h
@@ -32,9 +32,7 @@ int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
 /*
  * Initialize BCH encoder/decoder
  */
-struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
-	      unsigned int eccbytes, struct nand_ecclayout **ecclayout);
+struct nand_bch_control *nand_bch_init(struct mtd_info *mtd);
 /*
  * Release BCH encoder/decoder resources
  */
@@ -55,12 +53,10 @@ static inline int
 nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
 		      unsigned char *read_ecc, unsigned char *calc_ecc)
 {
-	return -1;
+	return -ENOTSUPP;
 }
 
-static inline struct nand_bch_control *
-nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
-	      unsigned int eccbytes, struct nand_ecclayout **ecclayout)
+static inline struct nand_bch_control *nand_bch_init(struct mtd_info *mtd)
 {
 	return NULL;
 }
diff --git a/include/linux/string.h b/include/linux/string.h
index c7047ba0bc..091ccab395 100644
--- a/include/linux/string.h
+++ b/include/linux/string.h
@@ -20,10 +20,6 @@ extern __kernel_size_t strspn(const char *,const char *);
  */
 #include <asm/string.h>
 
-#ifndef __HAVE_ARCH_BCOPY
-char *bcopy(const char *src, char *dest, int count);
-#endif
-
 #ifndef __HAVE_ARCH_STRCPY
 extern char * strcpy(char *,const char *);
 #endif
diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h
index c5e42e69fe..253eddf159 100644
--- a/include/linux/usb/xhci-fsl.h
+++ b/include/linux/usb/xhci-fsl.h
@@ -59,10 +59,14 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
diff --git a/include/mailbox_client.h b/include/mailbox_client.h
new file mode 100644
index 0000000000..8345ea0bf1
--- /dev/null
+++ b/include/mailbox_client.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_CLIENT_H
+#define _MAILBOX_CLIENT_H
+
+/**
+ * A mailbox is a hardware mechanism for transferring small fixed-size messages
+ * and/or notifications between the CPU on which U-Boot runs and some other
+ * device such as an auxiliary CPU running firmware or a hardware module.
+ *
+ * Data transfer is optional; a mailbox may consist solely of a notification
+ * mechanism. When data transfer is implemented, it is via HW registers or
+ * FIFOs, rather than via RAM-based buffers. The mailbox API generally
+ * implements any communication protocol enforced solely by hardware, and
+ * leaves any higher-level protocols to other layers.
+ *
+ * A mailbox channel is a bi-directional mechanism that can send a message or
+ * notification to a single specific remote entity, and receive messages or
+ * notifications from that entity. The size, content, and format of such
+ * messages is defined by the mailbox implementation, or the remote entity with
+ * which it communicates; there is no general standard at this API level.
+ *
+ * A driver that implements UCLASS_MAILBOX is a mailbox provider. A provider
+ * will often implement multiple separate mailbox channels, since the hardware
+ * it manages often has this capability. mailbox_uclass.h describes the
+ * interface which mailbox providers must implement.
+ *
+ * Mailbox consumers/clients generate and send, or receive and process,
+ * messages. This header file describes the API used by clients.
+ */
+
+struct udevice;
+
+/**
+ * struct mbox_chan - A handle to a single mailbox channel.
+ *
+ * Clients provide storage for channels. The content of the channel structure
+ * is managed solely by the mailbox API and mailbox drivers. A mailbox channel
+ * is initialized by "get"ing the mailbox. The channel struct is passed to all
+ * other mailbox APIs to identify which mailbox to operate upon.
+ *
+ * @dev: The device which implements the mailbox.
+ * @id: The mailbox channel ID within the provider.
+ *
+ * Currently, the mailbox API assumes that a single integer ID is enough to
+ * identify and configure any mailbox channel for any mailbox provider. If this
+ * assumption becomes invalid in the future, the struct could be expanded to
+ * either (a) add more fields to allow mailbox providers to store additional
+ * information, or (b) replace the id field with an opaque pointer, which the
+ * provider would dynamically allocated during its .of_xlate op, and process
+ * during is .request op. This may require the addition of an extra op to clean
+ * up the allocation.
+ */
+struct mbox_chan {
+	struct udevice *dev;
+	/*
+	 * Written by of_xlate. We assume a single id is enough for now. In the
+	 * future, we might add more fields here.
+	 */
+	unsigned long id;
+};
+
+/**
+ * mbox_get_by_index - Get/request a mailbox by integer index
+ *
+ * This looks up and requests a mailbox channel. The index is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel indices to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @index:	The index of the mailbox channel to request, within the
+ *		client's list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_index(struct udevice *dev, int index, struct mbox_chan *chan);
+
+/**
+ * mbox_get_by_name - Get/request a mailbox by name
+ *
+ * This looks up and requests a mailbox channel. The name is relative to the
+ * client device; each device is assumed to have n mailbox channels associated
+ * with it somehow, and this function finds and requests one of them. The
+ * mapping of client device channel names to provider channels may be via
+ * device-tree properties, board-provided mapping tables, or some other
+ * mechanism.
+ *
+ * @dev:	The client device.
+ * @name:	The name of the mailbox channel to request, within the client's
+ *		list of channels.
+ * @chan	A pointer to a channel object to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_get_by_name(struct udevice *dev, const char *name,
+		     struct mbox_chan *chan);
+
+/**
+ * mbox_free - Free a previously requested mailbox channel.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_free(struct mbox_chan *chan);
+
+/**
+ * mbox_send - Send a message over a mailbox channel
+ *
+ * This function will send a message to the remote entity. It may return before
+ * the remote entity has received and/or processed the message.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the message to transfer. The format and size of
+ *		the memory region pointed at by @data is determined by the
+ *		mailbox provider. Providers that solely transfer notifications
+ *		will ignore this parameter.
+ * @return 0 if OK, or a negative error code.
+ */
+int mbox_send(struct mbox_chan *chan, const void *data);
+
+/**
+ * mbox_recv - Receive any available message from a mailbox channel
+ *
+ * This function will wait (up to the specified @timeout_us) for a message to
+ * be sent by the remote entity, and write the content of any such message
+ * into a caller-provided buffer.
+ *
+ * @chan:	A channel object that was previously successfully requested by
+ *		calling mbox_get_by_*().
+ * @data:	A pointer to the buffer to receive the message. The format and
+ *		size of the memory region pointed at by @data is determined by
+ *		the mailbox provider. Providers that solely transfer
+ *		notifications will ignore this parameter.
+ * @timeout_us:	The maximum time to wait for a message to be available, in
+ *		micro-seconds. A value of 0 does not wait at all.
+ * @return 0 if OK, -ENODATA if no message was available, or a negative error
+ * code.
+ */
+int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us);
+
+#endif
diff --git a/include/mailbox_uclass.h b/include/mailbox_uclass.h
new file mode 100644
index 0000000000..6a2994c34c
--- /dev/null
+++ b/include/mailbox_uclass.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _MAILBOX_UCLASS_H
+#define _MAILBOX_UCLASS_H
+
+/* See mailbox_client.h for background documentation. */
+
+#include <mailbox_client.h>
+
+struct udevice;
+
+/**
+ * struct mbox_ops - The functions that a mailbox driver must implement.
+ */
+struct mbox_ops {
+	/**
+	 * of_xlate - Translate a client's device-tree (OF) mailbox specifier.
+	 *
+	 * The mailbox core calls this function as the first step in
+	 * implementing a client's mbox_get_by_*() call.
+	 *
+	 * If this function pointer is set to NULL, the mailbox core will use
+	 * a default implementation, which assumes #mbox-cells = <1>, and that
+	 * the DT cell contains a simple integer channel ID.
+	 *
+	 * At present, the mailbox API solely supports device-tree. If this
+	 * changes, other xxx_xlate() functions may be added to support those
+	 * other mechanisms.
+	 *
+	 * @chan:	The channel to hold the translation result.
+	 * @args:	The mailbox specifier values from device tree.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*of_xlate)(struct mbox_chan *chan,
+			struct fdtdec_phandle_args *args);
+	/**
+	 * request - Request a translated channel.
+	 *
+	 * The mailbox core calls this function as the second step in
+	 * implementing a client's mbox_get_by_*() call, following a successful
+	 * xxx_xlate() call.
+	 *
+	 * @chan:	The channel to request; this has been filled in by a
+	 *		previoux xxx_xlate() function call.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*request)(struct mbox_chan *chan);
+	/**
+	 * free - Free a previously requested channel.
+	 *
+	 * This is the implementation of the client mbox_free() API.
+	 *
+	 * @chan:	The channel to free.
+	 * @return 0 if OK, or a negative error code.
+	 */
+	int (*free)(struct mbox_chan *chan);
+	/**
+	* send - Send a message over a mailbox channel
+	*
+	* @chan:	The channel to send to the message to.
+	* @data:	A pointer to the message to send.
+	* @return 0 if OK, or a negative error code.
+	*/
+	int (*send)(struct mbox_chan *chan, const void *data);
+	/**
+	* recv - Receive any available message from the channel.
+	*
+	* This function does not block. If not message is immediately
+	* available, the function should return an error.
+	*
+	* @chan:	The channel to receive to the message from.
+	* @data:	A pointer to the buffer to hold the received message.
+	* @return 0 if OK, -ENODATA if no message was available, or a negative
+	* error code.
+	*/
+	int (*recv)(struct mbox_chan *chan, void *data);
+};
+
+#endif
diff --git a/include/mmc.h b/include/mmc.h
index a5c6573ddd..7fdfc324fe 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -411,7 +411,6 @@ enum mmc_hwpart_conf_mode {
 	MMC_HWPART_CONF_COMPLETE,
 };
 
-int mmc_register(struct mmc *mmc);
 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
 
 /**
@@ -492,16 +491,12 @@ int mmc_start_init(struct mmc *mmc);
  */
 void mmc_set_preinit(struct mmc *mmc, int preinit);
 
-#ifdef CONFIG_GENERIC_MMC
 #ifdef CONFIG_MMC_SPI
 #define mmc_host_is_spi(mmc)	((mmc)->cfg->host_caps & MMC_MODE_SPI)
 #else
 #define mmc_host_is_spi(mmc)	0
 #endif
 struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
-#else
-int mmc_legacy_init(int verbose);
-#endif
 
 void board_mmc_power_init(void);
 int board_mmc_init(bd_t *bis);
diff --git a/include/nand.h b/include/nand.h
index 7cbbbd327a..a4f0f9253d 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -33,34 +33,36 @@ extern void nand_init(void);
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 
+int nand_mtd_to_devnum(struct mtd_info *mtd);
+
 #ifdef CONFIG_SYS_NAND_SELF_INIT
 void board_nand_init(void);
-int nand_register(int devnum);
+int nand_register(int devnum, struct mtd_info *mtd);
 #else
 extern int board_nand_init(struct nand_chip *nand);
 #endif
 
-typedef struct mtd_info nand_info_t;
-
 extern int nand_curr_device;
-extern nand_info_t nand_info[];
+extern struct mtd_info *nand_info[];
 
-static inline int nand_read(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_read(struct mtd_info *info, loff_t ofs, size_t *len,
+			    u_char *buf)
 {
 	return mtd_read(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_write(nand_info_t *info, loff_t ofs, size_t *len, u_char *buf)
+static inline int nand_write(struct mtd_info *info, loff_t ofs, size_t *len,
+			     u_char *buf)
 {
 	return mtd_write(info, ofs, *len, (size_t *)len, buf);
 }
 
-static inline int nand_block_isbad(nand_info_t *info, loff_t ofs)
+static inline int nand_block_isbad(struct mtd_info *info, loff_t ofs)
 {
 	return mtd_block_isbad(info, ofs);
 }
 
-static inline int nand_erase(nand_info_t *info, loff_t off, size_t size)
+static inline int nand_erase(struct mtd_info *info, loff_t off, size_t size)
 {
 	struct erase_info instr;
 
@@ -96,27 +98,28 @@ struct nand_erase_options {
 
 typedef struct nand_erase_options nand_erase_options_t;
 
-int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
 		       size_t *actual, loff_t lim, u_char *buffer);
 
 #define WITH_DROP_FFS	(1 << 0) /* drop trailing all-0xff pages */
 #define WITH_WR_VERIFY	(1 << 1) /* verify data was written correctly */
 
-int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length,
+int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
 			size_t *actual, loff_t lim, u_char *buffer, int flags);
-int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts);
-int nand_torture(nand_info_t *nand, loff_t offset);
-int nand_verify_page_oob(nand_info_t *nand, struct mtd_oob_ops *ops,
-			loff_t ofs);
-int nand_verify(nand_info_t *nand, loff_t ofs, size_t len, u_char *buf);
+int nand_erase_opts(struct mtd_info *mtd,
+		    const nand_erase_options_t *opts);
+int nand_torture(struct mtd_info *mtd, loff_t offset);
+int nand_verify_page_oob(struct mtd_info *mtd, struct mtd_oob_ops *ops,
+			 loff_t ofs);
+int nand_verify(struct mtd_info *mtd, loff_t ofs, size_t len, u_char *buf);
 
 #define NAND_LOCK_STATUS_TIGHT	0x01
 #define NAND_LOCK_STATUS_UNLOCK 0x04
 
-int nand_lock(nand_info_t *meminfo, int tight);
-int nand_unlock(nand_info_t *meminfo, loff_t start, size_t length,
-	int allexcept);
-int nand_get_lock_status(nand_info_t *meminfo, loff_t offset);
+int nand_lock(struct mtd_info *mtd, int tight);
+int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length,
+		int allexcept);
+int nand_get_lock_status(struct mtd_info *mtd, loff_t offset);
 
 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst);
 void nand_deselect(void);
@@ -135,6 +138,6 @@ __attribute__((noreturn)) void nand_boot(void);
 #define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
 					stored as byte number */
 #define ENV_OFFSET_SIZE 8
-int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+int get_nand_env_oob(struct mtd_info *mtd, unsigned long *result);
 #endif
 int spl_nand_erase_one(int block, int page);
diff --git a/include/net.h b/include/net.h
index 05800c4422..5ee5929beb 100644
--- a/include/net.h
+++ b/include/net.h
@@ -269,7 +269,7 @@ int eth_getenv_enetaddr_by_index(const char *base_name, int index,
 int eth_init(void);			/* Initialize the device */
 int eth_send(void *packet, int length);	   /* Send a packet */
 
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 int eth_receive(void *packet, int length); /* Receive a packet*/
 extern void (*push_packet)(void *packet, int length);
 #endif
diff --git a/include/netdev.h b/include/netdev.h
index 244f23f93c..7a211bc609 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -134,64 +134,6 @@ static inline int pci_eth_init(bd_t *bis)
 	return num;
 }
 
-/*
- * Boards with mv88e61xx switch can use this by defining
- * CONFIG_MV88E61XX_SWITCH in respective board configheader file
- * the stuct and enums here are used to specify switch configuration params
- */
-#if defined(CONFIG_MV88E61XX_SWITCH)
-
-/* constants for any 88E61xx switch */
-#define MV88E61XX_MAX_PORTS_NUM	6
-
-enum mv88e61xx_cfg_mdip {
-	MV88E61XX_MDIP_NOCHANGE,
-	MV88E61XX_MDIP_REVERSE
-};
-
-enum mv88e61xx_cfg_ledinit {
-	MV88E61XX_LED_INIT_DIS,
-	MV88E61XX_LED_INIT_EN
-};
-
-enum mv88e61xx_cfg_rgmiid {
-	MV88E61XX_RGMII_DELAY_DIS,
-	MV88E61XX_RGMII_DELAY_EN
-};
-
-enum mv88e61xx_cfg_prtstt {
-	MV88E61XX_PORTSTT_DISABLED,
-	MV88E61XX_PORTSTT_BLOCKING,
-	MV88E61XX_PORTSTT_LEARNING,
-	MV88E61XX_PORTSTT_FORWARDING
-};
-
-struct mv88e61xx_config {
-	char *name;
-	u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
-	enum mv88e61xx_cfg_rgmiid rgmii_delay;
-	enum mv88e61xx_cfg_prtstt portstate;
-	enum mv88e61xx_cfg_ledinit led_init;
-	enum mv88e61xx_cfg_mdip mdip;
-	u32 ports_enabled;
-	u8 cpuport;
-};
-
-/*
- * Common mappings for Internal VLANs
- * These mappings consider that all ports are useable; the driver
- * will mask inexistent/unused ports.
- */
-
-/* Switch mode : routes any port to any port */
-#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
-
-/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
-#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
-
-int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
-#endif /* CONFIG_MV88E61XX_SWITCH */
-
 struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
 #ifdef CONFIG_PHYLIB
 struct phy_device;
diff --git a/include/phy.h b/include/phy.h
index 21459a8c80..268d9a1823 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -249,6 +249,7 @@ int gen10g_startup(struct phy_device *phydev);
 int gen10g_shutdown(struct phy_device *phydev);
 int gen10g_discover_mmds(struct phy_device *phydev);
 
+int phy_mv88e61xx_init(void);
 int phy_aquantia_init(void);
 int phy_atheros_init(void);
 int phy_broadcom_init(void);
@@ -277,6 +278,28 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
  */
 int phy_get_interface_by_name(const char *str);
 
+/**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
+ * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
+ * is SGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
+{
+	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
+		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
+}
+
 /* PHY UIDs for various PHYs that are referenced in external code */
 #define PHY_UID_CS4340  0x13e51002
 #define PHY_UID_TN2020	0x00a19410
diff --git a/include/power/tps65217.h b/include/power/tps65217.h
index 93cbe36c47..69a49f76fe 100644
--- a/include/power/tps65217.h
+++ b/include/power/tps65217.h
@@ -65,7 +65,10 @@ enum {
 #define TPS65217_USB_INPUT_CUR_LIMIT_1300MA	0x02
 #define TPS65217_USB_INPUT_CUR_LIMIT_1800MA	0x03
 
+#define TPS65217_DCDC_VOLT_SEL_950MV		0x02
+#define TPS65217_DCDC_VOLT_SEL_1100MV		0x08
 #define TPS65217_DCDC_VOLT_SEL_1125MV		0x09
+#define TPS65217_DCDC_VOLT_SEL_1200MV		0x0c
 #define TPS65217_DCDC_VOLT_SEL_1275MV		0x0F
 #define TPS65217_DCDC_VOLT_SEL_1325MV		0x11
 
diff --git a/arch/x86/include/asm/fw_cfg.h b/include/qfw.h
index e9450c6196..b0b3b5945e 100644
--- a/arch/x86/include/asm/fw_cfg.h
+++ b/include/qfw.h
@@ -7,11 +7,6 @@
 #ifndef __FW_CFG__
 #define __FW_CFG__
 
-#define FW_CONTROL_PORT	0x510
-#define FW_DATA_PORT		0x511
-#define FW_DMA_PORT_LOW	0x514
-#define FW_DMA_PORT_HIGH	0x518
-
 #include <linux/list.h>
 
 enum qemu_fwcfg_items {
@@ -87,12 +82,22 @@ struct fw_file {
 	struct list_head list;  /* list node to link to fw_list */
 };
 
+struct fw_cfg_file_iter {
+	struct list_head *entry; /* structure to iterate file list */
+};
+
 struct fw_cfg_dma_access {
 	__be32 control;
 	__be32 length;
 	__be64 address;
 };
 
+struct fw_cfg_arch_ops {
+	void (*arch_read_pio)(uint16_t selector, uint32_t size,
+			void *address);
+	void (*arch_read_dma)(struct fw_cfg_dma_access *dma);
+};
+
 struct bios_linker_entry {
 	__le32 command;
 	union {
@@ -144,8 +149,14 @@ struct bios_linker_entry {
 
 /**
  * Initialize QEMU fw_cfg interface
+ *
+ * @ops: arch specific read operations
  */
-void qemu_fwcfg_init(void);
+void qemu_fwcfg_init(struct fw_cfg_arch_ops *ops);
+
+void qemu_fwcfg_read_entry(uint16_t entry, uint32_t length, void *address);
+int qemu_fwcfg_read_firmware_list(void);
+struct fw_file *qemu_fwcfg_find_file(const char *name);
 
 /**
  * Get system cpu number
@@ -154,4 +165,12 @@ void qemu_fwcfg_init(void);
  */
 int qemu_fwcfg_online_cpus(void);
 
+/* helper functions to iterate firmware file list */
+struct fw_file *qemu_fwcfg_file_iter_init(struct fw_cfg_file_iter *iter);
+struct fw_file *qemu_fwcfg_file_iter_next(struct fw_cfg_file_iter *iter);
+bool qemu_fwcfg_file_iter_end(struct fw_cfg_file_iter *iter);
+
+bool qemu_fwcfg_present(void);
+bool qemu_fwcfg_dma_present(void);
+
 #endif
diff --git a/include/reset.h b/include/reset.h
deleted file mode 100644
index 383761eb1f..0000000000
--- a/include/reset.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Written by Simon Glass <sjg@chromium.org>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __RESET_H
-#define __RESET_H
-
-enum reset_t {
-	RESET_WARM,	/* Reset CPU, keep GPIOs active */
-	RESET_COLD,	/* Reset CPU and GPIOs */
-	RESET_POWER,	/* Reset PMIC (remove and restore power) */
-
-	RESET_COUNT,
-};
-
-struct reset_ops {
-	/**
-	 * request() - request a reset of the given type
-	 *
-	 * Note that this function may return before the reset takes effect.
-	 *
-	 * @type:	Reset type to request
-	 * @return -EINPROGRESS if the reset has been started and
-	 *		will complete soon, -EPROTONOSUPPORT if not supported
-	 *		by this device, 0 if the reset has already happened
-	 *		(in which case this method will not actually return)
-	 */
-	int (*request)(struct udevice *dev, enum reset_t type);
-};
-
-#define reset_get_ops(dev)        ((struct reset_ops *)(dev)->driver->ops)
-
-/**
- * reset_request() - request a reset
- *
- * @type:	Reset type to request
- * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
- */
-int reset_request(struct udevice *dev, enum reset_t type);
-
-/**
- * reset_walk() - cause a reset
- *
- * This works through the available reset devices until it finds one that can
- * perform a reset. If the provided reset type is not available, the next one
- * will be tried.
- *
- * If this function fails to reset, it will display a message and halt
- *
- * @type:	Reset type to request
- * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
- */
-int reset_walk(enum reset_t type);
-
-/**
- * reset_walk_halt() - try to reset, otherwise halt
- *
- * This calls reset_walk(). If it returns, indicating that reset is not
- * supported, it prints a message and halts.
- */
-void reset_walk_halt(enum reset_t type);
-
-/**
- * reset_cpu() - calls reset_walk(RESET_WARM)
- */
-void reset_cpu(ulong addr);
-
-#endif
diff --git a/include/serial.h b/include/serial.h
index e490f9a0cf..47332c5340 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -40,6 +40,10 @@ extern struct serial_device serial1_device;
 
 extern struct serial_device eserial1_device;
 extern struct serial_device eserial2_device;
+extern struct serial_device eserial3_device;
+extern struct serial_device eserial4_device;
+extern struct serial_device eserial5_device;
+extern struct serial_device eserial6_device;
 
 extern void serial_register(struct serial_device *);
 extern void serial_initialize(void);
diff --git a/include/spl.h b/include/spl.h
index 7edfab46dc..0ae160547d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -35,16 +35,28 @@ struct spl_image_info {
  * @dev: Pointer to the device, e.g. struct mmc *
  * @priv: Private data for the device
  * @bl_len: Block length for reading in bytes
+ * @filename: Name of the fit image file.
  * @read: Function to call to read from the device
  */
 struct spl_load_info {
 	void *dev;
 	void *priv;
 	int bl_len;
+	const char *filename;
 	ulong (*read)(struct spl_load_info *load, ulong sector, ulong count,
 		      void *buf);
 };
 
+/**
+ * spl_load_simple_fit() - Loads a fit image from a device.
+ * @info:	Structure containing the information required to load data.
+ * @sector:	Sector number where FIT image is located in the device
+ * @fdt:	Pointer to the copied FIT header.
+ *
+ * Reads the FIT image @sector in the device. Loads u-boot image to
+ * specified load address and copies the dtb to end of u-boot image.
+ * Returns 0 on success.
+ */
 int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt);
 
 #define SPL_COPY_PAYLOAD_ONLY	1
@@ -58,6 +70,7 @@ u32 spl_boot_mode(void);
 void spl_set_header_raw_uboot(void);
 int spl_parse_image_header(const struct image_header *header);
 void spl_board_prepare_for_linux(void);
+void spl_board_prepare_for_boot(void);
 void __noreturn jump_to_image_linux(void *arg);
 int spl_start_uboot(void);
 void spl_display_print(void);
diff --git a/include/sysreset.h b/include/sysreset.h
new file mode 100644
index 0000000000..393c7be3d8
--- /dev/null
+++ b/include/sysreset.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __SYSRESET_H
+#define __SYSRESET_H
+
+enum sysreset_t {
+	SYSRESET_WARM,	/* Reset CPU, keep GPIOs active */
+	SYSRESET_COLD,	/* Reset CPU and GPIOs */
+	SYSRESET_POWER,	/* Reset PMIC (remove and restore power) */
+
+	SYSRESET_COUNT,
+};
+
+struct sysreset_ops {
+	/**
+	 * request() - request a sysreset of the given type
+	 *
+	 * Note that this function may return before the reset takes effect.
+	 *
+	 * @type:	Reset type to request
+	 * @return -EINPROGRESS if the reset has been started and
+	 *		will complete soon, -EPROTONOSUPPORT if not supported
+	 *		by this device, 0 if the reset has already happened
+	 *		(in which case this method will not actually return)
+	 */
+	int (*request)(struct udevice *dev, enum sysreset_t type);
+};
+
+#define sysreset_get_ops(dev)        ((struct sysreset_ops *)(dev)->driver->ops)
+
+/**
+ * sysreset_request() - request a sysreset
+ *
+ * @type:	Reset type to request
+ * @return 0 if OK, -EPROTONOSUPPORT if not supported by this device
+ */
+int sysreset_request(struct udevice *dev, enum sysreset_t type);
+
+/**
+ * sysreset_walk() - cause a system reset
+ *
+ * This works through the available sysreset devices until it finds one that can
+ * perform a reset. If the provided sysreset type is not available, the next one
+ * will be tried.
+ *
+ * If this function fails to reset, it will display a message and halt
+ *
+ * @type:	Reset type to request
+ * @return -EINPROGRESS if a reset is in progress, -ENOSYS if not available
+ */
+int sysreset_walk(enum sysreset_t type);
+
+/**
+ * sysreset_walk_halt() - try to reset, otherwise halt
+ *
+ * This calls sysreset_walk(). If it returns, indicating that reset is not
+ * supported, it prints a message and halts.
+ */
+void sysreset_walk_halt(enum sysreset_t type);
+
+/**
+ * reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
+ */
+void reset_cpu(ulong addr);
+
+#endif
diff --git a/include/video.h b/include/video.h
index c434bc71ae..0d5bd21c60 100644
--- a/include/video.h
+++ b/include/video.h
@@ -23,6 +23,11 @@ struct video_uc_platdata {
 	ulong base;
 };
 
+enum video_polarity {
+	VIDEO_ACTIVE_HIGH,	/* Pins are active high */
+	VIDEO_ACTIVE_LOW,	/* Pins are active low */
+};
+
 /*
  * Bits per pixel selector. Each value n is such that the bits-per-pixel is
  * 2 ^ n
diff --git a/include/watchdog.h b/include/watchdog.h
index 9273fa1e80..174c894e49 100644
--- a/include/watchdog.h
+++ b/include/watchdog.h
@@ -21,8 +21,7 @@
 int init_func_watchdog_reset(void);
 #endif
 
-#if defined(CONFIG_SYS_GENERIC_BOARD) && \
-	(defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG))
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
 #define INIT_FUNC_WATCHDOG_INIT	init_func_watchdog_init,
 #define INIT_FUNC_WATCHDOG_RESET	init_func_watchdog_reset,
 #else
diff --git a/lib/Kconfig b/lib/Kconfig
index 2b97c2b0a4..02ca4058d3 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -14,6 +14,7 @@ config HAVE_PRIVATE_LIBGCC
 config USE_PRIVATE_LIBGCC
 	bool "Use private libgcc"
 	depends on HAVE_PRIVATE_LIBGCC
+	default y if HAVE_PRIVATE_LIBGCC && ((ARM && !ARM64) || MIPS)
 	help
 	  This option allows you to use the built-in libgcc implementation
 	  of U-Boot instead of the one provided by the compiler.
diff --git a/lib/Makefile b/lib/Makefile
index 02dfa29507..f77befe03c 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -42,7 +42,6 @@ obj-y += rc4.o
 obj-$(CONFIG_SHA1) += sha1.o
 obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
 obj-$(CONFIG_SHA256) += sha256.o
-obj-y	+= strmhz.o
 obj-$(CONFIG_TPM) += tpm.o
 obj-$(CONFIG_RBTREE)	+= rbtree.o
 obj-$(CONFIG_BITREVERSE) += bitrev.o
@@ -85,11 +84,11 @@ ifdef CONFIG_SPL_BUILD
 ifdef CONFIG_USE_TINY_PRINTF
 obj-$(CONFIG_SPL_SERIAL_SUPPORT) += tiny-printf.o panic.o strto.o
 else
-obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o
+obj-$(CONFIG_SPL_SERIAL_SUPPORT) += vsprintf.o panic.o strto.o strmhz.o
 endif
 else
 # Main U-Boot always uses the full printf support
-obj-y += vsprintf.o panic.o strto.o
+obj-y += vsprintf.o panic.o strto.o strmhz.o
 endif
 
 subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 14c99ec9cf..37a0dd60a5 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -7,3 +7,12 @@ config EFI_LOADER
 	  on top of U-Boot. If this option is enabled, U-Boot will expose EFI
 	  interfaces to a loaded EFI application, enabling it to reuse U-Boot's
 	  device drivers.
+
+config EFI_LOADER_BOUNCE_BUFFER
+	bool "EFI Applications use bounce buffers for DMA operations"
+	depends on EFI_LOADER && ARM64
+	default n
+	help
+	  Some hardware does not support DMA to full 64bit addresses. For this
+	  hardware we can create a bounce buffer so that payloads don't have to
+	  worry about platform details.
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 83e31f6d1f..2a3849e31b 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -11,3 +11,4 @@ obj-y += efi_image_loader.o efi_boottime.o efi_runtime.o efi_console.o
 obj-y += efi_memory.o
 obj-$(CONFIG_LCD) += efi_gop.o
 obj-$(CONFIG_PARTITIONS) += efi_disk.o
+obj-$(CONFIG_NET) += efi_net.o
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index 9daca50a72..be6f5e8112 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -6,8 +6,6 @@
  *  SPDX-License-Identifier:     GPL-2.0+
  */
 
-/* #define DEBUG_EFI */
-
 #include <common.h>
 #include <efi_loader.h>
 #include <malloc.h>
@@ -76,9 +74,7 @@ efi_status_t efi_exit_func(efi_status_t ret)
 
 static efi_status_t efi_unsupported(const char *funcname)
 {
-#ifdef DEBUG_EFI
-	printf("EFI: App called into unimplemented function %s\n", funcname);
-#endif
+	debug("EFI: App called into unimplemented function %s\n", funcname);
 	return EFI_EXIT(EFI_UNSUPPORTED);
 }
 
@@ -458,19 +454,30 @@ static efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle,
 	efi_is_direct_boot = false;
 
 	/* call the image! */
+	if (setjmp(&info->exit_jmp)) {
+		/* We returned from the child image */
+		return EFI_EXIT(info->exit_status);
+	}
+
 	entry(image_handle, &systab);
 
 	/* Should usually never get here */
 	return EFI_EXIT(EFI_SUCCESS);
 }
 
-static efi_status_t EFIAPI efi_exit(void *image_handle, long exit_status,
-				    unsigned long exit_data_size,
-				    uint16_t *exit_data)
+static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle,
+			efi_status_t exit_status, unsigned long exit_data_size,
+			int16_t *exit_data)
 {
+	struct efi_loaded_image *loaded_image_info = (void*)image_handle;
+
 	EFI_ENTRY("%p, %ld, %ld, %p", image_handle, exit_status,
 		  exit_data_size, exit_data);
-	return EFI_EXIT(efi_unsupported(__func__));
+
+	loaded_image_info->exit_status = exit_status;
+	longjmp(&loaded_image_info->exit_jmp);
+
+	panic("EFI application exited");
 }
 
 static struct efi_object *efi_search_obj(void *handle)
@@ -746,7 +753,7 @@ static const struct efi_boot_services efi_boot_services = {
 	.install_configuration_table = efi_install_configuration_table,
 	.load_image = efi_load_image,
 	.start_image = efi_start_image,
-	.exit = (void*)efi_exit,
+	.exit = efi_exit,
 	.unload_image = efi_unload_image,
 	.exit_boot_services = efi_exit_boot_services,
 	.get_next_monotonic_count = efi_get_next_monotonic_count,
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index 075fd34014..c434c92250 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <blk.h>
+#include <dm.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <part.h>
@@ -76,9 +77,6 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	int blocks;
 	unsigned long n;
 
-	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
-		  buffer_size, buffer);
-
 	diskobj = container_of(this, struct efi_disk_obj, ops);
 	if (!(desc = blk_get_dev(diskobj->ifname, diskobj->dev_index)))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
@@ -86,26 +84,23 @@ static efi_status_t EFIAPI efi_disk_rw_blocks(struct efi_block_io *this,
 	blocks = buffer_size / blksz;
 	lba += diskobj->offset;
 
-#ifdef DEBUG_EFI
-	printf("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
-	       __LINE__, blocks, lba, blksz, direction);
-#endif
+	debug("EFI: %s:%d blocks=%x lba=%"PRIx64" blksz=%x dir=%d\n", __func__,
+	      __LINE__, blocks, lba, blksz, direction);
 
 	/* We only support full block access */
 	if (buffer_size & (blksz - 1))
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
 	if (direction == EFI_DISK_READ)
-		n = desc->block_read(desc, lba, blocks, buffer);
+		n = blk_dread(desc, lba, blocks, buffer);
 	else
-		n = desc->block_write(desc, lba, blocks, buffer);
+		n = blk_dwrite(desc, lba, blocks, buffer);
 
 	/* We don't do interrupts, so check for timers cooperatively */
 	efi_timer_check();
 
-#ifdef DEBUG_EFI
-	printf("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
-#endif
+	debug("EFI: %s:%d n=%lx blocks=%x\n", __func__, __LINE__, n, blocks);
+
 	if (n != blocks)
 		return EFI_EXIT(EFI_DEVICE_ERROR);
 
@@ -116,16 +111,70 @@ static efi_status_t efi_disk_read_blocks(struct efi_block_io *this,
 			u32 media_id, u64 lba, unsigned long buffer_size,
 			void *buffer)
 {
-	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
-				  EFI_DISK_READ);
+	void *real_buffer = buffer;
+	efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+		r = efi_disk_read_blocks(this, media_id, lba,
+			EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+		if (r != EFI_SUCCESS)
+			return r;
+		return efi_disk_read_blocks(this, media_id, lba +
+			EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+			buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+			buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+	}
+
+	real_buffer = efi_bounce_buffer;
+#endif
+
+	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+		  buffer_size, buffer);
+
+	r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+			       EFI_DISK_READ);
+
+	/* Copy from bounce buffer to real buffer if necessary */
+	if ((r == EFI_SUCCESS) && (real_buffer != buffer))
+		memcpy(buffer, real_buffer, buffer_size);
+
+	return EFI_EXIT(r);
 }
 
 static efi_status_t efi_disk_write_blocks(struct efi_block_io *this,
 			u32 media_id, u64 lba, unsigned long buffer_size,
 			void *buffer)
 {
-	return efi_disk_rw_blocks(this, media_id, lba, buffer_size, buffer,
-				  EFI_DISK_WRITE);
+	void *real_buffer = buffer;
+	efi_status_t r;
+
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	if (buffer_size > EFI_LOADER_BOUNCE_BUFFER_SIZE) {
+		r = efi_disk_write_blocks(this, media_id, lba,
+			EFI_LOADER_BOUNCE_BUFFER_SIZE, buffer);
+		if (r != EFI_SUCCESS)
+			return r;
+		return efi_disk_write_blocks(this, media_id, lba +
+			EFI_LOADER_BOUNCE_BUFFER_SIZE / this->media->block_size,
+			buffer_size - EFI_LOADER_BOUNCE_BUFFER_SIZE,
+			buffer + EFI_LOADER_BOUNCE_BUFFER_SIZE);
+	}
+
+	real_buffer = efi_bounce_buffer;
+#endif
+
+	EFI_ENTRY("%p, %x, %"PRIx64", %lx, %p", this, media_id, lba,
+		  buffer_size, buffer);
+
+	/* Populate bounce buffer if necessary */
+	if (real_buffer != buffer)
+		memcpy(real_buffer, buffer, buffer_size);
+
+	r = efi_disk_rw_blocks(this, media_id, lba, buffer_size, real_buffer,
+			       EFI_DISK_WRITE);
+
+	return EFI_EXIT(r);
 }
 
 static efi_status_t EFIAPI efi_disk_flush_blocks(struct efi_block_io *this)
@@ -142,8 +191,8 @@ static const struct efi_block_io block_io_disk_template = {
 	.flush_blocks = &efi_disk_flush_blocks,
 };
 
-static void efi_disk_add_dev(char *name,
-			     const struct blk_driver *cur_drvr,
+static void efi_disk_add_dev(const char *name,
+			     const char *if_typename,
 			     const struct blk_desc *desc,
 			     int dev_index,
 			     lbaint_t offset)
@@ -161,7 +210,7 @@ static void efi_disk_add_dev(char *name,
 	diskobj->parent.protocols[1].open = efi_disk_open_dp;
 	diskobj->parent.handle = diskobj;
 	diskobj->ops = block_io_disk_template;
-	diskobj->ifname = cur_drvr->if_typename;
+	diskobj->ifname = if_typename;
 	diskobj->dev_index = dev_index;
 	diskobj->offset = offset;
 
@@ -190,7 +239,7 @@ static void efi_disk_add_dev(char *name,
 }
 
 static int efi_disk_create_eltorito(struct blk_desc *desc,
-				    const struct blk_driver *cur_drvr,
+				    const char *if_typename,
 				    int diskid)
 {
 	int disks = 0;
@@ -203,9 +252,10 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
 		return 0;
 
 	while (!part_get_info(desc, part, &info)) {
-		snprintf(devname, sizeof(devname), "%s%d:%d",
-			 cur_drvr->if_typename, diskid, part);
-		efi_disk_add_dev(devname, cur_drvr, desc, diskid, info.start);
+		snprintf(devname, sizeof(devname), "%s%d:%d", if_typename,
+			 diskid, part);
+		efi_disk_add_dev(devname, if_typename, desc, diskid,
+				 info.start);
 		part++;
 		disks++;
 	}
@@ -219,21 +269,49 @@ static int efi_disk_create_eltorito(struct blk_desc *desc,
  * EFI payload, we scan through all of the potentially available ones and
  * store them in our object pool.
  *
+ * TODO(sjg@chromium.org): Actually with CONFIG_BLK, U-Boot does have this.
+ * Consider converting the code to look up devices as needed. The EFI device
+ * could be a child of the UCLASS_BLK block device, perhaps.
+ *
  * This gets called from do_bootefi_exec().
  */
 int efi_disk_register(void)
 {
-	const struct blk_driver *cur_drvr;
-	int i, if_type;
 	int disks = 0;
+#ifdef CONFIG_BLK
+	struct udevice *dev;
+
+	for (uclass_first_device(UCLASS_BLK, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct blk_desc *desc = dev_get_uclass_platdata(dev);
+		const char *if_typename = dev->driver->name;
+
+		printf("Scanning disk %s...\n", dev->name);
+		efi_disk_add_dev(dev->name, if_typename, desc, desc->devnum, 0);
+		disks++;
+
+		/*
+		* El Torito images show up as block devices in an EFI world,
+		* so let's create them here
+		*/
+		disks += efi_disk_create_eltorito(desc, if_typename,
+						  desc->devnum);
+	}
+#else
+	int i, if_type;
 
 	/* Search for all available disk devices */
 	for (if_type = 0; if_type < IF_TYPE_COUNT; if_type++) {
+		const struct blk_driver *cur_drvr;
+		const char *if_typename;
+
 		cur_drvr = blk_driver_lookup_type(if_type);
 		if (!cur_drvr)
 			continue;
 
-		printf("Scanning disks on %s...\n", cur_drvr->if_typename);
+		if_typename = cur_drvr->if_typename;
+		printf("Scanning disks on %s...\n", if_typename);
 		for (i = 0; i < 4; i++) {
 			struct blk_desc *desc;
 			char devname[32] = { 0 }; /* dp->str is u16[32] long */
@@ -245,17 +323,18 @@ int efi_disk_register(void)
 				continue;
 
 			snprintf(devname, sizeof(devname), "%s%d",
-				 cur_drvr->if_typename, i);
-			efi_disk_add_dev(devname, cur_drvr, desc, i, 0);
+				 if_typename, i);
+			efi_disk_add_dev(devname, if_typename, desc, i, 0);
 			disks++;
 
 			/*
 			 * El Torito images show up as block devices
 			 * in an EFI world, so let's create them here
 			 */
-			disks += efi_disk_create_eltorito(desc, cur_drvr, i);
+			disks += efi_disk_create_eltorito(desc, if_typename, i);
 		}
 	}
+#endif
 	printf("Found %d disks\n", disks);
 
 	return 0;
diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c
index bdd62bc557..33a3d71767 100644
--- a/lib/efi_loader/efi_gop.c
+++ b/lib/efi_loader/efi_gop.c
@@ -7,10 +7,12 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <efi_loader.h>
 #include <inttypes.h>
 #include <lcd.h>
 #include <malloc.h>
+#include <video.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -24,6 +26,8 @@ struct efi_gop_obj {
 	/* The only mode we support */
 	struct efi_gop_mode_info info;
 	struct efi_gop_mode mode;
+	/* Fields we only have acces to during init */
+	u32 bpix;
 };
 
 static efi_status_t EFIAPI gop_query_mode(struct efi_gop *this, u32 mode_number,
@@ -57,6 +61,7 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 				   unsigned long dy, unsigned long width,
 				   unsigned long height, unsigned long delta)
 {
+	struct efi_gop_obj *gopobj = container_of(this, struct efi_gop_obj, ops);
 	int i, j, line_len16, line_len32;
 	void *fb;
 
@@ -67,13 +72,17 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 		return EFI_EXIT(EFI_INVALID_PARAMETER);
 
 	fb = (void*)gd->fb_base;
-	line_len16 = panel_info.vl_col * sizeof(u16);
-	line_len32 = panel_info.vl_col * sizeof(u32);
+	line_len16 = gopobj->info.width * sizeof(u16);
+	line_len32 = gopobj->info.width * sizeof(u32);
 
 	/* Copy the contents line by line */
 
-	switch (panel_info.vl_bpix) {
+	switch (gopobj->bpix) {
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP32:
+#else
 	case LCD_COLOR32:
+#endif
 		for (i = 0; i < height; i++) {
 			u32 *dest = fb + ((i + dy)  * line_len32) +
 					 (dx * sizeof(u32));
@@ -84,7 +93,11 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 			memcpy(dest, src, width * sizeof(u32));
 		}
 		break;
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP16:
+#else
 	case LCD_COLOR16:
+#endif
 		for (i = 0; i < height; i++) {
 			u16 *dest = fb + ((i + dy)  * line_len16) +
 					 (dx * sizeof(u16));
@@ -102,7 +115,11 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 		break;
 	}
 
+#ifdef CONFIG_DM_VIDEO
+	video_sync_all();
+#else
 	lcd_sync();
+#endif
 
 	return EFI_EXIT(EFI_SUCCESS);
 }
@@ -111,11 +128,34 @@ static efi_status_t EFIAPI gop_blt(struct efi_gop *this, void *buffer,
 int efi_gop_register(void)
 {
 	struct efi_gop_obj *gopobj;
-	int line_len;
+	u32 bpix, col, row;
 
-	switch (panel_info.vl_bpix) {
+#ifdef CONFIG_DM_VIDEO
+	struct udevice *vdev;
+
+	/* We only support a single video output device for now */
+	if (uclass_first_device(UCLASS_VIDEO, &vdev))
+		return -1;
+
+	struct video_priv *priv = dev_get_uclass_priv(vdev);
+	bpix = priv->bpix;
+	col = video_get_xsize(vdev);
+	row = video_get_ysize(vdev);
+#else
+
+	bpix = panel_info.vl_bpix;
+	col = panel_info.vl_col;
+	row = panel_info.vl_row;
+#endif
+
+	switch (bpix) {
+#ifdef CONFIG_DM_VIDEO
+	case VIDEO_BPP16:
+	case VIDEO_BPP32:
+#else
 	case LCD_COLOR32:
 	case LCD_COLOR16:
+#endif
 		break;
 	default:
 		/* So far, we only work in 16 or 32 bit mode */
@@ -136,14 +176,14 @@ int efi_gop_register(void)
 	gopobj->mode.max_mode = 1;
 	gopobj->mode.info = &gopobj->info;
 	gopobj->mode.info_size = sizeof(gopobj->info);
-	gopobj->mode.fb_base = gd->fb_base;
-	gopobj->mode.fb_size = lcd_get_size(&line_len);
 
 	gopobj->info.version = 0;
-	gopobj->info.width = panel_info.vl_col;
-	gopobj->info.height = panel_info.vl_row;
+	gopobj->info.width = col;
+	gopobj->info.height = row;
 	gopobj->info.pixel_format = EFI_GOT_RGBA8;
-	gopobj->info.pixels_per_scanline = panel_info.vl_col;
+	gopobj->info.pixels_per_scanline = col;
+
+	gopobj->bpix = bpix;
 
 	/* Hook up to the device list */
 	list_add_tail(&gopobj->parent.link, &efi_obj_list);
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 71a3d19269..df2381e42c 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -6,8 +6,6 @@
  *  SPDX-License-Identifier:     GPL-2.0+
  */
 
-/* #define DEBUG_EFI */
-
 #include <common.h>
 #include <efi_loader.h>
 #include <malloc.h>
@@ -24,9 +22,17 @@ struct efi_mem_list {
 	struct efi_mem_desc desc;
 };
 
+#define EFI_CARVE_NO_OVERLAP		-1
+#define EFI_CARVE_LOOP_AGAIN		-2
+#define EFI_CARVE_OVERLAPS_NONRAM	-3
+
 /* This list contains all memory map items */
 LIST_HEAD(efi_mem);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+void *efi_bounce_buffer;
+#endif
+
 /*
  * Sorts the memory list from highest address to lowest address
  *
@@ -74,11 +80,11 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 
 	/* check whether we're overlapping */
 	if ((carve_end <= map_start) || (carve_start >= map_end))
-		return 0;
+		return EFI_CARVE_NO_OVERLAP;
 
 	/* We're overlapping with non-RAM, warn the caller if desired */
 	if (overlap_only_ram && (map_desc->type != EFI_CONVENTIONAL_MEMORY))
-		return -1;
+		return EFI_CARVE_OVERLAPS_NONRAM;
 
 	/* Sanitize carve_start and carve_end to lie within our bounds */
 	carve_start = max(carve_start, map_start);
@@ -93,7 +99,7 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 
 		map_desc->physical_start = carve_end;
 		map_desc->num_pages = (map_end - carve_end) >> EFI_PAGE_SHIFT;
-		return 1;
+		return (carve_end - carve_start) >> EFI_PAGE_SHIFT;
 	}
 
 	/*
@@ -113,7 +119,7 @@ static int efi_mem_carve_out(struct efi_mem_list *map,
 	/* Shrink the map to [ map_start ... carve_start ] */
 	map_desc->num_pages = (carve_start - map_start) >> EFI_PAGE_SHIFT;
 
-	return 1;
+	return EFI_CARVE_LOOP_AGAIN;
 }
 
 uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
@@ -121,7 +127,8 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 {
 	struct list_head *lhandle;
 	struct efi_mem_list *newlist;
-	bool do_carving;
+	bool carve_again;
+	uint64_t carved_pages = 0;
 
 	if (!pages)
 		return start;
@@ -148,7 +155,7 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 
 	/* Add our new map */
 	do {
-		do_carving = false;
+		carve_again = false;
 		list_for_each(lhandle, &efi_mem) {
 			struct efi_mem_list *lmem;
 			int r;
@@ -156,14 +163,44 @@ uint64_t efi_add_memory_map(uint64_t start, uint64_t pages, int memory_type,
 			lmem = list_entry(lhandle, struct efi_mem_list, link);
 			r = efi_mem_carve_out(lmem, &newlist->desc,
 					      overlap_only_ram);
-			if (r < 0) {
+			switch (r) {
+			case EFI_CARVE_OVERLAPS_NONRAM:
+				/*
+				 * The user requested to only have RAM overlaps,
+				 * but we hit a non-RAM region. Error out.
+				 */
 				return 0;
-			} else if (r) {
-				do_carving = true;
+			case EFI_CARVE_NO_OVERLAP:
+				/* Just ignore this list entry */
+				break;
+			case EFI_CARVE_LOOP_AGAIN:
+				/*
+				 * We split an entry, but need to loop through
+				 * the list again to actually carve it.
+				 */
+				carve_again = true;
+				break;
+			default:
+				/* We carved a number of pages */
+				carved_pages += r;
+				carve_again = true;
+				break;
+			}
+
+			if (carve_again) {
+				/* The list changed, we need to start over */
 				break;
 			}
 		}
-	} while (do_carving);
+	} while (carve_again);
+
+	if (overlap_only_ram && (carved_pages != pages)) {
+		/*
+		 * The payload wanted to have RAM overlaps, but we overlapped
+		 * with an unallocated region. Error out.
+		 */
+		return 0;
+	}
 
 	/* Add our new map */
         list_add_tail(&newlist->link, &efi_mem);
@@ -349,5 +386,17 @@ int efi_memory_init(void)
 	efi_add_memory_map(runtime_start, runtime_pages,
 			   EFI_RUNTIME_SERVICES_CODE, false);
 
+#ifdef CONFIG_EFI_LOADER_BOUNCE_BUFFER
+	/* Request a 32bit 64MB bounce buffer region */
+	uint64_t efi_bounce_buffer_addr = 0xffffffff;
+
+	if (efi_allocate_pages(1, EFI_LOADER_DATA,
+			       (64 * 1024 * 1024) >> EFI_PAGE_SHIFT,
+			       &efi_bounce_buffer_addr) != EFI_SUCCESS)
+		return -1;
+
+	efi_bounce_buffer = (void*)(uintptr_t)efi_bounce_buffer_addr;
+#endif
+
 	return 0;
 }
diff --git a/lib/efi_loader/efi_net.c b/lib/efi_loader/efi_net.c
new file mode 100644
index 0000000000..dd3b48570d
--- /dev/null
+++ b/lib/efi_loader/efi_net.c
@@ -0,0 +1,291 @@
+/*
+ *  EFI application network access support
+ *
+ *  Copyright (c) 2016 Alexander Graf
+ *
+ *  SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <efi_loader.h>
+#include <inttypes.h>
+#include <lcd.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const efi_guid_t efi_net_guid = EFI_SIMPLE_NETWORK_GUID;
+static const efi_guid_t efi_pxe_guid = EFI_PXE_GUID;
+static struct efi_pxe_packet *dhcp_ack;
+static bool new_rx_packet;
+static void *new_tx_packet;
+
+struct efi_net_obj {
+	/* Generic EFI object parent class data */
+	struct efi_object parent;
+	/* EFI Interface callback struct for network */
+	struct efi_simple_network net;
+	struct efi_simple_network_mode net_mode;
+	/* Device path to the network adapter */
+	struct efi_device_path_file_path dp[2];
+	/* PXE struct to transmit dhcp data */
+	struct efi_pxe pxe;
+	struct efi_pxe_mode pxe_mode;
+};
+
+static efi_status_t EFIAPI efi_net_start(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_stop(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_initialize(struct efi_simple_network *this,
+					      ulong extra_rx, ulong extra_tx)
+{
+	EFI_ENTRY("%p, %lx, %lx", this, extra_rx, extra_tx);
+
+	eth_init();
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_reset(struct efi_simple_network *this,
+					 int extended_verification)
+{
+	EFI_ENTRY("%p, %x", this, extended_verification);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_shutdown(struct efi_simple_network *this)
+{
+	EFI_ENTRY("%p", this);
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_receive_filters(
+		struct efi_simple_network *this, u32 enable, u32 disable,
+		int reset_mcast_filter, ulong mcast_filter_count,
+		struct efi_mac_address *mcast_filter)
+{
+	EFI_ENTRY("%p, %x, %x, %x, %lx, %p", this, enable, disable,
+		  reset_mcast_filter, mcast_filter_count, mcast_filter);
+
+	/* XXX Do we care? */
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_station_address(
+		struct efi_simple_network *this, int reset,
+		struct efi_mac_address *new_mac)
+{
+	EFI_ENTRY("%p, %x, %p", this, reset, new_mac);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_statistics(struct efi_simple_network *this,
+					      int reset, ulong *stat_size,
+					      void *stat_table)
+{
+	EFI_ENTRY("%p, %x, %p, %p", this, reset, stat_size, stat_table);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_mcastiptomac(struct efi_simple_network *this,
+						int ipv6,
+						struct efi_ip_address *ip,
+						struct efi_mac_address *mac)
+{
+	EFI_ENTRY("%p, %x, %p, %p", this, ipv6, ip, mac);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_nvdata(struct efi_simple_network *this,
+					  int read_write, ulong offset,
+					  ulong buffer_size, char *buffer)
+{
+	EFI_ENTRY("%p, %x, %lx, %lx, %p", this, read_write, offset, buffer_size,
+		  buffer);
+
+	return EFI_EXIT(EFI_INVALID_PARAMETER);
+}
+
+static efi_status_t EFIAPI efi_net_get_status(struct efi_simple_network *this,
+					      u32 *int_status, void **txbuf)
+{
+	EFI_ENTRY("%p, %p, %p", this, int_status, txbuf);
+
+	/* We send packets synchronously, so nothing is outstanding */
+	if (int_status)
+		*int_status = 0;
+	if (txbuf)
+		*txbuf = new_tx_packet;
+
+	new_tx_packet = NULL;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t EFIAPI efi_net_transmit(struct efi_simple_network *this,
+		ulong header_size, ulong buffer_size, void *buffer,
+		struct efi_mac_address *src_addr,
+		struct efi_mac_address *dest_addr, u16 *protocol)
+{
+	EFI_ENTRY("%p, %lx, %lx, %p, %p, %p, %p", this, header_size,
+		  buffer_size, buffer, src_addr, dest_addr, protocol);
+
+	if (header_size) {
+		/* We would need to create the header if header_size != 0 */
+		return EFI_EXIT(EFI_INVALID_PARAMETER);
+	}
+
+	net_send_packet(buffer, buffer_size);
+	new_tx_packet = buffer;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static void efi_net_push(void *pkt, int len)
+{
+	new_rx_packet = true;
+}
+
+static efi_status_t EFIAPI efi_net_receive(struct efi_simple_network *this,
+		ulong *header_size, ulong *buffer_size, void *buffer,
+		struct efi_mac_address *src_addr,
+		struct efi_mac_address *dest_addr, u16 *protocol)
+{
+	EFI_ENTRY("%p, %p, %p, %p, %p, %p, %p", this, header_size,
+		  buffer_size, buffer, src_addr, dest_addr, protocol);
+
+	push_packet = efi_net_push;
+	eth_rx();
+	push_packet = NULL;
+
+	if (!new_rx_packet)
+		return EFI_EXIT(EFI_NOT_READY);
+
+	if (*buffer_size < net_rx_packet_len) {
+		/* Packet doesn't fit, try again with bigger buf */
+		*buffer_size = net_rx_packet_len;
+		return EFI_EXIT(EFI_BUFFER_TOO_SMALL);
+	}
+
+	memcpy(buffer, net_rx_packet, net_rx_packet_len);
+	*buffer_size = net_rx_packet_len;
+	new_rx_packet = false;
+
+	return EFI_EXIT(EFI_SUCCESS);
+}
+
+static efi_status_t efi_net_open_dp(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_simple_network *net = handle;
+	struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+	*protocol_interface = netobj->dp;
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t efi_net_open_pxe(void *handle, efi_guid_t *protocol,
+			void **protocol_interface, void *agent_handle,
+			void *controller_handle, uint32_t attributes)
+{
+	struct efi_simple_network *net = handle;
+	struct efi_net_obj *netobj = container_of(net, struct efi_net_obj, net);
+
+	*protocol_interface = &netobj->pxe;
+
+	return EFI_SUCCESS;
+}
+
+void efi_net_set_dhcp_ack(void *pkt, int len)
+{
+	int maxsize = sizeof(*dhcp_ack);
+
+	if (!dhcp_ack)
+		dhcp_ack = malloc(maxsize);
+
+	memcpy(dhcp_ack, pkt, min(len, maxsize));
+}
+
+/* This gets called from do_bootefi_exec(). */
+int efi_net_register(void **handle)
+{
+	struct efi_net_obj *netobj;
+	struct efi_device_path_file_path dp_net = {
+		.dp.type = DEVICE_PATH_TYPE_MEDIA_DEVICE,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_FILE_PATH,
+		.dp.length = sizeof(dp_net),
+		.str = { 'N', 'e', 't' },
+	};
+	struct efi_device_path_file_path dp_end = {
+		.dp.type = DEVICE_PATH_TYPE_END,
+		.dp.sub_type = DEVICE_PATH_SUB_TYPE_END,
+		.dp.length = sizeof(dp_end),
+	};
+
+	if (!eth_get_dev()) {
+		/* No eth device active, don't expose any */
+		return 0;
+	}
+
+	/* We only expose the "active" eth device, so one is enough */
+	netobj = calloc(1, sizeof(*netobj));
+
+	/* Fill in object data */
+	netobj->parent.protocols[0].guid = &efi_net_guid;
+	netobj->parent.protocols[0].open = efi_return_handle;
+	netobj->parent.protocols[1].guid = &efi_guid_device_path;
+	netobj->parent.protocols[1].open = efi_net_open_dp;
+	netobj->parent.protocols[2].guid = &efi_pxe_guid;
+	netobj->parent.protocols[2].open = efi_net_open_pxe;
+	netobj->parent.handle = &netobj->net;
+	netobj->net.start = efi_net_start;
+	netobj->net.stop = efi_net_stop;
+	netobj->net.initialize = efi_net_initialize;
+	netobj->net.reset = efi_net_reset;
+	netobj->net.shutdown = efi_net_shutdown;
+	netobj->net.receive_filters = efi_net_receive_filters;
+	netobj->net.station_address = efi_net_station_address;
+	netobj->net.statistics = efi_net_statistics;
+	netobj->net.mcastiptomac = efi_net_mcastiptomac;
+	netobj->net.nvdata = efi_net_nvdata;
+	netobj->net.get_status = efi_net_get_status;
+	netobj->net.transmit = efi_net_transmit;
+	netobj->net.receive = efi_net_receive;
+	netobj->net.mode = &netobj->net_mode;
+	netobj->net_mode.state = EFI_NETWORK_STARTED;
+	netobj->dp[0] = dp_net;
+	netobj->dp[1] = dp_end;
+	memcpy(netobj->net_mode.current_address.mac_addr, eth_get_ethaddr(), 6);
+	netobj->net_mode.max_packet_size = PKTSIZE;
+
+	netobj->pxe.mode = &netobj->pxe_mode;
+	if (dhcp_ack)
+		netobj->pxe_mode.dhcp_ack = *dhcp_ack;
+
+	/* Hook net up to the device list */
+	list_add_tail(&netobj->parent.link, &efi_obj_list);
+
+	if (handle)
+		*handle = &netobj->net;
+
+	return 0;
+}
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 3ee27ca9cc..99b5ef11c2 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -125,6 +125,22 @@ static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
 		/* RTC accessors are gone */
 		.ptr = &efi_runtime_services.get_time,
 		.patchto = &efi_device_error,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.con_in,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.con_out,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.std_err,
+		.patchto = NULL,
+	}, {
+		/* Clean up system table */
+		.ptr = &systab.boottime,
+		.patchto = NULL,
 	},
 };
 
@@ -149,9 +165,7 @@ static void efi_runtime_detach(ulong offset)
 		ulong *p = efi_runtime_detach_list[i].ptr;
 		ulong newaddr = patchto ? (patchto + patchoff) : 0;
 
-#ifdef DEBUG_EFI
-		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
+		debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
 		*p = newaddr;
 	}
 }
@@ -166,10 +180,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
 	static ulong lastoff = CONFIG_SYS_TEXT_BASE;
 #endif
 
-#ifdef DEBUG_EFI
-	printf("%s: Relocating to offset=%lx\n", __func__, offset);
-#endif
-
+	debug("%s: Relocating to offset=%lx\n", __func__, offset);
 	for (; (ulong)rel < (ulong)&__efi_runtime_rel_stop; rel++) {
 		ulong base = CONFIG_SYS_TEXT_BASE;
 		ulong *p;
@@ -196,10 +207,7 @@ void efi_runtime_relocate(ulong offset, struct efi_mem_desc *map)
 			continue;
 		}
 
-#ifdef DEBUG_EFI
-		printf("%s: Setting %p to %lx\n", __func__, p, newaddr);
-#endif
-
+		debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
 		*p = newaddr;
 		flush_dcache_range((ulong)p & ~(EFI_CACHELINE_SIZE - 1),
 			ALIGN((ulong)&p[1], EFI_CACHELINE_SIZE));
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 70acc29c92..ab002e9fa3 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -30,6 +30,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
 	COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
 	COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
+	COMPAT(NVIDIA_TEGRA186_SDMMC, "nvidia,tegra186-sdhci"),
 	COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
 	COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
 	COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
diff --git a/lib/string.c b/lib/string.c
index 87c9a408e6..67d5f6a421 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -461,30 +461,6 @@ void * memset(void * s,int c,size_t count)
 }
 #endif
 
-#ifndef __HAVE_ARCH_BCOPY
-/**
- * bcopy - Copy one area of memory to another
- * @src: Where to copy from
- * @dest: Where to copy to
- * @count: The size of the area.
- *
- * Note that this is the same as memcpy(), with the arguments reversed.
- * memcpy() is the standard, bcopy() is a legacy BSD function.
- *
- * You should not use this function to access IO space, use memcpy_toio()
- * or memcpy_fromio() instead.
- */
-char * bcopy(const char * src, char * dest, int count)
-{
-	char *tmp = dest;
-
-	while (count--)
-		*tmp++ = *src++;
-
-	return dest;
-}
-#endif
-
 #ifndef __HAVE_ARCH_MEMCPY
 /**
  * memcpy - Copy one area of memory to another
diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c
index a06abed495..3c65fc90bf 100644
--- a/lib/tiny-printf.c
+++ b/lib/tiny-printf.c
@@ -16,6 +16,9 @@
 static char *bf;
 static char zs;
 
+/* Current position in sprintf() output string */
+static char *outstr;
+
 static void out(char c)
 {
 	*bf++ = c;
@@ -40,7 +43,7 @@ static void div_out(unsigned int *num, unsigned int div)
 		out_dgt(dgt);
 }
 
-int vprintf(const char *fmt, va_list va)
+int _vprintf(const char *fmt, va_list va, void (*putc)(const char ch))
 {
 	char ch;
 	char *p;
@@ -52,8 +55,8 @@ int vprintf(const char *fmt, va_list va)
 		if (ch != '%') {
 			putc(ch);
 		} else {
-			char lz = 0;
-			char w = 0;
+			bool lz = false;
+			int width = 0;
 
 			ch = *(fmt++);
 			if (ch == '0') {
@@ -62,9 +65,9 @@ int vprintf(const char *fmt, va_list va)
 			}
 
 			if (ch >= '0' && ch <= '9') {
-				w = 0;
+				width = 0;
 				while (ch >= '0' && ch <= '9') {
-					w = (w * 10) + ch - '0';
+					width = (width * 10) + ch - '0';
 					ch = *fmt++;
 				}
 			}
@@ -73,7 +76,7 @@ int vprintf(const char *fmt, va_list va)
 			zs = 0;
 
 			switch (ch) {
-			case 0:
+			case '\0':
 				goto abort;
 			case 'u':
 			case 'd':
@@ -112,9 +115,9 @@ int vprintf(const char *fmt, va_list va)
 
 			*bf = 0;
 			bf = p;
-			while (*bf++ && w > 0)
-				w--;
-			while (w-- > 0)
+			while (*bf++ && width > 0)
+				width--;
+			while (width-- > 0)
 				putc(lz ? '0' : ' ');
 			if (p) {
 				while ((ch = *p++))
@@ -133,8 +136,42 @@ int printf(const char *fmt, ...)
 	int ret;
 
 	va_start(va, fmt);
-	ret = vprintf(fmt, va);
+	ret = _vprintf(fmt, va, putc);
+	va_end(va);
+
+	return ret;
+}
+
+static void putc_outstr(char ch)
+{
+	*outstr++ = ch;
+}
+
+int sprintf(char *buf, const char *fmt, ...)
+{
+	va_list va;
+	int ret;
+
+	va_start(va, fmt);
+	outstr = buf;
+	ret = _vprintf(fmt, va, putc_outstr);
+	va_end(va);
+	*outstr = '\0';
+
+	return ret;
+}
+
+/* Note that size is ignored */
+int snprintf(char *buf, size_t size, const char *fmt, ...)
+{
+	va_list va;
+	int ret;
+
+	va_start(va, fmt);
+	outstr = buf;
+	ret = _vprintf(fmt, va, putc_outstr);
 	va_end(va);
+	*outstr = '\0';
 
 	return ret;
 }
diff --git a/lib/tizen/tizen.c b/lib/tizen/tizen.c
index 814ed18329..d207f77d0b 100644
--- a/lib/tizen/tizen.c
+++ b/lib/tizen/tizen.c
@@ -12,6 +12,7 @@
 #include "tizen_logo_16bpp.h"
 #include "tizen_logo_16bpp_gzip.h"
 
+#ifdef CONFIG_LCD
 void get_tizen_logo_info(vidinfo_t *vid)
 {
 	switch (vid->vl_bpix) {
@@ -31,3 +32,4 @@ void get_tizen_logo_info(vidinfo_t *vid)
 		break;
 	}
 }
+#endif
diff --git a/net/Kconfig b/net/Kconfig
index a44a783cae..c393269f27 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -32,4 +32,20 @@ config NET_TFTP_VARS
 	  If unset, timeout and maximum are hard-defined as 1 second
 	  and 10 timouts per TFTP transfer.
 
+config BOOTP_PXE_CLIENTARCH
+	hex
+        default 0x16 if ARM64
+        default 0x15 if ARM
+        default 0 if X86
+
+config BOOTP_VCI_STRING
+	string
+	default "U-Boot.armv7" if CPU_V7 || CPU_V7M
+	default "U-Boot.armv8" if ARM64
+	default "U-Boot.arm" if ARM
+	default "U-Boot"
+
+config SPL_NET_VCI_STRING
+	string
+
 endif   # if NET
diff --git a/net/bootp.c b/net/bootp.c
index d7852dbb44..aa6cdf0a47 100644
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -10,6 +10,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <efi_loader.h>
 #include <net.h>
 #include <net/tftp.h>
 #include "bootp.h"
@@ -410,6 +411,26 @@ static void bootp_timeout_handler(void)
 		e += vci_strlen;				\
 	} while (0)
 
+static u8 *add_vci(u8 *e)
+{
+	char *vci = NULL;
+	char *env_vci = getenv("bootp_vci");
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
+	vci = CONFIG_SPL_NET_VCI_STRING;
+#elif defined(CONFIG_BOOTP_VCI_STRING)
+	vci = CONFIG_BOOTP_VCI_STRING;
+#endif
+
+	if (env_vci)
+		vci = env_vci;
+
+	if (vci)
+		put_vci(e, vci);
+
+	return e;
+}
+
 /*
  *	Initialize BOOTP extension fields in the request.
  */
@@ -419,10 +440,10 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 {
 	u8 *start = e;
 	u8 *cnt;
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_LIB_UUID
 	char *uuid;
-	u16 clientarch;
 #endif
+	int clientarch = -1;
 
 #if defined(CONFIG_BOOTP_VENDOREX)
 	u8 *x;
@@ -478,12 +499,19 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	}
 #endif
 
-#if defined(CONFIG_BOOTP_PXE)
+#ifdef CONFIG_BOOTP_PXE_CLIENTARCH
 	clientarch = CONFIG_BOOTP_PXE_CLIENTARCH;
-	*e++ = 93;	/* Client System Architecture */
-	*e++ = 2;
-	*e++ = (clientarch >> 8) & 0xff;
-	*e++ = clientarch & 0xff;
+#endif
+
+	if (getenv("bootp_arch"))
+		clientarch = getenv_ulong("bootp_arch", 16, clientarch);
+
+	if (clientarch > 0) {
+		*e++ = 93;	/* Client System Architecture */
+		*e++ = 2;
+		*e++ = (clientarch >> 8) & 0xff;
+		*e++ = clientarch & 0xff;
+	}
 
 	*e++ = 94;	/* Client Network Interface Identifier */
 	*e++ = 3;
@@ -491,6 +519,7 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	*e++ = 0;	/* major revision */
 	*e++ = 0;	/* minor revision */
 
+#ifdef CONFIG_LIB_UUID
 	uuid = getenv("pxeuuid");
 
 	if (uuid) {
@@ -507,11 +536,7 @@ static int dhcp_extended(u8 *e, int message_type, struct in_addr server_ip,
 	}
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING)
-	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#elif defined(CONFIG_BOOTP_VCI_STRING)
-	put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
+	e = add_vci(e);
 
 #if defined(CONFIG_BOOTP_VENDOREX)
 	x = dhcp_vendorex_prep(e);
@@ -597,14 +622,7 @@ static int bootp_extended(u8 *e)
 	*e++ = (576 - 312 + OPT_FIELD_SIZE) & 0xff;
 #endif
 
-#if defined(CONFIG_BOOTP_VCI_STRING) || \
-	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_NET_VCI_STRING))
-#ifdef CONFIG_SPL_BUILD
-	put_vci(e, CONFIG_SPL_NET_VCI_STRING);
-#else
-	put_vci(e, CONFIG_BOOTP_VCI_STRING);
-#endif
-#endif
+	add_vci(e);
 
 #if defined(CONFIG_BOOTP_SUBNETMASK)
 	*e++ = 1;		/* Subnet mask request */
@@ -1025,6 +1043,7 @@ static void dhcp_handler(uchar *pkt, unsigned dest, struct in_addr sip,
 			    strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
 #endif	/* CONFIG_SYS_BOOTFILE_PREFIX */
 			dhcp_packet_process_options(bp);
+			efi_net_set_dhcp_ack(pkt, len);
 
 			debug("TRANSITIONING TO REQUESTING STATE\n");
 			dhcp_state = REQUESTING;
diff --git a/net/net.c b/net/net.c
index fba111edfb..1e1d23dafa 100644
--- a/net/net.c
+++ b/net/net.c
@@ -146,7 +146,7 @@ static unsigned	net_ip_id;
 /* Ethernet bcast address */
 const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 const u8 net_null_ethaddr[6];
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 void (*push_packet)(void *, int len) = 0;
 #endif
 /* Network loop state */
@@ -1054,7 +1054,7 @@ void net_process_received_packet(uchar *in_packet, int len)
 	if (len < ETHER_HDR_SIZE)
 		return;
 
-#ifdef CONFIG_API
+#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
 	if (push_packet) {
 		(*push_packet)(in_packet, len);
 		return;
diff --git a/net/tftp.c b/net/tftp.c
index f2889fe4c9..ced45ec1f1 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <command.h>
+#include <efi_loader.h>
 #include <mapmem.h>
 #include <net.h>
 #include <net/tftp.h>
@@ -804,6 +805,7 @@ void tftp_start(enum proto_t protocol)
 		printf("Load address: 0x%lx\n", load_addr);
 		puts("Loading: *\b");
 		tftp_state = STATE_SEND_RRQ;
+		efi_set_bootdev("Net", "", tftp_filename);
 	}
 
 	time_start = get_timer(0);
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index ad1d9b5d7d..e720562623 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -323,13 +323,13 @@ $(obj)/%.S: $(src)/%.ttf
 
 # ACPI
 # ---------------------------------------------------------------------------
-quiet_cmd_acpi_c_asl= ASL     $@
+quiet_cmd_acpi_c_asl= ASL     $<
 cmd_acpi_c_asl=         \
-	$(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \
-	iasl -p $< -tc -va $<.tmp; \
+	$(CPP) -x assembler-with-cpp -D__ASSEMBLY__ -P $(UBOOTINCLUDE) -o $<.tmp $<; \
+	iasl -p $< -tc $<.tmp $(if $(KBUILD_VERBOSE:1=), >/dev/null); \
 	mv $(patsubst %.asl,%.hex,$<) $@
 
-$(obj)/%.c:    $(src)/%.asl
+$(obj)/dsdt.c:    $(src)/dsdt.asl
 	$(call cmd,acpi_c_asl)
 
 # Bzip2
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index ec8d8f1b72..0997fd9fdd 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -129,7 +129,12 @@ endif
 boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 else
+ifdef CONFIG_ARCH_ZYNQ
 MKIMAGEFLAGS_boot.bin = -T zynqimage
+endif
+ifdef CONFIG_ARCH_ZYNQMP
+MKIMAGEFLAGS_boot.bin = -T zynqmpimage
+endif
 
 spl/boot.bin: $(obj)/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
@@ -153,9 +158,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91")
 ALL-y	+= boot.bin
 endif
 
-ifdef CONFIG_ARCH_ZYNQ
-ALL-y	+= $(obj)/boot.bin
-endif
+ALL-$(CONFIG_ARCH_ZYNQ)		+= $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_ZYNQMP)	+= $(obj)/boot.bin
 
 all:	$(ALL-y)
 
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 9a11ae0a14..9eaf04b9ba 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -21,12 +21,13 @@ obj-$(CONFIG_DM_ETH) += eth.o
 obj-$(CONFIG_DM_GPIO) += gpio.o
 obj-$(CONFIG_DM_I2C) += i2c.o
 obj-$(CONFIG_LED) += led.o
+obj-$(CONFIG_DM_MAILBOX) += mailbox.o
 obj-$(CONFIG_DM_MMC) += mmc.o
 obj-$(CONFIG_DM_PCI) += pci.o
 obj-$(CONFIG_RAM) += ram.o
 obj-y += regmap.o
 obj-$(CONFIG_REMOTEPROC) += remoteproc.o
-obj-$(CONFIG_RESET) += reset.o
+obj-$(CONFIG_SYSRESET) += sysreset.o
 obj-$(CONFIG_DM_RTC) += rtc.o
 obj-$(CONFIG_DM_SPI_FLASH) += sf.o
 obj-$(CONFIG_DM_SPI) += spi.o
diff --git a/test/dm/gpio.c b/test/dm/gpio.c
index 727db18690..b99452340d 100644
--- a/test/dm/gpio.c
+++ b/test/dm/gpio.c
@@ -75,6 +75,13 @@ static int dm_test_gpio(struct unit_test_state *uts)
 	ut_assertok(ops->set_value(dev, offset, 1));
 	ut_asserteq(1, ops->get_value(dev, offset));
 
+	/* Make it an open drain output, and reset it */
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 1));
+	ut_asserteq(1, sandbox_gpio_get_open_drain(dev, offset));
+	ut_assertok(ops->set_open_drain(dev, offset, 0));
+	ut_asserteq(0, sandbox_gpio_get_open_drain(dev, offset));
+
 	/* Make it an input */
 	ut_assertok(ops->direction_input(dev, offset));
 	ut_assertok(gpio_get_status(dev, offset, buf, sizeof(buf)));
diff --git a/test/dm/mailbox.c b/test/dm/mailbox.c
new file mode 100644
index 0000000000..be7bd6de06
--- /dev/null
+++ b/test/dm/mailbox.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+#include <asm/mbox.h>
+#include <test/ut.h>
+
+static int dm_test_mailbox(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+	uint32_t msg;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "mbox-test", &dev));
+	ut_assertok(sandbox_mbox_test_get(dev));
+
+	ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+	ut_assertok(sandbox_mbox_test_send(dev, 0xaaff9955UL));
+	ut_assertok(sandbox_mbox_test_recv(dev, &msg));
+	ut_asserteq(msg, 0xaaff9955UL ^ SANDBOX_MBOX_PING_XOR);
+	ut_asserteq(-ETIMEDOUT, sandbox_mbox_test_recv(dev, &msg));
+
+	ut_assertok(sandbox_mbox_test_free(dev));
+
+	return 0;
+}
+DM_TEST(dm_test_mailbox, DM_TESTF_SCAN_FDT);
diff --git a/test/dm/reset.c b/test/dm/reset.c
deleted file mode 100644
index 5d53f252bb..0000000000
--- a/test/dm/reset.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2015 Google, Inc
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <reset.h>
-#include <asm/state.h>
-#include <asm/test.h>
-#include <dm/test.h>
-#include <test/ut.h>
-
-/* Test that we can use particular reset devices */
-static int dm_test_reset_base(struct unit_test_state *uts)
-{
-	struct sandbox_state *state = state_get_current();
-	struct udevice *dev;
-
-	/* Device 0 is the platform data device - it should never respond */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 0, &dev));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_WARM));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_COLD));
-	ut_asserteq(-ENODEV, reset_request(dev, RESET_POWER));
-
-	/* Device 1 is the warm reset device */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 1, &dev));
-	ut_asserteq(-EACCES, reset_request(dev, RESET_WARM));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_COLD));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_POWER));
-
-	state->reset_allowed[RESET_WARM] = true;
-	ut_asserteq(-EINPROGRESS, reset_request(dev, RESET_WARM));
-	state->reset_allowed[RESET_WARM] = false;
-
-	/* Device 2 is the cold reset device */
-	ut_assertok(uclass_get_device(UCLASS_RESET, 2, &dev));
-	ut_asserteq(-ENOSYS, reset_request(dev, RESET_WARM));
-	ut_asserteq(-EACCES, reset_request(dev, RESET_COLD));
-	state->reset_allowed[RESET_POWER] = false;
-	ut_asserteq(-EACCES, reset_request(dev, RESET_POWER));
-	state->reset_allowed[RESET_POWER] = true;
-
-	return 0;
-}
-DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
-
-/* Test that we can walk through the reset devices */
-static int dm_test_reset_walk(struct unit_test_state *uts)
-{
-	struct sandbox_state *state = state_get_current();
-
-	/* If we generate a power reset, we will exit sandbox! */
-	state->reset_allowed[RESET_POWER] = false;
-	ut_asserteq(-EACCES, reset_walk(RESET_WARM));
-	ut_asserteq(-EACCES, reset_walk(RESET_COLD));
-	ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-
-	/*
-	 * Enable cold reset - this should make cold reset work, plus a warm
-	 * reset should be promoted to cold, since this is the next step
-	 * along.
-	 */
-	state->reset_allowed[RESET_COLD] = true;
-	ut_asserteq(-EINPROGRESS, reset_walk(RESET_WARM));
-	ut_asserteq(-EINPROGRESS, reset_walk(RESET_COLD));
-	ut_asserteq(-EACCES, reset_walk(RESET_POWER));
-	state->reset_allowed[RESET_COLD] = false;
-	state->reset_allowed[RESET_POWER] = true;
-
-	return 0;
-}
-DM_TEST(dm_test_reset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
new file mode 100644
index 0000000000..5e94c072b6
--- /dev/null
+++ b/test/dm/sysreset.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <sysreset.h>
+#include <asm/state.h>
+#include <asm/test.h>
+#include <dm/test.h>
+#include <test/ut.h>
+
+/* Test that we can use particular sysreset devices */
+static int dm_test_sysreset_base(struct unit_test_state *uts)
+{
+	struct sandbox_state *state = state_get_current();
+	struct udevice *dev;
+
+	/* Device 0 is the platform data device - it should never respond */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 0, &dev));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_COLD));
+	ut_asserteq(-ENODEV, sysreset_request(dev, SYSRESET_POWER));
+
+	/* Device 1 is the warm sysreset device */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, &dev));
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+
+	state->sysreset_allowed[SYSRESET_WARM] = true;
+	ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
+	state->sysreset_allowed[SYSRESET_WARM] = false;
+
+	/* Device 2 is the cold sysreset device */
+	ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, &dev));
+	ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
+	state->sysreset_allowed[SYSRESET_POWER] = false;
+	ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_POWER));
+	state->sysreset_allowed[SYSRESET_POWER] = true;
+
+	return 0;
+}
+DM_TEST(dm_test_sysreset_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
+
+/* Test that we can walk through the sysreset devices */
+static int dm_test_sysreset_walk(struct unit_test_state *uts)
+{
+	struct sandbox_state *state = state_get_current();
+
+	/* If we generate a power sysreset, we will exit sandbox! */
+	state->sysreset_allowed[SYSRESET_POWER] = false;
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_WARM));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_COLD));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+
+	/*
+	 * Enable cold system reset - this should make cold system reset work,
+	 * plus a warm system reset should be promoted to cold, since this is
+	 * the next step along.
+	 */
+	state->sysreset_allowed[SYSRESET_COLD] = true;
+	ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_WARM));
+	ut_asserteq(-EINPROGRESS, sysreset_walk(SYSRESET_COLD));
+	ut_asserteq(-EACCES, sysreset_walk(SYSRESET_POWER));
+	state->sysreset_allowed[SYSRESET_COLD] = false;
+	state->sysreset_allowed[SYSRESET_POWER] = true;
+
+	return 0;
+}
+DM_TEST(dm_test_sysreset_walk, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
diff --git a/test/py/tests/test_env.py b/test/py/tests/test_env.py
index c41aa5a9d9..22a22d1d53 100644
--- a/test/py/tests/test_env.py
+++ b/test/py/tests/test_env.py
@@ -39,7 +39,11 @@ class StateTestEnv(object):
             Nothing.
         """
 
-        response = self.u_boot_console.run_command('printenv')
+        if self.u_boot_console.config.buildconfig['config_version_variable'] == 'y':
+            with self.u_boot_console.disable_check('main_signon'):
+                response = self.u_boot_console.run_command('printenv')
+        else:
+            response = self.u_boot_console.run_command('printenv')
         self.env = {}
         for l in response.splitlines():
             if not '=' in l:
diff --git a/test/py/u_boot_console_base.py b/test/py/u_boot_console_base.py
index f7434363fb..815fa64d5f 100644
--- a/test/py/u_boot_console_base.py
+++ b/test/py/u_boot_console_base.py
@@ -56,6 +56,22 @@ class ConsoleDisableCheck(object):
         self.console.disable_check_count[self.check_type] -= 1
         self.console.eval_bad_patterns()
 
+class ConsoleSetupTimeout(object):
+    """Context manager (for Python's with statement) that temporarily sets up
+    timeout for specific command. This is useful when execution time is greater
+    then default 30s."""
+
+    def __init__(self, console, timeout):
+        self.p = console.p
+        self.orig_timeout = self.p.timeout
+        self.p.timeout = timeout
+
+    def __enter__(self):
+        return self
+
+    def __exit__(self, extype, value, traceback):
+        self.p.timeout = self.orig_timeout
+
 class ConsoleBase(object):
     """The interface through which test functions interact with the U-Boot
     console. This primarily involves executing shell commands, capturing their
@@ -391,3 +407,18 @@ class ConsoleBase(object):
         """
 
         return ConsoleDisableCheck(self, check_type)
+
+    def temporary_timeout(self, timeout):
+        """Temporarily set up different timeout for commands.
+
+        Create a new context manager (for use with the "with" statement) which
+        temporarily change timeout.
+
+        Args:
+            timeout: Time in milliseconds.
+
+        Returns:
+            A context manager object.
+        """
+
+        return ConsoleSetupTimeout(self, timeout)
diff --git a/test/py/u_boot_utils.py b/test/py/u_boot_utils.py
index 9d243e047b..6a6b2ec0e6 100644
--- a/test/py/u_boot_utils.py
+++ b/test/py/u_boot_utils.py
@@ -10,6 +10,7 @@ import os.path
 import pytest
 import sys
 import time
+import pytest
 
 def md5sum_data(data):
     """Calculate the MD5 hash of some data.
diff --git a/tools/.gitignore b/tools/.gitignore
index ff07680308..cb1e722d45 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -1,4 +1,5 @@
 /atmel_pmecc_params
+/bin2header
 /bmp_logo
 /envcrc
 /fdtgrep
diff --git a/tools/Makefile b/tools/Makefile
index da50e1bffc..63355aa36d 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \
 			common/hash.o \
 			ublimage.o \
 			zynqimage.o \
+			zynqmpimage.o \
 			$(LIBFDT_OBJS) \
 			$(RSA_OBJS-y)
 
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 06cf63daa4..692abda731 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -35,9 +35,11 @@
 
 #include "fw_env.h"
 
-struct common_args common_args;
-struct printenv_args printenv_args;
-struct setenv_args setenv_args;
+struct env_opts default_opts = {
+#ifdef CONFIG_FILE
+	.config_file = CONFIG_FILE
+#endif
+};
 
 #define DIV_ROUND_UP(n, d)	(((n) + (d) - 1) / (d))
 
@@ -75,7 +77,8 @@ static int dev_current;
 
 #define CUR_ENVSIZE ENVSIZE(dev_current)
 
-#define ENV_SIZE      getenvsize()
+static unsigned long usable_envsize;
+#define ENV_SIZE      usable_envsize
 
 struct env_image_single {
 	uint32_t	crc;	/* CRC32 over data bytes    */
@@ -106,7 +109,7 @@ static struct environment environment = {
 	.flag_scheme = FLAG_NONE,
 };
 
-static int env_aes_cbc_crypt(char *data, const int enc);
+static int env_aes_cbc_crypt(char *data, const int enc, uint8_t *key);
 
 static int HaveRedundEnv = 0;
 
@@ -119,23 +122,11 @@ static unsigned char obsolete_flag = 0;
 
 static int flash_io (int mode);
 static char *envmatch (char * s1, char * s2);
-static int parse_config (void);
+static int parse_config(struct env_opts *opts);
 
 #if defined(CONFIG_FILE)
 static int get_config (char *);
 #endif
-static inline ulong getenvsize (void)
-{
-	ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
-
-	if (HaveRedundEnv)
-		rc -= sizeof (char);
-
-	if (common_args.aes_flag)
-		rc &= ~(AES_KEY_LENGTH - 1);
-
-	return rc;
-}
 
 static char *skip_chars(char *s)
 {
@@ -239,12 +230,15 @@ int parse_aes_key(char *key, uint8_t *bin_key)
  * Print the current definition of one, or more, or all
  * environment variables
  */
-int fw_printenv (int argc, char *argv[])
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts)
 {
 	char *env, *nxt;
 	int i, rc = 0;
 
-	if (fw_env_open())
+	if (!opts)
+		opts = &default_opts;
+
+	if (fw_env_open(opts))
 		return -1;
 
 	if (argc == 0) {		/* Print all env variables  */
@@ -262,7 +256,7 @@ int fw_printenv (int argc, char *argv[])
 		return 0;
 	}
 
-	if (printenv_args.name_suppress && argc != 1) {
+	if (value_only && argc != 1) {
 		fprintf(stderr,
 			"## Error: `-n' option requires exactly one argument\n");
 		return -1;
@@ -283,7 +277,7 @@ int fw_printenv (int argc, char *argv[])
 			}
 			val = envmatch (name, env);
 			if (val) {
-				if (!printenv_args.name_suppress) {
+				if (!value_only) {
 					fputs (name, stdout);
 					putc ('=', stdout);
 				}
@@ -300,11 +294,16 @@ int fw_printenv (int argc, char *argv[])
 	return rc;
 }
 
-int fw_env_close(void)
+int fw_env_close(struct env_opts *opts)
 {
 	int ret;
-	if (common_args.aes_flag) {
-		ret = env_aes_cbc_crypt(environment.data, 1);
+
+	if (!opts)
+		opts = &default_opts;
+
+	if (opts->aes_flag) {
+		ret = env_aes_cbc_crypt(environment.data, 1,
+					opts->aes_key);
 		if (ret) {
 			fprintf(stderr,
 				"Error: can't encrypt env for flash\n");
@@ -457,7 +456,7 @@ int fw_env_write(char *name, char *value)
  *	    modified or deleted
  *
  */
-int fw_setenv(int argc, char *argv[])
+int fw_setenv(int argc, char *argv[], struct env_opts *opts)
 {
 	int i;
 	size_t len;
@@ -465,13 +464,16 @@ int fw_setenv(int argc, char *argv[])
 	char *value = NULL;
 	int valc;
 
+	if (!opts)
+		opts = &default_opts;
+
 	if (argc < 1) {
 		fprintf(stderr, "## Error: variable name missing\n");
 		errno = EINVAL;
 		return -1;
 	}
 
-	if (fw_env_open()) {
+	if (fw_env_open(opts)) {
 		fprintf(stderr, "Error: environment not initialized\n");
 		return -1;
 	}
@@ -507,7 +509,7 @@ int fw_setenv(int argc, char *argv[])
 
 	free(value);
 
-	return fw_env_close();
+	return fw_env_close(opts);
 }
 
 /*
@@ -527,7 +529,7 @@ int fw_setenv(int argc, char *argv[])
  * 0	  - OK
  * -1     - Error
  */
-int fw_parse_script(char *fname)
+int fw_parse_script(char *fname, struct env_opts *opts)
 {
 	FILE *fp;
 	char dump[1024];	/* Maximum line length in the file */
@@ -537,7 +539,10 @@ int fw_parse_script(char *fname)
 	int len;
 	int ret = 0;
 
-	if (fw_env_open()) {
+	if (!opts)
+		opts = &default_opts;
+
+	if (fw_env_open(opts)) {
 		fprintf(stderr, "Error: environment not initialized\n");
 		return -1;
 	}
@@ -625,10 +630,9 @@ int fw_parse_script(char *fname)
 	if (strcmp(fname, "-") != 0)
 		fclose(fp);
 
-	ret |= fw_env_close();
+	ret |= fw_env_close(opts);
 
 	return ret;
-
 }
 
 /*
@@ -949,15 +953,15 @@ static int flash_flag_obsolete (int dev, int fd, off_t offset)
 }
 
 /* Encrypt or decrypt the environment before writing or reading it. */
-static int env_aes_cbc_crypt(char *payload, const int enc)
+static int env_aes_cbc_crypt(char *payload, const int enc, uint8_t *key)
 {
 	uint8_t *data = (uint8_t *)payload;
-	const int len = getenvsize();
+	const int len = usable_envsize;
 	uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
 	uint32_t aes_blocks;
 
 	/* First we expand the key. */
-	aes_expand_key(common_args.aes_key, key_exp);
+	aes_expand_key(key, key_exp);
 
 	/* Calculate the number of AES blocks to encrypt. */
 	aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
@@ -1138,7 +1142,7 @@ static char *envmatch (char * s1, char * s2)
 /*
  * Prevent confusion if running from erased flash memory
  */
-int fw_env_open(void)
+int fw_env_open(struct env_opts *opts)
 {
 	int crc0, crc0_ok;
 	unsigned char flag0;
@@ -1153,7 +1157,10 @@ int fw_env_open(void)
 	struct env_image_single *single;
 	struct env_image_redundant *redundant;
 
-	if (parse_config ())		/* should fill envdevices */
+	if (!opts)
+		opts = &default_opts;
+
+	if (parse_config(opts))		/* should fill envdevices */
 		return -1;
 
 	addr0 = calloc(1, CUR_ENVSIZE);
@@ -1185,8 +1192,9 @@ int fw_env_open(void)
 
 	crc0 = crc32 (0, (uint8_t *) environment.data, ENV_SIZE);
 
-	if (common_args.aes_flag) {
-		ret = env_aes_cbc_crypt(environment.data, 0);
+	if (opts->aes_flag) {
+		ret = env_aes_cbc_crypt(environment.data, 0,
+					opts->aes_key);
 		if (ret)
 			return ret;
 	}
@@ -1242,8 +1250,9 @@ int fw_env_open(void)
 
 		crc1 = crc32 (0, (uint8_t *) redundant->data, ENV_SIZE);
 
-		if (common_args.aes_flag) {
-			ret = env_aes_cbc_crypt(redundant->data, 0);
+		if (opts->aes_flag) {
+			ret = env_aes_cbc_crypt(redundant->data, 0,
+						opts->aes_key);
 			if (ret)
 				return ret;
 		}
@@ -1320,18 +1329,18 @@ int fw_env_open(void)
 }
 
 
-static int parse_config ()
+static int parse_config(struct env_opts *opts)
 {
 	struct stat st;
 
-#if defined(CONFIG_FILE)
-	if (!common_args.config_file)
-		common_args.config_file = CONFIG_FILE;
+	if (!opts)
+		opts = &default_opts;
 
+#if defined(CONFIG_FILE)
 	/* Fills in DEVNAME(), ENVSIZE(), DEVESIZE(). Or don't. */
-	if (get_config(common_args.config_file)) {
+	if (get_config(opts->config_file)) {
 		fprintf(stderr, "Cannot parse config file '%s': %m\n",
-			common_args.config_file);
+			opts->config_file);
 		return -1;
 	}
 #else
@@ -1379,6 +1388,21 @@ static int parse_config ()
 			DEVNAME (1), strerror (errno));
 		return -1;
 	}
+
+	if (HaveRedundEnv && ENVSIZE(0) != ENVSIZE(1)) {
+		ENVSIZE(0) = ENVSIZE(1) = min(ENVSIZE(0), ENVSIZE(1));
+		fprintf(stderr,
+			"Redundant environments have inequal size, set to 0x%08lx\n",
+			ENVSIZE(1));
+	}
+
+	usable_envsize = CUR_ENVSIZE - sizeof(uint32_t);
+	if (HaveRedundEnv)
+		usable_envsize -= sizeof(char);
+
+	if (opts->aes_flag)
+		usable_envsize &= ~(AES_KEY_LENGTH - 1);
+
 	return 0;
 }
 
diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h
index 57149e733b..dac964d933 100644
--- a/tools/env/fw_env.h
+++ b/tools/env/fw_env.h
@@ -57,33 +57,22 @@
 	"bootm"
 #endif
 
-struct common_args {
+struct env_opts {
 #ifdef CONFIG_FILE
 	char *config_file;
 #endif
-	uint8_t aes_key[AES_KEY_LENGTH];
 	int aes_flag; /* Is AES encryption used? */
+	uint8_t aes_key[AES_KEY_LENGTH];
 };
-extern struct common_args common_args;
-
-struct printenv_args {
-	int name_suppress;
-};
-extern struct printenv_args printenv_args;
-
-struct setenv_args {
-	char *script_file;
-};
-extern struct setenv_args setenv_args;
 
 int parse_aes_key(char *key, uint8_t *bin_key);
 
-extern int   fw_printenv(int argc, char *argv[]);
-extern char *fw_getenv  (char *name);
-extern int fw_setenv  (int argc, char *argv[]);
-extern int fw_parse_script(char *fname);
-extern int fw_env_open(void);
-extern int fw_env_write(char *name, char *value);
-extern int fw_env_close(void);
+int fw_printenv(int argc, char *argv[], int value_only, struct env_opts *opts);
+char *fw_getenv(char *name);
+int fw_setenv(int argc, char *argv[], struct env_opts *opts);
+int fw_parse_script(char *fname, struct env_opts *opts);
+int fw_env_open(struct env_opts *opts);
+int fw_env_write(char *name, char *value);
+int fw_env_close(struct env_opts *opts);
 
-extern unsigned	long  crc32	 (unsigned long, const unsigned char *, unsigned);
+unsigned long crc32(unsigned long, const unsigned char *, unsigned);
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 3706d8f1a6..7a17b28f40 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -49,6 +49,14 @@ static struct option long_options[] = {
 	{NULL, 0, NULL, 0}
 };
 
+static struct env_opts env_opts;
+
+/* setenv options */
+static int noheader;
+
+/* getenv options */
+static char *script_file;
+
 void usage_printenv(void)
 {
 
@@ -108,22 +116,22 @@ static void parse_common_args(int argc, char *argv[])
 	int c;
 
 #ifdef CONFIG_FILE
-	common_args.config_file = CONFIG_FILE;
+	env_opts.config_file = CONFIG_FILE;
 #endif
 
 	while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) !=
 	       EOF) {
 		switch (c) {
 		case 'a':
-			if (parse_aes_key(optarg, common_args.aes_key)) {
+			if (parse_aes_key(optarg, env_opts.aes_key)) {
 				fprintf(stderr, "AES key parse error\n");
 				exit(EXIT_FAILURE);
 			}
-			common_args.aes_flag = 1;
+			env_opts.aes_flag = 1;
 			break;
 #ifdef CONFIG_FILE
 		case 'c':
-			common_args.config_file = optarg;
+			env_opts.config_file = optarg;
 			break;
 #endif
 		case 'h':
@@ -151,7 +159,7 @@ int parse_printenv_args(int argc, char *argv[])
 	       EOF) {
 		switch (c) {
 		case 'n':
-			printenv_args.name_suppress = 1;
+			noheader = 1;
 			break;
 		case 'a':
 		case 'c':
@@ -177,7 +185,7 @@ int parse_setenv_args(int argc, char *argv[])
 	       EOF) {
 		switch (c) {
 		case 's':
-			setenv_args.script_file = optarg;
+			script_file = optarg;
 			break;
 		case 'a':
 		case 'c':
@@ -240,14 +248,14 @@ int main(int argc, char *argv[])
 	}
 
 	if (do_printenv) {
-		if (fw_printenv(argc, argv) != 0)
+		if (fw_printenv(argc, argv, noheader, &env_opts) != 0)
 			retval = EXIT_FAILURE;
 	} else {
-		if (!setenv_args.script_file) {
-			if (fw_setenv(argc, argv) != 0)
+		if (!script_file) {
+			if (fw_setenv(argc, argv, &env_opts) != 0)
 				retval = EXIT_FAILURE;
 		} else {
-			if (fw_parse_script(setenv_args.script_file) != 0)
+			if (fw_parse_script(script_file, &env_opts) != 0)
 				retval = EXIT_FAILURE;
 		}
 	}
diff --git a/tools/genboardscfg.py b/tools/genboardscfg.py
index 23c956bb8e..c2efad55ab 100755
--- a/tools/genboardscfg.py
+++ b/tools/genboardscfg.py
@@ -21,7 +21,6 @@ import glob
 import multiprocessing
 import optparse
 import os
-import subprocess
 import sys
 import tempfile
 import time
diff --git a/tools/palmtreo680/flash_u-boot.c b/tools/palmtreo680/flash_u-boot.c
deleted file mode 100644
index 832d3fef7b..0000000000
--- a/tools/palmtreo680/flash_u-boot.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
- *
- * This file is released under the terms of GPL v2 and any later version.
- * See the file COPYING in the root directory of the source tree for details.
- *
- *
- * This is a userspace Linux utility that, when run on the Treo 680, will
- * program u-boot to flash.  The docg4 driver *must* be loaded with the
- * reliable_mode and ignore_badblocks parameters enabled:
- *
- *        modprobe docg4 ignore_badblocks=1 reliable_mode=1
- *
- * This utility writes the concatenated spl + u-boot image to the start of the
- * mtd device in the format expected by the IPL/SPL.  The image file and mtd
- * device node are passed to the utility as arguments.  The blocks must have
- * been erased beforehand.
- *
- * When you compile this, note that it links to libmtd from mtd-utils, so ensure
- * that your include and lib paths include this.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/stat.h>
-#include <fcntl.h>
-#include <string.h>
-#include <sys/types.h>
-#include <unistd.h>
-#include <errno.h>
-#include <mtd/mtd-user.h>
-#include "libmtd.h"
-
-#define RELIABLE_BLOCKSIZE  0x10000 /* block capacity in reliable mode */
-#define STANDARD_BLOCKSIZE  0x40000 /* block capacity in normal mode */
-#define PAGESIZE 512
-#define PAGES_PER_BLOCK 512
-#define OOBSIZE 7		/* available to user (16 total) */
-
-uint8_t ff_oob[OOBSIZE] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
-/* this is the magic number the IPL looks for (ASCII "BIPO") */
-uint8_t page0_oob[OOBSIZE] = {'B', 'I', 'P', 'O', 0xff, 0xff, 0xff};
-
-int main(int argc, char * const argv[])
-{
-	int devfd, datafd, num_blocks, block;
-	off_t file_size;
-	libmtd_t mtd_desc;
-	struct mtd_dev_info devinfo;
-	uint8_t *blockbuf;
-	char response[8];
-
-	if (argc != 3) {
-		printf("usage: %s <image file> <mtd dev node>\n", argv[0]);
-		return -EINVAL;
-	}
-
-	mtd_desc = libmtd_open();
-	if (mtd_desc == NULL) {
-		int errsv = errno;
-		fprintf(stderr, "can't initialize libmtd\n");
-		return -errsv;
-	}
-
-	/* open the spl image file and mtd device */
-	datafd = open(argv[1], O_RDONLY);
-	if (datafd == -1) {
-		int errsv = errno;
-		perror(argv[1]);
-		return -errsv;
-	}
-	devfd = open(argv[2], O_WRONLY);
-	if (devfd == -1) {
-		int errsv = errno;
-		perror(argv[2]);
-		return -errsv;
-	}
-	if (mtd_get_dev_info(mtd_desc, argv[2], &devinfo) < 0) {
-		int errsv = errno;
-		perror(argv[2]);
-		return -errsv;
-	}
-
-	/* determine the number of blocks needed by the image */
-	file_size = lseek(datafd, 0, SEEK_END);
-	if (file_size == (off_t)-1) {
-		int errsv = errno;
-		perror("lseek");
-		return -errsv;
-	}
-	num_blocks = (file_size + RELIABLE_BLOCKSIZE - 1) / RELIABLE_BLOCKSIZE;
-	file_size = lseek(datafd, 0, SEEK_SET);
-	if (file_size == (off_t)-1) {
-		int errsv = errno;
-		perror("lseek");
-		return -errsv;
-	}
-	printf("The mtd partition contains %d blocks\n", devinfo.eb_cnt);
-	printf("U-Boot will occupy %d blocks\n", num_blocks);
-	if (num_blocks > devinfo.eb_cnt) {
-		fprintf(stderr, "Insufficient blocks on partition\n");
-		return -EINVAL;
-	}
-
-	printf("IMPORTANT: These blocks must be in an erased state!\n");
-	printf("Do you want to proceed?\n");
-	scanf("%s", response);
-	if ((response[0] != 'y') && (response[0] != 'Y')) {
-		printf("Exiting\n");
-		close(devfd);
-		close(datafd);
-		return 0;
-	}
-
-	blockbuf = calloc(RELIABLE_BLOCKSIZE, 1);
-	if (blockbuf == NULL) {
-		int errsv = errno;
-		perror("calloc");
-		return -errsv;
-	}
-
-	for (block = 0; block < num_blocks; block++) {
-		int ofs, page;
-		uint8_t *pagebuf = blockbuf, *buf = blockbuf;
-		uint8_t *oobbuf = page0_oob; /* magic num in oob of 1st page */
-		size_t len = RELIABLE_BLOCKSIZE;
-		int ret;
-
-		/* read data for one block from file */
-		while (len) {
-			ssize_t read_ret = read(datafd, buf, len);
-			if (read_ret == -1) {
-				int errsv = errno;
-				if (errno == EINTR)
-					continue;
-				perror("read");
-				return -errsv;
-			} else if (read_ret == 0) {
-				break; /* EOF */
-			}
-			len -= read_ret;
-			buf += read_ret;
-		}
-
-		printf("Block %d: writing\r", block + 1);
-		fflush(stdout);
-
-		for (page = 0, ofs = 0;
-		     page < PAGES_PER_BLOCK;
-		     page++, ofs += PAGESIZE) {
-			if (page & 0x04)  /* Odd-numbered 2k page */
-				continue; /* skipped in reliable mode */
-
-			ret = mtd_write(mtd_desc, &devinfo, devfd, block, ofs,
-					pagebuf, PAGESIZE, oobbuf, OOBSIZE,
-					MTD_OPS_PLACE_OOB);
-			if (ret) {
-				fprintf(stderr,
-					"\nmtd_write returned %d on block %d, ofs %x\n",
-					ret, block + 1, ofs);
-				return -EIO;
-			}
-			oobbuf = ff_oob;  /* oob for subsequent pages */
-
-			if (page & 0x01)  /* odd-numbered subpage */
-				pagebuf += PAGESIZE;
-		}
-	}
-
-	printf("\nDone\n");
-
-	close(devfd);
-	close(datafd);
-	free(blockbuf);
-	return 0;
-}
diff --git a/tools/rkimage.c b/tools/rkimage.c
index f9fdcfa712..ef31cb6944 100644
--- a/tools/rkimage.c
+++ b/tools/rkimage.c
@@ -13,11 +13,6 @@
 
 static uint32_t header;
 
-static int rkimage_check_params(struct image_tool_params *params)
-{
-	return 0;
-}
-
 static int rkimage_verify_header(unsigned char *buf, int size,
 				 struct image_tool_params *params)
 {
@@ -56,7 +51,7 @@ U_BOOT_IMAGE_TYPE(
 	"Rockchip Boot Image support",
 	4,
 	&header,
-	rkimage_check_params,
+	rkcommon_check_params,
 	rkimage_verify_header,
 	rkimage_print_header,
 	rkimage_set_header,
diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c
new file mode 100644
index 0000000000..3f28eb401d
--- /dev/null
+++ b/tools/zynqmpimage.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2016 Michal Simek <michals@xilinx.com>
+ * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * The following Boot Header format/structures and values are defined in the
+ * following documents:
+ *   * ug1085 ZynqMP TRM (Chapter 9, Table 9-3)
+ *
+ * Expected Header Size = 0x9C0
+ * Forced as 'little' endian, 32-bit words
+ *
+ *  0x  0 - Interrupt table (8 words)
+ *  ...     (Default value = 0xeafffffe)
+ *  0x 1f
+ *  0x 20 - Width detection
+ *         * DEFAULT_WIDTHDETECTION    0xaa995566
+ *  0x 24 - Image identifier
+ *         * DEFAULT_IMAGEIDENTIFIER   0x584c4e58
+ *  0x 28 - Encryption
+ *         * 0x00000000 - None
+ *         * 0xa5c3c5a3 - eFuse
+ *         * 0xa5c3c5a7 - obfuscated key in eFUSE
+ *         * 0x3a5c3c5a - bbRam
+ *         * 0xa35c7ca5 - obfuscated key in boot header
+ *  0x 2C - Image load
+ *  0x 30 - Image offset
+ *  0x 34 - PFW image length
+ *  0x 38 - Total PFW image length
+ *  0x 3C - Image length
+ *  0x 40 - Total image length
+ *  0x 44 - Image attributes
+ *  0x 48 - Header checksum
+ *  0x 4c - Obfuscated key
+ *  ...
+ *  0x 68
+ *  0x 6c - Reserved
+ *  0x 70 - User defined
+ *  ...
+ *  0x 9c
+ *  0x a0 - Secure header initialization vector
+ *  ...
+ *  0x a8
+ *  0x ac - Obfuscated key initialization vector
+ *  ...
+ *  0x b4
+ *  0x b8 - Register Initialization, 511 Address and Data word pairs
+ *         * List is terminated with an address of 0xffffffff or
+ *  ...    * at the max number of entries
+ *  0x8b4
+ *  0x8b8 - Reserved
+ *  ...
+ *  0x9bf
+ *  0x9c0 - Data/Image starts here or above
+ */
+
+#include "imagetool.h"
+#include "mkimage.h"
+#include <image.h>
+
+#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe))
+#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff))
+#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566))
+#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58))
+
+enum {
+	ENCRYPTION_EFUSE = 0xa5c3c5a3,
+	ENCRYPTION_OEFUSE = 0xa5c3c5a7,
+	ENCRYPTION_BBRAM = 0x3a5c3c5a,
+	ENCRYPTION_OBBRAM = 0xa35c7ca5,
+	ENCRYPTION_NONE = 0x0,
+};
+
+struct zynqmp_reginit {
+	uint32_t address;
+	uint32_t data;
+};
+
+#define HEADER_INTERRUPT_VECTORS	8
+#define HEADER_REGINITS			256
+
+struct zynqmp_header {
+	uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */
+	uint32_t width_detection; /* 0x20 */
+	uint32_t image_identifier; /* 0x24 */
+	uint32_t encryption; /* 0x28 */
+	uint32_t image_load; /* 0x2c */
+	uint32_t image_offset; /* 0x30 */
+	uint32_t pfw_image_length; /* 0x34 */
+	uint32_t total_pfw_image_length; /* 0x38 */
+	uint32_t image_size; /* 0x3c */
+	uint32_t image_stored_size; /* 0x40 */
+	uint32_t image_attributes; /* 0x44 */
+	uint32_t checksum; /* 0x48 */
+	uint32_t __reserved1[27]; /* 0x4c */
+	struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */
+	uint32_t __reserved4[66]; /* 0x9c0 */
+};
+
+static struct zynqmp_header zynqmpimage_header;
+
+static uint32_t zynqmpimage_checksum(struct zynqmp_header *ptr)
+{
+	uint32_t checksum = 0;
+
+	if (ptr == NULL)
+		return 0;
+
+	checksum += le32_to_cpu(ptr->width_detection);
+	checksum += le32_to_cpu(ptr->image_identifier);
+	checksum += le32_to_cpu(ptr->encryption);
+	checksum += le32_to_cpu(ptr->image_load);
+	checksum += le32_to_cpu(ptr->image_offset);
+	checksum += le32_to_cpu(ptr->pfw_image_length);
+	checksum += le32_to_cpu(ptr->total_pfw_image_length);
+	checksum += le32_to_cpu(ptr->image_size);
+	checksum += le32_to_cpu(ptr->image_stored_size);
+	checksum += le32_to_cpu(ptr->image_attributes);
+	checksum = ~checksum;
+
+	return cpu_to_le32(checksum);
+}
+
+static void zynqmpimage_default_header(struct zynqmp_header *ptr)
+{
+	int i;
+
+	if (ptr == NULL)
+		return;
+
+	ptr->width_detection = HEADER_WIDTHDETECTION;
+	ptr->image_attributes = 0x800;
+	ptr->image_identifier = HEADER_IMAGEIDENTIFIER;
+	ptr->encryption = cpu_to_le32(ENCRYPTION_NONE);
+
+	/* Setup not-supported/constant/reserved fields */
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++)
+		ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT;
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		ptr->register_init[i].address = HEADER_REGINIT_NULL;
+		ptr->register_init[i].data = 0;
+	}
+
+	/*
+	 * Certain reserved fields are required to be set to 0, ensure they are
+	 * set as such.
+	 */
+	ptr->pfw_image_length = 0x0;
+	ptr->total_pfw_image_length = 0x0;
+}
+
+/* mkimage glue functions */
+static int zynqmpimage_verify_header(unsigned char *ptr, int image_size,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+
+	if (image_size < sizeof(struct zynqmp_header))
+		return -1;
+
+	if (zynqhdr->width_detection != HEADER_WIDTHDETECTION)
+		return -1;
+	if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER)
+		return -1;
+
+	if (zynqmpimage_checksum(zynqhdr) != zynqhdr->checksum)
+		return -1;
+
+	return 0;
+}
+
+static void zynqmpimage_print_header(const void *ptr)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	int i;
+
+	printf("Image Type   : Xilinx Zynq Boot Image support\n");
+	printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset));
+	printf("Image Size   : %lu bytes (%lu bytes packed)\n",
+	       (unsigned long)le32_to_cpu(zynqhdr->image_size),
+	       (unsigned long)le32_to_cpu(zynqhdr->image_stored_size));
+	printf("Image Load   : 0x%08x\n", le32_to_cpu(zynqhdr->image_load));
+	printf("Checksum     : 0x%08x\n", le32_to_cpu(zynqhdr->checksum));
+
+	for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) {
+		if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT)
+			continue;
+
+		printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i,
+		       le32_to_cpu(zynqhdr->interrupt_vectors[i]));
+	}
+
+	for (i = 0; i < HEADER_REGINITS; i++) {
+		if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL)
+			break;
+
+		if (i == 0)
+			printf("Custom Register Initialization:\n");
+
+		printf("    @ 0x%08x -> 0x%08x\n",
+		       le32_to_cpu(zynqhdr->register_init[i].address),
+		       le32_to_cpu(zynqhdr->register_init[i].data));
+	}
+}
+
+static int zynqmpimage_check_params(struct image_tool_params *params)
+{
+	if (!params)
+		return 0;
+
+	if (params->addr != 0x0) {
+		fprintf(stderr, "Error: Load Address cannot be specified.\n");
+		return -1;
+	}
+
+	/*
+	 * If the entry point is specified ensure it is 64 byte aligned.
+	 */
+	if (params->eflag && (params->ep % 64 != 0)) {
+		fprintf(stderr,
+			"Error: Entry Point must be aligned to a 64-byte boundary.\n");
+		return -1;
+	}
+
+	return !(params->lflag || params->dflag);
+}
+
+static int zynqmpimage_check_image_types(uint8_t type)
+{
+	if (type == IH_TYPE_ZYNQMPIMAGE)
+		return EXIT_SUCCESS;
+	return EXIT_FAILURE;
+}
+
+static void zynqmpimage_set_header(void *ptr, struct stat *sbuf, int ifd,
+		struct image_tool_params *params)
+{
+	struct zynqmp_header *zynqhdr = (struct zynqmp_header *)ptr;
+	zynqmpimage_default_header(zynqhdr);
+
+	/* place image directly after header */
+	zynqhdr->image_offset =
+		cpu_to_le32((uint32_t)sizeof(struct zynqmp_header));
+	zynqhdr->image_size = cpu_to_le32(params->file_size -
+					  sizeof(struct zynqmp_header));
+	zynqhdr->image_stored_size = zynqhdr->image_size;
+	zynqhdr->image_load = 0xfffc0000;
+	if (params->eflag)
+		zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep);
+
+	zynqhdr->checksum = zynqmpimage_checksum(zynqhdr);
+}
+
+U_BOOT_IMAGE_TYPE(
+	zynqmpimage,
+	"Xilinx ZynqMP Boot Image support",
+	sizeof(struct zynqmp_header),
+	(void *)&zynqmpimage_header,
+	zynqmpimage_check_params,
+	zynqmpimage_verify_header,
+	zynqmpimage_print_header,
+	zynqmpimage_set_header,
+	NULL,
+	zynqmpimage_check_image_types,
+	NULL,
+	NULL
+);