| Commit message (Collapse) | Author | Age | Files | Lines |
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If a processor was booted in the second slot, it will be programmed
to use the memory for that slot. When it is installed in the first
slot it will then get reprogrammed to use the data for slot0.
However, if the new system only contains data for that 1 slot, we
won't be able to find a match to do the initial part of the boot.
This change will force some values into good enough shape to get
the boot far enough to do the SBE update to reprogram the memory
map.
Change-Id: I9b88d4181272104a8c680e9b5e84c4d204fdea05
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80680
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
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Sometimes generating incorrect L value for the darn instruction.
Removed the L variable and hard-coded into the instruction.
Change-Id: I5b478d2c220858942320f6fea3cb09d0ba6aee42
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79278
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Update random number generation, IPL and runtime.
Write encryption regs to enable nvdimm encryption,
crypto-erase, disable encryption. Read config-status
reg to verify encryption state.
Change-Id: I25625b53f90eeb542767fa729ebb47f8f8455a4b
RTC:201474
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77321
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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This commit fixes GCOV code coverage for P9 with GCC 4.9.2
Change-Id: Ie1e7c35f67414531dbd6e7a771ac1529a9ebd59d
RTC: 208351
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76812
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Fix issue where when compiling with GCC 8, illegal instruction of value
0x0 is placed instead of the expected "blr" instrusction.
Change-Id: I2ff28d5549689d541ea24d102230cbfc22cbbbff
RTC: 163075
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76650
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zachary Clark <zach@ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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While setting up the virtual memory mapped IO to the OCMB chips we
make some assumptions that the OCMB MMIO spaces will be contiguous.
The p9a_omi_setup_bars HWP uses OMI_INBAND_BAR_BASE_ADDR_OFFSET to
set the scom registers that determine the physical offset mapped
to the IO. When setting up the Virtual addresses hostboot uses to
represent the physical mmio address, we must validate that the attribute
matches with what we calculated. While doing this we found that the
virtual address attribute was being calculated incorrectly. It was
not localizing the OCMB position relative to the MC which is required
when calculating the offset into the MC bar.
Change-Id: I0ebbcd38e19a238e2cc16791bb0595536788bb7f
RTC: 201493
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75631
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Roland Veloz <rveloz@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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In istep14, need to call magic instruction 8021
in order to exit cache contained mode when running
simics.
Change-Id: I277f07420111c0383a7d9b61bf4d1750e39126f2
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75473
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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POWER9 added a new sync mode called 'msgsync' that is required
to avoid weak consistency issues when you are using doorbell
(msgsnd) functions.
See POWER ISA Section 5.9.2 for details, excerpt here:
The ordering done by sync (and ptesync) provides
the appearance of "causality" across a sequence of
msgsnd instructions, as in the following example.
"msgsnd->T1" means "msgsnd instruction target-
ting thread T1". "<DHDI 0>" means "occurrence of
Directed Hypervisor Doorbell interrupt caused by
msgsnd executed on T0". On T0, register r1 is
assumed to contain the value 1.
T0 T1 T2
std r1,X <DHDI 0> <DHDI 1>
sync msgsnd->T2 msgsync
msgsnd->T1 ld r1,X
In this example, T2's load from X must return 1.
The change here adds the msgsync call to the code that executes
any time we handle a doorbell interrupt. In addition there is a
POWER9 DD2 errata that indicates we also require a lwsync to
ensure consistency.
Change-Id: Ib0f3571926d71efcbffa205093278e2a1d58df85
CQ: SW454611
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70648
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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This commit introduces some new magic instructions one which will
temporarily elevate the log levels for given components and another
which will start and stop collection of these simics logs. This
was added so we can temporarily increase log levels during PSU
operations in hopes of catching a timeout we have been seeing
in simics and getting more info for the simics teams.
Change-Id: I990a4b5413f7ff14796dee36e39199f785aef458
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67359
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Ilya Smirnov <ismirno@us.ibm.com>
Reviewed-by: Hieu C. Nguyen <hieu.nguyen@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Support SMF for P9N/P9C. Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)
This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.
Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Add the new cpu type, update the pvr checks and other
miscellaneous changes to support a new Axone proc chip type
Change-Id: Ie2541bf826bdff65f6f11b0f16839855d69eb4d6
RTC: 173001
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64260
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Fixed some bad asm code
Change-Id: I6786a6010c682ce8bb5de74999da659ad2eb43d7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60775
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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There are two main changes in this commit:
1) Forcing an assert if we cannot allocate pages after
10,000 attempts to yield.
2) Adding a backtrace for a lot of exception paths.
Change-Id: I755ada753b78abed56e553f7c669f0f98ae68700
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58224
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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8001 - Tell Simics we are waiting on the FSP
8006 - Tell Simics we shutdown
8020 - Tell Simics which istep we're running
CQ: SW423959
Change-Id: Icea13d2ed7ff73de04400c46b9b1855e94db7c84
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58104
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Hieu C. Nguyen <hieu.nguyen@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Normally the OBUS PLL frequency is controlled via the MRW,
however P9NDD2.1 has a bug that forces the OBus freq to 25G.
Desire is to allow the MRW to set to a higher freq, but MRW
doesn't have entries for per chip EC, so this commit just
handles down leveling P9N DD2.1 (as a chip restriction)
Change-Id: I542f7810a69facb919cc3889ae3ed5ca0a233445
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55195
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
CI-Ready: Dean Sanner <dsanner@us.ibm.com>
CI-Ready: Corey V. Swenson <cswenson@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: ERICH J. HAUPTLI <ejhauptl@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: Iadfded90c09b149948348ee462ab34f9c2431982
RTC: 182134
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49865
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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during istep 15/16 of HCODE build/execution
Change-Id: I63f54cdc35b3ff7e68120a07c142b6a557257854
RTC: 180760
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49070
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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This enables buffer tracing at hostboot runtime.
Will add these traces to runtime errors for better debug
Change-Id: I795bb7deafdd02adea4588ebf8dfb11cbce116a0
RTC:172770
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48084
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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In the event that no memory is detected behind proc0. We will attempt
to use the memory behind a slave proc instead. When this occurs we
must adjust the interrupt bars to account for this swap
Change-Id: Ib37a190b7a7a2c655440ffd2bad56c351b4d4fa2
RTC: 173527
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40820
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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If the master processor has no memory behind it the entire
memory map must be modified. Each processor has its own statically
defined map that covers both memory and MMIOs. If the master
has no memory, its memory map is swapped with another processor.
Each processor gets a new effective fabric id that is then used
to compute all of the BAR values for those processors.
The SBE boots with a certain memory map programmed into the master
processor. That value is then passed up through the bootloader
into Hostboot. This value is compared to the BAR values that
Hostboot assumes it is using. Based on that comparison, various
attributes are computed to match the effective fabric positions.
Change-Id: I2b0d1959c303df8c9c28c8f0a5b5be1e77aa154f
RTC: 173528
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40359
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Change-Id: I9de1c4b08aceee76eed962413345c5e6d1444f23
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39947
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Added check for bit 18 to distinguish between Nimbus DD1.0 and
Cumulus DD1.0
Consolidated Nimbus DD1 checking to a common function
Added printk output that shows which CPU we're running on
Modified some existing printk output to use fewer characters
Change-Id: I1c42df0051fc2d9cc5fa54d95f68c3bd26b86462
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39876
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I8fc108877714ff76103510b7801af72a94e5aae3
RTC:160720
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39778
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Write current istep out to mbox scratch reg 5
Print istep out to simics console
Change-Id: I14d8a9afba12b627a0b1880e0818b5b16f317d7c
RTC: 171748
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39292
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
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Created new PVR_t structure that understands how to decode the
PVR for Nimbus DD1 and future versions.
Change-Id: Ie7e6f62d65fb1a3e11b1021f1600e7421b8c30a9
RTC: 160361
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37303
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
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Change-Id: I8a981628cd3adc54ba581deb0ce8afb183febef3
RTC: 150562
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29719
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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A quick change to add a new magic instruction that collects the
SBE traces any time we hit an error from the SBE. If multiple
errors occur they will all be appended to the same file.
Data will be saved to $sb/simics/sbetrace.hb.txt.
Change-Id: I27575c1565c0089e847e19c3e51cb2926833e387
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30206
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I58a382cfc285e37cc8748fe8e23f71c877850263
RTC: 130186
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/816
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I10b2be1ea9d0dc4a46c6c473b03ee024c6bf0de6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24801
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Created a new magic instruction handler that can be enabled via
environment variable to stop the simulation for Hostboot
exceptions. This is useful when we want to get a backtrace at
the failing spot without recompiling code or having to manually
insert breakpoints in simics directly.
Enable the function by setting HB_BREAK_ON_ERROR
The trigger call is MAGIC_BREAK_ON_ERROR
Change-Id: I17e008281d010e3f8c5e5817e5f30fd0ccb624d0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24600
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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- Change bit 24 to be reserved
Change-Id: Ic471d37bb304eb3ac06a37603762b6088f6bb2cb
CQ: SW352252
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24410
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Implemented a set of macros and constants that can be used
everywhere to translate a PIR into its component parts
and pull out individual pieces of data from a complete
PIR.
Also added and updated the references to the old
ATTR_FABRIC_NODE_ID with ATTR_FABRIC_GROUP_ID.
Change-Id: If9735f53940e5849a648729e4bf8ca0cfbb09f6e
RTC: 88055
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/706
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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Change-Id: I2ad133be733ee9e41590b3b8bd60bd6abe69d1a9
RTC: 126786
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22054
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ic5f234e0ce0747f887a706054f82372c9a96258c
RTC:126640
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19041
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ic5dfde1e975453d760631335bab674919e1109e7
RTC: 126637
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18321
Tested-by: Jenkins Server
Reviewed-by: Christian Geddes <crgeddes@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Ib4f3b0631a9afb92fd5950b1636b8a3077684dbc
Origin: Google Shared Technology
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11553
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5664587b4f889099290ef50d50fa9ce5e580e1eb
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/11167
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I743687d7072af303e62d638a7ee5ad6f89afbccb
RTC: 89403
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7484
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: Iccce5b641d0e2dc414bacc143a6b3e186f4e49ab
CQ: SW224728
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6960
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC:64829
Change-Id: Ic8e7983f6838b79c359c4cee2647b7676493cb1e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3564
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Support loading a fake payload that simply naps all the threads.
I am not enabling this via the simics_MACHINE.system.xml files
because it causes drastic usability concerns for developers wanting
to use the debug tools. When the payload is launched, the HRMOR
changes, which means the debug tools no longer point at Hostboot.
Change-Id: Ic899cf96af4d315f01c0ca4b7fc99e97c15d4dc1
RTC: 43029
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3642
Tested-by: Jenkins Server
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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For P8 the priority of different threads has no effect unless the
relative priority register is programmed to tell the relative
scheduling weight of the different priorities.
We will now be programming the RPR to give 32x performance boost
to "high" priority threads relative to "low" priority. This
means that when a thread is waiting on another, and thus has low
priority, it will get 32x less dispatch cycles then the thread
it is waiting on.
Change-Id: I0d1d1052b12ab8bd5612aa4580cd85b5c238f885
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2888
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I4a9cfc1f55c09ff6d02dce80889ac2e3150ab137
RTC: 44504
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1619
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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The Power processor has instructions of the form 'or a,a,a'
that allow code to change the priority of a hw-thread relative
to the others. We initially used 'or 1,1,1' as low priority
and 'or 3,3,3' as high priority. This is used in, for instance,
spinlocks to reduce the priority of a hw-thread while waiting
for another thread to perform an activity.
This code originally came from HAL. In reading the Power ISA
closer I realized that 'or 3,3,3' has no effect when in
user-space code, which means that a spinlock-like effect in
user code is going to end up with the thread stuck at low
priority until the next context switch. To prevent this we
are going to change from 1/3 to 1/2 as the priority levels.
Change-Id: I60ee866cde37499106f5e1e1d68a0b5ddeedf403
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1569
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 44730
Change-Id: Ifaeecc659e1bfd8ded4744dc591fc993471519ba
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1471
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Task 44887
Change-Id: If87b6e80b974bb4cbff13844d8a3f055a17282d2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1378
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 37009
Change-Id: I56669805c86d9659a20ad7c26e5e9860c7a248c7
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1087
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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RTC: 40764
Change-Id: Ic5b5b3e80915cb4f0ee543baa6fe4abc51e07ad2
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1079
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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- Reduce DCBZ and ICBI calls in memory copy and init functions.
- Reduce strlen calls in trace.
- Set thread to low priority while waiting on in-kernel barrier.
Change-Id: Ic9c23b1e26797ff393e5862819830de60554747e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/871
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
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Change-Id: I5f5d9c30b4cc0f0d8704fb99c10757e0f41018bf
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/603
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
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