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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-12-05 15:10:45 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-09-24 12:17:16 -0500 |
| commit | fcfd722a6abb01f780c10de0f5d801a9c4210ebd (patch) | |
| tree | 49cfafdc273b1aa7989d851d7c17fbb74dd54b0b /src/include/arch | |
| parent | 69cc45d8f059a113f6bad12e1fdd82123497893a (diff) | |
| download | talos-hostboot-fcfd722a6abb01f780c10de0f5d801a9c4210ebd.tar.gz talos-hostboot-fcfd722a6abb01f780c10de0f5d801a9c4210ebd.zip | |
Support HB running in SMF
Support SMF for P9N/P9C. Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)
This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.
Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/include/arch')
| -rw-r--r-- | src/include/arch/memorymap.H | 3 | ||||
| -rw-r--r-- | src/include/arch/ppc.H | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/src/include/arch/memorymap.H b/src/include/arch/memorymap.H index b20e43425..a25bcb62d 100644 --- a/src/include/arch/memorymap.H +++ b/src/include/arch/memorymap.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -61,6 +61,7 @@ constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR = 0x000603020310 constexpr uint64_t MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR = 0x0006020000000000; constexpr uint64_t MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR = 0x00060302031C0000; constexpr uint64_t MMIO_GROUP0_CHIP0_INTP_BASE_ADDR = 0x0003FFFF80000000; +constexpr uint64_t IS_SMF_ADDR_BIT = 0x0001000000000000; #endif //#ifndef _MEMORYMAP_H diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H index 977f712d9..241e123de 100644 --- a/src/include/arch/ppc.H +++ b/src/include/arch/ppc.H @@ -273,6 +273,14 @@ inline uint64_t getHRMOR() } ALWAYS_INLINE +inline uint64_t getURMOR() +{ + register uint64_t urmor = 0; + asm volatile("mfspr %0, 505" : "=r" (urmor)); + return urmor; +} + +ALWAYS_INLINE inline uint64_t getPTCR() { register uint64_t ptcr = 0; |
