NVDIMM encryption HW function support

Update random number generation, IPL and runtime.
Write encryption regs to enable nvdimm encryption,
crypto-erase, disable encryption. Read config-status
reg to verify encryption state.

Change-Id: I25625b53f90eeb542767fa729ebb47f8f8455a4b
RTC:201474
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77321
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matthew Raybuck <matthew.raybuck@ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 20 insertions, 0 deletions

diff --git a/src/include/arch/ppc.H b/src/include/arch/ppc.H
index b0c076d0a..2e6639da9 100644
--- a/src/include/arch/ppc.H
+++ b/src/include/arch/ppc.H
@@ -417,6 +417,26 @@ inline void writeScratchReg(uint64_t _scratch_addr, uint64_t _data)
 
 }
 
+#ifdef __HOSTBOOT_RUNTIME
+
+/** @brief  getDarn - deliver a random number instruction
+ *  Returns 64 bits of random data, requires random number generator
+ *  configured appropriately + locked down, only available at runtime.
+ */
+ALWAYS_INLINE
+inline uint64_t getDarn()
+{
+    register uint64_t rt = 0;
+    register uint64_t  L = 1;  // L=1 conditioned random number
+    asm volatile(".long 0x7C0005E6 | "
+                 "((%0 & 0x1F) << 21)  | "
+                 "((%1 & 0x3)  << 16)" :
+                 "=r" (rt), "=r" (L));
+    return rt;
+}
+
+#endif
+
 /** @brief  This is a special assembler instruction that is a nop on
  *  regular hardware, but has special meaning to Simics.  Code that
  *  executes this instruction in Simics will cause a "hap," a