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* Add slbv, slbe extraction to p9_ram_core procedureJenny Huynh2019-08-262-3/+17
| | | | | | | | | | | | | | | Change-Id: I6efe5d4f8fbb9f893a2371acd108d9d1d3002ecd Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82496 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K Light <mklight@us.ibm.com> Reviewed-by: Thi N Tran <thi@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82504 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
* p9_proc_gettracearray -- updates for AxoneJoe McGill2019-08-203-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_tracearray_defs.H: - adjust value of PROC_TB_LAST_AXONE_CHIP_TARGET, to cover NPU busses only - introduce PROC_TB_LAST_AXONE_MC_TARGET, to cover OMI busses that logically associate with MC pervasive targets p9_proc_gettracearray.H: - update proc_gettracearray_target_type to return TARGET_TYPE_MC for Axone OMI busses p9_sbe_tracearray.H: - update p9_sbe_tracearray_target_type to return TARGET_TYPE_PERV for Axone OMI busses p9_proc_gettracearray_wrap.C: - add eCMD looper to determine chip type - use chip type to swizzle target type returned by proc_gettracearray_target_type from MCBIST to MC, when running on Axone or Cumulus Change-Id: I5c729385c685ed3b1aac02f1f63b2c81f3e2f0e0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82308 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Adam S Hale <adam.samuel.hale@ibm.com> Dev-Ready: Joseph J McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82318 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
* p9_nv_ref_clk_enable, NV refclk bits moved to ROOT_CTRL7 for Axone.Ben Gass2019-08-021-8/+26
| | | | | | | | | | | | | | | Change-Id: I9b7e316dcdb2545d38426fe6cd29429e92305be2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79959 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N Tran <thi@us.ibm.com> Reviewed-by: Mark S Fredrickson <mfred@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/79980 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
* Streamline the way PIB/NET are initialized between SBE and CronusJoachim Fenkes2019-07-301-65/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of p9_start_cbs swinging the PCB mux to PIB2PCB, do it in p9_sbe_tp_chiplet_init1. The PIBMEM repair code on the SBE does it this way already so no change is needed there. This way, even if we start the SBE but then run isteps in Cronus, both pieces of code will work correctly since they don't depend on previous steps leaving the mux in a specific state. Change-Id: I4a2bd53f813cbb0a00486effb156a3c2a7f4336a CQ: SW470122 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81162 Reviewed-by: Joseph J McGill <jmcgill@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Milton D Miller <miltonm@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81193 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
* update i2c bit rate divisor for p9aJoe McGill2019-06-181-2/+8
| | | | | | | | | | | | | | | | | | | p9a i2cm HW changes require nest/4/2/4 programming Change-Id: Ib29c307fa2250f5096578809e3d0cb10a027086e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78640 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78665 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_tracearray: Updates for AxoneJoachim Fenkes2019-04-304-37/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | Add new trace bus names and trace array definitions for Axone. Some trace buses are just renamed, but I decided to add separate constants for clarity. Simplify the "can I dump the core trace arrays?" logic since no chips of the P9 family can have their core traces dumped via SCOM. Improve SBE size of ta_defs. Change-Id: I276f867a7fe9387fec9b7b216137767154ba1928 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67593 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67597 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Move lpc_rw to a source filespashabk-in2019-02-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | Moving lpc_rw to its source file to avoid code duplication if more than one file includes lpc_utils.H. This is mainly required by SBE to use lpc_rw for virtual PNOR access. Change-Id: Ib9cbb0abd74806959e4b78f3be2ade23066780cd Original-Change-Id: I7de30bcbae932307e0b63d8d42ae6ce050753339 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64296 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71488 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Skip final error check for Fleetwood GA1Joachim Fenkes2019-02-121-0/+2
| | | | | | | | | | | | | | | | | | As a temporary workaround for SW440738, ignore errors after LPC init so we don't halt the IPL for a benign LPC error on the alt master LPC. If the master LPC happens to have a problem we'll find out soon enough. Change-Id: I2d97efe6b49bfab83b834dde31ed878588339bd0 CQ: SW440738 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65767 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71487 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2019-02-121-1/+1
| | | | | | | | | | | | This reverts commit 77b6c7e6b123b32e37d07db91b0478a938a4d4a7. Change-Id: I95ffbf3404932c027093ea614ff979178292edeb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65113 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71486 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2019-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The LPC host controller has an interesting way to decode the timeout value. The left 4 bits are used for the "short wait" timeout, while the entire 8 bits are used for the "long wait" timeout. If the "short wait" timeout is 0xF, it is taken to be infinite, causing the host controller to hang if the slave doesn't respond. Change the timeout value from 0xFE to 0xEF, the correct maximum value that is not decoded to be infinity. Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360 CQ: SW442999 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71485 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Introducing lpc utils source filespashabk-in2019-02-121-0/+1
| | | | | | | | | | | | | | | | | | Including the dummy file so that the platforms could mirror this file without breaking existing implementation. Will follow up with separation of lpc_rw into source file on top of mirrored commits Change-Id: Ic166f82015a37fd7dbb3c799d25677016f0cf33a Original-Change-Id: I4596af3a8740cb9593f135a0138e84299a5946ac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64298 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71484 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Improve resetJoachim Fenkes2019-02-121-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The sequence to switch the LPC HC clock onto the nest clock temporarily was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it never really switched the clocks during reset. Also, for good measure, keep the clock switched to the nest clock while we're resetting the LPC bus. (Bonus change: Decrease the sim delay cycles waiting for a command to complete.) Change-Id: I5d463977d21df4dfe30f3c6fc02ed12dd3d19ebe Original-Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b CQ: SW439536 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71483 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Add final check for errorsJoachim Fenkes2019-02-122-0/+13
| | | | | | | | | | | | | | | | | | | | Add an external FFDC collection procedure that will dump the LPC register spaces, make sure it is called if after LPC setup an OPB error is registered. Change-Id: Ia4b31ced6c322cb56a7d408f66ac07c459bf5d9a Original-Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b CQ: SW435433 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71482 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Fix timeout setupJoachim Fenkes2019-02-122-37/+27
| | | | | | | | | | | | | | | | | | | | | Factor LPC register access out into its own utility function, with added timeout for the ADU access and proper FFDC if the ADU times out. CQ: SW418354 Change-Id: Id08653f49ddb66442533bf93a7a2ce8f72135c11 Original-Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71481 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Update hardware procedure metadataAnusha Reddy Rangareddygari2019-02-122-2/+2
| | | | | | | | | | | | | | | | | | | | update the metadata to reflect that HWPs are product ready (HWP Level: 3) Change-Id: Icd3b792359777652362c77e48de00c07dba5b430 Original-Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71480 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Fix LPC bus LRESET for DD2Joachim Fenkes2019-02-122-64/+111
| | | | | | | | | | | | | | | | | | | | | | Change the order of operations so that first the LPC Master is reset, then the bus reset is driven with a proper delay. Previously the bus reset duration depended on the code path taken (DD1 vs. DD2) and was likely too short on DD2. Also extract the various parts of the sequence into individual functions to improve readability. Change-Id: I55cd750735ae21131c57c185ffc8a4fa1392b2dc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44416 Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71479 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Do the real LPC reset for DD2CHRISTINA L. GRAVES2019-02-122-0/+32
| | | | | | | | | | | | | | | Change-Id: I6a3089e7f33fd69b82dc23a5d2e4f495a1ce8b75 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35698 Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/35702 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Adding in LPC and OPB timeout valuesCHRISTINA L. GRAVES2019-02-121-1/+15
| | | | | | | | | | | | | | Change-Id: I5a15d272d4fd5a5953a2057a02eb4c54f1438108 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33740 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71478 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2019-02-121-0/+32
| | | | | | | | | | | | | Change-Id: I103627369c600308e16e87c7b46184ed63c85794 Original-Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71477 Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Fixing order of setting clock muxes & functional reset & removing sim only scomsCHRISTINA L. GRAVES2019-02-121-40/+5
| | | | | | | | | | | | | Change-Id: I6234bfa16add15f7d1cd1cecc47b0e4f05733846 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31845 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71476 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Adding in configurations for PNOR/LPC communicationCHRISTINA L. GRAVES2019-02-121-0/+40
| | | | | | | | | | | | | | | | | | Adjust default LPC base address offset in image (0000030000000000) Change-Id: I98b1ddf8fc9d515b65b20421e9e480ba4def8b9f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28570 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71475 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2019-02-121-2/+2
| | | | | | | | | | | | | | Change-Id: I2fe927821e9c940ffa249165486960228993b45a Original-Change-Id: Iac3116df68febfd228e7e0dc19c30526ac932906 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27804 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71474 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2019-02-122-7/+6
| | | | | | | | | | | | | | | Change-Id: I2343dcaad657640258bcdf7954a9b5702a1061aa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24885 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71473 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Level 2 Procedure - p9_sbe_lpc_initSunil.Kumar2019-02-123-26/+68
| | | | | | | | | | | | | Change-Id: I55b70b8a2c1f6b4eccf3a75d09e6431c91e5872a Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20801 Tested-by: Jenkins Server Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71472 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2019-02-122-0/+117
| | | | | | | | | | | | | | | Change-Id: I6dc2cb6bc8358901e260805d5f5e204616927981 Original-Change-Id: I3ea0eec08ce479057277524021bfce540d7b63ca Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17755 Reviewed-by: Brian Silver <bsilver@us.ibm.com> Tested-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71471 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Adding p9a_ocmb_enableBen Gass2019-02-043-0/+235
| | | | | | | | | | | | | | | | | | Change-Id: I0e28ee52ad9088e87dd02ce2deca4e88bfcd9d8f Original-Change-Id: I40fbbf9a6323163d8c064ec435dc0cc666dcb0ab Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68088 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RYAN P. KING <rpking@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71215 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Remove SBE region fence check - p9_extract_sbe_rcSoma BhanuTej2019-01-181-5/+5
| | | | | | | | | | | | | | | | | Change-Id: I3e78fe7ee42e194fb764205dff7f63fec1e637f7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70283 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70287 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Axone updates to p9_extract_sbe_rcSoma BhanuTej2018-12-141-22/+72
| | | | | | | | | | | | | | | | | | | | | - Fix PIBMEM Interrupt Vector for Axone - Modify PIB-PCB Mux check error to no recovery Change-Id: Iee73735eb10b9a05aabc94f03012aff41481c086 RTC: 183052 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67231 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67279 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Support 1byte data access on LPCspashabk-in2018-09-272-6/+40
| | | | | | | | | | | | | | | | | | | | | | Currently LPC driver supports only 4bytes data access, with this commit introducing support for 1byte and also a way to extend this to 2bytes. RTC: 194000 Change-Id: I7cb258425100c2d2a3e78f35f0aaf7da1c0e8508 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64174 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64177 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Move lpc_rw to a source filespashabk-in2018-09-252-65/+83
| | | | | | | | | | | | | | | | | | | | | | Moving lpc_rw to its source file to avoid code duplication if more than one file includes lpc_utils.H. This is mainly required by SBE to use lpc_rw for virtual PNOR access. Change-Id: I7de30bcbae932307e0b63d8d42ae6ce050753339 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64296 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64310 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Axone only-IPL Procedures update to support SBE changesAbhishek Agarwal2018-09-103-2/+70
| | | | | | | | | | | | | | | | | | Using SBE_AXONE_CONFIG compile flag for Axone specific changes Change-Id: I3d67c8f9ebba9fc18925ae02d1fff3cca8a9440b Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53714 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/53736 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Update p9_sbe_i2c_bit_rate_divisor_setting to set I2C Rate Valid bitBill Hoffa2018-08-291-1/+13
| | | | | | | | | | | | | | | | | | | | | | | - Set Bit 1 (SBE I2C Bus speed based, ref clock valid) on Mailbox Scratch Reg 8 (CFAM 283F) to indicate the i2c bit rate divisor (set in Mailbox Scratch Reg 2) is correct - Without this change if the SBE needs to be restarted after a reset/reload it will use the default i2c divisor value which isn't always correct Change-Id: I2d0f071a0af42278bac886fce04a08d0c38682eb CQ: SW440895 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64697 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64705 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Introducing lpc utils source filespashabk-in2018-08-211-0/+24
| | | | | | | | | | | | | | | | | | | | Including the dummy file so that the platforms could mirror this file without breaking existing implementation. Will follow up with separation of lpc_rw into source file on top of mirrored commits Change-Id: I4596af3a8740cb9593f135a0138e84299a5946ac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64298 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64300 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* p9_sbe_lpc_init: Improve resetJoachim Fenkes2018-08-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The sequence to switch the LPC HC clock onto the nest clock temporarily was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it never really switched the clocks during reset. Also, for good measure, keep the clock switched to the nest clock while we're resetting the LPC bus. (Bonus change: Decrease the sim delay cycles waiting for a command to complete.) Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b CQ: SW439536 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63287 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Add constants to core checkstop handlerDan Crowell2018-07-252-1/+5
| | | | | | | | | | | | | | | | | Added some constants to make the arguments into the core checkstop handler code more obvious. Change-Id: I8e29b653a925096d867dc0e97d0ecaca3d412721 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62905 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63238 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Disable SBE HW i2c reset sequence on hresetSachin Gupta2018-07-231-0/+4
| | | | | | | | | | | | | | | | | Change-Id: I5dc6a9082876d7658cabf4e559e91cb310081835 CQ: SW437922 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62884 Reviewed-by: Sandeep Korrapati <sakorrap@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62897 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Secure memory allocation and setupJenny Huynh2018-07-131-16/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57348 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* BugFix for extract_sbe_rcSoma BhanuTej2018-07-101-1/+1
| | | | | | | | | | | | | | | | | | | - Fixing the checking condition for updating IAR from SRR0 Change-Id: Ia9e6e36dc64b95b3b4d53609810ebf89c2c7dd42 CQ: SW436877 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61932 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61937 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_cen_framelock update for channel failure attentionsThi Tran2018-07-091-64/+192
| | | | | | | | | | | | | | | | | | Updates CHIFIR attention settings based on changes of fir_chifir.xml from commit https://ralgit01.raleigh.ibm.com/gerrit1/#/c/58577 Change-Id: I53f63c4865737aae8a0719a9f21088177ccd2588 CQ:SW431715 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61567 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Marc Gollub <gollub@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61575 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_common -- mark TP LFIR bit 37 as recoverableJoe McGill2018-06-141-1/+1
| | | | | | | | | | | | | | | | | | | | | TP LFIR 37 is meant to be marked recoverable for Cumulus 60118 unmasked the bit, but the default action register settings are programmed to trigger a checkstop. This adjust the action1 register default to recoverable. Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60262 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Add Locking of Abus Sec MailboxesIlya Smirnov2018-06-042-4/+14
| | | | | | | | | | | | | | | | | | | | Add logic to support Abus security mailbox locking to p9_update_security_ctrl. This updated procedure will be called in istep 18 to secure the Abus mailboxes. Change-Id: Ie89df465299856d39dc5fa2bba6f9a9c38da469a RTC: 191005 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59489 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59495 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_common -- mark TP LFIR bits 18:20 recoverableJoe McGill2018-05-311-2/+2
| | | | | | | | | | | | | | | | | Change-Id: I641636e54dcc615cdf8f2de6f43d6878275113bf CQ: SW427932 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59591 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59607 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_spr_name_map -- change mnemonic for SPR 511 to SMFCTRLJoe McGill2018-05-191-2/+2
| | | | | | | | | | | | | | | | Change-Id: Ib279b63e91db8d648e8d57585f804460c8aca7ec Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55265 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55375 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Remove clear(step 3) of reset vectorsspashabk-in2018-05-182-8/+2
| | | | | | | | | | | | | | | | | | | | Making the reset vector bits sticky to figure out hreset flow Clear the reset vectors on start cbs Change-Id: I78273cf14a3f623052e8c01618b2596323801207 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57732 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57738 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* BugFix in progm exception & update brief infoSoma BhanuTej2018-04-201-18/+24
| | | | | | | | | | | | | | | | | Change-Id: I2929a5d6e6aeb657bad5ab1da5263b1fc7f34098 CQ: SW425836 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56992 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56995 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Adding changes to handle core checkstopsElizabeth Liner2018-04-183-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | At certain points during the IPL, we need to turn off unit checkstops and switch them to system checkstops. This HWP saves off the original value, turns unit to system checkstops, and then later restores them. Change-Id: I2f4137ca0f429b8e3d7b9047412a4e743324adbf Original-Change-Id: Iebd1d4c5b69eae04f05b890c879d8dd88f0655d3 RTC:147565 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56331 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57375 Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
* Add unmask errors back to cen_framelockLuke Mulkey2018-04-132-3/+13
| | | | | | | | | | | | | | | | Change-Id: Ia05fadcd6676f2c076bad14002d6afc26953aaf9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56027 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: LUCAS W. MULKEY <lwmulkey@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56037 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
* Enhance p9_extract_sbe_rcSoma BhanuTej2018-04-111-18/+57
| | | | | | | | | | | | | | | | | | | | | | -> Return error rc for invalid parameters -> Update OTPROM error detection -> Move L1 & L2 loader section in prog exception -> Add power check for fsp mode -> Extra debug msg when HC is 0 Change-Id: I864cbc19f4f85cad7bb717af957b26b930437eba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52356 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52363 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* Unmask MCA Command Sequence error bitThi Tran2018-04-101-3/+0
| | | | | | | | | | | | | | | | Change-Id: Ib26b15ac6c506cedfc9d74f582b21696b7823d14 CQ: SW413273 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56647 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56732 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
* p9_sbe_lpc_init: Fix cycle sim delay loopSoma BhanuTej2018-04-101-2/+3
| | | | | | | | | | | | | | | | | | | | Adding additional delay during polling for LPC status Issue encountered in GSD2PIB mode Awan simulations only Change-Id: I220843de8c37fa578ea26ea253345a380666a1d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56724 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56780 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
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