Secure memory allocation and setup

p9_mss_eff_grouping.C:
  - determines whether secure mem is requested, reserves smf space
  - always reserve smf at end of range because of end-of-range bit
  - set addr15 when reporting smf base address
  - mask off group_id(0) via chip address extension if smf is enabled
  - updated to set value of attr_smf_enabled
  - enhanced error reporting with smf config/supported values
  - made values reported to attr_mss_mcs_group_32 more clear

p9_mss_setup_bars.C:
  - set MCFGPA/MCFGPMA registers with SMF data
  - fixed scom registers for MCFGPA/MCFGPMA hole setup
  - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
  - added assert to check for HOLE1 and SMF enable overlaps

p9_query_mssinfo.C:
  - updated to print out SMF reservations
  - print out HTM/OCC/SMF reservations regardless of mirroring enable

p9_fbc_utils.C:
  - prevent group_id(0)=1 from affecting mappable memory ranges

p9_sbe_fabricinit.C:
  - mask off group_id(0) via chip address extension if smf is enabled

p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
  - use scratch_reg6 bit(16) to pass smf_config value

initfiles:
  - removed setup to use other addr bits as secure bit; core only uses addr15
  - added setup for ncu addr15 value in hcode
  - always set addr15 config bit in bridge unit if smf is supported
  - set addr15 bit across all mcs if smf is enabled
  - added in settings to enable smf in nmmu unit
  - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported

attributes:
  - ATTR_SMF_ENABLE is a system level attribute
  - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)

CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57348
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

1 files changed, 32 insertions, 16 deletions

diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
index 636f345be..91b7635bc 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_setup_sbe_config.C
@@ -46,10 +46,10 @@
 enum P9_SETUP_SBE_CONFIG_Private_Constants
 {
     // Scratch_reg_1
-    ATTR_EQ_GARD_STARTBIT             = 0,
-    ATTR_EQ_GARD_LENGTH               = 6,
-    ATTR_EC_GARD_STARTBIT             = 8,
-    ATTR_EC_GARD_LENGTH               = 24,
+    ATTR_EQ_GARD_STARTBIT              = 0,
+    ATTR_EQ_GARD_LENGTH                = 6,
+    ATTR_EC_GARD_STARTBIT              = 8,
+    ATTR_EC_GARD_LENGTH                = 24,
 
     // Scratch_reg_2
     ATTR_I2C_BUS_DIV_REF_STARTBIT      = 0,
@@ -58,8 +58,8 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_OPTICS_CONFIG_MODE_OBUS1_BIT  = 17,
     ATTR_OPTICS_CONFIG_MODE_OBUS2_BIT  = 18,
     ATTR_OPTICS_CONFIG_MODE_OBUS3_BIT  = 19,
-    ATTR_MC_PLL_BUCKET_STARTBIT      = 21,
-    ATTR_MC_PLL_BUCKET_LENGTH        = 3,
+    ATTR_MC_PLL_BUCKET_STARTBIT        = 21,
+    ATTR_MC_PLL_BUCKET_LENGTH          = 3,
     ATTR_OB0_PLL_BUCKET_STARTBIT       = 24,
     ATTR_OB0_PLL_BUCKET_LENGTH         = 2,
     ATTR_OB1_PLL_BUCKET_STARTBIT       = 26,
@@ -98,17 +98,18 @@ enum P9_SETUP_SBE_CONFIG_Private_Constants
     ATTR_SLOW_PCI_REF_CLOCK_BIT        = 5,
 
     // Scratch_reg_6
+    ATTR_SMF_CONFIG                        = 16,
     ATTR_PROC_EFF_FABRIC_GROUP_ID_STARTBIT = 17,
-    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH = 3,
-    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT = 20,
-    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH = 3,
-    ATTR_PUMP_CHIP_IS_GROUP            = 23,
-    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT = 26,
-    ATTR_PROC_FABRIC_GROUP_ID_LENGTH   = 3,
-    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT  = 29,
-    ATTR_PROC_FABRIC_CHIP_ID_LENGTH    = 3,
-    ATTR_PROC_MEM_TO_USE_STARTBIT = 1,
-    ATTR_PROC_MEM_TO_USE_LENGTH   = 6,
+    ATTR_PROC_EFF_FABRIC_GROUP_ID_LENGTH   = 3,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_STARTBIT  = 20,
+    ATTR_PROC_EFF_FABRIC_CHIP_ID_LENGTH    = 3,
+    ATTR_PUMP_CHIP_IS_GROUP                = 23,
+    ATTR_PROC_FABRIC_GROUP_ID_STARTBIT     = 26,
+    ATTR_PROC_FABRIC_GROUP_ID_LENGTH       = 3,
+    ATTR_PROC_FABRIC_CHIP_ID_STARTBIT      = 29,
+    ATTR_PROC_FABRIC_CHIP_ID_LENGTH        = 3,
+    ATTR_PROC_MEM_TO_USE_STARTBIT          = 1,
+    ATTR_PROC_MEM_TO_USE_LENGTH            = 6,
 };
 
 
@@ -526,6 +527,7 @@ fapi2::ReturnCode p9_setup_sbe_config(const
     }
     //set_scratch6_reg
     {
+        uint8_t l_smf_config;
         uint8_t l_pump_mode;
         uint8_t l_proc_chip_mem_to_use;
 
@@ -557,6 +559,20 @@ fapi2::ReturnCode p9_setup_sbe_config(const
             l_read_scratch_reg.setBit<24>();
         }
 
+        FAPI_DBG("Reading SMF_CONFIG");
+        FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG,
+                               fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),
+                               l_smf_config));
+
+        if (l_smf_config == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED)
+        {
+            l_read_scratch_reg.setBit<ATTR_SMF_CONFIG>();
+        }
+        else
+        {
+            l_read_scratch_reg.clearBit<ATTR_SMF_CONFIG>();
+        }
+
         FAPI_DBG("Reading PUMP MODE");
         FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE,
                                fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(),