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| author | CHRISTINA L. GRAVES <clgraves@us.ibm.com> | 2016-11-03 13:50:58 -0500 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-02-12 16:46:03 -0600 |
| commit | d7d6bff49f2219de594242224e66a1597d74000f (patch) | |
| tree | 41c7388f02d53d196a55dfa9e465b084be32485c /src/import/chips/p9/procedures/hwp/perv | |
| parent | b3c5dca5b4df7252e8c815d62487f35195b77229 (diff) | |
| download | talos-hostboot-d7d6bff49f2219de594242224e66a1597d74000f.tar.gz talos-hostboot-d7d6bff49f2219de594242224e66a1597d74000f.zip | |
p9_sbe_lpc_init fix with GPIO reset
Change-Id: I103627369c600308e16e87c7b46184ed63c85794
Original-Change-Id: I019d7ba16b4e39b5cf140fe1461218736ce329f5
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32199
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71477
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C index e137226e5..f0b10b329 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_lpc_init.C @@ -42,14 +42,34 @@ #include "p9_perv_scom_addresses.H" #include "p9_perv_scom_addresses_fld.H" #include "p9_misc_scom_addresses.H" +#include "p9_misc_scom_addresses_fld.H" fapi2::ReturnCode p9_sbe_lpc_init(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) { fapi2::buffer<uint64_t> l_data64; + uint8_t l_use_gpio = 0; + uint8_t l_is_fsp = 0; FAPI_DBG("p9_sbe_lpc_init: Entering ..."); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_LPC_RESET_GPIO, i_target_chip, l_use_gpio), + "Error getting the use_gpio_attr"); + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SP_MODE, i_target_chip, l_is_fsp), "Error getting ATTR_IS_SP_MODE"); + + if ((l_use_gpio != 0) && (l_is_fsp == fapi2::ENUM_ATTR_IS_SP_MODE_FSP)) + { + //LPC Reset active + l_data64.flush<1>().clearBit<0>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_GPIO_OUTPUT_SCOM2, l_data64)); + + //Set GPI0 output enable + FAPI_TRY(fapi2::getScom(i_target_chip, PU_GPIO_OUTPUT_EN, l_data64)); + l_data64.setBit<PU_GPIO_OUTPUT_EN_DO_EN_0>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_GPIO_OUTPUT_EN, l_data64)); + } + //Settting registers to do an LPC functional reset l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>(); FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_OR, l_data64)); @@ -70,6 +90,18 @@ fapi2::ReturnCode p9_sbe_lpc_init(const l_data64.flush<0>().setBit<CPLT_CONF1_TC_LP_RESET>(); FAPI_TRY(fapi2::putScom(i_target_chip, PERV_N3_CPLT_CONF1_CLEAR, l_data64)); + if ((l_use_gpio != 0) && (l_is_fsp == fapi2::ENUM_ATTR_IS_SP_MODE_FSP)) + { + //LPC Reset Disabled + l_data64.flush<0>().setBit<0>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_GPIO_OUTPUT_SCOM1, l_data64)); + + //Unset GPIO output enable + FAPI_TRY(fapi2::getScom(i_target_chip, PU_GPIO_OUTPUT_EN, l_data64)); + l_data64.clearBit<PU_GPIO_OUTPUT_EN_DO_EN_0>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PU_GPIO_OUTPUT_EN, l_data64)); + } + FAPI_DBG("p9_sbe_lpc_init: Exiting ..."); fapi_try_exit: |
