diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4')
21 files changed, 432 insertions, 408 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H index ab28d5b82..60b3c077b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,9 +40,10 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -276,7 +277,6 @@ struct cw_data /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -284,12 +284,12 @@ struct cw_data /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) + ccs::instruction_t& o_instruction) { // You're probably asking "Why always turn off CKE's? What is this madness?" // Well, due to a vendor sensitivity, we need to have the CKE's off until we run RC09 at the very end @@ -298,7 +298,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM // Therefore, we want to setup all RCW commands to have CKE's off across both DIMM's // We then manually turn on the CKE's associated with a specific DIMM constexpr bool CKE_OFF = false; - ccs::instruction_t<OT> l_inst = ccs::rcd_command<OT>(i_target, i_sim, CKE_OFF); + ccs::instruction_t l_inst = ccs::rcd_command(i_target, i_sim, CKE_OFF); // Turn on the CKE's for the ranks we're not touching, if it's needed // Note: we only have the whole CKE field, not the per DIMM one by default @@ -359,7 +359,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -367,14 +366,14 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for this RCW (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY(control_word_engine<T>(i_target, i_data, i_sim, i_turn_on_cke, l_inst)); io_inst.push_back(l_inst); @@ -386,7 +385,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -394,11 +392,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<cw_data>& i_data_list, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_data_list.empty(), @@ -495,7 +493,6 @@ struct cw_info /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info control word data and information about how to send it /// @param[in] i_sim true if in simulation mode @@ -503,12 +500,11 @@ struct cw_info /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const cw_info& i_info, - const bool i_sim, - const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const cw_info& i_info, + const bool i_sim, + const bool i_turn_on_cke, + ccs::instruction_t& o_instruction) { // BCW 4-bit if(i_info.iv_is_bcw && i_info.iv_data_len == CW4_DATA_LEN) @@ -548,7 +544,6 @@ fapi_try_exit: /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -556,12 +551,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::vector<cw_info>& i_info_list, - const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, - const bool i_turn_on_cke = true) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::vector<cw_info>& i_info_list, + const bool i_sim, + std::vector< ccs::instruction_t >& io_inst, + const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_info_list.empty(), fapi2::MSS_EMPTY_VECTOR(). @@ -571,7 +565,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM for (const auto& l_info : i_info_list) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY( control_word_engine(i_target, l_info, i_sim, i_turn_on_cke, l_inst) ); io_inst.push_back(l_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index d2bffc509..8cdb81f55 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -44,6 +44,9 @@ #include <lib/phy/dp16.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -96,6 +99,9 @@ enum db02_def : size_t HOST_VREF_CW = 0x5, // Func space 5 DRAM_VREF_CW = 0x6, // Func space 5 BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6 + + // Safe delays for BCW's + BCW_SAFE_DELAY = 2000, }; namespace ddr4 @@ -132,7 +138,7 @@ enum command : size_t /// inline fapi2::ReturnCode function_space_select(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const uint64_t i_func_space, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_ASSERT(i_func_space <= MAX_FUNC_SPACE, fapi2::MSS_LRDIMM_FUNC_SPACE_OUT_OF_RANGE() @@ -243,13 +249,13 @@ fapi_try_exit: template< mss::control_word T > static fapi2::ReturnCode settings_boilerplate(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const cw_data& i_data, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_sim = 0; mss::is_simulation(l_sim); // DES first - make sure those CKE go high and stay there - io_inst.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + io_inst.push_back(mss::ccs::des_command()); FAPI_TRY( function_space_select(i_target, i_data.iv_func_space, io_inst), "%s. Failed to select function space %d", @@ -271,17 +277,15 @@ fapi_try_exit: /// /// @brief Sets data buffer training mode control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_mode buffer training mode /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC0C) setting /// -template< fapi2::TargetType T > inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const training i_mode, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // This doesn't need to be reused so it is left local to this function scope static const std::vector< std::pair<training, uint64_t> > BUFF_TRAINING = @@ -302,7 +306,7 @@ inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_ uint64_t l_encoding = 0; fapi2::Assert(find_value_from_key(BUFF_TRAINING, i_mode, l_encoding)); - cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrd_l2()); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -362,17 +366,15 @@ fapi_try_exit: /// /// @brief Sets rank presence control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_num_package_ranks num of package ranks for LRDIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC07) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_rank_presence( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_num_package_ranks, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // Helper function handles error checking uint64_t l_encoding = 0; @@ -391,7 +393,6 @@ fapi_try_exit: /// /// @brief Sets Upper/Lower nibble DRAM interface receive enable training control word /// @tparam T the nibble of in training (upper/lower) -/// @tparam OT TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_rank DIMM0 rank [0:3] or DIMM1 rank [4:7] /// @param[in] i_trained_timing the delay MDQS receive enable timing @@ -399,11 +400,11 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word ( F[3:0]BC2x ) setting /// -template< mss::nibble N, fapi2::TargetType OT> +template< mss::nibble N > fapi2::ReturnCode set_mrep_timing_control( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, const uint64_t i_trained_timing, - std::vector< ccs::instruction_t<OT> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr size_t MAX_DELAY = 63; @@ -430,17 +431,15 @@ fapi_try_exit: /// /// @brief Sets command space control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_command command name /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC06) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const command i_command, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr uint64_t MAX_VALID_CMD = 4; @@ -453,9 +452,8 @@ inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TY } // From the DDR4DB02 Spec: BC06 - Command Space Control Word - // After issuing a data buffer command via writes to BC06 waiting for tMRC(16 tCK) - // is required before the next DRAM command or BCW write can be issued. - cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, mss::tmrc()); + // Waiting safe delay here as we've seen issues in the lab where the required tMRD_l2 isn't sufficient + cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, BCW_SAFE_DELAY); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -464,17 +462,15 @@ fapi_try_exit: /// /// @brief Sets per buffer addressibility (PBA) mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_state mss::ON or mss::OFF /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets DA0 setting for buffer control word (F0BC1x) /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mss::states i_state, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // PBA position is really bit 0, but we're right justified on our bit ordering here, so it's bit7 constexpr uint64_t PBA_POSITION = 7; @@ -495,7 +491,7 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI FAPI_TRY(mss::eff_dimm_ddr4_f0bc1x(i_target, l_nominal_bc_value)); { - cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrd_l2()); l_data.iv_data.writeBit<PBA_POSITION>(i_state); FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index 7676df23b..be59fe5e0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -36,11 +36,15 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> #include <lib/dimm/rank.H> #include <lib/workarounds/ccs_workarounds.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -62,7 +66,7 @@ namespace ddr4 fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // JEDEC has a 3 step latching process for WR VREF // 1) enter into VREFDQ training mode, with the desired range value is XXXXXX @@ -111,7 +115,7 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2 const auto l_mcbist = find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Warning: l_dimm is not a valid Target and will crash Cronus if used before it gets filled in by mss::rank::get_dimm_target_from_rank fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm; - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; std::vector<uint64_t> l_ranks; // Gets the ranks on which to latch the VREF's @@ -173,7 +177,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Check to make sure our ctor worked ok mrs06_data l_mrs06( i_target, fapi2::current_err ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index 0cb2a285e..4874000b8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -38,10 +38,14 @@ #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -65,7 +69,7 @@ enum wr_vref_override : uint8_t fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Add latching commands for WR VREF to the instruction array @@ -121,7 +125,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // close namespace DDR4 } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 71deb5bbe..0f0229a71 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -91,7 +96,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +118,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Map from Write Recovery attribute value to bits in the MRS. @@ -202,7 +207,7 @@ fapi_try_exit: /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -248,7 +253,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_burst_length = 0; @@ -264,10 +269,10 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs00; -fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs00_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 834ee1ead..cc5896c5c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -86,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -108,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Little table to map Output Driver Imepdance Control. 34Ohm is index 0, @@ -188,7 +193,7 @@ fapi_try_exit: /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -226,7 +231,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_dll_enable = 0; @@ -243,10 +248,10 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs01; -fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs01_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index fe819814b..43f90a0ee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -81,7 +81,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -105,7 +105,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CWL_LENGTH = 3; @@ -170,7 +170,7 @@ fapi_try_exit: /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -199,7 +199,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_write_crc = 0; @@ -212,10 +212,10 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs02; -fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs02_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index 06b9eb88c..4c797864b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -106,7 +106,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -130,7 +130,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { //Some consts for the swizzle action @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -228,7 +228,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_mpr_mode = 0; @@ -246,10 +246,10 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs03; -fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs03_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index b28dae69e..736f338de 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -105,7 +105,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -127,7 +127,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CS_CMD_LATENCY_LENGTH = 3; @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -232,7 +232,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_max_pd_mode = 0; @@ -255,10 +255,10 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs04; -fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs04_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index a4c5be8c6..e9be70395 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -91,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CA_PARITY_LATENCY_LENGTH = 3; @@ -188,7 +188,7 @@ fapi_try_exit: /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -231,7 +231,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_ca_parity_latency_buffer; @@ -252,10 +252,10 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs05; -fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs05_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C index bfc1fc885..554271727 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -79,7 +79,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -101,7 +101,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { @@ -159,7 +159,7 @@ fapi_try_exit: /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -188,7 +188,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_tccd_l_buffer; @@ -202,10 +202,10 @@ fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs06; -fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs06_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index cec455f6a..3ac509b6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -62,7 +62,7 @@ template< > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { FAPI_TRY( mrs_engine(i_target, i_data, i_rank, i_data.iv_delay, io_inst) ); @@ -138,7 +138,7 @@ namespace ddr4 /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target)); @@ -146,28 +146,82 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const size_t DOUBLE_TMRD = 2 * mss::tmrd(); const size_t DOUBLE_TMOD = 2 * mss::tmod(i_target); - static const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - // JEDEC ordering of MRS per DDR4 power on sequence - { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, - { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, - { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, - { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, - { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, - { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, - // We need to wait tmod before zqcl, a non-mrs command - { 0, mrs00, mrs00_decode, DOUBLE_TMOD }, - }; - - std::vector< uint64_t > l_ranks; - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // Load MRS - for (const auto& d : MRS_DATA) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 power on sequence + { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, + { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, + { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, + { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, + { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, + { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, + // We need to wait tmod before zqcl, a non-mrs command + // Adding Per Glancy's request, to ensure DLL locking time + { 0, mrs00, mrs00_decode, DOUBLE_TMOD + tDLLK }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) + { + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst) +{ + FAPI_INF("ddr4::mrs_load_nvdimm %s", mss::c_str(i_target)); + + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - for (const auto& r : l_ranks) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 NVDIMM restore sequence + // Need to perform DLL off to on procedure (mrs01&mrs00) + // before all the other MRS's + { 1, mrs01, mrs01_decode, mss::tmrd() }, + { 0, mrs00, mrs00_decode, mss::tmod(i_target) + tDLLK }, + { 3, mrs03, mrs03_decode, mss::tmrd() }, + { 6, mrs06, mrs06_decode, mss::tmrd() }, + { 5, mrs05, mrs05_decode, mss::tmrd() }, + { 4, mrs04, mrs04_decode, mss::tmrd() }, + { 2, mrs02, mrs02_decode, mss::tmrd() }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) { - FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } } } @@ -234,7 +288,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_override(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -274,7 +328,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -302,7 +356,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_nom_value[MAX_RANK_PER_DIMM] = {0}; @@ -335,7 +389,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Get original RTT_WR value uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index bd8277daa..5e6aa5c35 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -41,6 +41,9 @@ #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/eff_config/timing.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -99,13 +102,11 @@ enum rtt_nom_settings /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction - implementation -/// @tparam T typename of the ccs::instruction_t /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note written this way so this is easier to test /// -template<fapi2::TargetType T> -void address_mirror_impl(ccs::instruction_t<T>& io_inst) +inline void address_mirror_impl(ccs::instruction_t& io_inst) { // Nothing fancy here, just mirror the bits we're told to mirror in Table 14 — Address Mirroring and Inversion mss::template swap<A3, A4>(io_inst.arr0); @@ -118,17 +119,15 @@ void address_mirror_impl(ccs::instruction_t<T>& io_inst) /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction -/// @tparam T typename of the ccs::instruction_t /// @param[in] i_target target to use to get mirroring attribute /// @param[in] i_rank the rank in question /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note assumes the input is from an even number rank /// -template<fapi2::TargetType T> -fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - ccs::instruction_t<T>& io_inst) +inline fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + ccs::instruction_t& io_inst) { // We only mirror if the mirroring attribute is set. uint8_t l_mirror = 0; @@ -147,19 +146,17 @@ fapi_try_exit: /// /// @brief Invert (side to side) the ADR bits of a CCS instruction -/// @tparam T the target type of the ccs instruction /// @param[in] i_target the DIMM target of the ccs command /// @param[in] i_inst const reference to a CCS instruction. /// @param[in] l_is_a17 Boolean for whether A17 bit is enabled or not /// @return ccs instruction with the ADR bits inverted (side-to-side) /// -template<fapi2::TargetType T> -ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const ccs::instruction_t<T>& i_inst, - const bool i_is_a17 = false) +inline ccs::instruction_t address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const ccs::instruction_t& i_inst, + const bool i_is_a17 = false) { // Copy the input as the output doesn't all change. - ccs::instruction_t<T> i_out(i_inst); + ccs::instruction_t i_out(i_inst); // Nothing fancy here, just negate the bits we're told to negate in Table 14 — Address Mirroring and Inversion mss::template negate<A3>(i_out.arr0); @@ -189,7 +186,6 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// /// @brief Helper function to make a CCS instruction for an MRS -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -197,11 +193,11 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - ccs::instruction_t<T>& io_inst ) + ccs::instruction_t& io_inst ) { FAPI_TRY( D::make_ccs_instruction(i_target, i_data, io_inst, i_rank), "Failed making a CCS instruction for templated MRS data. MR%d rank %d on %s", @@ -219,11 +215,10 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// template< > -inline fapi2::ReturnCode make_ccs_helper( - const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, - const uint64_t i_rank, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst ) +inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, + const uint64_t i_rank, + ccs::instruction_t& io_inst ) { FAPI_TRY( i_data.iv_func(i_target, io_inst, i_rank), "Failed making a CCS instruction for mrs_data<TARGET_TYPE_MCBIST> specialization. MR%d rank %d on %s", @@ -235,17 +230,16 @@ fapi_try_exit: /// /// @brief Helper function to decode MRS and trace CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_data the completed MRS data to send /// @param[in] i_rank the rank to send to /// @param[in] i_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode decode_helper(const D& i_data, const uint64_t i_rank, - const ccs::instruction_t<T>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( D::decode(i_inst, i_rank), @@ -278,7 +272,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<T>& i_target, template< > inline fapi2::ReturnCode decode_helper(const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( i_data.iv_dumper(i_inst, i_rank), @@ -292,7 +286,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -301,15 +294,15 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, const uint64_t i_delay_in_cycles, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst_a_side = ccs::mrs_command<T>(i_rank, i_data.iv_mrs); - ccs::instruction_t<T> l_inst_b_side; + ccs::instruction_t l_inst_a_side = ccs::mrs_command(i_rank, i_data.iv_mrs); + ccs::instruction_t l_inst_b_side; bool l_is_a17 = false; // Thou shalt send 2 MRS, one for the a-side and the other inverted for the b-side. @@ -355,7 +348,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -363,11 +355,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); namespace ddr4 { @@ -395,7 +387,7 @@ class mrs06_data; /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -406,7 +398,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -417,7 +409,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs03 @@ -427,7 +419,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs04 @@ -437,7 +429,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs05 @@ -447,7 +439,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs06 @@ -457,7 +449,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -478,7 +470,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -491,7 +483,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -504,7 +496,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -517,7 +509,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -530,7 +522,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -543,7 +535,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -556,7 +548,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -579,7 +571,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -595,7 +587,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -611,7 +603,7 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -628,7 +620,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -641,7 +633,7 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -655,7 +647,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -672,7 +664,7 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -690,7 +682,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -709,7 +701,7 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -730,7 +722,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -748,7 +740,7 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -767,7 +759,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -780,7 +772,7 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -794,7 +786,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -818,10 +810,10 @@ struct mrs00_data // dynaimc polymorphism and I avoid that where possible. static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -909,10 +901,10 @@ struct mrs01_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1011,10 +1003,10 @@ struct mrs02_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1091,10 +1083,10 @@ struct mrs03_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1196,10 +1188,10 @@ struct mrs04_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1322,10 +1314,10 @@ struct mrs05_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1436,10 +1428,10 @@ struct mrs06_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1516,7 +1508,16 @@ struct mrs06_data /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Sets WR LVL mode @@ -1720,18 +1721,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set WR LVL Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for WR LVL mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mss::states i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mss::states i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Spec states we need to use tmod for our delay, so we do const uint64_t l_delay = mss::tmod(i_target); @@ -1754,18 +1753,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1789,7 +1786,6 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rd_format MPR read format @@ -1797,12 +1793,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint8_t i_rd_format, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint8_t i_rd_format, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1830,18 +1825,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_NOM value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_NOM /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1864,18 +1857,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_WR value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_WR /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1898,23 +1889,21 @@ fapi_try_exit: /// /// @brief Makes CCS instruction for an MPR read -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode MPR location /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_mpr_loc, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_mpr_loc, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Right now we only have support for RD and RDA // Unclear if we want the API select the type of read command right now // Note the auto precharge is ignored with MPR mode on so we just do a read cmd - ccs::instruction_t<T> l_inst = ccs::rd_command<T> (i_rank, i_mpr_loc); + ccs::instruction_t l_inst = ccs::rd_command (i_rank, i_mpr_loc); // In MPR Mode: // Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between read commands @@ -1948,18 +1937,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set precharge all command -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst = ccs::precharge_all_command<T> (i_rank); + ccs::instruction_t l_inst = ccs::precharge_all_command (i_rank); // From the DDR4 Spec tRP is the precharge command period uint8_t l_delay = 0; @@ -1995,58 +1982,54 @@ fapi2::ReturnCode rtt_wr_to_rtt_nom_helper(const fapi2::Target<T>& i_target, /// /// @brief Executes CCS instructions to set RTT_WR value into RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_override(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to disable RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // ddr4 } // mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index 869e18f25..8c19b99f9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,23 +33,25 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <vector> +#include <lib/shared/mss_const.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/nvdimm_utils.H> #include <lib/mc/mc.H> -#include <lib/ccs/ccs.H> #include <lib/dimm/rank.H> #include <lib/mss_attribute_accessors.H> +#include <lib/mcbist/mcbist.H> +#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/poll.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <lib/mcbist/address.H> #include <lib/mcbist/memdiags.H> -#include <lib/mcbist/mcbist.H> #include <lib/mcbist/settings.H> -#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/pos.H> #include <lib/mc/port.H> #include <lib/phy/dp16.H> @@ -82,7 +84,7 @@ fapi2::ReturnCode get_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_TYPE mss::states& o_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -105,7 +107,7 @@ fapi2::ReturnCode change_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_T const mss::states i_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -213,10 +215,10 @@ fapi2::ReturnCode self_refresh_exit_helper( const fapi2::Target<fapi2::TARGET_TY mss::mcbist::address l_start = 0, l_end = 0; mss::mcbist::end_boundary l_end_boundary = mss::mcbist::end_boundary::STOP_AFTER_SLAVE_RANK; l_start.set_port(l_port); - mss::mcbist::stop_conditions l_stop_conditions; + mss::mcbist::stop_conditions<> l_stop_conditions; // Read with targeted scrub - FAPI_TRY ( mss::memdiags::targeted_scrub(l_mcbist, + FAPI_TRY ( mss::memdiags::targeted_scrub<mss::mc_type::NIMBUS>(l_mcbist, l_stop_conditions, l_start, l_end, @@ -264,10 +266,14 @@ template<> fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data; + const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Entry time to 0 for immediate entry constexpr uint64_t l_str_entry_time = 0; + // Stop mcbist (scrub) in case of MPIPL. It will get restarted in the later istep + FAPI_TRY(mss::mcbist::start_stop(l_mcbist, mss::states::STOP)); + // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0, // and disable minimum domain reduction (allow immediate entry of STR) FAPI_TRY(mss::mc::read_mbarpc0(i_target, l_mbarpc0_data)); @@ -322,49 +328,6 @@ fapi_try_exit: } /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) -{ - FAPI_INF("rc09_disable_powerdown %s", mss::c_str(i_target)); - - constexpr uint8_t POWER_DOWN_BIT = 4; - constexpr bool l_sim = false; - constexpr uint8_t FS0 = 0; // Function space 0 - constexpr uint64_t CKE_HIGH = mss::ON; - fapi2::buffer<uint8_t> l_rc09_cw = 0; - std::vector<uint64_t> l_ranks; - - FAPI_TRY(mss::eff_dimm_ddr4_rc09(i_target, l_rc09_cw)); - - // Clear power down enable bit. - l_rc09_cw.clearBit<POWER_DOWN_BIT>(); - - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // DES to ensure we exit powerdown properly - FAPI_DBG("deselect for %s", mss::c_str(i_target)); - io_inst.push_back( ccs::des_command<TARGET_TYPE_MCBIST>() ); - - static const cw_data l_rc09_4bit_data( FS0, 9, l_rc09_cw, mss::tmrd() ); - - // Load RC09 - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), - "Failed to load 4-bit RC09 control word for %s", - mss::c_str(i_target)); - - // Hold the CKE high - mss::ccs::workarounds::hold_cke_high(io_inst); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -373,11 +336,11 @@ fapi_try_exit: /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("rcd_load_nvdimm %s", mss::c_str(i_target)); - constexpr uint64_t CKE_LOW = mss::OFF; + constexpr uint64_t CKE_HIGH = mss::ON; constexpr bool l_sim = false; // Per DDR4RCD02, tSTAB is us. We want this in cycles for the CCS. @@ -425,17 +388,19 @@ fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_targ }; // Load 4-bit data - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_LOW), + // Keeping the CKE high as this will be done not in powerdown/STR mode. Not affected for + // the RCD supplier on nvdimm + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit control words for %s", mss::c_str(i_target)); // Load 8-bit data - FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 8-bit control words for %s", mss::c_str(i_target)); // Load RC09 with CKE_LOW - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit RC09 control word for %s", mss::c_str(i_target)); @@ -456,34 +421,13 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) std::vector<uint64_t> l_ranks; // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector l_program.iv_poll.iv_initial_delay = 0; l_program.iv_poll.iv_initial_sim_delay = 0; - // We expect to come in with the port in STR. Before proceeding with - // restoring the RCD, power down needs to be disabled first on the RCD so - // the rest of the CWs can be restored with CKE low - for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) - { - FAPI_DBG("rc09_disable_powerdown for %s", mss::c_str(d)); - FAPI_TRY( rc09_disable_powerdown(d, l_program.iv_instructions), - "Failed rc09_disable_powerdown() for %s", mss::c_str(d) ); - }// dimms - - // Exit STR first so CKE is back to high and rcd isn't ignoring us - FAPI_TRY( self_refresh_exit( i_target ) ); - - FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target), - "Failed to execute ccs for %s", mss::c_str(i_target) ); - - // Now, drive CKE back to low via STR entry instead of pde (we have data in the drams!) - FAPI_TRY( self_refresh_entry( i_target ) ); - - l_program = ccs::program<TARGET_TYPE_MCBIST>(); //Reset the program - // Now, fill the program with instructions to program the RCD for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) { @@ -513,7 +457,7 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); std::vector<uint64_t> l_ranks; uint8_t l_trp[MAX_DIMM_PER_PORT]; - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Get tRP FAPI_TRY(mss::eff_dram_trp(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_trp)); @@ -526,9 +470,9 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA for ( const auto r : l_ranks) { FAPI_DBG("precharge_all_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::precharge_all_command<TARGET_TYPE_MCBIST>(r, l_trp[0]) ); + l_program.iv_instructions.push_back( ccs::precharge_all_command(r, l_trp[0]) ); FAPI_DBG("zqcal_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::zqcl_command<TARGET_TYPE_MCBIST>(r, mss::tzqinit()) ); + l_program.iv_instructions.push_back( ccs::zqcl_command(r, mss::tzqinit()) ); } }// dimms @@ -608,12 +552,12 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP FAPI_TRY(get_refresh_overrun_mask(i_target, l_refresh_overrun_mask)); FAPI_TRY(change_refresh_overrun_mask(i_target, mss::states::ON)); - // Restore the rcd - FAPI_TRY( rcd_restore( i_target ) ); - // Exit STR FAPI_TRY( self_refresh_exit( i_target ) ); + // Restore the rcd + FAPI_TRY( rcd_restore( i_target ) ); + // Load the MRS FAPI_TRY( mss::mrs_load( i_target, NVDIMM_WORKAROUND ) ); @@ -635,6 +579,26 @@ fapi_try_exit: } /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state) +{ + const auto& l_mcs = mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target); + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(l_mcs, MCS_MCFGP, l_data) ); + l_data.writeBit<MCS_MCFGP_VALID>(i_state); + FAPI_INF("Changing MCS_MCFGP_VALID to %d on %s", i_state, mss::c_str(l_mcs)); + FAPI_TRY( mss::putScom(l_mcs, MCS_MCFGP, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful @@ -643,15 +607,15 @@ fapi_try_exit: /// fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); const auto& l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(i_target); constexpr uint64_t CS_N_ACTIVE = 0b00; uint8_t l_trp = 0; uint16_t l_trfc = 0; std::vector<uint64_t> l_ranks; - ccs::program<TARGET_TYPE_MCBIST> l_program; - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::program l_program; + ccs::instruction_t l_inst; // Get tRP and tRFC FAPI_TRY(mss::eff_dram_trp(i_target, l_trp)); @@ -662,14 +626,14 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Start the program with DES and wait for tRFC // All CKE = high, all CSn = high, Reset_n = high, wait tRFC - l_inst = ccs::des_command<TARGET_TYPE_MCBIST>(l_trfc); + l_inst = ccs::des_command(l_trfc); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); FAPI_INF("des_command() arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); // Precharge all command // All CKE = high, all CSn = low, Reset_n = high, wait tRP - l_inst = ccs::precharge_all_command<TARGET_TYPE_MCBIST>(0, l_trp); + l_inst = ccs::precharge_all_command(0, l_trp); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); @@ -678,7 +642,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Self-refresh entry command // All CKE = low, all CSn = low, Reset_n = high, wait tCKSRE - l_inst = ccs::self_refresh_entry_command<TARGET_TYPE_MCBIST>(0, mss::tcksre(l_dimms[0])); + l_inst = ccs::self_refresh_entry_command(0, mss::tcksre(l_dimms[0])); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(mss::CKE_LOW); @@ -688,7 +652,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Push in an empty instruction for RESETn // All CKE = low, all CSn = high (default), Reset_n = low - l_inst = ccs::instruction_t<TARGET_TYPE_MCBIST>(); + l_inst = ccs::instruction_t(); FAPI_INF("Assert RESETn arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H index a3c4914a4..8345cae05 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H @@ -34,11 +34,11 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/shared/mss_const.H> -#include <lib/ccs/ccs.H> #include <lib/phy/dp16.H> #include <lib/mc/port.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -182,15 +182,6 @@ template< fapi2::TargetType T > fapi2::ReturnCode self_refresh_exit( const fapi2::Target<T>& i_target ); /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -199,7 +190,7 @@ fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Restore the rcd after restoring the nvdimm data @@ -237,6 +228,14 @@ template< fapi2::TargetType T > fapi2::ReturnCode post_restore_transition( const fapi2::Target<T>& i_target ); /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state); + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C index c1cab4997..a864ea8d2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C @@ -35,10 +35,11 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <lib/phy/phy_cntrl.H> #include <lib/dimm/ddr4/pba.H> @@ -113,7 +114,7 @@ fapi_try_exit: /// fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -145,7 +146,7 @@ fapi_try_exit: /// fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -200,10 +201,10 @@ fapi2::ReturnCode execute_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM> // Issue PBA commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Inserts the DES command to ensure we keep our CKE high - l_program.iv_instructions.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + l_program.iv_instructions.push_back(mss::ccs::des_command()); // Makes a copy of the vector, so we can do the function space swaps correctly auto l_bcws = i_bcws; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H index 34706d492..c2d47fed3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,8 +39,9 @@ #include <fapi2.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <map> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C index a89cee0e2..8eb698a62 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,13 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> +#include <lib/mc/port.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> @@ -49,6 +52,7 @@ #include <lib/dimm/ddr4/pda.H> #include <lib/workarounds/ccs_workarounds.H> + namespace mss { @@ -209,7 +213,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -232,7 +236,7 @@ fapi_try_exit: fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -261,7 +265,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -284,7 +288,7 @@ fapi_try_exit: fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -344,7 +348,7 @@ fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_ // Issue MRS commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; FAPI_TRY(mss::ddr4::add_latch_wr_vref_commands( i_target, i_mrs, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H index 379b0a2ba..c28dcceac 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,14 +38,18 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/phy/write_cntrl.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> + #include <map> namespace mss @@ -170,7 +174,7 @@ fapi2::ReturnCode blast_dram_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA> /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Enters into and configures PDA mode @@ -190,7 +194,7 @@ fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Exits out of and disables PDA mode @@ -313,7 +317,7 @@ class commands // Check for a valid rank FAPI_ASSERT(mss::rank::is_rank_on_dimm(i_target, i_rank), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). + set_PORT_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). set_RANK(i_rank). set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND), "%s does not have rank %lu", mss::c_str(i_target), i_rank); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C index 6e53bddd8..e522f970f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,13 +36,17 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/zqcal.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/eff_config/timing.H> #include <lib/workarounds/ccs_workarounds.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_DIMM; @@ -61,15 +65,15 @@ namespace mss template<> fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::instruction_t l_inst; uint64_t tDLLK = 0; FAPI_TRY( mss::tdllk(i_target, tDLLK) ); // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS - l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_rank); + l_inst = ccs::zqcl_command(i_rank); // Doubling tZQ to better margin per lab request { @@ -98,7 +102,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // For LRDIMMs, program BCW to send ZQCal Long command to all data buffers // in broadcast mode @@ -128,7 +132,7 @@ template<> fapi2::ReturnCode setup_and_execute_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const fapi2::buffer<uint32_t>& i_cal_steps_enabled) { - mss::ccs::program<TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; for ( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) ) { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H index d78a512f1..d80febc3b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,11 @@ #include <vector> #include <fapi2.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -46,28 +50,26 @@ namespace mss /// /// @brief Setup DRAM ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in] i_rank the current rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup LRDIMM data buffer ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<T>& i_target, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup and execute DRAM ZQCL |