diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/memory/lib/dimm')
38 files changed, 789 insertions, 867 deletions
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C index ae62be201..1b42026a4 100755 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,10 +34,15 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> - #include <mss.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/shared/mss_const.H> + #include <lib/dimm/bcw_load.H> #include <lib/dimm/bcw_load_ddr4.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -58,7 +63,7 @@ template<> fapi2::ReturnCode bcw_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector @@ -91,7 +96,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -121,7 +126,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform bcw_load for %s [expecting lrdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( bcw_load_ddr4(i_target, io_inst), "Failed bcw load for lrdimm %s", mss::c_str(i_target)); @@ -138,7 +143,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("Skipping BCW loading for %s since this is valid only for LRDIMMs", mss::c_str(i_target)); return fapi2::FAPI2_RC_SUCCESS; @@ -152,7 +157,7 @@ fapi2::ReturnCode perform_bcw_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_ /// template<> fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H index be5f1bfc5..4bdfe0033 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,10 +39,14 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> + namespace mss { @@ -113,7 +117,7 @@ struct perform_bcw_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_bcw_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_bcw_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); // // We know we registered overloads for perform_bcw_load, so we need the entry point to @@ -129,7 +133,7 @@ perform_bcw_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// template<> fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Perform the bcw_load operations (DEFAULT_KIND specialization) @@ -139,7 +143,7 @@ fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::T /// template<> fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); // // Boilerplate dispatcher @@ -157,7 +161,7 @@ fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_bcw_load_overload<K>::available > inline fapi2::ReturnCode perform_bcw_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -182,7 +186,7 @@ inline fapi2::ReturnCode perform_bcw_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_bcw_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { return perform_bcw_load<DEFAULT_KIND>(i_target, io_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C index 266e7ce56..0712939f3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C @@ -36,11 +36,13 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/utils/mss_nimbus_conversions.H> #include <lib/eff_config/timing.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/bcw_load_ddr4.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> @@ -48,6 +50,7 @@ #include <lib/workarounds/ccs_workarounds.H> #include <generic/memory/lib/spd/spd_utils.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; @@ -67,10 +70,8 @@ namespace mss /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { - constexpr uint64_t SAFE_DELAY = 2000; // Waiting a safe amount of time as the LRDIMM spec - // doesn't give us an explicit value for this delay FAPI_INF("bcw_load_ddr4 %s", mss::c_str(i_target) ); uint8_t l_sim = 0; @@ -104,21 +105,21 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FUNC_SPACE_0, DQ_DRIVER_CW, eff_dimm_ddr4_bc03, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_RTT_CW, eff_dimm_ddr4_bc04, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_DRIVER_CW, eff_dimm_ddr4_bc05, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works + { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works { FUNC_SPACE_0, RANK_SELECTION_CW, eff_dimm_ddr4_bc08, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, POWER_SAVING_CW, eff_dimm_ddr4_bc09, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, OPERATING_SPEED, eff_dimm_ddr4_bc0a, l_tDLLK , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, VOLT_AND_SLEW_RATE_CW, eff_dimm_ddr4_bc0b, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrd_l2() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, LDQ_OPERATION_CW, eff_dimm_ddr4_bc0d, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, PARITY_CW, eff_dimm_ddr4_bc0e, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, ERROR_STATUS_CW, eff_dimm_ddr4_bc0f, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, // 8-bit BCW's now // Function space 0 - we're already there, so that's nice - { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrd_l2() , CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 2 { FUNC_SPACE_2, FUNC_SPACE_SELECT_CW, FUNC_SPACE_2, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -126,8 +127,8 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // Function space 5 { FUNC_SPACE_5, FUNC_SPACE_SELECT_CW, FUNC_SPACE_5, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 6 { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -142,7 +143,7 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target }; // DES first - make sure those CKE go high and stay there - io_inst.push_back(mss::ccs::des_command<TARGET_TYPE_MCBIST>()); + io_inst.push_back(mss::ccs::des_command()); // Issues the CW's FAPI_TRY( control_word_engine(i_target, l_bcw_info, l_sim, io_inst), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H index 7e68d32d0..31ef02983 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,9 @@ #include <fapi2.H> #include <vector> -#include <lib/ccs/ccs.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -51,6 +53,6 @@ namespace mss /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H index ab28d5b82..60b3c077b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,9 +40,10 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -276,7 +277,6 @@ struct cw_data /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -284,12 +284,12 @@ struct cw_data /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) + ccs::instruction_t& o_instruction) { // You're probably asking "Why always turn off CKE's? What is this madness?" // Well, due to a vendor sensitivity, we need to have the CKE's off until we run RC09 at the very end @@ -298,7 +298,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM // Therefore, we want to setup all RCW commands to have CKE's off across both DIMM's // We then manually turn on the CKE's associated with a specific DIMM constexpr bool CKE_OFF = false; - ccs::instruction_t<OT> l_inst = ccs::rcd_command<OT>(i_target, i_sim, CKE_OFF); + ccs::instruction_t l_inst = ccs::rcd_command(i_target, i_sim, CKE_OFF); // Turn on the CKE's for the ranks we're not touching, if it's needed // Note: we only have the whole CKE field, not the per DIMM one by default @@ -359,7 +359,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -367,14 +366,14 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for this RCW (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY(control_word_engine<T>(i_target, i_data, i_sim, i_turn_on_cke, l_inst)); io_inst.push_back(l_inst); @@ -386,7 +385,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -394,11 +392,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<cw_data>& i_data_list, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_data_list.empty(), @@ -495,7 +493,6 @@ struct cw_info /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info control word data and information about how to send it /// @param[in] i_sim true if in simulation mode @@ -503,12 +500,11 @@ struct cw_info /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const cw_info& i_info, - const bool i_sim, - const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const cw_info& i_info, + const bool i_sim, + const bool i_turn_on_cke, + ccs::instruction_t& o_instruction) { // BCW 4-bit if(i_info.iv_is_bcw && i_info.iv_data_len == CW4_DATA_LEN) @@ -548,7 +544,6 @@ fapi_try_exit: /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -556,12 +551,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::vector<cw_info>& i_info_list, - const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, - const bool i_turn_on_cke = true) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::vector<cw_info>& i_info_list, + const bool i_sim, + std::vector< ccs::instruction_t >& io_inst, + const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_info_list.empty(), fapi2::MSS_EMPTY_VECTOR(). @@ -571,7 +565,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM for (const auto& l_info : i_info_list) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY( control_word_engine(i_target, l_info, i_sim, i_turn_on_cke, l_inst) ); io_inst.push_back(l_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index d2bffc509..8cdb81f55 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -44,6 +44,9 @@ #include <lib/phy/dp16.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -96,6 +99,9 @@ enum db02_def : size_t HOST_VREF_CW = 0x5, // Func space 5 DRAM_VREF_CW = 0x6, // Func space 5 BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6 + + // Safe delays for BCW's + BCW_SAFE_DELAY = 2000, }; namespace ddr4 @@ -132,7 +138,7 @@ enum command : size_t /// inline fapi2::ReturnCode function_space_select(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const uint64_t i_func_space, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_ASSERT(i_func_space <= MAX_FUNC_SPACE, fapi2::MSS_LRDIMM_FUNC_SPACE_OUT_OF_RANGE() @@ -243,13 +249,13 @@ fapi_try_exit: template< mss::control_word T > static fapi2::ReturnCode settings_boilerplate(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const cw_data& i_data, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_sim = 0; mss::is_simulation(l_sim); // DES first - make sure those CKE go high and stay there - io_inst.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + io_inst.push_back(mss::ccs::des_command()); FAPI_TRY( function_space_select(i_target, i_data.iv_func_space, io_inst), "%s. Failed to select function space %d", @@ -271,17 +277,15 @@ fapi_try_exit: /// /// @brief Sets data buffer training mode control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_mode buffer training mode /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC0C) setting /// -template< fapi2::TargetType T > inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const training i_mode, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // This doesn't need to be reused so it is left local to this function scope static const std::vector< std::pair<training, uint64_t> > BUFF_TRAINING = @@ -302,7 +306,7 @@ inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_ uint64_t l_encoding = 0; fapi2::Assert(find_value_from_key(BUFF_TRAINING, i_mode, l_encoding)); - cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrd_l2()); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -362,17 +366,15 @@ fapi_try_exit: /// /// @brief Sets rank presence control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_num_package_ranks num of package ranks for LRDIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC07) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_rank_presence( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_num_package_ranks, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // Helper function handles error checking uint64_t l_encoding = 0; @@ -391,7 +393,6 @@ fapi_try_exit: /// /// @brief Sets Upper/Lower nibble DRAM interface receive enable training control word /// @tparam T the nibble of in training (upper/lower) -/// @tparam OT TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_rank DIMM0 rank [0:3] or DIMM1 rank [4:7] /// @param[in] i_trained_timing the delay MDQS receive enable timing @@ -399,11 +400,11 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word ( F[3:0]BC2x ) setting /// -template< mss::nibble N, fapi2::TargetType OT> +template< mss::nibble N > fapi2::ReturnCode set_mrep_timing_control( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, const uint64_t i_trained_timing, - std::vector< ccs::instruction_t<OT> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr size_t MAX_DELAY = 63; @@ -430,17 +431,15 @@ fapi_try_exit: /// /// @brief Sets command space control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_command command name /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC06) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const command i_command, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr uint64_t MAX_VALID_CMD = 4; @@ -453,9 +452,8 @@ inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TY } // From the DDR4DB02 Spec: BC06 - Command Space Control Word - // After issuing a data buffer command via writes to BC06 waiting for tMRC(16 tCK) - // is required before the next DRAM command or BCW write can be issued. - cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, mss::tmrc()); + // Waiting safe delay here as we've seen issues in the lab where the required tMRD_l2 isn't sufficient + cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, BCW_SAFE_DELAY); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -464,17 +462,15 @@ fapi_try_exit: /// /// @brief Sets per buffer addressibility (PBA) mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_state mss::ON or mss::OFF /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets DA0 setting for buffer control word (F0BC1x) /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mss::states i_state, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // PBA position is really bit 0, but we're right justified on our bit ordering here, so it's bit7 constexpr uint64_t PBA_POSITION = 7; @@ -495,7 +491,7 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI FAPI_TRY(mss::eff_dimm_ddr4_f0bc1x(i_target, l_nominal_bc_value)); { - cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrd_l2()); l_data.iv_data.writeBit<PBA_POSITION>(i_state); FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index 7676df23b..be59fe5e0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -36,11 +36,15 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> #include <lib/dimm/rank.H> #include <lib/workarounds/ccs_workarounds.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -62,7 +66,7 @@ namespace ddr4 fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // JEDEC has a 3 step latching process for WR VREF // 1) enter into VREFDQ training mode, with the desired range value is XXXXXX @@ -111,7 +115,7 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2 const auto l_mcbist = find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Warning: l_dimm is not a valid Target and will crash Cronus if used before it gets filled in by mss::rank::get_dimm_target_from_rank fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm; - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; std::vector<uint64_t> l_ranks; // Gets the ranks on which to latch the VREF's @@ -173,7 +177,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Check to make sure our ctor worked ok mrs06_data l_mrs06( i_target, fapi2::current_err ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index 0cb2a285e..4874000b8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -38,10 +38,14 @@ #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -65,7 +69,7 @@ enum wr_vref_override : uint8_t fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Add latching commands for WR VREF to the instruction array @@ -121,7 +125,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // close namespace DDR4 } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 71deb5bbe..0f0229a71 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -91,7 +96,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +118,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Map from Write Recovery attribute value to bits in the MRS. @@ -202,7 +207,7 @@ fapi_try_exit: /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -248,7 +253,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_burst_length = 0; @@ -264,10 +269,10 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs00; -fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs00_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 834ee1ead..cc5896c5c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -86,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -108,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Little table to map Output Driver Imepdance Control. 34Ohm is index 0, @@ -188,7 +193,7 @@ fapi_try_exit: /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -226,7 +231,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_dll_enable = 0; @@ -243,10 +248,10 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs01; -fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs01_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index fe819814b..43f90a0ee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -81,7 +81,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -105,7 +105,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CWL_LENGTH = 3; @@ -170,7 +170,7 @@ fapi_try_exit: /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -199,7 +199,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_write_crc = 0; @@ -212,10 +212,10 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs02; -fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs02_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index 06b9eb88c..4c797864b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -106,7 +106,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -130,7 +130,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { //Some consts for the swizzle action @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -228,7 +228,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_mpr_mode = 0; @@ -246,10 +246,10 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs03; -fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs03_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index b28dae69e..736f338de 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -105,7 +105,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -127,7 +127,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CS_CMD_LATENCY_LENGTH = 3; @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -232,7 +232,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_max_pd_mode = 0; @@ -255,10 +255,10 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs04; -fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs04_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index a4c5be8c6..e9be70395 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -91,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CA_PARITY_LATENCY_LENGTH = 3; @@ -188,7 +188,7 @@ fapi_try_exit: /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -231,7 +231,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_ca_parity_latency_buffer; @@ -252,10 +252,10 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs05; -fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs05_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C index bfc1fc885..554271727 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -79,7 +79,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -101,7 +101,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { @@ -159,7 +159,7 @@ fapi_try_exit: /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -188,7 +188,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_tccd_l_buffer; @@ -202,10 +202,10 @@ fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs06; -fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs06_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index cec455f6a..3ac509b6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -62,7 +62,7 @@ template< > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { FAPI_TRY( mrs_engine(i_target, i_data, i_rank, i_data.iv_delay, io_inst) ); @@ -138,7 +138,7 @@ namespace ddr4 /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target)); @@ -146,28 +146,82 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const size_t DOUBLE_TMRD = 2 * mss::tmrd(); const size_t DOUBLE_TMOD = 2 * mss::tmod(i_target); - static const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - // JEDEC ordering of MRS per DDR4 power on sequence - { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, - { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, - { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, - { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, - { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, - { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, - // We need to wait tmod before zqcl, a non-mrs command - { 0, mrs00, mrs00_decode, DOUBLE_TMOD }, - }; - - std::vector< uint64_t > l_ranks; - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // Load MRS - for (const auto& d : MRS_DATA) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 power on sequence + { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, + { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, + { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, + { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, + { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, + { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, + // We need to wait tmod before zqcl, a non-mrs command + // Adding Per Glancy's request, to ensure DLL locking time + { 0, mrs00, mrs00_decode, DOUBLE_TMOD + tDLLK }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) + { + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst) +{ + FAPI_INF("ddr4::mrs_load_nvdimm %s", mss::c_str(i_target)); + + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - for (const auto& r : l_ranks) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 NVDIMM restore sequence + // Need to perform DLL off to on procedure (mrs01&mrs00) + // before all the other MRS's + { 1, mrs01, mrs01_decode, mss::tmrd() }, + { 0, mrs00, mrs00_decode, mss::tmod(i_target) + tDLLK }, + { 3, mrs03, mrs03_decode, mss::tmrd() }, + { 6, mrs06, mrs06_decode, mss::tmrd() }, + { 5, mrs05, mrs05_decode, mss::tmrd() }, + { 4, mrs04, mrs04_decode, mss::tmrd() }, + { 2, mrs02, mrs02_decode, mss::tmrd() }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) { - FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } } } @@ -234,7 +288,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_override(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -274,7 +328,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -302,7 +356,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_nom_value[MAX_RANK_PER_DIMM] = {0}; @@ -335,7 +389,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Get original RTT_WR value uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index bd8277daa..5e6aa5c35 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -41,6 +41,9 @@ #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/eff_config/timing.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -99,13 +102,11 @@ enum rtt_nom_settings /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction - implementation -/// @tparam T typename of the ccs::instruction_t /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note written this way so this is easier to test /// -template<fapi2::TargetType T> -void address_mirror_impl(ccs::instruction_t<T>& io_inst) +inline void address_mirror_impl(ccs::instruction_t& io_inst) { // Nothing fancy here, just mirror the bits we're told to mirror in Table 14 — Address Mirroring and Inversion mss::template swap<A3, A4>(io_inst.arr0); @@ -118,17 +119,15 @@ void address_mirror_impl(ccs::instruction_t<T>& io_inst) /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction -/// @tparam T typename of the ccs::instruction_t /// @param[in] i_target target to use to get mirroring attribute /// @param[in] i_rank the rank in question /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note assumes the input is from an even number rank /// -template<fapi2::TargetType T> -fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - ccs::instruction_t<T>& io_inst) +inline fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + ccs::instruction_t& io_inst) { // We only mirror if the mirroring attribute is set. uint8_t l_mirror = 0; @@ -147,19 +146,17 @@ fapi_try_exit: /// /// @brief Invert (side to side) the ADR bits of a CCS instruction -/// @tparam T the target type of the ccs instruction /// @param[in] i_target the DIMM target of the ccs command /// @param[in] i_inst const reference to a CCS instruction. /// @param[in] l_is_a17 Boolean for whether A17 bit is enabled or not /// @return ccs instruction with the ADR bits inverted (side-to-side) /// -template<fapi2::TargetType T> -ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const ccs::instruction_t<T>& i_inst, - const bool i_is_a17 = false) +inline ccs::instruction_t address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const ccs::instruction_t& i_inst, + const bool i_is_a17 = false) { // Copy the input as the output doesn't all change. - ccs::instruction_t<T> i_out(i_inst); + ccs::instruction_t i_out(i_inst); // Nothing fancy here, just negate the bits we're told to negate in Table 14 — Address Mirroring and Inversion mss::template negate<A3>(i_out.arr0); @@ -189,7 +186,6 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// /// @brief Helper function to make a CCS instruction for an MRS -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -197,11 +193,11 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - ccs::instruction_t<T>& io_inst ) + ccs::instruction_t& io_inst ) { FAPI_TRY( D::make_ccs_instruction(i_target, i_data, io_inst, i_rank), "Failed making a CCS instruction for templated MRS data. MR%d rank %d on %s", @@ -219,11 +215,10 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// template< > -inline fapi2::ReturnCode make_ccs_helper( - const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, - const uint64_t i_rank, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst ) +inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, + const uint64_t i_rank, + ccs::instruction_t& io_inst ) { FAPI_TRY( i_data.iv_func(i_target, io_inst, i_rank), "Failed making a CCS instruction for mrs_data<TARGET_TYPE_MCBIST> specialization. MR%d rank %d on %s", @@ -235,17 +230,16 @@ fapi_try_exit: /// /// @brief Helper function to decode MRS and trace CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_data the completed MRS data to send /// @param[in] i_rank the rank to send to /// @param[in] i_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode decode_helper(const D& i_data, const uint64_t i_rank, - const ccs::instruction_t<T>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( D::decode(i_inst, i_rank), @@ -278,7 +272,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<T>& i_target, template< > inline fapi2::ReturnCode decode_helper(const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( i_data.iv_dumper(i_inst, i_rank), @@ -292,7 +286,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -301,15 +294,15 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, const uint64_t i_delay_in_cycles, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst_a_side = ccs::mrs_command<T>(i_rank, i_data.iv_mrs); - ccs::instruction_t<T> l_inst_b_side; + ccs::instruction_t l_inst_a_side = ccs::mrs_command(i_rank, i_data.iv_mrs); + ccs::instruction_t l_inst_b_side; bool l_is_a17 = false; // Thou shalt send 2 MRS, one for the a-side and the other inverted for the b-side. @@ -355,7 +348,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -363,11 +355,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); namespace ddr4 { @@ -395,7 +387,7 @@ class mrs06_data; /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -406,7 +398,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -417,7 +409,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs03 @@ -427,7 +419,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs04 @@ -437,7 +429,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs05 @@ -447,7 +439,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs06 @@ -457,7 +449,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -478,7 +470,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -491,7 +483,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -504,7 +496,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -517,7 +509,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -530,7 +522,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -543,7 +535,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -556,7 +548,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -579,7 +571,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -595,7 +587,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -611,7 +603,7 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -628,7 +620,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -641,7 +633,7 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -655,7 +647,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -672,7 +664,7 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -690,7 +682,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -709,7 +701,7 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -730,7 +722,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -748,7 +740,7 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -767,7 +759,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -780,7 +772,7 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -794,7 +786,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -818,10 +810,10 @@ struct mrs00_data // dynaimc polymorphism and I avoid that where possible. static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -909,10 +901,10 @@ struct mrs01_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1011,10 +1003,10 @@ struct mrs02_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1091,10 +1083,10 @@ struct mrs03_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1196,10 +1188,10 @@ struct mrs04_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1322,10 +1314,10 @@ struct mrs05_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1436,10 +1428,10 @@ struct mrs06_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1516,7 +1508,16 @@ struct mrs06_data /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Sets WR LVL mode @@ -1720,18 +1721,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set WR LVL Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for WR LVL mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mss::states i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mss::states i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Spec states we need to use tmod for our delay, so we do const uint64_t l_delay = mss::tmod(i_target); @@ -1754,18 +1753,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1789,7 +1786,6 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rd_format MPR read format @@ -1797,12 +1793,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint8_t i_rd_format, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint8_t i_rd_format, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1830,18 +1825,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_NOM value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_NOM /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1864,18 +1857,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_WR value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_WR /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1898,23 +1889,21 @@ fapi_try_exit: /// /// @brief Makes CCS instruction for an MPR read -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode MPR location /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_mpr_loc, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_mpr_loc, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Right now we only have support for RD and RDA // Unclear if we want the API select the type of read command right now // Note the auto precharge is ignored with MPR mode on so we just do a read cmd - ccs::instruction_t<T> l_inst = ccs::rd_command<T> (i_rank, i_mpr_loc); + ccs::instruction_t l_inst = ccs::rd_command (i_rank, i_mpr_loc); // In MPR Mode: // Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between read commands @@ -1948,18 +1937,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set precharge all command -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst = ccs::precharge_all_command<T> (i_rank); + ccs::instruction_t l_inst = ccs::precharge_all_command (i_rank); // From the DDR4 Spec tRP is the precharge command period uint8_t l_delay = 0; @@ -1995,58 +1982,54 @@ fapi2::ReturnCode rtt_wr_to_rtt_nom_helper(const fapi2::Target<T>& i_target, /// /// @brief Executes CCS instructions to set RTT_WR value into RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_override(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to disable RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // ddr4 } // mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index 869e18f25..8c19b99f9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,23 +33,25 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <vector> +#include <lib/shared/mss_const.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/nvdimm_utils.H> #include <lib/mc/mc.H> -#include <lib/ccs/ccs.H> #include <lib/dimm/rank.H> #include <lib/mss_attribute_accessors.H> +#include <lib/mcbist/mcbist.H> +#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/poll.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <lib/mcbist/address.H> #include <lib/mcbist/memdiags.H> -#include <lib/mcbist/mcbist.H> #include <lib/mcbist/settings.H> -#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/pos.H> #include <lib/mc/port.H> #include <lib/phy/dp16.H> @@ -82,7 +84,7 @@ fapi2::ReturnCode get_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_TYPE mss::states& o_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -105,7 +107,7 @@ fapi2::ReturnCode change_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_T const mss::states i_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -213,10 +215,10 @@ fapi2::ReturnCode self_refresh_exit_helper( const fapi2::Target<fapi2::TARGET_TY mss::mcbist::address l_start = 0, l_end = 0; mss::mcbist::end_boundary l_end_boundary = mss::mcbist::end_boundary::STOP_AFTER_SLAVE_RANK; l_start.set_port(l_port); - mss::mcbist::stop_conditions l_stop_conditions; + mss::mcbist::stop_conditions<> l_stop_conditions; // Read with targeted scrub - FAPI_TRY ( mss::memdiags::targeted_scrub(l_mcbist, + FAPI_TRY ( mss::memdiags::targeted_scrub<mss::mc_type::NIMBUS>(l_mcbist, l_stop_conditions, l_start, l_end, @@ -264,10 +266,14 @@ template<> fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data; + const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Entry time to 0 for immediate entry constexpr uint64_t l_str_entry_time = 0; + // Stop mcbist (scrub) in case of MPIPL. It will get restarted in the later istep + FAPI_TRY(mss::mcbist::start_stop(l_mcbist, mss::states::STOP)); + // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0, // and disable minimum domain reduction (allow immediate entry of STR) FAPI_TRY(mss::mc::read_mbarpc0(i_target, l_mbarpc0_data)); @@ -322,49 +328,6 @@ fapi_try_exit: } /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) -{ - FAPI_INF("rc09_disable_powerdown %s", mss::c_str(i_target)); - - constexpr uint8_t POWER_DOWN_BIT = 4; - constexpr bool l_sim = false; - constexpr uint8_t FS0 = 0; // Function space 0 - constexpr uint64_t CKE_HIGH = mss::ON; - fapi2::buffer<uint8_t> l_rc09_cw = 0; - std::vector<uint64_t> l_ranks; - - FAPI_TRY(mss::eff_dimm_ddr4_rc09(i_target, l_rc09_cw)); - - // Clear power down enable bit. - l_rc09_cw.clearBit<POWER_DOWN_BIT>(); - - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // DES to ensure we exit powerdown properly - FAPI_DBG("deselect for %s", mss::c_str(i_target)); - io_inst.push_back( ccs::des_command<TARGET_TYPE_MCBIST>() ); - - static const cw_data l_rc09_4bit_data( FS0, 9, l_rc09_cw, mss::tmrd() ); - - // Load RC09 - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), - "Failed to load 4-bit RC09 control word for %s", - mss::c_str(i_target)); - - // Hold the CKE high - mss::ccs::workarounds::hold_cke_high(io_inst); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -373,11 +336,11 @@ fapi_try_exit: /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("rcd_load_nvdimm %s", mss::c_str(i_target)); - constexpr uint64_t CKE_LOW = mss::OFF; + constexpr uint64_t CKE_HIGH = mss::ON; constexpr bool l_sim = false; // Per DDR4RCD02, tSTAB is us. We want this in cycles for the CCS. @@ -425,17 +388,19 @@ fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_targ }; // Load 4-bit data - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_LOW), + // Keeping the CKE high as this will be done not in powerdown/STR mode. Not affected for + // the RCD supplier on nvdimm + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit control words for %s", mss::c_str(i_target)); // Load 8-bit data - FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 8-bit control words for %s", mss::c_str(i_target)); // Load RC09 with CKE_LOW - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit RC09 control word for %s", mss::c_str(i_target)); @@ -456,34 +421,13 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) std::vector<uint64_t> l_ranks; // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector l_program.iv_poll.iv_initial_delay = 0; l_program.iv_poll.iv_initial_sim_delay = 0; - // We expect to come in with the port in STR. Before proceeding with - // restoring the RCD, power down needs to be disabled first on the RCD so - // the rest of the CWs can be restored with CKE low - for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) - { - FAPI_DBG("rc09_disable_powerdown for %s", mss::c_str(d)); - FAPI_TRY( rc09_disable_powerdown(d, l_program.iv_instructions), - "Failed rc09_disable_powerdown() for %s", mss::c_str(d) ); - }// dimms - - // Exit STR first so CKE is back to high and rcd isn't ignoring us - FAPI_TRY( self_refresh_exit( i_target ) ); - - FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target), - "Failed to execute ccs for %s", mss::c_str(i_target) ); - - // Now, drive CKE back to low via STR entry instead of pde (we have data in the drams!) - FAPI_TRY( self_refresh_entry( i_target ) ); - - l_program = ccs::program<TARGET_TYPE_MCBIST>(); //Reset the program - // Now, fill the program with instructions to program the RCD for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) { @@ -513,7 +457,7 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); std::vector<uint64_t> l_ranks; uint8_t l_trp[MAX_DIMM_PER_PORT]; - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Get tRP FAPI_TRY(mss::eff_dram_trp(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_trp)); @@ -526,9 +470,9 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA for ( const auto r : l_ranks) { FAPI_DBG("precharge_all_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::precharge_all_command<TARGET_TYPE_MCBIST>(r, l_trp[0]) ); + l_program.iv_instructions.push_back( ccs::precharge_all_command(r, l_trp[0]) ); FAPI_DBG("zqcal_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::zqcl_command<TARGET_TYPE_MCBIST>(r, mss::tzqinit()) ); + l_program.iv_instructions.push_back( ccs::zqcl_command(r, mss::tzqinit()) ); } }// dimms @@ -608,12 +552,12 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP FAPI_TRY(get_refresh_overrun_mask(i_target, l_refresh_overrun_mask)); FAPI_TRY(change_refresh_overrun_mask(i_target, mss::states::ON)); - // Restore the rcd - FAPI_TRY( rcd_restore( i_target ) ); - // Exit STR FAPI_TRY( self_refresh_exit( i_target ) ); + // Restore the rcd + FAPI_TRY( rcd_restore( i_target ) ); + // Load the MRS FAPI_TRY( mss::mrs_load( i_target, NVDIMM_WORKAROUND ) ); @@ -635,6 +579,26 @@ fapi_try_exit: } /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state) +{ + const auto& l_mcs = mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target); + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(l_mcs, MCS_MCFGP, l_data) ); + l_data.writeBit<MCS_MCFGP_VALID>(i_state); + FAPI_INF("Changing MCS_MCFGP_VALID to %d on %s", i_state, mss::c_str(l_mcs)); + FAPI_TRY( mss::putScom(l_mcs, MCS_MCFGP, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful @@ -643,15 +607,15 @@ fapi_try_exit: /// fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); const auto& l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(i_target); constexpr uint64_t CS_N_ACTIVE = 0b00; uint8_t l_trp = 0; uint16_t l_trfc = 0; std::vector<uint64_t> l_ranks; - ccs::program<TARGET_TYPE_MCBIST> l_program; - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::program l_program; + ccs::instruction_t l_inst; // Get tRP and tRFC FAPI_TRY(mss::eff_dram_trp(i_target, l_trp)); @@ -662,14 +626,14 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Start the program with DES and wait for tRFC // All CKE = high, all CSn = high, Reset_n = high, wait tRFC - l_inst = ccs::des_command<TARGET_TYPE_MCBIST>(l_trfc); + l_inst = ccs::des_command(l_trfc); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); FAPI_INF("des_command() arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); // Precharge all command // All CKE = high, all CSn = low, Reset_n = high, wait tRP - l_inst = ccs::precharge_all_command<TARGET_TYPE_MCBIST>(0, l_trp); + l_inst = ccs::precharge_all_command(0, l_trp); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); @@ -678,7 +642,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Self-refresh entry command // All CKE = low, all CSn = low, Reset_n = high, wait tCKSRE - l_inst = ccs::self_refresh_entry_command<TARGET_TYPE_MCBIST>(0, mss::tcksre(l_dimms[0])); + l_inst = ccs::self_refresh_entry_command(0, mss::tcksre(l_dimms[0])); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(mss::CKE_LOW); @@ -688,7 +652,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Push in an empty instruction for RESETn // All CKE = low, all CSn = high (default), Reset_n = low - l_inst = ccs::instruction_t<TARGET_TYPE_MCBIST>(); + l_inst = ccs::instruction_t(); FAPI_INF("Assert RESETn arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H index a3c4914a4..8345cae05 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H @@ -34,11 +34,11 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/shared/mss_const.H> -#include <lib/ccs/ccs.H> #include <lib/phy/dp16.H> #include <lib/mc/port.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -182,15 +182,6 @@ template< fapi2::TargetType T > fapi2::ReturnCode self_refresh_exit( const fapi2::Target<T>& i_target ); /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -199,7 +190,7 @@ fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Restore the rcd after restoring the nvdimm data @@ -237,6 +228,14 @@ template< fapi2::TargetType T > fapi2::ReturnCode post_restore_transition( const fapi2::Target<T>& i_target ); /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state); + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C index c1cab4997..a864ea8d2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C @@ -35,10 +35,11 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <lib/phy/phy_cntrl.H> #include <lib/dimm/ddr4/pba.H> @@ -113,7 +114,7 @@ fapi_try_exit: /// fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -145,7 +146,7 @@ fapi_try_exit: /// fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -200,10 +201,10 @@ fapi2::ReturnCode execute_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM> // Issue PBA commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Inserts the DES command to ensure we keep our CKE high - l_program.iv_instructions.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + l_program.iv_instructions.push_back(mss::ccs::des_command()); // Makes a copy of the vector, so we can do the function space swaps correctly auto l_bcws = i_bcws; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H index 34706d492..c2d47fed3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,8 +39,9 @@ #include <fapi2.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <map> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C index a89cee0e2..8eb698a62 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,13 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> +#include <lib/mc/port.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> @@ -49,6 +52,7 @@ #include <lib/dimm/ddr4/pda.H> #include <lib/workarounds/ccs_workarounds.H> + namespace mss { @@ -209,7 +213,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -232,7 +236,7 @@ fapi_try_exit: fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -261,7 +265,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -284,7 +288,7 @@ fapi_try_exit: fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -344,7 +348,7 @@ fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_ // Issue MRS commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; FAPI_TRY(mss::ddr4::add_latch_wr_vref_commands( i_target, i_mrs, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H index 379b0a2ba..c28dcceac 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,14 +38,18 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/phy/write_cntrl.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> + #include <map> namespace mss @@ -170,7 +174,7 @@ fapi2::ReturnCode blast_dram_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA> /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Enters into and configures PDA mode @@ -190,7 +194,7 @@ fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Exits out of and disables PDA mode @@ -313,7 +317,7 @@ class commands // Check for a valid rank FAPI_ASSERT(mss::rank::is_rank_on_dimm(i_target, i_rank), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). + set_PORT_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). set_RANK(i_rank). set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND), "%s does not have rank %lu", mss::c_str(i_target), i_rank); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C index 6e53bddd8..e522f970f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,13 +36,17 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/zqcal.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/eff_config/timing.H> #include <lib/workarounds/ccs_workarounds.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_DIMM; @@ -61,15 +65,15 @@ namespace mss template<> fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::instruction_t l_inst; uint64_t tDLLK = 0; FAPI_TRY( mss::tdllk(i_target, tDLLK) ); // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS - l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_rank); + l_inst = ccs::zqcl_command(i_rank); // Doubling tZQ to better margin per lab request { @@ -98,7 +102,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // For LRDIMMs, program BCW to send ZQCal Long command to all data buffers // in broadcast mode @@ -128,7 +132,7 @@ template<> fapi2::ReturnCode setup_and_execute_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const fapi2::buffer<uint32_t>& i_cal_steps_enabled) { - mss::ccs::program<TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; for ( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) ) { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H index d78a512f1..d80febc3b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,11 @@ #include <vector> #include <fapi2.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -46,28 +50,26 @@ namespace mss /// /// @brief Setup DRAM ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in] i_rank the current rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup LRDIMM data buffer ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<T>& i_target, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup and execute DRAM ZQCL diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 38f6e9bae..2c3a3a757 100755..100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -44,13 +44,14 @@ #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/rank.H> #include <lib/utils/mss_nimbus_conversions.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/dimm/eff_dimm.H> #include <lib/dimm/mrs_load.H> #include <lib/shared/mss_kind.H> #include <lib/phy/dp16.H> #include <lib/mss_attribute_accessors_manual.H> #include <generic/memory/lib/utils/freq/gen_mss_freq.H> +#include <lib/workarounds/eff_config_workarounds.H> namespace mss { @@ -366,16 +367,6 @@ enum invalid_freq_function_encoding : uint8_t F0BC6X = 0x60, }; -/// -/// @brief encoding for MSS_INVALID_TIMING so we can look up functions based on encoding -/// -enum invalid_timing_function_encoding : uint8_t -{ - TRRD_S = 0, - TRRD_L = 1, - TFAW = 2, -}; - ///////////////////////// // Non-member function implementations ///////////////////////// @@ -1577,6 +1568,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc03() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x08; fapi2::buffer<uint8_t> l_buffer; uint8_t l_attrs_dimm_rc03[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; @@ -1599,6 +1591,10 @@ fapi2::ReturnCode eff_dimm::dimm_rc03() l_buffer.insertFromRight<CA_START, LEN>(l_ca_output_drive) .insertFromRight<CS_START, LEN>(l_cs_output_drive); } + + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc03(iv_mcs, &l_attrs_dimm_rc03[0][0]) ); @@ -1618,6 +1614,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc04() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x0a; uint8_t l_attrs_dimm_rc04[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; uint8_t l_odt_output_drive = 0; uint8_t l_cke_output_drive = 0; @@ -1641,6 +1638,9 @@ fapi2::ReturnCode eff_dimm::dimm_rc04() .insertFromRight<ODT_START, LEN>(l_odt_output_drive); } + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc04(iv_mcs, &l_attrs_dimm_rc04[0][0]) ); @@ -1660,6 +1660,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc05() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x0a; uint8_t l_attrs_dimm_rc05[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; uint8_t l_a_side_output_drive = 0; uint8_t l_b_side_output_drive = 0; @@ -1683,6 +1684,9 @@ fapi2::ReturnCode eff_dimm::dimm_rc05() .insertFromRight<A_START, LEN>(l_a_side_output_drive); } + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc05(iv_mcs, &l_attrs_dimm_rc05[0][0]) ); @@ -2960,36 +2964,44 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::vref_dq_train_value_and_range() { - constexpr uint8_t VREF_73PERCENT = 0x14; - constexpr uint8_t VREF_83PERCENT = 0x24; - constexpr uint8_t TRAIN_VALUE[NUM_VALID_RANKS_CONFIGS] = - { - VREF_73PERCENT, // 2 ranks per DIMM - VREF_83PERCENT, // 4 ranks per DIMM - }; - // Yes, range1 has a value of 0 this is taken from the JEDEC spec - constexpr uint8_t RANGE1 = 0x00; - constexpr uint8_t TRAIN_RANGE[NUM_VALID_RANKS_CONFIGS] = - { - RANGE1, - RANGE1, - }; - - + // Bits for range decode from the SPD + constexpr uint8_t RANK0 = 7; + constexpr uint8_t RANK1 = 6; + constexpr uint8_t RANK2 = 5; + constexpr uint8_t RANK3 = 4; uint8_t l_vref_dq_train_value[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; uint8_t l_vref_dq_train_range[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; + fapi2::buffer<uint8_t > l_range; // Gets the attributes FAPI_TRY( eff_vref_dq_train_value(iv_mcs, &l_vref_dq_train_value[0][0][0]) ); FAPI_TRY( eff_vref_dq_train_range(iv_mcs, &l_vref_dq_train_range[0][0][0]) ); - // Using hardcoded values for 2R settings from the IBM SI team - // It should be good enough to get us going - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) - { - l_vref_dq_train_value[iv_port_index][iv_dimm_index][mss::index(l_rank)] = TRAIN_VALUE[iv_master_ranks_index]; - l_vref_dq_train_range[iv_port_index][iv_dimm_index][mss::index(l_rank)] = TRAIN_RANGE[iv_master_ranks_index]; - } + // Value is easy, just drop the values in from the SPD + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank0(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK0])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank1(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK1])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank2(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK2])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank3(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK3])); + + // Range requires some decoding + FAPI_TRY( iv_spd_decoder.dram_vref_dq_range(l_range)); + + // Do the decode for each rank + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK0] = l_range.getBit<RANK0>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK1] = l_range.getBit<RANK1>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK2] = l_range.getBit<RANK2>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK3] = l_range.getBit<RANK3>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_VALUE, iv_mcs, l_vref_dq_train_value), "Failed setting attribute for ATTR_EFF_VREF_DQ_TRAIN_VALUE"); @@ -4090,7 +4102,7 @@ fapi2::ReturnCode eff_dimm::dram_trrd_s() l_trrd_s_in_nck); } - FAPI_TRY( trrd_s( iv_dimm, iv_dram_width, l_jedec_trrd) ); + FAPI_TRY( trrd_s( iv_dimm, iv_dram_width, iv_freq, l_jedec_trrd) ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_trrd != l_trrd_s_in_nck) @@ -4166,7 +4178,7 @@ fapi2::ReturnCode eff_dimm::dram_trrd_l() l_trrd_l_in_nck); } - FAPI_TRY( trrd_l( iv_dimm, iv_dram_width, l_jedec_trrd) ); + FAPI_TRY( trrd_l( iv_dimm, iv_dram_width, iv_freq, l_jedec_trrd) ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_trrd != l_trrd_l_in_nck) @@ -4265,7 +4277,7 @@ fapi2::ReturnCode eff_dimm::dram_tfaw() l_tfaw_in_nck); } - FAPI_TRY( mss::tfaw(iv_dimm, iv_dram_width, l_jedec_tfaw_in_nck), "Failed tfaw()" ); + FAPI_TRY( mss::tfaw(iv_dimm, iv_dram_width, iv_freq, l_jedec_tfaw_in_nck), "Failed tfaw()" ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_tfaw_in_nck != l_tfaw_in_nck) @@ -4334,11 +4346,15 @@ fapi2::ReturnCode eff_dimm::dram_tras() // which will give the best timing value for the dimm // (like 2400 MT/s) which may be different than the system // speed (if we were being limited by VPD or MRW restrictions) - const uint64_t l_tras_in_ps = mss::tras(iv_dimm); + uint64_t l_tras_in_ps; + uint64_t l_freq = 0; + uint8_t l_tras_in_nck = 0; // Calculate nck std::vector<uint8_t> l_attrs_dram_tras(PORTS_PER_MCS, 0); - uint8_t l_tras_in_nck = 0; + + FAPI_TRY( freq(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), l_freq) ); + l_tras_in_ps = mss::tras(iv_dimm, l_freq); // Cast needed for calculations to be done on the same integral type // as required by template deduction. We have iv_tCK_in_ps as a signed @@ -4471,20 +4487,22 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_nom() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b111, // 2R - 34Ohm - 0b111, // 4R - 34Ohm - }; + std::vector< uint64_t > l_ranks; + uint8_t l_decoder_val = 0; uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; FAPI_TRY( eff_dram_rtt_nom(iv_mcs, &l_mcs_attrs[0][0][0]) ); - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_nom(iv_freq, l_decoder_val)); + + // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value + // Same value for every rank for LRDIMMs + FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks)); + + for (const auto& l_rank : l_ranks) { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = DRAM_RTT_VALUES[iv_master_ranks_index]; + l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val; } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, iv_mcs, l_mcs_attrs) ); @@ -4553,25 +4571,22 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_wr() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b000, // 2R - disable - 0b001, // 4R - 120Ohm - }; + std::vector< uint64_t > l_ranks; + uint8_t l_decoder_val = 0; uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; FAPI_TRY( eff_dram_rtt_wr(iv_mcs, &l_mcs_attrs[0][0][0]) ); - // The host is in charge of ensuring good termination from the buffer to the DRAM - // That means that we need to know and set the settings - // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP - // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be - // Loops through all ranks - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_wr(iv_freq, l_decoder_val)); + + // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value + // Same value for every rank for LRDIMMs + FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks)); + + for (const auto& l_rank : l_ranks) { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][l_rank] = DRAM_RTT_VALUES[iv_master_ranks_index]; + l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val; } // Set the attribute @@ -4632,28 +4647,27 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_park() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b000, // 2R - disable - 0b010, // 4R - 120Ohm - }; - uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; + uint8_t l_decoder_val_01 = 0; + uint8_t l_decoder_val_23 = 0; FAPI_TRY( eff_dram_rtt_park(iv_mcs, &l_mcs_attrs[0][0][0]) ); - // The host is in charge of ensuring good termination from the buffer to the DRAM - // That means that we need to know and set the settings - // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP - // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be - // Loops through all ranks - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) - { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = DRAM_RTT_VALUES[iv_master_ranks_index]; - } + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks0_1(iv_freq, l_decoder_val_01), + "%s failed to decode RTT_PARK for ranks 0/1", mss::c_str(iv_mcs) ); + FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks2_3(iv_freq, l_decoder_val_23), + "%s failed to decode RTT_PARK for ranks 2/3", mss::c_str(iv_mcs) ); + // Setting the four rank values for this dimm + // Rank 0 and 1 have the same value, l_decoder_val_01 + // Rank 2 and 3 have the same value, l_decoder_val_23 + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK0] = l_decoder_val_01; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK1] = l_decoder_val_01; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK2] = l_decoder_val_23; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK3] = l_decoder_val_23; + + // Set the attribute FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, iv_mcs, l_mcs_attrs) ); fapi_try_exit: @@ -4956,13 +4970,18 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_bc04() { + uint8_t l_decoder_val = 0; // Retrieve MCS attribute data uint8_t l_attrs_dimm_bc04[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_ddr4_bc04(iv_mcs, &l_attrs_dimm_bc04[0][0]) ); - // Taken from SI spreadsheet and JEDEC - we want 60 Ohms, so 0x01 for a value - l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] = 0x01; + // So the encoding from the SPD is the same as the encoding for the buffer control encoding + // Simple grab and insert + // Value is checked in decoder function for validity + FAPI_TRY( iv_spd_decoder.data_buffer_mdq_rtt(iv_freq, l_decoder_val) ); + l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] = l_decoder_val; + // Update MCS attribute FAPI_INF("%s: BC04 settting (MDQ_RTT): %d", mss::c_str(iv_dimm), l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] ); FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC04, iv_mcs, l_attrs_dimm_bc04) ); @@ -4980,20 +4999,20 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_bc05() { - // Taken from the SI spreadsheet - we want 34 Ohms so 0x01 - fapi2::buffer<uint8_t> l_result(0x01); + uint8_t l_decoder_val = 0; // Retrieve MCS attribute data uint8_t l_attrs_dimm_bc05[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_ddr4_bc05(iv_mcs, &l_attrs_dimm_bc05[0][0]) ); - // Using a writeBit for clarity sake - // Enabling DQ/DQS drivers - l_result.writeBit<BC05_DRAM_DQ_DRIVER_DISABLE_POS>(BC05_DRAM_DQ_DRIVER_ENABLE); - l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_result; + // Same as BC04, grab from SPD and put into BC + FAPI_TRY( iv_spd_decoder.data_buffer_mdq_drive_strength(iv_freq, l_decoder_val) ); + l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_decoder_val; - FAPI_INF("%s: BC05 settting (MDQ Drive Strength): 0x%02x", mss::c_str(iv_dimm), + FAPI_INF("%s: BC05 settting (MDQ Drive Strength): %d", mss::c_str(iv_dimm), l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] ); + + // Updates the attribute FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC05, iv_mcs, l_attrs_dimm_bc05) ); fapi_try_exit: @@ -5514,20 +5533,17 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_f5bc6x() { - constexpr uint8_t VREF_73PERCENT = 0x14; - constexpr uint8_t VREF_83PERCENT = 0x24; - constexpr uint8_t RD_VREF[NUM_VALID_RANKS_CONFIGS] = - { - VREF_73PERCENT, // 2 ranks per DIMM - VREF_83PERCENT, // 4 ranks per DIMM - }; + uint8_t l_decode = 0; uint8_t l_attrs_dimm_f5bc6x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_f5bc6x(iv_mcs, &l_attrs_dimm_f5bc6x[0][0]) ); + // Gets the SPD value + FAPI_TRY( iv_spd_decoder.data_buffer_vref_dq(l_decode)); + // F5BC6x is just the VREF training range - l_attrs_dimm_f5bc6x[iv_port_index][iv_dimm_index] = RD_VREF[iv_master_ranks_index]; + l_attrs_dimm_f5bc6x[iv_port_index][iv_dimm_index] = l_decode; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, iv_mcs, l_attrs_dimm_f5bc6x), "Failed setting attribute for ATTR_EFF_DIMM_DDR4_F5BC6x"); @@ -5678,7 +5694,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::MT). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD MT keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5702,7 +5718,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::MR). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD MR keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5723,7 +5739,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::CK). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD CK keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5742,7 +5758,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::DQ). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD DQ keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5989,10 +6005,13 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::odt_wr() { + // Values were obtained experimentally + // For 2R, opposite termination is ideal + // For 4R, terminating everything is ideal constexpr uint8_t DRAM_ODT_VALUES[NUM_VALID_RANKS_CONFIGS][MAX_RANK_PER_DIMM] = { { 0x44, 0x88, 0x00, 0x00, }, // 2 ranks per DIMM - { 0x44, 0x88, 0x44, 0x88, }, // 4 ranks per DIMM + { 0xcc, 0xcc, 0xcc, 0xcc, }, // 4 ranks per DIMM }; // Masks on the ODT for a specific DIMM diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H index f60adaf7c..477b7114c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H @@ -38,7 +38,7 @@ #include <generic/memory/lib/spd/common/rcw_settings.H> #include <lib/spd/spd_factory.H> #include <lib/eff_config/timing.H> -#include <generic/memory/lib/data_engine/pre_data_init.H> +#include <lib/eff_config/pre_data_init.H> #include <generic/memory/lib/spd/spd_utils.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H deleted file mode 100644 index ee707c821..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H +++ /dev/null @@ -1,263 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file dimm.H -/// @brief Encapsulation for dimms of all types -/// -// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _MSS_DIMM_H_ -#define _MSS_DIMM_H_ - -#include <fapi2.H> - -#include <lib/mss_attribute_accessors.H> -#include <generic/memory/lib/utils/c_str.H> - -namespace mss -{ - -namespace dimm -{ - -/// -/// @class mss::dimm::kind -/// @brief A class containing information about a dimm like ranks, density, configuration - what kind of dimm is it? -/// -class kind -{ - public: - - /// - /// @brief Generate a vector of DIMM kind from a vector of DIMM - /// @param[in] i_dimm a vector of DIMM - /// @return std::vector of dimm::kind relating to the DIMM passed in - /// - static std::vector<kind> vector(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimm) - { - std::vector<kind> l_kinds; - - for (const auto& d : i_dimm) - { - l_kinds.push_back( kind(d) ); - } - - return l_kinds; - } - - /// - /// @brief operator=() - assign kinds (needed to sort vectors of kinds) - /// @param[in] i_rhs the right hand side of the assignment statement - /// @return reference to this - /// - inline kind& operator=(const kind& i_rhs) - { - iv_target = i_rhs.iv_target; - iv_master_ranks = i_rhs.iv_master_ranks; - iv_total_ranks = i_rhs.iv_total_ranks; - iv_dram_density = i_rhs.iv_dram_density; - iv_dram_width = i_rhs.iv_dram_width; - iv_dram_generation = i_rhs.iv_dram_generation; - iv_dimm_type = i_rhs.iv_dimm_type; - iv_rows = i_rhs.iv_rows; - iv_size = i_rhs.iv_size; - iv_mfgid = i_rhs.iv_mfgid; - iv_stack_type = i_rhs.iv_stack_type; - iv_hybrid = i_rhs.iv_hybrid; - iv_hybrid_memory_type = i_rhs.iv_hybrid_memory_type; - iv_rcd_mfgid = i_rhs.iv_rcd_mfgid; - return *this; - } - - /// - /// @brief operator==() - are two kinds the same? - /// @param[in] i_rhs the right hand side of the comparison statement - /// @return bool true iff the two kind are of the same kind - /// @warning this does not compare the targets (iv_target,) just the values - /// Also does not compare the mfgid as that's not really part of the DIMM kind but is additional information - /// - inline bool operator==(const kind& i_rhs) const - { - return ((iv_master_ranks == i_rhs.iv_master_ranks) && - (iv_total_ranks == i_rhs.iv_total_ranks) && - (iv_dram_density == i_rhs.iv_dram_density) && - (iv_dram_width == i_rhs.iv_dram_width) && - (iv_dram_generation == i_rhs.iv_dram_generation) && - (iv_dimm_type == i_rhs.iv_dimm_type) && - (iv_rows == i_rhs.iv_rows) && - (iv_size == i_rhs.iv_size) && - (iv_stack_type == i_rhs.iv_stack_type) && - (iv_hybrid == i_rhs.iv_hybrid) && - (iv_hybrid_memory_type == i_rhs.iv_hybrid_memory_type) && - (iv_rcd_mfgid == i_rhs.iv_rcd_mfgid)); - } - - /// - /// @brief operator!=() - are two kinds different? - /// @param[in] i_rhs the right hand side of the comparison statement - /// @return bool true iff the two kind are of different - /// @warning this does not compare the targets (iv_target,) just the values - /// - inline bool operator!=(const kind& i_rhs) const - { - return !(this->operator==(i_rhs)); - } - - /// - /// @brief Construct a dimm::kind data structure - information about the kind of DIMM this is - /// @param[in] i_target a DIMM target - /// - kind(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target): - iv_target(i_target) - { - FAPI_TRY( mss::eff_dram_gen(i_target, iv_dram_generation) ); - FAPI_TRY( mss::eff_dimm_type(i_target, iv_dimm_type) ); - FAPI_TRY( mss::eff_dram_density(i_target, iv_dram_density) ); - FAPI_TRY( mss::eff_dram_width(i_target, iv_dram_width) ); - FAPI_TRY( mss::eff_num_master_ranks_per_dimm(i_target, iv_master_ranks) ); - FAPI_TRY( mss::eff_num_ranks_per_dimm(i_target, iv_total_ranks) ); - FAPI_TRY( mss::eff_dram_row_bits(i_target, iv_rows) ); - FAPI_TRY( mss::eff_dimm_size(i_target, iv_size) ); - FAPI_TRY( mss::eff_dram_mfg_id(i_target, iv_mfgid) ); - FAPI_TRY( mss::eff_prim_stack_type( i_target, iv_stack_type) ); - FAPI_TRY( mss::eff_hybrid( i_target, iv_hybrid )); - FAPI_TRY( mss::eff_hybrid_memory_type( i_target, iv_hybrid_memory_type )); - FAPI_TRY( mss::eff_rcd_mfg_id(i_target, iv_rcd_mfgid) ); - return; - - fapi_try_exit: - // Not 100% sure what to do here ... - FAPI_ERR("error initializing DIMM structure: %s 0x%016lx", mss::c_str(i_target), uint64_t(fapi2::current_err)); - fapi2::Assert(false); - } - - /// - /// @brief Construct a DIMM kind used to identify this DIMM for tables. - /// @param[in] i_master_ranks number of master ranks on the DIMM - /// @param[in] i_total_ranks total number of ranks on the DIMM - /// @param[in] i_dram_density density of the DRAM - /// @param[in] i_dram_width width of the DRAM - /// @param[in] i_dram_generation DRAM generation - /// @param[in] i_dimm_type DIMM type (e.g. RDIMM) - /// @param[in] i_rows number of rows in the DRAM - /// @param[in] i_size the overal size of the DIMM in GB - /// @param[in] i_mfgid the dram manufacturer id of the dimm, defaulted to 0 - /// @param[in] i_stack_type dram die type, single die package or 3DS - /// @param[in] i_hybrid, default not hybrid - /// @param[in] i_hybrid_memory_type, defult none - /// @param[in] i_rcd_mfgid dimm register and data buffer manufacturer id, default 0 - /// @note can't be constexpr as fapi2::Target doesn't have a constexpr ctor. - /// - kind( const uint8_t i_master_ranks, - const uint8_t i_total_ranks, - const uint8_t i_dram_density, - const uint8_t i_dram_width, - const uint8_t i_dram_generation, - const uint8_t i_dimm_type, - const uint8_t i_rows, - const uint32_t i_size, - const uint16_t i_mfgid = 0, - const uint8_t i_stack_type = fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_SDP, - const uint8_t i_hybrid = fapi2::ENUM_ATTR_EFF_HYBRID_NOT_HYBRID, - const uint8_t i_hybrid_memory_type = fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NONE, - const uint16_t i_rcd_mfgid = 0): - iv_target(0), - iv_master_ranks(i_master_ranks), - iv_total_ranks(i_total_ranks), - iv_dram_density(i_dram_density), - iv_dram_width(i_dram_width), - iv_dram_generation(i_dram_generation), - iv_dimm_type(i_dimm_type), - iv_rows(i_rows), - // TK consider calculating size rather than requiring it be set. - iv_size(i_size), - iv_mfgid(i_mfgid), - iv_stack_type(i_stack_type), - iv_hybrid(i_hybrid), - iv_hybrid_memory_type(i_hybrid_memory_type), - iv_rcd_mfgid(i_rcd_mfgid) - { - // Bit of an idiot-check to be sure a hand-crafted dimm::kind make sense wrt slaves, masters, packages, etc. - // Both of these are checked in eff_config. If they are messed up, they should be caught there - if (iv_master_ranks > iv_total_ranks) - { - FAPI_ERR("Not enough total ranks? master: %d total: %d", - iv_master_ranks, - iv_total_ranks); - fapi2::Assert(false); - } - - if ((iv_total_ranks % iv_master_ranks) != 0) - { - FAPI_ERR("total or master ranks seems incorrect. master: %d total: %d", - iv_master_ranks, - iv_total_ranks); - fapi2::Assert(false); - } - } - - fapi2::Target<fapi2::TARGET_TYPE_DIMM> iv_target; - uint8_t iv_master_ranks; - uint8_t iv_total_ranks; - uint8_t iv_dram_density; - uint8_t iv_dram_width; - uint8_t iv_dram_generation; - uint8_t iv_dimm_type; - uint8_t iv_rows; - uint32_t iv_size; - uint16_t iv_mfgid; - uint8_t iv_stack_type; - uint8_t iv_hybrid; - uint8_t iv_hybrid_memory_type; - uint16_t iv_rcd_mfgid; - - /// - /// @brief equal_config - /// @param[in] i_input_compare the i_kind to compare against - /// @return bool true iff the two kind are of the same kind for xlate purposes - /// @warning this does not compare the targets (iv_target,), mfgid, prim_stack_type nor hybrid type - /// - inline bool equal_config(const kind& i_input_compare) const - { - return ((iv_master_ranks == i_input_compare.iv_master_ranks) && - (iv_total_ranks == i_input_compare.iv_total_ranks) && - (iv_dram_density == i_input_compare.iv_dram_density) && - (iv_dram_width == i_input_compare.iv_dram_width) && - (iv_dram_generation == i_input_compare.iv_dram_generation) && - (iv_dimm_type == i_input_compare.iv_dimm_type) && - (iv_rows == i_input_compare.iv_rows) && - (iv_size == i_input_compare.iv_size)); - } -}; - -} - -} -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C index aae4cce28..8928a6f98 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C @@ -62,7 +62,7 @@ fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector @@ -72,7 +72,17 @@ fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA for ( const auto& d : find_targets<TARGET_TYPE_DIMM>(i_target) ) { FAPI_DBG("mrs load for %s", mss::c_str(d)); - FAPI_TRY( perform_mrs_load(d, l_program.iv_instructions) ); + + // TK - break out the nvdimm stuff into function + if (i_nvdimm_workaround) + { + FAPI_DBG("nvdimm workaround detected. loading mrs for restore sequence"); + FAPI_TRY( ddr4::mrs_load_nvdimm(d, l_program.iv_instructions) ); + } + else + { + FAPI_TRY( perform_mrs_load(d, l_program.iv_instructions) ); + } } // We have to configure the CCS engine to let it know which port these instructions are @@ -121,7 +131,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -151,7 +161,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform mrs_load for %s [expecting rdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( ddr4::mrs_load(i_target, io_inst) ); @@ -168,7 +178,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform mrs_load for %s [expecting lrdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( ddr4::mrs_load(i_target, io_inst) ); @@ -186,7 +196,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H index f19679bc7..f18050f12 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H @@ -38,10 +38,13 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -90,15 +93,15 @@ struct mrs_data // The attribute getter. For MRS we pass in the ARR0 of the CCS instruction // as that allows us to encapsulate the attribute processing and the bit // manipulation in one function. - fapi2::ReturnCode (*iv_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t<T>&, const uint64_t); - fapi2::ReturnCode (*iv_dumper)(const ccs::instruction_t<T>&, const uint64_t); + fapi2::ReturnCode (*iv_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t&, const uint64_t); + fapi2::ReturnCode (*iv_dumper)(const ccs::instruction_t&, const uint64_t); // The delay needed after this MRS word is written uint64_t iv_delay; mrs_data( const uint64_t i_mrs, - fapi2::ReturnCode (*i_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t<T>&, const uint64_t), - fapi2::ReturnCode (*i_dumper)(const ccs::instruction_t<T>&, const uint64_t), + fapi2::ReturnCode (*i_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t&, const uint64_t), + fapi2::ReturnCode (*i_dumper)(const ccs::instruction_t&, const uint64_t), const uint64_t i_delay ): iv_mrs(i_mrs), iv_func(i_func), @@ -174,7 +177,7 @@ struct perform_mrs_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_mrs_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads @@ -186,7 +189,7 @@ perform_mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// template<> fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads /// @param[in] i_target the dimm target for the mrs's @@ -197,7 +200,7 @@ fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::T /// template<> fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads /// @param[in] i_kind the i_target's dimm_kind struct @@ -208,7 +211,7 @@ fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_mrs_load_overload<K>::available > inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -232,7 +235,7 @@ inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_mrs_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { return perform_mrs_load<DEFAULT_KIND>(i_target, io_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C deleted file mode 100644 index fa45be920..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H new file mode 100644 index 000000000..6c8d16bc0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file nimbus_kind.H +/// @brief Encapsulation for dimms of all types +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_NIMBUS_KIND_H_ +#define _MSS_NIMBUS_KIND_H_ + +#include <fapi2.H> + +#include <lib/shared/mss_const.H> +#include <lib/mss_attribute_accessors.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/dimm/kind.H> + +namespace mss +{ + +namespace dimm +{ + +/// +/// @class mss::dimm::kind specilization for NIMBUS +/// @brief A class containing information about a dimm like ranks, density, configuration - what kind of dimm is it? +/// +template<> +inline kind<mss::mc_type::NIMBUS>::kind(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) : + iv_target(i_target), + iv_module_height(0) +{ + FAPI_TRY( mss::eff_dram_gen(i_target, iv_dram_generation) ); + FAPI_TRY( mss::eff_dimm_type(i_target, iv_dimm_type) ); + FAPI_TRY( mss::eff_dram_density(i_target, iv_dram_density) ); + FAPI_TRY( mss::eff_dram_width(i_target, iv_dram_width) ); + FAPI_TRY( mss::eff_num_master_ranks_per_dimm(i_target, iv_master_ranks) ); + FAPI_TRY( mss::eff_num_ranks_per_dimm(i_target, iv_total_ranks) ); + FAPI_TRY( mss::eff_dram_row_bits(i_target, iv_rows) ); + FAPI_TRY( mss::eff_dimm_size(i_target, iv_size) ); + FAPI_TRY( mss::eff_dram_mfg_id(i_target, iv_mfgid) ); + FAPI_TRY( mss::eff_prim_stack_type( i_target, iv_stack_type) ); + FAPI_TRY( mss::eff_hybrid( i_target, iv_hybrid )); + FAPI_TRY( mss::eff_hybrid_memory_type( i_target, iv_hybrid_memory_type )); + FAPI_TRY( mss::eff_rcd_mfg_id(i_target, iv_rcd_mfgid) ); + return; + +fapi_try_exit: + // Not 100% sure what to do here ... + FAPI_ERR("error initializing DIMM structure: %s 0x%016lx", mss::c_str(i_target), uint64_t(fapi2::current_err)); + fapi2::Assert(false); +} + + +} //ns dimm +} //ns mss +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C index 37af40a5b..1026634b1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -902,6 +902,25 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Return a vector of rank numbers which represent the ranks for this dimm +/// @param[in] i_dimm_target TARGET_TYPE_DIMM +/// @param[out] o_ranks a vector of ranks for dimm (numbers) +/// @return FAPI2_RC_SUCCESS iff all is ok +/// +template<> +fapi2::ReturnCode ranks_on_dimm_helper<mss::mc_type::NIMBUS>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_dimm_target, + std::vector<uint64_t>& o_ranks) +{ + std::vector<uint64_t> l_ranks; + FAPI_TRY( mss::rank::ranks(i_dimm_target, l_ranks) ); + o_ranks = l_ranks; + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace rank } // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H index 901ed1a8c..130697bbb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H @@ -41,7 +41,7 @@ #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> #include <generic/memory/lib/utils/scom.H> -#include <lib/utils/num.H> +#include <generic/memory/lib/utils/num.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/shared/mss_const.H> #include <lib/phy/phy_cntrl.H> @@ -1033,7 +1033,7 @@ inline fapi2::ReturnCode set_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_RANK_FIELD), "%s Invalid rank (%d) in set_rank_field", mss::c_str(i_target), @@ -1101,7 +1101,7 @@ inline fapi2::ReturnCode get_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANK_FIELD), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1171,7 +1171,7 @@ inline fapi2::ReturnCode set_pair_valid( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_PAIR_VALID), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1243,7 +1243,7 @@ inline fapi2::ReturnCode get_pair_valid( const fapi2::Target<T> i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_PAIR_VALID), "%s Invalid rank (%d) passed into get get_pair_valid", mss::c_str(i_target), @@ -1350,7 +1350,7 @@ fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target, FAPI_ASSERT( l_ordinal < MAX_RANK_PER_DIMM, fapi2::MSS_INVALID_RANK() .set_RANK(l_ordinal) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANKS_IN_PAIR), "%s Invalid rank (%d) in set_ranks_in_pair", mss::c_str(i_target), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C index c999666cd..17bba3a88 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #include <mss.H> #include <lib/dimm/rcd_load.H> #include <lib/dimm/rcd_load_ddr4.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -60,7 +60,7 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; uint8_t l_sim = 0; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the @@ -76,7 +76,7 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA // So we use the power down entry command to achieve this if(!l_sim) { - l_program.iv_instructions.push_back( ccs::pde_command<TARGET_TYPE_MCBIST>() ); + l_program.iv_instructions.push_back( ccs::pde_command() ); } FAPI_DBG("rcd load for %s", mss::c_str(d)); @@ -119,7 +119,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -149,7 +149,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_sim = 0; FAPI_TRY( mss::is_simulation(l_sim) ); @@ -170,7 +170,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_sim = 0; FAPI_TRY( mss::is_simulation(l_sim) ); @@ -191,7 +191,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -206,4 +206,32 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Helper function to bring CKE high and hold for 400 cycles +/// @param[in] i_target MCA target on which to operate +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode draminit_cke_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + + auto l_des = mss::ccs::des_command(); + mss::ccs::program l_program; + + // Also a Deselect command must be registered as required from the Spec. + // Register DES instruction, which pulls CKE high. Idle 400 cycles, and then begin RCD loading + // Note: This only is sent to one of the MCA as we still have the mux_addr_sel bit set, meaning + // we'll PDE/DES all DIMM at the same time. + l_des.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(400); + l_program.iv_instructions.push_back(l_des); + + FAPI_TRY( mss::ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), + l_program, + i_target), + "%s Failed execute in p9_mss_draminit", + mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H index b9ee410d6..bfb73ae92 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,9 +39,11 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> - #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -112,7 +114,7 @@ struct perform_rcd_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_rcd_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_rcd_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); // // We know we registered overloads for perform_rcd_load, so we need the entry point to @@ -121,11 +123,11 @@ perform_rcd_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, // template<> fapi2::ReturnCode perform_rcd_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); template<> fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); /// /// @brief Start the rcd_load_dispatch boilerplate -- specialization for recursion dispatcher @@ -137,7 +139,7 @@ fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_rcd_load_overload<K>::available > inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -162,10 +164,17 @@ inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_rcd_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { return perform_rcd_load<DEFAULT_KIND>(i_target, i_inst); } +/// +/// @brief Helper function to bring CKE high and hold for 400 cycles +/// @param[in] i_target MCA target on which to operate +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode draminit_cke_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); + } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C index 690b7e180..d9cc10e5b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -60,7 +60,7 @@ namespace mss /// fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("rcd_load_ddr4 %s", mss::c_str(i_target)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H index bb70c20b6..0c6f8162c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,6 +53,6 @@ namespace mss /// fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } #endif |
