diff options
Diffstat (limited to 'src/import/chips')
472 files changed, 46467 insertions, 31957 deletions
diff --git a/src/import/chips/centaur/procedures/hwp/memory/lib/shared/dimmConsts.H b/src/import/chips/centaur/procedures/hwp/memory/lib/shared/dimmConsts.H index 03f1b2a51..ac18feba6 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/lib/shared/dimmConsts.H +++ b/src/import/chips/centaur/procedures/hwp/memory/lib/shared/dimmConsts.H @@ -40,6 +40,7 @@ enum consts : size_t { MAX_PORTS_PER_MBA = 2, ///< Maximum number of ports on an MBA MAX_DIMM_PER_PORT = 2, ///< Maximum number of DIMMs attached to an MBA PORT + MAX_DIMM_PER_MBA = MAX_DIMM_PER_PORT * MAX_PORTS_PER_MBA, ///< Maximum number of DIMMs attached to an MBA MAX_MBA_PER_CEN = 2, ///< Maximum number of MBAs on a membuf MAX_PORTS_PER_CEN = 4, ///< Maximum number of ports on a centaur MAX_RANKS_PER_DIMM = 4, ///< Maximum number of ranks on a DIMM diff --git a/src/import/chips/centaur/procedures/hwp/memory/lib/utils/cumulus_find.H b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/cumulus_find.H new file mode 100644 index 000000000..8adf99b3f --- /dev/null +++ b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/cumulus_find.H @@ -0,0 +1,126 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/centaur/procedures/hwp/memory/lib/utils/cumulus_find.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file cumulus_find.H +/// @brief Templates for finding things +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_CUMULUS_FIND_H +#define _MSS_CUMULUS_FIND_H + +#include <fapi2.H> +#include <vector> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ + +/// +/// @brief find the DMI given an MBA +/// @param[in] i_target the fapi2 target MBA +/// @return a DMI target. +/// +template<> +inline fapi2::Target<fapi2::TARGET_TYPE_DMI> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) +{ + return i_target.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>().getParent<fapi2::TARGET_TYPE_DMI>(); +} + +/// +/// @brief find the PROC given a MEMBUF +/// @param[in] i_target the fapi2 target MEMBUF +/// @return a PROC target. +/// +template<> +inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& + i_target) +{ + return i_target.getParent<fapi2::TARGET_TYPE_DMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); +} + +/// +/// @brief find the PROC_CHIP given a MBA +/// @param[in] i_target the fapi2 target MBA +/// @return a DMI target. +/// +template<> +inline fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> find_target(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) +{ + return i_target.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>() + .getParent<fapi2::TARGET_TYPE_DMI>() + .getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); +} + +/// +/// @brief find all the MBA connected to an DMI +/// @param[in] i_target a fapi2::Target DMI +/// @return a vector of fapi2::TARGET_TYPE_MBA +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MBA> > +find_targets( const fapi2::Target<fapi2::TARGET_TYPE_DMI>& i_target, + fapi2::TargetState i_state ) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_MBA> > l_mbas; + + for (const auto& membuf_chip : i_target.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>(i_state)) + { + auto l_these_mbas( membuf_chip.getChildren<fapi2::TARGET_TYPE_MBA>(i_state) ); + l_mbas.insert(l_mbas.end(), l_these_mbas.begin(), l_these_mbas.end()); + } + + return l_mbas; +} + +/// +/// @brief find all the DIMM connected to a centaur +/// @param[in] i_target a fapi2::Target TARGET_TYPE_MEMBUF_CHIP +/// @return a vector of fapi2::TARGET_TYPE_DIMM +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > +find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target, + fapi2::TargetState i_state ) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > l_dimms; + + for (const auto& l_mba : i_target.getChildren<fapi2::TARGET_TYPE_MBA>(i_state)) + { + auto l_these_dimms( l_mba.getChildren<fapi2::TARGET_TYPE_DIMM>(i_state) ); + l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); + } + + return l_dimms; +} + +}// mss + +#endif diff --git a/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C index 465e31779..507618ea1 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C +++ b/src/import/chips/centaur/procedures/hwp/memory/lib/utils/mem_size.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -28,7 +28,7 @@ #include <lib/shared/dimmConsts.H> #include <p9c_mss_funcs.H> #include <generic/memory/lib/utils/memory_size.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <generic/memory/lib/utils/c_str.H> /// diff --git a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C index f8324bb84..7c05e9608 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C +++ b/src/import/chips/centaur/procedures/hwp/memory/mss_dynamic_vid_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,7 @@ /// *HWP Consumed by: HB #include <mss_dynamic_vid_utils.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <generic/memory/lib/utils/c_str.H> /// diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_cen_plug_rules.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_cen_plug_rules.H new file mode 100644 index 000000000..c7c22f158 --- /dev/null +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_cen_plug_rules.H @@ -0,0 +1,396 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/centaur/procedures/hwp/memory/p9c_cen_plug_rules.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file p9c_cen_plug_ruiles.H +/// @brief Takes in spd and configures effective attrs +/// +/// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +/// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 2 +/// *HWP Consumed by: HB + +#ifndef P9C_CEN_PLUG_RULES_H_ +#define P9C_CEN_PLUG_RULES_H_ + +//------------------------------------------------------------------------------ +// My Includes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +#include <dimmConsts.H> +#include <generic/memory/lib/utils/c_str.H> + +namespace mss +{ +namespace cen +{ + +/// +/// @Brief Enumeration for the attributes to check +/// +enum attr +{ + ROWS = 0, + COLS = 1, + DENSITY = 2, + WIDTH = 3, + MASTER_RANKS = 4, + NUM_RANKS = 5, + + // Dispatcher parameters + START = ROWS, + END = NUM_RANKS + 1, +}; + +/// +/// @brief Traits class for each attribute +/// @tparam attribute traits +/// +template<attr A> +class attr_traits +{}; + +/// +/// @brief Traits class for each attribute - ROWS specialization +/// +template<> +class attr_traits<attr::ROWS> +{ + public: + static constexpr bool IS_DIMM_TYPE = false; + static constexpr const char* STR = "ROWS"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, uint8_t& o_data) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_ROWS, i_target, o_data); + } +}; + +/// +/// @brief Traits class for each attribute - COLS specialization +/// +template<> +class attr_traits<attr::COLS> +{ + public: + static constexpr bool IS_DIMM_TYPE = false; + static constexpr const char* STR = "COLS"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, uint8_t& o_data) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_COLS, i_target, o_data); + } +}; + +/// +/// @brief Traits class for each attribute - DENSITY specialization +/// +template<> +class attr_traits<attr::DENSITY> +{ + public: + static constexpr bool IS_DIMM_TYPE = false; + static constexpr const char* STR = "DENSITY"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, uint8_t& o_data) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_DENSITY, i_target, o_data); + } +}; + +/// +/// @brief Traits class for each attribute - WIDTH specialization +/// +template<> +class attr_traits<attr::WIDTH> +{ + public: + static constexpr bool IS_DIMM_TYPE = false; + static constexpr const char* STR = "WIDTH"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, uint8_t& o_data) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_WIDTH, i_target, o_data); + } +}; + +/// +/// @brief Traits class for each attribute - MASTER_RANKS specialization +/// +template<> +class attr_traits<attr::MASTER_RANKS> +{ + public: + static constexpr bool IS_DIMM_TYPE = true; + static constexpr const char* STR = "MASTER_RANKS"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, + uint8_t (&o_data)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT]) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, o_data); + } +}; + + +/// +/// @brief Traits class for each attribute - NUM_RANKS specialization +/// +template<> +class attr_traits<attr::NUM_RANKS> +{ + public: + static constexpr bool IS_DIMM_TYPE = true; + static constexpr const char* STR = "NUM_RANKS"; + + /// + /// @brief attribute getter helper + /// @param[in] i_target MBA target + /// @param[out] o_data data from the attr + /// @return fapi2::ReturnCode + /// + static fapi2::ReturnCode getter(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target, + uint8_t (&o_data)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT]) + { + return FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_NUM_RANKS_PER_DIMM, i_target, o_data); + } +}; + +/// +/// @brief Checks if a configuration is balanced for all attr +/// @param[in] i_data the attribute data for a centaur +/// @return true if the configuration is balanced +/// +inline bool is_data_equivalent(const std::vector<uint8_t>& i_data) +{ + // Default to a balanced config - if we don't have any MBA's on this centaur, that's balanced + bool l_balanced = true; + + // Make sure we have real data + if(!i_data.empty()) + { + // Find if the data is all the same + const auto l_start = i_data[0]; + const auto l_it = std::find_if(i_data.begin(), i_data.end(), [&l_start]( const uint8_t& i_rhs) -> bool + { + return l_start != i_rhs; + }); + + // Data is balanced if all of data is equal (didn't find an unequal piece of data) + l_balanced = l_it == i_data.end(); + } + + return l_balanced; +} + +/// +/// @brief Assembles the attribute into a vector for processing +/// @tparam attr A attribute on which to operate +/// @tparam attr_traits TT traits for the associated attribute +/// @param[in] i_target centaur target on which to operate +/// @param[in] std::false_type dispatch helper for MBA attribute types +/// @param[out] o_data vectorized attribute data +/// @return fapi2::ReturnCode +/// +template<attr A, typename TT = attr_traits<A>> +inline fapi2::ReturnCode vectorize_attr_data(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target, + std::false_type, std::vector<uint8_t>& o_data) +{ + o_data.clear(); + + // Loops through all MBA + for(const auto& l_mba : i_target.getChildren<fapi2::TARGET_TYPE_MBA>()) + { + // Gets the attribute in question + uint8_t l_attr_data = 0; + FAPI_TRY(TT::getter(l_mba, l_attr_data)); + o_data.push_back(l_attr_data); + FAPI_DBG("%s adding data0x%02x to vector size:%u for attr %u", + mss::spd::c_str(l_mba), l_attr_data, o_data.size(), A); + } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Assembles the attribute into a vector for processing +/// @tparam attr A attribute on which to operate +/// @tparam attr_traits TT traits for the associated attribute +/// @param[in] i_target centaur target on which to operate +/// @param[in] std::true_type dispatch helper for DIMM attribute types +/// @param[out] o_data vectorized attribute data +/// @return fapi2::ReturnCode +/// +template<attr A, typename TT = attr_traits<A>> +inline fapi2::ReturnCode vectorize_attr_data(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target, + std::true_type, std::vector<uint8_t>& o_data) +{ + o_data.clear(); + + // Loops through all MBA + for(const auto& l_mba : i_target.getChildren<fapi2::TARGET_TYPE_MBA>()) + { + // Gets the attribute in question + uint8_t l_attr_data[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; + FAPI_TRY(TT::getter(l_mba, l_attr_data)); + + // Loops through all DIMM's so we only get valid data + for(const auto& l_dimm : l_mba.getChildren<fapi2::TARGET_TYPE_DIMM>()) + { + uint32_t l_dimm_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FAPI_POS, l_dimm, l_dimm_pos)); + { + // Converts the DIMM pos into the relative position compared to the MBA + const auto l_relative_pos = l_dimm_pos % MAX_DIMM_PER_MBA; + + const auto l_port_index = l_relative_pos / MAX_PORTS_PER_MBA; + const auto l_dimm_index = l_relative_pos % MAX_DIMM_PER_PORT; + o_data.push_back(l_attr_data[l_port_index][l_dimm_index]); + FAPI_DBG("%s adding data0x%02x to vector port%u dimm%u size:%u", + mss::spd::c_str(l_mba), l_attr_data[l_port_index][l_dimm_index], + l_port_index, l_dimm_index, o_data.size()); + } + } + + } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Checks if a configuration for a specific attribute is balanced over both MBA - recursion helper +/// @tparam attr A the attribute on which to operate +/// @tparam attr_traits TT traits for the associated attribute +/// @param[in] i_target centaur target on which to operate +/// @return fapi2::ReturnCode +/// +template<attr A, typename TT = attr_traits<A>> +inline fapi2::ReturnCode check_for_balanced_config_helper(const fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target) +{ + // Helper for the FFDC below - FFDC doesnt like constexpr + const auto ATTR = A; + + // Vector of attribute data + std::vector<uint8_t> l_attr_data; + + // Gets the attribute data + FAPI_TRY(vectorize_attr_data<A>(i_target, std::integral_constant<bool, TT::IS_DIMM_TYPE> {}, + l_attr_data)); + + // Assert out if we're not balanced + FAPI_ASSERT(is_data_equivalent(l_attr_data), + fapi2::CEN_MSS_PLUG_RULES_MBA_MISMATCH() + .set_TARGET_CEN(i_target) + .set_ATTR(ATTR), + "%s has an unbalanced config for %s", + mss::c_str(i_target), TT::STR); + + return check_for_balanced_config_helper < static_cast<attr>(A + 1u) > (i_target); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Checks if a configuration for a specific attribute is balanced over both MBA - ending specialization +/// @param[in] i_target centaur target on which to operate +/// @return fapi2::ReturnCode +/// +template<> +inline fapi2::ReturnCode check_for_balanced_config_helper<attr::END>(const + fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP>& i_target) +{ + FAPI_INF("%s has a balanced configuration between the MBA's", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief mss_eff_config_verify_plug_rules(): Verifies plugrules on a per-Centaur basis +/// @param[in] i_target_mba: the fapi2 target +/// @return fapi2::ReturnCode +/// @note We pass in an MBA specifically to see if we're running on MBA23 +/// We only need to run this plug rules test if we have two MBA's +/// +inline fapi2::ReturnCode mss_eff_config_verify_centaur_plug_rules(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) +{ + const auto& l_cen = i_target.getParent<fapi2::TARGET_TYPE_MEMBUF_CHIP>(); + uint8_t l_mba_pos = 0; + + // First, check if we're MBA23 - if not, exit sucessfully + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target, l_mba_pos)); + + if(l_mba_pos % MAX_MBA_PER_CEN == 0) + { + FAPI_INF("%s is MBA01, exiting succesfully", mss::spd::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + FAPI_INF("%s is MBA23, checking that MBA01's configuration == MBA23's configuration", mss::spd::c_str(i_target)); + + return check_for_balanced_config_helper<attr::START>(l_cen); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns +} // cen + +#endif diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C index 06c84da79..02f8a2a1d 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_bulk_pwr_throttles.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -67,7 +67,7 @@ #include <p9c_mss_bulk_pwr_throttles.H> #include <generic/memory/lib/utils/c_str.H> #include <dimmConsts.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <generic/memory/lib/utils/count_dimm.H> //------------------------------------------------------------------------------ // Includes diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C index d01c3ccb6..5f0233b2c 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,7 +53,7 @@ #include <p9c_mss_draminit_mc.H> #include <p9c_mss_row_repair.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <dimmConsts.H> //---------------------------------------------------------------------- // Address Includes diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training.C index f45a498fd..461d7c576 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training.C @@ -53,7 +53,7 @@ #include <p9c_mss_row_repair.H> #include <p9c_mss_draminit_training.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <dimmConsts.H> #include <delayRegs.H> diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C index bc137313d..5b4c25277 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,6 +39,7 @@ #include <p9c_mss_eff_config_rank_group.H> #include <p9c_mss_eff_config_shmoo.H> #include <generic/memory/lib/utils/c_str.H> +#include <p9c_cen_plug_rules.H> //------------------------------------------------------------------------------ // Constants @@ -2725,6 +2726,9 @@ extern "C" FAPI_TRY(mss_eff_config_shmoo(i_target_mba)); + // Checks that both MBA's are configured the same + FAPI_TRY(mss::cen::mss_eff_config_verify_centaur_plug_rules(i_target_mba)); + FAPI_INF("mss_eff_config on %s COMPLETE\n", mss::c_str(i_target_mba)); fapi_try_exit: diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.H index 1c70a3918..e325b9f8a 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,7 +45,6 @@ #include <dimmConsts.H> typedef fapi2::ReturnCode (*p9c_mss_eff_config_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_MBA> i_target_mba); - /// /// @brief struct mss_eff_config_data /// @brief holds the the variables used in many function calls diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C index c613abb9f..c068389c5 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_eff_config_thermal.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,7 +45,7 @@ #include <generic/memory/lib/utils/c_str.H> #include <dimmConsts.H> #include <generic/memory/lib/utils/count_dimm.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C index 34aef9a4f..b33f4dad9 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mrs6_DDR4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,6 +57,7 @@ extern "C" fapi2::ReturnCode p9c_mss_mrs6_DDR4(const fapi2::Target<fapi2::TARGET_TYPE_MBA>& i_target) { uint32_t l_ccs_inst_cnt = 0; + fapi2::buffer<uint64_t> l_shadow_data; for (uint8_t l_port_number = 0; l_port_number < 2; ++l_port_number) { @@ -65,6 +66,9 @@ extern "C" FAPI_TRY(mss_mr6_loader(i_target, l_port_number, l_ccs_inst_cnt), " mrs_load Failed"); } + // Get MR0 Shadow reg + FAPI_TRY(fapi2::getScom(i_target, 0x8000c01c0301143f, l_shadow_data)); + // Execute the contents of CCS array if (l_ccs_inst_cnt > 0) { @@ -74,6 +78,17 @@ extern "C" l_ccs_inst_cnt = 0; } + // Put MR0 Shadow Reg + FAPI_INF("Resetting MR0 Shadow registers to %016x", l_shadow_data); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c01c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c01c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c11c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c11c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c21c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c21c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8001c31c0301143f, l_shadow_data)); + FAPI_TRY(fapi2::putScom(i_target, 0x8000c31c0301143f, l_shadow_data)); + fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C index 8362380a7..8323cf8b6 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_rowRepairFuncs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,7 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ #include <p9c_mss_rowRepairFuncs.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <generic/memory/lib/utils/c_str.H> using namespace fapi2; diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C index 19485c13b..c613eb50c 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_row_repair.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -26,7 +26,7 @@ #include <cen_gen_scom_addresses.H> #include <cen_gen_scom_addresses_fld.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <p9c_mss_funcs.H> #include <p9c_mss_ddr4_funcs.H> #include <p9c_mss_rowRepairFuncs.H> diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_unmask_errors.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_unmask_errors.C index d51b829be..868ae2234 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_unmask_errors.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_unmask_errors.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,7 +42,7 @@ #include <p9c_mss_unmask_errors.H> #include <cen_gen_scom_addresses.H> #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> /// /// @brief Sets action regs and mask settings for pervasive errors to their runtime settings. diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_dimm_count.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_dimm_count.C index c24fcf6fb..7617253a6 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_dimm_count.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_dimm_count.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <fapi2.H> #include <p9c_mss_volt_dimm_count.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> using fapi2::TARGET_TYPE_MBA; using fapi2::TARGET_TYPE_DIMM; diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C index 2cd518ef0..f4d959eb4 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_volt_vddr_offset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,7 +43,7 @@ #include <fapi2.H> #include <p9c_mss_volt_vddr_offset.H> #include <mss_dynamic_vid_utils.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/cumulus_find.H> #include <generic/memory/lib/utils/count_dimm.H> extern "C" diff --git a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml index a42bc0062..ce516875c 100644 --- a/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml +++ b/src/import/chips/centaur/procedures/xml/error_info/p9c_memory_mss_eff_config_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2017,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2017,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -226,10 +226,10 @@ <description>Plug rule violation, one position is empty but other are present </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> @@ -257,10 +257,10 @@ <description>Plug rule violation, sides do not match </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -290,10 +290,10 @@ <description>Plug rule violation, top and bottom do not match </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> - <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_0_1</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_0</ffdc> + <ffdc>CUR_DIMM_SPD_VALID_U8ARRAY_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -322,10 +322,10 @@ <description>Incompatable DRAM generation </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>DRAM_DEVICE_TYPE_0_0</ffdc> - <ffdc>DRAM_DEVICE_TYPE_0_1</ffdc> - <ffdc>DRAM_DEVICE_TYPE_1_0</ffdc> - <ffdc>DRAM_DEVICE_TYPE_1_1</ffdc> + <ffdc>DRAM_DEVICE_TYPE_0_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_0_1</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_0</ffdc> + <ffdc>DRAM_DEVICE_TYPE_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -354,10 +354,10 @@ <description>Incompatable DIMM type </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>MODULE_TYPE_0_0</ffdc> - <ffdc>MODULE_TYPE_0_1</ffdc> - <ffdc>MODULE_TYPE_1_0</ffdc> - <ffdc>MODULE_TYPE_1_1</ffdc> + <ffdc>MODULE_TYPE_0_0</ffdc> + <ffdc>MODULE_TYPE_0_1</ffdc> + <ffdc>MODULE_TYPE_1_0</ffdc> + <ffdc>MODULE_TYPE_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -386,10 +386,10 @@ <description>Incompatable DIMM ranks </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>NUM_RANKS_0_0</ffdc> - <ffdc>NUM_RANKS_0_1</ffdc> - <ffdc>NUM_RANKS_1_0</ffdc> - <ffdc>NUM_RANKS_1_1</ffdc> + <ffdc>NUM_RANKS_0_0</ffdc> + <ffdc>NUM_RANKS_0_1</ffdc> + <ffdc>NUM_RANKS_1_0</ffdc> + <ffdc>NUM_RANKS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -418,10 +418,10 @@ <description>Incompatable DIMM banks </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_BANKS_0_0</ffdc> - <ffdc>SDRAM_BANKS_0_1</ffdc> - <ffdc>SDRAM_BANKS_1_0</ffdc> - <ffdc>SDRAM_BANKS_1_1</ffdc> + <ffdc>SDRAM_BANKS_0_0</ffdc> + <ffdc>SDRAM_BANKS_0_1</ffdc> + <ffdc>SDRAM_BANKS_1_0</ffdc> + <ffdc>SDRAM_BANKS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -450,10 +450,10 @@ <description>Incompatable DIMM rows </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_ROWS_0_0</ffdc> - <ffdc>SDRAM_ROWS_0_1</ffdc> - <ffdc>SDRAM_ROWS_1_0</ffdc> - <ffdc>SDRAM_ROWS_1_1</ffdc> + <ffdc>SDRAM_ROWS_0_0</ffdc> + <ffdc>SDRAM_ROWS_0_1</ffdc> + <ffdc>SDRAM_ROWS_1_0</ffdc> + <ffdc>SDRAM_ROWS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -482,10 +482,10 @@ <description>Incompatable DIMM columns </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>SDRAM_COLS_0_0</ffdc> - <ffdc>SDRAM_COLS_0_1</ffdc> - <ffdc>SDRAM_COLS_1_0</ffdc> - <ffdc>SDRAM_COLS_1_1</ffdc> + <ffdc>SDRAM_COLS_0_0</ffdc> + <ffdc>SDRAM_COLS_0_1</ffdc> + <ffdc>SDRAM_COLS_1_0</ffdc> + <ffdc>SDRAM_COLS_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -514,10 +514,10 @@ <description>Incompatable DRAM primary bus width </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>BUS_WIDTH_0_0</ffdc> - <ffdc>BUS_WIDTH_0_1</ffdc> - <ffdc>BUS_WIDTH_1_0</ffdc> - <ffdc>BUS_WIDTH_1_1</ffdc> + <ffdc>BUS_WIDTH_0_0</ffdc> + <ffdc>BUS_WIDTH_0_1</ffdc> + <ffdc>BUS_WIDTH_1_0</ffdc> + <ffdc>BUS_WIDTH_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -575,10 +575,10 @@ <description>Incompatable DRAM width </description> <FFDC>TARGET_MBA</FFDC> - <ffdc>DRAM_WIDTH_0_0</ffdc> - <ffdc>DRAM_WIDTH_0_1</ffdc> - <ffdc>DRAM_WIDTH_1_0</ffdc> - <ffdc>DRAM_WIDTH_1_1</ffdc> + <ffdc>DRAM_WIDTH_0_0</ffdc> + <ffdc>DRAM_WIDTH_0_1</ffdc> + <ffdc>DRAM_WIDTH_1_0</ffdc> + <ffdc>DRAM_WIDTH_1_1</ffdc> <callout> <procedure>MEMORY_PLUGGING_ERROR</procedure> @@ -1028,5 +1028,19 @@ </hwpError> +<hwpError> + <rc>RC_CEN_MSS_PLUG_RULES_MBA_MISMATCH</rc> + <description>Mismatch found between MBA configurations</description> + <FFDC>TARGET_CEN</FFDC> + <ffdc>ATTR</ffdc> + <callout> + <target>TARGET_CEN</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET_CEN</target> + </deconfigure> +</hwpError> + </hwpErrors> diff --git a/src/import/chips/common/utils/chipids.H b/src/import/chips/common/utils/chipids.H index 5f9a321d6..6e05e21dd 100644 --- a/src/import/chips/common/utils/chipids.H +++ b/src/import/chips/common/utils/chipids.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -83,7 +83,8 @@ constexpr uint32_t NIMBUS = 0x020D1049; constexpr uint32_t CUMULUS = 0x020D4049; constexpr uint32_t AXONE = 0x020D9049; constexpr uint32_t CENTAUR = 0x06039049; -constexpr uint32_t EXPLORER = 0x060D2049; +constexpr uint32_t EXPLORER = 0x060D2000; +constexpr uint32_t GEMINI = 0x060DC000; // Shorter 16-bit value (drops Major nibble and 049) constexpr uint32_t NIMBUS_16 = 0x20D1; @@ -91,6 +92,7 @@ constexpr uint32_t CUMULUS_16 = 0x20D4; constexpr uint32_t AXONE_16 = 0x20D9; constexpr uint32_t CENTAUR_16 = 0x6039; constexpr uint32_t EXPLORER_16 = 0x60D2; +constexpr uint32_t GEMINI_16 = 0x60DC; }; //namespace @@ -103,9 +105,20 @@ namespace POWER_OCID constexpr uint16_t EXPLORER = 0x0636; -// Vendir IDs +// Vendor IDs constexpr uint16_t VENDOR_IBM = 0x1014; }; //namespace + +// DMB (Differential Memory Buffer) IDs +namespace DDIMM_DMB_ID +{ + +// DDR4 DDIMM - Bytes [198][199] +constexpr uint16_t EXPLORER = 0x8029; +constexpr uint16_t GEMINI = 0x80A4; + +}; + #endif /* _CHIPIDS_H */ diff --git a/src/import/chips/ocmb/common/include/pmic_regs.H b/src/import/chips/ocmb/common/include/pmic_regs.H new file mode 100644 index 000000000..f3010e727 --- /dev/null +++ b/src/import/chips/ocmb/common/include/pmic_regs.H @@ -0,0 +1,154 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/include/pmic_regs.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_regs.H +/// @brief PMIC Registers +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __PMIC_REGS__ +#define __PMIC_REGS__ + +#include <lib/utils/pmic_consts.H> + +/// +/// @brief Registers for PMIC devices +/// @class pmicRegs +/// @tparam P pmic_product +/// +template<mss::pmic::product P> +struct pmicRegs; + +/// +/// @brief JEDEC Common Registers +/// @note These registers are not defined with any particular name other than RXX. +/// Their purposes and bit-mappings are outlined in any of the JEDEC compliant PMIC specs. +/// +template<> +struct pmicRegs<mss::pmic::product::JEDEC_COMPLIANT> +{ + static constexpr uint8_t BROADCAST = 0x0; + /* R00 - R03 RESERVED */ + static constexpr uint8_t R04 = 0x04; + static constexpr uint8_t R05 = 0x05; + static constexpr uint8_t R06 = 0x06; + /* R07 RESERVED */ + static constexpr uint8_t R08 = 0x08; + static constexpr uint8_t R09 = 0x09; + static constexpr uint8_t R0A = 0x0A; + static constexpr uint8_t R0B = 0x0B; + static constexpr uint8_t R0C = 0x0C; + static constexpr uint8_t R0D = 0x0D; + static constexpr uint8_t R0E = 0x0E; + static constexpr uint8_t R0F = 0x0F; + static constexpr uint8_t R10 = 0x10; + static constexpr uint8_t R11 = 0x11; + static constexpr uint8_t R12 = 0x12; + static constexpr uint8_t R13 = 0x13; + static constexpr uint8_t R14 = 0x14; + static constexpr uint8_t R15 = 0x15; + static constexpr uint8_t R16 = 0x16; + static constexpr uint8_t R17 = 0x17; + static constexpr uint8_t R18 = 0x18; + static constexpr uint8_t R19 = 0x19; + static constexpr uint8_t R1A = 0x1A; + static constexpr uint8_t R1B = 0x1B; + static constexpr uint8_t R1C = 0x1C; + static constexpr uint8_t R1D = 0x1D; + static constexpr uint8_t R1E = 0x1E; + static constexpr uint8_t R1F = 0x1F; + static constexpr uint8_t R20 = 0x20; + static constexpr uint8_t R21_SWA_VOLTAGE_SETTING = 0x21; + static constexpr uint8_t R22 = 0x22; + static constexpr uint8_t R23_SWB_VOLTAGE_SETTING = 0x23; + static constexpr uint8_t R24 = 0x24; + static constexpr uint8_t R25_SWC_VOLTAGE_SETTING = 0x25; + static constexpr uint8_t R26 = 0x26; + static constexpr uint8_t R27_SWD_VOLTAGE_SETTING = 0x27; + static constexpr uint8_t R28 = 0x28; + static constexpr uint8_t R29 = 0x29; + static constexpr uint8_t R2A = 0x2A; + static constexpr uint8_t R2B = 0x2B; + static constexpr uint8_t R2C = 0x2C; + static constexpr uint8_t R2D = 0x2D; + static constexpr uint8_t R2E = 0x2E; + static constexpr uint8_t R2F = 0x2F; + static constexpr uint8_t R30 = 0x30; + static constexpr uint8_t R31 = 0x31; + static constexpr uint8_t R32 = 0x32; + static constexpr uint8_t R33 = 0x33; + static constexpr uint8_t R34 = 0x34; + static constexpr uint8_t R35 = 0x35; + /* R36 RESERVED */ + static constexpr uint8_t R37_PASSWORD_LOWER_BYTE_0 = 0x37; + static constexpr uint8_t R38_PASSWORD_UPPER_BYTE_1 = 0x38; + static constexpr uint8_t R39_COMMAND_CODES = 0x39; + static constexpr uint8_t R3A = 0x3A; + static constexpr uint8_t R3B = 0x3B; + static constexpr uint8_t R3C_VENDOR_ID_BYTE_0 = 0x3C; + static constexpr uint8_t R3D_VENDOR_ID_BYTE_1 = 0x3D; + + /* ----- DIMM VENDOR REGION ----- */ + + /* R3E - R3F RESERVED */ + static constexpr uint8_t R40_POWER_ON_SEQUENCE_CONFIG_1 = 0x40; + static constexpr uint8_t R41_POWER_ON_SEQUENCE_CONFIG_2 = 0x41; + static constexpr uint8_t R42_POWER_ON_SEQUENCE_CONFIG_3 = 0x42; + static constexpr uint8_t R43_POWER_ON_SEQUENCE_CONFIG_4 = 0x43; + /* R44 RESERVED */ + static constexpr uint8_t R45_SWA_VOLTAGE_SETTING = 0x45; + static constexpr uint8_t R46 = 0x46; + static constexpr uint8_t R47_SWB_VOLTAGE_SETTING = 0x47; + static constexpr uint8_t R48 = 0x48; + static constexpr uint8_t R49_SWC_VOLTAGE_SETTING = 0x49; + static constexpr uint8_t R4A = 0x4A; + static constexpr uint8_t R4B_SWD_VOLTAGE_SETTING = 0x4B; + static constexpr uint8_t R4C = 0x4C; + static constexpr uint8_t R4D = 0x4D; + static constexpr uint8_t R4E = 0x4E; + static constexpr uint8_t R4F = 0x4F; + static constexpr uint8_t R50 = 0x50; + static constexpr uint8_t R51 = 0x51; + /* R52 - R57 RESERVED */ + static constexpr uint8_t R58_POWER_OFF_SEQUENCE_CONFIG_1 = 0x58; + static constexpr uint8_t R59_POWER_OFF_SEQUENCE_CONFIG_2 = 0x59; + static constexpr uint8_t R5A_POWER_OFF_SEQUENCE_CONFIG_3 = 0x5A; + static constexpr uint8_t R5B_POWER_OFF_SEQUENCE_CONFIG_4 = 0x5B; + /* R5C RESERVED */ + static constexpr uint8_t R5D = 0x5D; + static constexpr uint8_t R5E = 0x5E; + static constexpr uint8_t R5F_PRIMARY_INFERFACE_IO_TYPE = 0x5F; + /* R60 - R6C RESERVED */ + static constexpr uint8_t R6D = 0x6D; + static constexpr uint8_t R6E = 0x6E; + /* R6F RESERVED */ +}; + +#endif diff --git a/src/import/chips/ocmb/common/include/pmic_regs_fld.H b/src/import/chips/ocmb/common/include/pmic_regs_fld.H new file mode 100644 index 000000000..b5139939a --- /dev/null +++ b/src/import/chips/ocmb/common/include/pmic_regs_fld.H @@ -0,0 +1,193 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/include/pmic_regs_fld.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_regs_fld.H +/// @brief PMIC Register Fields +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __PMIC_REGS_FLD__ +#define __PMIC_REGS_FLD__ + +#include <lib/utils/pmic_consts.H> + +/// +/// @brief Register fields for PMIC devices +/// @class pmicFields +/// @tparam P pmic_product +/// +template<mss::pmic::product P> +struct pmicFields; + +/// +/// @brief Fields for JEDEC_COMPLIANT PMICs +/// +template<> +struct pmicFields<mss::pmic::product::JEDEC_COMPLIANT> +{ + static constexpr uint8_t R2F_SECURE_MODE = 0x02; + static constexpr uint8_t R32_VR_ENABLE = 0x07; + static constexpr uint8_t PMIC_DEVICE = 0x00; + + static constexpr uint8_t SWA_SWB_PHASE_MODE_SELECT = 0x00; + + static constexpr uint8_t SWA_VOLTAGE_RANGE = 0x05; + static constexpr uint8_t SWB_VOLTAGE_RANGE = 0x04; + static constexpr uint8_t SWC_VOLTAGE_RANGE = 0x03; + static constexpr uint8_t SWD_VOLTAGE_RANGE = 0x00; + + static constexpr uint8_t SEQUENCE_ENABLE = 0x07; + static constexpr uint8_t SEQUENCE_SWA_ENABLE = 0x06; + static constexpr uint8_t SEQUENCE_SWB_ENABLE = 0x05; + static constexpr uint8_t SEQUENCE_SWC_ENABLE = 0x04; + static constexpr uint8_t SEQUENCE_SWD_ENABLE = 0x03; + + // R04 + static constexpr uint8_t R04_GLOBAL_ERROR_COUNT = 0x07; + static constexpr uint8_t R04_GLOBAL_ERROR_LOG_BUCK_OV_OR_UV = 0x06; + static constexpr uint8_t R04_GLOBAL_ERROR_LOG_VIN_BULK_OVER_VOLTAGE = 0x05; + static constexpr uint8_t R04_GLOBAL_ERROR_LOG_CRITICAL_TEMPERATURE = 0x04; + + // R05 + static constexpr uint8_t R05_SWA_POWER_GOOD = 0x06; + static constexpr uint8_t R05_SWB_POWER_GOOD = 0x05; + static constexpr uint8_t R05_SWC_POWER_GOOD = 0x04; + static constexpr uint8_t R05_SWD_POWER_GOOD = 0x03; + static constexpr uint8_t R05_PMIC_ERROR_LOG = 0x02; // TK ARRAY + + // R06 + static constexpr uint8_t R06_SWA_UNDER_VOLTAGE_LOCKOUT = 0x07; + static constexpr uint8_t R06_SWB_UNDER_VOLTAGE_LOCKOUT = 0x06; + static constexpr uint8_t R06_SWC_UNDER_VOLTAGE_LOCKOUT = 0x05; + static constexpr uint8_t R06_SWD_UNDER_VOLTAGE_LOCKOUT = 0x04; + static constexpr uint8_t R06_SWA_OVER_VOLTAGE = 0x03; + static constexpr uint8_t R06_SWB_OVER_VOLTAGE = 0x02; + static constexpr uint8_t R06_SWC_OVER_VOLTAGE = 0x01; + static constexpr uint8_t R06_SWD_OVER_VOLTAGE = 0x00; + + // R07 all reserved + + // R08 + static constexpr uint8_t R08_VIN_BULK_INPUT_PWR_GOOD_STATUS = 0x07; + static constexpr uint8_t R08_CRITICAL_TEMP_SHUTDOWN_STATUS = 0x06; + static constexpr uint8_t R08_SWA_PWR_GOOD_STATUS = 0x05; + static constexpr uint8_t R08_SWB_PWR_GOOD_STATUS = 0x04; + static constexpr uint8_t R08_SWC_PWR_GOOD_STATUS = 0x03; + static constexpr uint8_t R08_SWD_PWR_GOOD_STATUS = 0x02; + static constexpr uint8_t R08_VIN_MGMT_INPUT_OVER_VOLTAGE = 0x01; + static constexpr uint8_t R08_VIN_BULK_INPUT_OVER_VOLTAGE = 0x00; + + // R09 + static constexpr uint8_t R09_PMIC_HIGH_TEMP_WARNING_STATUS = 0x07; + static constexpr uint8_t R09_VBIAS_PWR_GOOD_STATUS = 0x06; + static constexpr uint8_t R09_VOUT_1_8_V_PWR_GOOD_STATUS = 0x05; + static constexpr uint8_t R09_VIN_MGMT_TO_VIN_BULK_SWITCHOVER_STATUS = 0x04; + static constexpr uint8_t R09_SWA_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS = 0x03; + static constexpr uint8_t R09_SWB_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS = 0x02; + static constexpr uint8_t R09_SWC_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS = 0x01; + static constexpr uint8_t R09_SWD_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS = 0x00; + + // R0A + static constexpr uint8_t R0A_SWA_OUTPUT_OVER_VOLTAGE_STATUS = 0x07; + static constexpr uint8_t R0A_SWB_OUTPUT_OVER_VOLTAGE_STATUS = 0x06; + static constexpr uint8_t R0A_SWC_OUTPUT_OVER_VOLTAGE_STATUS = 0x05; + static constexpr uint8_t R0A_SWD_OUTPUT_OVER_VOLTAGE_STATUS = 0x04; + static constexpr uint8_t R0A_PEC_ERROR_STATUS = 0x03; + static constexpr uint8_t R0A_PARITY_ERROR_STATUS = 0x02; + static constexpr uint8_t R0A_IBI_STATUS = 0x01; // 0x00 reserved + + // R0B + static constexpr uint8_t R0B_SWA_OUTPUT_CURRENT_LIMITER_WARNING_STATUS = 0x07; + static constexpr uint8_t R0B_SWB_OUTPUT_CURRENT_LIMITER_WARNING_STATUS = 0x06; + static constexpr uint8_t R0B_SWC_OUTPUT_CURRENT_LIMITER_WARNING_STATUS = 0x05; + static constexpr uint8_t R0B_SWD_OUTPUT_CURRENT_LIMITER_WARNING_STATUS = 0x04; + static constexpr uint8_t R0B_SWA_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS = 0x03; + static constexpr uint8_t R0B_SWB_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS = 0x02; + static constexpr uint8_t R0B_SWC_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS = 0x01; + static constexpr uint8_t R0B_SWD_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS = 0x00; + + // R14 + static constexpr uint8_t R14_GLOBAL_CLEAR_STATUS = 0x00; + + // R1A + static constexpr uint8_t R1A_OUTPUT_POWER_SELECT = 0x01; + + // R1B + static constexpr uint8_t R1B_CURRENT_OR_POWER_METER_SELECT = 0x06; + + // R1C/R1D/R1E/R1F - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t HIGH_CURRENT_WARNING_START = 0x00; + static constexpr uint8_t HIGH_CURRENT_WARNING_LENGTH = 0x06; + + // R20 - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t R20_SWA_OUTPUT_CURRENT_LIMITER_WARNING_THRESHOLD_SETTING_START = 0x00; + static constexpr uint8_t R20_SWB_OUTPUT_CURRENT_LIMITER_WARNING_THRESHOLD_SETTING_START = 0x02; + static constexpr uint8_t R20_SWC_OUTPUT_CURRENT_LIMITER_WARNING_THRESHOLD_SETTING_START = 0x04; + static constexpr uint8_t R20_SWD_OUTPUT_CURRENT_LIMITER_WARNING_THRESHOLD_SETTING_START = 0x06; + static constexpr uint8_t R20_OUTPUT_CURRENT_LIMITER_WARNING_THRESHOLD_SETTING_LENGTH = 0x02; + + // R2B - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t R2B_LDO_1P8_VOLT_SETTING_START = 0x00; + static constexpr uint8_t R2B_LDO_1P8_VOLT_SETTING_LENGTH = 0x02; + static constexpr uint8_t R2B_LDO_1P1_VOLT_SETTING_START = 0x05; + static constexpr uint8_t R2B_LDO_1P1_VOLT_SETTING_LENGTH = 0x02; + + // R2F + static constexpr uint8_t R2F_SWA_REGULATOR_CONTROL = 0x06; + static constexpr uint8_t R2F_SWB_REGULATOR_CONTROL = 0x05; + static constexpr uint8_t R2F_SWC_REGULATOR_CONTROL = 0x04; + static constexpr uint8_t R2F_SWD_REGULATOR_CONTROL = 0x03; + + // R3B + static constexpr uint8_t R3B_PMIC_CURRENT_CAPABILITY = 0x00; + + // R4F + static constexpr uint8_t R4F_SWA_SWB_PHASE_MODE_SELECT = 0x00; + + // R30 - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t R30_ADC_ENABLE = 0x00; + static constexpr uint8_t R30_ADC_SELECT_START = 0x01; + static constexpr uint8_t R30_ADC_SELECT_LENGTH = 0x04; + + // R31 - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t R31_ADC_READ_SETTING_START = 0x00; + static constexpr uint8_t R31_ADC_READ_SETTING_LENGTH = 0x08; + + // R33 - bit positions flipped (0 is for bit7, 1 is for bit6, etc) + static constexpr uint8_t R33_TEMPERATURE_SETTING_START = 0x00; + static constexpr uint8_t R33_TEMPERATURE_SETTING_LENGTH = 0x03; + + static constexpr uint8_t DELAY_FLD_LENGTH = 3; + static constexpr uint8_t VOLTAGE_SETTING_START = 0; + static constexpr uint8_t VOLTAGE_SETTING_LENGTH = 7; + +}; + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_attr_engine_traits.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_attr_engine_traits.H new file mode 100644 index 000000000..ebee62c53 --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_attr_engine_traits.H @@ -0,0 +1,2486 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_attr_engine_traits.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_attr_engine_traits.H +/// @brief Trait class definitions for pmic attrs +/// + +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP FW Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_PMIC_ATTR_ENGINE_TRAITS_H_ +#define _MSS_PMIC_ATTR_ENGINE_TRAITS_H_ + +#include <fapi2.H> +#include <lib/utils/pmic_consts.H> +#include <lib/eff_config/pmic_efd_processing.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <lib/mss_pmic_attribute_getters.H> +#include <lib/mss_pmic_attribute_setters.H> + +namespace mss +{ + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, ATTR_EFF_BASE_CASE partial specialization +/// NOP for base case needed to trigger partial specialization of attr_engine +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::ATTR_EFF_BASE_CASE> {}; + + +//---------------------------------------- +// PMIC 0 +//---------------------------------------- + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_MFG_ID partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_MFG_ID> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_MFG_ID_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_MFG_ID_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_MFG_ID; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_mfg_id(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_mfg_id(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.mfg_id_pmic0(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWA_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWA_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWA_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swa_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swa_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swa_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWA_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWA_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWA_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swa_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swa_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swa_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWA_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWA_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWA_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swa_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swa_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swa_pmic0(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swa_pmic0(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWA_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWA_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWA_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swa_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swa_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swa_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWA_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWA_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWA_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swa_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swa_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swa_pmic0(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWB_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWB_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWB_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swb_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swb_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swb_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWB_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWB_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWB_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swb_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swb_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swb_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWB_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWB_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWB_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swb_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swb_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swb_pmic0(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swb_pmic0(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWB_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWB_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWB_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swb_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swb_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swb_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWB_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWB_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWB_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swb_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swb_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swb_pmic0(o_setting); + } +}; + + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWC_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWC_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWC_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swc_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swc_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swc_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWC_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWC_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWC_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swc_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swc_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swc_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWC_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWC_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWC_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swc_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swc_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swc_pmic0(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swc_pmic0(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWC_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWC_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWC_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swc_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swc_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swc_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWC_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWC_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWC_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swc_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swc_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swc_pmic0(o_setting); + } +}; + + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWD_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWD_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWD_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swd_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swd_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swd_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWD_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWD_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWD_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swd_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swd_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swd_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWD_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWD_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWD_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swd_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swd_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swd_pmic0(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swd_pmic0(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWD_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWD_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWD_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swd_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swd_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swd_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SWD_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SWD_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SWD_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_swd_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_swd_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swd_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_PHASE_COMB partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_PHASE_COMB> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_PHASE_COMB_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_PHASE_COMB_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_PHASE_COMB; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_phase_comb(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_phase_comb(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.phase_combination_pmic0(o_setting); + } +}; + + +//---------------------------------------- +// PMIC 1 +//---------------------------------------- + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_MFG_ID partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_MFG_ID> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_MFG_ID_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_MFG_ID_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_MFG_ID; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_mfg_id(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_mfg_id(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.mfg_id_pmic1(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWA_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWA_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWA_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swa_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swa_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swa_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWA_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWA_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWA_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swa_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swa_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swa_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWA_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWA_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWA_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swa_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swa_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swa_pmic1(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swa_pmic1(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWA_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWA_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWA_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swa_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swa_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swa_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWA_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWA_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWA_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swa_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swa_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swa_pmic1(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWB_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWB_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWB_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swb_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swb_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swb_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWB_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWB_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWB_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swb_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swb_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swb_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWB_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWB_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWB_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swb_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swb_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swb_pmic1(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swb_pmic1(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWB_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWB_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWB_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swb_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swb_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swb_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWB_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWB_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWB_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swb_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swb_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swb_pmic1(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWC_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWC_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWC_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swc_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swc_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swc_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWC_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWC_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWC_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swc_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swc_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swc_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWC_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWC_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWC_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swc_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swc_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swc_pmic1(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swc_pmic1(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWC_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWC_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWC_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swc_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swc_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swc_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWC_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWC_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWC_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swc_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swc_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swc_pmic1(o_setting); + } +}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWD_VOLTAGE_SETTING partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWD_VOLTAGE_SETTING> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_SETTING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_SETTING_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWD_VOLTAGE_SETTING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swd_voltage_setting(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swd_voltage_setting(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_swd_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWD_VOLTAGE_RANGE_SELECT partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWD_VOLTAGE_RANGE_SELECT> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_RANGE_SELECT_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_RANGE_SELECT_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWD_VOLTAGE_RANGE_SELECT; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swd_voltage_range_select(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swd_voltage_range_select(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_setpoint_range_swd_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWD_VOLTAGE_OFFSET partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWD_VOLTAGE_OFFSET> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_OFFSET_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_OFFSET_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWD_VOLTAGE_OFFSET; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swd_voltage_offset(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swd_voltage_offset(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_spd_data.volt_offset_swd_pmic1(l_offset)); + FAPI_TRY(i_spd_data.volt_offset_direction_swd_pmic1(l_direction)); + + o_setting = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWD_SEQUENCE_DELAY partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWD_SEQUENCE_DELAY> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_DELAY_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_DELAY_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWD_SEQUENCE_DELAY; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swd_sequence_delay(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swd_sequence_delay(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_delay_swd_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SWD_SEQUENCE_ORDER partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SWD_SEQUENCE_ORDER> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_ORDER_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_ORDER_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SWD_SEQUENCE_ORDER; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_swd_sequence_order(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_swd_sequence_order(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.volt_order_swd_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_PHASE_COMB partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_PHASE_COMB> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_PHASE_COMB_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_PHASE_COMB_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_PHASE_COMB; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_phase_comb(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_phase_comb(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.phase_combination_pmic1(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC0_SEQUENCE partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC0_SEQUENCE> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC0_SEQUENCE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC0_SEQUENCE_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC0_SEQUENCE; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic0_sequence(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic0_sequence(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.sequence_pmic0(o_setting); + } +}; + +// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note P, pmic::attr_eff_engine_fields, PMIC1_SEQUENCE partial specialization +/// +template< proc_type P> +struct attrEngineTraits<P, pmic::attr_eff_engine_fields, pmic::attr_eff_engine_fields::PMIC1_SEQUENCE> +{ + using attr_type = fapi2::ATTR_MEM_EFF_PMIC1_SEQUENCE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_PMIC1_SEQUENCE_TargetType; + static constexpr pmic::ffdc_codes FFDC_CODE = pmic::SET_PMIC1_SEQUENCE; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return attr::get_pmic1_sequence(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return attr::set_pmic1_sequence(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.sequence_pmic1(o_setting); + } +}; + +}//mss + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.C new file mode 100644 index 000000000..32e3157cb --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.C @@ -0,0 +1,274 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file pmic_efd_processing.C +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Mark Pizzutillo Mark.Pizzutillo@ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#include <fapi2.H> +#include <lib/mss_pmic_attribute_setters.H> +#include <lib/eff_config/pmic_efd_processing.H> +#include <lib/utils/pmic_consts.H> +#include <lib/utils/pmic_common_utils.H> + +namespace mss +{ +namespace pmic +{ + +/// +/// @brief Convert unsigned offset from SPD to signed offset for attributes +/// +/// @param[in] i_offset - unsigned offset +/// @param[in] i_direction - direction +/// @return int8_t signed equivalent +/// @note Should be used with SPD data where the offset is 7 bits such that overflow could not be possible +/// +int8_t convert_to_signed_offset(const uint8_t i_offset, const uint8_t i_direction) +{ + // Since offset value must be 7 bits (from SPD), we can directly cast it to an int8_t + int8_t l_signed_offset = static_cast<int8_t>(i_offset); + + if (i_direction == CONSTS::OFFSET_MINUS) + { + // Can't overflow since signed_offset was only 7 bits + l_signed_offset = 0 - l_signed_offset; + } + + return l_signed_offset; +} + +namespace efd +{ + +using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; +/// +/// @brief Processes the EFD PMIC0 SWA Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swa_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic0_swa_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic0_swa_offset_direction(l_direction)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic0_swa_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC0 SWB Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swb_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic0_swb_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic0_swb_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic0_swb_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC0 SWC Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swc_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic0_swc_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic0_swc_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic0_swc_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC0 SWD Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swd_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic0_swd_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic0_swd_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic0_swd_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC1 SWA Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swa_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic1_swa_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic1_swa_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic1_swa_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC1 SWB Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swb_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic1_swb_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic1_swb_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic1_swb_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC1 SWC Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swc_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic1_swc_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic1_swc_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic1_swc_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the EFD PMIC1 SWD Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swd_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + uint8_t l_offset = 0; + uint8_t l_direction = 0; + FAPI_TRY(i_efd_data->pmic1_swd_offset(l_offset)); + FAPI_TRY(i_efd_data->pmic1_swd_offset_direction(l_offset)); + { + int8_t l_signed_offset = mss::pmic::convert_to_signed_offset(l_offset, l_direction); + FAPI_TRY(mss::attr::set_efd_pmic1_swd_voltage_offset(i_target, l_signed_offset)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + FAPI_TRY(pmic0_swa_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic0_swb_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic0_swc_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic0_swd_voltage_offset(i_target, i_efd_data)); + + FAPI_TRY(pmic1_swa_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic1_swb_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic1_swc_voltage_offset(i_target, i_efd_data)); + FAPI_TRY(pmic1_swd_voltage_offset(i_target, i_efd_data)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // efd +} // pmic +} // mss diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.H new file mode 100644 index 000000000..e09d8087f --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.H @@ -0,0 +1,144 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/eff_config/pmic_efd_processing.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file pmic_efd_processing.H +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_PMIC_EFD_PROCESSING_H_ +#define _MSS_PMIC_EFD_PROCESSING_H_ + +#include <fapi2.H> +#include <generic/memory/lib/spd/ddimm/efd_decoder.H> + +namespace mss +{ +namespace pmic +{ + +/// +/// @brief Convert unsigned offset from SPD to signed offset for attributes +/// +/// @param[in] i_offset - unsigned offset +/// @param[in] i_direction - direction +/// @return int8_t signed equivalent +/// @note Should be used with SPD data where the offset is 7 bits such that overflow could not be possible +/// +int8_t convert_to_signed_offset(const uint8_t i_offset, const uint8_t i_direction); + +namespace efd +{ + +/// +/// @brief Processes the EFD PMIC0 SWA Voltage Offset & Direction +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swa_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC0 SWB Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swb_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC0 SWC Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swc_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC0 SWD Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic0_swd_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC1 SWA Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swa_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC1 SWB Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swb_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC1 SWC Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swc_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the EFD PMIC1 SWD Voltage Offset +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode pmic1_swd_voltage_offset(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +} // ns efd +} // ns exp +} // ns mss +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/i2c/i2c_pmic.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/i2c/i2c_pmic.H new file mode 100644 index 000000000..fcd79dec0 --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/i2c/i2c_pmic.H @@ -0,0 +1,159 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/i2c/i2c_pmic.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_i2c.H +/// @brief PMIC I2C utility function declarations +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_I2C_PMIC_H_ +#define _MSS_I2C_PMIC_H_ + +#include <fapi2.H> +#include <i2c_access.H> + +#include <vector> +#include <lib/utils/pmic_consts.H> +#include <generic/memory/lib/utils/pos.H> +#include <generic/memory/lib/utils/c_str.H> + +namespace mss +{ +namespace pmic +{ +namespace i2c +{ + +/// +/// @brief Perform a register write operation on the given PMIC chip +/// @param[in] i_target the PMIC target +/// @param[in] i_addr address to write to +/// @param[in] i_data_buffer buffer of data to write to the register +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode reg_write(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_target, + const uint8_t i_addr, + const fapi2::buffer<uint8_t>& i_data_buffer) +{ + std::vector<uint8_t> l_command; + l_command.push_back(i_addr); + l_command.push_back(uint8_t(i_data_buffer)); + + // Use fapi2 putI2c interface to execute command + FAPI_TRY(fapi2::putI2c(i_target, l_command), + "putI2C returned error for WRITE operation to 0x%.8X on PMIC %s", + i_addr, mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform a register read operation on the given PMIC chip +/// @param[in] i_target the PMIC target +/// @param[in] i_addr address to read +/// @param[out] o_data_buffer buffer of data we will write the contents of the register to +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode reg_read(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_target, + const uint8_t i_addr, + fapi2::buffer<uint8_t>& o_data_buffer) +{ + std::vector<uint8_t> l_data; + std::vector<uint8_t> l_command; + l_command.push_back(i_addr); + + FAPI_TRY(fapi2::getI2c(i_target, mss::pmic::i2c::sizes::DATA_LENGTH, l_command, l_data), + "i2C read failed on %s for address 0x%8x", mss::c_str(i_target), i_addr); + + // Flush o_data_buffer to avoid stale data + o_data_buffer.flush<0>(); + + FAPI_ASSERT( (l_data.size() == mss::pmic::i2c::sizes::DATA_LENGTH), + fapi2::I2C_PMIC_INVALID_READ_SIZE() + .set_TARGET(i_target) + .set_ADDRESS(i_addr) + .set_SIZE_REQUESTED(mss::pmic::i2c::sizes::DATA_LENGTH) + .set_SIZE_RETURNED(l_data.size()), + "PMIC I2C read returned vector size of %u. Expected %u", + l_data.size(), mss::pmic::i2c::sizes::DATA_LENGTH, + mss::c_str(i_target) ); + + o_data_buffer = l_data[0]; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform a register write operation after flipping the data buffer +/// @param[in] i_target the PMIC target +/// @param[in] i_addr address to write to +/// @param[in] i_data_buffer buffer of data to flip & write to the register +/// @return FAPI2_RC_SUCCESS iff okay +/// @note flips buffer from fapi2-style [0:7] to PMIC-style [7:0] +/// +inline fapi2::ReturnCode reg_write_reverse_buffer(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_target, + const uint8_t i_addr, + const fapi2::buffer<uint8_t>& i_data_buffer) +{ + // Copy as to not modify original referenced buffer + auto l_reg_buffer_copy = i_data_buffer; + l_reg_buffer_copy.reverse(); + + FAPI_TRY(mss::pmic::i2c::reg_write(i_target, i_addr, l_reg_buffer_copy)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform a register read operation on the given PMIC chip, then flip the data buffer +/// @param[in] i_target the PMIC target +/// @param[in] i_addr address to read +/// @param[out] o_data_buffer buffer of data we will write the contents of the register to +/// @return FAPI2_RC_SUCCESS iff okay +/// @note flips buffer from PMIC-style [7:0], to fapi2-style [0:7] +/// +inline fapi2::ReturnCode reg_read_reverse_buffer(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_target, + const uint8_t i_addr, + fapi2::buffer<uint8_t>& o_data_buffer) +{ + FAPI_TRY(mss::pmic::i2c::reg_read(i_target, i_addr, o_data_buffer)); + o_data_buffer.reverse(); +fapi_try_exit: + return fapi2::current_err; +} + +} // i2c +} // pmic +} // mss + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C new file mode 100644 index 000000000..f89559dde --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C @@ -0,0 +1,390 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +/// +/// @file pmic_common_utils.C +/// @brief Utility functions common for several PMIC procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <pmic_regs.H> +#include <pmic_regs_fld.H> +#include <lib/i2c/i2c_pmic.H> +#include <lib/utils/pmic_consts.H> +#include <lib/utils/pmic_common_utils.H> +#include <generic/memory/lib/utils/poll.H> +#include <generic/memory/lib/utils/c_str.H> + +namespace mss +{ +namespace pmic +{ + +/// +/// @brief polls PMIC for PBULK PWR_GOOD status +/// +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::ReturnCode success if good, error if polling fail or power not good +/// +fapi2::ReturnCode poll_for_pbulk_good( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using REGS = pmicRegs<J>; + using FIELDS = pmicFields<J>; + + // Using default poll parameters + mss::poll_parameters l_poll_params; + + FAPI_ASSERT( mss::poll(i_pmic_target, l_poll_params, [&i_pmic_target]()->bool + { + fapi2::buffer<uint8_t> l_pbulk_status_buffer; + + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R08, l_pbulk_status_buffer), + "pmic_enable: Could not read 0x%02hhX on %s ", REGS::R08, mss::c_str(i_pmic_target)); + + return l_pbulk_status_buffer.getBit<FIELDS::R08_VIN_BULK_INPUT_PWR_GOOD_STATUS>() == + mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>::PWR_GOOD; + + fapi_try_exit: + // No ack, return false and continue polling + return false; + }), + fapi2::MSS_EXP_I2C_POLLING_TIMEOUT(). + set_TARGET(i_pmic_target), + "I2C read from %s either did not ACK or VIN_BULK did not respond with PWR_GOOD status", + mss::c_str(i_pmic_target) ); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Unlocks PMIC vendor region +/// +/// @param[in] i_pmic_target JEDEC-COMPLIANT PMIC to unlock +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode unlock_vendor_region(const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target) +{ + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + + // Unlock + const fapi2::buffer<uint8_t> l_password_low(CONSTS::VENDOR_PASSWORD_LOW); + const fapi2::buffer<uint8_t> l_password_high(CONSTS::VENDOR_PASSWORD_HIGH); + const fapi2::buffer<uint8_t> l_unlock_code(CONSTS::UNLOCK_VENDOR_REGION); + + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R37_PASSWORD_LOWER_BYTE_0, l_password_low)); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R38_PASSWORD_UPPER_BYTE_1, l_password_high)); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R39_COMMAND_CODES, l_unlock_code)); + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Locks PMIC vendor region +/// +/// @param[in] i_pmic_target - JEDEC-COMPLIANT PMIC to lock +/// @param[in] i_rc - return code from the end of the caller function (if applicable) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff i_rc == SUCCESS && no errors in unlocking, else return current_err +/// +fapi2::ReturnCode lock_vendor_region(const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::ReturnCode i_rc) +{ + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + + // Lock vendor region, password registers are cleared automatically + const fapi2::buffer<uint8_t> l_lock_code(CONSTS::LOCK_VENDOR_REGION); + const fapi2::buffer<uint8_t> l_zero_code(0); + + fapi2::ReturnCode l_lock_return_code = fapi2::FAPI2_RC_SUCCESS; + + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R39_COMMAND_CODES, l_lock_code)); + + return i_rc; + +fapi_try_exit: + // Since we could have 2 possible errors at the same time here, we are letting the caller's i_rc take precedence. + // So, if we find an error while locking, we will report it here. We will only "return" this error if the + // caller's error is success, as to not overwrite it. + FAPI_ERR("Error code 0x%0llx: Error while trying to lock vendor region", uint64_t(fapi2::current_err)); + return ((i_rc == fapi2::FAPI2_RC_SUCCESS) ? fapi2::current_err : i_rc); +} + +/// +/// @brief Check if PMIC is IDT vendor +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_is_idt true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// @note Can't unit test this properly as R3D is hardcoded in simics +/// +fapi2::ReturnCode pmic_is_idt(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_is_idt) +{ + o_is_idt = false; + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + fapi2::buffer<uint8_t> l_reg_contents; + + FAPI_TRY(mss::pmic::i2c::reg_read(i_pmic_target, REGS::R3D_VENDOR_ID_BYTE_1, l_reg_contents)); + + o_is_idt = (l_reg_contents == mss::pmic::vendor::IDT_SHORT); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check if PMIC is TI vendor +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_is_ti true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// @note Can't unit test this properly as R3D is hardcoded in simics +/// +fapi2::ReturnCode pmic_is_ti(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_is_ti) +{ + o_is_ti = false; + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + fapi2::buffer<uint8_t> l_reg_contents; + + FAPI_TRY(mss::pmic::i2c::reg_read(i_pmic_target, REGS::R3D_VENDOR_ID_BYTE_1, l_reg_contents)); + + o_is_ti = (l_reg_contents == mss::pmic::vendor::TI_SHORT); + +fapi_try_exit: + return fapi2::current_err; +} + +namespace status +{ + +/// +/// @brief Checks that the PMIC is enabled via VR Enable bit +/// +/// @param[in] i_ocmb_target OCMB target +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode check_for_vr_enable( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target) +{ + fapi2::buffer<uint8_t> l_vr_enable_buffer; + + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R32, l_vr_enable_buffer), + "start_vr_enable: Could not read address 0x%02hhX of %s to check for VR Enable", + REGS::R32, + mss::c_str(i_pmic_target)); + + // Make sure we are enabled + FAPI_ASSERT(l_vr_enable_buffer.getBit<FIELDS::R32_VR_ENABLE>(), + fapi2::PMIC_NOT_ENABLED() + .set_PMIC_TARGET(i_pmic_target) + .set_OCMB_TARGET(i_ocmb_target), + "PMIC %s was not identified as enabled by checking VR Enable bit", + mss::c_str(i_pmic_target)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check the statuses of all PMICs present on the given OCMB chip +/// +/// @param[in] i_ocmb_target OCMB target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if success, else error code +/// @note the returned target is only valid if o_errors returns as true. Else, the target is an uninitialized blank target! +/// +fapi2::ReturnCode check_all_pmics(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target) +{ + const char* l_ocmb_c_str = mss::c_str(i_ocmb_target); + + // Initialize returnable PMIC with a blank target. This blank target won't be used if there's no error. + // If there is an error, this will be overwritten with a valid erroneous PMIC + bool l_pmic_error = false; + + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + + // Start success so we can't log and return the same error in loop logic + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + // Check that the PMICs are enabled and without errors + for (const auto& l_pmic : mss::find_targets<fapi2::TARGET_TYPE_PMIC>(i_ocmb_target)) + { + FAPI_TRY(check_for_vr_enable(i_ocmb_target, l_pmic), + "PMIC %s did not return enabled status", mss::c_str(l_pmic)); + + FAPI_TRY(mss::pmic::status::check_pmic(l_pmic, l_pmic_error)); + + FAPI_ASSERT_NOEXIT(!l_pmic_error, + fapi2::PMIC_STATUS_ERRORS() + .set_OCMB_TARGET(i_ocmb_target) + .set_PMIC_TARGET(l_pmic), + "PMIC on OCMB %s had one or more status bits set after running pmic_enable(). " + "One of possibly several bad PMICs: %s", + l_ocmb_c_str, mss::c_str(l_pmic)); + + if (l_rc != fapi2::FAPI2_RC_SUCCESS) + { + fapi2::logError(fapi2::current_err, fapi2::FAPI2_ERRL_SEV_UNRECOVERABLE); + } + + // Reset for next loop + l_rc = fapi2::current_err; + l_pmic_error = false; + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + } + + // Else, exit on whatever RC we had + FAPI_TRY(l_rc); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check the PMIC's status codes and report back if an error occurred +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_error true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode check_pmic( + const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, + bool& o_error) +{ + o_error = false; + bool l_pmic_is_idt = false; + + FAPI_TRY(pmic_is_idt(i_pmic_target, l_pmic_is_idt)); + + if (l_pmic_is_idt) + { + // These registers reflect the previous power down cycle of the PMIC. Therefore, they may + // not necessarily cause issues on this life. So, we do not need to worry about keeping track if + // these failed with l_status_error, but the check_fields() function will still print them out. + bool l_status_error = false; + + // if we exit from this try, there were i2c errors + FAPI_TRY(mss::pmic::status::check_fields(i_pmic_target, mss::pmic::status::IDT_SPECIFIC_STATUS_FIELDS, l_status_error)); + } + + { + bool l_status_error = false; + + // if we exit from this try, there were i2c errors + FAPI_TRY(mss::pmic::status::check_fields(i_pmic_target, mss::pmic::status::STATUS_FIELDS, l_status_error)); + o_error = l_status_error; + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clear PMIC status registers +/// +/// @param[in] i_pmic_target PMIC to clear +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target) +{ + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>; + + fapi2::buffer<uint8_t> l_reg_contents; + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents)); + + // Write to clear + l_reg_contents.setBit<FIELDS::R14_GLOBAL_CLEAR_STATUS>(); + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R14, l_reg_contents)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check an individual set of PMIC status codes +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_statuses STATUS object to check +/// @param[out] o_error At least one error bit was found to be set +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error in case of an I2C read error +/// +fapi2::ReturnCode check_fields( + const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, + const std::vector<std::pair<uint8_t, std::vector<status_field>>>& i_statuses, + bool& o_error) +{ + o_error = false; + + for (const auto& l_reg_bit_pair : i_statuses) + { + fapi2::buffer<uint8_t> l_reg_contents; + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, l_reg_bit_pair.first, l_reg_contents)); + + for (const auto& l_status : l_reg_bit_pair.second) + { + if (l_reg_contents.getBit(l_status.l_reg_field)) + { + // Print it out + FAPI_ERR("%s :: REG 0x%02x bit %u was set on %s", + l_status.l_error_description, + l_reg_bit_pair.first, + l_status.l_reg_field, + mss::c_str(i_pmic_target)); + // We don't want to exit out here, errors can be independent of each other and we should check them all. + // Since there's no easy way to FFDC each individual error, we will report them here and then worry about + // return codes in the caller of this function + o_error = true; + } + } + + l_reg_contents.flush<0>(); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +} // status +} // pmic +} // mss diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H new file mode 100644 index 000000000..1bc3aea1a --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H @@ -0,0 +1,337 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_common_utils.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +/// +/// @file pmic_common_utils.H +/// @brief Utility functions common for several PMIC procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#ifndef __PMIC_COMMON_UTILS_H__ +#define __PMIC_COMMON_UTILS_H__ + +#include <fapi2.H> +#include <pmic_regs.H> +#include <pmic_regs_fld.H> +#include <lib/utils/pmic_consts.H> +#include <mss_pmic_attribute_getters.H> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ +namespace pmic +{ + +// Attribute getter pointer for manufacturer/vendor ID +typedef fapi2::ReturnCode (*mfg_id_attr_ptr)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint16_t& o_value); + +// Manufacturer / Vendor ID +static constexpr mfg_id_attr_ptr get_mfg_id[] = +{ + mss::attr::get_pmic0_mfg_id, + mss::attr::get_pmic1_mfg_id, +}; + +using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; +using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>; +using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>;; + +// Arrays to easily index common parameters by rail +static constexpr uint8_t const VOLT_SETTING_ACTIVE_REGS[] = +{ + REGS::R21_SWA_VOLTAGE_SETTING, + REGS::R23_SWB_VOLTAGE_SETTING, + REGS::R25_SWC_VOLTAGE_SETTING, + REGS::R27_SWD_VOLTAGE_SETTING, +}; + +static constexpr uint8_t const VOLT_SETTING_VENDOR_REGS[] = +{ + REGS::R45_SWA_VOLTAGE_SETTING, + REGS::R47_SWB_VOLTAGE_SETTING, + REGS::R49_SWC_VOLTAGE_SETTING, + REGS::R4B_SWD_VOLTAGE_SETTING, +}; + +static constexpr uint8_t const VOLT_RANGE_FLDS[] = +{ + FIELDS::SWA_VOLTAGE_RANGE, + FIELDS::SWB_VOLTAGE_RANGE, + FIELDS::SWC_VOLTAGE_RANGE, + FIELDS::SWD_VOLTAGE_RANGE, +}; + +static constexpr uint32_t const VOLT_RANGE_MINS[][CONSTS::NUM_RANGES] = +{ + {CONSTS::SWABC_VOLT_RANGE0_MIN, CONSTS::SWABC_VOLT_RANGE1_MIN}, + {CONSTS::SWABC_VOLT_RANGE0_MIN, CONSTS::SWABC_VOLT_RANGE1_MIN}, + {CONSTS::SWABC_VOLT_RANGE0_MIN, CONSTS::SWABC_VOLT_RANGE1_MIN}, + {CONSTS::SWD_VOLT_RANGE0_MIN, CONSTS::SWD_VOLT_RANGE1_MIN}, +}; + +static constexpr uint32_t const VOLT_RANGE_MAXES[][CONSTS::NUM_RANGES] = +{ + {CONSTS::SWABC_VOLT_RANGE0_MAX, CONSTS::SWABC_VOLT_RANGE1_MAX}, + {CONSTS::SWABC_VOLT_RANGE0_MAX, CONSTS::SWABC_VOLT_RANGE1_MAX}, + {CONSTS::SWABC_VOLT_RANGE0_MAX, CONSTS::SWABC_VOLT_RANGE1_MAX}, + {CONSTS::SWD_VOLT_RANGE0_MAX, CONSTS::SWD_VOLT_RANGE1_MAX}, +}; + +/// +/// @brief Get the valid pmics for id object +/// +/// @param[in] i_pmic_target +/// @param[in] i_id +/// @param[out] o_pmics vector of PMICS matching +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +inline std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>> get_valid_pmics_for_id( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const mss::pmic::id i_id) +{ + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>> l_output_pmics; + + const auto l_pmics = mss::find_targets<fapi2::TARGET_TYPE_PMIC>(i_ocmb_target); + + for (const auto& l_pmic : l_pmics) + { + if (mss::index(l_pmic) % CONSTS::NUM_UNIQUE_PMICS == i_id) + { + l_output_pmics.push_back(l_pmic); + } + } + + return l_output_pmics; +} + +/// +/// @brief polls PMIC for PBULK PWR_GOOD status +/// +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::ReturnCode success if good, error if polling fail or power not good +/// +fapi2::ReturnCode poll_for_pbulk_good( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target); + +/// +/// @brief Unlocks PMIC vendor region +/// +/// @param[in] i_pmic_target JEDEC-COMPLIANT PMIC to unlock +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode unlock_vendor_region(const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target); + +/// +/// @brief Locks PMIC vendor region +/// +/// @param[in] i_pmic_target - JEDEC-COMPLIANT PMIC to lock +/// @param[in] i_rc - return code from the end of the caller function (if applicable) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff i_rc == SUCCESS && no errors in unlocking, else return current_err +/// +fapi2::ReturnCode lock_vendor_region(const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::ReturnCode i_rc = fapi2::FAPI2_RC_SUCCESS); + +/// +/// @brief Check if PMIC is IDT vendor +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_is_idt true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode pmic_is_idt(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_is_idt); + +/// +/// @brief Check if PMIC is TI vendor +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_is_ti true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode pmic_is_ti(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_is_ti); + +namespace status +{ + +/// +/// @brief Information for each field that we can iterate through +/// +struct status_field +{ + uint8_t l_reg_field; + const char* l_error_description; +}; + +static const std::vector<std::pair<uint8_t, std::vector<status_field>>> IDT_SPECIFIC_STATUS_FIELDS = +{ + { + REGS::R04, + { {FIELDS::R04_GLOBAL_ERROR_COUNT, "GLOBAL_ERROR_COUNT: >1 error count since last erase operation"}, + {FIELDS::R04_GLOBAL_ERROR_LOG_BUCK_OV_OR_UV, "GLOBAL_ERROR_LOG: BUCK OV/UV: Error occurred"}, + {FIELDS::R04_GLOBAL_ERROR_LOG_VIN_BULK_OVER_VOLTAGE, "GLOBAL_ERROR_LOG: VIN_BULK_OVER_VOLTAGE"}, + {FIELDS::R04_GLOBAL_ERROR_LOG_CRITICAL_TEMPERATURE, "GLOBAL_ERROR_LOG: CRITICAL_TEMPERATURE"}, + } + }, + + { + REGS::R05, + { {FIELDS::R05_SWA_POWER_GOOD, "PMIC POWER ON: SWA_PWR_NOT_GOOD"}, + {FIELDS::R05_SWB_POWER_GOOD, "PMIC POWER ON: SWB_PWR_NOT_GOOD"}, + {FIELDS::R05_SWC_POWER_GOOD, "PMIC POWER ON: SWC_PWR_NOT_GOOD"}, + {FIELDS::R05_SWD_POWER_GOOD, "PMIC POWER ON: SWD_PWR_NOT_GOOD"}, + } + }, + + { + REGS::R06, + { {FIELDS::R06_SWA_UNDER_VOLTAGE_LOCKOUT, "SWA_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R06_SWB_UNDER_VOLTAGE_LOCKOUT, "SWB_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R06_SWC_UNDER_VOLTAGE_LOCKOUT, "SWC_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R06_SWD_UNDER_VOLTAGE_LOCKOUT, "SWD_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R06_SWA_OVER_VOLTAGE, "SWA_OVER_VOLTAGE"}, + {FIELDS::R06_SWB_OVER_VOLTAGE, "SWB_OVER_VOLTAGE"}, + {FIELDS::R06_SWC_OVER_VOLTAGE, "SWC_OVER_VOLTAGE"}, + {FIELDS::R06_SWD_OVER_VOLTAGE, "SWD_OVER_VOLTAGE"}, + } + } +}; + +/// +/// @brief const vector of statuses to check +/// +static const std::vector<std::pair<uint8_t, std::vector<status_field>>> STATUS_FIELDS = +{ + { + REGS::R08, + { {FIELDS::R08_VIN_BULK_INPUT_PWR_GOOD_STATUS, "VIN_BULK_INPUT_PWR_NOT_GOOD"}, + {FIELDS::R08_CRITICAL_TEMP_SHUTDOWN_STATUS, "CRITICAL_TEMP_SHUTDOWN"}, + {FIELDS::R08_SWA_PWR_GOOD_STATUS, "SWA_PWR_NOT_GOOD"}, + {FIELDS::R08_SWB_PWR_GOOD_STATUS, "SWB_PWR_NOT_GOOD"}, + {FIELDS::R08_SWC_PWR_GOOD_STATUS, "SWC_PWR_NOT_GOOD"}, + {FIELDS::R08_SWD_PWR_GOOD_STATUS, "SWD_PWR_NOT_GOOD"}, + {FIELDS::R08_VIN_MGMT_INPUT_OVER_VOLTAGE, "VIN_MGMT_INPUT_OVER_VOLTAGE"}, + {FIELDS::R08_VIN_BULK_INPUT_OVER_VOLTAGE, "VIN_BULK_INPUT_OVER_VOLTAGE"}, + } + }, + + { + REGS::R09, + { {FIELDS::R09_PMIC_HIGH_TEMP_WARNING_STATUS, "PMIC Temperature exceeded warning threshold"}, + {FIELDS::R09_VBIAS_PWR_GOOD_STATUS, "VBIAS_PWR_NOT_GOOD"}, + {FIELDS::R09_VOUT_1_8_V_PWR_GOOD_STATUS, "VOUT_1.8V_PWR_NOT_GOOD"}, + {FIELDS::R09_VIN_MGMT_TO_VIN_BULK_SWITCHOVER_STATUS, "VIN_MGMT is removed (using VIN_Bulk)"}, + {FIELDS::R09_SWA_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS, "SWA_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING"}, + {FIELDS::R09_SWB_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS, "SWB_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING"}, + {FIELDS::R09_SWC_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS, "SWC_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING"}, + {FIELDS::R09_SWD_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING_STATUS, "SWD_HIGH_OUTPUT_CURRENT_CONSUMPTION_WARNING"}, + } + }, + + { + REGS::R0A, + { {FIELDS::R0A_SWA_OUTPUT_OVER_VOLTAGE_STATUS, "SWA_OUTPUT_OVER_VOLTAGE"}, + {FIELDS::R0A_SWB_OUTPUT_OVER_VOLTAGE_STATUS, "SWB_OUTPUT_OVER_VOLTAGE"}, + {FIELDS::R0A_SWC_OUTPUT_OVER_VOLTAGE_STATUS, "SWC_OUTPUT_OVER_VOLTAGE"}, + {FIELDS::R0A_SWD_OUTPUT_OVER_VOLTAGE_STATUS, "SWD_OUTPUT_OVER_VOLTAGE"}, + {FIELDS::R0A_PEC_ERROR_STATUS, "PEC_ERROR"}, + {FIELDS::R0A_PARITY_ERROR_STATUS, "PARITY_ERROR"}, + {FIELDS::R0A_IBI_STATUS, "PENDING_IBI"}, + } + }, + + { + REGS::R0B, + { {FIELDS::R0B_SWA_OUTPUT_CURRENT_LIMITER_WARNING_STATUS, "SWA_OUTPUT_CURRENT_LIMITER_EVENT"}, + {FIELDS::R0B_SWB_OUTPUT_CURRENT_LIMITER_WARNING_STATUS, "SWB_OUTPUT_CURRENT_LIMITER_EVENT"}, + {FIELDS::R0B_SWC_OUTPUT_CURRENT_LIMITER_WARNING_STATUS, "SWC_OUTPUT_CURRENT_LIMITER_EVENT"}, + {FIELDS::R0B_SWD_OUTPUT_CURRENT_LIMITER_WARNING_STATUS, "SWD_OUTPUT_CURRENT_LIMITER_EVENT"}, + {FIELDS::R0B_SWA_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS , "SWA_OUTPUT_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R0B_SWB_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS , "SWB_OUTPUT_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R0B_SWC_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS , "SWC_OUTPUT_UNDER_VOLTAGE_LOCKOUT"}, + {FIELDS::R0B_SWD_OUTPUT_UNDER_VOLTAGE_LOCKOUT_STATUS , "SWD_OUTPUT_UNDER_VOLTAGE_LOCKOUT"}, + } + } +}; + +/// +/// @brief Checks that the PMIC is enabled via VR Enable bit +/// +/// @param[in] i_ocmb_target OCMB target +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode check_for_vr_enable( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target); + +/// +/// @brief Check the statuses of all PMICs present on the given OCMB chip +/// +/// @param[in] i_ocmb_target OCMB target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if success, else error code +/// @note the returned target is only valid if o_errors returns as true. Else, the target is an uninitialized blank target! +/// +fapi2::ReturnCode check_all_pmics(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target); + +/// +/// @brief Check the PMIC's status codes and report back if an error occurred +/// +/// @param[in] i_pmic_target PMIC target +/// @param[out] o_error true/false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode check_pmic(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, bool& o_error); + +/// +/// @brief Clear PMIC status registers +/// +/// @param[in] i_pmic_target PMIC to clear +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode clear(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target); + +/// +/// @brief Check the IDT specific status codes +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_statuses STATUS object to check +/// @param[out] o_error At least one error bit was found to be set +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error in case of an I2C read error +/// +fapi2::ReturnCode check_fields( + const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, + const std::vector<std::pair<uint8_t, std::vector<status_field>>>& i_statuses, + bool& o_error); + +} // status +} // pmic +} // mss + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H new file mode 100644 index 000000000..4cb511dae --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H @@ -0,0 +1,313 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_consts.H +/// @brief Constants for PMIC procedures / i2C +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Andre A. Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: CI + +#ifndef MSS_PMIC_CONSTS_H +#define MSS_PMIC_CONSTS_H + +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> + +namespace mss +{ +namespace pmic +{ + +/// +/// @brief Module height from SPD (1U-4U) +/// @note these values are taken directly from the SPD. +/// +enum module_height +{ + HEIGHT_1U = 0b000, + HEIGHT_2U = 0b001, + HEIGHT_4U = 0b100, +}; + +/// +/// @brief IDs for PMIC0 or PMIC1 +/// +enum id +{ + PMIC0 = 0, + PMIC1 = 1, + PMIC2 = 2, + PMIC3 = 3, + UNKNOWN_ID = 4, // default constant for wrapper procedure +}; + +/// +/// @brief Constants for pmic product types +/// +enum product +{ + JEDEC_COMPLIANT, // Only JEDEC exists +}; + +/// +/// @brief constants for pmic vendor +/// +enum vendor +{ + UNKNOWN_VENDOR, + TI = 0x9780, + IDT = 0xB380, + + TI_SHORT = 0x97, + IDT_SHORT = 0xB3, +}; + +/// +/// @brief Constants for pmic rail +/// +enum rail +{ + SWA = 0, + SWB = 1, + SWC = 2, + SWD = 3, +}; + +enum class attr_eff_engine_fields +{ + // Template recursive base case + ATTR_EFF_BASE_CASE = 0, + + PMIC0_SWA_VOLTAGE_SETTING = 1, + PMIC0_SWA_VOLTAGE_RANGE_SELECT = 2, + PMIC0_SWA_VOLTAGE_OFFSET = 3, + PMIC0_SWA_SEQUENCE_DELAY = 4, + PMIC0_SWA_SEQUENCE_ORDER = 5, + + PMIC0_SWB_VOLTAGE_SETTING = 6, + PMIC0_SWB_VOLTAGE_RANGE_SELECT = 7, + PMIC0_SWB_VOLTAGE_OFFSET = 8, + PMIC0_SWB_SEQUENCE_DELAY = 9, + PMIC0_SWB_SEQUENCE_ORDER = 10, + + PMIC0_SWC_VOLTAGE_SETTING = 11, + PMIC0_SWC_VOLTAGE_RANGE_SELECT = 12, + PMIC0_SWC_VOLTAGE_OFFSET = 13, + PMIC0_SWC_SEQUENCE_DELAY = 14, + PMIC0_SWC_SEQUENCE_ORDER = 15, + + PMIC0_SWD_VOLTAGE_SETTING = 16, + PMIC0_SWD_VOLTAGE_RANGE_SELECT = 17, + PMIC0_SWD_VOLTAGE_OFFSET = 18, + PMIC0_SWD_SEQUENCE_DELAY = 19, + PMIC0_SWD_SEQUENCE_ORDER = 20, + + PMIC1_SWA_VOLTAGE_SETTING = 21, + PMIC1_SWA_VOLTAGE_RANGE_SELECT = 22, + PMIC1_SWA_VOLTAGE_OFFSET = 23, + PMIC1_SWA_SEQUENCE_DELAY = 24, + PMIC1_SWA_SEQUENCE_ORDER = 25, + + PMIC1_SWB_VOLTAGE_SETTING = 26, + PMIC1_SWB_VOLTAGE_RANGE_SELECT = 27, + PMIC1_SWB_VOLTAGE_OFFSET = 28, + PMIC1_SWB_SEQUENCE_DELAY = 29, + PMIC1_SWB_SEQUENCE_ORDER = 30, + + PMIC1_SWC_VOLTAGE_SETTING = 31, + PMIC1_SWC_VOLTAGE_RANGE_SELECT = 32, + PMIC1_SWC_VOLTAGE_OFFSET = 33, + PMIC1_SWC_SEQUENCE_DELAY = 34, + PMIC1_SWC_SEQUENCE_ORDER = 35, + + PMIC1_SWD_VOLTAGE_SETTING = 36, + PMIC1_SWD_VOLTAGE_RANGE_SELECT = 37, + PMIC1_SWD_VOLTAGE_OFFSET = 38, + PMIC1_SWD_SEQUENCE_DELAY = 39, + PMIC1_SWD_SEQUENCE_ORDER = 40, + + PMIC0_PHASE_COMB = 41, + PMIC1_PHASE_COMB = 42, + + PMIC0_MFG_ID = 43, + PMIC1_MFG_ID = 44, + PMIC0_SEQUENCE = 45, + PMIC1_SEQUENCE = 46, + + // Dispatcher set to last enum value + DISPATCHER = PMIC1_SEQUENCE, +}; + +/// +/// @brief explorer ffdc codes +/// +enum ffdc_codes +{ + SET_PMIC0_SWA_VOLTAGE_SETTING = 0x1052, + SET_PMIC0_SWA_VOLTAGE_RANGE_SELECT = 0x1053, + SET_PMIC0_SWA_VOLTAGE_OFFSET = 0x1054, + SET_PMIC0_SWA_SEQUENCE_DELAY = 0x1055, + SET_PMIC0_SWA_SEQUENCE_ORDER = 0X1056, + + SET_PMIC0_SWB_VOLTAGE_SETTING = 0x1057, + SET_PMIC0_SWB_VOLTAGE_RANGE_SELECT = 0x1058, + SET_PMIC0_SWB_VOLTAGE_OFFSET = 0x1059, + SET_PMIC0_SWB_SEQUENCE_DELAY = 0x105A, + SET_PMIC0_SWB_SEQUENCE_ORDER = 0X105B, + + SET_PMIC0_SWC_VOLTAGE_SETTING = 0x105C, + SET_PMIC0_SWC_VOLTAGE_RANGE_SELECT = 0x105D, + SET_PMIC0_SWC_VOLTAGE_OFFSET = 0x105E, + SET_PMIC0_SWC_SEQUENCE_DELAY = 0x105F, + SET_PMIC0_SWC_SEQUENCE_ORDER = 0X1060, + + SET_PMIC0_SWD_VOLTAGE_SETTING = 0x1061, + SET_PMIC0_SWD_VOLTAGE_RANGE_SELECT = 0x1062, + SET_PMIC0_SWD_VOLTAGE_OFFSET = 0x1063, + SET_PMIC0_SWD_SEQUENCE_DELAY = 0x1064, + SET_PMIC0_SWD_SEQUENCE_ORDER = 0X1065, + + SET_PMIC1_SWA_VOLTAGE_SETTING = 0x1066, + SET_PMIC1_SWA_VOLTAGE_RANGE_SELECT = 0x1067, + SET_PMIC1_SWA_VOLTAGE_OFFSET = 0x1068, + SET_PMIC1_SWA_SEQUENCE_DELAY = 0x1069, + SET_PMIC1_SWA_SEQUENCE_ORDER = 0X106A, + + SET_PMIC1_SWB_VOLTAGE_SETTING = 0x106B, + SET_PMIC1_SWB_VOLTAGE_RANGE_SELECT = 0x106C, + SET_PMIC1_SWB_VOLTAGE_OFFSET = 0x106D, + SET_PMIC1_SWB_SEQUENCE_DELAY = 0x106E, + SET_PMIC1_SWB_SEQUENCE_ORDER = 0X106F, + + SET_PMIC1_SWC_VOLTAGE_SETTING = 0x1070, + SET_PMIC1_SWC_VOLTAGE_RANGE_SELECT = 0x1071, + SET_PMIC1_SWC_VOLTAGE_OFFSET = 0x1072, + SET_PMIC1_SWC_SEQUENCE_DELAY = 0x1073, + SET_PMIC1_SWC_SEQUENCE_ORDER = 0X1074, + + SET_PMIC1_SWD_VOLTAGE_SETTING = 0x1075, + SET_PMIC1_SWD_VOLTAGE_RANGE_SELECT = 0x1076, + SET_PMIC1_SWD_VOLTAGE_OFFSET = 0x1077, + SET_PMIC1_SWD_SEQUENCE_DELAY = 0x1078, + SET_PMIC1_SWD_SEQUENCE_ORDER = 0X1079, + + SET_PMIC0_PHASE_COMB = 0x107A, + SET_PMIC1_PHASE_COMB = 0x107B, + + SET_PMIC0_MFG_ID = 0x107C, + SET_PMIC1_MFG_ID = 0x107D, + + SET_PMIC0_SEQUENCE = 0x107E, + SET_PMIC1_SEQUENCE = 0x107F, +}; + +/// +/// @brief constants for PMIC procedures +/// +/// @tparam P product ID (jedec, etc.) +/// +template<mss::pmic::product P> +struct consts; + +/// +/// @brief constants for JEDEC_COMPLIANT PMICS +/// +template<> +struct consts<mss::pmic::product::JEDEC_COMPLIANT> +{ + static constexpr uint8_t RANGE_0 = 0; + static constexpr uint8_t RANGE_1 = 1; + static constexpr uint8_t NUM_UNIQUE_PMICS = 2; // PMIC0/2, PMIC1/3 + static constexpr uint8_t NUMBER_OF_RAILS = 4; + + static constexpr uint8_t VENDOR_PASSWORD_LOW = 0x73; + static constexpr uint8_t VENDOR_PASSWORD_HIGH = 0x94; + static constexpr uint8_t UNLOCK_VENDOR_REGION = 0x40; + static constexpr uint8_t LOCK_VENDOR_REGION = 0x00; + static constexpr uint8_t BURN_R40_TO_R4F = 0x81; + static constexpr uint8_t BURN_R50_TO_R5F = 0x82; + static constexpr uint8_t BURN_R60_TO_R6F = 0x85; // TI spec says 0x83, is that a deviation or a typo? + static constexpr uint8_t BURN_COMPLETE = 0x5A; + + static constexpr uint8_t PROGRAMMABLE_MODE = 0x01; + static constexpr uint8_t SECURE_MODE = 0x00; + + static constexpr uint8_t SINGLE_PHASE = 0x0; + static constexpr uint8_t DUAL_PHASE = 0x1; + + static constexpr uint8_t PWR_GOOD = 0x0; + static constexpr uint8_t PWR_NOT_GOOD = 0x1; + + // Sequencing + static constexpr uint8_t DELAY_LIMIT = 0b1000; + + // Despite the SPD max of 1000, the PMIC can only really support this value + static constexpr uint8_t ORDER_LIMIT = 0b0101; + + // Offset voltage from spd (+/-) + static constexpr uint8_t OFFSET_PLUS = 0; + static constexpr uint8_t OFFSET_MINUS = 1; + + // Shift left 1 to match buffer position + static constexpr uint8_t SHIFT_VOLTAGE_FOR_REG = 1; + + static constexpr uint8_t NUM_RANGES = 2; // RANGE0 and RANGE1 + static constexpr uint8_t MAX_VOLT_BITMAP = 0b01111111; + static constexpr uint8_t MAX_DELAY_BITMAP = 0b00000111; + static constexpr uint8_t CONVERT_RANGE1_TO_RANGE0 = 40; + + // Values below are in millivolts (mV) + static constexpr uint32_t SWABC_VOLT_RANGE0_MIN = 800; + static constexpr uint32_t SWABC_VOLT_RANGE0_MAX = 1435; + static constexpr uint32_t SWABC_VOLT_RANGE1_MIN = 600; + static constexpr uint32_t SWABC_VOLT_RANGE1_MAX = 1235; + + static constexpr uint32_t SWD_VOLT_RANGE0_MIN = 1500; + static constexpr uint32_t SWD_VOLT_RANGE0_MAX = 2135; + static constexpr uint32_t SWD_VOLT_RANGE1_MIN = 2200; + static constexpr uint32_t SWD_VOLT_RANGE1_MAX = 2835; + + static constexpr uint32_t VOLT_STEP = 5; +}; + +namespace i2c +{ + +/// +/// @brief common PMIC sizes +/// +enum sizes +{ + DATA_LENGTH = 1, +}; + +} // i2c +} // pmic +} // mss + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C new file mode 100644 index 000000000..26ea9e7ef --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C @@ -0,0 +1,615 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_enable_utils.C +/// @brief Utility functions for PMIC enable operation +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 1 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/i2c/i2c_pmic.H> +#include <lib/utils/pmic_enable_utils.H> +#include <lib/utils/pmic_consts.H> +#include <lib/utils/pmic_common_utils.H> +#include <pmic_regs.H> +#include <pmic_regs_fld.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/index.H> +#include <generic/memory/lib/utils/find.H> +#include <mss_pmic_attribute_getters.H> +#include <mss_generic_attribute_getters.H> + +namespace mss +{ +namespace pmic +{ + +/// +/// @breif set VR enable bit for system startup via R32 (not broadcast) +/// +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode start_vr_enable( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using REGS = pmicRegs<J>; + using FIELDS = pmicFields<J>; + + + fapi2::buffer<uint8_t> l_programmable_mode_buffer; + fapi2::buffer<uint8_t> l_vr_enable_buffer; + + // Enable programmable mode + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R2F, l_programmable_mode_buffer), + "start_vr_enable: Error reading address 0x%02hhX of %s to enable programmable mode operation", + REGS::R2F, mss::c_str(i_pmic_target)); + + l_programmable_mode_buffer.writeBit<FIELDS::R2F_SECURE_MODE>( + mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>::PROGRAMMABLE_MODE); + + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R2F, l_programmable_mode_buffer), + "start_vr_enable: Error writing address 0x%02hhX of %s to enable programmable mode operation", + REGS::R2F, mss::c_str(i_pmic_target)); + + // Start VR Enable + // Write 1 to R2F(2) + l_vr_enable_buffer.setBit<FIELDS::R32_VR_ENABLE>(); + + FAPI_INF("Executing VR_ENABLE for PMIC %s", mss::c_str(i_pmic_target)); + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R32, l_vr_enable_buffer), + "start_vr_enable: Could not write to address 0x%02hhX of %s to execute VR Enable", + REGS::R32, + mss::c_str(i_pmic_target)); + + // At this point, the PWR_GOOD pin should begin to rise to high. This can't directly be checked via a register + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief bias PMIC with spd settings for phase combination (SWA, SWB or SWA+SWB) +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target - DIMM target of PMIC +/// @param[in] i_id - PMIC0 or PMIC1 +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_phase_comb( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using FIELDS = pmicFields<J>; + using REGS = pmicRegs<J>; + + uint8_t l_phase_comb = 0; + fapi2::buffer<uint8_t> l_phase; + FAPI_TRY(mss::pmic::get_phase_comb[i_id](i_dimm_target, l_phase_comb)); + + // Read, replace bit, and then re-write + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R4F, l_phase)); + l_phase.writeBit<FIELDS::SWA_SWB_PHASE_MODE_SELECT>(l_phase_comb); + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R4F, l_phase)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief bias PMIC with SPD settings for voltage ranges +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target dimm target of PMIC +/// @param[in] i_id PMIC0 or PMIC1 +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_volt_ranges( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using FIELDS = pmicFields<J>; + using REGS = pmicRegs<J>; + + uint8_t l_swa_range = 0; + uint8_t l_swb_range = 0; + uint8_t l_swc_range = 0; + uint8_t l_swd_range = 0; + + fapi2::buffer<uint8_t> l_volt_range_buffer; + + FAPI_TRY(mss::pmic::get_swa_voltage_range_select[i_id](i_dimm_target, l_swa_range)); + FAPI_TRY(mss::pmic::get_swb_voltage_range_select[i_id](i_dimm_target, l_swb_range)); + FAPI_TRY(mss::pmic::get_swc_voltage_range_select[i_id](i_dimm_target, l_swc_range)); + FAPI_TRY(mss::pmic::get_swd_voltage_range_select[i_id](i_dimm_target, l_swd_range)); + + // Read in what the register has, as to not overwrite any default values + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R2B, l_volt_range_buffer)); + + // Set the buffer bits appropriately + l_volt_range_buffer.writeBit<FIELDS::SWA_VOLTAGE_RANGE>(l_swa_range); + l_volt_range_buffer.writeBit<FIELDS::SWB_VOLTAGE_RANGE>(l_swb_range); + l_volt_range_buffer.writeBit<FIELDS::SWC_VOLTAGE_RANGE>(l_swc_range); + l_volt_range_buffer.writeBit<FIELDS::SWD_VOLTAGE_RANGE>(l_swd_range); + + // Write back to PMIC + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R2B, l_volt_range_buffer)); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// +/// @brief bias PMIC with SPD settings for startup sequence +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target dimm target of PMIC +/// @param[in] i_id PMIC0 or PMIC1 +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_startup_seq( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using REGS = pmicRegs<J>; + using CONSTS = mss::pmic::consts<J>; + + // Arrays to key off of rail and PMIC ID + static const pmic_attr_ptr* l_get_sequence_order[] = {mss::pmic::get_swa_sequence_order, + mss::pmic::get_swb_sequence_order, + mss::pmic::get_swc_sequence_order, + mss::pmic::get_swd_sequence_order + }; + + static const pmic_attr_ptr* l_get_sequence_delay[] = {mss::pmic::get_swa_sequence_delay, + mss::pmic::get_swb_sequence_delay, + mss::pmic::get_swc_sequence_delay, + mss::pmic::get_swd_sequence_delay + }; + + static const std::vector<uint8_t> SEQUENCE_REGS = + { + 0, // 0 would imply no sequence config (won't occur due to assert in bias_with_spd_startup_seq) + REGS::R40_POWER_ON_SEQUENCE_CONFIG_1, + REGS::R41_POWER_ON_SEQUENCE_CONFIG_2, + REGS::R42_POWER_ON_SEQUENCE_CONFIG_3, + REGS::R43_POWER_ON_SEQUENCE_CONFIG_4 + }; + + // Arrays to store the attribute data + uint8_t l_sequence_orders[CONSTS::NUMBER_OF_RAILS]; + uint8_t l_sequence_delays[CONSTS::NUMBER_OF_RAILS]; + + // Loop through each rail to populate the order and delay arrays + for (uint8_t l_rail_index = mss::pmic::rail::SWA; l_rail_index <= mss::pmic::rail::SWD; ++l_rail_index) + { + // We know after these FAPI_TRY's that all 4 entries must be populated, else the TRYs fail + FAPI_TRY(((l_get_sequence_order[l_rail_index][i_id]))(i_dimm_target, l_sequence_orders[l_rail_index])); + FAPI_TRY(((l_get_sequence_delay[l_rail_index][i_id]))(i_dimm_target, l_sequence_delays[l_rail_index])); + + // The SPD allows for up to 8 sequences, but there are only 4 on the PMIC. The SPD defaults never go higher than 2. + // We put this check in here as with anything over 4, we don't really know what we can do. + FAPI_ASSERT(((l_sequence_orders[l_rail_index] < CONSTS::ORDER_LIMIT)), + fapi2::PMIC_ORDER_OUT_OF_RANGE() + .set_TARGET(i_pmic_target) + .set_RAIL(l_rail_index) + .set_ORDER(l_sequence_orders[l_rail_index]), + "PMIC sequence order specified by the SPD was out of range for PMIC: %s Rail: %s Order: %u", + mss::c_str(i_pmic_target), + PMIC_RAIL_NAMES[l_rail_index], + l_sequence_orders[l_rail_index]); + } + + { + fapi2::buffer<uint8_t> l_power_on_sequence_config; + uint8_t l_highest_sequence = 0; + + // Zero out sequence registers first + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R40_POWER_ON_SEQUENCE_CONFIG_1, l_power_on_sequence_config)); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R41_POWER_ON_SEQUENCE_CONFIG_2, l_power_on_sequence_config)); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R42_POWER_ON_SEQUENCE_CONFIG_3, l_power_on_sequence_config)); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, REGS::R43_POWER_ON_SEQUENCE_CONFIG_4, l_power_on_sequence_config)); + + // Set the registers appropriately. We kind of need to do this greedy algorithm here since + // the SPD has fields of sequence per rail, the PMIC wants rails per sequence. + // 1. For each rail, set that bit in the corresponding sequence, and enable that sequence + // 2. Set that rail bit for each of the following sequences + // 3. Record the highest sequence used throughout the run + // 4. Clear out registers of sequences higher than the highest used (clear the set rail bits) + // We do this because for each rail, we may not know what the highest sequence will be yet. + // It makes the most sense to assume all sequences, then clear those that aren't used. + for (uint8_t l_rail_index = mss::pmic::rail::SWA; l_rail_index <= mss::pmic::rail::SWD; ++l_rail_index) + { + static constexpr uint8_t NO_SEQUENCE = 0; + const uint8_t l_rail_sequence = l_sequence_orders[l_rail_index]; + + if (l_rail_sequence != NO_SEQUENCE) // If 0, it will not be sequenced + { + // Update the new highest working sequence + l_highest_sequence = std::max(l_rail_sequence, l_highest_sequence); + // Set the register contents appropriately + FAPI_TRY(mss::pmic::set_startup_seq_register(i_pmic_target, l_rail_index, + l_rail_sequence, l_sequence_delays[l_rail_index])); + } + + // else, zero, do nothing. + } + + // Now erase the registers that are higher than our highest sequence (in order to satisfy note 2 + // for registers R40 - R43): + // - 2. If bit [7] = ‘0’, bits [6:3] must be programmed as ‘0000’. If bit [7] = ‘1’, + // - at least one of the bits [6:3] must be programmed as ‘1’. + for (++l_highest_sequence; l_highest_sequence < SEQUENCE_REGS.size(); ++l_highest_sequence) + { + fapi2::buffer<uint8_t> l_clear; + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, SEQUENCE_REGS[l_highest_sequence], l_power_on_sequence_config)); + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Set the startup seq register with the given parameters +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_rail rail to +/// @param[in] i_round sequence round 1-4 +/// @param[in] i_delay delay after round +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode set_startup_seq_register( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const uint8_t i_rail, + const uint8_t i_round, + const uint8_t i_delay) +{ + static constexpr auto J = mss::pmic::product::JEDEC_COMPLIANT; + using REGS = pmicRegs<J>; + using FIELDS = pmicFields<J>; + using CONSTS = mss::pmic::consts<J>; + + // PMIC registers are indexed [7:0], so from the buffer point of view, our bit fields need to be flipped + static constexpr uint8_t RIGHT_ALIGN_OFFSET = 7; + + // Starts at bit 0 (right aligned) with length 3. So we need to take length 3 from bit 5 in our buffer + static constexpr uint8_t DELAY_START = 5; + + static const std::vector<uint8_t> SEQUENCE_REGS = + { + 0, // 0 would imply no sequence config (won't occur due to assert in bias_with_spd_startup_seq) + REGS::R40_POWER_ON_SEQUENCE_CONFIG_1, + REGS::R41_POWER_ON_SEQUENCE_CONFIG_2, + REGS::R42_POWER_ON_SEQUENCE_CONFIG_3, + REGS::R43_POWER_ON_SEQUENCE_CONFIG_4 + }; + + // Manual reversing of sequence bits + static const std::vector<uint8_t> SEQUENCE_BITS = + { + RIGHT_ALIGN_OFFSET - FIELDS::SEQUENCE_SWA_ENABLE, + RIGHT_ALIGN_OFFSET - FIELDS::SEQUENCE_SWB_ENABLE, + RIGHT_ALIGN_OFFSET - FIELDS::SEQUENCE_SWC_ENABLE, + RIGHT_ALIGN_OFFSET - FIELDS::SEQUENCE_SWD_ENABLE + }; + + fapi2::buffer<uint8_t> l_power_on_sequence_config; + + // Check and make sure the given delay is less than the bitmask (else, we overflow later on) + FAPI_ASSERT(i_delay <= CONSTS::MAX_DELAY_BITMAP, + fapi2::PMIC_DELAY_OUT_OF_RANGE() + .set_TARGET(i_pmic_target) + .set_RAIL(i_rail) + .set_DELAY(i_delay), + "PMIC sequence delay from the SPD attribute was out of range for PMIC: %s Rail: %s Delay: %u Max: %u", + mss::c_str(i_pmic_target), + PMIC_RAIL_NAMES[i_rail], + i_delay, + CONSTS::MAX_DELAY_BITMAP); + + // PMIC registers are indexed [7:0], so from the buffer point of view, our bit fields need to be flipped + static constexpr uint8_t SEQUENCE_ENABLE_REVERSED = (RIGHT_ALIGN_OFFSET - FIELDS::SEQUENCE_ENABLE); + + FAPI_TRY(mss::pmic::i2c::reg_read(i_pmic_target, SEQUENCE_REGS[i_round], l_power_on_sequence_config)); + + // Adding on the sequence delays (which are the far right 3 bits). + + // Note: The SPD has sequence delays per rail NOT per sequence (PMIC is by sequence). Here, + // if two rails on the same sequence have different delays, the last rail's delay (ex. SWD) will take precedence. + // In other words, they will be made to match. Otherwise, the SPD is flawed. + l_power_on_sequence_config.clearBit<DELAY_START, FIELDS::DELAY_FLD_LENGTH>(); + l_power_on_sequence_config = l_power_on_sequence_config + i_delay; + + FAPI_TRY(l_power_on_sequence_config.setBit(SEQUENCE_BITS[i_rail])); + FAPI_TRY(l_power_on_sequence_config.setBit(SEQUENCE_ENABLE_REVERSED)); + + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, SEQUENCE_REGS[i_round], l_power_on_sequence_config)); + + // The startup sequence registers after the provided one must set the bits of the rail we just enabled in + // the current sequence. So here, we iterate through the remaining sequences and set those bits. + // since we don't know the information about all the rails within this one function (others may be + // set in later calls to this function) we will set these for each sequence register now, and then + // clear them out later when we know exactly which sequences will be enabled and which ones won't + for (uint8_t l_round_modify = i_round; l_round_modify < SEQUENCE_REGS.size(); ++l_round_modify) + { + l_power_on_sequence_config.flush<0>(); + FAPI_TRY(mss::pmic::i2c::reg_read(i_pmic_target, SEQUENCE_REGS[l_round_modify], l_power_on_sequence_config)); + FAPI_TRY(l_power_on_sequence_config.setBit(SEQUENCE_BITS[i_rail])); + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, SEQUENCE_REGS[l_round_modify], l_power_on_sequence_config)); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Order PMICs by sequence defined in the SPD +/// +/// @param[in] i_dimm DIMM target to pull SPD fields from +/// @param[in] i_dimm_index index of the DIMM target +/// @param[in] i_pmics_per_dimm number of PMICs per dimm +/// @param[in,out] io_pmics vector of PMICs that will be re-ordered in place +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode order_pmics_by_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_DIMM> i_dimm, + const uint8_t i_dimm_index, + const uint8_t i_pmics_per_dimm, + std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& io_pmics) +{ + const auto l_begin_offset = i_dimm_index * i_pmics_per_dimm; + const auto l_iterator_begin = io_pmics.begin() + l_begin_offset; + const auto l_iterator_end = l_iterator_begin + i_pmics_per_dimm; + + fapi2::ReturnCode l_rc_0_out = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc_1_out = fapi2::FAPI2_RC_SUCCESS; + + std::sort(l_iterator_begin, l_iterator_end, [&l_rc_0_out, &l_rc_1_out, i_dimm] ( + const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& l_first_pmic, + const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& l_second_pmic) -> bool + { + // Here we should only be dealing with PMICs of the same DIMM. So we can just check the first one which dimm we're on + uint8_t l_sequence_pmic_0 = 0; + uint8_t l_sequence_pmic_1 = 0; + + // Need to pull out the RC's manually. Goto's in lambdas apparently don't play nicely + fapi2::ReturnCode l_rc_0 = mss::pmic::get_sequence[mss::index(l_first_pmic)](i_dimm, l_sequence_pmic_0); + fapi2::ReturnCode l_rc_1 = mss::pmic::get_sequence[mss::index(l_second_pmic)](i_dimm, l_sequence_pmic_1); + + // Hold on to an error if we see one + if (l_rc_0 != fapi2::FAPI2_RC_SUCCESS) + { + l_rc_0_out = l_rc_0; + } + if (l_rc_1 != fapi2::FAPI2_RC_SUCCESS) + { + l_rc_1_out = l_rc_1; + } + + return l_sequence_pmic_0 < l_sequence_pmic_1; + }); + + FAPI_TRY(l_rc_0_out, "Error getting sequencing attributes for PMICs associated with DIMM 0 target %s", + mss::c_str(i_dimm)); + FAPI_TRY(l_rc_1_out, "Error getting sequencing attributes for PMICs associated with DIMM 1 target %s", + mss::c_str(i_dimm)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Enable pmics using manual mode (direct VR enable, no SPD fields) +/// @param[in] i_pmics vector of PMICs to enable +/// @return FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode enable_manual(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics) +{ + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>; + + for (const auto& l_pmic : i_pmics) + { + fapi2::buffer<uint8_t> l_programmable_mode; + l_programmable_mode.writeBit<FIELDS::R2F_SECURE_MODE>(CONSTS::PROGRAMMABLE_MODE); + + FAPI_INF("Enabling PMIC %s with default settings", mss::c_str(l_pmic)); + + // Make sure power is applied and we can read the PMIC + FAPI_TRY(mss::pmic::poll_for_pbulk_good(l_pmic), + "pmic_enable: poll for pbulk good either failed, or returned not good status on PMIC %s", + mss::c_str(l_pmic)); + + // Enable programmable mode + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(l_pmic, REGS::R2F, l_programmable_mode)); + + // Start VR Enable + FAPI_TRY(mss::pmic::start_vr_enable(l_pmic), + "Error starting VR_ENABLE on PMIC %s", mss::c_str(l_pmic)); + } + +fapi_try_exit: + return fapi2::current_err; +} +/// +/// @brief Function to enable 1U and 2U pmics +/// +/// @param[in] i_pmic_target - the pmic target +/// @param[in] i_dimm_target - the dimm target that the PMIC resides on +/// @param[in] i_vendor_id - the vendor ID of the PMIC to bias +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS if successful +/// +fapi2::ReturnCode enable_chip_1U_2U(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_dimm_target, + const uint16_t i_vendor_id) +{ + FAPI_INF("Setting PMIC %s settings from SPD", mss::c_str(i_pmic_target)); + + // Make sure it is TI or IDT + FAPI_ASSERT((i_vendor_id == mss::pmic::vendor::IDT || + i_vendor_id == mss::pmic::vendor::TI), + fapi2::PMIC_CHIP_NOT_RECOGNIZED() + .set_TARGET(i_pmic_target) + .set_VENDOR_ID(i_vendor_id), + "Unknown PMIC: %s with vendor ID 0x%04hhX", + mss::c_str(i_pmic_target), + uint8_t(i_vendor_id) ); + + if (i_vendor_id == mss::pmic::vendor::IDT) + { + FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::IDT>(i_pmic_target, i_dimm_target), + "enable_chip<IDT, 1U/2U>: Error biasing PMIC %s with SPD settings", + mss::c_str(i_pmic_target)); + } + else // assert done in pmic_enable.C that vendor is IDT or TI + { + FAPI_TRY(mss::pmic::bias_with_spd_settings<mss::pmic::vendor::TI>(i_pmic_target, i_dimm_target), + "enable_chip<TI, 1U/2U>: Error biasing PMIC %s with SPD settings", + mss::c_str(i_pmic_target)); + } + + // Start VR Enable + FAPI_TRY(mss::pmic::start_vr_enable(i_pmic_target), + "Error starting VR_ENABLE on PMIC %s", mss::c_str(i_pmic_target)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Disable PMICs and clear status bits in preparation for enable +/// +/// @param[in] i_pmics vector of PMIC targets +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode disable_and_reset_pmics(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics) +{ + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using FIELDS = pmicFields<mss::pmic::product::JEDEC_COMPLIANT>; + + for (const auto& l_pmic : i_pmics) + { + // First, disable + { + fapi2::buffer<uint8_t> l_reg_contents; + + // Redundant clearBit, but just so it's clear what we're doing + l_reg_contents.clearBit<FIELDS::R32_VR_ENABLE>(); + + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(l_pmic, REGS::R32, l_reg_contents)); + } + + // Now that it's disabled, let's clear the status bits so errors don't hang over into the next enable + { + FAPI_TRY(mss::pmic::status::clear(l_pmic)); + } + } + +fapi_try_exit: + return fapi2::current_err; +} +/// +/// @brief Enable PMIC for SPD mode +/// +/// @param[in] i_pmics vector of PMICs sorted by mss::index +/// @param[in] i_dimms const vector of DIMMs sorted by mss::index +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode pmic_enable_SPD( + std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics, + const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimms) +{ + uint8_t l_module_height = 0; + FAPI_TRY(mss::attr::get_dram_module_height(i_dimms[0], l_module_height)); + + FAPI_ASSERT(l_module_height == fapi2::ENUM_ATTR_MEM_EFF_DRAM_MODULE_HEIGHT_1U || + l_module_height == fapi2::ENUM_ATTR_MEM_EFF_DRAM_MODULE_HEIGHT_2U, + fapi2::PMIC_DIMM_SPD_UNSUPPORTED_MODULE_HEIGHT() + .set_TARGET(i_dimms[0]) + .set_VALUE(l_module_height), + "DIMM %s module height attribute not identified as 1U or 2U. " + "ENUM_ATTR_MEM_EFF_DRAM_MODULE_HEIGHT of %u . Not supported yet.", + mss::c_str(i_dimms[0]), l_module_height); + + // Now we know there are 2 pmics per dimm (for DDIMM only... TK will change with future refactor) + static constexpr uint8_t PMICS_PER_DIMM = 2; + + for (uint8_t l_dimm_index = 0; l_dimm_index < i_dimms.size(); ++l_dimm_index) + { + // The PMICs are in sorted order + const auto& l_dimm = i_dimms[l_dimm_index]; + FAPI_TRY(mss::pmic::order_pmics_by_sequence(l_dimm, l_dimm_index, PMICS_PER_DIMM, i_pmics)); + + // Now the PMICs are in the right order of DIMM and the right order by their defined SPD sequence within each dimm + // Let's kick off the enables + for (const auto& l_pmic : i_pmics) + { + // Get the corresponding DIMM target to feed to the helpers + const auto& l_dimm = i_dimms[mss::index(l_pmic) / PMICS_PER_DIMM]; + uint16_t l_vendor_id = 0; + + // Get vendor ID + FAPI_TRY(mss::pmic::get_mfg_id[mss::index(l_pmic)](l_dimm, l_vendor_id)); + + // Poll to make sure PBULK reports good, then we can enable the chip and write/read registers + FAPI_TRY(mss::pmic::poll_for_pbulk_good(l_pmic), + "pmic_enable: poll for pbulk good either failed, or returned not good status on PMIC %s", + mss::c_str(l_pmic)); + + // Call the enable procedure + FAPI_TRY((mss::pmic::enable_chip_1U_2U(l_pmic, l_dimm, l_vendor_id)), + "pmic_enable: Error enabling PMIC %s", mss::c_str(l_pmic)); + } + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} +} // pmic +} // mss diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H new file mode 100644 index 000000000..9220993b5 --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H @@ -0,0 +1,788 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_enable_utils.H +/// @brief Utility functions for PMIC enable operation +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __PMIC_ENABLE_UTILS_H__ +#define __PMIC_ENABLE_UTILS_H__ + +#include <fapi2.H> +#include <pmic_regs.H> +#include <pmic_regs_fld.H> +#include <lib/i2c/i2c_pmic.H> +#include <lib/utils/pmic_common_utils.H> +#include <lib/utils/pmic_consts.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/index.H> +#include <mss_pmic_attribute_getters.H> +#include <mss_pmic_attribute_setters.H> + +namespace mss +{ +namespace pmic +{ +/// @brief pointer to PMIC attribute getters for DIMM target +typedef fapi2::ReturnCode (*pmic_attr_ptr)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value); +typedef fapi2::ReturnCode (*pmic_attr_ptr_signed)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + int8_t& o_value); +// Pointers below allow for run-time attribute getter selection by PMIC ID (0,1) + +// PMIC0/1 sequence order +static constexpr pmic_attr_ptr get_sequence[] = +{ + mss::attr::get_pmic0_sequence, + mss::attr::get_pmic1_sequence +}; + +// Voltage Setting +static constexpr pmic_attr_ptr get_swa_voltage_setting[] = +{ + mss::attr::get_pmic0_swa_voltage_setting, + mss::attr::get_pmic1_swa_voltage_setting +}; +static constexpr pmic_attr_ptr get_swb_voltage_setting[] = +{ + mss::attr::get_pmic0_swb_voltage_setting, + mss::attr::get_pmic1_swb_voltage_setting +}; +static constexpr pmic_attr_ptr get_swc_voltage_setting[] = +{ + mss::attr::get_pmic0_swc_voltage_setting, + mss::attr::get_pmic1_swc_voltage_setting +}; +static constexpr pmic_attr_ptr get_swd_voltage_setting[] = +{ + mss::attr::get_pmic0_swd_voltage_setting, + mss::attr::get_pmic1_swd_voltage_setting +}; + +// Voltage Range Select +static constexpr pmic_attr_ptr get_swa_voltage_range_select[] = +{ + mss::attr::get_pmic0_swa_voltage_range_select, + mss::attr::get_pmic1_swa_voltage_range_select +}; +static constexpr pmic_attr_ptr get_swb_voltage_range_select[] = +{ + mss::attr::get_pmic0_swb_voltage_range_select, + mss::attr::get_pmic1_swb_voltage_range_select +}; +static constexpr pmic_attr_ptr get_swc_voltage_range_select[] = +{ + mss::attr::get_pmic0_swc_voltage_range_select, + mss::attr::get_pmic1_swc_voltage_range_select +}; +static constexpr pmic_attr_ptr get_swd_voltage_range_select[] = +{ + mss::attr::get_pmic0_swd_voltage_range_select, + mss::attr::get_pmic1_swd_voltage_range_select +}; + +// Voltage Offset +static constexpr pmic_attr_ptr_signed get_swa_voltage_offset[] = +{ + mss::attr::get_pmic0_swa_voltage_offset, + mss::attr::get_pmic1_swa_voltage_offset +}; +static constexpr pmic_attr_ptr_signed get_swb_voltage_offset[] = +{ + mss::attr::get_pmic0_swb_voltage_offset, + mss::attr::get_pmic1_swb_voltage_offset +}; +static constexpr pmic_attr_ptr_signed get_swc_voltage_offset[] = +{ + mss::attr::get_pmic0_swc_voltage_offset, + mss::attr::get_pmic1_swc_voltage_offset +}; +static constexpr pmic_attr_ptr_signed get_swd_voltage_offset[] = +{ + mss::attr::get_pmic0_swd_voltage_offset, + mss::attr::get_pmic1_swd_voltage_offset +}; + +// Sequence Delay +static constexpr pmic_attr_ptr get_swa_sequence_delay[] = +{ + mss::attr::get_pmic0_swa_sequence_delay, + mss::attr::get_pmic1_swa_sequence_delay +}; +static constexpr pmic_attr_ptr get_swb_sequence_delay[] = +{ + mss::attr::get_pmic0_swb_sequence_delay, + mss::attr::get_pmic1_swb_sequence_delay +}; +static constexpr pmic_attr_ptr get_swc_sequence_delay[] = +{ + mss::attr::get_pmic0_swc_sequence_delay, + mss::attr::get_pmic1_swc_sequence_delay +}; +static constexpr pmic_attr_ptr get_swd_sequence_delay[] = +{ + mss::attr::get_pmic0_swd_sequence_delay, + mss::attr::get_pmic1_swd_sequence_delay +}; + +// Sequence Order +static constexpr pmic_attr_ptr get_swa_sequence_order[] = +{ + mss::attr::get_pmic0_swa_sequence_order, + mss::attr::get_pmic1_swa_sequence_order +}; +static constexpr pmic_attr_ptr get_swb_sequence_order[] = +{ + mss::attr::get_pmic0_swb_sequence_order, + mss::attr::get_pmic1_swb_sequence_order +}; +static constexpr pmic_attr_ptr get_swc_sequence_order[] = +{ + mss::attr::get_pmic0_swc_sequence_order, + mss::attr::get_pmic1_swc_sequence_order +}; +static constexpr pmic_attr_ptr get_swd_sequence_order[] = +{ + mss::attr::get_pmic0_swd_sequence_order, + mss::attr::get_pmic1_swd_sequence_order +}; + +// Phase Combination +static constexpr pmic_attr_ptr get_phase_comb[] = +{ + mss::attr::get_pmic0_phase_comb, + mss::attr::get_pmic1_phase_comb +}; + +// EFD Fields + +// Offset +static constexpr pmic_attr_ptr_signed get_efd_swa_voltage_offset[] = +{ + mss::attr::get_efd_pmic0_swa_voltage_offset, + mss::attr::get_efd_pmic1_swa_voltage_offset +}; + +static constexpr pmic_attr_ptr_signed get_efd_swb_voltage_offset[] = +{ + mss::attr::get_efd_pmic0_swb_voltage_offset, + mss::attr::get_efd_pmic1_swb_voltage_offset +}; + +static constexpr pmic_attr_ptr_signed get_efd_swc_voltage_offset[] = +{ + mss::attr::get_efd_pmic0_swc_voltage_offset, + mss::attr::get_efd_pmic1_swc_voltage_offset +}; + +static constexpr pmic_attr_ptr_signed get_efd_swd_voltage_offset[] = +{ + mss::attr::get_efd_pmic0_swd_voltage_offset, + mss::attr::get_efd_pmic1_swd_voltage_offset +}; + +// These arrays allow us to dynamically choose the right attribute getter at runtime based on the rail and mss::pmic::id +static const pmic_attr_ptr* get_volt_setting[] = +{ + mss::pmic::get_swa_voltage_setting, + mss::pmic::get_swb_voltage_setting, + mss::pmic::get_swc_voltage_setting, + mss::pmic::get_swd_voltage_setting +}; + +static const pmic_attr_ptr* get_volt_range_select[] = +{ + mss::pmic::get_swa_voltage_range_select, + mss::pmic::get_swb_voltage_range_select, + mss::pmic::get_swc_voltage_range_select, + mss::pmic::get_swd_voltage_range_select +}; + +static const pmic_attr_ptr_signed* get_volt_offset[] = +{ + mss::pmic::get_swa_voltage_offset, + mss::pmic::get_swb_voltage_offset, + mss::pmic::get_swc_voltage_offset, + mss::pmic::get_swd_voltage_offset +}; + +// EFD Offset + Direction functions +static const pmic_attr_ptr_signed* get_efd_volt_offset[] = +{ + mss::pmic::get_efd_swa_voltage_offset, + mss::pmic::get_efd_swb_voltage_offset, + mss::pmic::get_efd_swc_voltage_offset, + mss::pmic::get_efd_swd_voltage_offset +}; + +// For output traces +static const std::vector<const char*> PMIC_RAIL_NAMES = {"SWA", "SWB", "SWC", "SWD"}; + +// Attribute setter FP type +typedef fapi2::ReturnCode (*pmic_attr_setter_ptr)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t i_value); +typedef fapi2::ReturnCode (*pmic_attr_setter_ptr_signed)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + int8_t i_value); + +// Voltage Setting +static constexpr pmic_attr_setter_ptr set_swa_voltage_setting[] = +{ + mss::attr::set_pmic0_swa_voltage_setting, + mss::attr::set_pmic1_swa_voltage_setting +}; +static constexpr pmic_attr_setter_ptr set_swb_voltage_setting[] = +{ + mss::attr::set_pmic0_swb_voltage_setting, + mss::attr::set_pmic1_swb_voltage_setting +}; +static constexpr pmic_attr_setter_ptr set_swc_voltage_setting[] = +{ + mss::attr::set_pmic0_swc_voltage_setting, + mss::attr::set_pmic1_swc_voltage_setting +}; +static constexpr pmic_attr_setter_ptr set_swd_voltage_setting[] = +{ + mss::attr::set_pmic0_swd_voltage_setting, + mss::attr::set_pmic1_swd_voltage_setting +}; + +// Voltage Range Select +static constexpr pmic_attr_setter_ptr set_swa_voltage_range_select[] = +{ + mss::attr::set_pmic0_swa_voltage_range_select, + mss::attr::set_pmic1_swa_voltage_range_select +}; +static constexpr pmic_attr_setter_ptr set_swb_voltage_range_select[] = +{ + mss::attr::set_pmic0_swb_voltage_range_select, + mss::attr::set_pmic1_swb_voltage_range_select +}; +static constexpr pmic_attr_setter_ptr set_swc_voltage_range_select[] = +{ + mss::attr::set_pmic0_swc_voltage_range_select, + mss::attr::set_pmic1_swc_voltage_range_select +}; +static constexpr pmic_attr_setter_ptr set_swd_voltage_range_select[] = +{ + mss::attr::set_pmic0_swd_voltage_range_select, + mss::attr::set_pmic1_swd_voltage_range_select +}; + +// Voltage Offset +static constexpr pmic_attr_setter_ptr_signed set_swa_voltage_offset[] = +{ + mss::attr::set_pmic0_swa_voltage_offset, + mss::attr::set_pmic1_swa_voltage_offset +}; +static constexpr pmic_attr_setter_ptr_signed set_swb_voltage_offset[] = +{ + mss::attr::set_pmic0_swb_voltage_offset, + mss::attr::set_pmic1_swb_voltage_offset +}; +static constexpr pmic_attr_setter_ptr_signed set_swc_voltage_offset[] = +{ + mss::attr::set_pmic0_swc_voltage_offset, + mss::attr::set_pmic1_swc_voltage_offset +}; +static constexpr pmic_attr_setter_ptr_signed set_swd_voltage_offset[] = +{ + mss::attr::set_pmic0_swd_voltage_offset, + mss::attr::set_pmic1_swd_voltage_offset +}; + +// Sequence Delay +static constexpr pmic_attr_setter_ptr set_swa_sequence_delay[] = +{ + mss::attr::set_pmic0_swa_sequence_delay, + mss::attr::set_pmic1_swa_sequence_delay +}; +static constexpr pmic_attr_setter_ptr set_swb_sequence_delay[] = +{ + mss::attr::set_pmic0_swb_sequence_delay, + mss::attr::set_pmic1_swb_sequence_delay +}; +static constexpr pmic_attr_setter_ptr set_swc_sequence_delay[] = +{ + mss::attr::set_pmic0_swc_sequence_delay, + mss::attr::set_pmic1_swc_sequence_delay +}; +static constexpr pmic_attr_setter_ptr set_swd_sequence_delay[] = +{ + mss::attr::set_pmic0_swd_sequence_delay, + mss::attr::set_pmic1_swd_sequence_delay +}; + +// Sequence Order +static constexpr pmic_attr_setter_ptr set_swa_sequence_order[] = +{ + mss::attr::set_pmic0_swa_sequence_order, + mss::attr::set_pmic1_swa_sequence_order +}; +static constexpr pmic_attr_setter_ptr set_swb_sequence_order[] = +{ + mss::attr::set_pmic0_swb_sequence_order, + mss::attr::set_pmic1_swb_sequence_order +}; +static constexpr pmic_attr_setter_ptr set_swc_sequence_order[] = +{ + mss::attr::set_pmic0_swc_sequence_order, + mss::attr::set_pmic1_swc_sequence_order +}; +static constexpr pmic_attr_setter_ptr set_swd_sequence_order[] = +{ + mss::attr::set_pmic0_swd_sequence_order, + mss::attr::set_pmic1_swd_sequence_order +}; + +// Phase Combination +static constexpr pmic_attr_setter_ptr set_phase_comb[] = +{ + mss::attr::set_pmic0_phase_comb, + mss::attr::set_pmic1_phase_comb +}; + +// Offset +static constexpr pmic_attr_setter_ptr_signed set_efd_swa_voltage_offset[] = +{ + mss::attr::set_efd_pmic0_swa_voltage_offset, + mss::attr::set_efd_pmic1_swa_voltage_offset +}; + +static constexpr pmic_attr_setter_ptr_signed set_efd_swb_voltage_offset[] = +{ + mss::attr::set_efd_pmic0_swb_voltage_offset, + mss::attr::set_efd_pmic1_swb_voltage_offset +}; + +static constexpr pmic_attr_setter_ptr_signed set_efd_swc_voltage_offset[] = +{ + mss::attr::set_efd_pmic0_swc_voltage_offset, + mss::attr::set_efd_pmic1_swc_voltage_offset +}; + +static constexpr pmic_attr_setter_ptr_signed set_efd_swd_voltage_offset[] = +{ + mss::attr::set_efd_pmic0_swd_voltage_offset, + mss::attr::set_efd_pmic1_swd_voltage_offset +}; + +//----------------------------------- +// SPD Biasing functions +//----------------------------------- + +/// +/// @breif set VR enable bit for system startup via R32 (not broadcast) +/// +/// @param[in] i_pmic_target PMIC target +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode start_vr_enable( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target); + +/// +/// @brief bias PMIC0 with spd settings for phase combination (SWA, SWB or SWA+SWB) +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_port - port target of PMIC +/// @param[in] i_dimm_index - DIMM index for PMIC (0,1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_phase_comb( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm, + const mss::pmic::id i_id); + +/// +/// @brief bias with SPD settings for voltage ranges +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_port port target of PMIC +/// @param[in] i_dimm_index DIMM index for PMIC (0,1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_volt_ranges( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm, + const mss::pmic::id i_id); + +/// +/// @brief bias with SPD settings for startup sequence +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_port port target of PMIC +/// @param[in] i_dimm_index DIMM index for PMIC (0,1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode bias_with_spd_startup_seq( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm, + const mss::pmic::id i_id); + +/// +/// @brief Set the startup seq register with the given parameters +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_rail rail to +/// @param[in] i_round sequence round 1-4 +/// @param[in] i_delay delay after round +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +fapi2::ReturnCode set_startup_seq_register( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const uint8_t i_rail, + const uint8_t i_round, + const uint8_t i_delay); + +//----------------------------------- +// Templated SPD Biasing functions +//----------------------------------- + +/// +/// @brief bias with spd settings for voltages +/// +/// @tparam V mss::pmic::vendor (TI/IDT) +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target of PMIC +/// @param[in] i_dimm_index - DIMM index for PMIC (0,1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff no error +/// +template <mss::pmic::vendor V> +fapi2::ReturnCode bias_with_spd_voltages( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id); + +/// +/// @brief Calcuate target voltage for PMIC +/// +/// @param[in] i_dimm_target DIMM target of PMIC (holds the attributes) +/// @param[in] i_id ID of pmic (0,1) +/// @param[in] i_rail RAIL to calculate voltage for +/// @param[out] o_volt_buffer output buffer +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +inline fapi2::ReturnCode calculate_voltage_write_buffer( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id, + const uint8_t i_rail, + fapi2::buffer<uint8_t>& o_volt_buffer) +{ + uint8_t l_volt = 0; + int8_t l_volt_offset = 0; + int8_t l_efd_volt_offset = 0; + + // Get the attributes corresponding to the rail and PMIC indices + FAPI_TRY(get_volt_setting[i_rail][i_id](i_dimm_target, l_volt)); + FAPI_TRY(get_volt_offset[i_rail][i_id](i_dimm_target, l_volt_offset)); + FAPI_TRY(get_efd_volt_offset[i_rail][i_id](i_dimm_target, l_efd_volt_offset)); + + // Set output buffer + o_volt_buffer = l_volt + l_volt_offset + l_efd_volt_offset; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Order PMICs by sequence defined in the SPD +/// +/// @param[in] i_dimm DIMM target to pull SPD fields from +/// @param[in] i_dimm_index index of the DIMM target +/// @param[in] i_pmics_per_dimm number of PMICs per dimm +/// @param[in,out] io_pmics vector of PMICs that will be re-ordered in place +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode order_pmics_by_sequence( + const fapi2::Target<fapi2::TARGET_TYPE_DIMM> i_dimm, + const uint8_t i_dimm_index, + const uint8_t i_pmics_per_dimm, + std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& io_pmics); + +/// +/// @brief Bias with spd voltages for IDT pmic +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target +/// @param[in] i_id relative ID of PMIC (0/1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template <> +inline fapi2::ReturnCode bias_with_spd_voltages<mss::pmic::vendor::IDT>( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id) +{ + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + + for (uint8_t l_rail_index = mss::pmic::rail::SWA; l_rail_index <= mss::pmic::rail::SWD; ++l_rail_index) + { + fapi2::buffer<uint8_t> l_volt_buffer; + FAPI_TRY(calculate_voltage_write_buffer(i_dimm_target, i_id, l_rail_index, l_volt_buffer)); + + // Since we have unsigned integers, this should check both underflow and overflow + FAPI_ASSERT(l_volt_buffer <= CONSTS::MAX_VOLT_BITMAP, + fapi2::PMIC_VOLTAGE_OUT_OF_RANGE() + .set_TARGET(i_pmic_target) + .set_VOLTAGE_BITMAP(l_volt_buffer) + .set_RAIL(mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index]), + "Voltage out of range as determined by SPD voltage +/- offset for %s of %s", + PMIC_RAIL_NAMES[l_rail_index], mss::c_str(i_pmic_target) ); + + l_volt_buffer = l_volt_buffer << CONSTS::SHIFT_VOLTAGE_FOR_REG; + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index], l_volt_buffer), + "Error writing address 0x%02hhX of PMIC %s", mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index], + mss::c_str(i_pmic_target)); + + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Bias with spd voltages for TI pmic +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target +/// @param[in] i_id relative ID of PMIC (0/1) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template <> +inline fapi2::ReturnCode bias_with_spd_voltages<mss::pmic::vendor::TI>( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target, + const mss::pmic::id i_id) +{ + using REGS = pmicRegs<mss::pmic::product::JEDEC_COMPLIANT>; + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + + for (uint8_t l_rail_index = mss::pmic::rail::SWA; l_rail_index <= mss::pmic::rail::SWD; ++l_rail_index) + { + fapi2::buffer<uint8_t> l_volt_buffer; + FAPI_TRY(calculate_voltage_write_buffer(i_dimm_target, i_id, l_rail_index, l_volt_buffer)); + + bool l_overflow = false; + + uint8_t l_volt_range_select = 0; + FAPI_TRY(get_volt_range_select[l_rail_index][i_id](i_dimm_target, l_volt_range_select)); + + // SWD supports a RANGE 1, but NOT SWA-C + if (l_rail_index == mss::pmic::rail::SWD) + { + // Can set range and voltage directly + fapi2::buffer<uint8_t> l_volt_range_buffer; + + // Read in what the register has, as to not overwrite any default values + FAPI_TRY(mss::pmic::i2c::reg_read_reverse_buffer(i_pmic_target, REGS::R2B, l_volt_range_buffer)); + + l_volt_range_buffer.writeBit<FIELDS::SWD_VOLTAGE_RANGE>(l_volt_range_select); + + // Write to PMIC + FAPI_TRY(mss::pmic::i2c::reg_write_reverse_buffer(i_pmic_target, REGS::R2B, l_volt_range_buffer)); + } + else + { + // Check if the range is range 1, in which case we will need to convert to range 0 (thanks TI) + if (l_volt_range_select == CONSTS::RANGE_1) + { + // Convert from RANGE1 -> RANGE0 + + // Since both ranges are 5mV (at least they're supposed to be) + // we can just subtract the difference between range 1 and 0 + // which is 600mV -> 800mV + // 200mV / 5 = 40 + uint8_t l_old_voltage = uint8_t(l_volt_buffer); + l_volt_buffer = l_volt_buffer - CONSTS::CONVERT_RANGE1_TO_RANGE0; + + // Check for overflow (the old voltage should be larger unless we rolled over) + if (l_old_voltage < l_volt_buffer) + { + // Not using an extra xml error for this as overflow implies PMIC_VOLTAGE_OUT_OF_RANGE anyway. + FAPI_ERR("Overflow ocurred when converting SPD Range 1 voltage to TI Range 0"); + l_overflow = true; + } + } + } + + // Check for overflow due to range conversion (SWA-C), but also due to overflow due to offset attributes + FAPI_ASSERT( (!l_overflow) && (l_volt_buffer <= CONSTS::MAX_VOLT_BITMAP), + fapi2::PMIC_VOLTAGE_OUT_OF_RANGE() + .set_TARGET(i_pmic_target) + .set_VOLTAGE_BITMAP(l_volt_buffer) + .set_RAIL(mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index]), + "Voltage out of range as determined by SPD voltage +/- offset for %s of %s", + PMIC_RAIL_NAMES[l_rail_index], mss::c_str(i_pmic_target) ); + + l_volt_buffer = l_volt_buffer << CONSTS::SHIFT_VOLTAGE_FOR_REG; + FAPI_TRY(mss::pmic::i2c::reg_write(i_pmic_target, mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index], l_volt_buffer), + "Error writing address 0x%02hhX of PMIC %s", mss::pmic::VOLT_SETTING_ACTIVE_REGS[l_rail_index], + mss::c_str(i_pmic_target)); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Bias PMIC from SPD settings per vendor +/// +/// @tparam V mss::pmic::vendor (IDT/TI) +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target associated with PMIC +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template <mss::pmic::vendor V> +fapi2::ReturnCode bias_with_spd_settings( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target); + +/// +/// @brief Bias IDT PMIC from SPD settings +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template<> +inline fapi2::ReturnCode bias_with_spd_settings<mss::pmic::vendor::IDT>( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target) +{ + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + // Unlock Vendor Region + FAPI_TRY(mss::pmic::unlock_vendor_region(i_pmic_target), + "Error unlocking vendor region on PMIC %s", mss::c_str(i_pmic_target)); + + { + // PMIC position/ID of the OCMB target. There could be 4 total, but we care about whether its PMIC0(2) or PMIC1(3) + const mss::pmic::id l_relative_pmic_id = static_cast<mss::pmic::id>( + mss::index(i_pmic_target) % CONSTS::NUM_UNIQUE_PMICS); + + // Phase combination + FAPI_TRY(mss::pmic::bias_with_spd_phase_comb(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + + // Voltage ranges + FAPI_TRY(mss::pmic::bias_with_spd_volt_ranges(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + + // Voltages + FAPI_TRY(mss::pmic::bias_with_spd_voltages<mss::pmic::IDT>(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + + // Startup sequence + FAPI_TRY(mss::pmic::bias_with_spd_startup_seq(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + } + +fapi_try_exit: + // Try to lock vendor region even in the case of an error in this function + return mss::pmic::lock_vendor_region(i_pmic_target, fapi2::current_err); +} + +/// +/// @brief Bias TI PMIC from SPD settings +/// +/// @param[in] i_pmic_target PMIC target +/// @param[in] i_dimm_target DIMM target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template<> +inline fapi2::ReturnCode bias_with_spd_settings<mss::pmic::vendor::TI>( + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TargetType::TARGET_TYPE_DIMM>& i_dimm_target) +{ + using CONSTS = mss::pmic::consts<mss::pmic::product::JEDEC_COMPLIANT>; + // Unlock Vendor Region + FAPI_TRY(mss::pmic::unlock_vendor_region(i_pmic_target), + "Error unlocking vendor region on PMIC %s", mss::c_str(i_pmic_target)); + + { + // PMIC position/ID of the OCMB target. There could be 4 total, but we care about whether its PMIC0(2) or PMIC1(3) + const mss::pmic::id l_relative_pmic_id = static_cast<mss::pmic::id>( + mss::index(i_pmic_target) % CONSTS::NUM_UNIQUE_PMICS); + // Phase combination + FAPI_TRY(mss::pmic::bias_with_spd_phase_comb(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + + // Voltages + // TI pmic only has range 0 for SWA-C. We need to convert anything SPD that says range 1 --> range 0 + FAPI_TRY(mss::pmic::bias_with_spd_voltages<mss::pmic::TI>(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + + // Startup sequence + FAPI_TRY(mss::pmic::bias_with_spd_startup_seq(i_pmic_target, i_dimm_target, l_relative_pmic_id)); + } + +fapi_try_exit: + // Try to lock vendor region even in the case of an error in this function + return mss::pmic::lock_vendor_region(i_pmic_target, fapi2::current_err); +} + +//------------------- ENABLE FUNCTIONS-----------------// + +/// +/// @brief Enable pmics using manual mode (direct VR enable, no SPD fields) +/// @param[in] i_pmics vector of PMICs to enable +/// +fapi2::ReturnCode enable_manual(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics); + +/// +/// @brief Function to enable 1U and 2U pmics +/// +/// @param[in] i_pmic_target - the pmic target +/// @param[in] i_dimm_target - the dimm target that the PMIC resides on +/// @param[in] i_vendor_id - the vendor ID of the PMIC to bias +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS if successful +/// +fapi2::ReturnCode enable_chip_1U_2U(const fapi2::Target<fapi2::TARGET_TYPE_PMIC>& i_pmic_target, + const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_dimm_target, + const uint16_t i_vendor_id); + +/// +/// @brief Disable PMICs and clear status bits in preparation for enable +/// +/// @param[in] i_pmics vector of PMIC targets +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode disable_and_reset_pmics(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics); + +/// +/// @brief Enable PMIC for SPD mode +/// +/// @param[in] i_pmics vector of PMICs sorted by mss::index +/// @param[in] i_dimms const vector of DIMMs sorted by mss::index +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode pmic_enable_SPD( + std::vector<fapi2::Target<fapi2::TARGET_TYPE_PMIC>>& i_pmics, + const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimms); +} +} // mss + +#endif diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C new file mode 100644 index 000000000..eaab19cd5 --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pmic_enable.C +/// @brief Procedure definition to enable PMIC +/// +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <pmic_enable.H> +#include <generic/memory/lib/utils/find.H> +#include <lib/utils/pmic_common_utils.H> +#include <lib/utils/pmic_enable_utils.H> +#include <lib/utils/pmic_consts.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/c_str.H> + +extern "C" +{ + /// + /// @brief Enable function for pmic module. Calls appropriate enable func with matching DIMM target + /// @param[in] i_target ocmb target + /// @param[in] i_mode enable mode operation + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode pmic_enable(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_target, + const mss::pmic::enable_mode i_mode) + { + auto l_dimms = mss::find_targets_sorted_by_index<fapi2::TARGET_TYPE_DIMM>(i_ocmb_target); + auto l_pmics = mss::find_targets_sorted_by_index<fapi2::TARGET_TYPE_PMIC>(i_ocmb_target); + + // Check that we have PMICs (we wouldn't on gemini, for example) + if (l_pmics.empty()) + { + FAPI_INF("No PMICs to enable on %s, exiting.", mss::c_str(i_ocmb_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Disable PMICs and clear status bits so we are starting at a known off state + FAPI_TRY(mss::pmic::disable_and_reset_pmics(l_pmics)); + + // // If we're enabling via internal settings, we can just run VR ENABLE down the line + if (i_mode == mss::pmic::enable_mode::MANUAL) + { + FAPI_TRY(mss::pmic::enable_manual(l_pmics)); + } + else + { + if (!l_dimms.empty()) + { + FAPI_TRY(mss::pmic::pmic_enable_SPD(l_pmics, l_dimms)); + } + } + + // Check that all the PMIC statuses are good post-enable + FAPI_TRY(mss::pmic::status::check_all_pmics(i_ocmb_target), + "Bad statuses returned, or error checking statuses of PMICs on %s", mss::c_str(i_ocmb_target)); + + // If we get here, statuses are good + FAPI_INF("All status codes were OK for PMICs on %s", mss::c_str(i_ocmb_target)); + + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; + } + +} // extern C diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.H index c54c11787..e709c7f40 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.H +++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.H $ */ +/* $Source: src/import/chips/ocmb/common/procedures/hwp/pmic/pmic_enable.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,36 +24,48 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file p9a_mss_eff_config_thermal.H -/// @brief Perform thermal calculations as part of the effective configuration +/// @file pmic_enable.H +/// @brief Procedure definition to enable PMIC /// -// *HWP HWP Owner: Andre A. Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Michael Pardeik <pardeik@us.ibm.com> +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB -#ifndef P9A_MSS_EFF_CONFIG_THERMAL_H_ -#define P9A_MSS_EFF_CONFIG_THERMAL_H_ +#ifndef __PMIC_ENABLE_H__ +#define __PMIC_ENABLE_H__ #include <fapi2.H> -#include <vector> -typedef fapi2::ReturnCode (*p9a_mss_eff_config_thermal_FP_t) (const std::vector - <fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>>&); +namespace mss +{ +namespace pmic +{ -extern "C" +/// +/// @brief Different enable operations +/// +enum enable_mode { + SPD = 0, // Use values from the SPD (default). Overwrite the vendor region with SPD settings + MANUAL = 1, // Use voltage settings currently in the vendor region. (Changed via pmic_update, or factory defaults) +}; +} +} + +typedef fapi2::ReturnCode (*pmic_enable_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + const mss::pmic::enable_mode); +extern "C" +{ /// - /// @brief Perform thermal calculations as part of the effective configuration - /// @param[in] i_targets vector of ports (e.g., MEM_PORT) all on the same VDDR domain + /// @brief enable function for pmic module + /// @param[in] i_target ocmb target + /// @param[in] i_mode enable mode operation /// @return FAPI2_RC_SUCCESS iff ok - /// @note sets ATTR_MSS_MEM_WATT_TARGET, ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT and _PER_SLOT, and ATTR_MSS_PORT_MAXPOWER /// - fapi2::ReturnCode p9a_mss_eff_config_thermal( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& - i_targets ); - + fapi2::ReturnCode pmic_enable(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::pmic::enable_mode i_mode = mss::pmic::enable_mode::SPD); } - #endif diff --git a/src/import/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml b/src/import/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml new file mode 100644 index 000000000..a2488a6df --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml @@ -0,0 +1,729 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/common/procedures/xml/attribute_info/pmic_eff_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_MFG_ID</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Manufacturer ID Code + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_mfg_id</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWA Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swa_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWA Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swa_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWA_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWA Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swa_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWA + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swa_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWA_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWA will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swa_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWB Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swb_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWB Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swb_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWB_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWB Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swb_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWB + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swb_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWB_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWB will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swb_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWC Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swc_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWC Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swc_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWC_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWC Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swc_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWC + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swc_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWC_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWC will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swc_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWD Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swd_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWD Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swd_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWD_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWD Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swd_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swd_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SWD_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWD will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_swd_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_MFG_ID</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Manufacturer ID Code + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_mfg_id</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWA Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swa_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWA Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swa_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWA_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWA Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swa_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWA + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swa_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWA_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWA will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swa_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWB Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swb_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWB Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swb_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWB_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWB Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swb_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWB + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swb_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWB_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWB will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swb_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWC Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swc_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWC Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swc_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWC_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWC Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swc_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWC + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swc_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWC_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWC will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swc_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_SETTING</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWD Voltage Setting + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swd_voltage_setting</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_RANGE_SELECT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWD Voltage Range + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swd_voltage_range_select</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWD_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWD Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swd_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_DELAY</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Delay after the sequence which enables SWD + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swd_sequence_delay</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SWD_SEQUENCE_ORDER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + The sequence at which SWD will be enabled + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_swd_sequence_order</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_PHASE_COMB</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Phase configuration for PMIC0 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_phase_comb</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_PHASE_COMB</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Phase configuration for PMIC1 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_phase_comb</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC0_SEQUENCE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Sequence order to enable PMIC0 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic0_sequence</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_PMIC1_SEQUENCE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Sequence order to enable PMIC1 + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>pmic1_sequence</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC0_SWA_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWA Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic0_swa_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC0_SWB_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWB Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic0_swb_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC0_SWC_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWC Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic0_swc_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC0_SWD_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC0 SWD Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic0_swd_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC1_SWA_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWA Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic1_swa_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC1_SWB_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWB Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic1_swb_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC1_SWC_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWC Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic1_swc_voltage_offset</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_EFD_PMIC1_SWD_VOLTAGE_OFFSET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + PMIC1 SWD Voltage Offset (signed, 1 bit increments) + </description> + <initToZero></initToZero> + <valueType>int8</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>efd_pmic1_swd_voltage_offset</mssAccessorName> + </attribute> + +</attributes> diff --git a/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml b/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml new file mode 100644 index 000000000..fdc355620 --- /dev/null +++ b/src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml @@ -0,0 +1,209 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/common/procedures/xml/error_info/pmic_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + + <hwpError> + <rc>RC_I2C_PMIC_INVALID_READ_SIZE</rc> + <description> + The number of bytes returned from the read did not match + the expected value. + </description> + <ffdc>TARGET</ffdc> + <ffdc>ADDRESS</ffdc> + <ffdc>SIZE_RETURNED</ffdc> + <ffdc>SIZE_REQUESTED</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_CHIP_NOT_RECOGNIZED</rc> + <description> + The PMIC identifier register contents did not match any known chip. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VENDOR_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_VOLTAGE_OUT_OF_RANGE</rc> + <description> + The voltage from the SPD and offset combination or bias operation was out of range for the PMIC. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VOLTAGE_BITMAP</ffdc> + <ffdc>RAIL</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_ORDER_OUT_OF_RANGE</rc> + <description> + The sequence order specified by the SPD was out of range for the PMIC (max 4) + </description> + <ffdc>TARGET</ffdc> + <ffdc>RAIL</ffdc> + <ffdc>ORDER</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_VOLTAGE_RANGE_SETTING_OUT_OF_RANGE</rc> + <description> + The PMIC voltage setting range was too large (Valid: 0,1) + </description> + <ffdc>TARGET</ffdc> + <ffdc>RAIL</ffdc> + <ffdc>RANGE_SETTING</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_DELAY_OUT_OF_RANGE</rc> + <description> + The sequence delay specified by the SPD was out of range for the PMIC (max bitmap: 0b111) + </description> + <ffdc>TARGET</ffdc> + <ffdc>RAIL</ffdc> + <ffdc>DELAY</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_DIMM_SPD_UNSUPPORTED_MODULE_HEIGHT</rc> + <description> + The module_height attribute SPD of this DIMM was not identified as 1U or 2U. + Other heights (4U) are not supported at this time. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_PMIC_NOT_ENABLED</rc> + <description> + After running pmic_enable, the PMIC VR Enable bit did not remain set. + Therefore, the PMIC did not enable successfully. + </description> + <ffdc>PMIC_TARGET</ffdc> + <ffdc>OCMB_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>PMIC_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + <gard> + <target>OCMB_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_PMIC_STATUS_ERRORS</rc> + <description> + After running pmic_enable, one or more error status bits were set on the PMICs of this OCMB. + </description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>PMIC_TARGET</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>PMIC_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + <gard> + <target>OCMB_TARGET</target> + </gard> + </hwpError> + +</hwpErrors> diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.C b/src/import/chips/ocmb/common/spd_access/pmic_i2c_addr_get.H index 989fed6ab..f9134ccb4 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.C +++ b/src/import/chips/ocmb/common/spd_access/pmic_i2c_addr_get.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.C $ */ +/* $Source: src/import/chips/ocmb/common/spd_access/pmic_i2c_addr_get.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,28 +22,61 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ - /// -/// @file p9a_mss_eff_config_thermal.C -/// @brief Perform thermal calculations as part of the effective configuration +/// @file pmic_i2c_addr_get.H +/// @brief Function to get PMIC i2c addresses given SPD binary /// -// *HWP HWP Owner: Andre A. Marin <aamarin@us.ibm.com> -// *HWP HWP Backup: Michael Pardeik <pardeik@us.ibm.com> +// *HWP HWP Owner: Mark Pizzutillo <mark.pizzutillo@ibm.com> +// *HWP HWP Owner: Dan Crowell <dcrowell@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 1 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB -// fapi2 -#include <p9a_mss_eff_config_thermal.H> +/// +/// @brief Get the pmic i2c addrs from the provided spd binary +/// +/// @param[in] i_spd SPD binary +/// @param[out] o_pmic0_i2c_addr I2C Address from SPD +/// @param[out] o_pmic1_i2c_addr I2C Address from SPD +/// + +#ifndef __PMIC_I2C_ADDR_GET__ +#define __PMIC_I2C_ADDR_GET__ + +#include <vector> + +constexpr uint16_t SPD_PMIC0_I2C_BYTE = 260; +constexpr uint16_t SPD_PMIC1_I2C_BYTE = 261; + +constexpr uint8_t PMIC0 = 0; +constexpr uint8_t PMIC1 = 1; + +// Mapping from PMIC ID to SPD byte +static const std::vector<uint16_t> PMIC_I2C_ADDR_VECTOR = +{ + SPD_PMIC0_I2C_BYTE, // [0 == PMIC0] + SPD_PMIC1_I2C_BYTE // [1 == PMIC1] +}; /// -/// @brief Perform thermal calculations as part of the effective configuration -/// @param[in] i_targets vector of ports (e.g., MEM_PORT) all on the same VDDR domain -/// @return FAPI2_RC_SUCCESS iff ok -/// @note sets ATTR_MSS_MEM_WATT_TARGET, ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT and _PER_SLOT, and ATTR_MSS_PORT_MAXPOWER +/// @brief Get the pmic i2c address for the given PMIC ID /// -fapi2::ReturnCode p9a_mss_eff_config_thermal( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& - i_targets ) +/// @param[in] i_spd SPD binary +/// @param[in] i_pmic_id PMIC ID (0,1) +/// @return uint8_t I2C address for the given PMIC ID +/// @note May need to be changed to support 4U SPD +/// +inline uint8_t get_pmic_i2c_addr(const char* i_spd, const uint8_t i_pmic_id) { - return fapi2::FAPI2_RC_SUCCESS; + // Out of range, just return 0. Failsafe so we don't segfault + // The caller is responsible for calling this with a valid ID + if (i_pmic_id >= PMIC_I2C_ADDR_VECTOR.size()) + { + return 0; + } + + const uint16_t l_byte = PMIC_I2C_ADDR_VECTOR[i_pmic_id]; + return uint8_t(i_spd[l_byte]); } + +#endif diff --git a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H index df319eff1..2e5fcf906 100644 --- a/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H +++ b/src/import/chips/ocmb/explorer/common/include/exp_data_structs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,6 +56,10 @@ enum exp_struct_sizes SENSOR_CACHE_PADDING_SIZE_0 = 3, SENSOR_CACHE_PADDING_SIZE_1 = 15, + // Constants for draminit + DRAMINIT_NUM_ADDR_DELAYS = 8, + DRAMINIT_STRUCTURE_VERSION = 2, + // Training response constants TIMING_RESPONSE_2D_ARRAY_SIZE = 16, TRAINING_RESPONSE_NUM_RANKS = 4, @@ -63,6 +67,11 @@ enum exp_struct_sizes TRAINING_RESPONSE_NUM_LANES = 80, TRAINING_RESPONSE_NUM_RC = 27, TRAINING_RESPONSE_MR6_SIZE = TRAINING_RESPONSE_NUM_RANKS * TRAINING_RESPONSE_NUM_DRAM, + RCW_8BIT_CUTOFF = 16, + EYE_MIN_MAX_SIZE = 31, + DBYTE_N_SIZE = 10, + NIBBLE_N_SIZE = 20, + BIT_N_SIZE = 8, }; /// @@ -70,27 +79,29 @@ enum exp_struct_sizes /// @brief The host command structure /// @note The HOST uses 64 Byte Command Information Unit (IU) for sending commands to Firmware /// -typedef struct +typedef struct __attribute__((packed)) { // Command Header - uint8_t cmd_id; // Command type - uint8_t cmd_flags; // Various flags associated with the command - uint16_t request_identifier; // The request identifier of this transport request - uint32_t cmd_length; // Number of bytes following the UI header - uint32_t cmd_crc; // CRC of command data buffer, if used - uint32_t host_work_area; // Scratchpad area for Host, FW returns this value as a reponse - uint32_t cmd_work_area; // Scratchpad area for Firmware, can be used for tracking command progress etc. - uint32_t padding[CMD_PADDING_SIZE]; // Fill up to the size of one cache line - uint8_t command_argument[ARGUMENT_SIZE]; // Additional parameters associated with the command - uint32_t cmd_header_crc; // CRC of 64 bytes of command header -} host_fw_command_struct; + uint8_t cmd_id; // Command type + uint8_t cmd_flags; // Various flags associated with the command + uint16_t request_identifier; // The request identifier of this transport request + uint32_t cmd_length; // Number of bytes following the UI header + uint32_t cmd_crc; // CRC of command data buffer, if used + uint32_t host_work_area; // Scratchpad area for Host, FW returns this value as a reponse + uint32_t cmd_work_area; // Scratchpad area for Firmware, can be used for tracking command progress etc. + uint32_t padding[CMD_PADDING_SIZE]; // Fill up to the size of one cache line + uint8_t command_argument[ARGUMENT_SIZE]; // Additional parameters associated with the command + uint32_t cmd_header_crc; // CRC of 64 bytes of command header +} +host_fw_command_struct; + /// /// @class host_fw_response_struct /// @brief The firmware response structure /// @note The Firmware uses 64 Byte Response Information Unit (IU) for sending responses to HOST /// -typedef struct +typedef struct __attribute__((packed)) { // Response Header uint8_t response_id; // Response ID - same as Command ID @@ -102,7 +113,8 @@ typedef struct uint32_t padding[RSP_PADDING_SIZE]; // Fill up to the size of one cache line uint8_t response_argument[ARGUMENT_SIZE]; // Additional parameters associated with the response uint32_t response_header_crc; // CRC of 64 bytes of reponse header -} host_fw_response_struct; +} +host_fw_response_struct; /// @@ -110,12 +122,16 @@ typedef struct /// @brief PHY initialization parameters /// @note PHY FW module requires certain parameters from HOST software /// -typedef struct user_input_msdg +typedef struct __attribute__((packed)) user_input_msdg { + uint32_t version_number; + // Choose the Dimm type from one of below: // 0 = UDIMM // 1 = RDIMM - // 2 = LRDIMM + // 2 = LRDIMM (invalid for explorer) + // 3 = MDS-LRDIMM + // 4 = MDS uint16_t DimmType; // Indicates presence of DRAM at each chip select for PHY. Each @@ -159,7 +175,7 @@ typedef struct user_input_msdg // 0 = No Address Mirror. uint16_t AddrMirror; - // DRAM Column Addr Width (Valid value: 5,6,7,10) + // DRAM Column Addr Width (Valid value: 10) uint16_t ColumnAddrWidth; // DRAM Row Addr Width (Valid value: 14,15,16,17,18) @@ -186,6 +202,16 @@ typedef struct user_input_msdg // 0 = Normal mode (2-rank); uint16_t Rank4Mode; + // Operate PHY in Encoded QuadCs Mode (only valid for + // RDIMM/RLDIMM) (NOT Supported in Explorer) when enabled, + // each CA bus drives one RCD in Encoded QuadCs mode. + // {cid_a/b[0],csn_a/b[1:0]} are connected to {DC0,DCS1_n,DCS0_n} + // to select master ranks. cid_a/b[1] is connected to DC2 to + // select up to 2 logic ranks (2H 3DStack) + // 1 = Encoded QuadCs Mode + // 0 = Direct DualCs Mod + uint16_t EncodedQuadCs; + // Support 1rank 3DS Device in // 1 = 1 rank 3DS in DDP board // PHY are connected to c[0],c[1],c[2] of DRAM); @@ -206,6 +232,12 @@ typedef struct user_input_msdg // 0 = Normal DDR4 DRAM; uint16_t MRAMSupport; + + // 1 = Support MDS 8H DRAM (odt[1] is connected to c[2] of + // MDS DRAM); + // 0 = Normal Mode; + uint16_t MDSSupport; + // Number of p-states used // Always set NumPStates to 1 for Explorer. // For the fields with Pstate array, only need to fill [0] entry. @@ -425,7 +457,7 @@ typedef struct user_input_msdg // Disable Receiver DFE // PhyEqualization[1] = 0: Enable Driver FFE; = 0: // Disable Driver FFE - uint16_t PhyEqualization; + uint16_t PhyEqualization[MSDG_MAX_PSTATE]; // Initial VrefDQ (MR6) // InitVrefDQ[6] = VrefDQ training range (same as MR6[6]) @@ -440,25 +472,43 @@ typedef struct user_input_msdg uint16_t InitPhyVref[MSDG_MAX_PSTATE]; // Enter desired ODT[3:0] value when writing to ranks - // OdtWrMapCs[i][3:0] ODT value when writing to rank 0 - // OdtWrMapCs[i][7:4] ODT value when writing to rank 1 - // OdtWrMapCs[i][11:8] ODT value when writing to rank 2 - // OdtWrMapCs[i][15:12] ODT value when writing to rank 3 - // [0] - ODT value for P0 - // [1] - ODT value for P1 - // [2] - ODT value for P2 - // [3] - ODT value for P3 + // in normal mode (2 rank) + // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1 + // If EncodedQuadCs = 1 + // OdtWrMapCs BIT [1:0] ODT_A/B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A/B[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [9:8] ODT_A/B[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [13:12] ODT_A/B[1:0] value when writing to rank 3 + // If Rank4Mode = 1 + // OdtWrMapCs BIT [1:0] ODT_A[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [3:2] ODT_B[1:0] value when writing to rank 0 + // OdtWrMapCs BIT [5:4] ODT_A[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [7:6] ODT_B[1:0] value when writing to rank 1 + // OdtWrMapCs BIT [9:8] ODT_A[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [11:10] ODT_B[1:0] value when writing to rank 2 + // OdtWrMapCs BIT [13:12] ODT_A[1:0] value when writing to rank 3 + // OdtWrMapCs BIT [15:14] ODT_B[1:0] value when writing to rank 3 uint16_t OdtWrMapCs[MSDG_MAX_PSTATE]; - // Enter desired ODT[3:0] value when writing to ranks - // OdtRdMapCs[i][3:0] ODT value when writing to rank 0 - // OdtRdMapCs[i][7:4] ODT value when writing to rank 1 - // OdtRdMapCs[i][11:8] ODT value when writing to rank 2 - // OdtRdMapCs[i][15:12] ODT value when writing to rank 3 - // [0] - ODT value for P0 - // [1] - ODT value for P1 - // [2] - ODT value for P2 - // [3] - ODT value for P3 + // Enter desired ODT[3:0] value when reading from ranks + // in normal mode (2 rank) + // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1 + // If EncodedQuadCs = 1 + // OdtRdMapCs BIT [1:0] ODT_A/B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A/B[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [9:8] ODT_A/B[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [13:12] ODT_A/B[1:0] value when reading from rank 3 + // If Rank4Mode = 1 + // OdtRdMapCs BIT [1:0] ODT_A[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [3:2] ODT_B[1:0] value when reading from rank 0 + // OdtRdMapCs BIT [5:4] ODT_A[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [7:6] ODT_B[1:0] value when reading from rank 1 + // OdtRdMapCs BIT [9:8] ODT_A[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [11:10] ODT_B[1:0] value when reading from rank 2 + // OdtRdMapCs BIT [13:12] ODT_A[1:0] value when reading from rank 3 + // OdtRdMapCs BIT [15:14] ODT_B[1:0] value when reading from rank 3 uint16_t OdtRdMapCs[MSDG_MAX_PSTATE]; // Enable geardown mode during training/dfi_bist. @@ -527,14 +577,14 @@ typedef struct user_input_msdg // RcdIBTCtrl[1:0] CA Input Bus Termination // RcdIBTCtrl[3:2] DCS[3:0]_n Input Bus Termination // RcdIBTCtrl[5:4] DCKE Input Bus Termination // RcdIBTCtrl[7:6] DODT Input Bus Termination - uint16_t RcdIBTCtrl; + uint16_t RcdIBTCtrl[MSDG_MAX_PSTATE]; // RCD Data Buffer Interface Driver Characteristics (F1RC00) // RcdDBDic[0] BCOM[3:0],BODT,BCKE, driver strength // RcdDBDic[1] Reserved // RcdDBDic[2] BCK_t/BCK_c driver strength // RcdDBDic[3] Reserved - uint16_t RcdDBDic; + uint16_t RcdDBDic[MSDG_MAX_PSTATE]; // RCD slew rate control (F1RC02,F1RC03,F1RC04,F1RC05) // RcdSlewRate[1:0] slew rate control of address/command @@ -544,12 +594,27 @@ typedef struct user_input_msdg // RcdSlewRate[9:8] slew rate control of Y1_t/c, Y3_t/c // RcdSlewRate[11:10] slew rate control of Y0_t/c, Y2_t/c // RcdSlewRate[13:12] slew rate control of BCOM[3:0], BODT, BCKE // RcdSlewRate[15:14] slew rate control of BCK_t/c - uint16_t RcdSlewRate; - - // Enable Special mode for Emulation Support - // [0] = 0 Normal firmware mode - // [0] = 1 Emulation firmware mode - uint16_t EmulationSupport; + uint16_t RcdSlewRate[MSDG_MAX_PSTATE]; + + // DFIMRL_DDRCLK: Max Read Latency counted by DDR Clock. + // dfi_rddata is returned (14 + DFIMRL_DDRCLK) cycles after + // dfi_rddata_en is asserted. + uint16_t DFIMRL_DDRCLK; + + //ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] + //ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] + //ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] + //ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] + //ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY + //ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] + //ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] + //ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] + //7bit A-side AC Delay + //ATxDly_A[pstate][NumAnib] + uint8_t ATxDly_A[MSDG_MAX_PSTATE][DRAMINIT_NUM_ADDR_DELAYS]; + //7bit B-side AC Delay + //ATxDly_B[pstate][NumAnib] + uint8_t ATxDly_B[MSDG_MAX_PSTATE][DRAMINIT_NUM_ADDR_DELAYS]; } user_input_msdg_t; /// @@ -557,7 +622,7 @@ typedef struct user_input_msdg /// @brief The sensor cache structure /// @note The data in the sensor cache is returned in 2 32-byte packets /// -typedef struct +typedef struct __attribute__((packed)) { /* * Packet 0 @@ -598,14 +663,15 @@ typedef struct uint8_t initial_packet1; // initial_packet1[0] '1' on first packet1 return, otherwise '0' // // initial_packet1[1:7] Reserved uint8_t reserved1[SENSOR_CACHE_PADDING_SIZE_1]; -} sensor_cache_struct; +} +sensor_cache_struct; /// /// @class user_response_timing_msdg_t /// @brief Contains the command to command timing training results /// -typedef struct user_response_timing_msdg +typedef struct __attribute__((packed)) user_response_timing_msdg { uint16_t DFIMRL_DDRCLK_trained; // Training result of DFIMRL_DDRCLK parameter (by mrlTraining step). // DFIMRL_DDRCLK: Max Read Latency counted by DDR Clock. dfi_rddata is returned (14 + DFIMRL_DDRCLK) cycles after dfi_rddata_en is asserted. @@ -629,7 +695,7 @@ typedef struct user_response_timing_msdg /// @class user_response_error_msdg /// @brief Contains the lane failure results /// -typedef struct user_response_error_msdg +typedef struct __attribute__((packed)) user_response_error_msdg { uint16_t Failure_Lane[TRAINING_RESPONSE_NUM_LANES]; // error code of DQ[n] on Rank 3,2,1 & 0. Rank 0 is in LS Nibble. //Failure status of training. Each uint16_t field contains the training error code of all 4 ranks on 1 DQ lane. @@ -651,7 +717,7 @@ typedef struct user_response_error_msdg /// @class user_response_mrs_msdg_t /// @brief MRS response structure /// -typedef struct user_response_mrs_msdg_t +typedef struct __attribute__((packed)) user_response_mrs_msdg_t { uint16_t MR0; // Value of DDR mode register MR0 for all ranks, all devices uint16_t MR1[TRAINING_RESPONSE_NUM_RANKS]; // Value of DDR mode register MR1 for each rank (up to 4 ranks) @@ -667,7 +733,7 @@ typedef struct user_response_mrs_msdg_t /// @class user_response_rc_msdg_t /// @brief RCD response structure /// -typedef struct user_response_rc_msdg_t +typedef struct __attribute__((packed)) user_response_rc_msdg_t { uint8_t F0RC_D0[TRAINING_RESPONSE_NUM_RC]; // RCD control words for DIMM0; Invalid for UDIMM // F0RC_D0[15:0] BIT [3:0]: 4-bit value of F0RC00~F0RC0F @@ -684,10 +750,92 @@ typedef struct user_response_rc_msdg_t } user_response_rc_msdg_t; /// +/// @class train_2d_eye_min_max_msdg_t +/// @brief Microchip response structure +/// +typedef struct __attribute__((packed)) train_2d_eye_min_max_msdg +{ + //2D training has to run with 1D training results in the delay registers. Horizontally it takes 1D + //centered value as starting position and only sweep half of a UI to left and right (1 UI in total). + //Vertically it takes preset vref value as starting position and sweep until bit error is detected. + //The assumption is that data eye will be enclosed in that range. + //eye_max/min contain the max/min VrefDAC0/VrefDQ value which passes test with the Nth step shift + //within the 1UI range. The 1D centered RxClkDly/TxDqDly is always normalized to index 15 of the + //array. + //In train_2d_read_eye_msdg, eye_max/min value represents VrefDAC0 (PHY DQ receiver Vref setting) + //Vref = (0.510 + VrefDAC0[6:0] * 0.00385) * VDDQ + //In train_2d_write_eye_msdg, eye_max/min value represents VrefDQ (Dram DQ receiver Vref setting) + //Vref = (0.450 + VrefDQ[6:0] * 0.0065) * VDDQ + uint16_t eye_min[EYE_MIN_MAX_SIZE]; + uint16_t eye_max[EYE_MIN_MAX_SIZE]; +} train_2d_eye_min_max_msdg_t; + +/// +/// @class train_2d_read_eye_msdg_t +/// @brief Microchip response structure +/// +typedef struct __attribute__((packed)) train_2d_read_eye_msdg +{ + //train_2d_read_eye_msdg_t returns the read eye diagram from point of view of 2D training firmware. + //1D training center RxClkDly (per nibble) horizontally (left and right search), 2D training does + //sweep on horizontal (RxClkDly) and vertical (VrefDAC0) directions, then decide the center. + //2D training has to run with 1D training results in the delay registers. Horizontally it takes 1D + //centered value as starting position and only sweep half of a UI to left and right (1 UI in total). + //Vertically it takes preset vref value as starting position and sweep until bit error is detected. + //The assumption is that data eye will be enclosed in that range. + //VrefDAC0[*][*][*] contains the max/min VrefDAC0 value which passes test with the Nth step shift + //within the 1UI range. The 1D centered RxClkDly is always normalized to index 15 of the + //array. + //With both arrays, 2D read eye diagram can be plotted on debug host. + + // VrefDAC0[RANKi][DBYTEn][BITn] Maximum + // and minimum passing VrefDAC0 in 2D read training + train_2d_eye_min_max_msdg_t VrefDAC0[TRAINING_RESPONSE_NUM_RANKS][DBYTE_N_SIZE][BIT_N_SIZE]; + + // VrefDAC0_Center[DBYTEn][BITn] Centered + // VrefDAC0 value after 2D read training + uint16_t VrefDAC0_Center[DBYTE_N_SIZE][BIT_N_SIZE]; + + // RxClkDly_Center[RANKi][NIBBLEn] Centered + // RxClkDly location (w.r.t. eye diagram) after 2D + // read training + uint16_t RxClkDly_Center[TRAINING_RESPONSE_NUM_RANKS][NIBBLE_N_SIZE]; +} train_2d_read_eye_msdg_t; + +typedef struct __attribute__((packed)) train_2d_write_eye_msdg +{ + //train_2d_write_eye_msdg_t returns the write eye diagram from point of view of 2D training + //firmware. + //1D training center TxDqDly (per DQ) horizontally (left and right search), 2D training does sweep + //on horizontal (TxDqDly) and vertical (VrefDQ) directions, then decide the center. + //2D training has to run with 1D training results in the delay registers. Horizontally it takes 1D + //centered value as starting position and only sweep half of a UI to left and right (1 UI in total). + //Vertically it takes preset vref value as starting position and sweep until bit error is detected. + //The assumption is that data eye will be enclosed in that range. + //VrefDQ[*][*][*] contains the max/min VrefDQ value which passes test with the Nth step shift within + //the 1UI range. The 1D centered TxDqDly is always normalized to index 15 of the array. + //With both arrays, 2D read eye diagram can be plotted on debug host. + + // VrefDQ[RANKi][DBYTEn][BITn] Maximum and + // minimum passing VrefDQ in 2D write training + train_2d_eye_min_max_msdg_t VrefDQ[TRAINING_RESPONSE_NUM_RANKS][DBYTE_N_SIZE][BIT_N_SIZE]; + + // VrefDQ_Center[RANKi][NIBBLEn] Centered VrefDQ + // value after 2D write training + uint16_t VrefDQ_Center[TRAINING_RESPONSE_NUM_RANKS][NIBBLE_N_SIZE]; + + // TxDqDly_Center[RANKi][DBYTEn][BITn] Centered + // TxDqDly location (w.r.t. eye diagram) after 2D + // write training + uint16_t TxDqDly_Center[TRAINING_RESPONSE_NUM_RANKS][DBYTE_N_SIZE][BIT_N_SIZE]; + +} train_2d_write_eye_msdg_t; + +/// /// @class user_response_msdg_t /// @brief Microchip response structure /// -typedef struct user_response_msdg +typedef struct __attribute__((packed)) user_response_msdg { uint32_t version_number; user_response_timing_msdg_t tm_resp; @@ -697,4 +845,34 @@ typedef struct user_response_msdg } user_response_msdg_t; +/// +/// @class user_2d_eye_response_1_msdg_t +/// @brief Microchip response structure +/// +typedef struct __attribute__((packed)) user_2d_eye_response_1_msdg +{ + uint32_t version_number; + train_2d_read_eye_msdg_t read_2d_eye_resp; + user_response_timing_msdg_t tm_resp; + user_response_error_msdg_t err_resp; + user_response_mrs_msdg_t mrs_resp; + user_response_rc_msdg_t rc_resp; + +} user_2d_eye_response_1_msdg_t; + +/// +/// @class user_2d_eye_response_2_msdg_t +/// @brief Microchip response structure +/// +typedef struct __attribute__((packed)) user_2d_eye_response_2_msdg +{ + uint32_t version_number; + train_2d_write_eye_msdg_t write_2d_eye_resp; + user_response_timing_msdg_t tm_resp; + user_response_error_msdg_t err_resp; + user_response_mrs_msdg_t mrs_resp; + user_response_rc_msdg_t rc_resp; + +} user_2d_eye_response_2_msdg_t; + #endif diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses.H index 010b81049..66ad88c03 100644 --- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses.H +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses.H @@ -23,1540 +23,1504 @@ /* */ /* IBM_PROLOG_END_TAG */ + #ifndef __EXPLR_SCOM_ADDRESSES_H #define __EXPLR_SCOM_ADDRESSES_H -static const uint64_t EXPLR_DLX_CMN_CONFIG = 0x0801280Eull; - - -static const uint64_t EXPLR_DLX_DL0_CONFIG0 = 0x08012810ull; - - -static const uint64_t EXPLR_DLX_DL0_CONFIG1 = 0x08012811ull; - - -static const uint64_t EXPLR_DLX_DL0_CYA_BITS = 0x0801281Full; - - -static const uint64_t EXPLR_DLX_DL0_DEBUG_AID = 0x0801281Eull; - - -static const uint64_t EXPLR_DLX_DL0_DLX_CONFIG = 0x08012818ull; - - -static const uint64_t EXPLR_DLX_DL0_DLX_INFO = 0x08012819ull; - - -static const uint64_t EXPLR_DLX_DL0_EDPL_MAX_COUNT = 0x08012815ull; - - -static const uint64_t EXPLR_DLX_DL0_ERROR_ACTION = 0x0801281Dull; - - -static const uint64_t EXPLR_DLX_DL0_ERROR_CAPTURE = 0x08012814ull; - - -static const uint64_t EXPLR_DLX_DL0_ERROR_HOLD = 0x08012813ull; - - -static const uint64_t EXPLR_DLX_DL0_ERROR_MASK = 0x08012812ull; - - -static const uint64_t EXPLR_DLX_DL0_STATUS = 0x08012816ull; - - -static const uint64_t EXPLR_DLX_DL0_TRAINING_STATUS = 0x08012817ull; - - -static const uint64_t EXPLR_DLX_ERR_HOLD_LAT = 0x0801280Bull; - - -static const uint64_t EXPLR_DLX_ERR_MASK_LAT = 0x0801280Aull; - -static const uint64_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG = 0x08012806ull; +static const uint64_t EXPLR_DLX_CMN_CONFIG = 0x0801280Eull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG = 0x08012807ull; +static const uint64_t EXPLR_DLX_DL0_CONFIG0 = 0x08012810ull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG = 0x08012803ull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_AND = 0x08012804ull; +static const uint64_t EXPLR_DLX_DL0_CONFIG1 = 0x08012811ull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_OR = 0x08012805ull; +static const uint64_t EXPLR_DLX_DL0_CYA_BITS = 0x0801281Full; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG = 0x08012800ull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG_AND = 0x08012801ull; +static const uint64_t EXPLR_DLX_DL0_DEBUG_AID = 0x0801281Eull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG_OR = 0x08012802ull; +static const uint64_t EXPLR_DLX_DL0_DLX_CONFIG = 0x08012818ull; -static const uint64_t EXPLR_DLX_MC_OMI_FIR_WOF_REG = 0x08012808ull; +static const uint64_t EXPLR_DLX_DL0_DLX_INFO = 0x08012819ull; -static const uint64_t EXPLR_DLX_PMU_CNTR = 0x0801280Full; +static const uint64_t EXPLR_DLX_DL0_EDPL_MAX_COUNT = 0x08012815ull; -static const uint64_t EXPLR_MCBIST_CCSARRERRINJQ = 0x080118DEull; +static const uint64_t EXPLR_DLX_DL0_ERROR_ACTION = 0x0801281Dull; -static const uint64_t EXPLR_MCBIST_CCS_CNTLQ = 0x080118A5ull; +static const uint64_t EXPLR_DLX_DL0_ERROR_CAPTURE = 0x08012814ull; -static const uint64_t EXPLR_MCBIST_CCS_FIXED_DATA0Q = 0x080118E5ull; +static const uint64_t EXPLR_DLX_DL0_ERROR_HOLD = 0x08012813ull; -static const uint64_t EXPLR_MCBIST_CCS_FIXED_DATA1Q = 0x080118E6ull; +static const uint64_t EXPLR_DLX_DL0_ERROR_MASK = 0x08012812ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_00 = 0x08011815ull; +static const uint64_t EXPLR_DLX_DL0_STATUS = 0x08012816ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_01 = 0x08011816ull; +static const uint64_t EXPLR_DLX_DL0_TRAINING_STATUS = 0x08012817ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_02 = 0x08011817ull; +static const uint64_t EXPLR_DLX_ERR_HOLD_LAT = 0x0801280Bull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_03 = 0x08011818ull; +static const uint64_t EXPLR_DLX_ERR_MASK_LAT = 0x0801280Aull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_04 = 0x08011819ull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG = 0x08012806ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_05 = 0x0801181Aull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG = 0x08012807ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_06 = 0x0801181Bull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG = 0x08012803ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_07 = 0x0801181Cull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_AND = 0x08012804ull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_OR = 0x08012805ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_08 = 0x0801181Dull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG = 0x08012800ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_09 = 0x0801181Eull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG_AND = 0x08012801ull; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_REG_OR = 0x08012802ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_10 = 0x0801181Full; +static const uint64_t EXPLR_DLX_MC_OMI_FIR_WOF_REG = 0x08012808ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_11 = 0x08011820ull; +static const uint64_t EXPLR_DLX_PMU_CNTR = 0x0801280Full; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_12 = 0x08011821ull; +static const uint64_t EXPLR_MCBIST_CCSARRERRINJQ = 0x080118DEull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_13 = 0x08011822ull; +static const uint64_t EXPLR_MCBIST_CCS_CNTLQ = 0x080118A5ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_14 = 0x08011823ull; +static const uint64_t EXPLR_MCBIST_CCS_FIXED_DATA0Q = 0x080118E5ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_15 = 0x08011824ull; +static const uint64_t EXPLR_MCBIST_CCS_FIXED_DATA1Q = 0x080118E6ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_16 = 0x08011825ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_00 = 0x08011815ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_17 = 0x08011826ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_01 = 0x08011816ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_18 = 0x08011827ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_02 = 0x08011817ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_19 = 0x08011828ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_03 = 0x08011818ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_20 = 0x08011829ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_04 = 0x08011819ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_21 = 0x0801182Aull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_05 = 0x0801181Aull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_22 = 0x0801182Bull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_06 = 0x0801181Bull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_23 = 0x0801182Cull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_07 = 0x0801181Cull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_24 = 0x0801182Dull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_08 = 0x0801181Dull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_25 = 0x0801182Eull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_09 = 0x0801181Eull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_26 = 0x0801182Full; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_10 = 0x0801181Full; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_27 = 0x08011830ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_11 = 0x08011820ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_28 = 0x08011831ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_12 = 0x08011821ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_29 = 0x08011832ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_13 = 0x08011822ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_30 = 0x08011833ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_14 = 0x08011823ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_31 = 0x08011834ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_15 = 0x08011824ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_00 = 0x08011835ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_16 = 0x08011825ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_01 = 0x08011836ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_17 = 0x08011826ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_02 = 0x08011837ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_18 = 0x08011827ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_03 = 0x08011838ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_19 = 0x08011828ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_04 = 0x08011839ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_20 = 0x08011829ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_05 = 0x0801183Aull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_21 = 0x0801182Aull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_06 = 0x0801183Bull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_22 = 0x0801182Bull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_07 = 0x0801183Cull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_23 = 0x0801182Cull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_08 = 0x0801183Dull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_24 = 0x0801182Dull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_09 = 0x0801183Eull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_25 = 0x0801182Eull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_10 = 0x0801183Full; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_26 = 0x0801182Full; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_11 = 0x08011840ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_27 = 0x08011830ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_12 = 0x08011841ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_28 = 0x08011831ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_13 = 0x08011842ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_29 = 0x08011832ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_14 = 0x08011843ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_30 = 0x08011833ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_15 = 0x08011844ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR0_31 = 0x08011834ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_16 = 0x08011845ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_00 = 0x08011835ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_17 = 0x08011846ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_01 = 0x08011836ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_18 = 0x08011847ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_02 = 0x08011837ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_19 = 0x08011848ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_03 = 0x08011838ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_20 = 0x08011849ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_04 = 0x08011839ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_21 = 0x0801184Aull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_05 = 0x0801183Aull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_22 = 0x0801184Bull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_06 = 0x0801183Bull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_23 = 0x0801184Cull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_07 = 0x0801183Cull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_24 = 0x0801184Dull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_08 = 0x0801183Dull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_25 = 0x0801184Eull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_09 = 0x0801183Eull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_26 = 0x0801184Full; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_10 = 0x0801183Full; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_27 = 0x08011850ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_11 = 0x08011840ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_28 = 0x08011851ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_12 = 0x08011841ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_29 = 0x08011852ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_13 = 0x08011842ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_30 = 0x08011853ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_14 = 0x08011843ull; -static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_31 = 0x08011854ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_15 = 0x08011844ull; -static const uint64_t EXPLR_MCBIST_CCS_MODEQ = 0x080118A7ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_16 = 0x08011845ull; -static const uint64_t EXPLR_MCBIST_CCS_STATQ = 0x080118A6ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_17 = 0x08011846ull; -static const uint64_t EXPLR_MCBIST_DBGCFG0Q = 0x080118E8ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_18 = 0x08011847ull; -static const uint64_t EXPLR_MCBIST_DBGCFG1Q = 0x080118E9ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_19 = 0x08011848ull; -static const uint64_t EXPLR_MCBIST_DBGCFG2Q = 0x080118EAull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_20 = 0x08011849ull; -static const uint64_t EXPLR_MCBIST_DBGCFG3Q = 0x080118EBull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_21 = 0x0801184Aull; -static const uint64_t EXPLR_MCBIST_DBG_BUS_CFGQ = 0x08011872ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_22 = 0x0801184Bull; -static const uint64_t EXPLR_MCBIST_ERR_HOLD_LAT = 0x0801180Bull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_23 = 0x0801184Cull; -static const uint64_t EXPLR_MCBIST_ERR_MASK0Q = 0x08011873ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_24 = 0x0801184Dull; -static const uint64_t EXPLR_MCBIST_ERR_MASK1Q = 0x08011874ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_25 = 0x0801184Eull; -static const uint64_t EXPLR_MCBIST_ERR_MASK_LAT = 0x0801180Aull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_26 = 0x0801184Full; -static const uint64_t EXPLR_MCBIST_MBAUER0Q = 0x0801186Eull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_27 = 0x08011850ull; -static const uint64_t EXPLR_MCBIST_MBA_MCBERRPT0Q = 0x080118E7ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_28 = 0x08011851ull; -static const uint64_t EXPLR_MCBIST_MBA_MCBERRPT1Q = 0x080118ECull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_29 = 0x08011852ull; -static const uint64_t EXPLR_MCBIST_MBECTLQ = 0x08011810ull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_30 = 0x08011853ull; -static const uint64_t EXPLR_MCBIST_MBMPER0Q = 0x0801186Cull; +static const uint64_t EXPLR_MCBIST_CCS_INST_ARR1_31 = 0x08011854ull; -static const uint64_t EXPLR_MCBIST_MBNCER0Q = 0x0801186Aull; +static const uint64_t EXPLR_MCBIST_CCS_MODEQ = 0x080118A7ull; -static const uint64_t EXPLR_MCBIST_MBRCER0Q = 0x0801186Bull; +static const uint64_t EXPLR_MCBIST_CCS_STATQ = 0x080118A6ull; -static const uint64_t EXPLR_MCBIST_MBSEC0Q = 0x08011855ull; +static const uint64_t EXPLR_MCBIST_DBGCFG0Q = 0x080118E8ull; -static const uint64_t EXPLR_MCBIST_MBSEC1Q = 0x08011856ull; +static const uint64_t EXPLR_MCBIST_DBGCFG1Q = 0x080118E9ull; -static const uint64_t EXPLR_MCBIST_MBSEVR0Q = 0x0801187Eull; +static const uint64_t EXPLR_MCBIST_DBGCFG2Q = 0x080118EAull; -static const uint64_t EXPLR_MCBIST_MBSMODESQ = 0x08011862ull; +static const uint64_t EXPLR_MCBIST_DBGCFG3Q = 0x080118EBull; -static const uint64_t EXPLR_MCBIST_MBSMSECQ = 0x08011869ull; +static const uint64_t EXPLR_MCBIST_DBG_BUS_CFGQ = 0x08011872ull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC0Q = 0x08011858ull; +static const uint64_t EXPLR_MCBIST_ERR_HOLD_LAT = 0x0801180Bull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC1Q = 0x08011859ull; +static const uint64_t EXPLR_MCBIST_ERR_MASK0Q = 0x08011873ull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC2Q = 0x0801185Aull; +static const uint64_t EXPLR_MCBIST_ERR_MASK1Q = 0x08011874ull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC3Q = 0x0801185Bull; +static const uint64_t EXPLR_MCBIST_ERR_MASK_LAT = 0x0801180Aull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC4Q = 0x0801185Cull; +static const uint64_t EXPLR_MCBIST_MBAUER0Q = 0x0801186Eull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC5Q = 0x0801185Dull; +static const uint64_t EXPLR_MCBIST_MBA_MCBERRPT0Q = 0x080118E7ull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC6Q = 0x0801185Eull; +static const uint64_t EXPLR_MCBIST_MBA_MCBERRPT1Q = 0x080118ECull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC7Q = 0x0801185Full; +static const uint64_t EXPLR_MCBIST_MBECTLQ = 0x08011810ull; -static const uint64_t EXPLR_MCBIST_MBSSYMEC8Q = 0x08011860ull; +static const uint64_t EXPLR_MCBIST_MBMPER0Q = 0x0801186Cull; -static const uint64_t EXPLR_MCBIST_MBSTRQ = 0x08011857ull; +static const uint64_t EXPLR_MCBIST_MBNCER0Q = 0x0801186Aull; -static const uint64_t EXPLR_MCBIST_MBUER0Q = 0x0801186Dull; +static const uint64_t EXPLR_MCBIST_MBRCER0Q = 0x0801186Bull; -static const uint64_t EXPLR_MCBIST_MBXLT0Q = 0x0801186Full; +static const uint64_t EXPLR_MCBIST_MBSEC0Q = 0x08011855ull; -static const uint64_t EXPLR_MCBIST_MBXLT1 = 0x08011870ull; +static const uint64_t EXPLR_MCBIST_MBSEC1Q = 0x08011856ull; -static const uint64_t EXPLR_MCBIST_MBXLT2 = 0x08011871ull; +static const uint64_t EXPLR_MCBIST_MBSEVR0Q = 0x0801187Eull; -static const uint64_t EXPLR_MCBIST_MCBACQ = 0x080118D5ull; +static const uint64_t EXPLR_MCBIST_MBSMODESQ = 0x08011862ull; -static const uint64_t EXPLR_MCBIST_MCBAGRAQ = 0x080118D6ull; +static const uint64_t EXPLR_MCBIST_MBSMSECQ = 0x08011869ull; -static const uint64_t EXPLR_MCBIST_MCBAMR0A0Q = 0x080118C8ull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC0Q = 0x08011858ull; -static const uint64_t EXPLR_MCBIST_MCBAMR1A0Q = 0x080118C9ull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC1Q = 0x08011859ull; -static const uint64_t EXPLR_MCBIST_MCBAMR2A0Q = 0x080118CAull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC2Q = 0x0801185Aull; -static const uint64_t EXPLR_MCBIST_MCBAMR3A0Q = 0x080118CBull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC3Q = 0x0801185Bull; -static const uint64_t EXPLR_MCBIST_MCBCFGQ = 0x080118E0ull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC4Q = 0x0801185Cull; -static const uint64_t EXPLR_MCBIST_MCBDRCRQ = 0x080118BDull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC5Q = 0x0801185Dull; -static const uint64_t EXPLR_MCBIST_MCBDRSRQ = 0x080118BCull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC6Q = 0x0801185Eull; -static const uint64_t EXPLR_MCBIST_MCBEA0Q = 0x080118CEull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC7Q = 0x0801185Full; -static const uint64_t EXPLR_MCBIST_MCBEA1Q = 0x080118CFull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC8Q = 0x08011860ull; -static const uint64_t EXPLR_MCBIST_MCBEA2Q = 0x080118D2ull; +static const uint64_t EXPLR_MCBIST_MBSSYMEC9Q = 0x08011861ull; -static const uint64_t EXPLR_MCBIST_MCBEA3Q = 0x080118D3ull; +static const uint64_t EXPLR_MCBIST_MBSTRQ = 0x08011857ull; -static const uint64_t EXPLR_MCBIST_MCBFD0Q = 0x080118BEull; +static const uint64_t EXPLR_MCBIST_MBUER0Q = 0x0801186Dull; -static const uint64_t EXPLR_MCBIST_MCBFD1Q = 0x080118BFull; +static const uint64_t EXPLR_MCBIST_MBXLT0Q = 0x0801186Full; -static const uint64_t EXPLR_MCBIST_MCBFD2Q = 0x080118C0ull; +static const uint64_t EXPLR_MCBIST_MBXLT1 = 0x08011870ull; -static const uint64_t EXPLR_MCBIST_MCBFD3Q = 0x080118C1ull; +static const uint64_t EXPLR_MCBIST_MBXLT2 = 0x08011871ull; -static const uint64_t EXPLR_MCBIST_MCBFD4Q = 0x080118C2ull; +static const uint64_t EXPLR_MCBIST_MCBACQ = 0x080118D5ull; -static const uint64_t EXPLR_MCBIST_MCBFD5Q = 0x080118C3ull; +static const uint64_t EXPLR_MCBIST_MCBAGRAQ = 0x080118D6ull; -static const uint64_t EXPLR_MCBIST_MCBFD6Q = 0x080118C4ull; +static const uint64_t EXPLR_MCBIST_MCBAMR0A0Q = 0x080118C8ull; -static const uint64_t EXPLR_MCBIST_MCBFD7Q = 0x080118C5ull; +static const uint64_t EXPLR_MCBIST_MCBAMR1A0Q = 0x080118C9ull; -static const uint64_t EXPLR_MCBIST_MCBFDQ = 0x080118C6ull; +static const uint64_t EXPLR_MCBIST_MCBAMR2A0Q = 0x080118CAull; -static const uint64_t EXPLR_MCBIST_MCBFDSPQ = 0x080118C7ull; +static const uint64_t EXPLR_MCBIST_MCBAMR3A0Q = 0x080118CBull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRACT0 = 0x08011806ull; +static const uint64_t EXPLR_MCBIST_MCBCFGQ = 0x080118E0ull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRACT1 = 0x08011807ull; +static const uint64_t EXPLR_MCBIST_MCBDRCRQ = 0x080118BDull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK = 0x08011803ull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK_AND = 0x08011804ull; +static const uint64_t EXPLR_MCBIST_MCBDRSRQ = 0x080118BCull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK_OR = 0x08011805ull; +static const uint64_t EXPLR_MCBIST_MCBEA0Q = 0x080118CEull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRQ = 0x08011800ull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRQ_AND = 0x08011801ull; +static const uint64_t EXPLR_MCBIST_MCBEA1Q = 0x080118CFull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRQ_OR = 0x08011802ull; +static const uint64_t EXPLR_MCBIST_MCBEA2Q = 0x080118D2ull; -static const uint64_t EXPLR_MCBIST_MCBISTFIRWOF = 0x08011808ull; +static const uint64_t EXPLR_MCBIST_MCBEA3Q = 0x080118D3ull; -static const uint64_t EXPLR_MCBIST_MCBLFSRA0Q = 0x080118D4ull; +static const uint64_t EXPLR_MCBIST_MCBFD0Q = 0x080118BEull; -static const uint64_t EXPLR_MCBIST_MCBMCATQ = 0x080118D7ull; +static const uint64_t EXPLR_MCBIST_MCBFD1Q = 0x080118BFull; -static const uint64_t EXPLR_MCBIST_MCBMR0Q = 0x080118A8ull; +static const uint64_t EXPLR_MCBIST_MCBFD2Q = 0x080118C0ull; -static const uint64_t EXPLR_MCBIST_MCBMR1Q = 0x080118A9ull; +static const uint64_t EXPLR_MCBIST_MCBFD3Q = 0x080118C1ull; -static const uint64_t EXPLR_MCBIST_MCBMR2Q = 0x080118AAull; +static const uint64_t EXPLR_MCBIST_MCBFD4Q = 0x080118C2ull; -static const uint64_t EXPLR_MCBIST_MCBMR3Q = 0x080118ABull; +static const uint64_t EXPLR_MCBIST_MCBFD5Q = 0x080118C3ull; -static const uint64_t EXPLR_MCBIST_MCBMR4Q = 0x080118ACull; +static const uint64_t EXPLR_MCBIST_MCBFD6Q = 0x080118C4ull; -static const uint64_t EXPLR_MCBIST_MCBMR5Q = 0x080118ADull; +static const uint64_t EXPLR_MCBIST_MCBFD7Q = 0x080118C5ull; -static const uint64_t EXPLR_MCBIST_MCBMR6Q = 0x080118AEull; +static const uint64_t EXPLR_MCBIST_MCBFDQ = 0x080118C6ull; -static const uint64_t EXPLR_MCBIST_MCBMR7Q = 0x080118DFull; +static const uint64_t EXPLR_MCBIST_MCBFDSPQ = 0x080118C7ull; -static const uint64_t EXPLR_MCBIST_MCBPARMQ = 0x080118AFull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRACT0 = 0x08011806ull; -static const uint64_t EXPLR_MCBIST_MCBRCRQ = 0x080118B1ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRACT1 = 0x08011807ull; -static const uint64_t EXPLR_MCBIST_MCBRDS0Q = 0x080118B2ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK = 0x08011803ull; -static const uint64_t EXPLR_MCBIST_MCBRDS1Q = 0x080118B3ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK_AND = 0x08011804ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRMASK_OR = 0x08011805ull; -static const uint64_t EXPLR_MCBIST_MCBSA0Q = 0x080118CCull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRQ = 0x08011800ull; -static const uint64_t EXPLR_MCBIST_MCBSA1Q = 0x080118CDull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRQ_AND = 0x08011801ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRQ_OR = 0x08011802ull; -static const uint64_t EXPLR_MCBIST_MCBSA2Q = 0x080118D0ull; +static const uint64_t EXPLR_MCBIST_MCBISTFIRWOF = 0x08011808ull; -static const uint64_t EXPLR_MCBIST_MCBSA3Q = 0x080118D1ull; +static const uint64_t EXPLR_MCBIST_MCBLFSRA0Q = 0x080118D4ull; -static const uint64_t EXPLR_MCBIST_MCBSTATQ = 0x08011866ull; +static const uint64_t EXPLR_MCBIST_MCBMCATQ = 0x080118D7ull; -static const uint64_t EXPLR_MCBIST_MCB_CNTLQ = 0x080118DBull; +static const uint64_t EXPLR_MCBIST_MCBMR0Q = 0x080118A8ull; -static const uint64_t EXPLR_MCBIST_MCB_CNTLSTATQ = 0x080118DCull; +static const uint64_t EXPLR_MCBIST_MCBMR1Q = 0x080118A9ull; -static const uint64_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q = 0x080118DDull; +static const uint64_t EXPLR_MCBIST_MCBMR2Q = 0x080118AAull; -static const uint64_t EXPLR_MCBIST_RUNTIMECTRQ = 0x080118B0ull; +static const uint64_t EXPLR_MCBIST_MCBMR3Q = 0x080118ABull; -static const uint64_t EXPLR_MCBIST_WATCFG0AQ = 0x08011880ull; +static const uint64_t EXPLR_MCBIST_MCBMR4Q = 0x080118ACull; -static const uint64_t EXPLR_MCBIST_WATCFG0BQ = 0x08011881ull; +static const uint64_t EXPLR_MCBIST_MCBMR5Q = 0x080118ADull; -static const uint64_t EXPLR_MCBIST_WATCFG0CQ = 0x08011882ull; +static const uint64_t EXPLR_MCBIST_MCBMR6Q = 0x080118AEull; -static const uint64_t EXPLR_MCBIST_WATCFG0DQ = 0x08011883ull; +static const uint64_t EXPLR_MCBIST_MCBMR7Q = 0x080118DFull; -static const uint64_t EXPLR_MCBIST_WATCFG0EQ = 0x08011884ull; +static const uint64_t EXPLR_MCBIST_MCBPARMQ = 0x080118AFull; -static const uint64_t EXPLR_MCBIST_WATCFG1AQ = 0x08011885ull; +static const uint64_t EXPLR_MCBIST_MCBRCRQ = 0x080118B1ull; -static const uint64_t EXPLR_MCBIST_WATCFG1BQ = 0x08011886ull; +static const uint64_t EXPLR_MCBIST_MCBRDS0Q = 0x080118B2ull; -static const uint64_t EXPLR_MCBIST_WATCFG1CQ = 0x08011887ull; +static const uint64_t EXPLR_MCBIST_MCBRDS1Q = 0x080118B3ull; -static const uint64_t EXPLR_MCBIST_WATCFG1DQ = 0x08011888ull; +static const uint64_t EXPLR_MCBIST_MCBSA0Q = 0x080118CCull; -static const uint64_t EXPLR_MCBIST_WATCFG1EQ = 0x08011889ull; +static const uint64_t EXPLR_MCBIST_MCBSA1Q = 0x080118CDull; -static const uint64_t EXPLR_MCBIST_WATCFG2AQ = 0x0801188Aull; +static const uint64_t EXPLR_MCBIST_MCBSA2Q = 0x080118D0ull; -static const uint64_t EXPLR_MCBIST_WATCFG2BQ = 0x0801188Bull; +static const uint64_t EXPLR_MCBIST_MCBSA3Q = 0x080118D1ull; -static const uint64_t EXPLR_MCBIST_WATCFG2CQ = 0x0801188Cull; +static const uint64_t EXPLR_MCBIST_MCBSTATQ = 0x08011866ull; -static const uint64_t EXPLR_MCBIST_WATCFG2DQ = 0x0801188Dull; +static const uint64_t EXPLR_MCBIST_MCB_CNTLQ = 0x080118DBull; -static const uint64_t EXPLR_MCBIST_WATCFG2EQ = 0x0801188Eull; +static const uint64_t EXPLR_MCBIST_MCB_CNTLSTATQ = 0x080118DCull; -static const uint64_t EXPLR_MCBIST_WATCFG3AQ = 0x0801188Full; +static const uint64_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q = 0x080118DDull; -static const uint64_t EXPLR_MCBIST_WATCFG3BQ = 0x08011890ull; +static const uint64_t EXPLR_MCBIST_RUNTIMECTRQ = 0x080118B0ull; -static const uint64_t EXPLR_MCBIST_WATCFG3CQ = 0x08011891ull; +static const uint64_t EXPLR_MCBIST_WATCFG0AQ = 0x08011880ull; -static const uint64_t EXPLR_MCBIST_WATCFG3DQ = 0x08011892ull; +static const uint64_t EXPLR_MCBIST_WATCFG0BQ = 0x08011881ull; -static const uint64_t EXPLR_MCBIST_WATCFG3EQ = 0x08011893ull; +static const uint64_t EXPLR_MCBIST_WATCFG0CQ = 0x08011882ull; -static const uint64_t EXPLR_MMIO_MCFGERR = 0x080108EDull; +static const uint64_t EXPLR_MCBIST_WATCFG0DQ = 0x08011883ull; -static const uint64_t EXPLR_MMIO_MCFGERRA = 0x080108ECull; +static const uint64_t EXPLR_MCBIST_WATCFG0EQ = 0x08011884ull; -static const uint64_t EXPLR_MMIO_MCHOLD = 0x0801087Bull; +static const uint64_t EXPLR_MCBIST_WATCFG1AQ = 0x08011885ull; -static const uint64_t EXPLR_MMIO_MCMASK = 0x0801087Aull; +static const uint64_t EXPLR_MCBIST_WATCFG1BQ = 0x08011886ull; -static const uint64_t EXPLR_MMIO_MDBELL = 0x080108E6ull; +static const uint64_t EXPLR_MCBIST_WATCFG1CQ = 0x08011887ull; -static const uint64_t EXPLR_MMIO_MDBELLC = 0x080108E7ull; +static const uint64_t EXPLR_MCBIST_WATCFG1DQ = 0x08011888ull; -static const uint64_t EXPLR_MMIO_MDEBUG0 = 0x080108EEull; +static const uint64_t EXPLR_MCBIST_WATCFG1EQ = 0x08011889ull; -static const uint64_t EXPLR_MMIO_MDEBUG1 = 0x080108EFull; +static const uint64_t EXPLR_MCBIST_WATCFG2AQ = 0x0801188Aull; -static const uint64_t EXPLR_MMIO_MENTERP = 0x080108E4ull; +static const uint64_t EXPLR_MCBIST_WATCFG2BQ = 0x0801188Bull; -static const uint64_t EXPLR_MMIO_MERRCTL = 0x080108EAull; +static const uint64_t EXPLR_MCBIST_WATCFG2CQ = 0x0801188Cull; -static const uint64_t EXPLR_MMIO_MFIR = 0x08010870ull; -static const uint64_t EXPLR_MMIO_MFIR_AND = 0x08010871ull; +static const uint64_t EXPLR_MCBIST_WATCFG2DQ = 0x0801188Dull; -static const uint64_t EXPLR_MMIO_MFIR_OR = 0x08010872ull; +static const uint64_t EXPLR_MCBIST_WATCFG2EQ = 0x0801188Eull; -static const uint64_t EXPLR_MMIO_MFIRACT0 = 0x08010876ull; +static const uint64_t EXPLR_MCBIST_WATCFG3AQ = 0x0801188Full; -static const uint64_t EXPLR_MMIO_MFIRACT1 = 0x08010877ull; +static const uint64_t EXPLR_MCBIST_WATCFG3BQ = 0x08011890ull; -static const uint64_t EXPLR_MMIO_MFIRMASK = 0x08010873ull; -static const uint64_t EXPLR_MMIO_MFIRMASK_AND = 0x08010874ull; +static const uint64_t EXPLR_MCBIST_WATCFG3CQ = 0x08011891ull; -static const uint64_t EXPLR_MMIO_MFIRMASK_OR = 0x08010875ull; +static const uint64_t EXPLR_MCBIST_WATCFG3DQ = 0x08011892ull; -static const uint64_t EXPLR_MMIO_MFIRWOF = 0x08010878ull; +static const uint64_t EXPLR_MCBIST_WATCFG3EQ = 0x08011893ull; -static const uint64_t EXPLR_MMIO_MHOLD0 = 0x0801087Cull; +static const uint64_t EXPLR_MMIO_MCFGERR = 0x080108EDull; -static const uint64_t EXPLR_MMIO_MHOLD1 = 0x0801087Eull; +static const uint64_t EXPLR_MMIO_MCFGERRA = 0x080108ECull; -static const uint64_t EXPLR_MMIO_MMASK0 = 0x0801087Dull; +static const uint64_t EXPLR_MMIO_MCHOLD = 0x0801087Bull; -static const uint64_t EXPLR_MMIO_MMASK1 = 0x0801087Full; +static const uint64_t EXPLR_MMIO_MCMASK = 0x0801087Aull; -static const uint64_t EXPLR_MMIO_MMIOERR = 0x080108E8ull; +static const uint64_t EXPLR_MMIO_MDBELL = 0x080108E6ull; -static const uint64_t EXPLR_MMIO_MMIOEWD = 0x080108E9ull; +static const uint64_t EXPLR_MMIO_MDBELLC = 0x080108E7ull; -static const uint64_t EXPLR_MMIO_MPIBERR0 = 0x080108FCull; +static const uint64_t EXPLR_MMIO_MDEBUG0 = 0x080108EEull; -static const uint64_t EXPLR_MMIO_MPIBERR1 = 0x080108FDull; +static const uint64_t EXPLR_MMIO_MDEBUG1 = 0x080108EFull; -static const uint64_t EXPLR_MMIO_MPIBERR2 = 0x080108FEull; +static const uint64_t EXPLR_MMIO_MENTERP = 0x080108E4ull; -static const uint64_t EXPLR_MMIO_MPIBERR3 = 0x080108FFull; +static const uint64_t EXPLR_MMIO_MERRCTL = 0x080108EAull; -static const uint64_t EXPLR_MMIO_MSCCRNGE = 0x080108E5ull; +static const uint64_t EXPLR_MMIO_MFIR = 0x08010870ull; -static const uint64_t EXPLR_MMIO_O0ACTAG_O0FNID = 0x08010831ull; +static const uint64_t EXPLR_MMIO_MFIR_AND = 0x08010871ull; +static const uint64_t EXPLR_MMIO_MFIR_OR = 0x08010872ull; -static const uint64_t EXPLR_MMIO_O0BAR0 = 0x08010802ull; +static const uint64_t EXPLR_MMIO_MFIRACT0 = 0x08010876ull; -static const uint64_t EXPLR_MMIO_O0BAR1 = 0x08010803ull; +static const uint64_t EXPLR_MMIO_MFIRACT1 = 0x08010877ull; -static const uint64_t EXPLR_MMIO_O0BAR2 = 0x08010804ull; +static const uint64_t EXPLR_MMIO_MFIRMASK = 0x08010873ull; -static const uint64_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR = 0x08010806ull; +static const uint64_t EXPLR_MMIO_MFIRMASK_AND = 0x08010874ull; +static const uint64_t EXPLR_MMIO_MFIRMASK_OR = 0x08010875ull; -static const uint64_t EXPLR_MMIO_O0CCD = 0x08010801ull; +static const uint64_t EXPLR_MMIO_MFIRWOF = 0x08010878ull; -static const uint64_t EXPLR_MMIO_O0FNVID_O0FNCAP = 0x08010830ull; +static const uint64_t EXPLR_MMIO_MHOLD0 = 0x0801087Cull; -static const uint64_t EXPLR_MMIO_O0MBIT_O0DID = 0x08010800ull; +static const uint64_t EXPLR_MMIO_MHOLD1 = 0x0801087Eull; -static const uint64_t EXPLR_MMIO_O0SSYSID = 0x08010805ull; +static const uint64_t EXPLR_MMIO_MMASK0 = 0x0801087Dull; -static const uint64_t EXPLR_MMIO_O0VSDLXA = 0x08010864ull; +static const uint64_t EXPLR_MMIO_MMASK1 = 0x0801087Full; -static const uint64_t EXPLR_MMIO_O0VSDLXB = 0x08010865ull; +static const uint64_t EXPLR_MMIO_MMIOERR = 0x080108E8ull; -static const uint64_t EXPLR_MMIO_O0VSFLSH = 0x08010866ull; +static const uint64_t EXPLR_MMIO_MMIOEWD = 0x080108E9ull; -static const uint64_t EXPLR_MMIO_O0VSID = 0x08010861ull; +static const uint64_t EXPLR_MMIO_MPIBERR0 = 0x080108FCull; -static const uint64_t EXPLR_MMIO_O0VSTLXA = 0x08010862ull; +static const uint64_t EXPLR_MMIO_MPIBERR1 = 0x080108FDull; -static const uint64_t EXPLR_MMIO_O0VSTLXB = 0x08010863ull; +static const uint64_t EXPLR_MMIO_MPIBERR2 = 0x080108FEull; -static const uint64_t EXPLR_MMIO_O0VSVID_O0VSCAP = 0x08010860ull; +static const uint64_t EXPLR_MMIO_MPIBERR3 = 0x080108FFull; -static const uint64_t EXPLR_MMIO_O1ACTAG_O1FNID = 0x080108B1ull; +static const uint64_t EXPLR_MMIO_MSCCRNGE = 0x080108E5ull; -static const uint64_t EXPLR_MMIO_O1BAR0 = 0x08010882ull; +static const uint64_t EXPLR_MMIO_O0ACTAG_O0FNID = 0x08010831ull; -static const uint64_t EXPLR_MMIO_O1BAR1 = 0x08010883ull; +static const uint64_t EXPLR_MMIO_O0BAR0 = 0x08010802ull; -static const uint64_t EXPLR_MMIO_O1BAR2 = 0x08010884ull; +static const uint64_t EXPLR_MMIO_O0BAR1 = 0x08010803ull; -static const uint64_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR = 0x08010886ull; +static const uint64_t EXPLR_MMIO_O0BAR2 = 0x08010804ull; -static const uint64_t EXPLR_MMIO_O1CCD = 0x08010881ull; +static const uint64_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR = 0x08010806ull; -static const uint64_t EXPLR_MMIO_O1FNVID_O1FNCAP = 0x080108B0ull; +static const uint64_t EXPLR_MMIO_O0CCD = 0x08010801ull; -static const uint64_t EXPLR_MMIO_O1INFDAT = 0x080108C2ull; +static const uint64_t EXPLR_MMIO_O0FNVID_O0FNCAP = 0x08010830ull; -static const uint64_t EXPLR_MMIO_O1INFOFF_O1INFID = 0x080108C1ull; +static const uint64_t EXPLR_MMIO_O0MBIT_O0DID = 0x08010800ull; -static const uint64_t EXPLR_MMIO_O1INFVID_O1INFCAP = 0x080108C0ull; +static const uint64_t EXPLR_MMIO_O0SSYSID = 0x08010805ull; -static const uint64_t EXPLR_MMIO_O1MBIT_O1DID = 0x08010880ull; +static const uint64_t EXPLR_MMIO_O0VSDLXA = 0x08010864ull; -static const uint64_t EXPLR_MMIO_O1SSYSID = 0x08010885ull; +static const uint64_t EXPLR_MMIO_O0VSDLXB = 0x08010865ull; -static const uint64_t EXPLR_MMIO_O1VSID = 0x080108E1ull; +static const uint64_t EXPLR_MMIO_O0VSFLSH = 0x08010866ull; -static const uint64_t EXPLR_MMIO_O1VSVID_O1VSCAP = 0x080108E0ull; +static const uint64_t EXPLR_MMIO_O0VSID = 0x08010861ull; -static const uint64_t EXPLR_MMIO_OAFUVER_ONAME5 = 0x080108F3ull; +static const uint64_t EXPLR_MMIO_O0VSTLXA = 0x08010862ull; -static const uint64_t EXPLR_MMIO_OCTRLENB_OCTRLID = 0x080108D1ull; +static const uint64_t EXPLR_MMIO_O0VSTLXB = 0x08010863ull; -static const uint64_t EXPLR_MMIO_OCTRLPID = 0x080108D2ull; +static const uint64_t EXPLR_MMIO_O0VSVID_O0VSCAP = 0x08010860ull; -static const uint64_t EXPLR_MMIO_OCTRLTAG = 0x080108D3ull; +static const uint64_t EXPLR_MMIO_O1ACTAG_O1FNID = 0x080108B1ull; -static const uint64_t EXPLR_MMIO_OCTRLVID_OCTRLCAP = 0x080108D0ull; +static const uint64_t EXPLR_MMIO_O1BAR0 = 0x08010882ull; -static const uint64_t EXPLR_MMIO_ODSNHI = 0x08010811ull; +static const uint64_t EXPLR_MMIO_O1BAR1 = 0x08010883ull; -static const uint64_t EXPLR_MMIO_ODSNLO_ODSNCAP = 0x08010810ull; +static const uint64_t EXPLR_MMIO_O1BAR2 = 0x08010884ull; -static const uint64_t EXPLR_MMIO_OGMMIOOF = 0x080108F4ull; +static const uint64_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR = 0x08010886ull; -static const uint64_t EXPLR_MMIO_OGMMIOSZ = 0x080108F5ull; +static const uint64_t EXPLR_MMIO_O1CCD = 0x08010881ull; -static const uint64_t EXPLR_MMIO_OMEMADDR = 0x080108F8ull; +static const uint64_t EXPLR_MMIO_O1FNVID_O1FNCAP = 0x080108B0ull; -static const uint64_t EXPLR_MMIO_ONAME0_ODESCTML = 0x080108F0ull; +static const uint64_t EXPLR_MMIO_O1INFDAT = 0x080108C2ull; -static const uint64_t EXPLR_MMIO_ONAME21 = 0x080108F1ull; +static const uint64_t EXPLR_MMIO_O1INFOFF_O1INFID = 0x080108C1ull; -static const uint64_t EXPLR_MMIO_ONAME43 = 0x080108F2ull; +static const uint64_t EXPLR_MMIO_O1INFVID_O1INFCAP = 0x080108C0ull; -static const uint64_t EXPLR_MMIO_OPASID = 0x08010890ull; +static const uint64_t EXPLR_MMIO_O1MBIT_O1DID = 0x08010880ull; -static const uint64_t EXPLR_MMIO_OPMMIOOF = 0x080108F6ull; +static const uint64_t EXPLR_MMIO_O1SSYSID = 0x08010885ull; -static const uint64_t EXPLR_MMIO_OPMMIOST = 0x080108F7ull; +static const uint64_t EXPLR_MMIO_O1VSID = 0x080108E1ull; -static const uint64_t EXPLR_MMIO_ORRCAP10 = 0x08010826ull; +static const uint64_t EXPLR_MMIO_O1VSVID_O1VSCAP = 0x080108E0ull; -static const uint64_t EXPLR_MMIO_ORRCAP32 = 0x08010827ull; +static const uint64_t EXPLR_MMIO_OAFUVER_ONAME5 = 0x080108F3ull; -static const uint64_t EXPLR_MMIO_ORRCAP54 = 0x08010828ull; +static const uint64_t EXPLR_MMIO_OCTRLENB_OCTRLID = 0x080108D1ull; -static const uint64_t EXPLR_MMIO_ORRCAP76 = 0x08010829ull; +static const uint64_t EXPLR_MMIO_OCTRLPID = 0x080108D2ull; -static const uint64_t EXPLR_MMIO_ORTCAP = 0x08010823ull; +static const uint64_t EXPLR_MMIO_OCTRLTAG = 0x080108D3ull; -static const uint64_t EXPLR_MMIO_OSYSMEML = 0x080108FBull; +static const uint64_t EXPLR_MMIO_OCTRLVID_OCTRLCAP = 0x080108D0ull; -static const uint64_t EXPLR_MMIO_OTLVID_OTLCAP = 0x08010820ull; +static const uint64_t EXPLR_MMIO_ODSNHI = 0x08010811ull; -static const uint64_t EXPLR_MMIO_OTRCFG10 = 0x0801082Aull; +static const uint64_t EXPLR_MMIO_ODSNLO_ODSNCAP = 0x08010810ull; -static const uint64_t EXPLR_MMIO_OTRCFG32 = 0x0801082Bull; +static const uint64_t EXPLR_MMIO_OGMMIOOF = 0x080108F4ull; -static const uint64_t EXPLR_MMIO_OTRCFG54 = 0x0801082Cull; +static const uint64_t EXPLR_MMIO_OGMMIOSZ = 0x080108F5ull; -static const uint64_t EXPLR_MMIO_OTRCFG76 = 0x0801082Dull; +static const uint64_t EXPLR_MMIO_OMEMADDR = 0x080108F8ull; -static const uint64_t EXPLR_MMIO_OTTCFG = 0x08010824ull; +static const uint64_t EXPLR_MMIO_ONAME0_ODESCTML = 0x080108F0ull; -static const uint64_t EXPLR_MMIO_OVERCAP_OTLID = 0x08010821ull; +static const uint64_t EXPLR_MMIO_ONAME21 = 0x080108F1ull; -static const uint64_t EXPLR_MMIO_OVERCFG = 0x08010822ull; +static const uint64_t EXPLR_MMIO_ONAME43 = 0x080108F2ull; -static const uint64_t EXPLR_MMIO_OVPD = 0x08010808ull; +static const uint64_t EXPLR_MMIO_OPASID = 0x08010890ull; -static const uint64_t EXPLR_MMIO_OWWID10 = 0x080108F9ull; +static const uint64_t EXPLR_MMIO_OPMMIOOF = 0x080108F6ull; -static const uint64_t EXPLR_MMIO_OWWID32 = 0x080108FAull; +static const uint64_t EXPLR_MMIO_OPMMIOST = 0x080108F7ull; -static const uint64_t EXPLR_MMIO_SCOMEWD = 0x080108EBull; +static const uint64_t EXPLR_MMIO_ORRCAP10 = 0x08010826ull; -static const uint64_t EXPLR_MMIO_SNSC_ACTPWRUP = 0x08010855ull; +static const uint64_t EXPLR_MMIO_ORRCAP32 = 0x08010827ull; -static const uint64_t EXPLR_MMIO_SNSC_D0THERM = 0x08010852ull; +static const uint64_t EXPLR_MMIO_ORRCAP54 = 0x08010828ull; -static const uint64_t EXPLR_MMIO_SNSC_D1THERM = 0x08010853ull; +static const uint64_t EXPLR_MMIO_ORRCAP76 = 0x08010829ull; -static const uint64_t EXPLR_MMIO_SNSC_FRAMESR = 0x08010856ull; +static const uint64_t EXPLR_MMIO_ORTCAP = 0x08010823ull; -static const uint64_t EXPLR_MMIO_SNSC_HISTOBASELOW = 0x08010857ull; +static const uint64_t EXPLR_MMIO_OSYSMEML = 0x080108FBull; -static const uint64_t EXPLR_MMIO_SNSC_HISTOMEDHIGH = 0x08010858ull; +static const uint64_t EXPLR_MMIO_OTLVID_OTLCAP = 0x08010820ull; -static const uint64_t EXPLR_MMIO_SNSC_OCTHERM = 0x08010851ull; +static const uint64_t EXPLR_MMIO_OTRCFG10 = 0x0801082Aull; -static const uint64_t EXPLR_MMIO_SNSC_RDWR = 0x08010854ull; +static const uint64_t EXPLR_MMIO_OTRCFG32 = 0x0801082Bull; -static const uint64_t EXPLR_MMIO_SNSC_STATEREG = 0x08010850ull; +static const uint64_t EXPLR_MMIO_OTRCFG54 = 0x0801082Cull; -static const uint64_t EXPLR_RDF_AACR = 0x08011C29ull; +static const uint64_t EXPLR_MMIO_OTRCFG76 = 0x0801082Dull; -static const uint64_t EXPLR_RDF_AADR = 0x08011C2Aull; +static const uint64_t EXPLR_MMIO_OTTCFG = 0x08010824ull; -static const uint64_t EXPLR_RDF_AAER = 0x08011C2Bull; +static const uint64_t EXPLR_MMIO_OVERCAP_OTLID = 0x08010821ull; -static const uint64_t EXPLR_RDF_ACTION0 = 0x08011C06ull; +static const uint64_t EXPLR_MMIO_OVERCFG = 0x08010822ull; -static const uint64_t EXPLR_RDF_ACTION1 = 0x08011C07ull; +static const uint64_t EXPLR_MMIO_OVPD = 0x08010808ull; -static const uint64_t EXPLR_RDF_CERR0 = 0x08011C0Eull; +static const uint64_t EXPLR_MMIO_OWWID10 = 0x080108F9ull; -static const uint64_t EXPLR_RDF_CERR1 = 0x08011C0Full; +static const uint64_t EXPLR_MMIO_OWWID32 = 0x080108FAull; -static const uint64_t EXPLR_RDF_CGDR = 0x08011C32ull; +static const uint64_t EXPLR_MMIO_SCOMEWD = 0x080108EBull; -static const uint64_t EXPLR_RDF_CTCR = 0x08011C28ull; +static const uint64_t EXPLR_MMIO_SNSC_ACTPWRUP = 0x08010855ull; -static const uint64_t EXPLR_RDF_DBGR = 0x08011C2Eull; +static const uint64_t EXPLR_MMIO_SNSC_D0THERM = 0x08010852ull; -static const uint64_t EXPLR_RDF_EICR = 0x08011C0Dull; +static const uint64_t EXPLR_MMIO_SNSC_D1THERM = 0x08010853ull; -static const uint64_t EXPLR_RDF_ELPR = 0x08011C2Full; +static const uint64_t EXPLR_MMIO_SNSC_FRAMESR = 0x08010856ull; -static const uint64_t EXPLR_RDF_ERR_HOLD_LAT = 0x08011C0Bull; +static const uint64_t EXPLR_MMIO_SNSC_HISTOBASELOW = 0x08010857ull; -static const uint64_t EXPLR_RDF_ERR_MASK_LAT = 0x08011C0Aull; +static const uint64_t EXPLR_MMIO_SNSC_HISTOMEDHIGH = 0x08010858ull; -static const uint64_t EXPLR_RDF_FIR = 0x08011C00ull; -static const uint64_t EXPLR_RDF_FIR_AND = 0x08011C01ull; +static const uint64_t EXPLR_MMIO_SNSC_OCTHERM = 0x08010851ull; -static const uint64_t EXPLR_RDF_FIR_OR = 0x08011C02ull; +static const uint64_t EXPLR_MMIO_SNSC_RDWR = 0x08010854ull; -static const uint64_t EXPLR_RDF_FWMS0 = 0x08011C18ull; +static const uint64_t EXPLR_MMIO_SNSC_STATEREG = 0x08010850ull; -static const uint64_t EXPLR_RDF_FWMS1 = 0x08011C19ull; +static const uint64_t EXPLR_RDF_AACR = 0x08011C29ull; -static const uint64_t EXPLR_RDF_FWMS2 = 0x08011C1Aull; +static const uint64_t EXPLR_RDF_AADR = 0x08011C2Aull; -static const uint64_t EXPLR_RDF_FWMS3 = 0x08011C1Bull; +static const uint64_t EXPLR_RDF_AAER = 0x08011C2Bull; -static const uint64_t EXPLR_RDF_FWMS4 = 0x08011C1Cull; +static const uint64_t EXPLR_RDF_ACTION0 = 0x08011C06ull; -static const uint64_t EXPLR_RDF_FWMS5 = 0x08011C1Dull; +static const uint64_t EXPLR_RDF_ACTION1 = 0x08011C07ull; -static const uint64_t EXPLR_RDF_FWMS6 = 0x08011C1Eull; +static const uint64_t EXPLR_RDF_CERR0 = 0x08011C0Eull; -static const uint64_t EXPLR_RDF_FWMS7 = 0x08011C1Full; +static const uint64_t EXPLR_RDF_CERR1 = 0x08011C0Full; -static const uint64_t EXPLR_RDF_HWMS0 = 0x08011C10ull; +static const uint64_t EXPLR_RDF_CGDR = 0x08011C32ull; -static const uint64_t EXPLR_RDF_HWMS1 = 0x08011C11ull; +static const uint64_t EXPLR_RDF_CTCR = 0x08011C28ull; -static const uint64_t EXPLR_RDF_HWMS2 = 0x08011C12ull; +static const uint64_t EXPLR_RDF_DBGR = 0x08011C2Eull; -static const uint64_t EXPLR_RDF_HWMS3 = 0x08011C13ull; +static const uint64_t EXPLR_RDF_EICR = 0x08011C0Dull; -static const uint64_t EXPLR_RDF_HWMS4 = 0x08011C14ull; +static const uint64_t EXPLR_RDF_ELPR = 0x08011C2Full; -static const uint64_t EXPLR_RDF_HWMS5 = 0x08011C15ull; +static const uint64_t EXPLR_RDF_ERR_HOLD_LAT = 0x08011C0Bull; -static const uint64_t EXPLR_RDF_HWMS6 = 0x08011C16ull; +static const uint64_t EXPLR_RDF_ERR_MASK_LAT = 0x08011C0Aull; -static const uint64_t EXPLR_RDF_HWMS7 = 0x08011C17ull; +static const uint64_t EXPLR_RDF_FIR = 0x08011C00ull; -static const uint64_t EXPLR_RDF_MASK = 0x08011C03ull; +static const uint64_t EXPLR_RDF_FIR_AND = 0x08011C01ull; -static const uint64_t EXPLR_RDF_MASK_AND = 0x08011C04ull; +static const uint64_t EXPLR_RDF_FIR_OR = 0x08011C02ull; -static const uint64_t EXPLR_RDF_MASK_OR = 0x08011C05ull; +static const uint64_t EXPLR_RDF_FWMS0 = 0x08011C18ull; -static const uint64_t EXPLR_RDF_MASK0 = 0x08011C30ull; +static const uint64_t EXPLR_RDF_FWMS1 = 0x08011C19ull; -static const uint64_t EXPLR_RDF_MASK1 = 0x08011C31ull; +static const uint64_t EXPLR_RDF_FWMS2 = 0x08011C1Aull; -static const uint64_t EXPLR_RDF_MCBCM = 0x08011C2Cull; +static const uint64_t EXPLR_RDF_FWMS3 = 0x08011C1Bull; -static const uint64_t EXPLR_RDF_MSR = 0x08011C0Cull; +static const uint64_t EXPLR_RDF_FWMS4 = 0x08011C1Cull; -static const uint64_t EXPLR_RDF_RECR = 0x08011C2Dull; +static const uint64_t EXPLR_RDF_FWMS5 = 0x08011C1Dull; -static const uint64_t EXPLR_RDF_RSPAR = 0x08011C20ull; +static const uint64_t EXPLR_RDF_FWMS6 = 0x08011C1Eull; -static const uint64_t EXPLR_RDF_WOF = 0x08011C08ull; +static const uint64_t EXPLR_RDF_FWMS7 = 0x08011C1Full; -static const uint64_t EXPLR_SRQ_ERR_HOLD_LAT = 0x0801140Bull; +static const uint64_t EXPLR_RDF_HWMS0 = 0x08011C10ull; -static const uint64_t EXPLR_SRQ_ERR_MASK_LAT = 0x0801140Aull; +static const uint64_t EXPLR_RDF_HWMS1 = 0x08011C11ull; -static const uint64_t EXPLR_SRQ_MBAREF0Q = 0x08011434ull; +static const uint64_t EXPLR_RDF_HWMS2 = 0x08011C12ull; -static const uint64_t EXPLR_SRQ_MBAREFAQ = 0x08011438ull; +static const uint64_t EXPLR_RDF_HWMS3 = 0x08011C13ull; -static const uint64_t EXPLR_SRQ_MBARPC0Q = 0x08011436ull; +static const uint64_t EXPLR_RDF_HWMS4 = 0x08011C14ull; -static const uint64_t EXPLR_SRQ_MBARSVD0 = 0x08011435ull; +static const uint64_t EXPLR_RDF_HWMS5 = 0x08011C15ull; -static const uint64_t EXPLR_SRQ_MBASTR0Q = 0x08011437ull; +static const uint64_t EXPLR_RDF_HWMS6 = 0x08011C16ull; -static const uint64_t EXPLR_SRQ_MBA_DBG0Q = 0x0801141Eull; +static const uint64_t EXPLR_RDF_HWMS7 = 0x08011C17ull; -static const uint64_t EXPLR_SRQ_MBA_DBG1Q = 0x0801141Full; +static const uint64_t EXPLR_RDF_MASK = 0x08011C03ull; -static const uint64_t EXPLR_SRQ_MBA_DSM0Q = 0x0801140Cull; +static const uint64_t EXPLR_RDF_MASK_AND = 0x08011C04ull; +static const uint64_t EXPLR_RDF_MASK_OR = 0x08011C05ull; -static const uint64_t EXPLR_SRQ_MBA_ERR_REPORTQ = 0x0801141Cull; +static const uint64_t EXPLR_RDF_MASK0 = 0x08011C30ull; -static const uint64_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK = 0x0801142Bull; +static const uint64_t EXPLR_RDF_MASK1 = 0x08011C31ull; -static const uint64_t EXPLR_SRQ_MBA_FARB0Q = 0x08011415ull; +static const uint64_t EXPLR_RDF_MCBCM = 0x08011C34ull; -static const uint64_t EXPLR_SRQ_MBA_FARB1Q = 0x08011416ull; +static const uint64_t EXPLR_RDF_MCBCM2 = 0x08011C35ull; -static const uint64_t EXPLR_SRQ_MBA_FARB2Q = 0x08011417ull; +static const uint64_t EXPLR_RDF_MSR = 0x08011C0Cull; -static const uint64_t EXPLR_SRQ_MBA_FARB3Q = 0x08011418ull; +static const uint64_t EXPLR_RDF_RECR = 0x08011C2Dull; -static const uint64_t EXPLR_SRQ_MBA_FARB4Q = 0x08011419ull; +static const uint64_t EXPLR_RDF_RSPAR = 0x08011C20ull; -static const uint64_t EXPLR_SRQ_MBA_FARB5Q = 0x0801141Aull; +static const uint64_t EXPLR_RDF_WOF = 0x08011C08ull; -static const uint64_t EXPLR_SRQ_MBA_FARB6Q = 0x0801141Bull; +static const uint64_t EXPLR_SRQ_ERR_HOLD_LAT = 0x0801140Bull; -static const uint64_t EXPLR_SRQ_MBA_FARB7Q = 0x0801141Dull; +static const uint64_t EXPLR_SRQ_ERR_MASK_LAT = 0x0801140Aull; -static const uint64_t EXPLR_SRQ_MBA_FARB8Q = 0x08011420ull; +static const uint64_t EXPLR_SRQ_MBAREF0Q = 0x08011434ull; -static const uint64_t EXPLR_SRQ_MBA_FARB9Q = 0x08011411ull; +static const uint64_t EXPLR_SRQ_MBAREFAQ = 0x08011438ull; -static const uint64_t EXPLR_SRQ_MBA_PMU0Q = 0x08011439ull; +static const uint64_t EXPLR_SRQ_MBARPC0Q = 0x08011436ull; -static const uint64_t EXPLR_SRQ_MBA_PMU1Q = 0x0801143Aull; +static const uint64_t EXPLR_SRQ_MBARSVD0 = 0x08011435ull; -static const uint64_t EXPLR_SRQ_MBA_PMU2Q = 0x0801143Bull; +static const uint64_t EXPLR_SRQ_MBASTR0Q = 0x08011437ull; -static const uint64_t EXPLR_SRQ_MBA_PMU3Q = 0x0801143Cull; +static const uint64_t EXPLR_SRQ_MBA_DBG0Q = 0x0801141Eull; -static const uint64_t EXPLR_SRQ_MBA_PMU4Q = 0x0801143Dull; +static const uint64_t EXPLR_SRQ_MBA_DBG1Q = 0x0801141Full; -static const uint64_t EXPLR_SRQ_MBA_PMU5Q = 0x0801143Eull; +static const uint64_t EXPLR_SRQ_MBA_DSM0Q = 0x0801140Cull; -static const uint64_t EXPLR_SRQ_MBA_PMU6Q = 0x0801143Full; +static const uint64_t EXPLR_SRQ_MBA_ERR_REPORTQ = 0x0801141Cull; -static const uint64_t EXPLR_SRQ_MBA_PMU7Q = 0x08011440ull; +static const uint64_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK = 0x0801142Bull; -static const uint64_t EXPLR_SRQ_MBA_PMU8Q = 0x08011441ull; +static const uint64_t EXPLR_SRQ_MBA_FARB0Q = 0x08011415ull; -static const uint64_t EXPLR_SRQ_MBA_RRQ0Q = 0x08011410ull; +static const uint64_t EXPLR_SRQ_MBA_FARB1Q = 0x08011416ull; -static const uint64_t EXPLR_SRQ_MBA_SYNCCNTLQ = 0x0801142Aull; +static const uint64_t EXPLR_SRQ_MBA_FARB2Q = 0x08011417ull; -static const uint64_t EXPLR_SRQ_MBA_TMR0Q = 0x0801140Dull; +static const uint64_t EXPLR_SRQ_MBA_FARB3Q = 0x08011418ull; -static const uint64_t EXPLR_SRQ_MBA_TMR1Q = 0x0801140Eull; +static const uint64_t EXPLR_SRQ_MBA_FARB4Q = 0x08011419ull; -static const uint64_t EXPLR_SRQ_MBA_TMR2Q = 0x08011431ull; +static const uint64_t EXPLR_SRQ_MBA_FARB5Q = 0x0801141Aull; -static const uint64_t EXPLR_SRQ_MBA_WRQ0Q = 0x0801140Full; +static const uint64_t EXPLR_SRQ_MBA_FARB6Q = 0x0801141Bull; -static const uint64_t EXPLR_SRQ_SRQCFG0 = 0x0801142Eull; +static const uint64_t EXPLR_SRQ_MBA_FARB7Q = 0x0801141Dull; -static const uint64_t EXPLR_SRQ_SRQFIRQ = 0x08011400ull; -static const uint64_t EXPLR_SRQ_SRQFIRQ_AND = 0x08011401ull; +static const uint64_t EXPLR_SRQ_MBA_FARB8Q = 0x08011420ull; -static const uint64_t EXPLR_SRQ_SRQFIRQ_OR = 0x08011402ull; +static const uint64_t EXPLR_SRQ_MBA_FARB9Q = 0x08011411ull; -static const uint64_t EXPLR_SRQ_SRQFIRWOF = 0x08011408ull; +static const uint64_t EXPLR_SRQ_MBA_PMU0Q = 0x08011439ull; -static const uint64_t EXPLR_SRQ_SRQFIR_ACTION0 = 0x08011406ull; +static const uint64_t EXPLR_SRQ_MBA_PMU1Q = 0x0801143Aull; -static const uint64_t EXPLR_SRQ_SRQFIR_ACTION1 = 0x08011407ull; +static const uint64_t EXPLR_SRQ_MBA_PMU2Q = 0x0801143Bull; -static const uint64_t EXPLR_SRQ_SRQFIR_MASK = 0x08011403ull; -static const uint64_t EXPLR_SRQ_SRQFIR_MASK_AND = 0x08011404ull; +static const uint64_t EXPLR_SRQ_MBA_PMU3Q = 0x0801143Cull; -static const uint64_t EXPLR_SRQ_SRQFIR_MASK_OR = 0x08011405ull; +static const uint64_t EXPLR_SRQ_MBA_PMU4Q = 0x0801143Dull; -static const uint64_t EXPLR_SRQ_SRQTRAP0 = 0x0801142Cull; +static const uint64_t EXPLR_SRQ_MBA_PMU5Q = 0x0801143Eull; -static const uint64_t EXPLR_SRQ_SRQTRAP1 = 0x0801142Dull; +static const uint64_t EXPLR_SRQ_MBA_PMU6Q = 0x0801143Full; -static const uint64_t EXPLR_TLXT_ERR_HOLD_LAT = 0x0801240Bull; +static const uint64_t EXPLR_SRQ_MBA_PMU7Q = 0x08011440ull; -static const uint64_t EXPLR_TLXT_ERR_MASK_LAT = 0x0801240Aull; +static const uint64_t EXPLR_SRQ_MBA_PMU8Q = 0x08011441ull; -static const uint64_t EXPLR_TLXT_TLXCFG0 = 0x0801240Cull; +static const uint64_t EXPLR_SRQ_MBA_RRQ0Q = 0x08011410ull; -static const uint64_t EXPLR_TLXT_TLXCFG1 = 0x0801240Dull; +static const uint64_t EXPLR_SRQ_MBA_SYNCCNTLQ = 0x0801142Aull; -static const uint64_t EXPLR_TLXT_TLXCFG2 = 0x0801240Eull; +static const uint64_t EXPLR_SRQ_MBA_TMR0Q = 0x0801140Dull; -static const uint64_t EXPLR_TLXT_TLXFIRACT0 = 0x08012406ull; +static const uint64_t EXPLR_SRQ_MBA_TMR1Q = 0x0801140Eull; -static const uint64_t EXPLR_TLXT_TLXFIRACT1 = 0x08012407ull; +static const uint64_t EXPLR_SRQ_MBA_TMR2Q = 0x08011431ull; -static const uint64_t EXPLR_TLXT_TLXFIRMASK = 0x08012403ull; -static const uint64_t EXPLR_TLXT_TLXFIRMASK_AND = 0x08012404ull; +static const uint64_t EXPLR_SRQ_MBA_WRQ0Q = 0x0801140Full; -static const uint64_t EXPLR_TLXT_TLXFIRMASK_OR = 0x08012405ull; +static const uint64_t EXPLR_SRQ_SRQCFG0 = 0x0801142Eull; -static const uint64_t EXPLR_TLXT_TLXFIRQ = 0x08012400ull; -static const uint64_t EXPLR_TLXT_TLXFIRQ_AND = 0x08012401ull; +static const uint64_t EXPLR_SRQ_SRQFIRQ = 0x08011400ull; -static const uint64_t EXPLR_TLXT_TLXFIRQ_OR = 0x08012402ull; +static const uint64_t EXPLR_SRQ_SRQFIRQ_AND = 0x08011401ull; +static const uint64_t EXPLR_SRQ_SRQFIRQ_OR = 0x08011402ull; -static const uint64_t EXPLR_TLXT_TLXFIRWOF = 0x08012408ull; +static const uint64_t EXPLR_SRQ_SRQFIRWOF = 0x08011408ull; -static const uint64_t EXPLR_TLXT_TLXTINTHLD0 = 0x08012410ull; +static const uint64_t EXPLR_SRQ_SRQFIR_ACTION0 = 0x08011406ull; -static const uint64_t EXPLR_TLXT_TLXTINTHLD1 = 0x08012411ull; +static const uint64_t EXPLR_SRQ_SRQFIR_ACTION1 = 0x08011407ull; -static const uint64_t EXPLR_TLXT_TLXTINTHLD2 = 0x08012412ull; +static const uint64_t EXPLR_SRQ_SRQFIR_MASK = 0x08011403ull; -static const uint64_t EXPLR_TLXT_TLXTINTHLD3 = 0x08012413ull; +static const uint64_t EXPLR_SRQ_SRQFIR_MASK_AND = 0x08011404ull; +static const uint64_t EXPLR_SRQ_SRQFIR_MASK_OR = 0x08011405ull; -static const uint64_t EXPLR_TLXT_TLXTRAP0 = 0x08012424ull; +static const uint64_t EXPLR_SRQ_SRQTRAP0 = 0x0801142Cull; -static const uint64_t EXPLR_TLXT_TLXTRAP1 = 0x08012425ull; +static const uint64_t EXPLR_SRQ_SRQTRAP1 = 0x0801142Dull; -static const uint64_t EXPLR_TLXT_TLXTTRAP2 = 0x08012426ull; +static const uint64_t EXPLR_TLXT_ERR_HOLD_LAT = 0x0801240Bull; -static const uint64_t EXPLR_TLXT_TLXTTRAP3 = 0x08012427ull; +static const uint64_t EXPLR_TLXT_ERR_MASK_LAT = 0x0801240Aull; -static const uint64_t EXPLR_TLXT_TLXTTRAP4 = 0x08012428ull; +static const uint64_t EXPLR_TLXT_TLXCFG0 = 0x0801240Cull; -static const uint64_t EXPLR_TLXT_TLX_ERR0_REPORTQ = 0x0801241Cull; +static const uint64_t EXPLR_TLXT_TLXCFG1 = 0x0801240Dull; -static const uint64_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK = 0x08012414ull; +static const uint64_t EXPLR_TLXT_TLXCFG2 = 0x0801240Eull; -static const uint64_t EXPLR_TLXT_TLX_ERR1_REPORTQ = 0x0801241Dull; +static const uint64_t EXPLR_TLXT_TLXFIRACT0 = 0x08012406ull; -static const uint64_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK = 0x08012415ull; +static const uint64_t EXPLR_TLXT_TLXFIRACT1 = 0x08012407ull; -static const uint64_t EXPLR_TLXT_TLX_ERR2_REPORTQ = 0x0801241Eull; +static const uint64_t EXPLR_TLXT_TLXFIRMASK = 0x08012403ull; -static const uint64_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK = 0x08012416ull; +static const uint64_t EXPLR_TLXT_TLXFIRMASK_AND = 0x08012404ull; +static const uint64_t EXPLR_TLXT_TLXFIRMASK_OR = 0x08012405ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG = 0x08010003ull; +static const uint64_t EXPLR_TLXT_TLXFIRQ = 0x08012400ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG = 0x08010007ull; +static const uint64_t EXPLR_TLXT_TLXFIRQ_AND = 0x08012401ull; +static const uint64_t EXPLR_TLXT_TLXFIRQ_OR = 0x08012402ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1 = 0x080107C1ull; +static const uint64_t EXPLR_TLXT_TLXFIRWOF = 0x08012408ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2 = 0x080107C2ull; +static const uint64_t EXPLR_TLXT_TLXTINTHLD0 = 0x08012410ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_3 = 0x080107C3ull; +static const uint64_t EXPLR_TLXT_TLXTINTHLD1 = 0x08012411ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1 = 0x080107C4ull; +static const uint64_t EXPLR_TLXT_TLXTINTHLD2 = 0x08012412ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2 = 0x080107C5ull; +static const uint64_t EXPLR_TLXT_TLXTINTHLD3 = 0x08012413ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_3 = 0x080107C6ull; +static const uint64_t EXPLR_TLXT_TLXTRAP0 = 0x08012424ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG = 0x080107C0ull; +static const uint64_t EXPLR_TLXT_TLXTRAP1 = 0x08012425ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2 = 0x080107CFull; +static const uint64_t EXPLR_TLXT_TLXTTRAP2 = 0x08012426ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0 = 0x080107CDull; +static const uint64_t EXPLR_TLXT_TLXTTRAP3 = 0x08012427ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1 = 0x080107CEull; +static const uint64_t EXPLR_TLXT_TLXTTRAP4 = 0x08012428ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL = 0x080107D0ull; +static const uint64_t EXPLR_TLXT_TLX_ERR0_REPORTQ = 0x0801241Cull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT = 0x08040015ull; +static const uint64_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK = 0x08012414ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK = 0x08040014ull; +static const uint64_t EXPLR_TLXT_TLX_ERR1_REPORTQ = 0x0801241Dull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK = 0x0801000Aull; +static const uint64_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK = 0x08012415ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK = 0x08040002ull; +static const uint64_t EXPLR_TLXT_TLX_ERR2_REPORTQ = 0x0801241Eull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG = 0x080F0004ull; +static const uint64_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK = 0x08012416ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG = 0x080F0005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG = 0x08010003ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG = 0x080F0001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG = 0x08010007ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG = 0x080F0000ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1 = 0x080107C1ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_RESET_REG = 0x080F0003ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2 = 0x080107C2ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG = 0x080F0002ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_3 = 0x080107C3ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG = 0x0801000Bull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1 = 0x080107C4ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR = 0x0804000Aull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_AND = 0x0804000Bull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2 = 0x080107C5ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OR = 0x0804000Cull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_3 = 0x080107C6ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0 = 0x08040010ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG = 0x080107C0ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1 = 0x08040011ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2 = 0x080107CFull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK = 0x0804000Dull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_AND = 0x0804000Eull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0 = 0x080107CDull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_OR = 0x0804000Full; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1 = 0x080107CEull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR = 0x08040018ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL = 0x080107D0ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK = 0x08040019ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT = 0x08040015ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_MODE_REG = 0x08040008ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK = 0x08040014ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_MSG_REG = 0x08000001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK = 0x0801000Aull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG = 0x080E0005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK = 0x08040002ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG = 0x080E0002ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG = 0x080F0004ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG = 0x080E0001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG = 0x080F0005ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG = 0x080E0000ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG = 0x080F0001ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2 = 0x080E0004ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG = 0x080F0000ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG = 0x080E0003ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_RESET_REG = 0x080F0003ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK = 0x08010002ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG = 0x080F0002ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG = 0x08010000ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG = 0x0801000Bull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG = 0x08010001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR = 0x0804000Aull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_RFIR = 0x08040001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_AND = 0x0804000Bull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OR = 0x0804000Cull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG = 0x08010008ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0 = 0x08040010ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM = 0x08040004ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM1 = 0x08040005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1 = 0x08040011ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM2 = 0x08040006ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK = 0x0804000Dull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK = 0x08040007ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_AND = 0x0804000Eull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_OR = 0x0804000Full; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG = 0x08040017ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR = 0x08040018ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG = 0x08010400ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG = 0x08010401ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK = 0x08040019ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG = 0x08010402ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0 = 0x08010403ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_MODE_REG = 0x08040008ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1 = 0x08010404ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2 = 0x08010405ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_MSG_REG = 0x08000001ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3 = 0x08010406ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4 = 0x08010407ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG = 0x080E0005ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5 = 0x08010408ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9 = 0x08010409ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG = 0x080E0002ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG = 0x08010005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG = 0x080E0001ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG = 0x08010006ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG = 0x080E0000ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_XFIR = 0x08040000ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2 = 0x080E0004ull; -static const uint64_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE = 0x080107D1ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG = 0x080E0003ull; -static const uint64_t EXPLR_WDF_AACR = 0x08012002ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK = 0x08010002ull; -static const uint64_t EXPLR_WDF_AADR = 0x08012003ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG = 0x08010000ull; -static const uint64_t EXPLR_WDF_AAER = 0x08012004ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG = 0x08010001ull; -static const uint64_t EXPLR_WDF_DQS0R = 0x08012000ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_RFIR = 0x08040001ull; -static const uint64_t EXPLR_WDF_DQS1R = 0x08012001ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG = 0x08010008ull; -static const uint64_t EXPLR_WDF_WECR = 0x08012005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM = 0x08040004ull; -static const uint64_t EXPLR_WDF_WERR = 0x08012007ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM1 = 0x08040005ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPATTN_SCOM2 = 0x08040006ull; -static const uint64_t EXPLR_WDF_WESR = 0x08012006ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK = 0x08040007ull; -static const uint64_t EXPLR_WDF_WMSK = 0x08012009ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG = 0x08040017ull; -static const uint64_t EXPLR_WDF_WSPAR = 0x08012008ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG = 0x08010400ull; +//DUPS: 08010400, -static const uint32_t EXPLR_EFUSE_IMAGE_OUT_0 = 0x20B080ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG = 0x08010401ull; +//DUPS: 08010401, +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG = 0x08010402ull; +//DUPS: 08010402, -static const uint32_t EXPLR_EFUSE_IMAGE_OUT_1 = 0x20B084ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0 = 0x08010403ull; +//DUPS: 08010403, +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1 = 0x08010404ull; +//DUPS: 08010404, -static const uint32_t EXPLR_EFUSE_IMAGE_OUT_2 = 0x20B088ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2 = 0x08010405ull; +//DUPS: 08010405, +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3 = 0x08010406ull; +//DUPS: 08010406, -static const uint32_t EXPLR_EFUSE_IMAGE_OUT_3 = 0x20B08Cull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4 = 0x08010407ull; +//DUPS: 08010407, +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5 = 0x08010408ull; +//DUPS: 08010408, -static const uint32_t EXPLR_EFUSE_PE_DATA_0 = 0x20B090ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9 = 0x08010409ull; +//DUPS: 08010409, +static const uint64_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG = 0x08010005ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_1 = 0x20B094ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG = 0x08010006ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_2 = 0x20B098ull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_XFIR = 0x08040000ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_3 = 0x20B09Cull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE = 0x080107D1ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_4 = 0x20B0A0ull; +static const uint64_t EXPLR_WDF_AACR = 0x08012002ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_5 = 0x20B0A4ull; +static const uint64_t EXPLR_WDF_AADR = 0x08012003ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_6 = 0x20B0A8ull; +static const uint64_t EXPLR_WDF_AAER = 0x08012004ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_8 = 0x20B0ACull; +static const uint64_t EXPLR_WDF_DQS0R = 0x08012000ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_9 = 0x20B0B0ull; +static const uint64_t EXPLR_WDF_DQS1R = 0x08012001ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_10 = 0x20B0B4ull; +static const uint64_t EXPLR_WDF_WECR = 0x08012005ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_11 = 0x20B0B8ull; +static const uint64_t EXPLR_WDF_WERR = 0x08012007ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_12 = 0x20B0BCull; +static const uint64_t EXPLR_WDF_WESR = 0x08012006ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_13 = 0x20B0C0ull; +static const uint64_t EXPLR_WDF_WMSK = 0x08012009ull; -static const uint32_t EXPLR_EFUSE_PE_DATA_14 = 0x20B0C4ull; +static const uint64_t EXPLR_WDF_WSPAR = 0x08012008ull; #endif diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H new file mode 100644 index 000000000..e94c8732a --- /dev/null +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H @@ -0,0 +1,3297 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +#ifndef __EXPLR_SCOM_ADDRESSES_FIXES_H +#define __EXPLR_SCOM_ADDRESSES_FIXES_H + +static const uint64_t EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1 = 0x2058ull; + +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U0_P0 = 0x04040340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U0_P0 = 0x04040230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U0_P0 = 0x04040240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U0_P0 = 0x04040200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U1_P0 = 0x04040740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U1_P0 = 0x04040630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U1_P0 = 0x04040640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U1_P0 = 0x04040600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R0_P0 = 0x04040300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R1_P0 = 0x04040700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R2_P0 = 0x04040b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R3_P0 = 0x04040f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R4_P0 = 0x04041300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R5_P0 = 0x04041700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R6_P0 = 0x04041b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R7_P0 = 0x04041f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R8_P0 = 0x04042300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U0_P0 = 0x04044340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U0_P0 = 0x04044230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U0_P0 = 0x04044240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U0_P0 = 0x04044200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U1_P0 = 0x04044740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U1_P0 = 0x04044630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U1_P0 = 0x04044640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U1_P0 = 0x04044600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R0_P0 = 0x04044300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R1_P0 = 0x04044700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R2_P0 = 0x04044b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R3_P0 = 0x04044f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R4_P0 = 0x04045300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R5_P0 = 0x04045700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R6_P0 = 0x04045b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R7_P0 = 0x04045f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R8_P0 = 0x04046300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U0_P0 = 0x04048340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U0_P0 = 0x04048230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U0_P0 = 0x04048240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U0_P0 = 0x04048200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U1_P0 = 0x04048740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U1_P0 = 0x04048630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U1_P0 = 0x04048640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U1_P0 = 0x04048600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R0_P0 = 0x04048300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R1_P0 = 0x04048700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R2_P0 = 0x04048b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R3_P0 = 0x04048f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R4_P0 = 0x04049300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R5_P0 = 0x04049700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R6_P0 = 0x04049b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R7_P0 = 0x04049f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R8_P0 = 0x0404a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U0_P0 = 0x0404c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U0_P0 = 0x0404c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U0_P0 = 0x0404c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U0_P0 = 0x0404c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U1_P0 = 0x0404c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U1_P0 = 0x0404c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U1_P0 = 0x0404c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U1_P0 = 0x0404c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R0_P0 = 0x0404c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R1_P0 = 0x0404c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R2_P0 = 0x0404cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R3_P0 = 0x0404cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R4_P0 = 0x0404d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R5_P0 = 0x0404d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R6_P0 = 0x0404db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R7_P0 = 0x0404df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R8_P0 = 0x0404e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U0_P0 = 0x04050340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U0_P0 = 0x04050230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U0_P0 = 0x04050240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U0_P0 = 0x04050200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U1_P0 = 0x04050740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U1_P0 = 0x04050630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U1_P0 = 0x04050640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U1_P0 = 0x04050600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R0_P0 = 0x04050300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R1_P0 = 0x04050700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R2_P0 = 0x04050b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R3_P0 = 0x04050f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R4_P0 = 0x04051300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R5_P0 = 0x04051700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R6_P0 = 0x04051b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R7_P0 = 0x04051f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R8_P0 = 0x04052300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U0_P0 = 0x04054340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U0_P0 = 0x04054230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U0_P0 = 0x04054240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U0_P0 = 0x04054200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U1_P0 = 0x04054740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U1_P0 = 0x04054630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U1_P0 = 0x04054640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U1_P0 = 0x04054600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R0_P0 = 0x04054300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R1_P0 = 0x04054700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R2_P0 = 0x04054b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R3_P0 = 0x04054f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R4_P0 = 0x04055300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R5_P0 = 0x04055700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R6_P0 = 0x04055b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R7_P0 = 0x04055f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R8_P0 = 0x04056300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U0_P0 = 0x04058340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U0_P0 = 0x04058230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U0_P0 = 0x04058240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U0_P0 = 0x04058200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U1_P0 = 0x04058740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U1_P0 = 0x04058630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U1_P0 = 0x04058640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U1_P0 = 0x04058600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R0_P0 = 0x04058300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R1_P0 = 0x04058700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R2_P0 = 0x04058b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R3_P0 = 0x04058f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R4_P0 = 0x04059300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R5_P0 = 0x04059700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R6_P0 = 0x04059b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R7_P0 = 0x04059f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R8_P0 = 0x0405a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U0_P0 = 0x0405c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U0_P0 = 0x0405c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U0_P0 = 0x0405c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U0_P0 = 0x0405c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U1_P0 = 0x0405c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U1_P0 = 0x0405c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U1_P0 = 0x0405c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U1_P0 = 0x0405c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R0_P0 = 0x0405c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R1_P0 = 0x0405c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R2_P0 = 0x0405cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R3_P0 = 0x0405cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R4_P0 = 0x0405d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R5_P0 = 0x0405d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R6_P0 = 0x0405db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R7_P0 = 0x0405df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R8_P0 = 0x0405e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U0_P0 = 0x04060340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U0_P0 = 0x04060230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U0_P0 = 0x04060240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U0_P0 = 0x04060200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U1_P0 = 0x04060740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U1_P0 = 0x04060630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U1_P0 = 0x04060640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U1_P0 = 0x04060600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R0_P0 = 0x04060300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R1_P0 = 0x04060700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R2_P0 = 0x04060b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R3_P0 = 0x04060f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R4_P0 = 0x04061300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R5_P0 = 0x04061700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R6_P0 = 0x04061b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R7_P0 = 0x04061f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R8_P0 = 0x04062300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U0_P0 = 0x04064340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U0_P0 = 0x04064230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U0_P0 = 0x04064240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U0_P0 = 0x04064200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U1_P0 = 0x04064740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U1_P0 = 0x04064630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U1_P0 = 0x04064640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U1_P0 = 0x04064600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R0_P0 = 0x04064300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R1_P0 = 0x04064700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R2_P0 = 0x04064b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R3_P0 = 0x04064f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R4_P0 = 0x04065300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R5_P0 = 0x04065700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R6_P0 = 0x04065b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R7_P0 = 0x04065f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R8_P0 = 0x04066300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U0_P0 = 0x04040344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U0_P0 = 0x04040234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U0_P0 = 0x04040244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U0_P0 = 0x04040204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U1_P0 = 0x04040744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U1_P0 = 0x04040634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U1_P0 = 0x04040644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U1_P0 = 0x04040604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R0_P0 = 0x04040304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R1_P0 = 0x04040704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R2_P0 = 0x04040b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R3_P0 = 0x04040f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R4_P0 = 0x04041304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R5_P0 = 0x04041704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R6_P0 = 0x04041b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R7_P0 = 0x04041f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R8_P0 = 0x04042304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U0_P0 = 0x04044344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U0_P0 = 0x04044234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U0_P0 = 0x04044244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U0_P0 = 0x04044204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U1_P0 = 0x04044744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U1_P0 = 0x04044634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U1_P0 = 0x04044644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U1_P0 = 0x04044604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R0_P0 = 0x04044304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R1_P0 = 0x04044704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R2_P0 = 0x04044b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R3_P0 = 0x04044f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R4_P0 = 0x04045304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R5_P0 = 0x04045704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R6_P0 = 0x04045b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R7_P0 = 0x04045f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R8_P0 = 0x04046304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U0_P0 = 0x04048344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U0_P0 = 0x04048234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U0_P0 = 0x04048244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U0_P0 = 0x04048204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U1_P0 = 0x04048744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U1_P0 = 0x04048634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U1_P0 = 0x04048644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U1_P0 = 0x04048604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R0_P0 = 0x04048304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R1_P0 = 0x04048704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R2_P0 = 0x04048b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R3_P0 = 0x04048f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R4_P0 = 0x04049304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R5_P0 = 0x04049704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R6_P0 = 0x04049b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R7_P0 = 0x04049f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R8_P0 = 0x0404a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U0_P0 = 0x0404c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U0_P0 = 0x0404c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U0_P0 = 0x0404c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U0_P0 = 0x0404c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U1_P0 = 0x0404c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U1_P0 = 0x0404c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U1_P0 = 0x0404c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U1_P0 = 0x0404c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R0_P0 = 0x0404c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R1_P0 = 0x0404c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R2_P0 = 0x0404cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R3_P0 = 0x0404cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R4_P0 = 0x0404d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R5_P0 = 0x0404d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R6_P0 = 0x0404db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R7_P0 = 0x0404df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R8_P0 = 0x0404e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U0_P0 = 0x04050344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U0_P0 = 0x04050234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U0_P0 = 0x04050244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U0_P0 = 0x04050204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U1_P0 = 0x04050744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U1_P0 = 0x04050634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U1_P0 = 0x04050644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U1_P0 = 0x04050604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R0_P0 = 0x04050304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R1_P0 = 0x04050704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R2_P0 = 0x04050b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R3_P0 = 0x04050f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R4_P0 = 0x04051304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R5_P0 = 0x04051704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R6_P0 = 0x04051b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R7_P0 = 0x04051f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R8_P0 = 0x04052304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U0_P0 = 0x04054344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U0_P0 = 0x04054234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U0_P0 = 0x04054244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U0_P0 = 0x04054204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U1_P0 = 0x04054744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U1_P0 = 0x04054634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U1_P0 = 0x04054644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U1_P0 = 0x04054604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R0_P0 = 0x04054304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R1_P0 = 0x04054704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R2_P0 = 0x04054b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R3_P0 = 0x04054f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R4_P0 = 0x04055304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R5_P0 = 0x04055704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R6_P0 = 0x04055b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R7_P0 = 0x04055f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R8_P0 = 0x04056304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U0_P0 = 0x04058344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U0_P0 = 0x04058234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U0_P0 = 0x04058244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U0_P0 = 0x04058204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U1_P0 = 0x04058744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U1_P0 = 0x04058634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U1_P0 = 0x04058644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U1_P0 = 0x04058604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R0_P0 = 0x04058304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R1_P0 = 0x04058704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R2_P0 = 0x04058b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R3_P0 = 0x04058f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R4_P0 = 0x04059304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R5_P0 = 0x04059704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R6_P0 = 0x04059b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R7_P0 = 0x04059f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R8_P0 = 0x0405a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U0_P0 = 0x0405c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U0_P0 = 0x0405c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U0_P0 = 0x0405c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U0_P0 = 0x0405c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U1_P0 = 0x0405c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U1_P0 = 0x0405c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U1_P0 = 0x0405c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U1_P0 = 0x0405c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R0_P0 = 0x0405c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R1_P0 = 0x0405c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R2_P0 = 0x0405cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R3_P0 = 0x0405cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R4_P0 = 0x0405d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R5_P0 = 0x0405d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R6_P0 = 0x0405db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R7_P0 = 0x0405df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R8_P0 = 0x0405e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U0_P0 = 0x04060344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U0_P0 = 0x04060234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U0_P0 = 0x04060244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U0_P0 = 0x04060204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U1_P0 = 0x04060744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U1_P0 = 0x04060634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U1_P0 = 0x04060644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U1_P0 = 0x04060604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R0_P0 = 0x04060304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R1_P0 = 0x04060704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R2_P0 = 0x04060b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R3_P0 = 0x04060f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R4_P0 = 0x04061304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R5_P0 = 0x04061704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R6_P0 = 0x04061b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R7_P0 = 0x04061f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R8_P0 = 0x04062304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U0_P0 = 0x04064344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U0_P0 = 0x04064234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U0_P0 = 0x04064244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U0_P0 = 0x04064204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U1_P0 = 0x04064744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U1_P0 = 0x04064634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U1_P0 = 0x04064644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U1_P0 = 0x04064604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R0_P0 = 0x04064304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R1_P0 = 0x04064704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R2_P0 = 0x04064b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R3_P0 = 0x04064f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R4_P0 = 0x04065304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R5_P0 = 0x04065704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R6_P0 = 0x04065b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R7_P0 = 0x04065f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R8_P0 = 0x04066304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U0_P0 = 0x04040348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U0_P0 = 0x04040238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U0_P0 = 0x04040248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U0_P0 = 0x04040208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U1_P0 = 0x04040748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U1_P0 = 0x04040638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U1_P0 = 0x04040648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U1_P0 = 0x04040608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R0_P0 = 0x04040308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R1_P0 = 0x04040708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R2_P0 = 0x04040b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R3_P0 = 0x04040f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R4_P0 = 0x04041308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R5_P0 = 0x04041708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R6_P0 = 0x04041b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R7_P0 = 0x04041f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R8_P0 = 0x04042308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U0_P0 = 0x04044348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U0_P0 = 0x04044238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U0_P0 = 0x04044248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U0_P0 = 0x04044208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U1_P0 = 0x04044748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U1_P0 = 0x04044638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U1_P0 = 0x04044648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U1_P0 = 0x04044608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R0_P0 = 0x04044308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R1_P0 = 0x04044708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R2_P0 = 0x04044b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R3_P0 = 0x04044f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R4_P0 = 0x04045308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R5_P0 = 0x04045708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R6_P0 = 0x04045b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R7_P0 = 0x04045f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R8_P0 = 0x04046308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U0_P0 = 0x04048348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U0_P0 = 0x04048238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U0_P0 = 0x04048248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U0_P0 = 0x04048208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U1_P0 = 0x04048748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U1_P0 = 0x04048638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U1_P0 = 0x04048648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U1_P0 = 0x04048608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R0_P0 = 0x04048308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R1_P0 = 0x04048708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R2_P0 = 0x04048b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R3_P0 = 0x04048f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R4_P0 = 0x04049308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R5_P0 = 0x04049708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R6_P0 = 0x04049b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R7_P0 = 0x04049f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R8_P0 = 0x0404a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U0_P0 = 0x0404c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U0_P0 = 0x0404c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U0_P0 = 0x0404c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U0_P0 = 0x0404c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U1_P0 = 0x0404c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U1_P0 = 0x0404c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U1_P0 = 0x0404c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U1_P0 = 0x0404c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R0_P0 = 0x0404c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R1_P0 = 0x0404c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R2_P0 = 0x0404cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R3_P0 = 0x0404cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R4_P0 = 0x0404d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R5_P0 = 0x0404d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R6_P0 = 0x0404db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R7_P0 = 0x0404df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R8_P0 = 0x0404e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U0_P0 = 0x04050348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U0_P0 = 0x04050238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U0_P0 = 0x04050248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U0_P0 = 0x04050208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U1_P0 = 0x04050748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U1_P0 = 0x04050638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U1_P0 = 0x04050648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U1_P0 = 0x04050608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R0_P0 = 0x04050308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R1_P0 = 0x04050708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R2_P0 = 0x04050b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R3_P0 = 0x04050f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R4_P0 = 0x04051308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R5_P0 = 0x04051708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R6_P0 = 0x04051b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R7_P0 = 0x04051f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R8_P0 = 0x04052308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U0_P0 = 0x04054348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U0_P0 = 0x04054238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U0_P0 = 0x04054248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U0_P0 = 0x04054208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U1_P0 = 0x04054748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U1_P0 = 0x04054638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U1_P0 = 0x04054648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U1_P0 = 0x04054608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R0_P0 = 0x04054308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R1_P0 = 0x04054708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R2_P0 = 0x04054b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R3_P0 = 0x04054f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R4_P0 = 0x04055308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R5_P0 = 0x04055708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R6_P0 = 0x04055b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R7_P0 = 0x04055f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R8_P0 = 0x04056308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U0_P0 = 0x04058348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U0_P0 = 0x04058238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U0_P0 = 0x04058248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U0_P0 = 0x04058208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U1_P0 = 0x04058748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U1_P0 = 0x04058638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U1_P0 = 0x04058648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U1_P0 = 0x04058608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R0_P0 = 0x04058308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R1_P0 = 0x04058708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R2_P0 = 0x04058b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R3_P0 = 0x04058f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R4_P0 = 0x04059308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R5_P0 = 0x04059708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R6_P0 = 0x04059b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R7_P0 = 0x04059f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R8_P0 = 0x0405a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U0_P0 = 0x0405c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U0_P0 = 0x0405c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U0_P0 = 0x0405c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U0_P0 = 0x0405c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U1_P0 = 0x0405c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U1_P0 = 0x0405c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U1_P0 = 0x0405c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U1_P0 = 0x0405c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R0_P0 = 0x0405c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R1_P0 = 0x0405c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R2_P0 = 0x0405cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R3_P0 = 0x0405cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R4_P0 = 0x0405d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R5_P0 = 0x0405d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R6_P0 = 0x0405db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R7_P0 = 0x0405df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R8_P0 = 0x0405e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U0_P0 = 0x04060348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U0_P0 = 0x04060238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U0_P0 = 0x04060248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U0_P0 = 0x04060208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U1_P0 = 0x04060748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U1_P0 = 0x04060638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U1_P0 = 0x04060648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U1_P0 = 0x04060608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R0_P0 = 0x04060308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R1_P0 = 0x04060708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R2_P0 = 0x04060b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R3_P0 = 0x04060f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R4_P0 = 0x04061308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R5_P0 = 0x04061708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R6_P0 = 0x04061b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R7_P0 = 0x04061f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R8_P0 = 0x04062308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U0_P0 = 0x04064348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U0_P0 = 0x04064238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U0_P0 = 0x04064248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U0_P0 = 0x04064208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U1_P0 = 0x04064748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U1_P0 = 0x04064638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U1_P0 = 0x04064648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U1_P0 = 0x04064608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R0_P0 = 0x04064308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R1_P0 = 0x04064708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R2_P0 = 0x04064b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R3_P0 = 0x04064f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R4_P0 = 0x04065308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R5_P0 = 0x04065708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R6_P0 = 0x04065b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R7_P0 = 0x04065f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R8_P0 = 0x04066308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U0_P0 = 0x0404034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U0_P0 = 0x0404023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U0_P0 = 0x0404024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U0_P0 = 0x0404020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U1_P0 = 0x0404074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U1_P0 = 0x0404063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U1_P0 = 0x0404064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U1_P0 = 0x0404060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R0_P0 = 0x0404030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R1_P0 = 0x0404070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R2_P0 = 0x04040b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R3_P0 = 0x04040f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R4_P0 = 0x0404130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R5_P0 = 0x0404170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R6_P0 = 0x04041b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R7_P0 = 0x04041f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R8_P0 = 0x0404230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U0_P0 = 0x0404434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U0_P0 = 0x0404423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U0_P0 = 0x0404424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U0_P0 = 0x0404420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U1_P0 = 0x0404474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U1_P0 = 0x0404463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U1_P0 = 0x0404464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U1_P0 = 0x0404460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R0_P0 = 0x0404430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R1_P0 = 0x0404470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R2_P0 = 0x04044b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R3_P0 = 0x04044f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R4_P0 = 0x0404530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R5_P0 = 0x0404570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R6_P0 = 0x04045b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R7_P0 = 0x04045f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R8_P0 = 0x0404630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U0_P0 = 0x0404834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U0_P0 = 0x0404823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U0_P0 = 0x0404824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U0_P0 = 0x0404820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U1_P0 = 0x0404874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U1_P0 = 0x0404863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U1_P0 = 0x0404864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U1_P0 = 0x0404860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R0_P0 = 0x0404830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R1_P0 = 0x0404870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R2_P0 = 0x04048b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R3_P0 = 0x04048f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R4_P0 = 0x0404930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R5_P0 = 0x0404970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R6_P0 = 0x04049b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R7_P0 = 0x04049f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R8_P0 = 0x0404a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U0_P0 = 0x0404c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U0_P0 = 0x0404c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U0_P0 = 0x0404c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U0_P0 = 0x0404c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U1_P0 = 0x0404c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U1_P0 = 0x0404c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U1_P0 = 0x0404c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U1_P0 = 0x0404c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R0_P0 = 0x0404c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R1_P0 = 0x0404c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R2_P0 = 0x0404cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R3_P0 = 0x0404cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R4_P0 = 0x0404d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R5_P0 = 0x0404d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R6_P0 = 0x0404db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R7_P0 = 0x0404df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R8_P0 = 0x0404e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U0_P0 = 0x0405034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U0_P0 = 0x0405023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U0_P0 = 0x0405024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U0_P0 = 0x0405020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U1_P0 = 0x0405074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U1_P0 = 0x0405063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U1_P0 = 0x0405064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U1_P0 = 0x0405060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R0_P0 = 0x0405030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R1_P0 = 0x0405070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R2_P0 = 0x04050b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R3_P0 = 0x04050f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R4_P0 = 0x0405130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R5_P0 = 0x0405170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R6_P0 = 0x04051b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R7_P0 = 0x04051f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R8_P0 = 0x0405230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U0_P0 = 0x0405434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U0_P0 = 0x0405423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U0_P0 = 0x0405424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U0_P0 = 0x0405420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U1_P0 = 0x0405474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U1_P0 = 0x0405463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U1_P0 = 0x0405464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U1_P0 = 0x0405460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R0_P0 = 0x0405430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R1_P0 = 0x0405470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R2_P0 = 0x04054b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R3_P0 = 0x04054f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R4_P0 = 0x0405530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R5_P0 = 0x0405570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R6_P0 = 0x04055b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R7_P0 = 0x04055f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R8_P0 = 0x0405630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U0_P0 = 0x0405834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U0_P0 = 0x0405823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U0_P0 = 0x0405824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U0_P0 = 0x0405820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U1_P0 = 0x0405874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U1_P0 = 0x0405863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U1_P0 = 0x0405864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U1_P0 = 0x0405860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R0_P0 = 0x0405830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R1_P0 = 0x0405870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R2_P0 = 0x04058b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R3_P0 = 0x04058f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R4_P0 = 0x0405930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R5_P0 = 0x0405970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R6_P0 = 0x04059b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R7_P0 = 0x04059f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R8_P0 = 0x0405a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U0_P0 = 0x0405c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U0_P0 = 0x0405c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U0_P0 = 0x0405c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U0_P0 = 0x0405c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U1_P0 = 0x0405c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U1_P0 = 0x0405c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U1_P0 = 0x0405c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U1_P0 = 0x0405c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R0_P0 = 0x0405c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R1_P0 = 0x0405c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R2_P0 = 0x0405cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R3_P0 = 0x0405cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R4_P0 = 0x0405d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R5_P0 = 0x0405d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R6_P0 = 0x0405db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R7_P0 = 0x0405df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R8_P0 = 0x0405e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U0_P0 = 0x0406034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U0_P0 = 0x0406023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U0_P0 = 0x0406024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U0_P0 = 0x0406020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U1_P0 = 0x0406074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U1_P0 = 0x0406063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U1_P0 = 0x0406064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U1_P0 = 0x0406060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R0_P0 = 0x0406030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R1_P0 = 0x0406070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R2_P0 = 0x04060b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R3_P0 = 0x04060f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R4_P0 = 0x0406130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R5_P0 = 0x0406170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R6_P0 = 0x04061b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R7_P0 = 0x04061f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R8_P0 = 0x0406230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U0_P0 = 0x0406434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U0_P0 = 0x0406423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U0_P0 = 0x0406424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U0_P0 = 0x0406420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U1_P0 = 0x0406474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U1_P0 = 0x0406463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U1_P0 = 0x0406464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U1_P0 = 0x0406460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R0_P0 = 0x0406430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R1_P0 = 0x0406470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R2_P0 = 0x04064b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R3_P0 = 0x04064f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R4_P0 = 0x0406530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R5_P0 = 0x0406570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R6_P0 = 0x04065b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R7_P0 = 0x04065f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R8_P0 = 0x0406630cull; +static const uint64_t EXP_DDR4_PHY_ANIB0_ATXDLY_P0 = 0x04000200ull; +static const uint64_t EXP_DDR4_PHY_ANIB1_ATXDLY_P0 = 0x04004200ull; +static const uint64_t EXP_DDR4_PHY_ANIB2_ATXDLY_P0 = 0x04008200ull; +static const uint64_t EXP_DDR4_PHY_ANIB3_ATXDLY_P0 = 0x0400c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB4_ATXDLY_P0 = 0x04010200ull; +static const uint64_t EXP_DDR4_PHY_ANIB5_ATXDLY_P0 = 0x04014200ull; +static const uint64_t EXP_DDR4_PHY_ANIB6_ATXDLY_P0 = 0x04018200ull; +static const uint64_t EXP_DDR4_PHY_ANIB7_ATXDLY_P0 = 0x0401c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB8_ATXDLY_P0 = 0x04020200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U0_P1 = 0x04440340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U0_P1 = 0x04440230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U0_P1 = 0x04440240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U0_P1 = 0x04440200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U1_P1 = 0x04440740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U1_P1 = 0x04440630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U1_P1 = 0x04440640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U1_P1 = 0x04440600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R0_P1 = 0x04440300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R1_P1 = 0x04440700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R2_P1 = 0x04440b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R3_P1 = 0x04440f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R4_P1 = 0x04441300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R5_P1 = 0x04441700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R6_P1 = 0x04441b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R7_P1 = 0x04441f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R8_P1 = 0x04442300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U0_P1 = 0x04444340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U0_P1 = 0x04444230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U0_P1 = 0x04444240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U0_P1 = 0x04444200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U1_P1 = 0x04444740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U1_P1 = 0x04444630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U1_P1 = 0x04444640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U1_P1 = 0x04444600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R0_P1 = 0x04444300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R1_P1 = 0x04444700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R2_P1 = 0x04444b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R3_P1 = 0x04444f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R4_P1 = 0x04445300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R5_P1 = 0x04445700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R6_P1 = 0x04445b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R7_P1 = 0x04445f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R8_P1 = 0x04446300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U0_P1 = 0x04448340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U0_P1 = 0x04448230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U0_P1 = 0x04448240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U0_P1 = 0x04448200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U1_P1 = 0x04448740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U1_P1 = 0x04448630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U1_P1 = 0x04448640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U1_P1 = 0x04448600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R0_P1 = 0x04448300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R1_P1 = 0x04448700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R2_P1 = 0x04448b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R3_P1 = 0x04448f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R4_P1 = 0x04449300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R5_P1 = 0x04449700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R6_P1 = 0x04449b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R7_P1 = 0x04449f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R8_P1 = 0x0444a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U0_P1 = 0x0444c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U0_P1 = 0x0444c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U0_P1 = 0x0444c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U0_P1 = 0x0444c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U1_P1 = 0x0444c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U1_P1 = 0x0444c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U1_P1 = 0x0444c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U1_P1 = 0x0444c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R0_P1 = 0x0444c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R1_P1 = 0x0444c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R2_P1 = 0x0444cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R3_P1 = 0x0444cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R4_P1 = 0x0444d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R5_P1 = 0x0444d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R6_P1 = 0x0444db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R7_P1 = 0x0444df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R8_P1 = 0x0444e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U0_P1 = 0x04450340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U0_P1 = 0x04450230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U0_P1 = 0x04450240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U0_P1 = 0x04450200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U1_P1 = 0x04450740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U1_P1 = 0x04450630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U1_P1 = 0x04450640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U1_P1 = 0x04450600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R0_P1 = 0x04450300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R1_P1 = 0x04450700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R2_P1 = 0x04450b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R3_P1 = 0x04450f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R4_P1 = 0x04451300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R5_P1 = 0x04451700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R6_P1 = 0x04451b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R7_P1 = 0x04451f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R8_P1 = 0x04452300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U0_P1 = 0x04454340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U0_P1 = 0x04454230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U0_P1 = 0x04454240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U0_P1 = 0x04454200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U1_P1 = 0x04454740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U1_P1 = 0x04454630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U1_P1 = 0x04454640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U1_P1 = 0x04454600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R0_P1 = 0x04454300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R1_P1 = 0x04454700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R2_P1 = 0x04454b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R3_P1 = 0x04454f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R4_P1 = 0x04455300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R5_P1 = 0x04455700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R6_P1 = 0x04455b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R7_P1 = 0x04455f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R8_P1 = 0x04456300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U0_P1 = 0x04458340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U0_P1 = 0x04458230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U0_P1 = 0x04458240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U0_P1 = 0x04458200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U1_P1 = 0x04458740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U1_P1 = 0x04458630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U1_P1 = 0x04458640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U1_P1 = 0x04458600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R0_P1 = 0x04458300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R1_P1 = 0x04458700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R2_P1 = 0x04458b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R3_P1 = 0x04458f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R4_P1 = 0x04459300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R5_P1 = 0x04459700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R6_P1 = 0x04459b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R7_P1 = 0x04459f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R8_P1 = 0x0445a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U0_P1 = 0x0445c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U0_P1 = 0x0445c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U0_P1 = 0x0445c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U0_P1 = 0x0445c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U1_P1 = 0x0445c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U1_P1 = 0x0445c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U1_P1 = 0x0445c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U1_P1 = 0x0445c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R0_P1 = 0x0445c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R1_P1 = 0x0445c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R2_P1 = 0x0445cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R3_P1 = 0x0445cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R4_P1 = 0x0445d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R5_P1 = 0x0445d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R6_P1 = 0x0445db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R7_P1 = 0x0445df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R8_P1 = 0x0445e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U0_P1 = 0x04460340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U0_P1 = 0x04460230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U0_P1 = 0x04460240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U0_P1 = 0x04460200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U1_P1 = 0x04460740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U1_P1 = 0x04460630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U1_P1 = 0x04460640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U1_P1 = 0x04460600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R0_P1 = 0x04460300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R1_P1 = 0x04460700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R2_P1 = 0x04460b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R3_P1 = 0x04460f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R4_P1 = 0x04461300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R5_P1 = 0x04461700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R6_P1 = 0x04461b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R7_P1 = 0x04461f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R8_P1 = 0x04462300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U0_P1 = 0x04464340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U0_P1 = 0x04464230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U0_P1 = 0x04464240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U0_P1 = 0x04464200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U1_P1 = 0x04464740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U1_P1 = 0x04464630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U1_P1 = 0x04464640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U1_P1 = 0x04464600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R0_P1 = 0x04464300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R1_P1 = 0x04464700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R2_P1 = 0x04464b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R3_P1 = 0x04464f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R4_P1 = 0x04465300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R5_P1 = 0x04465700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R6_P1 = 0x04465b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R7_P1 = 0x04465f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R8_P1 = 0x04466300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U0_P1 = 0x04440344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U0_P1 = 0x04440234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U0_P1 = 0x04440244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U0_P1 = 0x04440204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U1_P1 = 0x04440744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U1_P1 = 0x04440634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U1_P1 = 0x04440644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U1_P1 = 0x04440604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R0_P1 = 0x04440304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R1_P1 = 0x04440704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R2_P1 = 0x04440b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R3_P1 = 0x04440f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R4_P1 = 0x04441304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R5_P1 = 0x04441704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R6_P1 = 0x04441b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R7_P1 = 0x04441f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R8_P1 = 0x04442304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U0_P1 = 0x04444344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U0_P1 = 0x04444234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U0_P1 = 0x04444244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U0_P1 = 0x04444204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U1_P1 = 0x04444744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U1_P1 = 0x04444634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U1_P1 = 0x04444644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U1_P1 = 0x04444604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R0_P1 = 0x04444304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R1_P1 = 0x04444704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R2_P1 = 0x04444b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R3_P1 = 0x04444f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R4_P1 = 0x04445304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R5_P1 = 0x04445704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R6_P1 = 0x04445b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R7_P1 = 0x04445f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R8_P1 = 0x04446304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U0_P1 = 0x04448344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U0_P1 = 0x04448234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U0_P1 = 0x04448244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U0_P1 = 0x04448204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U1_P1 = 0x04448744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U1_P1 = 0x04448634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U1_P1 = 0x04448644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U1_P1 = 0x04448604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R0_P1 = 0x04448304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R1_P1 = 0x04448704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R2_P1 = 0x04448b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R3_P1 = 0x04448f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R4_P1 = 0x04449304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R5_P1 = 0x04449704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R6_P1 = 0x04449b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R7_P1 = 0x04449f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R8_P1 = 0x0444a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U0_P1 = 0x0444c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U0_P1 = 0x0444c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U0_P1 = 0x0444c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U0_P1 = 0x0444c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U1_P1 = 0x0444c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U1_P1 = 0x0444c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U1_P1 = 0x0444c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U1_P1 = 0x0444c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R0_P1 = 0x0444c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R1_P1 = 0x0444c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R2_P1 = 0x0444cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R3_P1 = 0x0444cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R4_P1 = 0x0444d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R5_P1 = 0x0444d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R6_P1 = 0x0444db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R7_P1 = 0x0444df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R8_P1 = 0x0444e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U0_P1 = 0x04450344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U0_P1 = 0x04450234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U0_P1 = 0x04450244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U0_P1 = 0x04450204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U1_P1 = 0x04450744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U1_P1 = 0x04450634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U1_P1 = 0x04450644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U1_P1 = 0x04450604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R0_P1 = 0x04450304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R1_P1 = 0x04450704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R2_P1 = 0x04450b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R3_P1 = 0x04450f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R4_P1 = 0x04451304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R5_P1 = 0x04451704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R6_P1 = 0x04451b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R7_P1 = 0x04451f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R8_P1 = 0x04452304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U0_P1 = 0x04454344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U0_P1 = 0x04454234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U0_P1 = 0x04454244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U0_P1 = 0x04454204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U1_P1 = 0x04454744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U1_P1 = 0x04454634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U1_P1 = 0x04454644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U1_P1 = 0x04454604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R0_P1 = 0x04454304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R1_P1 = 0x04454704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R2_P1 = 0x04454b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R3_P1 = 0x04454f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R4_P1 = 0x04455304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R5_P1 = 0x04455704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R6_P1 = 0x04455b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R7_P1 = 0x04455f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R8_P1 = 0x04456304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U0_P1 = 0x04458344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U0_P1 = 0x04458234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U0_P1 = 0x04458244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U0_P1 = 0x04458204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U1_P1 = 0x04458744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U1_P1 = 0x04458634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U1_P1 = 0x04458644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U1_P1 = 0x04458604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R0_P1 = 0x04458304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R1_P1 = 0x04458704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R2_P1 = 0x04458b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R3_P1 = 0x04458f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R4_P1 = 0x04459304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R5_P1 = 0x04459704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R6_P1 = 0x04459b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R7_P1 = 0x04459f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R8_P1 = 0x0445a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U0_P1 = 0x0445c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U0_P1 = 0x0445c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U0_P1 = 0x0445c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U0_P1 = 0x0445c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U1_P1 = 0x0445c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U1_P1 = 0x0445c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U1_P1 = 0x0445c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U1_P1 = 0x0445c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R0_P1 = 0x0445c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R1_P1 = 0x0445c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R2_P1 = 0x0445cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R3_P1 = 0x0445cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R4_P1 = 0x0445d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R5_P1 = 0x0445d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R6_P1 = 0x0445db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R7_P1 = 0x0445df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R8_P1 = 0x0445e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U0_P1 = 0x04460344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U0_P1 = 0x04460234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U0_P1 = 0x04460244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U0_P1 = 0x04460204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U1_P1 = 0x04460744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U1_P1 = 0x04460634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U1_P1 = 0x04460644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U1_P1 = 0x04460604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R0_P1 = 0x04460304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R1_P1 = 0x04460704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R2_P1 = 0x04460b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R3_P1 = 0x04460f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R4_P1 = 0x04461304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R5_P1 = 0x04461704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R6_P1 = 0x04461b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R7_P1 = 0x04461f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R8_P1 = 0x04462304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U0_P1 = 0x04464344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U0_P1 = 0x04464234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U0_P1 = 0x04464244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U0_P1 = 0x04464204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U1_P1 = 0x04464744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U1_P1 = 0x04464634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U1_P1 = 0x04464644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U1_P1 = 0x04464604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R0_P1 = 0x04464304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R1_P1 = 0x04464704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R2_P1 = 0x04464b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R3_P1 = 0x04464f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R4_P1 = 0x04465304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R5_P1 = 0x04465704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R6_P1 = 0x04465b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R7_P1 = 0x04465f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R8_P1 = 0x04466304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U0_P1 = 0x04440348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U0_P1 = 0x04440238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U0_P1 = 0x04440248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U0_P1 = 0x04440208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U1_P1 = 0x04440748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U1_P1 = 0x04440638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U1_P1 = 0x04440648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U1_P1 = 0x04440608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R0_P1 = 0x04440308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R1_P1 = 0x04440708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R2_P1 = 0x04440b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R3_P1 = 0x04440f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R4_P1 = 0x04441308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R5_P1 = 0x04441708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R6_P1 = 0x04441b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R7_P1 = 0x04441f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R8_P1 = 0x04442308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U0_P1 = 0x04444348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U0_P1 = 0x04444238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U0_P1 = 0x04444248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U0_P1 = 0x04444208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U1_P1 = 0x04444748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U1_P1 = 0x04444638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U1_P1 = 0x04444648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U1_P1 = 0x04444608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R0_P1 = 0x04444308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R1_P1 = 0x04444708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R2_P1 = 0x04444b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R3_P1 = 0x04444f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R4_P1 = 0x04445308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R5_P1 = 0x04445708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R6_P1 = 0x04445b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R7_P1 = 0x04445f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R8_P1 = 0x04446308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U0_P1 = 0x04448348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U0_P1 = 0x04448238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U0_P1 = 0x04448248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U0_P1 = 0x04448208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U1_P1 = 0x04448748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U1_P1 = 0x04448638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U1_P1 = 0x04448648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U1_P1 = 0x04448608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R0_P1 = 0x04448308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R1_P1 = 0x04448708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R2_P1 = 0x04448b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R3_P1 = 0x04448f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R4_P1 = 0x04449308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R5_P1 = 0x04449708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R6_P1 = 0x04449b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R7_P1 = 0x04449f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R8_P1 = 0x0444a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U0_P1 = 0x0444c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U0_P1 = 0x0444c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U0_P1 = 0x0444c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U0_P1 = 0x0444c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U1_P1 = 0x0444c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U1_P1 = 0x0444c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U1_P1 = 0x0444c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U1_P1 = 0x0444c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R0_P1 = 0x0444c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R1_P1 = 0x0444c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R2_P1 = 0x0444cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R3_P1 = 0x0444cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R4_P1 = 0x0444d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R5_P1 = 0x0444d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R6_P1 = 0x0444db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R7_P1 = 0x0444df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R8_P1 = 0x0444e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U0_P1 = 0x04450348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U0_P1 = 0x04450238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U0_P1 = 0x04450248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U0_P1 = 0x04450208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U1_P1 = 0x04450748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U1_P1 = 0x04450638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U1_P1 = 0x04450648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U1_P1 = 0x04450608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R0_P1 = 0x04450308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R1_P1 = 0x04450708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R2_P1 = 0x04450b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R3_P1 = 0x04450f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R4_P1 = 0x04451308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R5_P1 = 0x04451708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R6_P1 = 0x04451b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R7_P1 = 0x04451f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R8_P1 = 0x04452308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U0_P1 = 0x04454348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U0_P1 = 0x04454238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U0_P1 = 0x04454248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U0_P1 = 0x04454208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U1_P1 = 0x04454748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U1_P1 = 0x04454638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U1_P1 = 0x04454648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U1_P1 = 0x04454608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R0_P1 = 0x04454308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R1_P1 = 0x04454708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R2_P1 = 0x04454b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R3_P1 = 0x04454f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R4_P1 = 0x04455308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R5_P1 = 0x04455708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R6_P1 = 0x04455b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R7_P1 = 0x04455f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R8_P1 = 0x04456308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U0_P1 = 0x04458348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U0_P1 = 0x04458238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U0_P1 = 0x04458248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U0_P1 = 0x04458208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U1_P1 = 0x04458748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U1_P1 = 0x04458638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U1_P1 = 0x04458648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U1_P1 = 0x04458608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R0_P1 = 0x04458308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R1_P1 = 0x04458708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R2_P1 = 0x04458b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R3_P1 = 0x04458f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R4_P1 = 0x04459308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R5_P1 = 0x04459708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R6_P1 = 0x04459b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R7_P1 = 0x04459f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R8_P1 = 0x0445a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U0_P1 = 0x0445c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U0_P1 = 0x0445c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U0_P1 = 0x0445c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U0_P1 = 0x0445c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U1_P1 = 0x0445c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U1_P1 = 0x0445c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U1_P1 = 0x0445c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U1_P1 = 0x0445c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R0_P1 = 0x0445c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R1_P1 = 0x0445c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R2_P1 = 0x0445cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R3_P1 = 0x0445cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R4_P1 = 0x0445d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R5_P1 = 0x0445d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R6_P1 = 0x0445db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R7_P1 = 0x0445df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R8_P1 = 0x0445e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U0_P1 = 0x04460348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U0_P1 = 0x04460238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U0_P1 = 0x04460248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U0_P1 = 0x04460208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U1_P1 = 0x04460748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U1_P1 = 0x04460638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U1_P1 = 0x04460648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U1_P1 = 0x04460608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R0_P1 = 0x04460308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R1_P1 = 0x04460708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R2_P1 = 0x04460b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R3_P1 = 0x04460f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R4_P1 = 0x04461308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R5_P1 = 0x04461708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R6_P1 = 0x04461b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R7_P1 = 0x04461f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R8_P1 = 0x04462308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U0_P1 = 0x04464348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U0_P1 = 0x04464238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U0_P1 = 0x04464248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U0_P1 = 0x04464208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U1_P1 = 0x04464748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U1_P1 = 0x04464638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U1_P1 = 0x04464648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U1_P1 = 0x04464608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R0_P1 = 0x04464308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R1_P1 = 0x04464708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R2_P1 = 0x04464b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R3_P1 = 0x04464f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R4_P1 = 0x04465308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R5_P1 = 0x04465708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R6_P1 = 0x04465b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R7_P1 = 0x04465f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R8_P1 = 0x04466308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U0_P1 = 0x0444034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U0_P1 = 0x0444023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U0_P1 = 0x0444024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U0_P1 = 0x0444020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U1_P1 = 0x0444074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U1_P1 = 0x0444063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U1_P1 = 0x0444064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U1_P1 = 0x0444060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R0_P1 = 0x0444030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R1_P1 = 0x0444070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R2_P1 = 0x04440b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R3_P1 = 0x04440f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R4_P1 = 0x0444130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R5_P1 = 0x0444170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R6_P1 = 0x04441b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R7_P1 = 0x04441f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R8_P1 = 0x0444230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U0_P1 = 0x0444434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U0_P1 = 0x0444423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U0_P1 = 0x0444424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U0_P1 = 0x0444420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U1_P1 = 0x0444474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U1_P1 = 0x0444463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U1_P1 = 0x0444464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U1_P1 = 0x0444460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R0_P1 = 0x0444430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R1_P1 = 0x0444470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R2_P1 = 0x04444b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R3_P1 = 0x04444f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R4_P1 = 0x0444530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R5_P1 = 0x0444570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R6_P1 = 0x04445b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R7_P1 = 0x04445f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R8_P1 = 0x0444630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U0_P1 = 0x0444834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U0_P1 = 0x0444823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U0_P1 = 0x0444824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U0_P1 = 0x0444820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U1_P1 = 0x0444874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U1_P1 = 0x0444863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U1_P1 = 0x0444864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U1_P1 = 0x0444860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R0_P1 = 0x0444830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R1_P1 = 0x0444870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R2_P1 = 0x04448b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R3_P1 = 0x04448f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R4_P1 = 0x0444930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R5_P1 = 0x0444970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R6_P1 = 0x04449b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R7_P1 = 0x04449f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R8_P1 = 0x0444a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U0_P1 = 0x0444c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U0_P1 = 0x0444c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U0_P1 = 0x0444c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U0_P1 = 0x0444c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U1_P1 = 0x0444c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U1_P1 = 0x0444c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U1_P1 = 0x0444c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U1_P1 = 0x0444c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R0_P1 = 0x0444c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R1_P1 = 0x0444c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R2_P1 = 0x0444cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R3_P1 = 0x0444cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R4_P1 = 0x0444d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R5_P1 = 0x0444d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R6_P1 = 0x0444db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R7_P1 = 0x0444df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R8_P1 = 0x0444e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U0_P1 = 0x0445034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U0_P1 = 0x0445023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U0_P1 = 0x0445024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U0_P1 = 0x0445020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U1_P1 = 0x0445074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U1_P1 = 0x0445063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U1_P1 = 0x0445064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U1_P1 = 0x0445060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R0_P1 = 0x0445030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R1_P1 = 0x0445070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R2_P1 = 0x04450b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R3_P1 = 0x04450f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R4_P1 = 0x0445130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R5_P1 = 0x0445170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R6_P1 = 0x04451b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R7_P1 = 0x04451f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R8_P1 = 0x0445230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U0_P1 = 0x0445434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U0_P1 = 0x0445423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U0_P1 = 0x0445424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U0_P1 = 0x0445420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U1_P1 = 0x0445474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U1_P1 = 0x0445463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U1_P1 = 0x0445464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U1_P1 = 0x0445460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R0_P1 = 0x0445430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R1_P1 = 0x0445470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R2_P1 = 0x04454b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R3_P1 = 0x04454f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R4_P1 = 0x0445530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R5_P1 = 0x0445570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R6_P1 = 0x04455b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R7_P1 = 0x04455f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R8_P1 = 0x0445630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U0_P1 = 0x0445834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U0_P1 = 0x0445823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U0_P1 = 0x0445824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U0_P1 = 0x0445820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U1_P1 = 0x0445874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U1_P1 = 0x0445863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U1_P1 = 0x0445864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U1_P1 = 0x0445860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R0_P1 = 0x0445830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R1_P1 = 0x0445870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R2_P1 = 0x04458b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R3_P1 = 0x04458f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R4_P1 = 0x0445930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R5_P1 = 0x0445970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R6_P1 = 0x04459b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R7_P1 = 0x04459f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R8_P1 = 0x0445a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U0_P1 = 0x0445c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U0_P1 = 0x0445c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U0_P1 = 0x0445c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U0_P1 = 0x0445c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U1_P1 = 0x0445c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U1_P1 = 0x0445c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U1_P1 = 0x0445c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U1_P1 = 0x0445c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R0_P1 = 0x0445c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R1_P1 = 0x0445c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R2_P1 = 0x0445cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R3_P1 = 0x0445cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R4_P1 = 0x0445d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R5_P1 = 0x0445d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R6_P1 = 0x0445db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R7_P1 = 0x0445df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R8_P1 = 0x0445e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U0_P1 = 0x0446034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U0_P1 = 0x0446023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U0_P1 = 0x0446024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U0_P1 = 0x0446020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U1_P1 = 0x0446074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U1_P1 = 0x0446063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U1_P1 = 0x0446064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U1_P1 = 0x0446060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R0_P1 = 0x0446030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R1_P1 = 0x0446070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R2_P1 = 0x04460b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R3_P1 = 0x04460f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R4_P1 = 0x0446130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R5_P1 = 0x0446170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R6_P1 = 0x04461b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R7_P1 = 0x04461f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R8_P1 = 0x0446230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U0_P1 = 0x0446434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U0_P1 = 0x0446423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U0_P1 = 0x0446424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U0_P1 = 0x0446420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U1_P1 = 0x0446474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U1_P1 = 0x0446463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U1_P1 = 0x0446464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U1_P1 = 0x0446460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R0_P1 = 0x0446430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R1_P1 = 0x0446470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R2_P1 = 0x04464b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R3_P1 = 0x04464f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R4_P1 = 0x0446530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R5_P1 = 0x0446570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R6_P1 = 0x04465b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R7_P1 = 0x04465f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R8_P1 = 0x0446630cull; +static const uint64_t EXP_DDR4_PHY_ANIB0_ATXDLY_P1 = 0x04400200ull; +static const uint64_t EXP_DDR4_PHY_ANIB1_ATXDLY_P1 = 0x04404200ull; +static const uint64_t EXP_DDR4_PHY_ANIB2_ATXDLY_P1 = 0x04408200ull; +static const uint64_t EXP_DDR4_PHY_ANIB3_ATXDLY_P1 = 0x0440c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB4_ATXDLY_P1 = 0x04410200ull; +static const uint64_t EXP_DDR4_PHY_ANIB5_ATXDLY_P1 = 0x04414200ull; +static const uint64_t EXP_DDR4_PHY_ANIB6_ATXDLY_P1 = 0x04418200ull; +static const uint64_t EXP_DDR4_PHY_ANIB7_ATXDLY_P1 = 0x0441c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB8_ATXDLY_P1 = 0x04420200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U0_P2 = 0x04840340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U0_P2 = 0x04840230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U0_P2 = 0x04840240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U0_P2 = 0x04840200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U1_P2 = 0x04840740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U1_P2 = 0x04840630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U1_P2 = 0x04840640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U1_P2 = 0x04840600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R0_P2 = 0x04840300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R1_P2 = 0x04840700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R2_P2 = 0x04840b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R3_P2 = 0x04840f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R4_P2 = 0x04841300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R5_P2 = 0x04841700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R6_P2 = 0x04841b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R7_P2 = 0x04841f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R8_P2 = 0x04842300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U0_P2 = 0x04844340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U0_P2 = 0x04844230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U0_P2 = 0x04844240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U0_P2 = 0x04844200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U1_P2 = 0x04844740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U1_P2 = 0x04844630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U1_P2 = 0x04844640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U1_P2 = 0x04844600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R0_P2 = 0x04844300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R1_P2 = 0x04844700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R2_P2 = 0x04844b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R3_P2 = 0x04844f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R4_P2 = 0x04845300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R5_P2 = 0x04845700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R6_P2 = 0x04845b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R7_P2 = 0x04845f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R8_P2 = 0x04846300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U0_P2 = 0x04848340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U0_P2 = 0x04848230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U0_P2 = 0x04848240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U0_P2 = 0x04848200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U1_P2 = 0x04848740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U1_P2 = 0x04848630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U1_P2 = 0x04848640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U1_P2 = 0x04848600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R0_P2 = 0x04848300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R1_P2 = 0x04848700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R2_P2 = 0x04848b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R3_P2 = 0x04848f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R4_P2 = 0x04849300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R5_P2 = 0x04849700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R6_P2 = 0x04849b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R7_P2 = 0x04849f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R8_P2 = 0x0484a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U0_P2 = 0x0484c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U0_P2 = 0x0484c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U0_P2 = 0x0484c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U0_P2 = 0x0484c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U1_P2 = 0x0484c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U1_P2 = 0x0484c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U1_P2 = 0x0484c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U1_P2 = 0x0484c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R0_P2 = 0x0484c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R1_P2 = 0x0484c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R2_P2 = 0x0484cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R3_P2 = 0x0484cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R4_P2 = 0x0484d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R5_P2 = 0x0484d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R6_P2 = 0x0484db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R7_P2 = 0x0484df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R8_P2 = 0x0484e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U0_P2 = 0x04850340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U0_P2 = 0x04850230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U0_P2 = 0x04850240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U0_P2 = 0x04850200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U1_P2 = 0x04850740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U1_P2 = 0x04850630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U1_P2 = 0x04850640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U1_P2 = 0x04850600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R0_P2 = 0x04850300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R1_P2 = 0x04850700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R2_P2 = 0x04850b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R3_P2 = 0x04850f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R4_P2 = 0x04851300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R5_P2 = 0x04851700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R6_P2 = 0x04851b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R7_P2 = 0x04851f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R8_P2 = 0x04852300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U0_P2 = 0x04854340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U0_P2 = 0x04854230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U0_P2 = 0x04854240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U0_P2 = 0x04854200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U1_P2 = 0x04854740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U1_P2 = 0x04854630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U1_P2 = 0x04854640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U1_P2 = 0x04854600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R0_P2 = 0x04854300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R1_P2 = 0x04854700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R2_P2 = 0x04854b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R3_P2 = 0x04854f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R4_P2 = 0x04855300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R5_P2 = 0x04855700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R6_P2 = 0x04855b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R7_P2 = 0x04855f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R8_P2 = 0x04856300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U0_P2 = 0x04858340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U0_P2 = 0x04858230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U0_P2 = 0x04858240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U0_P2 = 0x04858200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U1_P2 = 0x04858740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U1_P2 = 0x04858630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U1_P2 = 0x04858640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U1_P2 = 0x04858600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R0_P2 = 0x04858300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R1_P2 = 0x04858700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R2_P2 = 0x04858b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R3_P2 = 0x04858f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R4_P2 = 0x04859300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R5_P2 = 0x04859700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R6_P2 = 0x04859b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R7_P2 = 0x04859f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R8_P2 = 0x0485a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U0_P2 = 0x0485c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U0_P2 = 0x0485c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U0_P2 = 0x0485c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U0_P2 = 0x0485c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U1_P2 = 0x0485c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U1_P2 = 0x0485c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U1_P2 = 0x0485c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U1_P2 = 0x0485c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R0_P2 = 0x0485c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R1_P2 = 0x0485c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R2_P2 = 0x0485cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R3_P2 = 0x0485cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R4_P2 = 0x0485d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R5_P2 = 0x0485d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R6_P2 = 0x0485db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R7_P2 = 0x0485df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R8_P2 = 0x0485e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U0_P2 = 0x04860340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U0_P2 = 0x04860230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U0_P2 = 0x04860240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U0_P2 = 0x04860200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U1_P2 = 0x04860740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U1_P2 = 0x04860630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U1_P2 = 0x04860640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U1_P2 = 0x04860600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R0_P2 = 0x04860300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R1_P2 = 0x04860700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R2_P2 = 0x04860b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R3_P2 = 0x04860f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R4_P2 = 0x04861300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R5_P2 = 0x04861700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R6_P2 = 0x04861b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R7_P2 = 0x04861f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R8_P2 = 0x04862300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U0_P2 = 0x04864340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U0_P2 = 0x04864230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U0_P2 = 0x04864240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U0_P2 = 0x04864200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U1_P2 = 0x04864740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U1_P2 = 0x04864630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U1_P2 = 0x04864640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U1_P2 = 0x04864600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R0_P2 = 0x04864300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R1_P2 = 0x04864700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R2_P2 = 0x04864b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R3_P2 = 0x04864f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R4_P2 = 0x04865300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R5_P2 = 0x04865700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R6_P2 = 0x04865b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R7_P2 = 0x04865f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R8_P2 = 0x04866300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U0_P2 = 0x04840344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U0_P2 = 0x04840234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U0_P2 = 0x04840244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U0_P2 = 0x04840204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U1_P2 = 0x04840744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U1_P2 = 0x04840634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U1_P2 = 0x04840644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U1_P2 = 0x04840604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R0_P2 = 0x04840304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R1_P2 = 0x04840704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R2_P2 = 0x04840b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R3_P2 = 0x04840f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R4_P2 = 0x04841304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R5_P2 = 0x04841704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R6_P2 = 0x04841b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R7_P2 = 0x04841f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R8_P2 = 0x04842304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U0_P2 = 0x04844344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U0_P2 = 0x04844234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U0_P2 = 0x04844244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U0_P2 = 0x04844204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U1_P2 = 0x04844744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U1_P2 = 0x04844634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U1_P2 = 0x04844644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U1_P2 = 0x04844604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R0_P2 = 0x04844304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R1_P2 = 0x04844704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R2_P2 = 0x04844b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R3_P2 = 0x04844f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R4_P2 = 0x04845304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R5_P2 = 0x04845704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R6_P2 = 0x04845b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R7_P2 = 0x04845f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R8_P2 = 0x04846304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U0_P2 = 0x04848344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U0_P2 = 0x04848234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U0_P2 = 0x04848244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U0_P2 = 0x04848204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U1_P2 = 0x04848744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U1_P2 = 0x04848634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U1_P2 = 0x04848644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U1_P2 = 0x04848604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R0_P2 = 0x04848304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R1_P2 = 0x04848704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R2_P2 = 0x04848b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R3_P2 = 0x04848f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R4_P2 = 0x04849304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R5_P2 = 0x04849704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R6_P2 = 0x04849b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R7_P2 = 0x04849f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R8_P2 = 0x0484a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U0_P2 = 0x0484c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U0_P2 = 0x0484c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U0_P2 = 0x0484c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U0_P2 = 0x0484c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U1_P2 = 0x0484c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U1_P2 = 0x0484c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U1_P2 = 0x0484c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U1_P2 = 0x0484c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R0_P2 = 0x0484c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R1_P2 = 0x0484c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R2_P2 = 0x0484cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R3_P2 = 0x0484cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R4_P2 = 0x0484d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R5_P2 = 0x0484d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R6_P2 = 0x0484db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R7_P2 = 0x0484df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R8_P2 = 0x0484e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U0_P2 = 0x04850344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U0_P2 = 0x04850234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U0_P2 = 0x04850244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U0_P2 = 0x04850204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U1_P2 = 0x04850744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U1_P2 = 0x04850634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U1_P2 = 0x04850644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U1_P2 = 0x04850604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R0_P2 = 0x04850304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R1_P2 = 0x04850704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R2_P2 = 0x04850b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R3_P2 = 0x04850f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R4_P2 = 0x04851304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R5_P2 = 0x04851704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R6_P2 = 0x04851b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R7_P2 = 0x04851f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R8_P2 = 0x04852304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U0_P2 = 0x04854344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U0_P2 = 0x04854234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U0_P2 = 0x04854244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U0_P2 = 0x04854204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U1_P2 = 0x04854744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U1_P2 = 0x04854634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U1_P2 = 0x04854644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U1_P2 = 0x04854604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R0_P2 = 0x04854304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R1_P2 = 0x04854704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R2_P2 = 0x04854b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R3_P2 = 0x04854f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R4_P2 = 0x04855304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R5_P2 = 0x04855704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R6_P2 = 0x04855b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R7_P2 = 0x04855f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R8_P2 = 0x04856304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U0_P2 = 0x04858344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U0_P2 = 0x04858234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U0_P2 = 0x04858244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U0_P2 = 0x04858204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U1_P2 = 0x04858744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U1_P2 = 0x04858634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U1_P2 = 0x04858644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U1_P2 = 0x04858604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R0_P2 = 0x04858304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R1_P2 = 0x04858704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R2_P2 = 0x04858b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R3_P2 = 0x04858f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R4_P2 = 0x04859304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R5_P2 = 0x04859704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R6_P2 = 0x04859b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R7_P2 = 0x04859f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R8_P2 = 0x0485a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U0_P2 = 0x0485c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U0_P2 = 0x0485c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U0_P2 = 0x0485c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U0_P2 = 0x0485c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U1_P2 = 0x0485c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U1_P2 = 0x0485c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U1_P2 = 0x0485c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U1_P2 = 0x0485c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R0_P2 = 0x0485c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R1_P2 = 0x0485c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R2_P2 = 0x0485cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R3_P2 = 0x0485cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R4_P2 = 0x0485d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R5_P2 = 0x0485d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R6_P2 = 0x0485db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R7_P2 = 0x0485df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R8_P2 = 0x0485e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U0_P2 = 0x04860344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U0_P2 = 0x04860234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U0_P2 = 0x04860244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U0_P2 = 0x04860204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U1_P2 = 0x04860744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U1_P2 = 0x04860634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U1_P2 = 0x04860644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U1_P2 = 0x04860604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R0_P2 = 0x04860304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R1_P2 = 0x04860704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R2_P2 = 0x04860b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R3_P2 = 0x04860f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R4_P2 = 0x04861304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R5_P2 = 0x04861704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R6_P2 = 0x04861b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R7_P2 = 0x04861f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R8_P2 = 0x04862304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U0_P2 = 0x04864344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U0_P2 = 0x04864234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U0_P2 = 0x04864244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U0_P2 = 0x04864204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U1_P2 = 0x04864744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U1_P2 = 0x04864634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U1_P2 = 0x04864644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U1_P2 = 0x04864604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R0_P2 = 0x04864304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R1_P2 = 0x04864704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R2_P2 = 0x04864b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R3_P2 = 0x04864f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R4_P2 = 0x04865304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R5_P2 = 0x04865704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R6_P2 = 0x04865b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R7_P2 = 0x04865f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R8_P2 = 0x04866304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U0_P2 = 0x04840348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U0_P2 = 0x04840238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U0_P2 = 0x04840248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U0_P2 = 0x04840208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U1_P2 = 0x04840748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U1_P2 = 0x04840638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U1_P2 = 0x04840648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U1_P2 = 0x04840608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R0_P2 = 0x04840308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R1_P2 = 0x04840708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R2_P2 = 0x04840b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R3_P2 = 0x04840f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R4_P2 = 0x04841308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R5_P2 = 0x04841708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R6_P2 = 0x04841b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R7_P2 = 0x04841f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R8_P2 = 0x04842308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U0_P2 = 0x04844348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U0_P2 = 0x04844238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U0_P2 = 0x04844248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U0_P2 = 0x04844208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U1_P2 = 0x04844748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U1_P2 = 0x04844638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U1_P2 = 0x04844648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U1_P2 = 0x04844608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R0_P2 = 0x04844308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R1_P2 = 0x04844708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R2_P2 = 0x04844b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R3_P2 = 0x04844f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R4_P2 = 0x04845308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R5_P2 = 0x04845708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R6_P2 = 0x04845b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R7_P2 = 0x04845f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R8_P2 = 0x04846308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U0_P2 = 0x04848348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U0_P2 = 0x04848238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U0_P2 = 0x04848248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U0_P2 = 0x04848208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U1_P2 = 0x04848748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U1_P2 = 0x04848638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U1_P2 = 0x04848648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U1_P2 = 0x04848608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R0_P2 = 0x04848308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R1_P2 = 0x04848708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R2_P2 = 0x04848b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R3_P2 = 0x04848f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R4_P2 = 0x04849308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R5_P2 = 0x04849708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R6_P2 = 0x04849b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R7_P2 = 0x04849f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R8_P2 = 0x0484a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U0_P2 = 0x0484c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U0_P2 = 0x0484c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U0_P2 = 0x0484c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U0_P2 = 0x0484c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U1_P2 = 0x0484c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U1_P2 = 0x0484c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U1_P2 = 0x0484c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U1_P2 = 0x0484c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R0_P2 = 0x0484c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R1_P2 = 0x0484c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R2_P2 = 0x0484cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R3_P2 = 0x0484cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R4_P2 = 0x0484d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R5_P2 = 0x0484d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R6_P2 = 0x0484db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R7_P2 = 0x0484df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R8_P2 = 0x0484e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U0_P2 = 0x04850348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U0_P2 = 0x04850238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U0_P2 = 0x04850248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U0_P2 = 0x04850208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U1_P2 = 0x04850748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U1_P2 = 0x04850638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U1_P2 = 0x04850648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U1_P2 = 0x04850608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R0_P2 = 0x04850308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R1_P2 = 0x04850708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R2_P2 = 0x04850b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R3_P2 = 0x04850f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R4_P2 = 0x04851308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R5_P2 = 0x04851708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R6_P2 = 0x04851b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R7_P2 = 0x04851f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R8_P2 = 0x04852308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U0_P2 = 0x04854348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U0_P2 = 0x04854238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U0_P2 = 0x04854248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U0_P2 = 0x04854208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U1_P2 = 0x04854748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U1_P2 = 0x04854638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U1_P2 = 0x04854648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U1_P2 = 0x04854608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R0_P2 = 0x04854308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R1_P2 = 0x04854708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R2_P2 = 0x04854b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R3_P2 = 0x04854f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R4_P2 = 0x04855308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R5_P2 = 0x04855708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R6_P2 = 0x04855b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R7_P2 = 0x04855f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R8_P2 = 0x04856308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U0_P2 = 0x04858348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U0_P2 = 0x04858238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U0_P2 = 0x04858248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U0_P2 = 0x04858208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U1_P2 = 0x04858748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U1_P2 = 0x04858638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U1_P2 = 0x04858648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U1_P2 = 0x04858608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R0_P2 = 0x04858308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R1_P2 = 0x04858708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R2_P2 = 0x04858b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R3_P2 = 0x04858f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R4_P2 = 0x04859308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R5_P2 = 0x04859708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R6_P2 = 0x04859b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R7_P2 = 0x04859f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R8_P2 = 0x0485a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U0_P2 = 0x0485c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U0_P2 = 0x0485c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U0_P2 = 0x0485c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U0_P2 = 0x0485c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U1_P2 = 0x0485c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U1_P2 = 0x0485c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U1_P2 = 0x0485c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U1_P2 = 0x0485c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R0_P2 = 0x0485c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R1_P2 = 0x0485c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R2_P2 = 0x0485cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R3_P2 = 0x0485cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R4_P2 = 0x0485d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R5_P2 = 0x0485d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R6_P2 = 0x0485db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R7_P2 = 0x0485df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R8_P2 = 0x0485e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U0_P2 = 0x04860348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U0_P2 = 0x04860238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U0_P2 = 0x04860248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U0_P2 = 0x04860208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U1_P2 = 0x04860748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U1_P2 = 0x04860638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U1_P2 = 0x04860648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U1_P2 = 0x04860608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R0_P2 = 0x04860308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R1_P2 = 0x04860708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R2_P2 = 0x04860b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R3_P2 = 0x04860f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R4_P2 = 0x04861308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R5_P2 = 0x04861708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R6_P2 = 0x04861b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R7_P2 = 0x04861f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R8_P2 = 0x04862308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U0_P2 = 0x04864348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U0_P2 = 0x04864238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U0_P2 = 0x04864248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U0_P2 = 0x04864208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U1_P2 = 0x04864748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U1_P2 = 0x04864638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U1_P2 = 0x04864648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U1_P2 = 0x04864608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R0_P2 = 0x04864308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R1_P2 = 0x04864708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R2_P2 = 0x04864b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R3_P2 = 0x04864f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R4_P2 = 0x04865308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R5_P2 = 0x04865708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R6_P2 = 0x04865b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R7_P2 = 0x04865f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R8_P2 = 0x04866308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U0_P2 = 0x0484034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U0_P2 = 0x0484023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U0_P2 = 0x0484024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U0_P2 = 0x0484020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U1_P2 = 0x0484074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U1_P2 = 0x0484063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U1_P2 = 0x0484064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U1_P2 = 0x0484060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R0_P2 = 0x0484030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R1_P2 = 0x0484070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R2_P2 = 0x04840b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R3_P2 = 0x04840f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R4_P2 = 0x0484130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R5_P2 = 0x0484170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R6_P2 = 0x04841b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R7_P2 = 0x04841f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R8_P2 = 0x0484230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U0_P2 = 0x0484434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U0_P2 = 0x0484423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U0_P2 = 0x0484424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U0_P2 = 0x0484420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U1_P2 = 0x0484474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U1_P2 = 0x0484463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U1_P2 = 0x0484464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U1_P2 = 0x0484460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R0_P2 = 0x0484430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R1_P2 = 0x0484470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R2_P2 = 0x04844b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R3_P2 = 0x04844f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R4_P2 = 0x0484530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R5_P2 = 0x0484570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R6_P2 = 0x04845b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R7_P2 = 0x04845f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R8_P2 = 0x0484630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U0_P2 = 0x0484834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U0_P2 = 0x0484823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U0_P2 = 0x0484824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U0_P2 = 0x0484820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U1_P2 = 0x0484874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U1_P2 = 0x0484863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U1_P2 = 0x0484864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U1_P2 = 0x0484860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R0_P2 = 0x0484830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R1_P2 = 0x0484870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R2_P2 = 0x04848b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R3_P2 = 0x04848f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R4_P2 = 0x0484930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R5_P2 = 0x0484970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R6_P2 = 0x04849b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R7_P2 = 0x04849f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R8_P2 = 0x0484a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U0_P2 = 0x0484c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U0_P2 = 0x0484c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U0_P2 = 0x0484c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U0_P2 = 0x0484c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U1_P2 = 0x0484c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U1_P2 = 0x0484c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U1_P2 = 0x0484c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U1_P2 = 0x0484c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R0_P2 = 0x0484c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R1_P2 = 0x0484c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R2_P2 = 0x0484cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R3_P2 = 0x0484cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R4_P2 = 0x0484d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R5_P2 = 0x0484d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R6_P2 = 0x0484db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R7_P2 = 0x0484df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R8_P2 = 0x0484e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U0_P2 = 0x0485034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U0_P2 = 0x0485023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U0_P2 = 0x0485024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U0_P2 = 0x0485020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U1_P2 = 0x0485074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U1_P2 = 0x0485063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U1_P2 = 0x0485064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U1_P2 = 0x0485060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R0_P2 = 0x0485030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R1_P2 = 0x0485070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R2_P2 = 0x04850b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R3_P2 = 0x04850f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R4_P2 = 0x0485130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R5_P2 = 0x0485170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R6_P2 = 0x04851b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R7_P2 = 0x04851f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R8_P2 = 0x0485230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U0_P2 = 0x0485434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U0_P2 = 0x0485423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U0_P2 = 0x0485424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U0_P2 = 0x0485420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U1_P2 = 0x0485474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U1_P2 = 0x0485463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U1_P2 = 0x0485464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U1_P2 = 0x0485460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R0_P2 = 0x0485430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R1_P2 = 0x0485470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R2_P2 = 0x04854b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R3_P2 = 0x04854f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R4_P2 = 0x0485530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R5_P2 = 0x0485570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R6_P2 = 0x04855b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R7_P2 = 0x04855f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R8_P2 = 0x0485630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U0_P2 = 0x0485834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U0_P2 = 0x0485823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U0_P2 = 0x0485824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U0_P2 = 0x0485820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U1_P2 = 0x0485874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U1_P2 = 0x0485863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U1_P2 = 0x0485864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U1_P2 = 0x0485860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R0_P2 = 0x0485830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R1_P2 = 0x0485870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R2_P2 = 0x04858b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R3_P2 = 0x04858f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R4_P2 = 0x0485930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R5_P2 = 0x0485970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R6_P2 = 0x04859b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R7_P2 = 0x04859f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R8_P2 = 0x0485a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U0_P2 = 0x0485c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U0_P2 = 0x0485c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U0_P2 = 0x0485c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U0_P2 = 0x0485c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U1_P2 = 0x0485c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U1_P2 = 0x0485c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U1_P2 = 0x0485c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U1_P2 = 0x0485c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R0_P2 = 0x0485c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R1_P2 = 0x0485c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R2_P2 = 0x0485cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R3_P2 = 0x0485cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R4_P2 = 0x0485d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R5_P2 = 0x0485d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R6_P2 = 0x0485db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R7_P2 = 0x0485df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R8_P2 = 0x0485e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U0_P2 = 0x0486034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U0_P2 = 0x0486023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U0_P2 = 0x0486024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U0_P2 = 0x0486020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U1_P2 = 0x0486074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U1_P2 = 0x0486063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U1_P2 = 0x0486064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U1_P2 = 0x0486060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R0_P2 = 0x0486030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R1_P2 = 0x0486070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R2_P2 = 0x04860b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R3_P2 = 0x04860f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R4_P2 = 0x0486130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R5_P2 = 0x0486170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R6_P2 = 0x04861b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R7_P2 = 0x04861f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R8_P2 = 0x0486230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U0_P2 = 0x0486434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U0_P2 = 0x0486423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U0_P2 = 0x0486424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U0_P2 = 0x0486420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U1_P2 = 0x0486474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U1_P2 = 0x0486463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U1_P2 = 0x0486464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U1_P2 = 0x0486460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R0_P2 = 0x0486430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R1_P2 = 0x0486470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R2_P2 = 0x04864b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R3_P2 = 0x04864f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R4_P2 = 0x0486530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R5_P2 = 0x0486570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R6_P2 = 0x04865b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R7_P2 = 0x04865f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R8_P2 = 0x0486630cull; +static const uint64_t EXP_DDR4_PHY_ANIB0_ATXDLY_P2 = 0x04800200ull; +static const uint64_t EXP_DDR4_PHY_ANIB1_ATXDLY_P2 = 0x04804200ull; +static const uint64_t EXP_DDR4_PHY_ANIB2_ATXDLY_P2 = 0x04808200ull; +static const uint64_t EXP_DDR4_PHY_ANIB3_ATXDLY_P2 = 0x0480c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB4_ATXDLY_P2 = 0x04810200ull; +static const uint64_t EXP_DDR4_PHY_ANIB5_ATXDLY_P2 = 0x04814200ull; +static const uint64_t EXP_DDR4_PHY_ANIB6_ATXDLY_P2 = 0x04818200ull; +static const uint64_t EXP_DDR4_PHY_ANIB7_ATXDLY_P2 = 0x0481c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB8_ATXDLY_P2 = 0x04820200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U0_P3 = 0x04c40340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U0_P3 = 0x04c40230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U0_P3 = 0x04c40240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U0_P3 = 0x04c40200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG0_U1_P3 = 0x04c40740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG0_U1_P3 = 0x04c40630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG0_U1_P3 = 0x04c40640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG0_U1_P3 = 0x04c40600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R0_P3 = 0x04c40300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R1_P3 = 0x04c40700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R2_P3 = 0x04c40b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R3_P3 = 0x04c40f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R4_P3 = 0x04c41300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R5_P3 = 0x04c41700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R6_P3 = 0x04c41b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R7_P3 = 0x04c41f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG0_R8_P3 = 0x04c42300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U0_P3 = 0x04c44340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U0_P3 = 0x04c44230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U0_P3 = 0x04c44240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U0_P3 = 0x04c44200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG0_U1_P3 = 0x04c44740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG0_U1_P3 = 0x04c44630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG0_U1_P3 = 0x04c44640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG0_U1_P3 = 0x04c44600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R0_P3 = 0x04c44300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R1_P3 = 0x04c44700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R2_P3 = 0x04c44b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R3_P3 = 0x04c44f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R4_P3 = 0x04c45300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R5_P3 = 0x04c45700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R6_P3 = 0x04c45b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R7_P3 = 0x04c45f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG0_R8_P3 = 0x04c46300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U0_P3 = 0x04c48340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U0_P3 = 0x04c48230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U0_P3 = 0x04c48240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U0_P3 = 0x04c48200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG0_U1_P3 = 0x04c48740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG0_U1_P3 = 0x04c48630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG0_U1_P3 = 0x04c48640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG0_U1_P3 = 0x04c48600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R0_P3 = 0x04c48300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R1_P3 = 0x04c48700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R2_P3 = 0x04c48b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R3_P3 = 0x04c48f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R4_P3 = 0x04c49300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R5_P3 = 0x04c49700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R6_P3 = 0x04c49b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R7_P3 = 0x04c49f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG0_R8_P3 = 0x04c4a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U0_P3 = 0x04c4c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U0_P3 = 0x04c4c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U0_P3 = 0x04c4c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U0_P3 = 0x04c4c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG0_U1_P3 = 0x04c4c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG0_U1_P3 = 0x04c4c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG0_U1_P3 = 0x04c4c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG0_U1_P3 = 0x04c4c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R0_P3 = 0x04c4c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R1_P3 = 0x04c4c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R2_P3 = 0x04c4cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R3_P3 = 0x04c4cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R4_P3 = 0x04c4d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R5_P3 = 0x04c4d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R6_P3 = 0x04c4db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R7_P3 = 0x04c4df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG0_R8_P3 = 0x04c4e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U0_P3 = 0x04c50340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U0_P3 = 0x04c50230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U0_P3 = 0x04c50240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U0_P3 = 0x04c50200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG0_U1_P3 = 0x04c50740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG0_U1_P3 = 0x04c50630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG0_U1_P3 = 0x04c50640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG0_U1_P3 = 0x04c50600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R0_P3 = 0x04c50300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R1_P3 = 0x04c50700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R2_P3 = 0x04c50b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R3_P3 = 0x04c50f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R4_P3 = 0x04c51300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R5_P3 = 0x04c51700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R6_P3 = 0x04c51b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R7_P3 = 0x04c51f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG0_R8_P3 = 0x04c52300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U0_P3 = 0x04c54340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U0_P3 = 0x04c54230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U0_P3 = 0x04c54240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U0_P3 = 0x04c54200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG0_U1_P3 = 0x04c54740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG0_U1_P3 = 0x04c54630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG0_U1_P3 = 0x04c54640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG0_U1_P3 = 0x04c54600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R0_P3 = 0x04c54300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R1_P3 = 0x04c54700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R2_P3 = 0x04c54b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R3_P3 = 0x04c54f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R4_P3 = 0x04c55300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R5_P3 = 0x04c55700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R6_P3 = 0x04c55b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R7_P3 = 0x04c55f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG0_R8_P3 = 0x04c56300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U0_P3 = 0x04c58340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U0_P3 = 0x04c58230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U0_P3 = 0x04c58240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U0_P3 = 0x04c58200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG0_U1_P3 = 0x04c58740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG0_U1_P3 = 0x04c58630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG0_U1_P3 = 0x04c58640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG0_U1_P3 = 0x04c58600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R0_P3 = 0x04c58300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R1_P3 = 0x04c58700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R2_P3 = 0x04c58b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R3_P3 = 0x04c58f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R4_P3 = 0x04c59300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R5_P3 = 0x04c59700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R6_P3 = 0x04c59b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R7_P3 = 0x04c59f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG0_R8_P3 = 0x04c5a300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U0_P3 = 0x04c5c340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U0_P3 = 0x04c5c230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U0_P3 = 0x04c5c240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U0_P3 = 0x04c5c200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG0_U1_P3 = 0x04c5c740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG0_U1_P3 = 0x04c5c630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG0_U1_P3 = 0x04c5c640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG0_U1_P3 = 0x04c5c600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R0_P3 = 0x04c5c300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R1_P3 = 0x04c5c700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R2_P3 = 0x04c5cb00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R3_P3 = 0x04c5cf00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R4_P3 = 0x04c5d300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R5_P3 = 0x04c5d700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R6_P3 = 0x04c5db00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R7_P3 = 0x04c5df00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG0_R8_P3 = 0x04c5e300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U0_P3 = 0x04c60340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U0_P3 = 0x04c60230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U0_P3 = 0x04c60240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U0_P3 = 0x04c60200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG0_U1_P3 = 0x04c60740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG0_U1_P3 = 0x04c60630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG0_U1_P3 = 0x04c60640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG0_U1_P3 = 0x04c60600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R0_P3 = 0x04c60300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R1_P3 = 0x04c60700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R2_P3 = 0x04c60b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R3_P3 = 0x04c60f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R4_P3 = 0x04c61300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R5_P3 = 0x04c61700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R6_P3 = 0x04c61b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R7_P3 = 0x04c61f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG0_R8_P3 = 0x04c62300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U0_P3 = 0x04c64340ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U0_P3 = 0x04c64230ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U0_P3 = 0x04c64240ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U0_P3 = 0x04c64200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG0_U1_P3 = 0x04c64740ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG0_U1_P3 = 0x04c64630ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG0_U1_P3 = 0x04c64640ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG0_U1_P3 = 0x04c64600ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R0_P3 = 0x04c64300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R1_P3 = 0x04c64700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R2_P3 = 0x04c64b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R3_P3 = 0x04c64f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R4_P3 = 0x04c65300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R5_P3 = 0x04c65700ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R6_P3 = 0x04c65b00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R7_P3 = 0x04c65f00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG0_R8_P3 = 0x04c66300ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U0_P3 = 0x04c40344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U0_P3 = 0x04c40234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U0_P3 = 0x04c40244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U0_P3 = 0x04c40204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG1_U1_P3 = 0x04c40744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG1_U1_P3 = 0x04c40634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG1_U1_P3 = 0x04c40644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG1_U1_P3 = 0x04c40604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R0_P3 = 0x04c40304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R1_P3 = 0x04c40704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R2_P3 = 0x04c40b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R3_P3 = 0x04c40f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R4_P3 = 0x04c41304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R5_P3 = 0x04c41704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R6_P3 = 0x04c41b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R7_P3 = 0x04c41f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG1_R8_P3 = 0x04c42304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U0_P3 = 0x04c44344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U0_P3 = 0x04c44234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U0_P3 = 0x04c44244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U0_P3 = 0x04c44204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG1_U1_P3 = 0x04c44744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG1_U1_P3 = 0x04c44634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG1_U1_P3 = 0x04c44644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG1_U1_P3 = 0x04c44604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R0_P3 = 0x04c44304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R1_P3 = 0x04c44704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R2_P3 = 0x04c44b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R3_P3 = 0x04c44f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R4_P3 = 0x04c45304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R5_P3 = 0x04c45704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R6_P3 = 0x04c45b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R7_P3 = 0x04c45f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG1_R8_P3 = 0x04c46304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U0_P3 = 0x04c48344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U0_P3 = 0x04c48234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U0_P3 = 0x04c48244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U0_P3 = 0x04c48204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG1_U1_P3 = 0x04c48744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG1_U1_P3 = 0x04c48634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG1_U1_P3 = 0x04c48644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG1_U1_P3 = 0x04c48604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R0_P3 = 0x04c48304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R1_P3 = 0x04c48704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R2_P3 = 0x04c48b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R3_P3 = 0x04c48f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R4_P3 = 0x04c49304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R5_P3 = 0x04c49704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R6_P3 = 0x04c49b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R7_P3 = 0x04c49f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG1_R8_P3 = 0x04c4a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U0_P3 = 0x04c4c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U0_P3 = 0x04c4c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U0_P3 = 0x04c4c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U0_P3 = 0x04c4c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG1_U1_P3 = 0x04c4c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG1_U1_P3 = 0x04c4c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG1_U1_P3 = 0x04c4c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG1_U1_P3 = 0x04c4c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R0_P3 = 0x04c4c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R1_P3 = 0x04c4c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R2_P3 = 0x04c4cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R3_P3 = 0x04c4cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R4_P3 = 0x04c4d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R5_P3 = 0x04c4d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R6_P3 = 0x04c4db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R7_P3 = 0x04c4df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG1_R8_P3 = 0x04c4e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U0_P3 = 0x04c50344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U0_P3 = 0x04c50234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U0_P3 = 0x04c50244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U0_P3 = 0x04c50204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG1_U1_P3 = 0x04c50744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG1_U1_P3 = 0x04c50634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG1_U1_P3 = 0x04c50644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG1_U1_P3 = 0x04c50604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R0_P3 = 0x04c50304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R1_P3 = 0x04c50704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R2_P3 = 0x04c50b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R3_P3 = 0x04c50f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R4_P3 = 0x04c51304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R5_P3 = 0x04c51704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R6_P3 = 0x04c51b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R7_P3 = 0x04c51f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG1_R8_P3 = 0x04c52304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U0_P3 = 0x04c54344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U0_P3 = 0x04c54234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U0_P3 = 0x04c54244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U0_P3 = 0x04c54204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG1_U1_P3 = 0x04c54744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG1_U1_P3 = 0x04c54634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG1_U1_P3 = 0x04c54644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG1_U1_P3 = 0x04c54604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R0_P3 = 0x04c54304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R1_P3 = 0x04c54704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R2_P3 = 0x04c54b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R3_P3 = 0x04c54f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R4_P3 = 0x04c55304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R5_P3 = 0x04c55704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R6_P3 = 0x04c55b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R7_P3 = 0x04c55f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG1_R8_P3 = 0x04c56304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U0_P3 = 0x04c58344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U0_P3 = 0x04c58234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U0_P3 = 0x04c58244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U0_P3 = 0x04c58204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG1_U1_P3 = 0x04c58744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG1_U1_P3 = 0x04c58634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG1_U1_P3 = 0x04c58644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG1_U1_P3 = 0x04c58604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R0_P3 = 0x04c58304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R1_P3 = 0x04c58704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R2_P3 = 0x04c58b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R3_P3 = 0x04c58f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R4_P3 = 0x04c59304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R5_P3 = 0x04c59704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R6_P3 = 0x04c59b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R7_P3 = 0x04c59f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG1_R8_P3 = 0x04c5a304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U0_P3 = 0x04c5c344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U0_P3 = 0x04c5c234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U0_P3 = 0x04c5c244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U0_P3 = 0x04c5c204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG1_U1_P3 = 0x04c5c744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG1_U1_P3 = 0x04c5c634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG1_U1_P3 = 0x04c5c644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG1_U1_P3 = 0x04c5c604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R0_P3 = 0x04c5c304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R1_P3 = 0x04c5c704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R2_P3 = 0x04c5cb04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R3_P3 = 0x04c5cf04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R4_P3 = 0x04c5d304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R5_P3 = 0x04c5d704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R6_P3 = 0x04c5db04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R7_P3 = 0x04c5df04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG1_R8_P3 = 0x04c5e304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U0_P3 = 0x04c60344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U0_P3 = 0x04c60234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U0_P3 = 0x04c60244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U0_P3 = 0x04c60204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG1_U1_P3 = 0x04c60744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG1_U1_P3 = 0x04c60634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG1_U1_P3 = 0x04c60644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG1_U1_P3 = 0x04c60604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R0_P3 = 0x04c60304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R1_P3 = 0x04c60704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R2_P3 = 0x04c60b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R3_P3 = 0x04c60f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R4_P3 = 0x04c61304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R5_P3 = 0x04c61704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R6_P3 = 0x04c61b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R7_P3 = 0x04c61f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG1_R8_P3 = 0x04c62304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U0_P3 = 0x04c64344ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U0_P3 = 0x04c64234ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U0_P3 = 0x04c64244ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U0_P3 = 0x04c64204ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG1_U1_P3 = 0x04c64744ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG1_U1_P3 = 0x04c64634ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG1_U1_P3 = 0x04c64644ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG1_U1_P3 = 0x04c64604ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R0_P3 = 0x04c64304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R1_P3 = 0x04c64704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R2_P3 = 0x04c64b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R3_P3 = 0x04c64f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R4_P3 = 0x04c65304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R5_P3 = 0x04c65704ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R6_P3 = 0x04c65b04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R7_P3 = 0x04c65f04ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG1_R8_P3 = 0x04c66304ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U0_P3 = 0x04c40348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U0_P3 = 0x04c40238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U0_P3 = 0x04c40248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U0_P3 = 0x04c40208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG2_U1_P3 = 0x04c40748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG2_U1_P3 = 0x04c40638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG2_U1_P3 = 0x04c40648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG2_U1_P3 = 0x04c40608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R0_P3 = 0x04c40308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R1_P3 = 0x04c40708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R2_P3 = 0x04c40b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R3_P3 = 0x04c40f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R4_P3 = 0x04c41308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R5_P3 = 0x04c41708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R6_P3 = 0x04c41b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R7_P3 = 0x04c41f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG2_R8_P3 = 0x04c42308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U0_P3 = 0x04c44348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U0_P3 = 0x04c44238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U0_P3 = 0x04c44248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U0_P3 = 0x04c44208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG2_U1_P3 = 0x04c44748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG2_U1_P3 = 0x04c44638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG2_U1_P3 = 0x04c44648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG2_U1_P3 = 0x04c44608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R0_P3 = 0x04c44308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R1_P3 = 0x04c44708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R2_P3 = 0x04c44b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R3_P3 = 0x04c44f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R4_P3 = 0x04c45308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R5_P3 = 0x04c45708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R6_P3 = 0x04c45b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R7_P3 = 0x04c45f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG2_R8_P3 = 0x04c46308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U0_P3 = 0x04c48348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U0_P3 = 0x04c48238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U0_P3 = 0x04c48248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U0_P3 = 0x04c48208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG2_U1_P3 = 0x04c48748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG2_U1_P3 = 0x04c48638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG2_U1_P3 = 0x04c48648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG2_U1_P3 = 0x04c48608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R0_P3 = 0x04c48308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R1_P3 = 0x04c48708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R2_P3 = 0x04c48b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R3_P3 = 0x04c48f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R4_P3 = 0x04c49308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R5_P3 = 0x04c49708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R6_P3 = 0x04c49b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R7_P3 = 0x04c49f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG2_R8_P3 = 0x04c4a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U0_P3 = 0x04c4c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U0_P3 = 0x04c4c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U0_P3 = 0x04c4c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U0_P3 = 0x04c4c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG2_U1_P3 = 0x04c4c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG2_U1_P3 = 0x04c4c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG2_U1_P3 = 0x04c4c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG2_U1_P3 = 0x04c4c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R0_P3 = 0x04c4c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R1_P3 = 0x04c4c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R2_P3 = 0x04c4cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R3_P3 = 0x04c4cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R4_P3 = 0x04c4d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R5_P3 = 0x04c4d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R6_P3 = 0x04c4db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R7_P3 = 0x04c4df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG2_R8_P3 = 0x04c4e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U0_P3 = 0x04c50348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U0_P3 = 0x04c50238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U0_P3 = 0x04c50248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U0_P3 = 0x04c50208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG2_U1_P3 = 0x04c50748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG2_U1_P3 = 0x04c50638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG2_U1_P3 = 0x04c50648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG2_U1_P3 = 0x04c50608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R0_P3 = 0x04c50308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R1_P3 = 0x04c50708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R2_P3 = 0x04c50b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R3_P3 = 0x04c50f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R4_P3 = 0x04c51308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R5_P3 = 0x04c51708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R6_P3 = 0x04c51b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R7_P3 = 0x04c51f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG2_R8_P3 = 0x04c52308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U0_P3 = 0x04c54348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U0_P3 = 0x04c54238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U0_P3 = 0x04c54248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U0_P3 = 0x04c54208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG2_U1_P3 = 0x04c54748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG2_U1_P3 = 0x04c54638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG2_U1_P3 = 0x04c54648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG2_U1_P3 = 0x04c54608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R0_P3 = 0x04c54308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R1_P3 = 0x04c54708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R2_P3 = 0x04c54b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R3_P3 = 0x04c54f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R4_P3 = 0x04c55308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R5_P3 = 0x04c55708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R6_P3 = 0x04c55b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R7_P3 = 0x04c55f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG2_R8_P3 = 0x04c56308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U0_P3 = 0x04c58348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U0_P3 = 0x04c58238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U0_P3 = 0x04c58248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U0_P3 = 0x04c58208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG2_U1_P3 = 0x04c58748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG2_U1_P3 = 0x04c58638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG2_U1_P3 = 0x04c58648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG2_U1_P3 = 0x04c58608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R0_P3 = 0x04c58308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R1_P3 = 0x04c58708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R2_P3 = 0x04c58b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R3_P3 = 0x04c58f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R4_P3 = 0x04c59308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R5_P3 = 0x04c59708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R6_P3 = 0x04c59b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R7_P3 = 0x04c59f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG2_R8_P3 = 0x04c5a308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U0_P3 = 0x04c5c348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U0_P3 = 0x04c5c238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U0_P3 = 0x04c5c248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U0_P3 = 0x04c5c208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG2_U1_P3 = 0x04c5c748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG2_U1_P3 = 0x04c5c638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG2_U1_P3 = 0x04c5c648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG2_U1_P3 = 0x04c5c608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R0_P3 = 0x04c5c308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R1_P3 = 0x04c5c708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R2_P3 = 0x04c5cb08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R3_P3 = 0x04c5cf08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R4_P3 = 0x04c5d308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R5_P3 = 0x04c5d708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R6_P3 = 0x04c5db08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R7_P3 = 0x04c5df08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG2_R8_P3 = 0x04c5e308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U0_P3 = 0x04c60348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U0_P3 = 0x04c60238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U0_P3 = 0x04c60248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U0_P3 = 0x04c60208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG2_U1_P3 = 0x04c60748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG2_U1_P3 = 0x04c60638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG2_U1_P3 = 0x04c60648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG2_U1_P3 = 0x04c60608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R0_P3 = 0x04c60308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R1_P3 = 0x04c60708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R2_P3 = 0x04c60b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R3_P3 = 0x04c60f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R4_P3 = 0x04c61308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R5_P3 = 0x04c61708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R6_P3 = 0x04c61b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R7_P3 = 0x04c61f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG2_R8_P3 = 0x04c62308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U0_P3 = 0x04c64348ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U0_P3 = 0x04c64238ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U0_P3 = 0x04c64248ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U0_P3 = 0x04c64208ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG2_U1_P3 = 0x04c64748ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG2_U1_P3 = 0x04c64638ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG2_U1_P3 = 0x04c64648ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG2_U1_P3 = 0x04c64608ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R0_P3 = 0x04c64308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R1_P3 = 0x04c64708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R2_P3 = 0x04c64b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R3_P3 = 0x04c64f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R4_P3 = 0x04c65308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R5_P3 = 0x04c65708ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R6_P3 = 0x04c65b08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R7_P3 = 0x04c65f08ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG2_R8_P3 = 0x04c66308ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U0_P3 = 0x04c4034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U0_P3 = 0x04c4023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U0_P3 = 0x04c4024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U0_P3 = 0x04c4020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQSDLYTG3_U1_P3 = 0x04c4074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKDLYTG3_U1_P3 = 0x04c4063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXCLKCDLYTG3_U1_P3 = 0x04c4064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXENDLYTG3_U1_P3 = 0x04c4060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R0_P3 = 0x04c4030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R1_P3 = 0x04c4070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R2_P3 = 0x04c40b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R3_P3 = 0x04c40f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R4_P3 = 0x04c4130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R5_P3 = 0x04c4170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R6_P3 = 0x04c41b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R7_P3 = 0x04c41f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_TXDQDLYTG3_R8_P3 = 0x04c4230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U0_P3 = 0x04c4434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U0_P3 = 0x04c4423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U0_P3 = 0x04c4424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U0_P3 = 0x04c4420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQSDLYTG3_U1_P3 = 0x04c4474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKDLYTG3_U1_P3 = 0x04c4463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXCLKCDLYTG3_U1_P3 = 0x04c4464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXENDLYTG3_U1_P3 = 0x04c4460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R0_P3 = 0x04c4430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R1_P3 = 0x04c4470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R2_P3 = 0x04c44b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R3_P3 = 0x04c44f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R4_P3 = 0x04c4530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R5_P3 = 0x04c4570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R6_P3 = 0x04c45b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R7_P3 = 0x04c45f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_TXDQDLYTG3_R8_P3 = 0x04c4630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U0_P3 = 0x04c4834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U0_P3 = 0x04c4823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U0_P3 = 0x04c4824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U0_P3 = 0x04c4820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQSDLYTG3_U1_P3 = 0x04c4874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKDLYTG3_U1_P3 = 0x04c4863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXCLKCDLYTG3_U1_P3 = 0x04c4864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXENDLYTG3_U1_P3 = 0x04c4860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R0_P3 = 0x04c4830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R1_P3 = 0x04c4870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R2_P3 = 0x04c48b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R3_P3 = 0x04c48f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R4_P3 = 0x04c4930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R5_P3 = 0x04c4970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R6_P3 = 0x04c49b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R7_P3 = 0x04c49f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_TXDQDLYTG3_R8_P3 = 0x04c4a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U0_P3 = 0x04c4c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U0_P3 = 0x04c4c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U0_P3 = 0x04c4c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U0_P3 = 0x04c4c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQSDLYTG3_U1_P3 = 0x04c4c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKDLYTG3_U1_P3 = 0x04c4c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXCLKCDLYTG3_U1_P3 = 0x04c4c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXENDLYTG3_U1_P3 = 0x04c4c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R0_P3 = 0x04c4c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R1_P3 = 0x04c4c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R2_P3 = 0x04c4cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R3_P3 = 0x04c4cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R4_P3 = 0x04c4d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R5_P3 = 0x04c4d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R6_P3 = 0x04c4db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R7_P3 = 0x04c4df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_TXDQDLYTG3_R8_P3 = 0x04c4e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U0_P3 = 0x04c5034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U0_P3 = 0x04c5023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U0_P3 = 0x04c5024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U0_P3 = 0x04c5020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQSDLYTG3_U1_P3 = 0x04c5074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKDLYTG3_U1_P3 = 0x04c5063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXCLKCDLYTG3_U1_P3 = 0x04c5064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXENDLYTG3_U1_P3 = 0x04c5060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R0_P3 = 0x04c5030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R1_P3 = 0x04c5070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R2_P3 = 0x04c50b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R3_P3 = 0x04c50f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R4_P3 = 0x04c5130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R5_P3 = 0x04c5170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R6_P3 = 0x04c51b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R7_P3 = 0x04c51f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_TXDQDLYTG3_R8_P3 = 0x04c5230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U0_P3 = 0x04c5434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U0_P3 = 0x04c5423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U0_P3 = 0x04c5424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U0_P3 = 0x04c5420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQSDLYTG3_U1_P3 = 0x04c5474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKDLYTG3_U1_P3 = 0x04c5463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXCLKCDLYTG3_U1_P3 = 0x04c5464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXENDLYTG3_U1_P3 = 0x04c5460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R0_P3 = 0x04c5430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R1_P3 = 0x04c5470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R2_P3 = 0x04c54b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R3_P3 = 0x04c54f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R4_P3 = 0x04c5530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R5_P3 = 0x04c5570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R6_P3 = 0x04c55b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R7_P3 = 0x04c55f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_TXDQDLYTG3_R8_P3 = 0x04c5630cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U0_P3 = 0x04c5834cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U0_P3 = 0x04c5823cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U0_P3 = 0x04c5824cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U0_P3 = 0x04c5820cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQSDLYTG3_U1_P3 = 0x04c5874cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKDLYTG3_U1_P3 = 0x04c5863cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXCLKCDLYTG3_U1_P3 = 0x04c5864cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXENDLYTG3_U1_P3 = 0x04c5860cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R0_P3 = 0x04c5830cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R1_P3 = 0x04c5870cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R2_P3 = 0x04c58b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R3_P3 = 0x04c58f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R4_P3 = 0x04c5930cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R5_P3 = 0x04c5970cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R6_P3 = 0x04c59b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R7_P3 = 0x04c59f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_TXDQDLYTG3_R8_P3 = 0x04c5a30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U0_P3 = 0x04c5c34cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U0_P3 = 0x04c5c23cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U0_P3 = 0x04c5c24cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U0_P3 = 0x04c5c20cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQSDLYTG3_U1_P3 = 0x04c5c74cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKDLYTG3_U1_P3 = 0x04c5c63cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXCLKCDLYTG3_U1_P3 = 0x04c5c64cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXENDLYTG3_U1_P3 = 0x04c5c60cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R0_P3 = 0x04c5c30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R1_P3 = 0x04c5c70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R2_P3 = 0x04c5cb0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R3_P3 = 0x04c5cf0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R4_P3 = 0x04c5d30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R5_P3 = 0x04c5d70cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R6_P3 = 0x04c5db0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R7_P3 = 0x04c5df0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_TXDQDLYTG3_R8_P3 = 0x04c5e30cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U0_P3 = 0x04c6034cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U0_P3 = 0x04c6023cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U0_P3 = 0x04c6024cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U0_P3 = 0x04c6020cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQSDLYTG3_U1_P3 = 0x04c6074cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKDLYTG3_U1_P3 = 0x04c6063cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXCLKCDLYTG3_U1_P3 = 0x04c6064cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXENDLYTG3_U1_P3 = 0x04c6060cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R0_P3 = 0x04c6030cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R1_P3 = 0x04c6070cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R2_P3 = 0x04c60b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R3_P3 = 0x04c60f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R4_P3 = 0x04c6130cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R5_P3 = 0x04c6170cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R6_P3 = 0x04c61b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R7_P3 = 0x04c61f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_TXDQDLYTG3_R8_P3 = 0x04c6230cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U0_P3 = 0x04c6434cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U0_P3 = 0x04c6423cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U0_P3 = 0x04c6424cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U0_P3 = 0x04c6420cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQSDLYTG3_U1_P3 = 0x04c6474cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKDLYTG3_U1_P3 = 0x04c6463cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXCLKCDLYTG3_U1_P3 = 0x04c6464cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXENDLYTG3_U1_P3 = 0x04c6460cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R0_P3 = 0x04c6430cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R1_P3 = 0x04c6470cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R2_P3 = 0x04c64b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R3_P3 = 0x04c64f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R4_P3 = 0x04c6530cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R5_P3 = 0x04c6570cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R6_P3 = 0x04c65b0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R7_P3 = 0x04c65f0cull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_TXDQDLYTG3_R8_P3 = 0x04c6630cull; +static const uint64_t EXP_DDR4_PHY_ANIB0_ATXDLY_P3 = 0x04c00200ull; +static const uint64_t EXP_DDR4_PHY_ANIB1_ATXDLY_P3 = 0x04c04200ull; +static const uint64_t EXP_DDR4_PHY_ANIB2_ATXDLY_P3 = 0x04c08200ull; +static const uint64_t EXP_DDR4_PHY_ANIB3_ATXDLY_P3 = 0x04c0c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB4_ATXDLY_P3 = 0x04c10200ull; +static const uint64_t EXP_DDR4_PHY_ANIB5_ATXDLY_P3 = 0x04c14200ull; +static const uint64_t EXP_DDR4_PHY_ANIB6_ATXDLY_P3 = 0x04c18200ull; +static const uint64_t EXP_DDR4_PHY_ANIB7_ATXDLY_P3 = 0x04c1c200ull; +static const uint64_t EXP_DDR4_PHY_ANIB8_ATXDLY_P3 = 0x04c20200ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R0 = 0x040401a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R1 = 0x040405a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R2 = 0x040409a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R3 = 0x04040da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R4 = 0x040411a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R5 = 0x040415a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R6 = 0x040419a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R7 = 0x04041da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG0_R8 = 0x040421a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R0 = 0x040441a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R1 = 0x040445a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R2 = 0x040449a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R3 = 0x04044da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R4 = 0x040451a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R5 = 0x040455a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R6 = 0x040459a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R7 = 0x04045da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG0_R8 = 0x040461a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R0 = 0x040481a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R1 = 0x040485a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R2 = 0x040489a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R3 = 0x04048da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R4 = 0x040491a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R5 = 0x040495a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R6 = 0x040499a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R7 = 0x04049da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG0_R8 = 0x0404a1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R0 = 0x0404c1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R1 = 0x0404c5a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R2 = 0x0404c9a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R3 = 0x0404cda0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R4 = 0x0404d1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R5 = 0x0404d5a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R6 = 0x0404d9a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R7 = 0x0404dda0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG0_R8 = 0x0404e1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R0 = 0x040501a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R1 = 0x040505a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R2 = 0x040509a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R3 = 0x04050da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R4 = 0x040511a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R5 = 0x040515a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R6 = 0x040519a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R7 = 0x04051da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG0_R8 = 0x040521a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R0 = 0x040541a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R1 = 0x040545a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R2 = 0x040549a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R3 = 0x04054da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R4 = 0x040551a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R5 = 0x040555a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R6 = 0x040559a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R7 = 0x04055da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG0_R8 = 0x040561a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R0 = 0x040581a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R1 = 0x040585a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R2 = 0x040589a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R3 = 0x04058da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R4 = 0x040591a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R5 = 0x040595a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R6 = 0x040599a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R7 = 0x04059da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG0_R8 = 0x0405a1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R0 = 0x0405c1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R1 = 0x0405c5a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R2 = 0x0405c9a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R3 = 0x0405cda0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R4 = 0x0405d1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R5 = 0x0405d5a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R6 = 0x0405d9a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R7 = 0x0405dda0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG0_R8 = 0x0405e1a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R0 = 0x040601a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R1 = 0x040605a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R2 = 0x040609a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R3 = 0x04060da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R4 = 0x040611a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R5 = 0x040615a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R6 = 0x040619a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R7 = 0x04061da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG0_R8 = 0x040621a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R0 = 0x040641a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R1 = 0x040645a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R2 = 0x040649a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R3 = 0x04064da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R4 = 0x040651a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R5 = 0x040655a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R6 = 0x040659a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R7 = 0x04065da0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG0_R8 = 0x040661a0ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R0 = 0x040401a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R1 = 0x040405a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R2 = 0x040409a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R3 = 0x04040da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R4 = 0x040411a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R5 = 0x040415a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R6 = 0x040419a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R7 = 0x04041da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG1_R8 = 0x040421a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R0 = 0x040441a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R1 = 0x040445a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R2 = 0x040449a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R3 = 0x04044da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R4 = 0x040451a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R5 = 0x040455a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R6 = 0x040459a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R7 = 0x04045da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG1_R8 = 0x040461a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R0 = 0x040481a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R1 = 0x040485a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R2 = 0x040489a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R3 = 0x04048da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R4 = 0x040491a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R5 = 0x040495a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R6 = 0x040499a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R7 = 0x04049da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG1_R8 = 0x0404a1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R0 = 0x0404c1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R1 = 0x0404c5a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R2 = 0x0404c9a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R3 = 0x0404cda4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R4 = 0x0404d1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R5 = 0x0404d5a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R6 = 0x0404d9a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R7 = 0x0404dda4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG1_R8 = 0x0404e1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R0 = 0x040501a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R1 = 0x040505a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R2 = 0x040509a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R3 = 0x04050da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R4 = 0x040511a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R5 = 0x040515a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R6 = 0x040519a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R7 = 0x04051da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG1_R8 = 0x040521a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R0 = 0x040541a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R1 = 0x040545a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R2 = 0x040549a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R3 = 0x04054da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R4 = 0x040551a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R5 = 0x040555a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R6 = 0x040559a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R7 = 0x04055da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG1_R8 = 0x040561a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R0 = 0x040581a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R1 = 0x040585a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R2 = 0x040589a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R3 = 0x04058da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R4 = 0x040591a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R5 = 0x040595a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R6 = 0x040599a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R7 = 0x04059da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG1_R8 = 0x0405a1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R0 = 0x0405c1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R1 = 0x0405c5a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R2 = 0x0405c9a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R3 = 0x0405cda4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R4 = 0x0405d1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R5 = 0x0405d5a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R6 = 0x0405d9a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R7 = 0x0405dda4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG1_R8 = 0x0405e1a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R0 = 0x040601a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R1 = 0x040605a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R2 = 0x040609a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R3 = 0x04060da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R4 = 0x040611a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R5 = 0x040615a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R6 = 0x040619a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R7 = 0x04061da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG1_R8 = 0x040621a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R0 = 0x040641a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R1 = 0x040645a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R2 = 0x040649a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R3 = 0x04064da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R4 = 0x040651a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R5 = 0x040655a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R6 = 0x040659a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R7 = 0x04065da4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG1_R8 = 0x040661a4ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R0 = 0x040401a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R1 = 0x040405a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R2 = 0x040409a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R3 = 0x04040da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R4 = 0x040411a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R5 = 0x040415a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R6 = 0x040419a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R7 = 0x04041da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG2_R8 = 0x040421a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R0 = 0x040441a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R1 = 0x040445a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R2 = 0x040449a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R3 = 0x04044da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R4 = 0x040451a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R5 = 0x040455a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R6 = 0x040459a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R7 = 0x04045da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG2_R8 = 0x040461a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R0 = 0x040481a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R1 = 0x040485a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R2 = 0x040489a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R3 = 0x04048da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R4 = 0x040491a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R5 = 0x040495a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R6 = 0x040499a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R7 = 0x04049da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG2_R8 = 0x0404a1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R0 = 0x0404c1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R1 = 0x0404c5a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R2 = 0x0404c9a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R3 = 0x0404cda8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R4 = 0x0404d1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R5 = 0x0404d5a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R6 = 0x0404d9a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R7 = 0x0404dda8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG2_R8 = 0x0404e1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R0 = 0x040501a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R1 = 0x040505a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R2 = 0x040509a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R3 = 0x04050da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R4 = 0x040511a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R5 = 0x040515a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R6 = 0x040519a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R7 = 0x04051da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG2_R8 = 0x040521a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R0 = 0x040541a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R1 = 0x040545a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R2 = 0x040549a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R3 = 0x04054da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R4 = 0x040551a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R5 = 0x040555a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R6 = 0x040559a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R7 = 0x04055da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG2_R8 = 0x040561a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R0 = 0x040581a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R1 = 0x040585a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R2 = 0x040589a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R3 = 0x04058da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R4 = 0x040591a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R5 = 0x040595a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R6 = 0x040599a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R7 = 0x04059da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG2_R8 = 0x0405a1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R0 = 0x0405c1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R1 = 0x0405c5a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R2 = 0x0405c9a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R3 = 0x0405cda8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R4 = 0x0405d1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R5 = 0x0405d5a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R6 = 0x0405d9a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R7 = 0x0405dda8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG2_R8 = 0x0405e1a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R0 = 0x040601a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R1 = 0x040605a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R2 = 0x040609a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R3 = 0x04060da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R4 = 0x040611a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R5 = 0x040615a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R6 = 0x040619a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R7 = 0x04061da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG2_R8 = 0x040621a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R0 = 0x040641a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R1 = 0x040645a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R2 = 0x040649a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R3 = 0x04064da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R4 = 0x040651a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R5 = 0x040655a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R6 = 0x040659a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R7 = 0x04065da8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG2_R8 = 0x040661a8ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R0 = 0x040401acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R1 = 0x040405acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R2 = 0x040409acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R3 = 0x04040dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R4 = 0x040411acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R5 = 0x040415acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R6 = 0x040419acull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R7 = 0x04041dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_RXPBDLYTG3_R8 = 0x040421acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R0 = 0x040441acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R1 = 0x040445acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R2 = 0x040449acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R3 = 0x04044dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R4 = 0x040451acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R5 = 0x040455acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R6 = 0x040459acull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R7 = 0x04045dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_RXPBDLYTG3_R8 = 0x040461acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R0 = 0x040481acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R1 = 0x040485acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R2 = 0x040489acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R3 = 0x04048dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R4 = 0x040491acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R5 = 0x040495acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R6 = 0x040499acull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R7 = 0x04049dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_RXPBDLYTG3_R8 = 0x0404a1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R0 = 0x0404c1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R1 = 0x0404c5acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R2 = 0x0404c9acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R3 = 0x0404cdacull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R4 = 0x0404d1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R5 = 0x0404d5acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R6 = 0x0404d9acull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R7 = 0x0404ddacull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_RXPBDLYTG3_R8 = 0x0404e1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R0 = 0x040501acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R1 = 0x040505acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R2 = 0x040509acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R3 = 0x04050dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R4 = 0x040511acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R5 = 0x040515acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R6 = 0x040519acull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R7 = 0x04051dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_RXPBDLYTG3_R8 = 0x040521acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R0 = 0x040541acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R1 = 0x040545acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R2 = 0x040549acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R3 = 0x04054dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R4 = 0x040551acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R5 = 0x040555acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R6 = 0x040559acull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R7 = 0x04055dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_RXPBDLYTG3_R8 = 0x040561acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R0 = 0x040581acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R1 = 0x040585acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R2 = 0x040589acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R3 = 0x04058dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R4 = 0x040591acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R5 = 0x040595acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R6 = 0x040599acull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R7 = 0x04059dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_RXPBDLYTG3_R8 = 0x0405a1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R0 = 0x0405c1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R1 = 0x0405c5acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R2 = 0x0405c9acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R3 = 0x0405cdacull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R4 = 0x0405d1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R5 = 0x0405d5acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R6 = 0x0405d9acull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R7 = 0x0405ddacull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_RXPBDLYTG3_R8 = 0x0405e1acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R0 = 0x040601acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R1 = 0x040605acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R2 = 0x040609acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R3 = 0x04060dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R4 = 0x040611acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R5 = 0x040615acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R6 = 0x040619acull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R7 = 0x04061dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_RXPBDLYTG3_R8 = 0x040621acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R0 = 0x040641acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R1 = 0x040645acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R2 = 0x040649acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R3 = 0x04064dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R4 = 0x040651acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R5 = 0x040655acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R6 = 0x040659acull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R7 = 0x04065dacull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_RXPBDLYTG3_R8 = 0x040661acull; +static const uint64_t EXPLR_TP_MB_UNIT_TOP_TR1_TRACE_TRCTRL_CONFIG = 0x08010442ull; +static const uint64_t EXP_APBONLY0_MICROCONTMUXSEL = 0x04340000ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R0 = 0x4040100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R1 = 0x4040500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R2 = 0x4040900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R3 = 0x4040D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R4 = 0x4041100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R5 = 0x4041500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R6 = 0x4041900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R7 = 0x4041D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE0_VREFDAC0_R8 = 0x4042100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R0 = 0x4044100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R1 = 0x4044500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R2 = 0x4044900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R3 = 0x4044D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R4 = 0x4045100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R5 = 0x4045500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R6 = 0x4045900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R7 = 0x4045D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE1_VREFDAC0_R8 = 0x4046100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R0 = 0x4048100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R1 = 0x4048500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R2 = 0x4048900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R3 = 0x4048D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R4 = 0x4049100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R5 = 0x4049500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R6 = 0x4049900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R7 = 0x4049D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE2_VREFDAC0_R8 = 0x404A100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R0 = 0x404C100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R1 = 0x404C500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R2 = 0x404C900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R3 = 0x404CD00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R4 = 0x404D100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R5 = 0x404D500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R6 = 0x404D900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R7 = 0x404DD00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE3_VREFDAC0_R8 = 0x404E100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R0 = 0x4050100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R1 = 0x4050500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R2 = 0x4050900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R3 = 0x4050D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R4 = 0x4051100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R5 = 0x4051500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R6 = 0x4051900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R7 = 0x4051D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE4_VREFDAC0_R8 = 0x4052100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R0 = 0x4054100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R1 = 0x4054500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R2 = 0x4054900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R3 = 0x4054D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R4 = 0x4055100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R5 = 0x4055500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R6 = 0x4055900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R7 = 0x4055D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE5_VREFDAC0_R8 = 0x4056100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R0 = 0x4058100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R1 = 0x4058500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R2 = 0x4058900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R3 = 0x4058D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R4 = 0x4059100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R5 = 0x4059500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R6 = 0x4059900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R7 = 0x4059D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE6_VREFDAC0_R8 = 0x405A100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R0 = 0x405C100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R1 = 0x405C500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R2 = 0x405C900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R3 = 0x405CD00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R4 = 0x405D100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R5 = 0x405D500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R6 = 0x405D900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R7 = 0x405DD00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE7_VREFDAC0_R8 = 0x405E100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R0 = 0x4060100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R1 = 0x4060500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R2 = 0x4060900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R3 = 0x4060D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R4 = 0x4061100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R5 = 0x4061500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R6 = 0x4061900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R7 = 0x4061D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE8_VREFDAC0_R8 = 0x4062100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R0 = 0x4064100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R1 = 0x4064500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R2 = 0x4064900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R3 = 0x4064D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R4 = 0x4065100ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R5 = 0x4065500ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R6 = 0x4065900ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R7 = 0x4065D00ull; +static const uint64_t EXP_DDR4_PHY_DBYTE9_VREFDAC0_R8 = 0x4066100ull; +static const uint64_t EXP_DDR4_PHY_DDR_PHY_CONTROL = 0x6000118ull; + + + +static const uint32_t EXPLR_EFUSE_IMAGE_OUT_0 = 0x20B080ull; + + +static const uint32_t EXPLR_EFUSE_IMAGE_OUT_1 = 0x20B084ull; + + +static const uint32_t EXPLR_EFUSE_IMAGE_OUT_2 = 0x20B088ull; + + +static const uint32_t EXPLR_EFUSE_IMAGE_OUT_3 = 0x20B08Cull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_0 = 0x20B090ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_1 = 0x20B094ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_2 = 0x20B098ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_3 = 0x20B09Cull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_4 = 0x20B0A0ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_5 = 0x20B0A4ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_6 = 0x20B0A8ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_8 = 0x20B0ACull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_9 = 0x20B0B0ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_10 = 0x20B0B4ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_11 = 0x20B0B8ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_12 = 0x20B0BCull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_13 = 0x20B0C0ull; + + +static const uint32_t EXPLR_EFUSE_PE_DATA_14 = 0x20B0C4ull; + +#endif diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H index 5b93db5fb..ab747c2bb 100644 --- a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H @@ -27,6096 +27,6258 @@ #define __EXPLR_SCOM_ADDRESSES_FLD_H -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE = 0 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE_LEN = 4 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER = 4 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER_LEN = 4 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER = 8 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER_LEN = 4 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PSAVE_STS_ENABLE = 12 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER = 13 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER_LEN = 3 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR = 16 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR_LEN = 12 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_EN = 28 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL = 29 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL_LEN = 3 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RD_RST = 32 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR = 33 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR_LEN = 3 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_FREEZE = 36 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL = 37 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL_LEN = 3 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS = 40 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES = 42 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS = 44 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES = 46 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS = 48 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES = 50 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS = 52 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES = 54 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES_LEN = 2 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PE = 56 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PE = 57 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PE = 58 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PE = 59 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_EN = 60 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_EN = 61 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_EN = 62 ; -static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_EN = 63 ; - -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ENABLE = 0 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE = 1 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE_LEN = 5 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS = 6 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS_LEN = 6 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS = 12 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS = 16 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER = 20 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES = 24 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT = 28 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_ENABLE = 31 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT = 32 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT = 33 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_UE_INJECTION = 34 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_CE_INJECTION = 35 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FP_DISABLE = 36 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_UNUSED2 = 37 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TX_LN_REV_ENA = 38 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED = 39 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT = 40 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RUNLANE_OVRD_ENABLE = 44 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PWRMGT_ENABLE = 45 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE = 46 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE = 47 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES = 48 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE = 52 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION = 56 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION_LEN = 6 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RETRAIN = 62 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RESET = 63 ; - -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE = 0 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME = 5 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS = 8 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS = 12 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH = 16 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH = 18 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED = 20 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED = 22 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE = 24 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE = 32 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE1 = 40 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE1_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_HLD = 44 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_CAP = 45 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_TSHD_REG = 46 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_RMT_MSG = 47 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION = 48 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE = 49 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE = 52 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_ERROR = 55 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME = 56 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD = 60 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_ENA = 63 ; - -static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0 = 32 ; -static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0_LEN = 32 ; - -static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED = 0 ; -static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED_LEN = 55 ; -static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_RESET = 55 ; -static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS = 56 ; -static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS_LEN = 8 ; - -static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0 = 32 ; -static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0_LEN = 32 ; - -static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS = 0 ; -static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS_LEN = 64 ; - -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7 = 0 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6 = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5 = 16 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4 = 24 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3 = 32 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2 = 40 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1 = 48 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0 = 56 ; -static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0_LEN = 8 ; - -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11 = 16 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10 = 20 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9 = 24 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8 = 28 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7 = 32 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6 = 36 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5 = 40 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4 = 44 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3 = 48 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2 = 52 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1 = 56 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0 = 60 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0_LEN = 4 ; - -static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO = 1 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO_LEN = 63 ; - -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_47 = 16 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_46 = 17 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_45 = 18 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_44 = 19 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_43 = 20 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_42 = 21 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_41 = 22 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_40 = 23 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_39 = 24 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_38 = 25 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_37 = 26 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_36 = 27 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_35 = 28 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_34 = 29 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_33 = 30 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_32 = 31 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_31 = 32 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_30 = 33 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_29 = 34 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_28 = 35 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_27 = 36 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_26 = 37 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_25 = 38 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_24 = 39 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_23 = 40 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_22 = 41 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_21 = 42 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_20 = 43 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_19 = 44 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_18 = 45 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_17 = 46 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_16 = 47 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_15 = 48 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_14 = 49 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_13 = 50 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_12 = 51 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_11 = 52 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_10 = 53 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_09 = 54 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_08 = 55 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_07 = 56 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_06 = 57 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_05 = 58 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_04 = 59 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_03 = 60 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_02 = 61 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_01 = 62 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_00 = 63 ; - -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_47 = 16 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_46 = 17 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_45 = 18 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_44 = 19 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_43 = 20 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_42 = 21 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_41 = 22 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_40 = 23 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_39 = 24 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_38 = 25 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_37 = 26 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_36 = 27 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_35 = 28 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_34 = 29 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_33 = 30 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_32 = 31 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_31 = 32 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_30 = 33 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_29 = 34 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_28 = 35 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_27 = 36 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_26 = 37 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_25 = 38 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_24 = 39 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_23 = 40 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_22 = 41 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_21 = 42 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_20 = 43 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_19 = 44 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_18 = 45 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_17 = 46 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_16 = 47 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_15 = 48 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_14 = 49 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_13 = 50 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_12 = 51 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_11 = 52 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_10 = 53 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_09 = 54 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_08 = 55 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_07 = 56 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_06 = 57 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_05 = 58 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_04 = 59 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_03 = 60 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_02 = 61 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_01 = 62 ; -static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_00 = 63 ; - -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE = 0 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_LANE_REVERSED = 4 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_LANE_REVERSED = 5 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD0 = 6 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACK_PTRS_EQUAL = 7 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1 = 8 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1_LEN = 4 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH = 12 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH = 14 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH_LEN = 2 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES = 16 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES = 24 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO = 32 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO_LEN = 16 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD2 = 48 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE = 49 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3 = 52 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3_LEN = 3 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_DESKEW_DONE = 55 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED = 56 ; -static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED_LEN = 8 ; - -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A = 0 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN = 16 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE = 24 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED = 32 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1 = 40 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2 = 48 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2_LEN = 8 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3 = 56 ; -static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3_LEN = 8 ; - -static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_PAR = 0 ; -static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0 = 0 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0_LEN = 64 ; - -static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1 = 0 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1_LEN = 64 ; - -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR = 0 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR_LEN = 20 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR = 20 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR_LEN = 20 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR = 40 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR_LEN = 20 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_PERF_MON_WRAPPED = 60 ; - -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FATAL_ERROR = 0 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_DATA_UE = 1 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FLIT_CE = 2 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_CRC_ERROR = 3 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_NACK = 4 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_X4_MODE = 5 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL = 6 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TIMEOUT = 7 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_REMOTE_RETRAIN = 8 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN = 9 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN = 10 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TRAINED = 11 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR0 = 12 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR1 = 13 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR2 = 14 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR3 = 15 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR4 = 16 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR5 = 17 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR6 = 18 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR7 = 19 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FATAL_ERROR = 20 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_DATA_UE = 21 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FLIT_CE = 22 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_CRC_ERROR = 23 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_NACK = 24 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_X4_MODE = 25 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL = 26 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TIMEOUT = 27 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_REMOTE_RETRAIN = 28 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN = 29 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN = 30 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TRAINED = 31 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR0 = 32 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR1 = 33 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR2 = 34 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR3 = 35 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR4 = 36 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR5 = 37 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR6 = 38 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR7 = 39 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FATAL_ERROR = 40 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_DATA_UE = 41 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FLIT_CE = 42 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_CRC_ERROR = 43 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_NACK = 44 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_X4_MODE = 45 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL = 46 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TIMEOUT = 47 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_REMOTE_RETRAIN = 48 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN = 49 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN = 50 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TRAINED = 51 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR0 = 52 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR1 = 53 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR2 = 54 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR3 = 55 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR4 = 56 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR5 = 57 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR6 = 58 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR7 = 59 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_PERF_MON_WRAPPED = 60 ; - -static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF = 0 ; -static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF_LEN = 64 ; - -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3 = 0 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3_LEN = 16 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2 = 16 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2_LEN = 16 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1 = 32 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1_LEN = 16 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0 = 48 ; -static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0_LEN = 16 ; - -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE = 0 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ = 1 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE = 2 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ = 3 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_4 = 4 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE = 5 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14 = 6 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN = 9 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE = 15 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 = 16 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 = 48 ; -static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN = 16 ; - -static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_START = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_STOP = 1 ; -static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_UNPAUSE = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY_LEN = 16 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_28_31_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13 = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17 = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1 = 15 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_RESETN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1 = 17 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0 = 19 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ACTN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16 = 21 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15 = 22 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14 = 23 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_28 = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_28_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1 = 34 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3 = 36 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_2 = 38 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_39 = 39 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT = 40 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_PAUSE_INSTR = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CAL_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_PARITY = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_2 = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CAL_RANK_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_DDR_CALIBRATION_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_END = 58 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD = 59 ; -static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE = 1 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6 = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_TRACE_SELECT_DQBYPASS = 7 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD = 24 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NESTED_LOOP_ENABLE = 25 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE = 26 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK = 27 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION = 28 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE = 29 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT = 30 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13 = 32 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17 = 46 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1 = 47 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1 = 48 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0 = 50 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN = 51 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16 = 52 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15 = 53 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14 = 54 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY = 56 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2 = 60 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE = 61 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY = 62 ; -static const uint8_t EXPLR_MCBIST_CCS_MODEQ_PAUSE_DISABLE = 63 ; - -static const uint8_t EXPLR_MCBIST_CCS_STATQ_IP = 0 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_DONE = 1 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL = 2 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP = 6 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_RCD = 7 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_PAUSED = 8 ; -static const uint8_t EXPLR_MCBIST_CCS_STATQ_CE = 9 ; - -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_ENABLE = 0 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 = 1 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN = 11 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23 = 12 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN = 11 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01 = 23 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN = 11 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23 = 34 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN = 11 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER = 45 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET = 46 ; -static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM = 47 ; - -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_ENABLE = 0 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT = 1 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL = 3 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL = 23 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL = 43 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG1Q_RESERVED_63 = 63 ; - -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL = 0 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL = 40 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL = 0 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL = 20 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL = 23 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL = 26 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL = 29 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE = 32 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 33 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE = 37 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 41 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE = 45 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE = 51 ; -static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A = 0 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C = 8 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D = 12 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A = 16 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B = 20 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C = 24 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D = 28 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXR_SHIFT_SEL = 32 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXT_SHIFT_SEL = 33 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_WDF_SHIFT_SEL = 34 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RDF_SHIFT_SEL = 35 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_SRQ_SHIFT_SEL = 36 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MCB_SHIFT_SEL = 37 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MMIO_SHIFT_SEL = 38 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DLX_SHIFT_SEL = 39 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL = 40 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL = 44 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A = 48 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B = 52 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_56 = 56 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0 = 57 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_60 = 60 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1 = 61 ; -static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1_LEN = 3 ; - -static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBECTLQ_PE = 0 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_STATQ_PE = 1 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_MODEQ_PE = 2 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE = 3 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCSARRERRINJQ_PE = 4 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA0Q_PE = 5 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA1Q_PE = 6 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR0A0Q_PE = 7 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR1A0Q_PE = 8 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR2A0Q_PE = 9 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR3A0Q_PE = 10 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA0Q_PE = 11 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA1Q_PE = 12 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA0Q_PE = 13 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA1Q_PE = 14 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA2Q_PE = 15 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA3Q_PE = 16 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA2Q_PE = 17 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA3Q_PE = 18 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBLFSRA0Q_PE = 19 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBACQ_PE = 20 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAGRAQ_PE = 21 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS0Q_PE = 22 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS1Q_PE = 23 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRSRQ_PE = 24 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRCRQ_PE = 25 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD0Q_PE = 26 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD1Q_PE = 27 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD2Q_PE = 28 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD3Q_PE = 29 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD4Q_PE = 30 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD5Q_PE = 31 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD6Q_PE = 32 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD7Q_PE = 33 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDSPQ_PE = 34 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDQ_PE = 35 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBPARMQ_PE = 36 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RUNTIMECTRQ_PE = 37 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRCRQ_PE = 38 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCB_CNTLSTATQ_PE = 39 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBCFGQ_PE = 40 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBMCATQ_PE = 41 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC0Q_PE = 42 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC1Q_PE = 43 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSTRQ_PE = 44 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC0Q_PE = 45 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC1Q_PE = 46 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC2Q_PE = 47 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC3Q_PE = 48 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC4Q_PE = 49 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC5Q_PE = 50 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC6Q_PE = 51 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC7Q_PE = 52 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC8Q_PE = 53 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMODESQ_PE = 54 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSTATQ_PE = 55 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMSECQ_PE = 56 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBNCER0Q_PE = 57 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBRCER0Q_PE = 58 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBMPER0Q_PE = 59 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBUER0Q_PE = 60 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBAUER0Q_PE = 61 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_DBG_BUS_CFGQ_PE = 62 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MASK1Q_PE = 63 ; - -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MASK0Q_PE = 0 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBSEVR0Q_PE = 1 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG0Q_PE = 2 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG1Q_PE = 3 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG2Q_PE = 4 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG3Q_PE = 5 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0AQ_PE = 6 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0BQ_PE = 7 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0CQ_PE = 8 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0DQ_PE = 9 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0EQ_PE = 10 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1AQ_PE = 11 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1BQ_PE = 12 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1CQ_PE = 13 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1DQ_PE = 14 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1EQ_PE = 15 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2AQ_PE = 16 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2BQ_PE = 17 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2CQ_PE = 18 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2DQ_PE = 19 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2EQ_PE = 20 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3AQ_PE = 21 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3BQ_PE = 22 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3CQ_PE = 23 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3DQ_PE = 24 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3EQ_PE = 25 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR0Q_PE = 26 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR1Q_PE = 27 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR2Q_PE = 28 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR3Q_PE = 29 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR4Q_PE = 30 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR5Q_PE = 31 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR6Q_PE = 32 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR7Q_PE = 33 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT0Q_PE = 34 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT1Q_PE = 35 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT2Q_PE = 36 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_CNTLQ_PE = 37 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_CNTLQ_PE = 38 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_CCS = 39 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_MCBFSM = 40 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UNCORRECTED_CE = 41 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UE = 42 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_SCOM_ECC = 43 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_44_63 = 44 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_44_63_LEN = 20 ; - -static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_PAR = 0 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39 = 38 ; -static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBECTLQ_PE = 0 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_STATQ_PE = 1 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_MODEQ_PE = 2 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE = 3 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCSARRERRINJQ_PE = 4 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA0Q_PE = 5 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA1Q_PE = 6 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR0A0Q_PE = 7 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR1A0Q_PE = 8 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR2A0Q_PE = 9 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR3A0Q_PE = 10 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA0Q_PE = 11 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA1Q_PE = 12 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA0Q_PE = 13 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA1Q_PE = 14 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA2Q_PE = 15 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA3Q_PE = 16 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA2Q_PE = 17 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA3Q_PE = 18 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBLFSRA0Q_PE = 19 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBACQ_PE = 20 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAGRAQ_PE = 21 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS0Q_PE = 22 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS1Q_PE = 23 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRSRQ_PE = 24 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRCRQ_PE = 25 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD0Q_PE = 26 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD1Q_PE = 27 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD2Q_PE = 28 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD3Q_PE = 29 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD4Q_PE = 30 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD5Q_PE = 31 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD6Q_PE = 32 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD7Q_PE = 33 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDSPQ_PE = 34 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDQ_PE = 35 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBPARMQ_PE = 36 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RUNTIMECTRQ_PE = 37 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRCRQ_PE = 38 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCB_CNTLSTATQ_PE = 39 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBCFGQ_PE = 40 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBMCATQ_PE = 41 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC0Q_PE = 42 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC1Q_PE = 43 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSTRQ_PE = 44 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC0Q_PE = 45 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC1Q_PE = 46 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC2Q_PE = 47 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC3Q_PE = 48 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC4Q_PE = 49 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC5Q_PE = 50 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC6Q_PE = 51 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC7Q_PE = 52 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC8Q_PE = 53 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMODESQ_PE = 54 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSTATQ_PE = 55 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMSECQ_PE = 56 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBNCER0Q_PE = 57 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBRCER0Q_PE = 58 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBMPER0Q_PE = 59 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBUER0Q_PE = 60 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBAUER0Q_PE = 61 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_DBG_BUS_CFGQ_PE = 62 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_ERR_MASK1Q_PE = 63 ; - -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_ERR_MASK0Q_PE = 0 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBSEVR0Q_PE = 1 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG0Q_PE = 2 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG1Q_PE = 3 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG2Q_PE = 4 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG3Q_PE = 5 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0AQ_PE = 6 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0BQ_PE = 7 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0CQ_PE = 8 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0DQ_PE = 9 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0EQ_PE = 10 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1AQ_PE = 11 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1BQ_PE = 12 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1CQ_PE = 13 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1DQ_PE = 14 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1EQ_PE = 15 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2AQ_PE = 16 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2BQ_PE = 17 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2CQ_PE = 18 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2DQ_PE = 19 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2EQ_PE = 20 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3AQ_PE = 21 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3BQ_PE = 22 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3CQ_PE = 23 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3DQ_PE = 24 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3EQ_PE = 25 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR0Q_PE = 26 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR1Q_PE = 27 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR2Q_PE = 28 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR3Q_PE = 29 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR4Q_PE = 30 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR5Q_PE = 31 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR6Q_PE = 32 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR7Q_PE = 33 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT0Q_PE = 34 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT1Q_PE = 35 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT2Q_PE = 36 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_CNTLQ_PE = 37 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_CNTLQ_PE = 38 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_CCS_ERR = 39 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_MCBFSM_ERR = 40 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UNCORRECTED_CE_ERR = 41 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UE_ERR = 42 ; -static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_SCOM_ECC_ERR = 43 ; - -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ = 0 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ = 1 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ = 2 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ = 3 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL = 4 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN = 7 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVE_11 = 11 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ = 13 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE = 14 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG = 15 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_MODE = 16 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_REG = 17 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31 = 18 ; -static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31_LEN = 14 ; - -static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE = 38 ; -static const uint8_t EXPLR_MCBIST_MBMPER0Q_RESERVED_39 = 39 ; - -static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE = 38 ; -static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE = 39 ; - -static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39 = 38 ; -static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT = 0 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT = 24 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT = 36 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT = 48 ; -static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN = 12 ; - -static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT = 0 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT = 24 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE = 36 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT = 48 ; -static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT_LEN = 12 ; - -static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 0 ; + +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE = 0 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_SPARE_LEN = 4 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER = 4 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_CDR_TIMER_LEN = 4 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER = 8 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PM_DIDT_TIMER_LEN = 4 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PSAVE_STS_ENABLE = 12 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER = 13 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RECAL_TIMER_LEN = 3 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR = 16 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_1US_TMR_LEN = 12 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_EN = 28 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL = 29 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_DBG_SEL_LEN = 3 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_RD_RST = 32 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR = 33 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PRE_SCALAR_LEN = 3 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_FREEZE = 36 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL = 37 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_PORT_SEL_LEN = 3 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS = 40 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PS_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES = 42 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_ES_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS = 44 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PS_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES = 46 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_ES_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS = 48 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PS_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES = 50 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_ES_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS = 52 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PS_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES = 54 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_ES_LEN = 2 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_PE = 56 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_PE = 57 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_PE = 58 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_PE = 59 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR3_EN = 60 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR2_EN = 61 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR1_EN = 62 ; +static const uint8_t EXPLR_DLX_CMN_CONFIG_CFG_CNTR0_EN = 63 ; + +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ENABLE = 0 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE = 1 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_SPARE_LEN = 5 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS = 6 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_CFG_TL_CREDITS_LEN = 6 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS = 12 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS = 16 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER = 20 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES = 24 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT = 28 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DEBUG_ENABLE = 31 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT = 32 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT = 33 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_UE_INJECTION = 34 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_ECC_CE_INJECTION = 35 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_FP_DISABLE = 36 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_UNUSED2 = 37 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TX_LN_REV_ENA = 38 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED = 39 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT = 40 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RUNLANE_OVRD_ENABLE = 44 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_PWRMGT_ENABLE = 45 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_QUARTER_WIDTH_BACKOFF_ENABLE = 46 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_HALF_WIDTH_BACKOFF_ENABLE = 47 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES = 48 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE = 52 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION = 56 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_VERSION_LEN = 6 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RETRAIN = 62 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG0_CFG_RESET = 63 ; + +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE = 0 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_CFG1_SPARE_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_LANE_WIDTH_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME = 5 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS = 8 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS = 12 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH = 16 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH = 18 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED = 20 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED = 22 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE = 24 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE = 32 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_MACRO_DBG_SEL = 40 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_MACRO_DBG_SEL_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_HLD = 44 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_ERR_CAP = 45 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_TSHD_REG = 46 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_RESET_RMT_MSG = 47 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION = 48 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE = 49 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE = 52 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_INJECT_CRC_ERROR = 55 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME = 56 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_TIME_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD = 60 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_ENA = 63 ; + +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0 = 32 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_BITS0_LEN = 17 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_KILL_CRC_REPLAY0 = 49 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_RETRAIN_CRC_REPLAY0 = 50 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_PM_DISABLE_EDPL0 = 51 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_RETRAIN_CRC_RETRAIN0 = 52 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_RETRAIN_CRC_RESET0 = 53 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_FRBUF_FULL0 = 54 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_FRBUF_FULL_REPLAY0 = 55 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_PM_RETRAIN0 = 56 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_PM_RESET0 = 57 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_CRC_RETRAIN0 = 58 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_CRC_RESET0 = 59 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_MESO_BUFFER_ENABLE = 60 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_MESO_BUFFER_START = 61 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_MESO_BUFFER_DEPTH = 62 ; +static const uint8_t EXPLR_DLX_DL0_CYA_BITS_CFG_MESO_BUFFER_DEPTH_LEN = 2 ; + +static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED = 0 ; +static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_RESERVED_LEN = 55 ; +static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_RESET = 55 ; +static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS = 56 ; +static const uint8_t EXPLR_DLX_DL0_DEBUG_AID_PRBS7_STATUS_LEN = 8 ; + +static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0 = 32 ; +static const uint8_t EXPLR_DLX_DL0_DLX_CONFIG_CFG_DLX0_LEN = 32 ; + +static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS = 0 ; +static const uint8_t EXPLR_DLX_DL0_DLX_INFO_STS_LEN = 64 ; + +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7 = 0 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L7_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6 = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L6_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5 = 16 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L5_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4 = 24 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L4_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3 = 32 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L3_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2 = 40 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L2_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1 = 48 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L1_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0 = 56 ; +static const uint8_t EXPLR_DLX_DL0_EDPL_MAX_COUNT_L0_LEN = 8 ; + +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11 = 16 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_11_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10 = 20 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_10_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9 = 24 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_9_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8 = 28 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_8_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7 = 32 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_7_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6 = 36 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_6_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5 = 40 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_5_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4 = 44 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_4_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3 = 48 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_3_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2 = 52 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_2_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1 = 56 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_1_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0 = 60 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_ACTION_FIR_0_LEN = 4 ; + +static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO = 1 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_CAPTURE_INFO_LEN = 63 ; + +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_47 = 16 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_46 = 17 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_45 = 18 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_44 = 19 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_43 = 20 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_42 = 21 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_41 = 22 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_40 = 23 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_39 = 24 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_38 = 25 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_37 = 26 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_36 = 27 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_35 = 28 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_34 = 29 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_33 = 30 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_32 = 31 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_31 = 32 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_30 = 33 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_29 = 34 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_28 = 35 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_27 = 36 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_26 = 37 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_25 = 38 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_24 = 39 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_23 = 40 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_22 = 41 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_21 = 42 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_20 = 43 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_19 = 44 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_18 = 45 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_17 = 46 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_16 = 47 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_15 = 48 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_14 = 49 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_13 = 50 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_12 = 51 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_11 = 52 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_10 = 53 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_09 = 54 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_08 = 55 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_07 = 56 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_06 = 57 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_05 = 58 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_04 = 59 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_03 = 60 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_02 = 61 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_01 = 62 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_HOLD_CERR_00 = 63 ; + +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_47 = 16 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_46 = 17 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_45 = 18 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_44 = 19 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_43 = 20 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_42 = 21 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_41 = 22 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_40 = 23 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_39 = 24 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_38 = 25 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_37 = 26 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_36 = 27 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_35 = 28 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_34 = 29 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_33 = 30 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_32 = 31 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_31 = 32 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_30 = 33 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_29 = 34 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_28 = 35 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_27 = 36 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_26 = 37 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_25 = 38 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_24 = 39 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_23 = 40 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_22 = 41 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_21 = 42 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_20 = 43 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_19 = 44 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_18 = 45 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_17 = 46 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_16 = 47 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_15 = 48 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_14 = 49 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_13 = 50 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_12 = 51 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_11 = 52 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_10 = 53 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_09 = 54 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_08 = 55 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_07 = 56 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_06 = 57 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_05 = 58 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_04 = 59 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_03 = 60 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_02 = 61 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_01 = 62 ; +static const uint8_t EXPLR_DLX_DL0_ERROR_MASK_00 = 63 ; + +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE = 0 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINED_MODE_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_LANE_REVERSED = 4 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_LANE_REVERSED = 5 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD0 = 6 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACK_PTRS_EQUAL = 7 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1 = 8 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD1_LEN = 4 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH = 12 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_REQUESTED_LN_WIDTH_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH = 14 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ACTUAL_LN_WIDTH_LEN = 2 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES = 16 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TX_TRAINED_LANES_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES = 24 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RX_TRAINED_LANES_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO = 32 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_ENDPOINT_INFO_LEN = 16 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD2 = 48 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE = 49 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3 = 52 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_RSVD3_LEN = 3 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_DESKEW_DONE = 55 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED = 56 ; +static const uint8_t EXPLR_DLX_DL0_STATUS_STS_LANES_DISABLED_LEN = 8 ; + +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A = 0 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_A_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_PATTERN_B_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN = 16 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_SYNC_PATTERN_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE = 24 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_PHY_INIT_DONE_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED = 32 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_BLOCK_LOCKED_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1 = 40 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS1_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2 = 48 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS2_LEN = 8 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3 = 56 ; +static const uint8_t EXPLR_DLX_DL0_TRAINING_STATUS_STS_RX_TS3_LEN = 8 ; + +static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_DLX_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_PAR = 0 ; +static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_DLX_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0 = 0 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION0_REG_ACTION0_LEN = 64 ; + +static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1 = 0 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_ACTION1_REG_ACTION1_LEN = 64 ; + +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR = 0 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL0_ERROR_LEN = 20 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR = 20 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL1_ERROR_LEN = 20 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR = 40 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_DL2_ERROR_LEN = 20 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_PERF_MON_WRAPPED = 60 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_LFIR_PAR_ERR = 62 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_MASK_REG_SCOM_SAT_ERR = 63 ; + +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FATAL_ERROR = 0 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_DATA_UE = 1 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_FLIT_CE = 2 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_CRC_ERROR = 3 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_NACK = 4 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_X4_MODE = 5 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL = 6 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TIMEOUT = 7 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_REMOTE_RETRAIN = 8 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ERROR_RETRAIN = 9 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_EDPL_RETRAIN = 10 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_TRAINED = 11 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR0 = 12 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR1 = 13 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR2 = 14 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR3 = 15 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR4 = 16 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR5 = 17 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR6 = 18 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL0_ENDPOINT_FIR7 = 19 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FATAL_ERROR = 20 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_DATA_UE = 21 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_FLIT_CE = 22 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_CRC_ERROR = 23 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_NACK = 24 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_X4_MODE = 25 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL = 26 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TIMEOUT = 27 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_REMOTE_RETRAIN = 28 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ERROR_RETRAIN = 29 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_EDPL_RETRAIN = 30 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_TRAINED = 31 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR0 = 32 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR1 = 33 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR2 = 34 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR3 = 35 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR4 = 36 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR5 = 37 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR6 = 38 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL1_ENDPOINT_FIR7 = 39 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FATAL_ERROR = 40 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_DATA_UE = 41 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_FLIT_CE = 42 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_CRC_ERROR = 43 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_NACK = 44 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_X4_MODE = 45 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL = 46 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TIMEOUT = 47 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_REMOTE_RETRAIN = 48 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ERROR_RETRAIN = 49 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_EDPL_RETRAIN = 50 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_TRAINED = 51 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR0 = 52 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR1 = 53 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR2 = 54 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR3 = 55 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR4 = 56 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR5 = 57 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR6 = 58 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_DL2_ENDPOINT_FIR7 = 59 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_PERF_MON_WRAPPED = 60 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_LFIR_PAR_ERR = 62 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_REG_SCOM_SAT_ERR = 63 ; + +static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF = 0 ; +static const uint8_t EXPLR_DLX_MC_OMI_FIR_WOF_REG_WOF_LEN = 64 ; + +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3 = 0 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU3_LEN = 16 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2 = 16 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU2_LEN = 16 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1 = 32 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU1_LEN = 16 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0 = 48 ; +static const uint8_t EXPLR_DLX_PMU_CNTR_CFG_PMU0_LEN = 16 ; + +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ_MODE = 0 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_CE_ERR_INJ = 1 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ_MODE = 2 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_ARRAY_UE_ERR_INJ = 3 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_4 = 4 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_DISABLE_2N_MODE = 5 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14 = 6 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_RESERVED_6_14_LEN = 9 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_READ_RESPONSE_DELAY_ENABLE = 15 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0 = 16 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE0_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE1_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2 = 48 ; +static const uint8_t EXPLR_MCBIST_CCSARRERRINJQ_CCS_LOOP_COUNTER_COMPARE2_LEN = 16 ; + +static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_START = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_STOP = 1 ; +static const uint8_t EXPLR_MCBIST_CCS_CNTLQ_UNPAUSE = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA0Q_DATA_0_63_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_DATA_64_79_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_NTTM_READ_DELAY_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_WRITE_DATA_DELAY = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_FIXED_DATA1Q_WRITE_DATA_DELAY_LEN = 16 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_01_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_02_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_03_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_04_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_05_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_06_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_07_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_08_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_09_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_10_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_11_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_12_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_0_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_13_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ADDRESS = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_14_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_15_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_16_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_17_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_18_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_19_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_20_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_21_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_22_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_23_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_24_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_25_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_26_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_27_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_28_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_29_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_30_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13 = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_17 = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_1 = 15 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_RESETN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1 = 17 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_GROUP_0 = 19 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ACTN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_16 = 21 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_15 = 22 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ADDRESS_14 = 23 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CKE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_ADDRESS_OP = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_ADDRESS_OP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_30 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_30_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1 = 34 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3 = 36 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CSN_2_3_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_CID_2 = 38 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_FORCE_DATA_IMMED = 39 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT = 40 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_NESTED_LOOP_CNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_ODT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_52_54_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_PAUSE_INSTR = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_VARIABLE_SEL = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_VARIABLE_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_58_59 = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_RESERVED_58_59_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_PARITY = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_DDR_BANK_2 = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR0_31_LOOP_BREAK_MODE_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_01_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_02_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_03_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_04_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_05_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_06_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_07_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_08_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_09_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_10_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_11_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_12_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_13_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_14_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_15_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_16_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_17_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_18_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_19_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_20_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_21_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_22_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_23_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_24_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_25_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_26_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_27_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_28_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_29_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_30_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_IDLES_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_REPEAT_CMD_CNT_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_OR_WRITE_DATA_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_READ_COMPARE_REQUIRED = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_VARIABLE_OP = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_VARIABLE_OP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_END = 58 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD = 59 ; +static const uint8_t EXPLR_MCBIST_CCS_INST_ARR1_31_GOTO_CMD_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE = 1 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6 = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_4_6_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_TRACE_SELECT_DQBYPASS = 7 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_8_23 = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_8_23_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD = 24 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NESTED_LOOP_ENABLE = 25 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE = 26 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK = 27 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION = 28 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE = 29 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_30_31 = 30 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_RESERVED_30_31_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13 = 32 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17 = 46 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1 = 47 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1 = 48 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0 = 50 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN = 51 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16 = 52 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15 = 53 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14 = 54 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY = 56 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2 = 60 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE = 61 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY = 62 ; +static const uint8_t EXPLR_MCBIST_CCS_MODEQ_PAUSE_DISABLE = 63 ; + +static const uint8_t EXPLR_MCBIST_CCS_STATQ_IP = 0 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_DONE = 1 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL = 2 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_TYPE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_MCBIST_SUBTEST_IP = 6 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_FAIL_RCD = 7 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_PAUSED = 8 ; +static const uint8_t EXPLR_MCBIST_CCS_STATQ_CE = 9 ; + +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_ENABLE = 0 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01 = 1 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT01_LEN = 11 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23 = 12 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_ASYNC_PORT23_LEN = 11 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01 = 23 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST01_LEN = 11 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23 = 34 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_CFG_DBG_PICK_MCBIST23_LEN = 11 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_TRIGGER = 45 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_RESET = 46 ; +static const uint8_t EXPLR_MCBIST_DBGCFG0Q_SCOM_SET_WAT_EXT_ARM = 47 ; + +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_ENABLE = 0 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT = 1 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_EVENT_TO_INT_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL = 3 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_TRIGGER_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL = 23 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_RESET_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL = 43 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_CFG_WAT_EXT_ARM_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG1Q_RESERVED_63 = 63 ; + +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL = 0 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT0_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT1_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL = 40 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_CFG_WAT_LOC_EVENT2_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_MCBIST_DBGCFG2Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL = 0 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_LOC_EVENT3_SEL_LEN = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL = 20 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT0_SEL_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL = 23 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT1_SEL_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL = 26 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT2_SEL_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL = 29 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_GLOB_EVENT3_SEL_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_OUTPUT_PULSE = 32 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE = 33 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_MNT_GO_IDLE_PULSE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE = 37 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_SET_SPATTN_PULSE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE = 41 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_ACT_FRC_TB_PULSE_PULSE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE = 45 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_CNT_VALUE_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE = 51 ; +static const uint8_t EXPLR_MCBIST_DBGCFG3Q_CFG_WAT_TMR_VALUE_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A = 0 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_A_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_B_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C = 8 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_C_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D = 12 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL0_D_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A = 16 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_A_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B = 20 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_B_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C = 24 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_C_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D = 28 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE_SEL1_D_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXR_SHIFT_SEL = 32 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TLXT_SHIFT_SEL = 33 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_WDF_SHIFT_SEL = 34 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RDF_SHIFT_SEL = 35 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_SRQ_SHIFT_SEL = 36 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MCB_SHIFT_SEL = 37 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_MMIO_SHIFT_SEL = 38 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DLX_SHIFT_SEL = 39 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL = 40 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE0_TRACE_ERR_SEL_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL = 44 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_TRACE1_TRACE_ERR_SEL_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A = 48 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_A_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B = 52 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_SLICE_SEL_B_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_56 = 56 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0 = 57 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL0_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_RESERVED_60 = 60 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1 = 61 ; +static const uint8_t EXPLR_MCBIST_DBG_BUS_CFGQ_DFI_GROUP_SEL1_LEN = 3 ; + +static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_MCBIST_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBECTLQ_PE = 0 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_STATQ_PE = 1 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_MODEQ_PE = 2 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE = 3 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCSARRERRINJQ_PE = 4 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA0Q_PE = 5 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_CCS_FIXED_DATA1Q_PE = 6 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR0A0Q_PE = 7 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR1A0Q_PE = 8 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR2A0Q_PE = 9 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAMR3A0Q_PE = 10 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA0Q_PE = 11 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA1Q_PE = 12 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA0Q_PE = 13 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA1Q_PE = 14 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA2Q_PE = 15 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSA3Q_PE = 16 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA2Q_PE = 17 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBEA3Q_PE = 18 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBLFSRA0Q_PE = 19 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBACQ_PE = 20 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBAGRAQ_PE = 21 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS0Q_PE = 22 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRDS1Q_PE = 23 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRSRQ_PE = 24 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBDRCRQ_PE = 25 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD0Q_PE = 26 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD1Q_PE = 27 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD2Q_PE = 28 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD3Q_PE = 29 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD4Q_PE = 30 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD5Q_PE = 31 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD6Q_PE = 32 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFD7Q_PE = 33 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDSPQ_PE = 34 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBFDQ_PE = 35 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBPARMQ_PE = 36 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_RUNTIMECTRQ_PE = 37 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBRCRQ_PE = 38 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCB_CNTLSTATQ_PE = 39 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBCFGQ_PE = 40 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBMCATQ_PE = 41 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC0Q_PE = 42 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSEC1Q_PE = 43 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSTRQ_PE = 44 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC0Q_PE = 45 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC1Q_PE = 46 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC2Q_PE = 47 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC3Q_PE = 48 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC4Q_PE = 49 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC5Q_PE = 50 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC6Q_PE = 51 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC7Q_PE = 52 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSSYMEC8Q_PE = 53 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMODESQ_PE = 54 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MCBSTATQ_PE = 55 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBSMSECQ_PE = 56 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBNCER0Q_PE = 57 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBRCER0Q_PE = 58 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBMPER0Q_PE = 59 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBUER0Q_PE = 60 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MBAUER0Q_PE = 61 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_DBG_BUS_CFGQ_PE = 62 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK0Q_MASK1Q_PE = 63 ; + +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MASK0Q_PE = 0 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBSEVR0Q_PE = 1 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG0Q_PE = 2 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG1Q_PE = 3 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG2Q_PE = 4 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_DBGCFG3Q_PE = 5 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0AQ_PE = 6 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0BQ_PE = 7 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0CQ_PE = 8 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0DQ_PE = 9 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG0EQ_PE = 10 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1AQ_PE = 11 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1BQ_PE = 12 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1CQ_PE = 13 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1DQ_PE = 14 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG1EQ_PE = 15 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2AQ_PE = 16 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2BQ_PE = 17 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2CQ_PE = 18 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2DQ_PE = 19 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG2EQ_PE = 20 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3AQ_PE = 21 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3BQ_PE = 22 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3CQ_PE = 23 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3DQ_PE = 24 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_WATCFG3EQ_PE = 25 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR0Q_PE = 26 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR1Q_PE = 27 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR2Q_PE = 28 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR3Q_PE = 29 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR4Q_PE = 30 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR5Q_PE = 31 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR6Q_PE = 32 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCBMR7Q_PE = 33 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT0Q_PE = 34 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT1Q_PE = 35 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBXLT2Q_PE = 36 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_CNTLQ_PE = 37 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_CNTLQ_PE = 38 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_CCS = 39 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MCB_FIR_MCBFSM = 40 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UNCORRECTED_CE = 41 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_UE = 42 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_CCS_ARRAY_SCOM_ECC = 43 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_MBSSYMEC9Q_PE = 44 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_45_63 = 45 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK1Q_RESERVED_45_63_LEN = 19 ; + +static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_PAR = 0 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_MCBIST_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39 = 38 ; +static const uint8_t EXPLR_MCBIST_MBAUER0Q_RESERVED_38_39_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBECTLQ_PE = 0 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_STATQ_PE = 1 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_MODEQ_PE = 2 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RCD_LRDIM_CNTL_WORD0_15Q_PE = 3 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCSARRERRINJQ_PE = 4 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA0Q_PE = 5 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_CCS_FIXED_DATA1Q_PE = 6 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR0A0Q_PE = 7 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR1A0Q_PE = 8 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR2A0Q_PE = 9 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAMR3A0Q_PE = 10 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA0Q_PE = 11 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA1Q_PE = 12 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA0Q_PE = 13 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA1Q_PE = 14 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA2Q_PE = 15 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSA3Q_PE = 16 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA2Q_PE = 17 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBEA3Q_PE = 18 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBLFSRA0Q_PE = 19 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBACQ_PE = 20 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBAGRAQ_PE = 21 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS0Q_PE = 22 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRDS1Q_PE = 23 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRSRQ_PE = 24 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBDRCRQ_PE = 25 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD0Q_PE = 26 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD1Q_PE = 27 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD2Q_PE = 28 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD3Q_PE = 29 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD4Q_PE = 30 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD5Q_PE = 31 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD6Q_PE = 32 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFD7Q_PE = 33 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDSPQ_PE = 34 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBFDQ_PE = 35 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBPARMQ_PE = 36 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_RUNTIMECTRQ_PE = 37 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBRCRQ_PE = 38 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCB_CNTLSTATQ_PE = 39 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBCFGQ_PE = 40 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBMCATQ_PE = 41 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC0Q_PE = 42 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSEC1Q_PE = 43 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSTRQ_PE = 44 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC0Q_PE = 45 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC1Q_PE = 46 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC2Q_PE = 47 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC3Q_PE = 48 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC4Q_PE = 49 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC5Q_PE = 50 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC6Q_PE = 51 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC7Q_PE = 52 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSSYMEC8Q_PE = 53 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMODESQ_PE = 54 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MCBSTATQ_PE = 55 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBSMSECQ_PE = 56 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBNCER0Q_PE = 57 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBRCER0Q_PE = 58 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBMPER0Q_PE = 59 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBUER0Q_PE = 60 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_MBAUER0Q_PE = 61 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_DBG_BUS_CFGQ_PE = 62 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT0Q_ERR_MASK1Q_PE = 63 ; + +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_ERR_MASK0Q_PE = 0 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBSEVR0Q_PE = 1 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG0Q_PE = 2 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG1Q_PE = 3 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG2Q_PE = 4 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_DBGCFG3Q_PE = 5 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0AQ_PE = 6 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0BQ_PE = 7 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0CQ_PE = 8 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0DQ_PE = 9 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG0EQ_PE = 10 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1AQ_PE = 11 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1BQ_PE = 12 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1CQ_PE = 13 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1DQ_PE = 14 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG1EQ_PE = 15 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2AQ_PE = 16 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2BQ_PE = 17 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2CQ_PE = 18 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2DQ_PE = 19 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG2EQ_PE = 20 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3AQ_PE = 21 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3BQ_PE = 22 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3CQ_PE = 23 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3DQ_PE = 24 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_WATCFG3EQ_PE = 25 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR0Q_PE = 26 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR1Q_PE = 27 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR2Q_PE = 28 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR3Q_PE = 29 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR4Q_PE = 30 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR5Q_PE = 31 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR6Q_PE = 32 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCBMR7Q_PE = 33 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT0Q_PE = 34 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT1Q_PE = 35 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBXLT2Q_PE = 36 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_CNTLQ_PE = 37 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_CNTLQ_PE = 38 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_CCS_ERR = 39 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MCB_FIR_MCBFSM_ERR = 40 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UNCORRECTED_CE_ERR = 41 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_UE_ERR = 42 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_CCS_ARRAY_SCOM_ECC_ERR = 43 ; +static const uint8_t EXPLR_MCBIST_MBA_MCBERRPT1Q_MBSSYMEC9Q_PE = 44 ; + +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CE_INJ = 0 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_CHIP_KILL_INJ = 1 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_UE_INJ = 2 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_SUE_INJ = 3 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL = 4 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_ATOMIC_ALT_INJ_SYM_SEL_LEN = 7 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVE_11 = 11 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_SCOM_CMD_REG_INJ = 13 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_MODE = 14 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_MCBIST_FSM_INJ_REG = 15 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_MODE = 16 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_CCS_FSM_INJ_REG = 17 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31 = 18 ; +static const uint8_t EXPLR_MCBIST_MBECTLQ_RESERVED_18_31_LEN = 14 ; + +static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE = 38 ; +static const uint8_t EXPLR_MCBIST_MBMPER0Q_RESERVED_39 = 39 ; + +static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE = 38 ; +static const uint8_t EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE = 39 ; + +static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39 = 38 ; +static const uint8_t EXPLR_MCBIST_MBRCER0Q_RESERVED_38_39_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT = 0 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT = 24 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT = 36 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT = 48 ; +static const uint8_t EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN = 12 ; + +static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT = 0 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_ICE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT = 24 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_UE_COUNT_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE = 36 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_AUE_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT = 48 ; +static const uint8_t EXPLR_MCBIST_MBSEC1Q_RCE_COUNT_LEN = 12 ; + +static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD = 0 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD = 8 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 16 ; +static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD = 16 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN = 8 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD = 24 ; static const uint8_t EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63_LEN = 32 ; +static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSEVR0Q_RESERVED_32_63_LEN = 32 ; -static const uint8_t EXPLR_MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE = 0 ; +static const uint8_t EXPLR_MCBIST_MBSMODESQ_CFG_DDR4E_BLIND_STEER_MODE = 0 ; static const uint8_t EXPLR_MCBIST_MBSMODESQ_CFG_MCB_NIB_CNT_PORT_AGNOSTIC_MASK_DIS = 1 ; -static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15 = 2 ; -static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15_LEN = 14 ; - -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT = 0 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT = 8 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT = 16 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT = 24 ; -static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64 = 0 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65 = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66 = 16 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67 = 24 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68 = 32 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69 = 40 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70 = 48 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71 = 56 ; -static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT = 0 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD = 8 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE = 12 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE = 16 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT = 20 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = 24 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD = 28 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE = 32 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVED_33 = 33 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE = 34 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE = 35 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE = 36 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE = 37 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD = 38 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52 = 39 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE = 53 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 55 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 56 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 57 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR = 58 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = 59 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 60 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 61 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 62 ; -static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 63 ; - -static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39 = 38 ; -static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_VALID = 0 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_D_VALUE = 1 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_12GB_ENABLE = 2 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4 = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M0_VALID = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M1_VALID = 6 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8 = 7 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S0_VALID = 9 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S1_VALID = 10 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S2_VALID = 11 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_B2_VALID = 12 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW15_VALID = 13 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW16_VALID = 14 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW17_VALID = 15 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID = 16 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_D_VALUE = 17 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20 = 18 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M0_VALID = 21 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M1_VALID = 22 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24 = 23 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S0_VALID = 25 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S1_VALID = 26 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S2_VALID = 27 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_B2_VALID = 28 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW15_VALID = 29 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW16_VALID = 30 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW17_VALID = 31 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_ENAB_ROW_ADDR_HASH = 32 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP = 33 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP = 38 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP = 43 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_48 = 48 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP = 49 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP = 54 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP = 59 ; -static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2 = 0 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10 = 8 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP = 11 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18 = 16 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP = 19 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29 = 24 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP = 30 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP = 35 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42 = 40 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP = 43 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50 = 48 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP = 51 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58 = 56 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP = 59 ; -static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP_LEN = 5 ; - -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2 = 0 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10 = 8 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP = 11 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18 = 16 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP = 19 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26 = 24 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP = 27 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34 = 32 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP = 35 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42 = 40 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP = 43 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50 = 48 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP = 51 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63 = 56 ; -static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER = 0 ; -static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH = 0 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN = 10 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_11 = 11 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 12 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31 = 13 ; -static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31_LEN = 19 ; - -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT = 0 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0 = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1 = 12 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23 = 18 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1 = 30 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2 = 36 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2 = 42 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0 = 54 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0 = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17 = 12 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16 = 18 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14 = 30 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13 = 36 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 = 42 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10 = 54 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8 = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7 = 12 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6 = 18 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4 = 30 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3 = 36 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2 = 42 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0 = 54 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8 = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7 = 12 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6 = 18 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4 = 30 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3 = 36 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2 = 42 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN = 16 ; - -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESET_KEEPER = 10 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 11 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS = 12 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33 = 13 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33_LEN = 21 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK = 34 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK = 35 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE = 36 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS = 37 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN = 38 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 39 ; +static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15 = 2 ; +static const uint8_t EXPLR_MCBIST_MBSMODESQ_RESERVE_2_15_LEN = 14 ; + +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT = 0 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT = 8 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT = 16 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT = 24 ; +static const uint8_t EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_08_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_09_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_10_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_11_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_12_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_13_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_14_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC1Q_MODAL_SYMBOL_COUNTER_15_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_16_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_17_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_18_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_19_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_20_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_21_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_22_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC2Q_MODAL_SYMBOL_COUNTER_23_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_24_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_25_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_26_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_27_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_28_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_29_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_30_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC3Q_MODAL_SYMBOL_COUNTER_31_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_32_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_33_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_34_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_35_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_36_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_37_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_38_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC4Q_MODAL_SYMBOL_COUNTER_39_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_40_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_41_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_42_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_43_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_44_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_45_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_46_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC5Q_MODAL_SYMBOL_COUNTER_47_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_48_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_49_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_50_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_51_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_52_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_53_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_54_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC6Q_MODAL_SYMBOL_COUNTER_55_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_56_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_57_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_58_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_59_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_60_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_61_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_62_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC7Q_MODAL_SYMBOL_COUNTER_63_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_64_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_65_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_66_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_67_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_68_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_69_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_70_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC8Q_MODAL_SYMBOL_COUNTER_71_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT = 0 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD = 8 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE = 12 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE = 16 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT = 20 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = 24 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD = 28 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE = 32 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVED_33 = 33 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE = 34 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE = 35 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE = 36 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE = 37 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD = 38 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52 = 39 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_RESERVE_39_52_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE = 53 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = 55 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = 56 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = 57 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR = 58 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = 59 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE = 60 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = 61 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = 62 ; +static const uint8_t EXPLR_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = 63 ; + +static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39 = 38 ; +static const uint8_t EXPLR_MCBIST_MBUER0Q_RESERVED_38_39_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_VALID = 0 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_D_VALUE = 1 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_12GB_ENABLE = 2 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4 = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_3_4_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M0_VALID = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_M1_VALID = 6 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8 = 7 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_7_8_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S0_VALID = 9 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S1_VALID = 10 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_S2_VALID = 11 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_B2_VALID = 12 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW15_VALID = 13 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW16_VALID = 14 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW17_VALID = 15 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID = 16 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_D_VALUE = 17 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20 = 18 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_18_20_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M0_VALID = 21 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_M1_VALID = 22 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24 = 23 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_23_24_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S0_VALID = 25 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S1_VALID = 26 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_S2_VALID = 27 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_B2_VALID = 28 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW15_VALID = 29 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW16_VALID = 30 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_SLOT1_ROW17_VALID = 31 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_ENAB_ROW_ADDR_HASH = 32 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP = 33 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_D_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP = 38 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_M0_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP = 43 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_M1_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_RESERVED_48 = 48 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP = 49 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R17_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP = 54 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R16_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP = 59 ; +static const uint8_t EXPLR_MCBIST_MBXLT0Q_R15_BIT_MAP_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2 = 0 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_0_2_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S0_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10 = 8 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_8_10_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP = 11 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S1_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18 = 16 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_16_18_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP = 19 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_S2_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29 = 24 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_24_29_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP = 30 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL3_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP = 35 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL4_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42 = 40 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_40_42_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP = 43 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL5_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50 = 48 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_48_50_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP = 51 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL6_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58 = 56 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_RESERVED_56_58_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP = 59 ; +static const uint8_t EXPLR_MCBIST_MBXLT1_COL7_BIT_MAP_LEN = 5 ; + +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2 = 0 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_0_2_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_COL8_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10 = 8 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_8_10_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP = 11 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_COL9_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18 = 16 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_16_18_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP = 19 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK0_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26 = 24 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_24_26_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP = 27 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK1_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34 = 32 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_32_34_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP = 35 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK2_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42 = 40 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_40_42_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP = 43 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP0_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50 = 48 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_48_50_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP = 51 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_BANK_GROUP1_BIT_MAP_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63 = 56 ; +static const uint8_t EXPLR_MCBIST_MBXLT2_RESERVED_56_63_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER = 0 ; +static const uint8_t EXPLR_MCBIST_MCBACQ_CFG_ADDRESS_COUNTER_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH = 0 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN = 10 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_11 = 11 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES = 12 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31 = 13 ; +static const uint8_t EXPLR_MCBIST_MCBAGRAQ_RESERVED_13_31_LEN = 19 ; + +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT = 0 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0 = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1 = 12 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23 = 18 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_18_23_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1 = 30 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2 = 36 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2 = 42 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0 = 54 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_MCBIST_MCBAMR0A0Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0 = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17 = 12 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16 = 18 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14 = 30 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13 = 36 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 = 42 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10 = 54 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_MCBIST_MCBAMR1A0Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8 = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7 = 12 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6 = 18 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4 = 30 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3 = 36 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2 = 42 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0 = 54 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_MCBIST_MCBAMR2A0Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8 = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7 = 12 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6 = 18 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4 = 30 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3 = 36 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2 = 42 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBAMR3A0Q_RESERVED_48_63_LEN = 16 ; + +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_0_7_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESET_KEEPER = 10 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = 11 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS = 12 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33 = 13 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_13_33_LEN = 21 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK = 34 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK = 35 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE = 36 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS = 37 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN = 38 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = 39 ; static const uint8_t EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN = 41 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME = 42 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN = 14 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_MCB_LEN64 = 56 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 59 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 60 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN = 41 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME = 42 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN = 14 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_MCB_LEN64 = 56 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = 59 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = 60 ; static const uint8_t EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = 61 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63 = 62 ; -static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT = 0 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED = 4 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 16 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_20 = 20 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE = 21 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63 = 23 ; -static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63_LEN = 41 ; - -static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN = 64 ; - -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2 = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3 = 16 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5 = 32 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6 = 40 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8 = 56 ; -static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2 = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3 = 16 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5 = 32 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6 = 40 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7 = 48 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8 = 56 ; -static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN = 20 ; - -static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN = 20 ; - -static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK = 0 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK_LEN = 20 ; - -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS = 0 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT = 1 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR = 2 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_CCS_ARRAY_UNCORRECT_CE_OR_UE = 3 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR = 4 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN = 5 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN = 6 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN = 7 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RCE_ETE_ATTN = 8 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_ICE_ETE_ATTN = 9 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE = 10 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE = 11 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN = 12 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE = 14 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE = 15 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_16 = 16 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_17 = 17 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR = 18 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE = 19 ; - -static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF = 0 ; -static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF_LEN = 20 ; - -static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63 = 38 ; -static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN = 26 ; - -static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP = 40 ; - -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE = 0 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 5 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 6 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE = 7 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 8 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE = 9 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE = 13 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL = 14 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE = 16 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 20 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 21 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 22 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE = 23 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 24 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE = 25 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE = 28 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE = 29 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL = 30 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE = 32 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 36 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 37 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE = 39 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 40 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE = 41 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE = 44 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE = 45 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL = 46 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE = 48 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 52 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 53 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 54 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE = 55 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 56 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE = 57 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE = 60 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE = 61 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL = 62 ; -static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 2 ; - -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP = 0 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE = 12 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER = 13 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 12 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 25 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49 = 26 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49_LEN = 24 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT = 50 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59 = 53 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59_LEN = 7 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP = 60 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT = 61 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_BC4_EN = 63 ; - -static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31_LEN = 32 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL = 32 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST = 33 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD = 38 ; -static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_39 = 39 ; - -static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 24 ; -static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1 = 24 ; -static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 24 ; - -static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 24 ; -static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING = 24 ; -static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN = 40 ; - -static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN = 38 ; - -static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3 = 0 ; -static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63 = 62 ; +static const uint8_t EXPLR_MCBIST_MCBCFGQ_RESERVED_62_63_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT = 0 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED = 4 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN = 16 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_20 = 20 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE = 21 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63 = 23 ; +static const uint8_t EXPLR_MCBIST_MCBDRCRQ_RESERVED_23_63_LEN = 41 ; + +static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBEA1Q_CFG_END_ADDR_1_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBEA2Q_CFG_END_ADDR_2_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBEA3Q_CFG_END_ADDR_3_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD0Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD1Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD2Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD3Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD4Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD5Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD6Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFD7Q_CFG_FIXED_SEED_LEN = 64 ; + +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED1_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2 = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED2_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3 = 16 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED3_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED4_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5 = 32 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED5_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6 = 40 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED6_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED7_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8 = 56 ; +static const uint8_t EXPLR_MCBIST_MCBFDQ_CFG_FIXED_SEED8_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED1_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2 = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED2_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3 = 16 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED3_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED4_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5 = 32 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED5_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6 = 40 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED6_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7 = 48 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED7_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8 = 56 ; +static const uint8_t EXPLR_MCBIST_MCBFDSPQ_CFG_FIXED_SEED8_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRACT0_FIR_ACTION0_LEN = 20 ; + +static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRACT1_FIR_ACTION1_LEN = 20 ; + +static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK = 0 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRMASK_FIR_MASK_LEN = 20 ; + +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INVALID_MAINT_ADDRESS = 0 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT = 1 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR = 2 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_CCS_ARRAY_UNCORRECT_CE_OR_UE = 3 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR = 4 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_HARD_NCE_ETE_ATTN = 5 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SOFT_NCE_ETE_ATTN = 6 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INT_NCE_ETE_ATTN = 7 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RCE_ETE_ATTN = 8 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_ICE_ETE_ATTN = 9 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE = 10 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_MCBIST_CCS_SUBTEST_DONE = 11 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN = 12 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE = 14 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_REG_PE = 15 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_16 = 16 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_RESERVED_17 = 17 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR = 18 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_SCOM_ERROR_CLONE = 19 ; + +static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF = 0 ; +static const uint8_t EXPLR_MCBIST_MCBISTFIRWOF_FIR_WOF_LEN = 20 ; + +static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63 = 38 ; +static const uint8_t EXPLR_MCBIST_MCBLFSRA0Q_RESERVED_38_63_LEN = 26 ; + +static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP = 40 ; + +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST01_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST02_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST03_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST04_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST05_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST06_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR1Q_MCBIST_CFG_TEST07_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST08_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST09_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST10_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR2Q_MCBIST_CFG_TEST11_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST12_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST13_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST14_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR3Q_MCBIST_CFG_TEST15_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST16_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST17_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST18_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR4Q_MCBIST_CFG_TEST19_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST20_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST21_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST22_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR5Q_MCBIST_CFG_TEST23_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST24_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST25_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST26_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR6Q_MCBIST_CFG_TEST27_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE = 0 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_1ST_CMD = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_2ND_CMD = 5 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_COMPL_3RD_CMD = 6 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_REV_MODE = 7 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_RAND_MODE = 8 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE = 9 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ECC_MODE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_DONE = 13 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL = 14 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST28_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE = 16 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_1ST_CMD = 20 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_2ND_CMD = 21 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_COMPL_3RD_CMD = 22 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_REV_MODE = 23 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_RAND_MODE = 24 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE = 25 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ECC_MODE = 28 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_DONE = 29 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL = 30 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST29_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE = 32 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_1ST_CMD = 36 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_2ND_CMD = 37 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_COMPL_3RD_CMD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_REV_MODE = 39 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_RAND_MODE = 40 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE = 41 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ECC_MODE = 44 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_DONE = 45 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL = 46 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST30_ADDR_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE = 48 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_OP_TYPE_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_1ST_CMD = 52 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_2ND_CMD = 53 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_COMPL_3RD_CMD = 54 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_REV_MODE = 55 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_RAND_MODE = 56 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE = 57 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DATA_MODE_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ECC_MODE = 60 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_DONE = 61 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL = 62 ; +static const uint8_t EXPLR_MCBIST_MCBMR7Q_MCBIST_CFG_TEST31_ADDR_SEL_LEN = 2 ; + +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP = 0 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE = 12 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER = 13 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN = 12 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER = 25 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49 = 26 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_26_49_LEN = 24 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT = 50 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59 = 53 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_RESERVED_53_59_LEN = 7 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP = 60 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT = 61 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_MCBPARMQ_CFG_BC4_EN = 63 ; + +static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_0_31_LEN = 32 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_MCBALL = 32 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST = 33 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_SUBTEST_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_CFG_RUNTIME_OVERHEAD = 38 ; +static const uint8_t EXPLR_MCBIST_MCBRCRQ_RESERVED_39 = 39 ; + +static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN = 24 ; +static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1 = 24 ; +static const uint8_t EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN = 24 ; + +static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN = 24 ; +static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING = 24 ; +static const uint8_t EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN = 40 ; + +static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBSA0Q_CFG_START_ADDR_0_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBSA1Q_CFG_START_ADDR_1_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBSA2Q_CFG_START_ADDR_2_LEN = 38 ; + +static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3 = 0 ; +static const uint8_t EXPLR_MCBIST_MCBSA3Q_CFG_START_ADDR_3_LEN = 38 ; static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR = 0 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3 = 1 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3_LEN = 3 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR = 4 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 5 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15 = 9 ; -static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15_LEN = 7 ; - -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_START = 0 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_STOP = 1 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5 = 2 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG = 6 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS = 7 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE = 8 ; - -static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_IP = 0 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_DONE = 1 ; -static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_FAIL = 2 ; - -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM = 0 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 = 8 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 = 12 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 = 16 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 = 20 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 = 24 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 = 28 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 = 32 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 = 36 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 = 40 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 = 44 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 = 48 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 = 52 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 = 56 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN = 4 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 = 60 ; -static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN = 4 ; - -static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR = 0 ; -static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN = 37 ; - -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL = 16 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL = 24 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL = 32 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL = 40 ; -static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_ENABLE = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_INT_ARM_MODE = 45 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_EXT_ARM_MODE = 46 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TIMER_STATE_MODE = 47 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SET_LEVEL_ON_PULSE = 48 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_RESET_LEVEL_ON_PULSE = 49 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_ENABLE_EXT_RESET_LEVEL = 50 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_SET_DOM = 51 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_FOLLOW_LEVEL = 52 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE = 53 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE = 54 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE2 = 55 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE2 = 56 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SLIDE_TRIG = 57 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL = 58 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL_LEN = 2 ; -static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_FORCE_TEST_MODE = 60 ; - -static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL = 16 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL = 24 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL = 32 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL_LEN = 8 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL = 40 ; -static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL_LEN = 8 ; - -static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN = 17 ; - -static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; - -static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN = 17 ; - -static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; - -static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL = 44 ; -static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN = 17 ; - -static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN = 44 ; - -static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB = 0 ; -static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN = 44 ; - -static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE = 16 ; -static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MCFGERR_BDI = 20 ; -static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE = 21 ; -static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE_LEN = 3 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE = 24 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE_LEN = 5 ; -static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION = 29 ; -static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION_LEN = 3 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DEV_FUNC_MISMATCH = 32 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DETECT_BAD_OP = 33 ; -static const uint8_t EXPLR_MMIO_MCFGERR_TBIT_IS_1 = 34 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DATA_IS_BAD = 35 ; -static const uint8_t EXPLR_MMIO_MCFGERR_PL_IS_INVALID = 36 ; -static const uint8_t EXPLR_MMIO_MCFGERR_BAD_OP_OR_ALIGN = 37 ; -static const uint8_t EXPLR_MMIO_MCFGERR_ADDR_NO_IMPLEMENTED = 38 ; -static const uint8_t EXPLR_MMIO_MCFGERR_RDATA_VLD = 39 ; -static const uint8_t EXPLR_MMIO_MCFGERR_TBIT = 40 ; -static const uint8_t EXPLR_MMIO_MCFGERR_PLEN = 41 ; -static const uint8_t EXPLR_MMIO_MCFGERR_PLEN_LEN = 3 ; -static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM = 44 ; -static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM_LEN = 2 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DL = 46 ; -static const uint8_t EXPLR_MMIO_MCFGERR_DL_LEN = 2 ; -static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG = 48 ; -static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR = 0 ; -static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MCHOLD_FIR_MASK_PAR_ERR = 0 ; -static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION0_PAR_ERR = 1 ; -static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION1_PAR_ERR = 2 ; - -static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_MASK_PAR_ERR = 0 ; -static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION0_PAR_ERR = 1 ; -static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION1_PAR_ERR = 2 ; - -static const uint8_t EXPLR_MMIO_MDBELL_MDBELL = 0 ; - -static const uint8_t EXPLR_MMIO_MDBELLC_MDBELL_MDBELL = 0 ; - -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87 = 0 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87_LEN = 24 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE = 24 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE_LEN = 8 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7 = 32 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6 = 36 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5 = 40 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4 = 44 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3 = 48 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2 = 52 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1 = 56 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1_LEN = 4 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0 = 60 ; -static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63 = 0 ; -static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MENTERP_MMIO_ENTERPRISE_MODE = 0 ; -static const uint8_t EXPLR_MMIO_MENTERP_HALF_DIMM_MODE = 1 ; -static const uint8_t EXPLR_MMIO_MENTERP_CFG_ENTERPRISE_MODE = 2 ; - -static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS = 0 ; -static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_LEN = 44 ; -static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46 = 44 ; -static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46_LEN = 3 ; -static const uint8_t EXPLR_MMIO_MERRCTL_PASID_CHK_DIS = 47 ; -static const uint8_t EXPLR_MMIO_MERRCTL_ACTAG_CHK_DIS = 48 ; -static const uint8_t EXPLR_MMIO_MERRCTL_MSCC_RNGE_CHK_DIS = 49 ; -static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BIT_50 = 50 ; -static const uint8_t EXPLR_MMIO_MERRCTL_HOLD_ACUM = 51 ; -static const uint8_t EXPLR_MMIO_MERRCTL_SNSC_MASTER_ENABLE = 52 ; -static const uint8_t EXPLR_MMIO_MERRCTL_TRAP_CLEAR = 53 ; -static const uint8_t EXPLR_MMIO_MERRCTL_WDATA_P = 54 ; -static const uint8_t EXPLR_MMIO_MERRCTL_RNW = 55 ; -static const uint8_t EXPLR_MMIO_MERRCTL_ADDR = 56 ; -static const uint8_t EXPLR_MMIO_MERRCTL_ADDR_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_MFIR_AFU_DESC_UNIMP = 0 ; -static const uint8_t EXPLR_MMIO_MFIR_MMIO_ERR = 1 ; -static const uint8_t EXPLR_MMIO_MFIR_SCOM_ERR = 2 ; -static const uint8_t EXPLR_MMIO_MFIR_FSM_PERR = 3 ; -static const uint8_t EXPLR_MMIO_MFIR_FIFO_OVERFLOW = 4 ; -static const uint8_t EXPLR_MMIO_MFIR_CTL_REG_PERR = 5 ; -static const uint8_t EXPLR_MMIO_MFIR_INFO_REG_PERR = 6 ; -static const uint8_t EXPLR_MMIO_MFIR_SNSC_BOTH_STARTS_ERR = 7 ; -static const uint8_t EXPLR_MMIO_MFIR_SNSC_MULT_SEQ_PERR = 8 ; -static const uint8_t EXPLR_MMIO_MFIR_SNSC_FSM_PERR = 9 ; -static const uint8_t EXPLR_MMIO_MFIR_SNSC_REG_PERR = 10 ; -static const uint8_t EXPLR_MMIO_MFIR_ACTAG_PASID_CFG_ERR = 11 ; - -static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0 = 0 ; -static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0_LEN = 12 ; - -static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1 = 0 ; -static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1_LEN = 12 ; - -static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK = 0 ; -static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK_LEN = 12 ; - -static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF = 0 ; -static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF_LEN = 12 ; - -static const uint8_t EXPLR_MMIO_MHOLD0_O0MBIT_O0DID_PERR = 0 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0CCD_PERR = 1 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR0_PERR = 2 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR1_PERR = 3 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR2_PERR = 4 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0SSYSID_PERR = 5 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0CAPPTR_O0ROMBAR_PERR = 6 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OVPD_PERR = 7 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ODSNLO_ODSNCAP_PERR = 8 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ODSNHI_PERR = 9 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTLVID_OTLCAP_PERR = 10 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OVERCAP_OTLID_PERR = 11 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OVERCFG_PERR = 12 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ORTCAP_PERR = 13 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTTCFG_PERR = 14 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP10_PERR = 15 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP32_PERR = 16 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP54_PERR = 17 ; -static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP76_PERR = 18 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG10_PERR = 19 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG32_PERR = 20 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG54_PERR = 21 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG76_PERR = 22 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0FNVID_O0FNCAP_PERR = 23 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0ACTAG_O0FNID_PERR = 24 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0VSVID_O0VSCAP_PERR = 25 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O0VSID_PERR = 26 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1MBIT_O1DID_PERR = 27 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1CCD_PERR = 28 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR0_PERR = 29 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR1_PERR = 30 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR2_PERR = 31 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1SSYSID_PERR = 32 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1CAPPTR_O1ROMBAR_PERR = 33 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OPASID_PERR = 34 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1FNVID_O1FNCAP_PERR = 35 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1ACTAG_O1FNID_PERR = 36 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1INFVID_O1INFCAP_PERR = 37 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1INFOFF_O1INFID_PERR = 38 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1INFDAT_PERR = 39 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLVID_OCTRLCAP_PERR = 40 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLENB_OCTRLID_PERR = 41 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLPID_PERR = 42 ; -static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLTAG_PERR = 43 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1VSVID_O1VSCAP_PERR = 44 ; -static const uint8_t EXPLR_MMIO_MHOLD0_O1VSID_PERR = 45 ; -static const uint8_t EXPLR_MMIO_MHOLD0_AFU_DESC_UNIMP = 46 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MMIO_ERR = 47 ; -static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_ERR = 48 ; -static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CCMD_FSMPERR = 49 ; -static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CRESP_FSMPERR = 50 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CTL_MMIO_FSMPERR = 51 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CCMD_FSMPERR = 52 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CRESP_FSMPERR = 53 ; -static const uint8_t EXPLR_MMIO_MHOLD0_PIB_FSMPERR = 54 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CMUX_ARBPERR = 55 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CFG_CMDFIFO_OVRFLOW = 56 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CFG_RESPFIFO_OVRFLOW = 57 ; -static const uint8_t EXPLR_MMIO_MHOLD0_CFGP_FIFO_OVRFLOW = 58 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MERRCTL_PERR = 59 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MHOLD1_PERR = 60 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MMASK1_PERR = 61 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MDBELL_PERR = 62 ; -static const uint8_t EXPLR_MMIO_MHOLD0_MSCCRNGE_PERR = 63 ; - -static const uint8_t EXPLR_MMIO_MHOLD1_ONAME0_ODESCTML_PERR = 0 ; -static const uint8_t EXPLR_MMIO_MHOLD1_ONAME21_PERR = 1 ; -static const uint8_t EXPLR_MMIO_MHOLD1_ONAME43_PERR = 2 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OAFUVER_ONAME5_PERR = 3 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOOF_PERR = 4 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOSZ_PERR = 5 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOOOF_PERR = 6 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOST_PERR = 7 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OMEMADDR_PERR = 8 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OWWID10_PERR = 9 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OWWID32_PERR = 10 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MHOLD0_PERR = 11 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MMASK0_PERR = 12 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MMIOERR_PERR = 13 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MMIOEWD_PERR = 14 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SCOMEWD_PERR = 15 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRA_PERR = 16 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRB_PERR = 17 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_BOTH_STARTS_ERR = 18 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_MULT_SEQ_PERR = 19 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FSM_PERR = 20 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_OCTHERM_PERR = 21 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D0THERM_PERR = 22 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D1THERM_PERR = 23 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_RDWR_PERR = 24 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_ACTPWRUP_PERR = 25 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FRAMESR_PERR = 26 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASELOW_PERR = 27 ; -static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASEHIGH_PERR = 28 ; -static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXA_PERR = 29 ; -static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXB_PERR = 30 ; -static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXA_PERR = 31 ; -static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXB_PERR = 32 ; -static const uint8_t EXPLR_MMIO_MHOLD1_O0VSFLSH_PERR = 33 ; -static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_ACTAG_LENGTH = 34 ; -static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_ACTAG_LENGTH = 35 ; -static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_PASID_LENGTH = 36 ; -static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_PASID_LENGTH = 37 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MENTRP_PERR = 38 ; -static const uint8_t EXPLR_MMIO_MHOLD1_OSYSMEML_PERR = 39 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG0_PERR = 40 ; -static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG1_PERR = 41 ; - -static const uint8_t EXPLR_MMIO_MMASK0_MSK = 0 ; -static const uint8_t EXPLR_MMIO_MMASK0_MSK_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MMASK1_MSK = 0 ; -static const uint8_t EXPLR_MMIO_MMASK1_MSK_LEN = 42 ; - -static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P = 0 ; -static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P_LEN = 8 ; -static const uint8_t EXPLR_MMIO_MMIOERR_INFO = 8 ; -static const uint8_t EXPLR_MMIO_MMIOERR_INFO_LEN = 16 ; -static const uint8_t EXPLR_MMIO_MMIOERR_PLEN = 25 ; -static const uint8_t EXPLR_MMIO_MMIOERR_PLEN_LEN = 3 ; -static const uint8_t EXPLR_MMIO_MMIOERR_RNW = 28 ; -static const uint8_t EXPLR_MMIO_MMIOERR_ADDR = 29 ; -static const uint8_t EXPLR_MMIO_MMIOERR_ADDR_LEN = 35 ; - -static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA = 0 ; -static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO = 0 ; -static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO = 0 ; -static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO = 0 ; -static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO = 0 ; -static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER = 0 ; -static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER_LEN = 29 ; -static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER = 32 ; -static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE = 4 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE_LEN = 12 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH = 20 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH_LEN = 12 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_AFU_PRESENT = 32 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX = 34 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX_LEN = 6 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_FUNCTION_RESET = 40 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS_LEN = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR0_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR0_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O0BAR0_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O0BAR0_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS_LEN = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR1_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR1_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O0BAR1_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O0BAR1_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS_LEN = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR2_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O0BAR2_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O0BAR2_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O0BAR2_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE = 32 ; -static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE_LEN = 21 ; -static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_ENABLE = 63 ; - -static const uint8_t EXPLR_MMIO_O0CCD_MULTI_FUNCTION = 8 ; -static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE = 32 ; -static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE_LEN = 24 ; -static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID = 56 ; -static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_CAPABILITIES_LIST = 11 ; -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_MEMORY_SPACE = 30 ; -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID = 32 ; -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID = 48 ; -static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID = 0 ; -static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID = 16 ; -static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1 = 0 ; -static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1_LEN = 32 ; -static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0 = 32 ; -static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3 = 0 ; -static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3_LEN = 32 ; -static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2 = 32 ; -static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA = 0 ; -static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA_LEN = 32 ; -static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL = 44 ; -static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL_LEN = 20 ; - -static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE = 32 ; -static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1 = 0 ; -static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1_LEN = 32 ; -static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0 = 32 ; -static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3 = 0 ; -static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3_LEN = 32 ; -static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2 = 32 ; -static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE = 4 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE_LEN = 12 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH = 20 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH_LEN = 12 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_AFU_PRESENT = 32 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX = 34 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX_LEN = 6 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_FUNCTION_RESET = 40 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS_LEN = 29 ; -static const uint8_t EXPLR_MMIO_O1BAR0_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O1BAR0_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O1BAR0_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O1BAR0_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS_LEN = 60 ; -static const uint8_t EXPLR_MMIO_O1BAR1_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O1BAR1_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O1BAR1_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O1BAR1_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS = 0 ; -static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS_LEN = 60 ; -static const uint8_t EXPLR_MMIO_O1BAR2_PREFETCHABLE = 60 ; -static const uint8_t EXPLR_MMIO_O1BAR2_TYPE = 61 ; -static const uint8_t EXPLR_MMIO_O1BAR2_TYPE_LEN = 2 ; -static const uint8_t EXPLR_MMIO_O1BAR2_ADDRESS_SPACE = 63 ; - -static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE = 32 ; -static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE_LEN = 21 ; -static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_ENABLE = 63 ; - -static const uint8_t EXPLR_MMIO_O1CCD_MULTI_FUNCTION = 8 ; -static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE = 32 ; -static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE_LEN = 24 ; -static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID = 56 ; -static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA = 32 ; -static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DATA_VALID = 0 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET = 1 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET_LEN = 31 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX = 42 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX_LEN = 6 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_CAPABILITIES_LIST = 11 ; -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_MEMORY_SPACE = 30 ; -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID = 32 ; -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID = 48 ; -static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID = 0 ; -static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID = 16 ; -static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE = 32 ; -static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE_LEN = 16 ; -static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR = 0 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE = 16 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE_LEN = 3 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE = 19 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE_LEN = 3 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE = 24 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23 = 32 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22 = 40 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21 = 48 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20 = 56 ; -static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE = 0 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_FENCE_AFU = 6 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_ENABLE_AFU = 7 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_RESET_AFU = 8 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_TERMINATE_VALID = 11 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE = 12 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE_LEN = 20 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX = 42 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX_LEN = 6 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID = 48 ; -static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_SUPPORTED = 0 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_ENABLED = 1 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL = 2 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL_LEN = 3 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE = 12 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE_LEN = 20 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED = 51 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED_LEN = 5 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED = 59 ; -static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED_LEN = 5 ; - -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE = 20 ; -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE_LEN = 12 ; -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED = 36 ; -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED_LEN = 12 ; -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED = 52 ; -static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED_LEN = 12 ; - -static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH = 32 ; -static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW = 0 ; -static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET = 0 ; -static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET_LEN = 48 ; -static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR = 61 ; -static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR_LEN = 3 ; - -static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE = 32 ; -static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR = 0 ; -static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3 = 0 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2 = 8 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1 = 16 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0 = 24 ; -static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11 = 0 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10 = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9 = 16 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8 = 24 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7 = 32 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6 = 40 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5 = 48 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4 = 56 ; -static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19 = 0 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18 = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17 = 16 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16 = 24 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15 = 32 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14 = 40 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13 = 48 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13_LEN = 8 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12 = 56 ; -static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH = 19 ; -static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH_LEN = 5 ; - -static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET = 0 ; -static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET_LEN = 48 ; -static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR = 61 ; -static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR_LEN = 3 ; - -static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE = 24 ; -static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE = 32 ; -static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55 = 0 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54 = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53 = 8 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52 = 12 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51 = 16 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50 = 20 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49 = 24 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48 = 28 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63 = 32 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62 = 36 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61 = 40 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60 = 44 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59 = 48 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58 = 52 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57 = 56 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56 = 60 ; -static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39 = 0 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38 = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37 = 8 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36 = 12 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35 = 16 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34 = 20 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33 = 24 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32 = 28 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47 = 32 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46 = 36 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45 = 40 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44 = 44 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43 = 48 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42 = 52 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41 = 56 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40 = 60 ; -static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23 = 0 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22 = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21 = 8 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20 = 12 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19 = 16 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18 = 20 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17 = 24 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16 = 28 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31 = 32 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30 = 36 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29 = 40 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28 = 44 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27 = 48 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26 = 52 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25 = 56 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24 = 60 ; -static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7 = 0 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6 = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5 = 8 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4 = 12 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3 = 16 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2 = 20 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1 = 24 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0 = 28 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15 = 32 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14 = 36 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13 = 40 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12 = 44 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11 = 48 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10 = 52 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9 = 56 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9_LEN = 4 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8 = 60 ; -static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_31 = 0 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_30 = 1 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_29 = 2 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_28 = 3 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_27 = 4 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_26 = 5 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_25 = 6 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_24 = 7 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_23 = 8 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_22 = 9 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_21 = 10 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_20 = 11 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_19 = 12 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_18 = 13 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_17 = 14 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_16 = 15 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_15 = 16 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_14 = 17 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_13 = 18 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_12 = 19 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_11 = 20 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_10 = 21 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_9 = 22 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_8 = 23 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_7 = 24 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_6 = 25 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_5 = 26 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_4 = 27 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_3 = 28 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_2 = 29 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_1 = 30 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_0 = 31 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_63 = 32 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_62 = 33 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_61 = 34 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_60 = 35 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_59 = 36 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_58 = 37 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_57 = 38 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_56 = 39 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_55 = 40 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_54 = 41 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_53 = 42 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_52 = 43 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_51 = 44 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_50 = 45 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_49 = 46 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_48 = 47 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_47 = 48 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_46 = 49 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_45 = 50 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_44 = 51 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_43 = 52 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_42 = 53 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_41 = 54 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_40 = 55 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_39 = 56 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_38 = 57 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_37 = 58 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_36 = 59 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_35 = 60 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_34 = 61 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_33 = 62 ; -static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_32 = 63 ; - -static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN = 0 ; -static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN_LEN = 48 ; - -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55 = 0 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54 = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53 = 8 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52 = 12 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51 = 16 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50 = 20 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49 = 24 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48 = 28 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63 = 32 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62 = 36 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61 = 40 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60 = 44 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59 = 48 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58 = 52 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57 = 56 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56 = 60 ; -static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39 = 0 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38 = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37 = 8 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36 = 12 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35 = 16 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34 = 20 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33 = 24 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32 = 28 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47 = 32 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46 = 36 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45 = 40 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44 = 44 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43 = 48 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42 = 52 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41 = 56 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40 = 60 ; -static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23 = 0 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22 = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21 = 8 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20 = 12 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19 = 16 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18 = 20 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17 = 24 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16 = 28 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31 = 32 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30 = 36 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29 = 40 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28 = 44 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27 = 48 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26 = 52 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25 = 56 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24 = 60 ; -static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7 = 0 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6 = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5 = 8 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4 = 12 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3 = 16 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2 = 20 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1 = 24 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0 = 28 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15 = 32 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14 = 36 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13 = 40 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12 = 44 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11 = 48 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10 = 52 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9 = 56 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8 = 60 ; -static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_31 = 0 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_30 = 1 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_29 = 2 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_28 = 3 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_27 = 4 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_26 = 5 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_25 = 6 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_24 = 7 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_23 = 8 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_22 = 9 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_21 = 10 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_20 = 11 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_19 = 12 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_18 = 13 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_17 = 14 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_16 = 15 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_15 = 16 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_14 = 17 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_13 = 18 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_12 = 19 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_11 = 20 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_10 = 21 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_9 = 22 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_8 = 23 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_7 = 24 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_6 = 25 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_5 = 26 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_4 = 27 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_3 = 28 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_2 = 29 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_1 = 30 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_0 = 31 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_63 = 32 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_62 = 33 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_61 = 34 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_60 = 35 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_59 = 36 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_58 = 37 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_57 = 38 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_56 = 39 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_55 = 40 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_54 = 41 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_53 = 42 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_52 = 43 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_51 = 44 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_50 = 45 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_49 = 46 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_48 = 47 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_47 = 48 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_46 = 49 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_45 = 50 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_44 = 51 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_43 = 52 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_42 = 53 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_41 = 54 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_40 = 55 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_39 = 56 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_38 = 57 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_37 = 58 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_36 = 59 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_35 = 60 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_34 = 61 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_33 = 62 ; -static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_32 = 63 ; - -static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY = 0 ; -static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY = 8 ; -static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION = 32 ; -static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION = 40 ; -static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER = 56 ; -static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER_LEN = 4 ; -static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER = 60 ; -static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER_LEN = 4 ; - -static const uint8_t EXPLR_MMIO_OVPD_DATA = 0 ; -static const uint8_t EXPLR_MMIO_OVPD_DATA_LEN = 32 ; -static const uint8_t EXPLR_MMIO_OVPD_FLAG = 32 ; -static const uint8_t EXPLR_MMIO_OVPD_ADDRESS = 33 ; -static const uint8_t EXPLR_MMIO_OVPD_ADDRESS_LEN = 15 ; -static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER = 48 ; -static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER_LEN = 8 ; -static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID = 56 ; -static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_OWWID10_ID = 0 ; -static const uint8_t EXPLR_MMIO_OWWID10_ID_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_OWWID32_ID = 0 ; -static const uint8_t EXPLR_MMIO_OWWID32_ID_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA = 0 ; -static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA_LEN = 64 ; - -static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT_LEN = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_SNSC_D0THERM_ERRORBIT = 47 ; -static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA = 48 ; -static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_SNSC_D1THERM_ERRORBIT = 47 ; -static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA = 48 ; -static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT_LEN = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT_LEN = 8 ; - -static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT_LEN = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT_LEN = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_ERRORBIT = 47 ; -static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA = 48 ; -static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA_LEN = 16 ; - -static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT_LEN = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT = 32 ; -static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT_LEN = 32 ; - -static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER = 0 ; -static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER_LEN = 22 ; - -static const uint8_t EXPLR_RDF_AACR_ADDRESS = 0 ; -static const uint8_t EXPLR_RDF_AACR_ADDRESS_LEN = 7 ; -static const uint8_t EXPLR_RDF_AACR_AUTOINC = 7 ; - -static const uint8_t EXPLR_RDF_AADR_DATA = 0 ; -static const uint8_t EXPLR_RDF_AADR_DATA_LEN = 64 ; - -static const uint8_t EXPLR_RDF_AAER_DATA = 0 ; -static const uint8_t EXPLR_RDF_AAER_DATA_LEN = 8 ; - -static const uint8_t EXPLR_RDF_ACTION0_FIR = 0 ; -static const uint8_t EXPLR_RDF_ACTION0_FIR_LEN = 64 ; - -static const uint8_t EXPLR_RDF_ACTION1_FIR = 0 ; -static const uint8_t EXPLR_RDF_ACTION1_FIR_LEN = 64 ; - -static const uint8_t EXPLR_RDF_CERR0_MSR_PE = 12 ; -static const uint8_t EXPLR_RDF_CERR0_EICR_PE = 13 ; -static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE = 16 ; -static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE_LEN = 8 ; -static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE = 24 ; -static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE_LEN = 8 ; -static const uint8_t EXPLR_RDF_CERR0_RSPAR_PE = 32 ; -static const uint8_t EXPLR_RDF_CERR0_AACR_PE = 41 ; -static const uint8_t EXPLR_RDF_CERR0_MCBCM_PE = 44 ; -static const uint8_t EXPLR_RDF_CERR0_RECR_PE = 45 ; -static const uint8_t EXPLR_RDF_CERR0_DBGR_PE = 46 ; -static const uint8_t EXPLR_RDF_CERR0_MASK0_PE = 48 ; -static const uint8_t EXPLR_RDF_CERR0_MASK1_PE = 49 ; -static const uint8_t EXPLR_RDF_CERR0_CGDR_PE = 50 ; - -static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_AF_PERR = 0 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_TCHN_PERR = 1 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_CMPMODE_ERR = 2 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_PCX_PERR = 3 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYND_PERR = 4 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_2SYM_PERR = 5 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CPLX_PERR = 6 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EP2_PERR = 7 ; -static const uint8_t EXPLR_RDF_CERR1_READ_ECC_DATAPATH_PARITY_ERROR = 8 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CMX_PERR = 9 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP1_PERR = 10 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP2_PERR = 11 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYG_PERR = 12 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EF1_PERR = 13 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_MK3_PERR = 14 ; -static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_E1A_PERR = 15 ; -static const uint8_t EXPLR_RDF_CERR1_UNEXPECTED_RDDATA_VALID = 16 ; -static const uint8_t EXPLR_RDF_CERR1_MISSING_RDDATA_VALID = 17 ; -static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW0 = 20 ; -static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW0 = 21 ; -static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW1 = 22 ; -static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW1 = 23 ; -static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME = 24 ; -static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME_LEN = 8 ; - -static const uint8_t EXPLR_RDF_CGDR_CGDIS_PCTL = 0 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_RESP = 1 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_RMW = 2 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_LPTR = 3 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_AHASH = 4 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_STG = 5 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_OUT = 6 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_TLM = 7 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_BD = 8 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_DCMP = 9 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBCTL = 10 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBRMW = 11 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBTRC = 12 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_MPE = 13 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_CONF = 14 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_HWMS = 15 ; -static const uint8_t EXPLR_RDF_CGDR_PSDIS_ZERO_SYND = 16 ; -static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_MARKS = 17 ; -static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_STEER = 18 ; -static const uint8_t EXPLR_RDF_CGDR_CGDIS_SPARE = 19 ; - -static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER = 0 ; -static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER_LEN = 6 ; -static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE = 6 ; -static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN = 3 ; -static const uint8_t EXPLR_RDF_CTCR_UE_TIMER = 9 ; -static const uint8_t EXPLR_RDF_CTCR_UE_TIMER_LEN = 6 ; -static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE = 15 ; -static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE_LEN = 3 ; -static const uint8_t EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE = 18 ; - -static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT = 0 ; -static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT_LEN = 4 ; -static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT = 4 ; -static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT_LEN = 4 ; -static const uint8_t EXPLR_RDF_DBGR_EPX_CHIP = 8 ; -static const uint8_t EXPLR_RDF_DBGR_EPX_SYMS = 9 ; -static const uint8_t EXPLR_RDF_DBGR_TRACE_ALWAYS = 10 ; -static const uint8_t EXPLR_RDF_DBGR_WAT_ENABLE = 11 ; -static const uint8_t EXPLR_RDF_DBGR_WAT_ACTION_SELECT = 12 ; -static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE = 13 ; -static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE_LEN = 2 ; - -static const uint8_t EXPLR_RDF_EICR_ADDRESS = 0 ; -static const uint8_t EXPLR_RDF_EICR_ADDRESS_LEN = 37 ; -static const uint8_t EXPLR_RDF_EICR_RESERVED = 37 ; -static const uint8_t EXPLR_RDF_EICR_PERSIST = 38 ; -static const uint8_t EXPLR_RDF_EICR_PERSIST_LEN = 2 ; -static const uint8_t EXPLR_RDF_EICR_REGION = 40 ; -static const uint8_t EXPLR_RDF_EICR_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_EICR_TYPE = 43 ; -static const uint8_t EXPLR_RDF_EICR_TYPE_LEN = 5 ; -static const uint8_t EXPLR_RDF_EICR_MISC = 48 ; -static const uint8_t EXPLR_RDF_EICR_MISC_LEN = 6 ; - -static const uint8_t EXPLR_RDF_ELPR_LOG_FULL = 0 ; -static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER = 2 ; -static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER_LEN = 6 ; - -static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_PAR = 0 ; -static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_NCE = 8 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_TCE = 9 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_SCE = 10 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_MCE = 11 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_SUE = 12 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_AUE = 13 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_UE = 14 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_RCD = 15 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_IAUE = 16 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_IUE = 17 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_IRCD = 18 ; -static const uint8_t EXPLR_RDF_FIR_MAINLINE_IMPE = 19 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_NCE = 28 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_TCE = 29 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SCE = 30 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MCE = 31 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SUE = 32 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_AUE = 33 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_UE = 34 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_RCD = 35 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IAUE = 36 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IUE = 37 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IRCD = 38 ; -static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IMPE = 39 ; -static const uint8_t EXPLR_RDF_FIR_RDDATA_VALID_ERROR = 40 ; -static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_STATUS = 41 ; -static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ; -static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ; -static const uint8_t EXPLR_RDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ; -static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW0 = 45 ; -static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW1 = 46 ; -static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW0 = 47 ; -static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW1 = 48 ; -static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59 = 49 ; -static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59_LEN = 11 ; -static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_DEBUG_WAT = 60 ; -static const uint8_t EXPLR_RDF_FIR_RESERVED = 61 ; -static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR = 62 ; -static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ; - -static const uint8_t EXPLR_RDF_FWMS0_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS0_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS0_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS0_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS0_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS0_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS0_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS0_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS1_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS1_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS1_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS1_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS1_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS1_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS1_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS1_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS2_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS2_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS2_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS2_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS2_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS2_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS2_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS2_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS3_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS3_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS3_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS3_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS3_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS3_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS3_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS3_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS4_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS4_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS4_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS4_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS4_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS4_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS4_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS4_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS5_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS5_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS5_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS5_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS5_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS5_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS5_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS5_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS6_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS6_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS6_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS6_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS6_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS6_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS6_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS6_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_FWMS7_MARK = 0 ; -static const uint8_t EXPLR_RDF_FWMS7_MARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_FWMS7_TYPE = 8 ; -static const uint8_t EXPLR_RDF_FWMS7_REGION = 9 ; -static const uint8_t EXPLR_RDF_FWMS7_REGION_LEN = 3 ; -static const uint8_t EXPLR_RDF_FWMS7_ADDRESS = 12 ; -static const uint8_t EXPLR_RDF_FWMS7_ADDRESS_LEN = 11 ; -static const uint8_t EXPLR_RDF_FWMS7_EXIT_1 = 23 ; - -static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS0_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS0_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS1_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS1_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS2_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS2_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS3_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS3_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS4_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS4_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS5_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS5_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS6_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS6_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK = 0 ; -static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_HWMS7_CONFIRMED = 8 ; -static const uint8_t EXPLR_RDF_HWMS7_EXIT_1 = 9 ; - -static const uint8_t EXPLR_RDF_MASK_FIR = 0 ; -static const uint8_t EXPLR_RDF_MASK_FIR_LEN = 64 ; - -static const uint8_t EXPLR_RDF_MASK0_MSR_PE = 12 ; -static const uint8_t EXPLR_RDF_MASK0_EICR_PE = 13 ; -static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE = 16 ; -static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE_LEN = 8 ; -static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE = 24 ; -static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE_LEN = 8 ; -static const uint8_t EXPLR_RDF_MASK0_RSPAR_PE = 32 ; -static const uint8_t EXPLR_RDF_MASK0_CTCR_PE = 40 ; -static const uint8_t EXPLR_RDF_MASK0_AACR_PE = 41 ; -static const uint8_t EXPLR_RDF_MASK0_MCBCM_PE = 44 ; -static const uint8_t EXPLR_RDF_MASK0_RECR_PE = 45 ; -static const uint8_t EXPLR_RDF_MASK0_DBGR_PE = 46 ; -static const uint8_t EXPLR_RDF_MASK0_MASK0_PE = 48 ; -static const uint8_t EXPLR_RDF_MASK0_MASK1_PE = 49 ; -static const uint8_t EXPLR_RDF_MASK0_CGDR_PE = 50 ; - -static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_AF_PERR = 0 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_TCHN_PERR = 1 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_CMPMODE_ERR = 2 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_PCX_PERR = 3 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYND_PERR = 4 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_2SYM_PERR = 5 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CPLX_PERR = 6 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EP2_PERR = 7 ; -static const uint8_t EXPLR_RDF_MASK1_READ_ECC_DATAPATH_PARITY_ERROR = 8 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CMX_PERR = 9 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP1_PERR = 10 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP2_PERR = 11 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYG_PERR = 12 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EF1_PERR = 13 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_MK3_PERR = 14 ; -static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_E1A_PERR = 15 ; -static const uint8_t EXPLR_RDF_MASK1_UNEXPECTED_RDDATA_VALID = 16 ; -static const uint8_t EXPLR_RDF_MASK1_MISSING_RDDATA_VALID = 17 ; - -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK = 0 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN = 40 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR = 40 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_NONSTOP = 41 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_CE_ENABLE = 42 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_MPE_ENABLE = 43 ; -static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_UE_ENABLE = 44 ; - -static const uint8_t EXPLR_RDF_MSR_CHIPMARK = 8 ; -static const uint8_t EXPLR_RDF_MSR_CHIPMARK_LEN = 8 ; -static const uint8_t EXPLR_RDF_MSR_RANK = 16 ; -static const uint8_t EXPLR_RDF_MSR_RANK_LEN = 3 ; - -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 0 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 1 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE = 2 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UE_RETRY = 3 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ITAG_METADATA_ENABLE = 4 ; -static const uint8_t EXPLR_RDF_RECR_DISABLE_RCD_CHECK = 5 ; -static const uint8_t EXPLR_RDF_RECR_DISABLE_RDDATA_VALID_CHECK = 6 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UTC_EXIT_INCREASE = 8 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE = 9 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE_LEN = 2 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_HWMARK_EXIT1 = 11 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_ENABLE = 14 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_ENABLE = 15 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT = 16 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT_LEN = 4 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT = 20 ; -static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT_LEN = 4 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MPE_CONFIRM = 25 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 26 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION = 27 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 28 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH = 29 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION = 30 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN = 2 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 32 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE = 33 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE = 34 ; -static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_BYPASS_MARK_PLACE = 39 ; -static const uint8_t EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS = 40 ; -static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT = 41 ; -static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT_LEN = 6 ; - -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT = 0 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT = 10 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT = 15 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT = 20 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT = 25 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT = 30 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT_LEN = 5 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT = 35 ; -static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT_LEN = 5 ; - -static const uint8_t EXPLR_RDF_WOF_FIR = 0 ; -static const uint8_t EXPLR_RDF_WOF_FIR_LEN = 64 ; - -static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_PAR = 0 ; -static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE = 0 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 1 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3 = 1 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_1_3_LEN = 3 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR = 4 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN = 5 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15 = 9 ; +static const uint8_t EXPLR_MCBIST_MCBSTATQ_RESERVED_9_15_LEN = 7 ; + +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_START = 0 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_STOP = 1 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5 = 2 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESERVED_2_5_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_TRAP_CNFG = 6 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS = 7 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE = 8 ; + +static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_IP = 0 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_DONE = 1 ; +static const uint8_t EXPLR_MCBIST_MCB_CNTLSTATQ_FAIL = 2 ; + +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM = 0 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1 = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD1_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2 = 8 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD2_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3 = 12 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD3_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4 = 16 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD4_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5 = 20 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD5_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6 = 24 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD6_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7 = 28 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD7_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8 = 32 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD8_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9 = 36 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD9_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10 = 40 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD10_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11 = 44 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD11_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12 = 48 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD12_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13 = 52 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD13_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14 = 56 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD14_LEN = 4 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15 = 60 ; +static const uint8_t EXPLR_MCBIST_RCD_LRDIM_CNTL_WORD0_15Q_LRDIMM_WORD15_LEN = 4 ; + +static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR = 0 ; +static const uint8_t EXPLR_MCBIST_RUNTIMECTRQ_CFG_RUNTIME_CTR_LEN = 37 ; + +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ASEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_BSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL = 16 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ABSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL = 24 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_ETSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL = 32 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CMSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL = 40 ; +static const uint8_t EXPLR_MCBIST_WATCFG0AQ_CFG_WAT_EVENT_CYSEL_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_MSKA_LEN = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_WAT_ENABLE = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_INT_ARM_MODE = 45 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_EXT_ARM_MODE = 46 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TIMER_STATE_MODE = 47 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SET_LEVEL_ON_PULSE = 48 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_RESET_LEVEL_ON_PULSE = 49 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_ENABLE_EXT_RESET_LEVEL = 50 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_SET_DOM = 51 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_STATE_FOLLOW_LEVEL = 52 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE = 53 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE = 54 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATA_MODE2 = 55 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_NOT_PATB_MODE2 = 56 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_SLIDE_TRIG = 57 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL = 58 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_TRIGB_DELAY_SEL_LEN = 2 ; +static const uint8_t EXPLR_MCBIST_WATCFG0BQ_CFG_FORCE_TEST_MODE = 60 ; + +static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG0CQ_CFG_WAT_MSKB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG0DQ_CFG_WAT_PATA_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG0EQ_CFG_WAT_PATB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ASEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_BSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL = 16 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ABSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL = 24 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_ETSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL = 32 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CMSEL_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL = 40 ; +static const uint8_t EXPLR_MCBIST_WATCFG1AQ_CFG_WAT_EVENT_CYSEL_LEN = 8 ; + +static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_MSKA_LEN = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG1BQ_CFG_WAT_CNTL_LEN = 17 ; + +static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG1CQ_CFG_WAT_MSKB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG1DQ_CFG_WAT_PATA_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG1EQ_CFG_WAT_PATB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG2AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; + +static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_MSKA_LEN = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG2BQ_CFG_WAT_CNTL_LEN = 17 ; + +static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG2CQ_CFG_WAT_MSKB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG2DQ_CFG_WAT_PATA_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG2EQ_CFG_WAT_PATB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG3AQ_CFG_WAT_EVENT_SEL_LEN = 48 ; + +static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_MSKA_LEN = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL = 44 ; +static const uint8_t EXPLR_MCBIST_WATCFG3BQ_CFG_WAT_CNTL_LEN = 17 ; + +static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG3CQ_CFG_WAT_MSKB_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG3DQ_CFG_WAT_PATA_LEN = 44 ; + +static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB = 0 ; +static const uint8_t EXPLR_MCBIST_WATCFG3EQ_CFG_WAT_PATB_LEN = 44 ; + +static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE = 16 ; +static const uint8_t EXPLR_MMIO_MCFGERR_RESP_CODE_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MCFGERR_BDI = 20 ; +static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE = 21 ; +static const uint8_t EXPLR_MMIO_MCFGERR_ERROR_TYPE_LEN = 3 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE = 24 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DEVICE_LEN = 5 ; +static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION = 29 ; +static const uint8_t EXPLR_MMIO_MCFGERR_FUNCTION_LEN = 3 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DEV_FUNC_MISMATCH = 32 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DETECT_BAD_OP = 33 ; +static const uint8_t EXPLR_MMIO_MCFGERR_TBIT_IS_1 = 34 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DATA_IS_BAD = 35 ; +static const uint8_t EXPLR_MMIO_MCFGERR_PL_IS_INVALID = 36 ; +static const uint8_t EXPLR_MMIO_MCFGERR_BAD_OP_OR_ALIGN = 37 ; +static const uint8_t EXPLR_MMIO_MCFGERR_ADDR_NO_IMPLEMENTED = 38 ; +static const uint8_t EXPLR_MMIO_MCFGERR_RDATA_VLD = 39 ; +static const uint8_t EXPLR_MMIO_MCFGERR_TBIT = 40 ; +static const uint8_t EXPLR_MMIO_MCFGERR_PLEN = 41 ; +static const uint8_t EXPLR_MMIO_MCFGERR_PLEN_LEN = 3 ; +static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM = 44 ; +static const uint8_t EXPLR_MMIO_MCFGERR_PORTNUM_LEN = 2 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DL = 46 ; +static const uint8_t EXPLR_MMIO_MCFGERR_DL_LEN = 2 ; +static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG = 48 ; +static const uint8_t EXPLR_MMIO_MCFGERR_CAPPTAG_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR = 0 ; +static const uint8_t EXPLR_MMIO_MCFGERRA_ADDR_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MCHOLD_FIR_MASK_PAR_ERR = 0 ; +static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION0_PAR_ERR = 1 ; +static const uint8_t EXPLR_MMIO_MCHOLD_FIR_ACTION1_PAR_ERR = 2 ; + +static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_MASK_PAR_ERR = 0 ; +static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION0_PAR_ERR = 1 ; +static const uint8_t EXPLR_MMIO_MCMASK_MASK_FIR_ACTION1_PAR_ERR = 2 ; + +static const uint8_t EXPLR_MMIO_MDBELL_MDBELL = 0 ; + +static const uint8_t EXPLR_MMIO_MDBELLC_MDBELL_MDBELL = 0 ; + +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87 = 0 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGBUS_64_87_LEN = 24 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE = 24 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_SPARE_LEN = 8 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7 = 32 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL7_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6 = 36 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL6_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5 = 40 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL5_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4 = 44 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL4_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3 = 48 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL3_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2 = 52 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL2_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1 = 56 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL1_LEN = 4 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0 = 60 ; +static const uint8_t EXPLR_MMIO_MDEBUG0_DBGSEL0_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63 = 0 ; +static const uint8_t EXPLR_MMIO_MDEBUG1_DBGBUS_0_63_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MENTERP_MMIO_ENTERPRISE_MODE = 0 ; +static const uint8_t EXPLR_MMIO_MENTERP_HALF_DIMM_MODE = 1 ; +static const uint8_t EXPLR_MMIO_MENTERP_CFG_ENTERPRISE_MODE = 2 ; + +static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS = 0 ; +static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_LEN = 44 ; +static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46 = 44 ; +static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BITS_44_46_LEN = 3 ; +static const uint8_t EXPLR_MMIO_MERRCTL_PASID_CHK_DIS = 47 ; +static const uint8_t EXPLR_MMIO_MERRCTL_ACTAG_CHK_DIS = 48 ; +static const uint8_t EXPLR_MMIO_MERRCTL_MSCC_RNGE_CHK_DIS = 49 ; +static const uint8_t EXPLR_MMIO_MERRCTL_MODE_BIT_50 = 50 ; +static const uint8_t EXPLR_MMIO_MERRCTL_HOLD_ACUM = 51 ; +static const uint8_t EXPLR_MMIO_MERRCTL_SNSC_MASTER_ENABLE = 52 ; +static const uint8_t EXPLR_MMIO_MERRCTL_TRAP_CLEAR = 53 ; +static const uint8_t EXPLR_MMIO_MERRCTL_WDATA_P = 54 ; +static const uint8_t EXPLR_MMIO_MERRCTL_RNW = 55 ; +static const uint8_t EXPLR_MMIO_MERRCTL_ADDR = 56 ; +static const uint8_t EXPLR_MMIO_MERRCTL_ADDR_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_MFIR_AFU_DESC_UNIMP = 0 ; +static const uint8_t EXPLR_MMIO_MFIR_MMIO_ERR = 1 ; +static const uint8_t EXPLR_MMIO_MFIR_SCOM_ERR = 2 ; +static const uint8_t EXPLR_MMIO_MFIR_FSM_PERR = 3 ; +static const uint8_t EXPLR_MMIO_MFIR_FIFO_OVERFLOW = 4 ; +static const uint8_t EXPLR_MMIO_MFIR_CTL_REG_PERR = 5 ; +static const uint8_t EXPLR_MMIO_MFIR_INFO_REG_PERR = 6 ; +static const uint8_t EXPLR_MMIO_MFIR_SNSC_BOTH_STARTS_ERR = 7 ; +static const uint8_t EXPLR_MMIO_MFIR_SNSC_MULT_SEQ_PERR = 8 ; +static const uint8_t EXPLR_MMIO_MFIR_SNSC_FSM_PERR = 9 ; +static const uint8_t EXPLR_MMIO_MFIR_SNSC_REG_PERR = 10 ; +static const uint8_t EXPLR_MMIO_MFIR_ACTAG_PASID_CFG_ERR = 11 ; + +static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0 = 0 ; +static const uint8_t EXPLR_MMIO_MFIRACT0_FIR_ACTION0_LEN = 12 ; + +static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1 = 0 ; +static const uint8_t EXPLR_MMIO_MFIRACT1_FIR_ACTION1_LEN = 12 ; + +static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK = 0 ; +static const uint8_t EXPLR_MMIO_MFIRMASK_FIR_MASK_LEN = 12 ; + +static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF = 0 ; +static const uint8_t EXPLR_MMIO_MFIRWOF_FIR_WOF_LEN = 12 ; + +static const uint8_t EXPLR_MMIO_MHOLD0_O0MBIT_O0DID_PERR = 0 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0CCD_PERR = 1 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR0_PERR = 2 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR1_PERR = 3 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0BAR2_PERR = 4 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0SSYSID_PERR = 5 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0CAPPTR_O0ROMBAR_PERR = 6 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OVPD_PERR = 7 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ODSNLO_ODSNCAP_PERR = 8 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ODSNHI_PERR = 9 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTLVID_OTLCAP_PERR = 10 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OVERCAP_OTLID_PERR = 11 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OVERCFG_PERR = 12 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ORTCAP_PERR = 13 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTTCFG_PERR = 14 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP10_PERR = 15 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP32_PERR = 16 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP54_PERR = 17 ; +static const uint8_t EXPLR_MMIO_MHOLD0_ORRCAP76_PERR = 18 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG10_PERR = 19 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG32_PERR = 20 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG54_PERR = 21 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OTRCFG76_PERR = 22 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0FNVID_O0FNCAP_PERR = 23 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0ACTAG_O0FNID_PERR = 24 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0VSVID_O0VSCAP_PERR = 25 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O0VSID_PERR = 26 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1MBIT_O1DID_PERR = 27 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1CCD_PERR = 28 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR0_PERR = 29 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR1_PERR = 30 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1BAR2_PERR = 31 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1SSYSID_PERR = 32 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1CAPPTR_O1ROMBAR_PERR = 33 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OPASID_PERR = 34 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1FNVID_O1FNCAP_PERR = 35 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1ACTAG_O1FNID_PERR = 36 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1INFVID_O1INFCAP_PERR = 37 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1INFOFF_O1INFID_PERR = 38 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1INFDAT_PERR = 39 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLVID_OCTRLCAP_PERR = 40 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLENB_OCTRLID_PERR = 41 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLPID_PERR = 42 ; +static const uint8_t EXPLR_MMIO_MHOLD0_OCTRLTAG_PERR = 43 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1VSVID_O1VSCAP_PERR = 44 ; +static const uint8_t EXPLR_MMIO_MHOLD0_O1VSID_PERR = 45 ; +static const uint8_t EXPLR_MMIO_MHOLD0_AFU_DESC_UNIMP = 46 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MMIO_ERR = 47 ; +static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_ERR = 48 ; +static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CCMD_FSMPERR = 49 ; +static const uint8_t EXPLR_MMIO_MHOLD0_SCOM_CRESP_FSMPERR = 50 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CTL_MMIO_FSMPERR = 51 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CCMD_FSMPERR = 52 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CTL_CRESP_FSMPERR = 53 ; +static const uint8_t EXPLR_MMIO_MHOLD0_PIB_FSMPERR = 54 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CMUX_ARBPERR = 55 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CFG_CMDFIFO_OVRFLOW = 56 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CFG_RESPFIFO_OVRFLOW = 57 ; +static const uint8_t EXPLR_MMIO_MHOLD0_CFGP_FIFO_OVRFLOW = 58 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MERRCTL_PERR = 59 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MHOLD1_PERR = 60 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MMASK1_PERR = 61 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MDBELL_PERR = 62 ; +static const uint8_t EXPLR_MMIO_MHOLD0_MSCCRNGE_PERR = 63 ; + +static const uint8_t EXPLR_MMIO_MHOLD1_ONAME0_ODESCTML_PERR = 0 ; +static const uint8_t EXPLR_MMIO_MHOLD1_ONAME21_PERR = 1 ; +static const uint8_t EXPLR_MMIO_MHOLD1_ONAME43_PERR = 2 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OAFUVER_ONAME5_PERR = 3 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOOF_PERR = 4 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OGMMIOSZ_PERR = 5 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOOOF_PERR = 6 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OPMMIOST_PERR = 7 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OMEMADDR_PERR = 8 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OWWID10_PERR = 9 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OWWID32_PERR = 10 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MHOLD0_PERR = 11 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MMASK0_PERR = 12 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MMIOERR_PERR = 13 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MMIOEWD_PERR = 14 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SCOMEWD_PERR = 15 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRA_PERR = 16 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MCFGERRB_PERR = 17 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_BOTH_STARTS_ERR = 18 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_MULT_SEQ_PERR = 19 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FSM_PERR = 20 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_OCTHERM_PERR = 21 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D0THERM_PERR = 22 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_D1THERM_PERR = 23 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_RDWR_PERR = 24 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_ACTPWRUP_PERR = 25 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_FRAMESR_PERR = 26 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASELOW_PERR = 27 ; +static const uint8_t EXPLR_MMIO_MHOLD1_SNSC_HISTOBASEHIGH_PERR = 28 ; +static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXA_PERR = 29 ; +static const uint8_t EXPLR_MMIO_MHOLD1_O0VSTLXB_PERR = 30 ; +static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXA_PERR = 31 ; +static const uint8_t EXPLR_MMIO_MHOLD1_O0VSDLXB_PERR = 32 ; +static const uint8_t EXPLR_MMIO_MHOLD1_O0VSFLSH_PERR = 33 ; +static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_ACTAG_LENGTH = 34 ; +static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_ACTAG_LENGTH = 35 ; +static const uint8_t EXPLR_MMIO_MHOLD1_BAD_FUNC_PASID_LENGTH = 36 ; +static const uint8_t EXPLR_MMIO_MHOLD1_BAD_AFU_PASID_LENGTH = 37 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MENTRP_PERR = 38 ; +static const uint8_t EXPLR_MMIO_MHOLD1_OSYSMEML_PERR = 39 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG0_PERR = 40 ; +static const uint8_t EXPLR_MMIO_MHOLD1_MDEBUG1_PERR = 41 ; + +static const uint8_t EXPLR_MMIO_MMASK0_MSK = 0 ; +static const uint8_t EXPLR_MMIO_MMASK0_MSK_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MMASK1_MSK = 0 ; +static const uint8_t EXPLR_MMIO_MMASK1_MSK_LEN = 42 ; + +static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P = 0 ; +static const uint8_t EXPLR_MMIO_MMIOERR_WDATA_P_LEN = 8 ; +static const uint8_t EXPLR_MMIO_MMIOERR_INFO = 8 ; +static const uint8_t EXPLR_MMIO_MMIOERR_INFO_LEN = 16 ; +static const uint8_t EXPLR_MMIO_MMIOERR_PLEN = 25 ; +static const uint8_t EXPLR_MMIO_MMIOERR_PLEN_LEN = 3 ; +static const uint8_t EXPLR_MMIO_MMIOERR_RNW = 28 ; +static const uint8_t EXPLR_MMIO_MMIOERR_ADDR = 29 ; +static const uint8_t EXPLR_MMIO_MMIOERR_ADDR_LEN = 35 ; + +static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA = 0 ; +static const uint8_t EXPLR_MMIO_MMIOEWD_WDATA_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO = 0 ; +static const uint8_t EXPLR_MMIO_MPIBERR0_ERRINFO_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO = 0 ; +static const uint8_t EXPLR_MMIO_MPIBERR1_ERRINFO_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO = 0 ; +static const uint8_t EXPLR_MMIO_MPIBERR2_ERRINFO_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO = 0 ; +static const uint8_t EXPLR_MMIO_MPIBERR3_ERRINFO_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER = 0 ; +static const uint8_t EXPLR_MMIO_MSCCRNGE_LOWER_LEN = 29 ; +static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER = 32 ; +static const uint8_t EXPLR_MMIO_MSCCRNGE_UPPER_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE = 4 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_BASE_LEN = 12 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH = 20 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_ACTAG_LENGTH_LEN = 12 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_AFU_PRESENT = 32 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX = 34 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_MAX_AFU_INDEX_LEN = 6 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_FUNCTION_RESET = 40 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_O0ACTAG_O0FNID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O0BAR0_BAR_ADDRESS_LEN = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR0_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR0_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O0BAR0_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O0BAR0_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O0BAR1_BAR_ADDRESS_LEN = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR1_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR1_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O0BAR1_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O0BAR1_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O0BAR2_BAR_ADDRESS_LEN = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR2_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O0BAR2_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O0BAR2_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O0BAR2_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE = 32 ; +static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_BASE_LEN = 21 ; +static const uint8_t EXPLR_MMIO_O0CAPPTR_O0ROMBAR_ROM_ENABLE = 63 ; + +static const uint8_t EXPLR_MMIO_O0CCD_MULTI_FUNCTION = 8 ; +static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE = 32 ; +static const uint8_t EXPLR_MMIO_O0CCD_CLASS_CODE_LEN = 24 ; +static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID = 56 ; +static const uint8_t EXPLR_MMIO_O0CCD_REVISION_ID_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_CAPABILITIES_LIST = 11 ; +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_MEMORY_SPACE = 30 ; +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID = 32 ; +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_DEVICE_ID_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID = 48 ; +static const uint8_t EXPLR_MMIO_O0MBIT_O0DID_VENDOR_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID = 0 ; +static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_ID_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID = 16 ; +static const uint8_t EXPLR_MMIO_O0SSYSID_SUBSYSTEM_VENDOR_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1 = 0 ; +static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT1_LEN = 32 ; +static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0 = 32 ; +static const uint8_t EXPLR_MMIO_O0VSDLXA_DLX_PORT0_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3 = 0 ; +static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT3_LEN = 32 ; +static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2 = 32 ; +static const uint8_t EXPLR_MMIO_O0VSDLXB_DLX_PORT2_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA = 0 ; +static const uint8_t EXPLR_MMIO_O0VSFLSH_DATA_LEN = 32 ; +static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL = 44 ; +static const uint8_t EXPLR_MMIO_O0VSFLSH_CONTROL_LEN = 20 ; + +static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE = 32 ; +static const uint8_t EXPLR_MMIO_O0VSID_VENDOR_UNIQUE_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_O0VSID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1 = 0 ; +static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT1_LEN = 32 ; +static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0 = 32 ; +static const uint8_t EXPLR_MMIO_O0VSTLXA_TLX_PORT0_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3 = 0 ; +static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT3_LEN = 32 ; +static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2 = 32 ; +static const uint8_t EXPLR_MMIO_O0VSTLXB_TLX_PORT2_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE = 4 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_BASE_LEN = 12 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH = 20 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_ACTAG_LENGTH_LEN = 12 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_AFU_PRESENT = 32 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX = 34 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_MAX_AFU_INDEX_LEN = 6 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_FUNCTION_RESET = 40 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_O1ACTAG_O1FNID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O1BAR0_BAR_ADDRESS_LEN = 29 ; +static const uint8_t EXPLR_MMIO_O1BAR0_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O1BAR0_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O1BAR0_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O1BAR0_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O1BAR1_BAR_ADDRESS_LEN = 60 ; +static const uint8_t EXPLR_MMIO_O1BAR1_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O1BAR1_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O1BAR1_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O1BAR1_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS = 0 ; +static const uint8_t EXPLR_MMIO_O1BAR2_BAR_ADDRESS_LEN = 60 ; +static const uint8_t EXPLR_MMIO_O1BAR2_PREFETCHABLE = 60 ; +static const uint8_t EXPLR_MMIO_O1BAR2_TYPE = 61 ; +static const uint8_t EXPLR_MMIO_O1BAR2_TYPE_LEN = 2 ; +static const uint8_t EXPLR_MMIO_O1BAR2_ADDRESS_SPACE = 63 ; + +static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE = 32 ; +static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_BASE_LEN = 21 ; +static const uint8_t EXPLR_MMIO_O1CAPPTR_O1ROMBAR_ROM_ENABLE = 63 ; + +static const uint8_t EXPLR_MMIO_O1CCD_MULTI_FUNCTION = 8 ; +static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE = 32 ; +static const uint8_t EXPLR_MMIO_O1CCD_CLASS_CODE_LEN = 24 ; +static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID = 56 ; +static const uint8_t EXPLR_MMIO_O1CCD_REVISION_ID_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA = 32 ; +static const uint8_t EXPLR_MMIO_O1INFDAT_AFU_DESCRIPTOR_DATA_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DATA_VALID = 0 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET = 1 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_DESCRIPTOR_OFFSET_LEN = 31 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX = 42 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_AFU_INFO_INDEX_LEN = 6 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_O1INFOFF_O1INFID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_CAPABILITIES_LIST = 11 ; +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_MEMORY_SPACE = 30 ; +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID = 32 ; +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_DEVICE_ID_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID = 48 ; +static const uint8_t EXPLR_MMIO_O1MBIT_O1DID_VENDOR_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID = 0 ; +static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_ID_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID = 16 ; +static const uint8_t EXPLR_MMIO_O1SSYSID_SUBSYSTEM_VENDOR_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE = 32 ; +static const uint8_t EXPLR_MMIO_O1VSID_VENDOR_UNIQUE_LEN = 16 ; +static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_O1VSID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR = 0 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MAJOR_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_VERSION_MINOR_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE = 16 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_C_TYPE_LEN = 3 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE = 19 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_AFU_M_TYPE_LEN = 3 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE = 24 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_PROFILE_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23 = 32 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_23_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22 = 40 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_22_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21 = 48 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_21_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20 = 56 ; +static const uint8_t EXPLR_MMIO_OAFUVER_ONAME5_NAME_SPACE_20_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE = 0 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_UNIQUE_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_FENCE_AFU = 6 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_ENABLE_AFU = 7 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_RESET_AFU = 8 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_TERMINATE_VALID = 11 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE = 12 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_PASID_TERMINATION_VALUE_LEN = 20 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX = 42 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_AFU_CONTROL_INDEX_LEN = 6 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID = 48 ; +static const uint8_t EXPLR_MMIO_OCTRLENB_OCTRLID_DVSEC_ID_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_SUPPORTED = 0 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_METADATA_ENABLED = 1 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL = 2 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_HTRL_LEN = 3 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE = 12 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_BASE_LEN = 20 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED = 51 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_ENABLED_LEN = 5 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED = 59 ; +static const uint8_t EXPLR_MMIO_OCTRLPID_PASID_LENGTH_SUPPORTED_LEN = 5 ; + +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE = 20 ; +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_BASE_LEN = 12 ; +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED = 36 ; +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_ENABLED_LEN = 12 ; +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED = 52 ; +static const uint8_t EXPLR_MMIO_OCTRLTAG_AFU_ACTAG_LENGTH_SUPPORTED_LEN = 12 ; + +static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH = 32 ; +static const uint8_t EXPLR_MMIO_ODSNHI_DSN_HIGH_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW = 0 ; +static const uint8_t EXPLR_MMIO_ODSNLO_ODSNCAP_DSN_LOW_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET = 0 ; +static const uint8_t EXPLR_MMIO_OGMMIOOF_OFFSET_LEN = 48 ; +static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR = 61 ; +static const uint8_t EXPLR_MMIO_OGMMIOOF_BAR_LEN = 3 ; + +static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE = 32 ; +static const uint8_t EXPLR_MMIO_OGMMIOSZ_SIZE_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR = 0 ; +static const uint8_t EXPLR_MMIO_OMEMADDR_ADDR_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3 = 0 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_3_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2 = 8 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_2_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1 = 16 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_1_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0 = 24 ; +static const uint8_t EXPLR_MMIO_ONAME0_ODESCTML_NAME_SPACE_0_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11 = 0 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_11_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10 = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_10_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9 = 16 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_9_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8 = 24 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_8_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7 = 32 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_7_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6 = 40 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_6_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5 = 48 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_5_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4 = 56 ; +static const uint8_t EXPLR_MMIO_ONAME21_NAME_SPACE_4_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19 = 0 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_19_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18 = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_18_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17 = 16 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_17_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16 = 24 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_16_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15 = 32 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_15_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14 = 40 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_14_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13 = 48 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_13_LEN = 8 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12 = 56 ; +static const uint8_t EXPLR_MMIO_ONAME43_NAME_SPACE_12_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH = 19 ; +static const uint8_t EXPLR_MMIO_OPASID_MAX_PASID_WIDTH_LEN = 5 ; + +static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET = 0 ; +static const uint8_t EXPLR_MMIO_OPMMIOOF_OFFSET_LEN = 48 ; +static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR = 61 ; +static const uint8_t EXPLR_MMIO_OPMMIOOF_BAR_LEN = 3 ; + +static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE = 24 ; +static const uint8_t EXPLR_MMIO_OPMMIOST_MEM_SIZE_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE = 32 ; +static const uint8_t EXPLR_MMIO_OPMMIOST_STRIDE_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55 = 0 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_55_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54 = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_54_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53 = 8 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_53_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52 = 12 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_52_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51 = 16 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_51_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50 = 20 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_50_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49 = 24 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_49_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48 = 28 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_48_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63 = 32 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_63_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62 = 36 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_62_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61 = 40 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_61_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60 = 44 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_60_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59 = 48 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_59_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58 = 52 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_58_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57 = 56 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_57_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56 = 60 ; +static const uint8_t EXPLR_MMIO_ORRCAP10_TEMPLATE_56_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39 = 0 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_39_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38 = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_38_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37 = 8 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_37_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36 = 12 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_36_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35 = 16 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_35_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34 = 20 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_34_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33 = 24 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_33_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32 = 28 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_32_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47 = 32 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_47_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46 = 36 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_46_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45 = 40 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_45_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44 = 44 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_44_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43 = 48 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_43_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42 = 52 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_42_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41 = 56 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_41_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40 = 60 ; +static const uint8_t EXPLR_MMIO_ORRCAP32_TEMPLATE_40_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23 = 0 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_23_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22 = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_22_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21 = 8 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_21_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20 = 12 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_20_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19 = 16 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_19_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18 = 20 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_18_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17 = 24 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_17_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16 = 28 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_16_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31 = 32 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_31_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30 = 36 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_30_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29 = 40 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_29_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28 = 44 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_28_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27 = 48 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_27_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26 = 52 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_26_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25 = 56 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_25_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24 = 60 ; +static const uint8_t EXPLR_MMIO_ORRCAP54_TEMPLATE_24_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7 = 0 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_7_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6 = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_6_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5 = 8 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_5_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4 = 12 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_4_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3 = 16 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_3_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2 = 20 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_2_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1 = 24 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_1_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0 = 28 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_0_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15 = 32 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_15_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14 = 36 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_14_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13 = 40 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_13_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12 = 44 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_12_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11 = 48 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_11_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10 = 52 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_10_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9 = 56 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_9_LEN = 4 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8 = 60 ; +static const uint8_t EXPLR_MMIO_ORRCAP76_TEMPLATE_8_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_31 = 0 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_30 = 1 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_29 = 2 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_28 = 3 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_27 = 4 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_26 = 5 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_25 = 6 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_24 = 7 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_23 = 8 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_22 = 9 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_21 = 10 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_20 = 11 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_19 = 12 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_18 = 13 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_17 = 14 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_16 = 15 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_15 = 16 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_14 = 17 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_13 = 18 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_12 = 19 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_11 = 20 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_10 = 21 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_9 = 22 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_8 = 23 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_7 = 24 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_6 = 25 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_5 = 26 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_4 = 27 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_3 = 28 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_2 = 29 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_1 = 30 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_0 = 31 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_63 = 32 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_62 = 33 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_61 = 34 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_60 = 35 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_59 = 36 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_58 = 37 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_57 = 38 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_56 = 39 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_55 = 40 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_54 = 41 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_53 = 42 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_52 = 43 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_51 = 44 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_50 = 45 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_49 = 46 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_48 = 47 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_47 = 48 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_46 = 49 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_45 = 50 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_44 = 51 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_43 = 52 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_42 = 53 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_41 = 54 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_40 = 55 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_39 = 56 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_38 = 57 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_37 = 58 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_36 = 59 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_35 = 60 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_34 = 61 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_33 = 62 ; +static const uint8_t EXPLR_MMIO_ORTCAP_TEMPLATE_32 = 63 ; + +static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN = 0 ; +static const uint8_t EXPLR_MMIO_OSYSMEML_SYSLEN_LEN = 48 ; + +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55 = 0 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_55_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54 = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_54_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53 = 8 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_53_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52 = 12 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_52_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51 = 16 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_51_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50 = 20 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_50_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49 = 24 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_49_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48 = 28 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_48_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63 = 32 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_63_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62 = 36 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_62_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61 = 40 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_61_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60 = 44 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_60_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59 = 48 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_59_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58 = 52 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_58_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57 = 56 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_57_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56 = 60 ; +static const uint8_t EXPLR_MMIO_OTRCFG10_TEMPLATE_56_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39 = 0 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_39_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38 = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_38_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37 = 8 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_37_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36 = 12 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_36_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35 = 16 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_35_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34 = 20 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_34_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33 = 24 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_33_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32 = 28 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_32_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47 = 32 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_47_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46 = 36 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_46_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45 = 40 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_45_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44 = 44 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_44_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43 = 48 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_43_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42 = 52 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_42_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41 = 56 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_41_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40 = 60 ; +static const uint8_t EXPLR_MMIO_OTRCFG32_TEMPLATE_40_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23 = 0 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_23_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22 = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_22_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21 = 8 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_21_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20 = 12 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_20_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19 = 16 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_19_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18 = 20 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_18_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17 = 24 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_17_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16 = 28 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_16_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31 = 32 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_31_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30 = 36 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_30_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29 = 40 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_29_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28 = 44 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_28_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27 = 48 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_27_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26 = 52 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_26_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25 = 56 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_25_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24 = 60 ; +static const uint8_t EXPLR_MMIO_OTRCFG54_TEMPLATE_24_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7 = 0 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_7_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6 = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_6_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5 = 8 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_5_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4 = 12 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_4_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3 = 16 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_3_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2 = 20 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_2_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1 = 24 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_1_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0 = 28 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_0_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15 = 32 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_15_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14 = 36 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_14_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13 = 40 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_13_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12 = 44 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_12_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11 = 48 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_11_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10 = 52 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_10_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9 = 56 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_9_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8 = 60 ; +static const uint8_t EXPLR_MMIO_OTRCFG76_TEMPLATE_8_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_31 = 0 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_30 = 1 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_29 = 2 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_28 = 3 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_27 = 4 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_26 = 5 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_25 = 6 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_24 = 7 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_23 = 8 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_22 = 9 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_21 = 10 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_20 = 11 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_19 = 12 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_18 = 13 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_17 = 14 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_16 = 15 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_15 = 16 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_14 = 17 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_13 = 18 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_12 = 19 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_11 = 20 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_10 = 21 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_9 = 22 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_8 = 23 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_7 = 24 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_6 = 25 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_5 = 26 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_4 = 27 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_3 = 28 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_2 = 29 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_1 = 30 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_0 = 31 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_63 = 32 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_62 = 33 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_61 = 34 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_60 = 35 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_59 = 36 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_58 = 37 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_57 = 38 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_56 = 39 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_55 = 40 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_54 = 41 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_53 = 42 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_52 = 43 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_51 = 44 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_50 = 45 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_49 = 46 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_48 = 47 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_47 = 48 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_46 = 49 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_45 = 50 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_44 = 51 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_43 = 52 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_42 = 53 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_41 = 54 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_40 = 55 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_39 = 56 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_38 = 57 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_37 = 58 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_36 = 59 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_35 = 60 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_34 = 61 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_33 = 62 ; +static const uint8_t EXPLR_MMIO_OTTCFG_TEMPLATE_32 = 63 ; + +static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY = 0 ; +static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MAJOR_VERSION_CAPABILITY_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY = 8 ; +static const uint8_t EXPLR_MMIO_OVERCAP_OTLID_TL_MINOR_VERSION_CAPABILITY_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION = 32 ; +static const uint8_t EXPLR_MMIO_OVERCFG_TL_MAJOR_VERSION_CONFIGURATION_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION = 40 ; +static const uint8_t EXPLR_MMIO_OVERCFG_TL_MINOR_VERSION_CONFIGURATION_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER = 56 ; +static const uint8_t EXPLR_MMIO_OVERCFG_LONG_BACK_OFF_TIMER_LEN = 4 ; +static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER = 60 ; +static const uint8_t EXPLR_MMIO_OVERCFG_SHORT_BACK_OFF_TIMER_LEN = 4 ; + +static const uint8_t EXPLR_MMIO_OVPD_DATA = 0 ; +static const uint8_t EXPLR_MMIO_OVPD_DATA_LEN = 32 ; +static const uint8_t EXPLR_MMIO_OVPD_FLAG = 32 ; +static const uint8_t EXPLR_MMIO_OVPD_ADDRESS = 33 ; +static const uint8_t EXPLR_MMIO_OVPD_ADDRESS_LEN = 15 ; +static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER = 48 ; +static const uint8_t EXPLR_MMIO_OVPD_NEXT_POINTER_LEN = 8 ; +static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID = 56 ; +static const uint8_t EXPLR_MMIO_OVPD_CAPABILITY_ID_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_OWWID10_ID = 0 ; +static const uint8_t EXPLR_MMIO_OWWID10_ID_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_OWWID32_ID = 0 ; +static const uint8_t EXPLR_MMIO_OWWID32_ID_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA = 0 ; +static const uint8_t EXPLR_MMIO_SCOMEWD_WDATA_LEN = 64 ; + +static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_ACTSCOUNT_LEN = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_ACTPWRUP_POWERUPSCOUNT_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_SNSC_D0THERM_PRESENTBIT = 45 ; +static const uint8_t EXPLR_MMIO_SNSC_D0THERM_VALIDBIT = 46 ; +static const uint8_t EXPLR_MMIO_SNSC_D0THERM_ERRORBIT = 47 ; +static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA = 48 ; +static const uint8_t EXPLR_MMIO_SNSC_D0THERM_THERMALDATA_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_SNSC_D1THERM_PRESENTBIT = 45 ; +static const uint8_t EXPLR_MMIO_SNSC_D1THERM_VALIDBIT = 46 ; +static const uint8_t EXPLR_MMIO_SNSC_D1THERM_ERRORBIT = 47 ; +static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA = 48 ; +static const uint8_t EXPLR_MMIO_SNSC_D1THERM_THERMALDATA_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_FRAMECOUNT_LEN = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_FRAMESR_SELFREFRESHCOUNT_LEN = 8 ; + +static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMBASECOUNT_LEN = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOBASELOW_HISTOGRAMLOWCOUNT_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMMEDCOUNT_LEN = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_HISTOMEDHIGH_HISTOGRAMHIGHCOUNT_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_PRESENTBIT = 45 ; +static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_VALIDBIT = 46 ; +static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_ERRORBIT = 47 ; +static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA = 48 ; +static const uint8_t EXPLR_MMIO_SNSC_OCTHERM_THERMALDATA_LEN = 16 ; + +static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_RDWR_READSCOUNT_LEN = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT = 32 ; +static const uint8_t EXPLR_MMIO_SNSC_RDWR_WRITESCOUNT_LEN = 32 ; + +static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER = 0 ; +static const uint8_t EXPLR_MMIO_SNSC_STATEREG_STREGISTER_LEN = 22 ; + +static const uint8_t EXPLR_RDF_AACR_ADDRESS = 0 ; +static const uint8_t EXPLR_RDF_AACR_ADDRESS_LEN = 7 ; +static const uint8_t EXPLR_RDF_AACR_AUTOINC = 7 ; + +static const uint8_t EXPLR_RDF_AADR_DATA = 0 ; +static const uint8_t EXPLR_RDF_AADR_DATA_LEN = 64 ; + +static const uint8_t EXPLR_RDF_AAER_DATA = 0 ; +static const uint8_t EXPLR_RDF_AAER_DATA_LEN = 8 ; + +static const uint8_t EXPLR_RDF_ACTION0_FIR = 0 ; +static const uint8_t EXPLR_RDF_ACTION0_FIR_LEN = 64 ; + +static const uint8_t EXPLR_RDF_ACTION1_FIR = 0 ; +static const uint8_t EXPLR_RDF_ACTION1_FIR_LEN = 64 ; + +static const uint8_t EXPLR_RDF_CERR0_MSR_PE = 12 ; +static const uint8_t EXPLR_RDF_CERR0_EICR_PE = 13 ; +static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE = 16 ; +static const uint8_t EXPLR_RDF_CERR0_HWMSX_PE_LEN = 8 ; +static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE = 24 ; +static const uint8_t EXPLR_RDF_CERR0_FWMSX_PE_LEN = 8 ; +static const uint8_t EXPLR_RDF_CERR0_RSPAR_PE = 32 ; +static const uint8_t EXPLR_RDF_CERR0_AACR_PE = 41 ; +static const uint8_t EXPLR_RDF_CERR0_RECR_PE = 45 ; +static const uint8_t EXPLR_RDF_CERR0_DBGR_PE = 46 ; +static const uint8_t EXPLR_RDF_CERR0_MASK0_PE = 48 ; +static const uint8_t EXPLR_RDF_CERR0_MASK1_PE = 49 ; +static const uint8_t EXPLR_RDF_CERR0_CGDR_PE = 50 ; +static const uint8_t EXPLR_RDF_CERR0_MCBCM_PE = 52 ; +static const uint8_t EXPLR_RDF_CERR0_MCBCM2_PE = 53 ; + +static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_AF_PERR = 0 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_TCHN_PERR = 1 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_CTL_CMPMODE_ERR = 2 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_PCX_PERR = 3 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYND_PERR = 4 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_2SYM_PERR = 5 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CPLX_PERR = 6 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EP2_PERR = 7 ; +static const uint8_t EXPLR_RDF_CERR1_READ_ECC_DATAPATH_PARITY_ERROR = 8 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_CMX_PERR = 9 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP1_PERR = 10 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_VP2_PERR = 11 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_SYG_PERR = 12 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_EF1_PERR = 13 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_MK3_PERR = 14 ; +static const uint8_t EXPLR_RDF_CERR1_ECC_PIPE_E1A_PERR = 15 ; +static const uint8_t EXPLR_RDF_CERR1_UNEXPECTED_RDDATA_VALID = 16 ; +static const uint8_t EXPLR_RDF_CERR1_MISSING_RDDATA_VALID = 17 ; +static const uint8_t EXPLR_RDF_CERR1_SUE_01_DETECT = 18 ; +static const uint8_t EXPLR_RDF_CERR1_SUE_10_DETECT = 19 ; +static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW0 = 20 ; +static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW0 = 21 ; +static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_CE_DW1 = 22 ; +static const uint8_t EXPLR_RDF_CERR1_RBUF_ECC_ERR_UE_DW1 = 23 ; +static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME = 24 ; +static const uint8_t EXPLR_RDF_CERR1_RD_BUFF_ECC_ERR_SYNDROME_LEN = 8 ; + +static const uint8_t EXPLR_RDF_CGDR_CGDIS_PCTL = 0 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_RESP = 1 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_RMW = 2 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_LPTR = 3 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_AHASH = 4 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_STG = 5 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_OUT = 6 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_TLM = 7 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_BD = 8 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_DCMP = 9 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBCTL = 10 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBRMW = 11 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_RBTRC = 12 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_MPE = 13 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_CONF = 14 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_HWMS = 15 ; +static const uint8_t EXPLR_RDF_CGDR_PSDIS_ZERO_SYND = 16 ; +static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_MARKS = 17 ; +static const uint8_t EXPLR_RDF_CGDR_PSDIS_SAME_STEER = 18 ; +static const uint8_t EXPLR_RDF_CGDR_CGDIS_SPARE = 19 ; + +static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER = 0 ; +static const uint8_t EXPLR_RDF_CTCR_MPE_TIMER_LEN = 6 ; +static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE = 6 ; +static const uint8_t EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN = 3 ; +static const uint8_t EXPLR_RDF_CTCR_UE_TIMER = 9 ; +static const uint8_t EXPLR_RDF_CTCR_UE_TIMER_LEN = 6 ; +static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE = 15 ; +static const uint8_t EXPLR_RDF_CTCR_UE_TIMEBASE_LEN = 3 ; +static const uint8_t EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE = 18 ; + +static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT = 0 ; +static const uint8_t EXPLR_RDF_DBGR_PRIMARY_SELECT_LEN = 4 ; +static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT = 4 ; +static const uint8_t EXPLR_RDF_DBGR_SECONDARY_SELECT_LEN = 4 ; +static const uint8_t EXPLR_RDF_DBGR_EPX_CHIP = 8 ; +static const uint8_t EXPLR_RDF_DBGR_EPX_SYMS = 9 ; +static const uint8_t EXPLR_RDF_DBGR_TRACE_ALWAYS = 10 ; +static const uint8_t EXPLR_RDF_DBGR_WAT_ENABLE = 11 ; +static const uint8_t EXPLR_RDF_DBGR_WAT_ACTION_SELECT = 12 ; +static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE = 13 ; +static const uint8_t EXPLR_RDF_DBGR_WAT_SOURCE_LEN = 2 ; + +static const uint8_t EXPLR_RDF_EICR_ADDRESS = 0 ; +static const uint8_t EXPLR_RDF_EICR_ADDRESS_LEN = 37 ; +static const uint8_t EXPLR_RDF_EICR_RESERVED = 37 ; +static const uint8_t EXPLR_RDF_EICR_PERSIST = 38 ; +static const uint8_t EXPLR_RDF_EICR_PERSIST_LEN = 2 ; +static const uint8_t EXPLR_RDF_EICR_REGION = 40 ; +static const uint8_t EXPLR_RDF_EICR_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_EICR_TYPE = 43 ; +static const uint8_t EXPLR_RDF_EICR_TYPE_LEN = 5 ; +static const uint8_t EXPLR_RDF_EICR_MISC = 48 ; +static const uint8_t EXPLR_RDF_EICR_MISC_LEN = 6 ; + +static const uint8_t EXPLR_RDF_ELPR_LOG_FULL = 0 ; +static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER = 2 ; +static const uint8_t EXPLR_RDF_ELPR_LOG_POINTER_LEN = 6 ; + +static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_RDF_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_PAR = 0 ; +static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_RDF_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7 = 0 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN = 8 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_NCE = 8 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_TCE = 9 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_SCE = 10 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_MCE = 11 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_SUE = 12 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_AUE = 13 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_UE = 14 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_RCD = 15 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_IAUE = 16 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_IUE = 17 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_IRCD = 18 ; +static const uint8_t EXPLR_RDF_FIR_MAINLINE_IMPE = 19 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7 = 20 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MPE_RANK_0_TO_7_LEN = 8 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_NCE = 28 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_TCE = 29 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SCE = 30 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_MCE = 31 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_SUE = 32 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_AUE = 33 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_UE = 34 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_RCD = 35 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IAUE = 36 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IUE = 37 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IRCD = 38 ; +static const uint8_t EXPLR_RDF_FIR_MAINTENANCE_IMPE = 39 ; +static const uint8_t EXPLR_RDF_FIR_RDDATA_VALID_ERROR = 40 ; +static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_STATUS = 41 ; +static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE = 42 ; +static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE = 43 ; +static const uint8_t EXPLR_RDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR = 44 ; +static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW0 = 45 ; +static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_CE_DW1 = 46 ; +static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW0 = 47 ; +static const uint8_t EXPLR_RDF_FIR_ECC_RBUF_UE_DW1 = 48 ; +static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59 = 49 ; +static const uint8_t EXPLR_RDF_FIR_RESERVED_49_59_LEN = 11 ; +static const uint8_t EXPLR_RDF_FIR_SCOM_PARITY_DEBUG_WAT = 60 ; +static const uint8_t EXPLR_RDF_FIR_RESERVED = 61 ; +static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR = 62 ; +static const uint8_t EXPLR_RDF_FIR_INTERNAL_SCOM_ERROR_COPY = 63 ; + +static const uint8_t EXPLR_RDF_FWMS0_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS0_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS0_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS0_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS0_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS0_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS0_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS0_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS1_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS1_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS1_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS1_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS1_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS1_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS1_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS1_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS2_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS2_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS2_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS2_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS2_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS2_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS2_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS2_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS3_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS3_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS3_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS3_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS3_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS3_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS3_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS3_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS4_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS4_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS4_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS4_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS4_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS4_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS4_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS4_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS5_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS5_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS5_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS5_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS5_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS5_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS5_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS5_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS6_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS6_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS6_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS6_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS6_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS6_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS6_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS6_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_FWMS7_MARK = 0 ; +static const uint8_t EXPLR_RDF_FWMS7_MARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_FWMS7_TYPE = 8 ; +static const uint8_t EXPLR_RDF_FWMS7_REGION = 9 ; +static const uint8_t EXPLR_RDF_FWMS7_REGION_LEN = 3 ; +static const uint8_t EXPLR_RDF_FWMS7_ADDRESS = 12 ; +static const uint8_t EXPLR_RDF_FWMS7_ADDRESS_LEN = 11 ; +static const uint8_t EXPLR_RDF_FWMS7_EXIT_1 = 23 ; + +static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS0_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS0_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS0_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS1_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS1_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS1_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS2_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS2_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS2_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS3_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS3_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS3_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS4_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS4_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS4_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS5_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS5_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS5_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS6_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS6_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS6_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK = 0 ; +static const uint8_t EXPLR_RDF_HWMS7_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_HWMS7_CONFIRMED = 8 ; +static const uint8_t EXPLR_RDF_HWMS7_EXIT_1 = 9 ; + +static const uint8_t EXPLR_RDF_MASK_FIR = 0 ; +static const uint8_t EXPLR_RDF_MASK_FIR_LEN = 64 ; + +static const uint8_t EXPLR_RDF_MASK0_MSR_PE = 12 ; +static const uint8_t EXPLR_RDF_MASK0_EICR_PE = 13 ; +static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE = 16 ; +static const uint8_t EXPLR_RDF_MASK0_HWMSX_PE_LEN = 8 ; +static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE = 24 ; +static const uint8_t EXPLR_RDF_MASK0_FWMSX_PE_LEN = 8 ; +static const uint8_t EXPLR_RDF_MASK0_RSPAR_PE = 32 ; +static const uint8_t EXPLR_RDF_MASK0_CTCR_PE = 40 ; +static const uint8_t EXPLR_RDF_MASK0_AACR_PE = 41 ; +static const uint8_t EXPLR_RDF_MASK0_RECR_PE = 45 ; +static const uint8_t EXPLR_RDF_MASK0_DBGR_PE = 46 ; +static const uint8_t EXPLR_RDF_MASK0_MASK0_PE = 48 ; +static const uint8_t EXPLR_RDF_MASK0_MASK1_PE = 49 ; +static const uint8_t EXPLR_RDF_MASK0_CGDR_PE = 50 ; +static const uint8_t EXPLR_RDF_MASK0_MCBCM_PE = 52 ; +static const uint8_t EXPLR_RDF_MASK0_MCBCM2_PE = 53 ; + +static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_AF_PERR = 0 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_TCHN_PERR = 1 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_CTL_CMPMODE_ERR = 2 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_PCX_PERR = 3 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYND_PERR = 4 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_2SYM_PERR = 5 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CPLX_PERR = 6 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EP2_PERR = 7 ; +static const uint8_t EXPLR_RDF_MASK1_READ_ECC_DATAPATH_PARITY_ERROR = 8 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_CMX_PERR = 9 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP1_PERR = 10 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_VP2_PERR = 11 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_SYG_PERR = 12 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_EF1_PERR = 13 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_MK3_PERR = 14 ; +static const uint8_t EXPLR_RDF_MASK1_ECC_PIPE_E1A_PERR = 15 ; +static const uint8_t EXPLR_RDF_MASK1_UNEXPECTED_RDDATA_VALID = 16 ; +static const uint8_t EXPLR_RDF_MASK1_MISSING_RDDATA_VALID = 17 ; +static const uint8_t EXPLR_RDF_MASK1_SUE_01_DETECT = 18 ; +static const uint8_t EXPLR_RDF_MASK1_SUE_10_DETECT = 19 ; + +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK = 0 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_HALF_COMPARE_MASK_LEN = 40 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_MASK_COVERAGE_SELECTOR = 40 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_NONSTOP = 41 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_CE_ENABLE = 42 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_MPE_ENABLE = 43 ; +static const uint8_t EXPLR_RDF_MCBCM_MCBIST_TRAP_UE_ENABLE = 44 ; + +static const uint8_t EXPLR_RDF_MSR_CHIPMARK = 8 ; +static const uint8_t EXPLR_RDF_MSR_CHIPMARK_LEN = 8 ; +static const uint8_t EXPLR_RDF_MSR_RANK = 16 ; +static const uint8_t EXPLR_RDF_MSR_RANK_LEN = 3 ; + +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT = 0 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT = 1 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MARK_STORE_WRITE = 2 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UE_RETRY = 3 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ITAG_METADATA_ENABLE = 4 ; +static const uint8_t EXPLR_RDF_RECR_DISABLE_RCD_CHECK = 5 ; +static const uint8_t EXPLR_RDF_RECR_DISABLE_RDDATA_VALID_CHECK = 6 ; +static const uint8_t EXPLR_RDF_RECR_ENABLE_BAD_DATA_ON_SUE = 7 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_UTC_EXIT_INCREASE = 8 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE = 9 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_EXIT_OVERRIDE_LEN = 2 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_HWMARK_EXIT1 = 11 ; +static const uint8_t EXPLR_RDF_RECR_DISABLE_EXIT_0_DELAY_0 = 12 ; +static const uint8_t EXPLR_RDF_RECR_DISABLE_MPE_CORRECTION = 13 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_ENABLE = 14 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_ENABLE = 15 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT = 16 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_BYPASS_BIT_SELECT_LEN = 4 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT = 20 ; +static const uint8_t EXPLR_RDF_RECR_CAPPTAG_RETRY_BIT_SELECT_LEN = 4 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_MPE_NOISE_WINDOW = 24 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_MPE_CONFIRM = 25 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW = 26 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION = 27 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_ENABLE_CHIPMARKED_SCE_NCE = 28 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH = 29 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION = 30 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN = 2 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_DISABLE_PIPE_NOERR_CLOCK_GATING = 32 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE = 33 ; +static const uint8_t EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE = 34 ; +static const uint8_t EXPLR_RDF_RECR_RETRY_UNMARKED_ERRORS = 35 ; +static const uint8_t EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS = 40 ; +static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT = 41 ; +static const uint8_t EXPLR_RDF_RECR_HWMS_RANK_SELECT_LEN = 6 ; + +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT = 0 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_LEFT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R0_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT = 10 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_LEFT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT = 15 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R1_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT = 20 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_LEFT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT = 25 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R2_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT = 30 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_LEFT_LEN = 5 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT = 35 ; +static const uint8_t EXPLR_RDF_RSPAR_CFG_STEERING_R3_RIGHT_LEN = 5 ; + +static const uint8_t EXPLR_RDF_WOF_FIR = 0 ; +static const uint8_t EXPLR_RDF_WOF_FIR_LEN = 64 ; + +static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_SRQ_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_PAR = 0 ; +static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_SRQ_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT = 1 ; static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_TIMEBASE_SELECT_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_PER_BANK_REFRESH = 3 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_4 = 4 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD = 5 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL = 8 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL = 19 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC = 30 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_LEN = 10 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK = 40 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK_LEN = 10 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL = 50 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF = 61 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63 = 62 ; -static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63_LEN = 2 ; - -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY = 0 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT = 4 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 6 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_HP_WR_GATE_LP_REF_DIS = 7 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9 = 8 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY = 10 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB = 16 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB_LEN = 13 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31 = 29 ; -static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31_LEN = 3 ; - -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_CTRL_ENABLE = 0 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_DATA_ENABLE = 1 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE = 2 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS = 3 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL = 6 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP = 11 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN = 16 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_QUAD_RANK_ENC = 21 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 22 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME = 23 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 10 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 33 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 34 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 8 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_LP_DATA_DISABLE = 42 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 43 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN = 44 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING = 47 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME = 48 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP = 49 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP = 54 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_CCS_STR_EN = 59 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_STR_ENABLE = 0 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_DIS_CLK_IN_STR = 1 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME = 2 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME_LEN = 10 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR = 12 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE = 17 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX = 22 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL = 27 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS = 38 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN = 8 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL = 46 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL = 57 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL = 61 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_FORCE_STR = 62 ; -static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_EPOW_DISABLE = 63 ; - -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE = 0 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0 = 1 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1 = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2 = 7 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3 = 10 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4 = 13 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5 = 16 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6 = 19 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7 = 22 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP0_FLIP = 25 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP1_FLIP = 26 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP2_FLIP = 27 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP3_FLIP = 28 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP4_FLIP = 29 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP5_FLIP = 30 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP6_FLIP = 31 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP7_FLIP = 32 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47 = 33 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47_LEN = 15 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT = 48 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT = 52 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT = 56 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63 = 60 ; -static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP = 0 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS = 8 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG = 12 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG = 16 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL = 20 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR = 24 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP = 28 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC = 32 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE = 36 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43 = 40 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT = 44 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD = 48 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR = 52 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH = 56 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY = 60 ; -static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY = 0 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY = 12 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY = 18 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY = 24 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY = 30 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY = 36 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY = 42 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY = 47 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY = 52 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY = 57 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_RESERVED_62_63 = 62 ; -static const uint8_t EXPLR_SRQ_MBA_DSM0Q_RESERVED_62_63_LEN = 2 ; - -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PCFSM_1HOT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_STRFSM_1HOT = 1 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_RECVFSM_1HOT = 2 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PE = 3 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_PE = 4 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_PE = 5 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_PE = 6 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_TMR_PE = 7 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_PE = 8 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_HANG = 9 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_HANG = 10 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT = 11 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT = 12 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE = 13 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD = 15 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR = 17 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR = 22 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR_LEN = 15 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR = 37 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR = 42 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE = 53 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK = 0 ; -static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK_LEN = 57 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_BLOCK = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_BLOCK_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_2N_ADDR = 17 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DDP_ADDR_MODE = 18 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PLANAR_ADDR_MODE = 19 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME = 20 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW = 24 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN = 7 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW = 31 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN = 7 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_AFTER_CMD = 38 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_WEN = 39 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 = 40 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE = 41 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_DETECT_TIME = 43 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_DETECT_TIME_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME = 48 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY = 54 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_WAIT_FOR_INIT_COMPLETE = 55 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES = 56 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE = 57 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_58 = 58 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT = 59 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD = 60 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE = 61 ; -static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN = 3 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID = 6 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID = 9 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID = 12 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID = 15 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID = 18 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID = 21 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID = 24 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID = 27 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID = 30 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID = 33 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID = 36 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID = 39 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID = 42 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID = 45 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DIS_SMDR = 48 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS = 49 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_READ_2CYC_PREAMBLE_EN = 50 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRITE_2CYC_PREAMBLE_EN = 51 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY = 52 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY = 55 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RSV0 = 58 ; -static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RSV0_LEN = 6 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT = 8 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT = 12 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT = 20 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT = 24 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT = 28 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT = 32 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT = 36 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT = 40 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT = 44 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT = 48 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT = 52 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT = 56 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT = 60 ; -static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN = 15 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT = 15 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M = 31 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M_LEN = 14 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT = 45 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT = 48 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_51 = 51 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_52 = 52 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC = 53 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63 = 54 ; -static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63_LEN = 10 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW = 22 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26 = 23 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N = 27 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N_LEN = 15 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M = 42 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M_LEN = 14 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63 = 56 ; -static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63_LEN = 8 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3 = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL = 5 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE = 6 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15 = 7 ; -static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15_LEN = 9 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE = 11 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_STR_STATE = 15 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH = 16 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH = 21 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY = 26 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_EVENT = 31 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB7Q_EMER_THROTTLE_IP = 0 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB8Q_SAFE_REFRESH_MODE = 0 ; - -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE = 0 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB = 1 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL = 3 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_LEN = 9 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_12 = 12 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH = 13 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_LEN = 8 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB = 21 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_31 = 23 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_31_LEN = 9 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_ENABLE = 32 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB = 33 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL = 35 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_LEN = 9 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_FIXED_RUN_LENGTH_EN = 44 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH = 45 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH_LEN = 10 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN = 55 ; -static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN_LEN = 9 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT_LEN = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT_LEN = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT_LEN = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT_LEN = 8 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT_LEN = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT_LEN = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER_LEN = 16 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER = 48 ; -static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER_LEN = 16 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT = 12 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT = 18 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0 = 24 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1 = 26 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2 = 28 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3 = 30 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE = 32 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_FREEZE = 35 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_RESET = 36 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_NO_RESET = 37 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_STOP = 38 ; -static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_RESET_PMU6_WHEN_READ = 39 ; - -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE = 0 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK = 6 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK = 9 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG = 12 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK = 14 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE = 17 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN = 19 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN = 20 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN = 21 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN = 22 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK = 23 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK = 26 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG = 29 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK = 31 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE = 34 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN = 36 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN = 37 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN = 38 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN = 39 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK = 40 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK = 43 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG = 46 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_LEN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK = 48 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63 = 51 ; -static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63_LEN = 13 ; - -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT = 0 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE = 6 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE = 7 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10 = 8 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10_LEN = 3 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE = 11 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT = 12 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR = 13 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN = 11 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT = 24 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL = 30 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56 = 34 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56_LEN = 23 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING = 57 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT_FIFO = 61 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE = 62 ; -static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_CRIT_OW_FIRST_EN = 63 ; - -static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN = 0 ; -static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_PC_EN = 1 ; -static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_TIMEBASE_EN = 2 ; -static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7 = 3 ; -static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7_LEN = 5 ; - -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY = 0 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY = 8 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY = 12 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY = 16 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY = 20 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY = 24 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY = 28 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY = 32 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY = 37 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY = 42 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY = 47 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY = 51 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY = 57 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RESERVED_63 = 63 ; - -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY = 0 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW = 10 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD = 16 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP = 21 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS = 26 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_SRQ_TMR_DBG_SEL = 32 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_SRQ_TMR_DBG_SEL_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RESERVED_37_40 = 37 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RESERVED_37_40_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE = 41 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE_LEN = 7 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE = 48 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD = 52 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG = 56 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY = 60 ; -static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS = 0 ; -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN = 20 ; -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS = 20 ; -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 12 ; -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_32_63 = 32 ; -static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_32_63_LEN = 32 ; - -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK = 0 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE = 5 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE = 6 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY = 7 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN = 12 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK = 19 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR = 20 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 21 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 12 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK = 33 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN = 5 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT = 38 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN = 6 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE = 44 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD = 45 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN = 8 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_RRQ_ENTRIES_DIS = 53 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_RESERVED_54 = 54 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING = 55 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ALLOW_NEW_PAGE_COMMIT = 59 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL = 60 ; -static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL_LEN = 4 ; - -static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_CHK_DIS = 0 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_COR_DIS = 1 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK = 2 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK_LEN = 14 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_PAUSE = 16 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CREDIT_UPDATE = 17 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT = 18 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT_LEN = 4 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_TRACE_UPDATE = 22 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_CLEAR = 23 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_HOLD_ACUM = 24 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ0 = 25 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ1 = 26 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_TBD0 = 27 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS = 28 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS_LEN = 3 ; -static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_DRAM_CMD_FLUSH_EN = 31 ; - -static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_RECOVERABLE_ERROR = 0 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_NONRECOVERABLE_ERROR = 1 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_REFRESH_OVERRUN = 2 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WAT_ERROR = 3 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_RCD_PARITY_ERROR = 4 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_LOGIC_ERROR = 5 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_EMERGENCY_THROTTLE = 6 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_PARITY_ERROR = 7 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_DDR_MBA_EVENT_N = 8 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WRQ_RRQ_HANG_ERR = 9 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_SM_1HOT_ERR = 10 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_REG_PARITY_ERROR = 11 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_CMD_PARITY_ERROR = 12 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_PORT_FAIL = 13 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_INFO_REG_PARITY_ERROR = 14 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_DEBUG_PARITY_ERROR = 15 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR0 = 16 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR1 = 17 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR2 = 18 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR3 = 19 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR4 = 20 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR5 = 21 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR6 = 22 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR7 = 23 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_UE = 24 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_TBD_FREE = 25 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_LOGIC_ERROR = 26 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_PARITY_ERROR = 27 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_CORR_ERROR = 28 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR = 29 ; -static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR_COPY = 30 ; - -static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF = 0 ; -static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF_LEN = 31 ; - -static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR = 0 ; -static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR_LEN = 31 ; - -static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR = 0 ; -static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR_LEN = 31 ; - -static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA = 0 ; -static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA_LEN = 31 ; - -static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS_LEN = 24 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME = 24 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME_LEN = 8 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME = 32 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME_LEN = 8 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE = 40 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE = 44 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS = 48 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS_LEN = 4 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE = 52 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE_LEN = 4 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE = 56 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE_LEN = 3 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS = 59 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS_LEN = 2 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD = 61 ; -static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD_LEN = 3 ; - -static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_PAR = 0 ; -static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; - -static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_CLEAR = 0 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE = 1 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE_LEN = 2 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_UPDATE = 3 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_HOLD_ACUM = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_TBD = 5 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_TBD_LEN = 5 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_RETURN_PAUSE = 10 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_CREDIT_UPDATE = 11 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_RETURN_PAUSE = 12 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_CREDIT_UPDATE = 13 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_RETURN_PAUSE = 14 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_CREDIT_UPDATE = 15 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT = 16 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT_LEN = 16 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT = 32 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT_LEN = 16 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT = 48 ; -static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT_LEN = 16 ; - -static const uint8_t EXPLR_TLXT_TLXCFG1_SLOW_CLOCK = 0 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE = 1 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE_LEN = 2 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_OPT_ERR = 3 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_MMIO_BAD = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_DFLOW_ERR = 5 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_BAR0_BAD = 6 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_RESERVED = 7 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO = 8 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI = 12 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL = 16 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL_LEN = 16 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD = 32 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD_LEN = 3 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD = 35 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD_LEN = 3 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_DIS = 38 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_ENAB = 39 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_ENAB_RD_THRESH = 40 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_LOW_LAT_RD_DIS = 41 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_CLK_GATE_DIS = 42 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_ENAB = 43 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_PERSIST = 44 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT0 = 45 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT1 = 46 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TBD = 47 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0 = 48 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1 = 52 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2 = 56 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3 = 60 ; -static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3_LEN = 4 ; - -static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG = 0 ; -static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG_LEN = 24 ; -static const uint8_t EXPLR_TLXT_TLXCFG2_TBD = 24 ; -static const uint8_t EXPLR_TLXT_TLXCFG2_TBD_LEN = 40 ; - -static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0 = 0 ; -static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0_LEN = 30 ; - -static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1 = 0 ; -static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1_LEN = 30 ; - -static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK = 0 ; -static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK_LEN = 30 ; - -static const uint8_t EXPLR_TLXT_TLXFIRQ_INFO_REG_PARITY_ERROR = 0 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_CTRL_REG_PARITY_ERROR = 1 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC0_MAX_CRD_ERROR = 2 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC1_MAX_CRD_ERROR = 3 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP0_MAX_CRD_ERROR = 4 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP1_MAX_CRD_ERROR = 5 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_ERROR = 6 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_PERROR = 7 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_PARITY_ERROR = 8 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_RECOVERABLE_ERROR = 9 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_CONFIG_ERROR = 10 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_INFORMATIONAL_PERROR = 11 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_HARD_ERROR = 12 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10 = 13 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10_LEN = 3 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_SHUTDOWN = 16 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_BAR0_OR_MMIO_NF = 17 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_MALFORMED = 18 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_PROTOCOL_ERROR = 19 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_ADDR_XLAT = 20 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_METADATA_UNC_DPERR = 21 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_UNSUPPORTED = 22 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_FATAL = 23 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_CONTROL_ERROR = 24 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INTERNAL_ERROR = 25 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INFORMATIONAL = 26 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_TRACE_STOP = 27 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR = 28 ; -static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR_CLONE = 29 ; - -static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF = 0 ; -static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF_LEN = 30 ; - -static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG = 0 ; -static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG = 0 ; -static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG = 0 ; -static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG = 0 ; -static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS = 0 ; -static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED_LEN = 5 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_7 = 5 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_SHUTDOWN = 6 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_NF = 7 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_NF = 8 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_OPCODE_COMBO = 9 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_6 = 10 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_CREDIT_RETURN_SLOT = 11 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_0_FORMAT = 12 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RESERVED_FIELD_VALUE = 13 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATA_SEQ_ERR = 14 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RD_BDY_ERR = 15 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_WR_BDY_ERR = 16 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_5 = 17 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_INTRP_RESP_TAG = 18 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_MEMCTL = 19 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_4 = 20 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_3 = 21 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_2 = 22 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDRESS_DROPPED = 23 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_RD = 24 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_WR = 25 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PATTERN_CORRUPT = 26 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_NF = 27 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_UNC = 28 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_RD_DDR = 29 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_RD_MEM = 30 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE = 31 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_LENGTH = 32 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PAD_MEM = 33 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PAD_MEM_LEN_ERR = 34 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE_LENGTH = 35 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_READ_LENGTH = 36 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_OPCODE = 37 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_TEMPLATE = 38 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_DATA_CARRIER = 39 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BUFF_CNTL_PERR = 40 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNC = 41 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAGSTORE_UNC = 42 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_3 = 43 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_1 = 44 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_FLIT_PERR = 45 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_PERR = 46 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_INV = 47 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_PERR = 48 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_INV = 49 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNDERFLOW = 50 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_F = 51 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_OVERFLOW = 52 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_F = 53 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_F = 54 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_1 = 55 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_2 = 56 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLATE_HOLE = 57 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_DATA_RXD = 58 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_CORR = 59 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAG_BUFFER_CORR = 60 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_CORR = 61 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_EPOW_SIGNALLED = 62 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TRACE_STOP = 63 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS_LEN = 37 ; -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS = 37 ; -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS_LEN = 27 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK_LEN = 64 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS_LEN = 8 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS = 8 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS_LEN = 6 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR = 14 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR_LEN = 4 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE = 18 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE_LEN = 14 ; - -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK = 0 ; -static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_PER_BANK_REFRESH = 3 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_4 = 4 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD = 5 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_PRIORITY_THRESHOLD_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL = 8 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_INTERVAL_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL = 19 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_RESET_INTERVAL_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC = 30 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_LEN = 10 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK = 40 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_TSV_STACK_LEN = 10 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL = 50 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_REFR_CHECK_INTERVAL_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_CFG_TRFC_STACK_GATE_ALL_REF = 61 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63 = 62 ; +static const uint8_t EXPLR_SRQ_MBAREF0Q_RESERVED_62_63_LEN = 2 ; + +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY = 0 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_STATIC_IDLE_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT = 4 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_LP_SUB_CNT_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REFRESH_HP_RANK_BLOCK_ENABLE = 6 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_HP_WR_GATE_LP_REF_DIS = 7 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9 = 8 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_8_9_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY = 10 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_REF_BLOCK_STOP_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB = 16 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_CFG_TSTAB_LEN = 13 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31 = 29 ; +static const uint8_t EXPLR_SRQ_MBAREFAQ_RESERVED_29_31_LEN = 3 ; + +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_CTRL_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_LP_DATA_ENABLE = 1 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE = 2 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS = 3 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL = 6 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AVAIL_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP = 11 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PDN_PUP_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN = 16 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_PDN_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_QUAD_RANK_ENC = 21 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE = 22 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME = 23 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_TIME_LEN = 10 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_ENABLE = 33 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME = 34 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_AFTER_ACTIVATE_WAIT_TIME_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_LP_DATA_DISABLE = 42 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_CNT_REFR_INT = 43 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN = 44 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_EMER_MIN_MAX_DOMAIN_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_PUP_ALL_WRITES_PENDING = 47 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_ALWAYS_WAIT_ACT_TIME = 48 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP = 49 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_RESP_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP = 54 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_TLP_WAKEUP_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_CFG_CONC_CCS_STR_EN = 59 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_SRQ_MBARPC0Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_STR_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_DIS_CLK_IN_STR = 1 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME = 2 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_ENTER_STR_TIME_LEN = 10 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR = 12 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKESR_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE = 17 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRE_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX = 22 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TCKSRX_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL = 27 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TXSDLL_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS = 38 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_TRFC_COUNTER_DIS_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL = 46 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_SAFE_REFRESH_INTERVAL_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL = 57 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TIMER_SEL_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_OCC_DEADMAN_TB_SEL = 61 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_FORCE_STR = 62 ; +static const uint8_t EXPLR_SRQ_MBASTR0Q_CFG_EPOW_DISABLE = 63 ; + +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0 = 1 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL0_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1 = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL1_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2 = 7 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL2_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3 = 10 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL3_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4 = 13 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL4_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5 = 16 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL5_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6 = 19 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL6_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7 = 22 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SEL7_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP0_FLIP = 25 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP1_FLIP = 26 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP2_FLIP = 27 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP3_FLIP = 28 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP4_FLIP = 29 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP5_FLIP = 30 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP6_FLIP = 31 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_DBG_SRQ_SETUP7_FLIP = 32 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47 = 33 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_33_47_LEN = 15 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT = 48 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_RRQ_GT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT = 52 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_WRQ_GT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT = 56 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_CFG_WAT_FARB_REF_GT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63 = 60 ; +static const uint8_t EXPLR_SRQ_MBA_DBG0Q_RESERVED_60_63_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP = 0 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_WR_ENTRY0_HP_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FORCE_RD_ENTRY0_HP_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS = 8 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_FP_DIS_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG = 12 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_RD_PG_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG = 16 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_DIS_WR_PG_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL = 20 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_PUP_ALL_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR = 24 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EXIT_STR_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP = 28 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_HP_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC = 32 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SYNC_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE = 36 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_REF_SAFE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43 = 40 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_RESERVED_40_43_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT = 44 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_MCBIST_GT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD = 48 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_NCF_RM_INVALID_CMD_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR = 52 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_SET_FIR_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH = 56 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_EMER_TH_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY = 60 ; +static const uint8_t EXPLR_SRQ_MBA_DBG1Q_CFG_WAT_START_RECOVERY_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY = 0 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_START_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RODT_END_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY = 12 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_START_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY = 18 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WODT_END_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY = 24 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY = 30 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY = 36 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY = 42 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDCSLAT_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY = 47 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDDATA_EN_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY = 52 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRCSLAT_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY = 57 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_WRDATA_EN_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_MSB = 62 ; +static const uint8_t EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_MSB_LEN = 2 ; + +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PCFSM_1HOT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_STRFSM_1HOT = 1 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_RECVFSM_1HOT = 2 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_PC_PE = 3 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_PE = 4 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_PE = 5 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_PE = 6 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_TMR_PE = 7 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_PE = 8 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_WRQ_HANG = 9 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_RRQ_HANG = 10 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_FARB_CMD_PE_HOLD_OUT = 11 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_DSM_CMD_PE_HOLD_OUT = 12 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE = 13 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_UE_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD = 15 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_TBD_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR = 17 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_LOGIC_ERROR_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR = 22 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_LOGIC_ERROR_LEN = 15 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR = 37 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_MCB_PARITY_ERROR_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR = 42 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_PARITY_ERROR_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE = 53 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_NCF_CE_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK = 0 ; +static const uint8_t EXPLR_SRQ_MBA_ERR_REPORTQ_MASK_ERRMASK_LEN = 57 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_CID2_AS_PAR_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_QUAD_RANK_ENC_4DATA_CSN_ENABLE = 1 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_2_15 = 2 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_2_15_LEN = 14 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INIT_START = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_2N_ADDR = 17 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DDP_ADDR_MODE = 18 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PLANAR_ADDR_MODE = 19 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME = 20 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_ACT_SAME_RANK_HOLD_TIME_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW = 24 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_READS_IN_A_ROW_LEN = 7 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW = 31 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_MAX_WRITES_IN_A_ROW_LEN = 7 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PARITY_AFTER_CMD = 38 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_HYNIX_MDS_MODE = 39 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_ADDR5 = 40 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE = 41 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_43_47 = 43 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_RESERVED_43_47_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME = 48 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_RCD_PROTECTION_TIME_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY = 54 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_WAIT_FOR_INIT_COMPLETE = 55 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FARB_CLOSE_ALL_PAGES = 56 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE = 57 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_DBG_HALF_DIMM = 58 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_INJECT_PARITY_ERR_CONSTANT = 59 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_FINISH_WR_BEFORE_RD = 60 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE = 61 ; +static const uint8_t EXPLR_SRQ_MBA_FARB0Q_CFG_OPT_RD_SIZE_LEN = 3 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S0_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S1_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID = 6 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S2_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID = 9 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S3_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID = 12 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S4_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID = 15 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S5_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID = 18 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S6_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID = 21 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT0_S7_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID = 24 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S0_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID = 27 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S1_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID = 30 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S2_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID = 33 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S3_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID = 36 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S4_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID = 39 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S5_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID = 42 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S6_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID = 45 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_SLOT1_S7_CID_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DIS_SMDR = 48 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_DDR4_PARITY_ON_CID_DIS = 49 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_READ_2CYC_PREAMBLE_EN = 50 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRITE_2CYC_PREAMBLE_EN = 51 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY = 52 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSGAP_DLY_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY = 55 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_WRCSGAP_DLY_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSLAT_DLY_MSB = 58 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDCSLAT_DLY_MSB_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDDATA_EN_DLY_MSB = 61 ; +static const uint8_t EXPLR_SRQ_MBA_FARB1Q_CFG_RDDATA_EN_DLY_MSB_LEN = 3 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT = 8 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT = 12 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT = 20 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT = 24 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT = 28 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_RD_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT = 32 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK0_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT = 36 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK1_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT = 40 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK2_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT = 44 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK3_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT = 48 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK4_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT = 52 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK5_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT = 56 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK6_WR_ODT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT = 60 ; +static const uint8_t EXPLR_SRQ_MBA_FARB2Q_CFG_RANK7_WR_ODT_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN = 15 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT = 15 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M = 31 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_M_LEN = 14 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT = 45 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_RAS_WEIGHT_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT = 48 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CAS_WEIGHT_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_51 = 51 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_52 = 52 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_CFG_NM_CHANGE_AFTER_SYNC = 53 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63 = 54 ; +static const uint8_t EXPLR_SRQ_MBA_FARB3Q_RESERVED_54_63_LEN = 10 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_NOISE_WAIT_TIME_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_PRECHARGE_WAIT_TIME_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_CFG_SIM_FAST_NOISE_WINDOW = 22 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26 = 23 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_23_26_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N = 27 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_N_LEN = 15 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M = 42 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_EMERGENCY_M_LEN = 14 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63 = 56 ; +static const uint8_t EXPLR_SRQ_MBA_FARB4Q_RESERVED_56_63_LEN = 8 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3 = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_0_3_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL = 5 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE = 6 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15 = 7 ; +static const uint8_t EXPLR_SRQ_MBA_FARB5Q_RESERVED_7_15_LEN = 9 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE = 11 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_CKE_PUP_STATE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_STR_STATE = 15 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH = 16 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RRQ_DEPTH_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH = 21 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_WRQ_DEPTH_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY = 26 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_RCD_PARITY_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_EVENT = 31 ; +static const uint8_t EXPLR_SRQ_MBA_FARB6Q_CFG_INIT_COMPLETE = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB7Q_EMER_THROTTLE_IP = 0 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB8Q_SAFE_REFRESH_MODE = 0 ; + +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE = 0 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB = 1 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_TB_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL = 3 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_INTERVAL_LEN = 9 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_12 = 12 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH = 13 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB = 21 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_RUN_LENGTH_TB_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_28 = 23 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_RESERVED_23_28_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_CTRLUPD_SINGLE_REQ = 29 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_CTRLUPD_AFTER_PHY_INT = 30 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_CTRLUPD_AFTER_ERR = 31 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_ENABLE = 32 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB = 33 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_TB_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL = 35 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_INTERVAL_LEN = 9 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_FIXED_RUN_LENGTH_EN = 44 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH = 45 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_RUN_LENGTH_LEN = 10 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN = 55 ; +static const uint8_t EXPLR_SRQ_MBA_FARB9Q_CFG_MC_PER_CAL_CTRLUPD_MIN_LEN = 9 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU0Q_READ_COUNT_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU0Q_WRITE_COUNT_LEN = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU1Q_ACTIVATE_COUNT_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU1Q_PU_COUNTS_LEN = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU2Q_FRAME_COUNT_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU2Q_STR_EXIT_COUNT_LEN = 8 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_LOW_IDLE_THRESHOLD_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_MED_IDLE_THRESHOLD_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU3Q_HIGH_IDLE_THRESHOLD_LEN = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU4Q_BASE_IDLE_COUNT_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU4Q_LOW_IDLE_COUNT_LEN = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU5Q_MED_IDLE_COUNT_LEN = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU5Q_HIGH_IDLE_COUNT_LEN = 32 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT0_COUNTER_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT1_COUNTER_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT2_COUNTER_LEN = 16 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER = 48 ; +static const uint8_t EXPLR_SRQ_MBA_PMU6Q_EVENT3_COUNTER_LEN = 16 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT0_SELECT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT1_SELECT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT = 12 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT2_SELECT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT = 18 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_EVENT3_SELECT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0 = 24 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C0_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1 = 26 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C1_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2 = 28 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C2_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3 = 30 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PRESCALER_C3_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE = 32 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CASCADE_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_FREEZE = 35 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_RESET = 36 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_START_NO_RESET = 37 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_PMU_STOP = 38 ; +static const uint8_t EXPLR_SRQ_MBA_PMU7Q_CFG_RESET_PMU6_WHEN_READ = 39 ; + +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE = 0 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_TYPE_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_MATCH_EN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_MATCH_EN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_MATCH_EN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_MATCH_EN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK = 6 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_MRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK = 9 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_SRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG = 12 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BG_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK = 14 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD0_BANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE = 17 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_TYPE_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_MATCH_EN = 19 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_MATCH_EN = 20 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_MATCH_EN = 21 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_MATCH_EN = 22 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK = 23 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_MRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK = 26 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_SRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG = 29 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BG_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK = 31 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD1_BANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE = 34 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_TYPE_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_MATCH_EN = 36 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_MATCH_EN = 37 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_MATCH_EN = 38 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_MATCH_EN = 39 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK = 40 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_MRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK = 43 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_SRANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG = 46 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BG_LEN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK = 48 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_CFG_CMD2_BANK_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63 = 51 ; +static const uint8_t EXPLR_SRQ_MBA_PMU8Q_RESERVED_51_63_LEN = 13 ; + +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT = 0 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SKIP_LIMIT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_FIFO_MODE = 6 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_SINGLE_THREAD_MODE = 7 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10 = 8 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_8_10_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_RD_PG_MODE = 11 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT = 12 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR = 13 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RD_IDLE_ALLOW_WR_LEN = 11 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT = 24 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RDBUFF_CAPACITY_LIMIT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL = 30 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_SRQ_RRQ_DBG_SEL_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56 = 34 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_RESERVED_34_56_LEN = 23 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING = 57 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ACT_NUM_READS_PENDING_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_DISABLE_FAST_ACT_FIFO = 61 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_RRQ_ENTRY0_ENABLE = 62 ; +static const uint8_t EXPLR_SRQ_MBA_RRQ0Q_CFG_CRIT_OW_FIRST_EN = 63 ; + +static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN = 0 ; +static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_PC_EN = 1 ; +static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_TIMEBASE_EN = 2 ; +static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7 = 3 ; +static const uint8_t EXPLR_SRQ_MBA_SYNCCNTLQ_RESERVED_3_7_LEN = 5 ; + +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY = 0 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRDM_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMSR_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY = 8 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RRSMDR_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY = 12 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RROP_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY = 16 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWDM_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY = 20 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMSR_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY = 24 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWSMDR_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY = 28 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WWOP_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY = 32 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWDM_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY = 37 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMSR_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY = 42 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RWSMDR_DLY_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY = 47 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRDM_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY = 51 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMSR_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY = 57 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_WRSMDR_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR0Q_RESERVED_63 = 63 ; + +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY = 0 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RRSBG_DLY_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_WRSBG_DLY_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW = 10 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TFAW_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD = 16 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP = 21 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS = 26 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRAS_MSB = 32 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRCD_MSB = 33 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_TRP_MSB = 34 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE_MSB = 35 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE_MSB_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE_MSB = 39 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_RESERVED_40 = 40 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE = 41 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_WR2PRE_LEN = 7 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE = 48 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_RD2PRE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD = 52 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG = 56 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_TRRD_SBG_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY = 60 ; +static const uint8_t EXPLR_SRQ_MBA_TMR1Q_CFG_ACT_TO_DIFF_RANK_DLY_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS = 0 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_FSM_DIS_LEN = 20 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS = 20 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_BANK_BUSY_OPEN_PAGE_DIS_LEN = 12 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_SRQ_TMR_DBG_SEL = 32 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_SRQ_TMR_DBG_SEL_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_37_39 = 37 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_37_39_LEN = 3 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_READ_WRITE_SWITCH_DLY = 40 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_READ_WRITE_SWITCH_DLY_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_WRITE_READ_SWITCH_DLY = 48 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_CFG_WRITE_READ_SWITCH_DLY_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_REFRESH_RESET_RANK = 56 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_REFRESH_RESET_RANK_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_62_63 = 62 ; +static const uint8_t EXPLR_SRQ_MBA_TMR2Q_RESERVED_62_63_LEN = 2 ; + +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK = 0 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_HW_MARK_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FIFO_MODE = 5 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_DISABLE_WR_PG_MODE = 6 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY = 7 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENTRY0_HP_DLY_LEN = 12 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_FLUSH_WR_RANK = 19 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ENABLE_NON_HP_WR = 20 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR = 21 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_ENTRY0_MIN_FOR_RRQ_IDLE_WR_LEN = 12 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK = 33 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRITE_LW_MARK_LEN = 5 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT = 38 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_LIMIT_LEN = 6 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SINGLE_THREAD_MODE = 44 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD = 45 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_RQ_HANG_THRESHOLD_LEN = 8 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_SKIP_RRQ_ENTRIES_DIS = 53 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_RESERVED_54 = 54 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING = 55 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ACT_NUM_WRITES_PENDING_LEN = 4 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_WRQ_ALLOW_NEW_PAGE_COMMIT = 59 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL = 60 ; +static const uint8_t EXPLR_SRQ_MBA_WRQ0Q_CFG_SRQ_WRQ_DBG_SEL_LEN = 4 ; + +static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_CHK_DIS = 0 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_MODE_ECC_COR_DIS = 1 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK = 2 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_RMW_RBUF_PTR_MASK_LEN = 14 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_PAUSE = 16 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CREDIT_UPDATE = 17 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT = 18 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_MCB_CRD_INIT_LEN = 4 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_TRACE_UPDATE = 22 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_CLEAR = 23 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_HOLD_ACUM = 24 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ0 = 25 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_ERR_INJ1 = 26 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_TBD0 = 27 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS = 28 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_CGT_DIS_LEN = 3 ; +static const uint8_t EXPLR_SRQ_SRQCFG0_NCF_DRAM_CMD_FLUSH_EN = 31 ; + +static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_RECOVERABLE_ERROR = 0 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_MBA_NONRECOVERABLE_ERROR = 1 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_REFRESH_OVERRUN = 2 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WAT_ERROR = 3 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_RCD_PARITY_ERROR = 4 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_LOGIC_ERROR = 5 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_EMERGENCY_THROTTLE = 6 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_MCB_PARITY_ERROR = 7 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_DDR_MBA_EVENT_N = 8 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WRQ_RRQ_HANG_ERR = 9 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_SM_1HOT_ERR = 10 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_REG_PARITY_ERROR = 11 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_CMD_PARITY_ERROR = 12 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_PORT_FAIL = 13 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_INFO_REG_PARITY_ERROR = 14 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_DEBUG_PARITY_ERROR = 15 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR0 = 16 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR1 = 17 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR2 = 18 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR3 = 19 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR4 = 20 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR5 = 21 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR6 = 22 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_WDF_ERROR7 = 23 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_UE = 24 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_TBD_FREE = 25 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_LOGIC_ERROR = 26 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_PARITY_ERROR = 27 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_NCF_CORR_ERROR = 28 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR = 29 ; +static const uint8_t EXPLR_SRQ_SRQFIRQ_INTERNAL_SCOM_ERROR_COPY = 30 ; + +static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF = 0 ; +static const uint8_t EXPLR_SRQ_SRQFIRWOF_FIR_WOF_LEN = 31 ; + +static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR = 0 ; +static const uint8_t EXPLR_SRQ_SRQFIR_ACTION0_FIR_LEN = 31 ; + +static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR = 0 ; +static const uint8_t EXPLR_SRQ_SRQFIR_ACTION1_FIR_LEN = 31 ; + +static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA = 0 ; +static const uint8_t EXPLR_SRQ_SRQFIR_MASK_MBA_LEN = 31 ; + +static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_SRQ_SRQTRAP0_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_DEBUG_BUS_LEN = 24 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME = 24 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_SYNDROME_LEN = 8 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME = 32 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_SYNDROME_LEN = 8 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE = 40 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_INVALID_CMD_CODE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE = 44 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_INVALID_CMD_CODE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS = 48 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_CREDITS_LEN = 4 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE = 52 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_NCF_FSM_ENCODE_LEN = 4 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE = 56 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_REFBLK_FSM_ENCODE_LEN = 3 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS = 59 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_MCB_STATUS_LEN = 2 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD = 61 ; +static const uint8_t EXPLR_SRQ_SRQTRAP1_TBD_LEN = 3 ; + +static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_TLXT_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_PAR = 0 ; +static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_TLXT_ERR_MASK_LAT_FIR_ACTION1_PAR = 2 ; + +static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_CLEAR = 0 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE = 1 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_EARLY_WDONE_DISABLE_LEN = 2 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_TRAP_UPDATE = 3 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_HOLD_ACUM = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_TBD = 5 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_TBD_LEN = 5 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_RETURN_PAUSE = 10 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_CREDIT_UPDATE = 11 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_RETURN_PAUSE = 12 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_CREDIT_UPDATE = 13 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_RETURN_PAUSE = 14 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_CREDIT_UPDATE = 15 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT = 16 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_DCP1_INIT_LEN = 16 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT = 32 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC0_INIT_LEN = 16 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT = 48 ; +static const uint8_t EXPLR_TLXT_TLXCFG0_VC1_INIT_LEN = 16 ; + +static const uint8_t EXPLR_TLXT_TLXCFG1_SLOW_CLOCK = 0 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE = 1 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_MODE_LEN = 2 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_OPT_ERR = 3 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_MMIO_BAD = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_DFLOW_ERR = 5 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_SHUTDOWN_ON_BAR0_BAD = 6 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_IGNORE_A4_ON_PR_RD = 7 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO = 8 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_LO_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI = 12 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXR_DEBSEL_HI_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL = 16 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_DBG_DIAL_LEN = 16 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD = 32 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_THRESHOLD_LEN = 3 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD = 35 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_THRESHOLD_LEN = 3 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_DIS = 38 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_MID_BW_ENAB = 39 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_HI_BW_ENAB_RD_THRESH = 40 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_LOW_LAT_RD_DIS = 41 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_CLK_GATE_DIS = 42 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_ENAB = 43 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_PERSIST = 44 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT0 = 45 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_CFEI_BIT1 = 46 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_LOW_LAT_DEGRADE_DIS = 47 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0 = 48 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_0_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1 = 52 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_1_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2 = 56 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_2_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3 = 60 ; +static const uint8_t EXPLR_TLXT_TLXCFG1_TLXT_INTRP_CMDFLAG_3_LEN = 4 ; + +static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG = 0 ; +static const uint8_t EXPLR_TLXT_TLXCFG2_TLXC_WAT_EN_REG_LEN = 24 ; +static const uint8_t EXPLR_TLXT_TLXCFG2_XSTOP_RD_GATE_DIS = 24 ; +static const uint8_t EXPLR_TLXT_TLXCFG2_TBD = 25 ; +static const uint8_t EXPLR_TLXT_TLXCFG2_TBD_LEN = 39 ; + +static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0 = 0 ; +static const uint8_t EXPLR_TLXT_TLXFIRACT0_FIR_ACTION0_LEN = 30 ; + +static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1 = 0 ; +static const uint8_t EXPLR_TLXT_TLXFIRACT1_FIR_ACTION1_LEN = 30 ; + +static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK = 0 ; +static const uint8_t EXPLR_TLXT_TLXFIRMASK_FIR_MASK_LEN = 30 ; + +static const uint8_t EXPLR_TLXT_TLXFIRQ_INFO_REG_PARITY_ERROR = 0 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_CTRL_REG_PARITY_ERROR = 1 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC0_MAX_CRD_ERROR = 2 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_VC1_MAX_CRD_ERROR = 3 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP0_MAX_CRD_ERROR = 4 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLX_DCP3_MAX_CRD_ERROR = 5 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_ERROR = 6 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_CREDIT_MGMT_PERROR = 7 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_PARITY_ERROR = 8 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_RECOVERABLE_ERROR = 9 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_CONFIG_ERROR = 10 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_INFORMATIONAL_PERROR = 11 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXT_HARD_ERROR = 12 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10 = 13 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_RESERVED_10_LEN = 3 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_SHUTDOWN = 16 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_BAR0_OR_MMIO_NF = 17 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_MALFORMED = 18 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_PROTOCOL_ERROR = 19 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_ADDR_XLAT = 20 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_METADATA_UNC_DPERR = 21 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_UNSUPPORTED = 22 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_OC_FATAL = 23 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_CONTROL_ERROR = 24 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INTERNAL_ERROR = 25 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_INFORMATIONAL = 26 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_TLXR_TRACE_STOP = 27 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR = 28 ; +static const uint8_t EXPLR_TLXT_TLXFIRQ_INTERNAL_SCOM_ERROR_CLONE = 29 ; + +static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF = 0 ; +static const uint8_t EXPLR_TLXT_TLXFIRWOF_FIR_WOF_LEN = 30 ; + +static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG = 0 ; +static const uint8_t EXPLR_TLXT_TLXTINTHLD0_TLXT_INTHLD_0_REG_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG = 0 ; +static const uint8_t EXPLR_TLXT_TLXTINTHLD1_TLXT_INTHLD_1_REG_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG = 0 ; +static const uint8_t EXPLR_TLXT_TLXTINTHLD2_TLXT_INTHLD_2_REG_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG = 0 ; +static const uint8_t EXPLR_TLXT_TLXTINTHLD3_TLXT_INTHLD_3_REG_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_TLXT_TLXTRAP0_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_TLXT_TLXTRAP1_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_TLXT_TLXTTRAP2_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_TLXT_TLXTTRAP3_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS = 0 ; +static const uint8_t EXPLR_TLXT_TLXTTRAP4_DEBUG_BUS_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_UNUSED_LEN = 5 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_7 = 5 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TLXR_SHUTDOWN = 6 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_NF = 7 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_NF = 8 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_OPCODE_COMBO = 9 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_6 = 10 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_CREDIT_RETURN_SLOT = 11 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_TEMPLATE_0_FORMAT = 12 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RESERVED_FIELD_VALUE = 13 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATA_SEQ_ERR = 14 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_RD_BDY_ERR = 15 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_WR_BDY_ERR = 16 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_5 = 17 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_INTRP_RESP_TAG = 18 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_MEMCTL = 19 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_4 = 20 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_3 = 21 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_2 = 22 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDRESS_DROPPED = 23 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_RD = 24 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLAT_ERROR_WR = 25 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PATTERN_CORRUPT = 26 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_NF = 27 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_UNC = 28 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_RD_DDR = 29 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_RD_MEM = 30 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE = 31 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PR_LENGTH = 32 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_PAD_MEM = 33 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_PAD_MEM_LEN_ERR = 34 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_WRITE_LENGTH = 35 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_READ_LENGTH = 36 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_OPCODE = 37 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_TEMPLATE = 38 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_UNSUPPORTED_DATA_CARRIER = 39 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BUFF_CNTL_PERR = 40 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNC = 41 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAGSTORE_UNC = 42 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_3 = 43 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SPARE_1 = 44 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_FLIT_PERR = 45 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_PERR = 46 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_WD_INV = 47 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_PERR = 48 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_SRQ_WD_INV = 49 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_UNDERFLOW = 50 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_DATAFLOW_PERR_F = 51 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_OVERFLOW = 52 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MMIO_BAD_WR_RESP_F = 53 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAR0_PERR_F = 54 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_1 = 55 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_B_MGMT_2 = 56 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_ADDR_XLATE_HOLE = 57 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_BAD_DATA_RXD = 58 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_METADATA_CORR = 59 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TAG_BUFFER_CORR = 60 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_D_LIST_CORR = 61 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_EPOW_SIGNALLED = 62 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_TRACE_STOP = 63 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR0_REPORTQ_MASK_ERRMASK_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_PERRORS_LEN = 37 ; +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS = 37 ; +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_TLXT_ERRORS_LEN = 27 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR1_REPORTQ_MASK_ERRMASK_LEN = 64 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_PERRORS_LEN = 8 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS = 8 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_ERRORS_LEN = 6 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR = 14 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTHLD_PERROR_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_DATA_TAKEN_BUT_NOT_VALID = 18 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTRP_REQ_SM_PERRORS = 19 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_INTRP_REQ_SM_PERRORS_LEN = 4 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TL_2SL_4SL_PKT_FULL_PERR = 23 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE = 24 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_TLXC_SPARE_LEN = 8 ; + +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK = 0 ; +static const uint8_t EXPLR_TLXT_TLX_ERR2_REPORTQ_MASK_ERRMASK_LEN = 32 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_RESERVED_LAST_LT = 17 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR = 18 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN = 13 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY = 31 ; @@ -6124,38 +6286,38 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BI static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION = 33 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER = 34 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_A = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_B = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_A = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_B = 24 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_INAROW_MODE = 32 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 = 33 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED = 36 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED = 36 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_INAROW_MODE = 39 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 = 40 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2 = 43 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_UNUSED_2_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET = 46 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EXACT_TO_MODE = 47 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 = 49 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_SLOW_TO_MODE = 50 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_COUNT_LT = 52 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_COUNT_LT = 56 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_SELECT = 60 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN = 3 ; @@ -6168,38 +6330,38 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELE static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_A = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_B = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_A = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_B = 24 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_INAROW_MODE = 32 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 = 33 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 = 34 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 = 35 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED = 36 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED = 36 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_INAROW_MODE = 39 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 = 40 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 = 41 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 = 42 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2 = 43 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_UNUSED_2_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET = 46 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EXACT_TO_MODE = 47 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 = 48 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 = 49 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_SLOW_TO_MODE = 50 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO = 51 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_COUNT_LT = 52 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_COUNT_LT = 56 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_SELECT = 60 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN = 3 ; @@ -6212,24 +6374,24 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELE static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST_LEN = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL_LEN = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN = 24 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_GLB_BRCST_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_SEL_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRIG_SEL_LEN = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION = 9 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_FREEZE_SEL = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS = 17 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_IS_FROZEN_STATUS = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_FREEZE_SEL = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_SYNC_BRCST_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_TRACE_RUN_STATUS_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_IS_FROZEN_STATUS = 19 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST1_CONDITION_HISTORY_STATUS = 20 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST1_CONDITION_HISTORY_STATUS_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST2_CONDITION_HISTORY_STATUS = 23 ; @@ -6241,17 +6403,17 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_MODE_REG_INST4_CONDITION_HISTORY_S static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_IMM_FREEZE = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_STOP_ON_ERR = 17 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH = 18 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_FORCE_TEST = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_ACCUM_HIST = 20 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ = 21 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_COND3_ENABLE = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_COND3_ENABLE = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST3_COND3_ENABLE = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST4_COND3_ENABLE = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE = 6 ; @@ -6268,20 +6430,20 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL = 18 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE = 33 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL = 34 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL = 39 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL = 46 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL = 44 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL = 46 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_ARM_SEL_LEN = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL = 54 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN = 2 ; @@ -6315,23 +6477,23 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_L static const uint8_t EXPLR_TP_MB_UNIT_TOP_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR = 55 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_START = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP = 1 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_MASK_PAR = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_HOLD_LAT_FIR_ACTION1_PAR = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_PAR = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION0_PAR = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION1_PAR = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_PAR = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION0_PAR = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_MASK_FIR_ACTION1_PAR = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_WDATA_PARITY_ERROR = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_WDATA_PARITY_ERROR = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_ADDRESS_PARITY_ERROR = 1 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_DL_RETURN_WDATA_PARITY_ERROR = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_DL_RETURN_P0_ERROR = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_RDATA_PARITY_ERROR = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_P0_ERROR = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_DL_RETURN_P0_ERROR = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_RDATA_PARITY_ERROR = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_UL_P0_ERROR = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PARITY_ERROR_ON_INTERFACE_MACHINE = 6 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PARITY_ERROR_ON_P2S_MACHINE = 7 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ; @@ -6341,26 +6503,26 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_WRITE_NVLD static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_READ_NVLD = 12 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PSCOM_PARALLEL_ADDR_INVALID = 13 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_PCB_COMMAND_PARITY_ERROR = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_GENERAL_TIMEOUT = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_GENERAL_TIMEOUT = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_ERR_RPT_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN10 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN11 = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN12 = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14 = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14_LEN = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN26 = 26 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN9 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN10 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN11 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN12 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN14_LEN = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_FIR_MASK_IN26 = 26 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG_MASK_READ_ADDR_P = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ABORT_ON_ERROR_REG_MASK_WRITE_ADDR_P = 1 ; @@ -6380,8 +6542,15 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_FIRST_PR_ static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_FIRST_PR_WR_DATA_ERR = 11 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SECOND_PR_WR_ADDRESS_ERR = 12 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SECOND_PR_WR_DATA_ERR = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED_LEN = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_FSM = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_SM1_STATE = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_AXI2PCB = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_AXI2PCB_MASK = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_AXI2PCB_TIMER = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON_AXI2PCB_ABORT_ON = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_ERR_ON = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED = 21 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_RESERVED_LEN = 11 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SLAVE_ADDR = 32 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_AXI_PARITY_ERROR_REG_SLAVE_ADDR_LEN = 32 ; @@ -6390,10 +6559,10 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_1 = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_2 = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_RSP_DATA_3 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_TIMEOUT = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_TIMEOUT = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_INT_ADDR_ACCESS = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PIB2GIF = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PCB_ERR_CODE = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PIB2GIF = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PCB_ERR_CODE = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PCB_ERR_CODE_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_READ_ADDR_PARITY = 11 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_ADDR_PARITY = 12 ; @@ -6402,158 +6571,216 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_ static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_15_8 = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_AXI_WRITE_DATA_PARITY_7_0 = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PIB2GIF_PARITY = 17 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_INFO = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_0 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_1 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_2 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_3 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_TIMEOUT = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INT_ADDR_ACCESS = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INVALID_ACCESS = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON_STATE_MACHINE = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON_SM1 = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON = 21 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON_TIMER = 22 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON_ABORT_ON = 23 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_MASK_REG_PARITY_ON_PARITY = 24 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_INFO = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_0 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_1 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_2 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PARITY_RSP_DATA_3 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_TIMEOUT = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INT_ADDR_ACCESS = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_INVALID_ACCESS = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PCB_ERR_CODE_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_READ_ADDR_PARITY = 11 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_ADDR_PARITY = 12 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_31_24 = 13 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_23_16 = 14 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_15_8 = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_AXI_WRITE_DATA_PARITY_7_0 = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PIB2GIF_PARITY = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_ERROR_REG_PIB2GIF_PARITY = 17 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_RESET_REG_RESET_STATEMACHINE = 63 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT = 48 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT_LEN = 16 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_SPARE_LATCH_UNUSED = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT_LEN = 18 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN10 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN10_LEN = 53 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN_LEN = 63 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN_LEN = 63 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN_LEN = 63 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN10 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN11 = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN12 = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN13 = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN14 = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN15 = 15 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN16 = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN17 = 17 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN18 = 18 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN19 = 19 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN20 = 20 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN21 = 21 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN22 = 22 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN_LEN = 22 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN10 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN11 = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN_LEN = 4 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_106 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_MOORTEC_PVT = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_111 = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_112 = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__FAIL_N = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_FATAL = 15 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_NON_FATAL = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_7 = 17 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_6 = 18 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_5 = 19 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_4 = 20 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_3 = 21 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_2 = 22 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_1 = 23 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_0 = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__DDR_EVENTB = 25 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__FATAL = 26 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__NON_FATAL = 27 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__DDR_PHY_IRQ0 = 28 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__FATAL = 29 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__FATAL = 30 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__FATAL = 31 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__FATAL = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__FATAL = 33 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__FATAL = 34 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__FATAL = 35 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__FATAL = 36 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__NON_FATAL = 37 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__NON_FATAL = 38 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__NON_FATAL = 39 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__NON_FATAL = 40 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__NON_FATAL = 41 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__NON_FATAL = 42 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__NON_FATAL = 43 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__NON_FATAL = 44 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__SERDES_INT = 45 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__SERDES_INT = 46 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__SERDES_INT = 47 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__SERDES_INT = 48 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__SERDES_INT = 49 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__SERDES_INT = 50 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__SERDES_INT = 51 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__SERDES_INT = 52 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT = 48 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_GIF2PCB_TIMER_REG_COUNT_LEN = 16 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_SPARE_LATCH_UNUSED = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_HOLD_OUT_REG_OUT_LEN = 18 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN9 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_0 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_1 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_2 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_3 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_4 = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_5 = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_6 = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_7 = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_UNUSED_8 = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_DLL_IRQ = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_PCS_GPBC_IRQ_106 = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MOORTEC_PVT = 21 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_PCS_GPBC_IRQ_111 = 22 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_PCS_GPBC_IRQ_112 = 23 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_TOP_DIGITAL_IO__FAIL_N = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_PROC_SS__TOP_FATAL = 25 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_PROC_SS__TOP_NON_FATAL = 26 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_7 = 27 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_6 = 28 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_5 = 29 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_4 = 30 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_3 = 31 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_2 = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_1 = 33 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_OCMB_DOORBELL_INT_0 = 34 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_TOP_DIGITAL_IO__DDR_EVENTB = 35 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_DDR4_PHY__FATAL = 36 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_DDR4_PHY__NON_FATAL = 37 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_DDR4_PHY__DDR_PHY_IRQ0 = 38 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_7__FATAL = 39 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_6__FATAL = 40 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_5__FATAL = 41 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_4__FATAL = 42 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_3__FATAL = 43 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_2__FATAL = 44 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_1__FATAL = 45 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_0__FATAL = 46 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_7__NON_FATAL = 47 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_6__NON_FATAL = 48 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_5__NON_FATAL = 49 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_4__NON_FATAL = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_3__NON_FATAL = 51 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_2__NON_FATAL = 52 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_1__NON_FATAL = 53 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_0__NON_FATAL = 54 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_7__SERDES_INT = 55 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_6__SERDES_INT = 56 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_5__SERDES_INT = 57 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_4__SERDES_INT = 58 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_3__SERDES_INT = 59 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_2__SERDES_INT = 60 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_1__SERDES_INT = 61 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_FOXHOUND_LANE_0__SERDES_INT = 62 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_IN63 = 63 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION0_IN_LEN = 64 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_ACTION1_IN_LEN = 64 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_FIR_MASK_LFIR_IN_LEN = 64 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN9 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN10 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN11 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN12 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN13 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN14 = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN15 = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN16 = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN17 = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN18 = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN19 = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN20 = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN21 = 21 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_ERR_IN22 = 22 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_LOCAL_XSTOP_MASK_IN_LEN = 22 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN9 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN10 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN11 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MODE_REG_IN_LEN = 4 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_UNUSED_8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DLL_IRQ = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_106 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_MOORTEC_PVT = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_111 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PCS_GPBC_IRQ_112 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__FAIL_N = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_FATAL = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_PROC_SS__TOP_NON_FATAL = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_7 = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_6 = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_5 = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_4 = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_3 = 21 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_2 = 22 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_1 = 23 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_OCMB_DOORBELL_INT_0 = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_TOP_DIGITAL_IO__DDR_EVENTB = 25 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__FATAL = 26 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__NON_FATAL = 27 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_DDR4_PHY__DDR_PHY_IRQ0 = 28 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__FATAL = 29 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__FATAL = 30 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__FATAL = 31 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__FATAL = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__FATAL = 33 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__FATAL = 34 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__FATAL = 35 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__FATAL = 36 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__NON_FATAL = 37 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__NON_FATAL = 38 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__NON_FATAL = 39 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__NON_FATAL = 40 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__NON_FATAL = 41 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__NON_FATAL = 42 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__NON_FATAL = 43 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__NON_FATAL = 44 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_7__SERDES_INT = 45 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_6__SERDES_INT = 46 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_5__SERDES_INT = 47 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_4__SERDES_INT = 48 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_3__SERDES_INT = 49 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_2__SERDES_INT = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_1__SERDES_INT = 51 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_MSG_REG_FOXHOUND_LANE_0__SERDES_INT = 52 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_READ_ADDR_P = 61 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_WRITE_ADDR_P = 62 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ABORT_ON_ERROR_REG_MASK_WRITE_DATA_P = 63 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_ERROR_MASK2_REG = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_ERROR_MASK2_REG_LEN = 64 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_MASK_TP_MSG = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK2_REG_MASK_TP_MSG_LEN = 64 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_0 = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA_1 = 1 ; @@ -6562,65 +6789,83 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_DATA static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_ADDR_0 = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_ADDR_1 = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_REQ_CTRL = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_TIMEOUT = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_TIMEOUT = 7 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_INT_ADDR_ACCESS = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB_LEN = 7 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_0 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_1 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_CTRL = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_TIMEOUT = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_INT_ADDR_ACCESS = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1_LEN = 23 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_LEN = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_ERROR_REG = 46 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_ERROR_REG_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED2 = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_FSM = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG0 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG1 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG2 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG3 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG4 = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_PARITY_ON_REG5 = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_INVALID_ADDRESS = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_MASK_ERROR_REG_UNUSED1 = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_MASK_ERROR_REG_UNUSED1_LEN = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_GIF2PCB_LEN = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_MASK_ERROR_REG_UNUSED2 = 50 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_MASK_REG_MASK_ERROR_REG_UNUSED2_LEN = 14 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_DATA_3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_0 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_ADDR_1 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_REQ_CTRL = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_TIMEOUT = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_INT_ADDR_ACCESS = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_FSM = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG0 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG1 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG2 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG3 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG4 = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_PARITY_ON_REG5 = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_INVALID_ADDRESS = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1 = 17 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED1_LEN = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_GIF2PCB_LEN = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED2 = 50 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG_ERROR_REG_UNUSED2_LEN = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG_LEN = 64 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_ERROR_REG2_TP_MSG_REG_LEN = 64 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT = 48 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT_LEN = 16 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT = 48 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PIB2GIF_TIMER_REG_COUNT_LEN = 16 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_WDATA_PARITY = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY = 1 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_P0 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_DL_RETURN_P0 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_RDATA_PARITY = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_UL_P0 = 5 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE = 6 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE = 7 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN = 9 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH = 10 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD = 12 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_GENERAL_TIMEOUT = 15 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 16 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 17 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_UNUSED_BIT_2 = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_WATCHDOG_ENABLE = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_FORCE_ALL_RINGS = 7 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_MODE_REG_RESERVED_LT_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY = 1 ; @@ -6662,74 +6907,74 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION = 34 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER = 35 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_LFIR_RECOV_ERR = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN4 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN5 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN6 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN7 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN8 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN9 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN10 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN11 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN12 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN13 = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14 = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14_LEN = 12 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_LFIR_RECOV_ERR = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN4 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN5 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN6 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN7 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN8 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN9 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN10 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN11 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN12 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN13 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RFIR_IN14_LEN = 12 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG_ENABLE = 1 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN = 31 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN9 = 9 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN_LEN = 10 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN_LEN = 5 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA_LEN = 64 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA_LEN = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS = 32 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK = 42 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_RUNNING = 53 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPATTN_IN9 = 9 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SPA_MASK_IN_LEN = 10 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_SUM_MASK_REG_SMASK_IN_LEN = 5 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_HI_DATA_REG_DATA_LEN = 64 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_DATA_LEN = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS = 32 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_ADDRESS_LEN = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK = 42 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_LEN = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_LAST_BANK_VALID = 51 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_WRITE_ON_RUN = 52 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_RUNNING = 53 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS = 54 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN = 10 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE = 1 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_BANK_MODE = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_ENH_MODE = 11 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL = 12 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_SELECT_CONTROL = 14 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_SELECT_CONTROL_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_HOLD_OFF = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STATUS = 19 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_RUN_STICKY = 20 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_DISABLE_BANK_EDGE_DETECT = 21 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_TRA_MASTER_CLOCK_ENABLE = 22 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_DISABLE_RD_ACT = 23 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_TRA_MUX_SEL = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 25 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_DISABLE_RD_ACT = 23 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_TRA_MUX_SEL = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED = 25 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRCTRL_CONFIG_CONTROL_UNUSED_LEN = 3 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 = 0 ; @@ -6738,41 +6983,41 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_ static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_3_PATTERND_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKA_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_4_MASKB_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD = 24 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKC_LEN = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD = 24 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_5_MASKD_LEN = 24 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL = 6 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL = 8 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK = 10 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK = 14 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK = 18 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK = 22 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN = 4 ; @@ -6782,174 +7027,172 @@ static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE = static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN = 4 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_CMP_MASK = 32 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_ERROR_CMP_PATTERN = 33 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG0_ERR_CMP = 34 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_TRIG1_ERR_CMP = 35 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES = 36 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_UNIT_TC_TRA_FIR_ERR = 37 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT = 38 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT = 38 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN = 2 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG_RING_LOCKING = 0 ; static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 32 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN0 = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN1 = 1 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN2 = 2 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN3 = 3 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN4 = 4 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN5 = 5 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN6 = 6 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN7 = 7 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN8 = 8 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN9 = 9 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN10 = 10 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN11 = 11 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN12 = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN13 = 13 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14 = 14 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14_LEN = 12 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN26 = 26 ; - -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA = 0 ; -static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA_LEN = 64 ; - -static const uint8_t EXPLR_WDF_AACR_BUFFER = 0 ; -static const uint8_t EXPLR_WDF_AACR_ADDRESS = 1 ; -static const uint8_t EXPLR_WDF_AACR_ADDRESS_LEN = 9 ; -static const uint8_t EXPLR_WDF_AACR_AUTOINC = 10 ; -static const uint8_t EXPLR_WDF_AACR_ECCGEN = 11 ; -static const uint8_t EXPLR_WDF_AACR_PASSTHRU = 12 ; - -static const uint8_t EXPLR_WDF_AADR_DATA = 0 ; -static const uint8_t EXPLR_WDF_AADR_DATA_LEN = 64 ; - -static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE = 0 ; -static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE_LEN = 16 ; - -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE = 0 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE = 11 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE = 22 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE = 33 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE = 44 ; -static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE_LEN = 11 ; - -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE = 0 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE = 11 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE = 22 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE = 33 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE_LEN = 11 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_ODD_RANK_SWIZZLE_EN = 44 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE = 45 ; -static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE_LEN = 11 ; - -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_CHK_DISABLE = 0 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_COR_DISABLE = 1 ; -static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_EN = 2 ; -static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_X8 = 3 ; -static const uint8_t EXPLR_WDF_WECR_CFG_FORCE_DFI_CG_ALWAYS_ON = 4 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_INTEGRITY_CHECK_DISABLE = 5 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_CG_FORCE = 6 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11 = 7 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11_LEN = 5 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL = 12 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL_LEN = 4 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN = 16 ; -static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN_LEN = 4 ; - -static const uint8_t EXPLR_WDF_WERR_DQS0R_PE = 0 ; -static const uint8_t EXPLR_WDF_WERR_DQS1R_PE = 1 ; -static const uint8_t EXPLR_WDF_WERR_AACR_PE = 2 ; -static const uint8_t EXPLR_WDF_WERR_AADR_PE = 3 ; -static const uint8_t EXPLR_WDF_WERR_AAER_PE = 4 ; -static const uint8_t EXPLR_WDF_WERR_WECR_PE = 5 ; -static const uint8_t EXPLR_WDF_WERR_WSPAR_PE = 8 ; -static const uint8_t EXPLR_WDF_WERR_WMSK_PE = 9 ; -static const uint8_t EXPLR_WDF_WERR_RDF_BE_PE = 15 ; -static const uint8_t EXPLR_WDF_WERR_TLXR_WR_PE = 16 ; -static const uint8_t EXPLR_WDF_WERR_TLXR_BAD_PE = 17 ; -static const uint8_t EXPLR_WDF_WERR_TLXR_BE_PE = 18 ; -static const uint8_t EXPLR_WDF_WERR_SRQ_IF_PE = 19 ; -static const uint8_t EXPLR_WDF_WERR_RDF_IF_PE = 20 ; -static const uint8_t EXPLR_WDF_WERR_MMIO_IF_PE = 21 ; -static const uint8_t EXPLR_WDF_WERR_CONTROL_PE = 22 ; -static const uint8_t EXPLR_WDF_WERR_ECCGEN_ERR = 23 ; -static const uint8_t EXPLR_WDF_WERR_WBUF_FUNC_UE = 24 ; -static const uint8_t EXPLR_WDF_WERR_RMWBUF_FUNC_UE = 25 ; -static const uint8_t EXPLR_WDF_WERR_BEBUF_FUNC_UE = 26 ; -static const uint8_t EXPLR_WDF_WERR_BE_PE = 27 ; -static const uint8_t EXPLR_WDF_WERR_INTEGRITY_ERR = 28 ; -static const uint8_t EXPLR_WDF_WERR_WBUF_MMIO_UE = 29 ; -static const uint8_t EXPLR_WDF_WERR_SCOM_FSM_PE = 32 ; -static const uint8_t EXPLR_WDF_WERR_RMWBUF_SCOM_UE = 33 ; -static const uint8_t EXPLR_WDF_WERR_BEBUF_SCOM_UE = 34 ; -static const uint8_t EXPLR_WDF_WERR_WBUF_CE = 48 ; -static const uint8_t EXPLR_WDF_WERR_RMWBUF_CE = 49 ; -static const uint8_t EXPLR_WDF_WERR_BEBUF_CE = 50 ; - -static const uint8_t EXPLR_WDF_WESR_SYNDROME = 0 ; -static const uint8_t EXPLR_WDF_WESR_SYNDROME_LEN = 8 ; -static const uint8_t EXPLR_WDF_WESR_SEVERITY = 8 ; -static const uint8_t EXPLR_WDF_WESR_PART = 9 ; -static const uint8_t EXPLR_WDF_WESR_SOURCE = 10 ; -static const uint8_t EXPLR_WDF_WESR_SOURCE_LEN = 3 ; - -static const uint8_t EXPLR_WDF_WMSK_DQS0R_PE = 0 ; -static const uint8_t EXPLR_WDF_WMSK_DQS1R_PE = 1 ; -static const uint8_t EXPLR_WDF_WMSK_AACR_PE = 2 ; -static const uint8_t EXPLR_WDF_WMSK_AADR_PE = 3 ; -static const uint8_t EXPLR_WDF_WMSK_AAER_PE = 4 ; -static const uint8_t EXPLR_WDF_WMSK_WECR_PE = 5 ; -static const uint8_t EXPLR_WDF_WMSK_WSPAR_PE = 8 ; -static const uint8_t EXPLR_WDF_WMSK_WMSK_PE = 9 ; -static const uint8_t EXPLR_WDF_WMSK_RDF_BE_PE = 15 ; -static const uint8_t EXPLR_WDF_WMSK_TLXR_WR_PE = 16 ; -static const uint8_t EXPLR_WDF_WMSK_TLXR_BAD_PE = 17 ; -static const uint8_t EXPLR_WDF_WMSK_TLXR_BE_PE = 18 ; -static const uint8_t EXPLR_WDF_WMSK_SRQ_IF_PE = 19 ; -static const uint8_t EXPLR_WDF_WMSK_RDF_IF_PE = 20 ; -static const uint8_t EXPLR_WDF_WMSK_MMIO_IF_PE = 21 ; -static const uint8_t EXPLR_WDF_WMSK_CONTROL_PE = 22 ; -static const uint8_t EXPLR_WDF_WMSK_ECCGEN_ERR = 23 ; -static const uint8_t EXPLR_WDF_WMSK_WBUF_FUNC_UE = 24 ; -static const uint8_t EXPLR_WDF_WMSK_RMWBUF_FUNC_UE = 25 ; -static const uint8_t EXPLR_WDF_WMSK_BEBUF_FUNC_UE = 26 ; -static const uint8_t EXPLR_WDF_WMSK_BE_PE = 27 ; -static const uint8_t EXPLR_WDF_WMSK_INTEGRITY_ERR = 28 ; -static const uint8_t EXPLR_WDF_WMSK_WBUF_MMIO_UE = 29 ; -static const uint8_t EXPLR_WDF_WMSK_SCOM_FSM_PE = 32 ; -static const uint8_t EXPLR_WDF_WMSK_RMWBUF_SCOM_UE = 33 ; -static const uint8_t EXPLR_WDF_WMSK_BEBUF_SCOM_UE = 34 ; -static const uint8_t EXPLR_WDF_WMSK_WBUF_CE = 48 ; -static const uint8_t EXPLR_WDF_WMSK_RMWBUF_CE = 49 ; -static const uint8_t EXPLR_WDF_WMSK_BEBUF_CE = 50 ; - -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT = 0 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT = 10 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT = 15 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT = 20 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT = 25 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT = 30 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT_LEN = 5 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT = 35 ; -static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT_LEN = 5 ; - -static const uint8_t EXPLR_EFUSE_IMAGE_OUT_0_ENTERPRISE_MODE_DIS = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_WRITE_PROTECT_RINGS_REG_RINGS_LEN = 32 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN0 = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN1 = 1 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN2 = 2 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN3 = 3 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN4 = 4 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN5 = 5 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN6 = 6 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN7 = 7 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN8 = 8 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN9 = 9 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN10 = 10 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN11 = 11 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN12 = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN13 = 13 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14 = 14 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN14_LEN = 12 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XFIR_IN26 = 26 ; + +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA = 0 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_XTRA_TRACE_MODE_DATA_LEN = 64 ; + +static const uint8_t EXPLR_WDF_AACR_BUFFER = 0 ; +static const uint8_t EXPLR_WDF_AACR_ADDRESS = 1 ; +static const uint8_t EXPLR_WDF_AACR_ADDRESS_LEN = 9 ; +static const uint8_t EXPLR_WDF_AACR_AUTOINC = 10 ; +static const uint8_t EXPLR_WDF_AACR_ECCGEN = 11 ; +static const uint8_t EXPLR_WDF_AACR_PASSTHRU = 12 ; + +static const uint8_t EXPLR_WDF_AADR_DATA = 0 ; +static const uint8_t EXPLR_WDF_AADR_DATA_LEN = 64 ; + +static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE = 0 ; +static const uint8_t EXPLR_WDF_AAER_META_ECC_SPARE_LEN = 16 ; + +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE = 0 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE0_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE = 11 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE1_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE = 22 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE2_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE = 33 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE3_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE = 44 ; +static const uint8_t EXPLR_WDF_DQS0R_CFG_BYTE4_SWIZZLE_LEN = 11 ; + +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE = 0 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE5_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE = 11 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE6_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE = 22 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE7_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE = 33 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE8_SWIZZLE_LEN = 11 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_ODD_RANK_SWIZZLE_EN = 44 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE = 45 ; +static const uint8_t EXPLR_WDF_DQS1R_CFG_BYTE9_SWIZZLE_LEN = 11 ; + +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_CHK_DISABLE = 0 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_ECC_COR_DISABLE = 1 ; +static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_EN = 2 ; +static const uint8_t EXPLR_WDF_WECR_CFG_CRC_MODE_X8 = 3 ; +static const uint8_t EXPLR_WDF_WECR_CFG_FORCE_DFI_CG_ALWAYS_ON = 4 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_INTEGRITY_CHECK_DISABLE = 5 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_CG_FORCE = 6 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11 = 7 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_SPARE7_11_LEN = 5 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL = 12 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_TRACE_SEL_LEN = 4 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN = 16 ; +static const uint8_t EXPLR_WDF_WECR_CFG_WDF_WAT_EN_LEN = 4 ; + +static const uint8_t EXPLR_WDF_WERR_DQS0R_PE = 0 ; +static const uint8_t EXPLR_WDF_WERR_DQS1R_PE = 1 ; +static const uint8_t EXPLR_WDF_WERR_AACR_PE = 2 ; +static const uint8_t EXPLR_WDF_WERR_AADR_PE = 3 ; +static const uint8_t EXPLR_WDF_WERR_AAER_PE = 4 ; +static const uint8_t EXPLR_WDF_WERR_WECR_PE = 5 ; +static const uint8_t EXPLR_WDF_WERR_WSPAR_PE = 8 ; +static const uint8_t EXPLR_WDF_WERR_WMSK_PE = 9 ; +static const uint8_t EXPLR_WDF_WERR_RDF_BE_PE = 15 ; +static const uint8_t EXPLR_WDF_WERR_TLXR_WR_PE = 16 ; +static const uint8_t EXPLR_WDF_WERR_TLXR_BAD_PE = 17 ; +static const uint8_t EXPLR_WDF_WERR_TLXR_BE_PE = 18 ; +static const uint8_t EXPLR_WDF_WERR_SRQ_IF_PE = 19 ; +static const uint8_t EXPLR_WDF_WERR_RDF_IF_PE = 20 ; +static const uint8_t EXPLR_WDF_WERR_MMIO_IF_PE = 21 ; +static const uint8_t EXPLR_WDF_WERR_CONTROL_PE = 22 ; +static const uint8_t EXPLR_WDF_WERR_ECCGEN_ERR = 23 ; +static const uint8_t EXPLR_WDF_WERR_WBUF_FUNC_UE = 24 ; +static const uint8_t EXPLR_WDF_WERR_RMWBUF_FUNC_UE = 25 ; +static const uint8_t EXPLR_WDF_WERR_BEBUF_FUNC_UE = 26 ; +static const uint8_t EXPLR_WDF_WERR_BE_PE = 27 ; +static const uint8_t EXPLR_WDF_WERR_INTEGRITY_ERR = 28 ; +static const uint8_t EXPLR_WDF_WERR_WBUF_MMIO_UE = 29 ; +static const uint8_t EXPLR_WDF_WERR_SCOM_FSM_PE = 32 ; +static const uint8_t EXPLR_WDF_WERR_RMWBUF_SCOM_UE = 33 ; +static const uint8_t EXPLR_WDF_WERR_BEBUF_SCOM_UE = 34 ; +static const uint8_t EXPLR_WDF_WERR_WBUF_CE = 48 ; +static const uint8_t EXPLR_WDF_WERR_RMWBUF_CE = 49 ; +static const uint8_t EXPLR_WDF_WERR_BEBUF_CE = 50 ; + +static const uint8_t EXPLR_WDF_WESR_SYNDROME = 0 ; +static const uint8_t EXPLR_WDF_WESR_SYNDROME_LEN = 8 ; +static const uint8_t EXPLR_WDF_WESR_SEVERITY = 8 ; +static const uint8_t EXPLR_WDF_WESR_PART = 9 ; +static const uint8_t EXPLR_WDF_WESR_SOURCE = 10 ; +static const uint8_t EXPLR_WDF_WESR_SOURCE_LEN = 3 ; + +static const uint8_t EXPLR_WDF_WMSK_DQS0R_PE = 0 ; +static const uint8_t EXPLR_WDF_WMSK_DQS1R_PE = 1 ; +static const uint8_t EXPLR_WDF_WMSK_AACR_PE = 2 ; +static const uint8_t EXPLR_WDF_WMSK_AADR_PE = 3 ; +static const uint8_t EXPLR_WDF_WMSK_AAER_PE = 4 ; +static const uint8_t EXPLR_WDF_WMSK_WECR_PE = 5 ; +static const uint8_t EXPLR_WDF_WMSK_WSPAR_PE = 8 ; +static const uint8_t EXPLR_WDF_WMSK_WMSK_PE = 9 ; +static const uint8_t EXPLR_WDF_WMSK_RDF_BE_PE = 15 ; +static const uint8_t EXPLR_WDF_WMSK_TLXR_WR_PE = 16 ; +static const uint8_t EXPLR_WDF_WMSK_TLXR_BAD_PE = 17 ; +static const uint8_t EXPLR_WDF_WMSK_TLXR_BE_PE = 18 ; +static const uint8_t EXPLR_WDF_WMSK_SRQ_IF_PE = 19 ; +static const uint8_t EXPLR_WDF_WMSK_RDF_IF_PE = 20 ; +static const uint8_t EXPLR_WDF_WMSK_MMIO_IF_PE = 21 ; +static const uint8_t EXPLR_WDF_WMSK_CONTROL_PE = 22 ; +static const uint8_t EXPLR_WDF_WMSK_ECCGEN_ERR = 23 ; +static const uint8_t EXPLR_WDF_WMSK_WBUF_FUNC_UE = 24 ; +static const uint8_t EXPLR_WDF_WMSK_RMWBUF_FUNC_UE = 25 ; +static const uint8_t EXPLR_WDF_WMSK_BEBUF_FUNC_UE = 26 ; +static const uint8_t EXPLR_WDF_WMSK_BE_PE = 27 ; +static const uint8_t EXPLR_WDF_WMSK_INTEGRITY_ERR = 28 ; +static const uint8_t EXPLR_WDF_WMSK_WBUF_MMIO_UE = 29 ; +static const uint8_t EXPLR_WDF_WMSK_SCOM_FSM_PE = 32 ; +static const uint8_t EXPLR_WDF_WMSK_RMWBUF_SCOM_UE = 33 ; +static const uint8_t EXPLR_WDF_WMSK_BEBUF_SCOM_UE = 34 ; +static const uint8_t EXPLR_WDF_WMSK_WBUF_CE = 48 ; +static const uint8_t EXPLR_WDF_WMSK_RMWBUF_CE = 49 ; +static const uint8_t EXPLR_WDF_WMSK_BEBUF_CE = 50 ; + +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT = 0 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_LEFT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R0_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT = 10 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_LEFT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT = 15 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R1_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT = 20 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_LEFT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT = 25 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R2_RIGHT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT = 30 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_LEFT_LEN = 5 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT = 35 ; +static const uint8_t EXPLR_WDF_WSPAR_CFG_STEERING_R3_RIGHT_LEN = 5 ; #endif diff --git a/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H new file mode 100644 index 000000000..fc02d5360 --- /dev/null +++ b/src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef __EXPLR_SCOM_ADDRESSES_FLD_FIXES_H +#define __EXPLR_SCOM_ADDRESSES_FLD_FIXES_H + +static const uint64_t EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1_DOORBELL = 63; +static const uint64_t EXPLR_EFUSE_IMAGE_OUT_0_ENTERPRISE_MODE_DIS = 53; +static const uint64_t EXPLR_SRQ_MBA_PMU8Q_CFG_INIT_COMPLETE = 63; + +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_72 = 0 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_72_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_73 = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_73_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_74 = 16 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_74_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_75 = 24 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_75_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_76 = 32 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_76_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_77 = 40 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_77_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_78 = 48 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_78_LEN = 8 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_79 = 56 ; +static const uint8_t EXPLR_MCBIST_MBSSYMEC9Q_MODAL_SYMBOL_COUNTER_79_LEN = 8 ; +static const uint8_t EXPLR_RDF_MCBCM2_MCBIST_HALF_COMPARE_MASK = 0 ; +static const uint8_t EXPLR_RDF_MCBCM2_MCBIST_HALF_COMPARE_MASK_LEN = 40 ; +static const uint8_t EXPLR_TP_MB_UNIT_TOP_TR1_TRACE_TRCTRL_CONFIG_TRA_MASTER_CLOCK_ENABLE = 22; +static const uint8_t EXP_APBONLY0_MICROCONTMUXSEL_MICROCONTMUXSEL = 63 ; +static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_AC_SELECT = 63 - 8; +static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK = 63 - 5; +static const uint8_t EXP_DDR4_PHY_DDR_PHY_CONTROL_DFI_CFGCMD_AC_MASK_LEN = 2; + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.C new file mode 100644 index 000000000..e451cc669 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.C @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_background_scrub.C +/// @brief Begin background scrub +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <lib/shared/exp_defaults.H> +#include <exp_background_scrub.H> +#include <lib/mcbist/exp_memdiags.H> + +extern "C" +{ + + /// + /// @brief Begin background scrub + /// @param[in] i_target OCMB chip + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_background_scrub(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) + { + FAPI_INF("Start exp background scrub for %s", mss::c_str(i_target)); + FAPI_TRY(mss::memdiags::mss_background_scrub_helper(i_target)); + + fapi_try_exit: + FAPI_INF("End exp background scrub for %s", mss::c_str(i_target)); + return fapi2::current_err; + } + +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.H new file mode 100644 index 000000000..2e95cf6f9 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.H @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_background_scrub.H +/// @brief Procedure declaration to begin background scrub +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_EXP_BACKGROUND_SCRUB__ +#define __MSS_EXP_BACKGROUND_SCRUB__ + +#include <fapi2.H> + +// Required for Cronus +typedef fapi2::ReturnCode (*exp_background_scrub_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ + + /// + /// @brief Begin background scrub + /// @param[in] i_target the controller + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_background_scrub(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +}// extern C +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.mk new file mode 100644 index 000000000..bf8e5f44a --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.mk @@ -0,0 +1,31 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_background_scrub.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# Include the macros and things for MSS EXP procedures +-include 00exp_common.mk + +PROCEDURE=exp_background_scrub +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.C index 28aad7416..880004e23 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.C @@ -22,3 +22,62 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_bulk_pwr_throttles.C +/// @brief The explorer thermal/power config +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: Memory + +#include <lib/shared/exp_defaults.H> +#include <vector> + +#include <fapi2.H> +#include <exp_bulk_pwr_throttles.H> +#include <lib/shared/exp_consts.H> +#include <lib/power_thermal/exp_throttle.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/count_dimm.H> + +extern "C" +{ + /// + /// @brief Set ATTR_EXP_PORT_MAXPOWER, ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_SLOT, ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_PORT + /// @param[in] i_targets vector of OCMB chips + /// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits + /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK + /// @note determines the throttle levels based off of the port's power curve, + /// sets the slot throttles to the same + /// @note Enums are POWER for power egulator throttles and THERMAL for thermal throttles + /// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value + /// + fapi2::ReturnCode exp_bulk_pwr_throttles( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& i_targets, + const mss::throttle_type i_throttle_type) + { + FAPI_INF("Start exp_bulk_pwr_throttles for %s type throttling", + (( i_throttle_type == mss::throttle_type::THERMAL) ? "THERMAL" : "POWER")); + + for ( const auto& l_ocmb : i_targets) + { + FAPI_TRY(mss::power_thermal::pwr_throttles(l_ocmb, i_throttle_type)); + } + + // Equalizes the throttles to the lowest of runtime and the lowest slot-throttle value + FAPI_TRY(mss::power_thermal::equalize_throttles(i_targets, i_throttle_type)); + + FAPI_INF("End exp_bulk_pwr_throttles"); + return fapi2::current_err; + + fapi_try_exit: + FAPI_ERR("Error calculating exp_bulk_pwr_throttles using %s throttling", + ((i_throttle_type == mss::throttle_type::POWER) ? "power" : "thermal")); + return fapi2::current_err; + } + +} //extern C diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.H index 1112aefb8..79472932b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.H @@ -22,3 +22,42 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_bulk_pwr_throttles.H +/// @brief The explorer thermal/power config +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: Memory +#ifndef EXP_BULK_PWR_THROTTLES_H_ +#define EXP_BULK_PWR_THROTTLES_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> + +typedef fapi2::ReturnCode (*exp_bulk_pwr_throttles_FP_t) ( const + std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >&, + const mss::throttle_type i_throttle_type); + +extern "C" +{ + + /// + /// @brief Set ATTR_MSS_PORT_MAXPOWER, ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT + /// @param[in] i_targets vector of OCMB chip + /// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits + /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK + /// @note Called in p9_mss_bulk_pwr_throttles + /// @note determines the throttle levels based off of the port's power curve, + /// sets the slot throttles to the same + /// @note Enums are POWER for power egulator throttles and THERMAL for thermal throttles + /// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value + /// + fapi2::ReturnCode exp_bulk_pwr_throttles( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& i_targets, + const mss::throttle_type i_throttle_type); +} + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.mk index 6dfbc4fe6..c0ef17e69 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_bulk_pwr_throttles.mk @@ -22,3 +22,9 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + +-include 00exp_common.mk + +PROCEDURE=exp_bulk_pwr_throttles +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C index 6a7b0d894..d7f80d648 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_check_for_ready.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,9 @@ #include <lib/shared/exp_defaults.H> #include <exp_check_for_ready.H> #include <lib/i2c/exp_i2c.H> -#include <generic/memory/lib/utils/poll.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <mss_explorer_attribute_getters.H> extern "C" { @@ -48,32 +50,13 @@ extern "C" /// fapi2::ReturnCode exp_check_for_ready(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { - // Using default parameters - mss::poll_parameters l_poll_params; + mss::display_git_commit_info("exp_check_for_ready"); - // From MSCC explorer firmware arch spec - // 4.1.5: After power-up, the Explorer Chip will respond with NACK to all incoming I2C requests - // from the HOST until the I2C slave interface is ready to receive commands. - FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool - { - return mss::exp::i2c::is_ready(i_target) == fapi2::FAPI2_RC_SUCCESS; - }), - fapi2::MSS_EXP_I2C_POLLING_TIMEOUT(). - set_TARGET(i_target), - "Failed to see an ACK from I2C -- polling timeout on %s", - mss::c_str(i_target) ); + fapi2::ATTR_MSS_CHECK_FOR_READY_TIMEOUT_Type l_poll_count = 0; - // We send the EXP_FW_STATUS command as a sanity check to see if it returns SUCCESS - FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool - { - return mss::exp::i2c::fw_status(i_target) == fapi2::FAPI2_RC_SUCCESS; - }), - fapi2::MSS_EXP_STATUS_POLLING_TIMEOUT(). - set_TARGET(i_target), - "Failled to see a successful return code -- polling timeout on %s", - mss::c_str(i_target) ); + FAPI_TRY(mss::attr::get_check_for_ready_timeout(i_target, l_poll_count)); - return fapi2::FAPI2_RC_SUCCESS; + FAPI_TRY(mss::exp::i2c::exp_check_for_ready_helper(i_target, l_poll_count, mss::DELAY_1MS)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C index 78d941db2..bc9187fbe 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,12 +34,15 @@ // *HWP Consumed by: FSP:HB #include <lib/shared/exp_consts.H> -#include <exp_inband.H> +#include <lib/inband/exp_inband.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/mss_bad_bits.H> #include <lib/exp_draminit_utils.H> #include <lib/phy/exp_train_display.H> #include <lib/phy/exp_train_handler.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/utils/fir/gen_mss_unmask.H> extern "C" { @@ -50,7 +53,10 @@ extern "C" /// fapi2::ReturnCode exp_draminit(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { + mss::display_git_commit_info("exp_draminit"); + uint32_t l_crc = 0; + uint8_t l_phy_init_mode = 0; user_input_msdg l_phy_params; FAPI_TRY(mss::exp::setup_phy_params(i_target, l_phy_params), @@ -60,47 +66,31 @@ extern "C" FAPI_TRY( mss::exp::ib::putUserInputMsdg(i_target, l_phy_params, l_crc), "Failed putUserInputMsdg() for %s", mss::c_str(i_target) ); - // Issue full boot mode cmd though EXP-FW REQ buffer + // Get phy init mode attribute + FAPI_TRY(mss::attr::get_exp_phy_init_mode(i_target, l_phy_init_mode)); + + // Make sure we're in range + FAPI_ASSERT((l_phy_init_mode <= fapi2::ENUM_ATTR_MSS_OCMB_PHY_INIT_MODE_WITH_EYE_CAPTURE), + fapi2::MSS_EXP_UNKNOWN_PHY_INIT_MODE() + .set_TARGET(i_target) + .set_VALUE(l_phy_init_mode), + "%s Value for phy init mode for exp_draminit is unknown: %u expected 0 (NORMAL), 1 (WITH_EYE_CAPTURE)", + mss::c_str(i_target), l_phy_init_mode); + + // Call appropriate init function + if (l_phy_init_mode == fapi2::ENUM_ATTR_MSS_OCMB_PHY_INIT_MODE_NORMAL) { - host_fw_command_struct l_cmd; - mss::exp::setup_cmd_params(l_crc, l_cmd); - FAPI_TRY( mss::exp::ib::putCMD(i_target, l_cmd), - "Failed putCMD() for %s", mss::c_str(i_target) ); + FAPI_TRY(mss::exp::host_fw_phy_normal_init(i_target, l_crc)); } - - // Read the response message from EXP-FW RESP buffer + else { - host_fw_response_struct l_response; - user_response_msdg l_train_response; - - std::vector<uint8_t> l_rsp_data; - fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS); - - FAPI_TRY( mss::exp::ib::getRSP(i_target, l_response, l_rsp_data), - "Failed getRSP() for %s", mss::c_str(i_target) ); - - // Proccesses the response data - FAPI_TRY( mss::exp::read_training_response(i_target, l_rsp_data, l_train_response), - "Failed read_training_response for %s", mss::c_str(i_target)); - - // Displays the training response - FAPI_TRY( mss::exp::train::display_info(i_target, l_train_response)); - - // Check if cmd was successful - l_rc = mss::exp::check::response(i_target, l_response); - - // If not, then we need to process the bad bitmap - if(l_rc != fapi2::FAPI2_RC_SUCCESS) - { - mss::exp::bad_bit_interface l_interface(l_train_response); + FAPI_TRY(mss::exp::host_fw_phy_init_with_eye_capture(i_target, l_crc, l_phy_params)); + } - // Record bad bits should only fail if we have an attributes issue - that's a major issue - FAPI_TRY(mss::record_bad_bits<mss::mc_type::EXPLORER>(i_target, l_interface)); + // Unmask registers after draminit training + FAPI_TRY(mss::unmask::after_draminit_training(i_target), "%s Failed after_draminit_training", mss::c_str(i_target)); - // Now, go to our true error handling procedure - FAPI_TRY(l_rc, "mss::exp::check::response failed for %s", mss::c_str(i_target)); - } - } + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: FAPI_INF("Draminit training - %s %s", diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.mk index dd6f3e2a3..a9e488383 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C index be2d4e36f..546299f57 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,6 +40,8 @@ #include <generic/memory/lib/utils/count_dimm.H> #include <lib/mc/exp_port.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/utils/fir/gen_mss_unmask.H> extern "C" { @@ -50,6 +52,8 @@ extern "C" /// fapi2::ReturnCode exp_draminit_mc( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) { + mss::display_git_commit_info("exp_draminit_mc"); + FAPI_INF("%s Start exp_draminit MC", mss::c_str(i_target)); @@ -81,18 +85,21 @@ extern "C" FAPI_TRY( mss::change_refresh_enable(i_target, mss::HIGH), "%s Failed change_refresh_enable", mss::c_str(i_target) ); + // Trigger the MC to take the DRAMs out of self refresh + FAPI_TRY( mss::change_force_str<mss::mc_type::EXPLORER>(i_target, mss::LOW), "%s Failed change_force_str", + mss::c_str(i_target) ); + // Enable periodic short zq cal FAPI_TRY( mss::enable_zq_cal(i_target), "%s Failed enable_zq_cal", mss::c_str(i_target) ); // Enable ecc checking - FAPI_TRY( mss::enable_read_ecc(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc<mss::mc_type::EXPLORER>(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // Apply marks from OCMB VPD FAPI_TRY( mss::apply_mark_store(i_target), "%s Failed enable_read_ecc", mss::c_str(i_target) ); - // TODO: Move mss::unmask::after_draminit_mc to generic and call it - // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. - //FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); + // Unmask registers after draminit_mc + FAPI_TRY(mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target)); fapi_try_exit: FAPI_INF("%s End exp_draminit MC", mss::c_str(i_target)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.C new file mode 100644 index 000000000..ad2c20a97 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.C @@ -0,0 +1,109 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file exp_fw_log_data.C +/// +/// @brief Collects Explorer firmware log data +// ---------------------------------------- +// *HWP HWP Owner: Matt Derksen <mderkse1@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB +// ---------------------------------------- +#include <exp_fw_log_data.H> +#include <fapi2.H> +#include <lib/inband/exp_inband.H> +#include <lib/inband/exp_fw_log.H> +#include <lib/shared/exp_consts.H> +#include <exp_data_structs.H> +#include <generic/memory/lib/utils/c_str.H> + + +extern "C" +{ + /// See header + fapi2::ReturnCode exp_active_log( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmbTarget, + std::vector<uint8_t>& o_data) + { + host_fw_command_struct l_active_errl_cmd; + host_fw_response_struct l_response; + + // Set up the command packet + mss::exp::ib::build_log_cmd(i_ocmbTarget, + mss::exp::ib::SUB_CMD_READ_ACTIVE_LOG, + l_active_errl_cmd); + + // Send the command packet + FAPI_TRY(mss::exp::ib::putCMD(i_ocmbTarget, l_active_errl_cmd), + "exp_active_error_log: Failed putCMD() for %s!", + mss::c_str(i_ocmbTarget)); + + // Get the response + FAPI_TRY(mss::exp::ib::getRSP(i_ocmbTarget, l_response, o_data), + "exp_active_error_log: Failed getRSP() cmd " + "for %s!", mss::c_str(i_ocmbTarget)); + + // Check if cmd was successful + FAPI_TRY(mss::exp::ib::check_log_cmd_response(i_ocmbTarget, l_response), + "exp_active_error_log: Failed check_log_cmd_response()" + " for %s!", mss::c_str(i_ocmbTarget)); + + fapi_try_exit: + return fapi2::current_err; + } + + + /// See header + fapi2::ReturnCode exp_saved_log( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmbTarget, + std::vector<uint8_t>& o_data) + { + host_fw_command_struct l_saved_log_cmd; + host_fw_response_struct l_response; + + // Set up the command packet + mss::exp::ib::build_log_cmd(i_ocmbTarget, + mss::exp::ib::SUB_CMD_READ_SAVED_LOG, + l_saved_log_cmd); + + // Send the command packet + FAPI_TRY(mss::exp::ib::putCMD(i_ocmbTarget, l_saved_log_cmd), + "exp_saved_log: Failed putCMD() for %s!", + mss::c_str(i_ocmbTarget)); + + // Get the response + FAPI_TRY(mss::exp::ib::getRSP(i_ocmbTarget, l_response, o_data), + "exp_saved_log: Failed getRSP() for %s!", + mss::c_str(i_ocmbTarget)); + + // Check if cmd was successful + FAPI_TRY(mss::exp::ib::check_log_cmd_response(i_ocmbTarget, l_response), + "exp_saved_log: Failed check_log_cmd_response()" + " for %s!", mss::c_str(i_ocmbTarget)); + fapi_try_exit: + return fapi2::current_err; + } +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.H new file mode 100644 index 000000000..4cfe074a1 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.H @@ -0,0 +1,77 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_log_data.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file exp_fw_log_data.H +/// @brief Procedure declaration to get Explorer log data +/// +// ---------------------------------------- +// *HWP HWP Owner: Matt Derksen <mderkse1@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB +// ---------------------------------------- +#ifndef __EXP_FW_LOG_DATA__ +#define __EXP_FW_LOG_DATA__ + +#include <fapi2.H> +#include <vector> + +// Required for Cronus +typedef fapi2::ReturnCode (*exp_active_log_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + std::vector<uint8_t>& ); + +typedef fapi2::ReturnCode (*exp_saved_log_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + std::vector<uint8_t>& ); + +extern "C" +{ + + /// + /// @brief Grab active log entries from Explorer RAM + /// @param[in] i_target the controller + /// @param[out] o_data - where to put error log data + /// + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_active_log( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmbTarget, + std::vector<uint8_t>& o_data ); + + /// + /// @brief Grab saved log entries from Explorer SPI flash + /// @param[in] i_target the controller + /// @param[out] o_data - where to put error log data + /// + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_saved_log( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmbTarget, + std::vector<uint8_t>& o_data ); + +}// extern C +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.C new file mode 100644 index 000000000..8a4cb9978 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.C @@ -0,0 +1,379 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_fw_update.C +/// @brief Procedure definition to update explorer firmware +/// +// *HWP HWP Owner: Glenn Miles <milesg@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <exp_fw_update.H> +#include <lib/inband/exp_inband.H> +#include <lib/shared/exp_consts.H> +#include <exp_data_structs.H> +#include <generic/memory/lib/utils/c_str.H> +#include <lib/omi/crc32.H> +#include <mmio_access.H> + +namespace mss +{ +namespace exp +{ + +constexpr uint32_t FLASH_WRITE_BLOCK_SIZE = 256; + +namespace bupg +{ + +/// +/// @brief Checks explorer response argument for a successful command +/// @param[in] i_target OCMB target +/// @param[in] i_rsp response from command +/// @param[in] i_cmd original command +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode check_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp, + const host_fw_command_struct& i_cmd) +{ + std::vector<uint8_t> resp_arg; + uint8_t success_flag = 0; + uint16_t err_code = 0; + uint32_t index = 0; + + //copy response_argument field into a vector that can be used by + //readCrctEndian() + resp_arg.assign(i_rsp.response_argument, + i_rsp.response_argument + ARGUMENT_SIZE); + + //convert fields to native endianness + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, success_flag)); + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, err_code)); + + // Check if cmd was successful + FAPI_ASSERT(success_flag == omi::response_arg::SUCCESS && + i_rsp.request_identifier == i_cmd.request_identifier, + fapi2::EXP_UPDATE_CMD_FAILED(). + set_TARGET(i_target). + set_RSP_ID(i_rsp.response_id). + set_REQ_ID(i_rsp.request_identifier). + set_ERROR_CODE(err_code). + set_RSP_DATA(i_rsp), + "Recieved failure response for firmware update command on %s", + mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +}//bupg + +/// +/// @brief host_fw_command_struct structure setup for flash_write +/// @param[in] i_binary_size the total size of the binary image +/// @param[in] i_seq_number the sequence number of this command +/// @param[in] i_cmd_data_crc the command data CRC +/// @param[out] o_cmd the command packet to update +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode setup_flash_write_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_binary_size, + const uint16_t i_seq_number, + const uint32_t i_cmd_data_crc, + host_fw_command_struct& o_cmd) +{ + std::vector<uint8_t> swapped32; + std::vector<uint8_t> cmd_args; + std::vector<uint8_t> test16_vec; + const uint16_t test16_value = 1; + + memset(&o_cmd, 0, sizeof(host_fw_command_struct)); + + // Issue EXP_FW_BINARY_UPGRADE cmd though EXP-FW REQ buffer + o_cmd.cmd_id = mss::exp::omi::EXP_FW_BINARY_UPGRADE; + o_cmd.cmd_flags = mss::exp::omi::ADDITIONAL_DATA; + + // Host generated id number (returned in response packet) + uint32_t l_counter = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OCMB_COUNTER, i_target, l_counter)); + o_cmd.request_identifier = l_counter; + + //always send a block of data + o_cmd.cmd_length = FLASH_WRITE_BLOCK_SIZE; + + o_cmd.cmd_crc = i_cmd_data_crc; + o_cmd.host_work_area = 0; + o_cmd.cmd_work_area = 0; + memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); + + //populate command arguments using correct endian byte ordering + //NOTE: putCMD can not do the byte ordering of the command_arguments + // field for us. + + //sub-command id is single byte. Never requires byte-swapping. + cmd_args.push_back(bupg::SUB_CMD_WRITE); + + //forceCrctEndian can only handle 1, 2, 4, and 8 byte integers, so + //for the flash_binary_size field, which is a 3 byte integer, treat + //it as a 4 byte value and shift result right or left one byte + //depending on if it is little or big endian. + FAPI_TRY(mss::exp::ib::forceCrctEndian(i_binary_size, swapped32)); + + // Test for big or little endian value on a known value (0x1) + FAPI_TRY(mss::exp::ib::forceCrctEndian(test16_value, test16_vec)); + + //if the least significant byte ended up in byte 0, then the + //result is a little endian value. + if(test16_vec[0] == 1) + { + //use first 3 bytes of 4 byte value + cmd_args.insert(cmd_args.end(), swapped32.begin(), swapped32.end() - 1); + } + else //big endian + { + //use last 3 bytes of 4 byte value + cmd_args.insert(cmd_args.end(), swapped32.begin() + 1, swapped32.end()); + } + + //add the sequence number + FAPI_TRY(mss::exp::ib::forceCrctEndian(i_seq_number, cmd_args)); + + //copy cmd_args vector into command_args array + std::copy(cmd_args.begin(), cmd_args.end(), &o_cmd.command_argument[0]); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Sets the command_argument fields for flash_commit sub-command +/// in the correct endianness. +/// +/// @param[in] i_target OCMB target that will be acted upon with this command +/// @param[out] o_cmd the command packet to update +/// +fapi2::ReturnCode setup_flash_commit_cmd( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_command_struct& o_cmd) +{ + memset(&o_cmd, 0, sizeof(host_fw_command_struct)); + + // Issue EXP_FW_BINARY_UPGRADE cmd though EXP-FW REQ buffer + o_cmd.cmd_id = mss::exp::omi::EXP_FW_BINARY_UPGRADE; + o_cmd.cmd_flags = 0; + + // Retrieve a unique sequence id for this transaction + uint32_t l_counter = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OCMB_COUNTER, i_target, l_counter)); + o_cmd.request_identifier = l_counter; + o_cmd.cmd_length = 0; + + o_cmd.cmd_crc = 0xffffffff; + o_cmd.host_work_area = 0; + o_cmd.cmd_work_area = 0; + memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); + + // Set the sub-command ID in the command argument field to FLASH_COMMIT + o_cmd.command_argument[0] = bupg::SUB_CMD_COMMIT; + +fapi_try_exit: + return fapi2::current_err; +} + +}//exp +}//mss + +extern "C" +{ + +/// +/// @brief Updates explorer firmware +/// @param[in] i_target the controller +/// @param[in] i_image_ptr pointer to the binary image +/// @param[in] i_image_sz size of the binary image +/// @return FAPI2_RC_SUCCESS if ok +/// + fapi2::ReturnCode exp_fw_update(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t* i_image_ptr, const size_t i_image_sz) + { + uint16_t seq_num = 0; + uint32_t block_crc = 0; + std::vector<uint8_t> buffer; + const uint8_t* end_ptr = i_image_ptr + i_image_sz; + + FAPI_INF("Entering exp_fw_update(%s). imageSize[0x%08x]", + mss::c_str(i_target), i_image_sz); + + //Check that i_image_sz value is not larger than 3 bytes, which + //is the actual field size for this value in the packet. + FAPI_ASSERT(((i_image_sz & 0xff000000) == 0), + fapi2::EXP_UPDATE_INVALID_IMAGE_SIZE() + .set_IMAGE_SIZE(i_image_sz), + "exp_fw_update: image size[0x%08x] must be less than 16MB!", + i_image_sz); + + // Write successive blocks until the entire image is written + buffer.reserve(mss::exp::FLASH_WRITE_BLOCK_SIZE); + + for(uint8_t* cur_ptr = const_cast<uint8_t*>(i_image_ptr); + cur_ptr < end_ptr; + cur_ptr += mss::exp::FLASH_WRITE_BLOCK_SIZE) + { + const uint32_t bytes_left = end_ptr - cur_ptr; + const uint32_t data_size = (bytes_left < + mss::exp::FLASH_WRITE_BLOCK_SIZE) ? + bytes_left : + mss::exp::FLASH_WRITE_BLOCK_SIZE; + + // copy data into a vector (required by crc32_gen) + buffer.assign(cur_ptr, cur_ptr + data_size); + + // pad end with FF's if smaller than block size + buffer.resize(mss::exp::FLASH_WRITE_BLOCK_SIZE, 0xFF); + + // calculate the crc + block_crc = crc32_gen(buffer); + + // endian swap + FAPI_TRY(mss::exp::ib::correctMMIOEndianForStruct(buffer)); + FAPI_TRY(mss::exp::ib::correctMMIOword_order(buffer)); + + // write block to data buffer on explorer + FAPI_TRY(fapi2::putMMIO(i_target, + mss::exp::ib::EXPLR_IB_DATA_ADDR, + mss::exp::ib::BUFFER_TRANSACTION_SIZE, + buffer)); + + // Issue flash_write sub-command through EXP-FW request buffer + host_fw_command_struct flash_write_cmd; + { + // Set up the command packet + FAPI_TRY(mss::exp::setup_flash_write_cmd( + i_target, + i_image_sz, + seq_num, + block_crc, + flash_write_cmd), + "exp_fw_update: Failed setup_flash_write_cmd() " + "for %s! seq_num[%u]", + mss::c_str(i_target), seq_num); + + // Send the command packet + FAPI_TRY(mss::exp::ib::putCMD(i_target, flash_write_cmd), + "exp_fw_update: Failed flash_write putCMD() " + "for %s! seq_num[%u]", + mss::c_str(i_target), seq_num); + } + + // Read the response message from EXP-FW RESP buffer + { + host_fw_response_struct response; + std::vector<uint8_t> rsp_data; + + // Normally we need to poll the outbound doorbell and read/check the + // fw_response_struct to make sure the command completed. In this case, + // we will only check the fw_response_struct for every 16th transfer to + // speed things up. + // We still have to poll the doorbell to make sure the command completed + if ((seq_num % 16) == 0) + { + // Read response from buffer + FAPI_TRY(mss::exp::ib::getRSP(i_target, response, rsp_data), + "exp_fw_update: getRSP() failed for flash_write " + "on %s! seq_num[%u]", + mss::c_str(i_target), seq_num); + + // Check status in response packet + FAPI_TRY(mss::exp::bupg::check_response(i_target, response, flash_write_cmd), + "exp_fw_update: error response for flash_write " + "on %s! seq_num[%u]", + mss::c_str(i_target), seq_num); + } + else + { + // Poll response doorbell only + FAPI_TRY(mss::exp::ib::poll_for_response_ready(i_target), + "exp_fw_update: error polling response for flash_write " + "on %s! seq_num[%u]", + mss::c_str(i_target), seq_num); + + // Clear response doorbell + FAPI_TRY(mss::exp::ib::clear_outbound_doorbell(i_target)); + } + } + + //increment sequence number after each 256 byte block is written + seq_num++; + } + + host_fw_command_struct flash_commit_cmd; + // Issue the flash_commit sub-command through EXP-FW request buffer + { + FAPI_TRY(mss::exp::setup_flash_commit_cmd(i_target, + flash_commit_cmd)); + FAPI_TRY(mss::exp::ib::putCMD(i_target, flash_commit_cmd), + "exp_fw_update: putCMD() failed for flash_commit on %s!", + mss::c_str(i_target)); + } + + // Read the response message from EXP-FW RESP buffer + { + host_fw_response_struct response; + std::vector<uint8_t> rsp_data; + + // Wait a little while first (value based on MCHP estimations): + // 2 sec for image authentication + // 7 sec to erase 600K on flash part + // 1800 usec to program flash image + // = 10.8 sec, so wait 15 sec to be safe + FAPI_INF("Waiting for flash image commit to complete on %s...", mss::c_str(i_target)); + + for (uint64_t l_seconds = 0; l_seconds < 15; ++l_seconds) + { + FAPI_TRY(fapi2::delay(mss::DELAY_1S, 200)); + } + + FAPI_TRY(mss::exp::ib::getRSP(i_target, response, rsp_data), + "exp_fw_update: getRSP() failed for flash_commit on %s!", + mss::c_str(i_target) ); + + // Check if cmd was successful + FAPI_TRY(mss::exp::bupg::check_response(i_target, response, flash_commit_cmd), + "exp_fw_update: error response for flash_commit on %s!", + mss::c_str(i_target) ); + } + + fapi_try_exit: + FAPI_INF("Exiting exp_fw_update(%s) with return code : 0x%08x...", + mss::c_str(i_target), (uint64_t) fapi2::current_err); + return fapi2::current_err; + } + +} //extern "C" diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.H new file mode 100644 index 000000000..b6c1fbd0f --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.H @@ -0,0 +1,126 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_fw_update.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_fw_update.H +/// @brief Procedure declaration to update explorer firmware +/// +// *HWP HWP Owner: Glenn Miles <milesg@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_EXP_FW_UPDATE__ +#define __MSS_EXP_FW_UPDATE__ + +#include <fapi2.H> +#include <exp_data_structs.H> + +// Required for Cronus +typedef fapi2::ReturnCode (*exp_fw_update_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + const uint8_t*, const size_t); + +extern "C" +{ + +/// +/// @brief Updates explorer firmware +/// @param[in] i_target the controller +/// @param[in] i_image_ptr pointer to the binary image +/// @param[in] i_image_sz size of the binary image +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode exp_fw_update(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t* i_image_ptr, const size_t i_image_sz); + +}// extern C + +namespace mss +{ +namespace exp +{ +namespace bupg +{ + +/// +/// @brief Defines the sub-commands available for the EXP_FW_BINARY_UPGRADE +/// command +/// +typedef enum sub_cmd_id +{ + SUB_CMD_NULL = 0x00, + SUB_CMD_WRITE = 0x01, + SUB_CMD_COMMIT = 0x02, + SUB_CMD_WRITE_ABORT = 0x03, + SUB_CMD_PART_INFO_GET = 0x04, + SUB_CMD_READ = 0x05, + SUB_CMD_PART_ERASE = 0x06, + SUB_CMD_MAX +} sub_cmd_id_t; + +/// +/// @brief Checks explorer response argument for a successful command +/// @param[in] i_target OCMB target +/// @param[in] i_rsp response command +/// @param[in] i_cmd original command +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode check_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp, + const host_fw_command_struct& i_cmd); + +}// ns bupg + +/// +/// @brief host_fw_command_struct structure setup for flash_write +/// @param[in] i_target OCMB target that will be acted upon with this command +/// @param[in] i_binary_size the total size of the binary image +/// @param[in] i_seq_number the sequence number of this command +/// @param[in] i_cmd_data_crc the command data CRC +/// @param[out] o_cmd the command packet to update +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode setup_flash_write_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_binary_size, + const uint16_t i_seq_number, + const uint32_t i_cmd_data_crc, + host_fw_command_struct& o_cmd); + +/// +/// @brief Sets the command_argument fields for flash_commit sub-command +/// in the correct endianness. +/// +/// @param[in] i_target OCMB target that will be acted upon with this command +/// @param[out] o_cmd the command packet to update +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode setup_flash_commit_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_command_struct& o_cmd); + +}// ns exp +}// ns mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getecid.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getecid.C index ad20d2e0c..ac8d7e7cb 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getecid.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getecid.C @@ -39,6 +39,8 @@ #include <explorer_scom_addresses.H> #include <explorer_scom_addresses_fld.H> #include <mss_explorer_attribute_setters.H> +#include <generic/memory/mss_git_data_helper.H> +#include <lib/plug_rules/exp_plug_rules.H> extern "C" { @@ -50,24 +52,22 @@ extern "C" /// fapi2::ReturnCode exp_getecid(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { - // Using FUSE enterprise_dis bit, determine whether enterprise is disabled, otherwise - // we will enable it. Override to disable it is done in omi_setup. Half_dimm_mode we - // will also disable by default, as it is not a feature of P systems + mss::display_git_commit_info("exp_getecid"); + { - uint8_t l_enterprise_mode = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_MODE_NON_ENTERPRISE; // 0 - uint8_t l_half_dimm_mode = fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_FULL_DIMM; // 0 + bool l_enterprise_fuse = false; + bool l_enterprise_final = false; - FAPI_TRY(mss::exp::ecid::get_enterprise_and_half_dimm_from_fuse( - i_target, l_enterprise_mode, l_half_dimm_mode), - "exp_getecid: getting enterprise and half_dimm from fuse failed on %s", + FAPI_TRY(mss::exp::ecid::get_enterprise_from_fuse(i_target, l_enterprise_fuse), + "exp_getecid: getting enterprise from fuse failed on %s", mss::c_str(i_target)); - // Set attributes - FAPI_TRY(mss::attr::set_ocmb_enterprise_mode(i_target, l_enterprise_mode), - "exp_getecid: Could not set ATTR_MSS_OCMB_ENTERPRISE_MODE"); + // Calculate the global enterprise mode state while verifying plug rules with policy and override attributes + FAPI_TRY(mss::exp::plug_rule::enterprise_mode(i_target, l_enterprise_fuse, l_enterprise_final)); - FAPI_TRY(mss::attr::set_ocmb_half_dimm_mode(i_target, l_half_dimm_mode), - "exp_getecid: Could not set ATTR_MSS_OCMB_HALF_DIMM_MODE"); + // Set global enterprise mode attribute + FAPI_TRY(mss::attr::set_ocmb_enterprise_mode(i_target, l_enterprise_final), + "exp_getecid: Could not set ATTR_MSS_OCMB_ENTERPRISE_MODE"); } // @@ -87,6 +87,11 @@ extern "C" FAPI_TRY(mss::exp::ecid::read_from_fuse(i_target, l_ecid), "exp_getecid: Could not read ecid from FUSE on %s", mss::c_str(i_target)); + for (uint8_t l_ecid_idx = 0; l_ecid_idx < mss::exp::ecid_consts::FUSE_ARRAY_SIZE; ++l_ecid_idx) + { + FAPI_INF("%s ECID[%u]: 0x%04X", mss::c_str(i_target), l_ecid_idx, l_ecid[l_ecid_idx]); + } + // TK - Remove once ATTR_ECID is made large enough FAPI_TRY(mss::attr::set_ocmb_ecid(i_target, l_ecid), "exp_getecid: Could not set ATTR_MSS_OCMB_ECID on %s", mss::c_str(i_target)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.C new file mode 100644 index 000000000..a5008d62f --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_getidec.C +/// @brief Contains function to lookup Chip ID and EC values of Explorer Chip +/// +/// *HWP HWP Owner: Christian Geddes <crgeddes@us.ibm.com> +/// *HWP HWP Backup: <none> +/// *HWP Team: Hostboot +/// *HWP Level: 2 +/// *HWP Consumed by: Hostboot / Cronus + +#include <fapi2.H> +#include <exp_getidec.H> +#include <lib/shared/exp_consts.H> +#include <chips/ocmb/explorer/common/include/explorer_scom_addresses.H> +#include <chips/ocmb/explorer/common/include/explorer_scom_addresses_fixes.H> +#include <chips/ocmb/explorer/common/include/explorer_scom_addresses_fld.H> +#include <chips/ocmb/explorer/common/include/explorer_scom_addresses_fld_fixes.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/utils/c_str.H> + +extern "C" +{ + + /// + /// @brief Lookup the Chip ID and EC level values for this explorer chip + /// @param[in] i_target Explorer OCMB chip + /// @param[out] o_chipId Explorer Chip ID + /// @param[out] o_chipEc Explorer Chip EC + /// @return fapi2:ReturnCode FAPI2_RC_SUCCESS if success, else error code. + /// + fapi2::ReturnCode exp_getidec(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint16_t& o_chipId, + uint8_t& o_chipEc) + { + mss::display_git_commit_info("exp_getidec"); + uint8_t l_revision = 0; + uint8_t l_location = 0; + uint8_t l_chipBaseId = 0; + fapi2::buffer<uint64_t> l_chip_info_buffer; + fapi2::buffer<uint64_t> l_efuse3_buffer; + + // The chipid and location come from the CHIP_INFO register + FAPI_TRY(fapi2::getScom( i_target, + static_cast<uint64_t>(mss::exp::idec_consts::EXPLR_CHIP_INFO_REG), + l_chip_info_buffer ), + "exp_getidec: could not read explorer chip_info register register 0x%08x", + mss::exp::idec_consts::EXPLR_CHIP_INFO_REG); + + l_chip_info_buffer.extractToRight<mss::exp::idec_consts::LOCATION_BIT_START, + mss::exp::idec_consts::LOCATION_BIT_LENGTH>(l_location); + l_chip_info_buffer.extractToRight<mss::exp::idec_consts::CHIPID_BIT_START, + mss::exp::idec_consts::CHIPID_BIT_LENGTH>(l_chipBaseId); + + // Location 0:3 + // Empty 4:7 + // ChipId 8:15 + o_chipId = (l_location << 12) | l_chipBaseId; + + + // The revision/DD/EC level comes from EFUSE_IMAGE_OUT_3 + FAPI_TRY(fapi2::getScom( i_target, static_cast<uint64_t>(EXPLR_EFUSE_IMAGE_OUT_3), l_efuse3_buffer ), + "exp_getidec: could not read explorer efuse_out3 register 0x%08x", EXPLR_EFUSE_IMAGE_OUT_3); + + l_efuse3_buffer.extractToRight<mss::exp::idec_consts::REVISION_BIT_START, + mss::exp::idec_consts::REVISION_BIT_LENGTH>(l_revision); + + // Due to limitations in what logic could be updated between revisions + // there is no explicit Major+Minor value available in the hardware. + // Instead we have to explicitly convert a rolling number into the + // standard major.minor DD value we expect. + o_chipEc = 0; + + switch( l_revision ) + { + case(0): + o_chipEc = 0x10; + break; //A.0 + + case(1): + o_chipEc = 0x11; + break; //A.1 + + case(2): + o_chipEc = 0x20; + break; //B.0 + } + + // Ensure we found a known level + FAPI_ASSERT(o_chipEc != 0, + fapi2::EXP_UNKNOWN_REVISION(). + set_TARGET(i_target). + set_REVISION(l_revision). + set_CHIP_INFO_REG(l_chip_info_buffer). + set_EFUSE_IMAGE_OUT_3(l_efuse3_buffer), + "The %s revision (%d) does not match a known DD level.", + mss::c_str(i_target), l_revision); + + + FAPI_DBG("EC found 0x%.02x chipId found 0x%.04x", o_chipEc, o_chipId); + + fapi_try_exit: + return fapi2::current_err; + } + +} // extern "C" diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.H new file mode 100644 index 000000000..e319981a7 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.H @@ -0,0 +1,60 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_getidec.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_getidec.H +/// @brief Contains function to lookup Chip ID and EC values of Explorer Chip +/// +/// *HWP HWP Owner: Christian Geddes <crgeddes@us.ibm.com> +/// *HWP HWP Backup: <none> +/// *HWP Team: Hostboot +/// *HWP Level: 2 +/// *HWP Consumed by: Hostboot / Cronus + +#ifndef __EXP_GETIDEC_H_ +#define __EXP_GETIDEC_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*exp_getidec_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + uint16_t&, uint8_t&); + +extern "C" +{ + +/// +/// @brief Lookup the Chip ID and EC level values for this explorer chip +/// @param[in] i_target Explorer OCMB chip +/// @param[out] o_chipId Explorer Chip ID +/// @param[out] o_chipEc Explorer Chip EC +/// @return fapi2:ReturnCode FAPI2_RC_SUCCESS if success, else error code. +/// + fapi2::ReturnCode exp_getidec(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint16_t& o_chipId, + uint8_t& o_chipEc); + +} // extern "C" + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk deleted file mode 100644 index 3f998fd58..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk +++ /dev/null @@ -1,32 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.mk $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2018 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -PROCEDURE=exp_inband -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/nest) -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/common/include) -# Explicitly calling the below to only pick up the generic constants -# We don't want to clutter this procedure w/ too many includes -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)) -$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/procedures/hwp/memory) -$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.C new file mode 100644 index 000000000..71358528f --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.C @@ -0,0 +1,190 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_eff_config_thermal.C +/// @brief The explorer thermal/power config +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: Memory + +#include <lib/shared/exp_defaults.H> +#include <fapi2.H> +#include <vector> +#include <exp_bulk_pwr_throttles.H> +#include <exp_mss_eff_config_thermal.H> +#include <lib/power_thermal/exp_decoder.H> +#include <lib/power_thermal/exp_throttle.H> +#include <lib/shared/exp_consts.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_system_attribute_getters.H> + +extern "C" +{ + /// + /// @brief Perform thermal calculations + /// @param[in] i_targets vector of OCMB chip + /// @return FAPI2_RC_SUCCESS iff ok + fapi2::ReturnCode exp_mss_eff_config_thermal( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& + i_targets ) + { + using TT = mss::power_thermal::throttle_traits<>; + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + FAPI_INF("Start exp_mss_eff_config_thermal"); + + // For regulaor power/current throttling or thermal throtling + // Do thermal throttling last so the attributes end up representing a total power value for later usage + // Need to have ATTR_EXP_TOTAL_PWR_SLOPE and ATTR_EXP_TOTAL_PWR_INTERCEPT with total DIMM power + // (not regulator current values) after exp_mss_eff_config_thermal is run, so when OCC calls + // exp_bulk_pwr_throttles at runtime the total DIMM power will be used for any memory bulk supply throttling + const std::vector<mss::throttle_type> throttle_types{ mss::throttle_type::POWER, mss::throttle_type::THERMAL}; + + // Return error if safemode throttle utilization is less than MIN_UTIL + const uint64_t l_min_util = TT::MIN_UTIL; + uint32_t l_safemode_util = 0; + FAPI_TRY( mss::attr::get_mrw_safemode_dram_databus_util(l_safemode_util), "Error in exp_mss_eff_config_thermal" ); + FAPI_ASSERT( l_safemode_util >= TT::MIN_UTIL, + fapi2::MSS_MRW_SAFEMODE_UTIL_THROTTLE_NOT_SUPPORTED() + .set_MRW_SAFEMODE_UTIL(l_safemode_util) + .set_MIN_UTIL_VALUE(l_min_util), + "MRW safemode util (%d centi percent) has less util than the min util allowed (%d centi percent)", + l_safemode_util, l_min_util ); + + for ( const auto& l_ocmb : i_targets) + { + //Restore runtime_throttles + //Sets throttles to max_databus_util value + FAPI_INF("Restoring throttles for %s", mss::c_str(l_ocmb)); + FAPI_TRY( mss::power_thermal::restore_runtime_throttles<>(l_ocmb), "Error in exp_mss_eff_config_thermal"); + } + + for (const auto& l_throttle_type : throttle_types ) + { + for ( const auto& l_ocmb : i_targets) + { + //Not doing any work if there are no dimms installed + if (mss::count_dimm(l_ocmb) == 0) + { + FAPI_INF("Skipping eff_config thermal because no dimms for %s", mss::c_str(l_ocmb)); + continue; + } + + // Thermal power (OCMB+DRAM) + uint64_t l_thermal_power_limit[TT::SIZE_OF_THERMAL_LIMIT_ATTR] = {0}; + uint64_t l_thermal_power_slope[TT::SIZE_OF_THERMAL_SLOPE_ATTR] = {0}; + uint64_t l_thermal_power_intecept[TT::SIZE_OF_THERMAL_INTERCEPT_ATTR] = {0}; + // Power (PMIC) + uint64_t l_current_curve_with_limit[TT::SIZE_OF_CURRENT_CURVE_WITH_LIMIT_ATTR] = {0}; + + // Get the data from MRW + FAPI_TRY( mss::attr::get_mrw_ocmb_thermal_memory_power_limit (l_thermal_power_limit), + "Error in exp_mss_eff_config_thermal"); + FAPI_TRY( mss::attr::get_mrw_ocmb_pwr_slope (l_thermal_power_slope), "Error in exp_mss_eff_config_thermal"); + FAPI_TRY( mss::attr::get_mrw_ocmb_pwr_intercept (l_thermal_power_intecept), "Error in exp_mss_eff_config_thermal"); + FAPI_TRY( mss::attr::get_mrw_ocmb_current_curve_with_limit (l_current_curve_with_limit), + "Error in exp_mss_eff_config_thermal"); + + // Convert array to vector + std::vector<uint64_t> l_thermal_power_limit_v ( std::begin(l_thermal_power_limit), + std::end(l_thermal_power_limit) ); + std::vector<uint64_t> l_thermal_power_slope_v ( std::begin(l_thermal_power_slope), + std::end(l_thermal_power_slope) ); + std::vector<uint64_t> l_thermal_power_intecept_v ( std::begin(l_thermal_power_intecept), + std::end(l_thermal_power_intecept) ); + std::vector<uint64_t> l_current_curve_with_limit_v( std::begin(l_current_curve_with_limit), + std::end(l_current_curve_with_limit) ); + + + uint16_t l_slope [TT::DIMMS_PER_PORT] = {0}; + uint16_t l_intercept[TT::DIMMS_PER_PORT] = {0}; + uint32_t l_limit [TT::DIMMS_PER_PORT] = {0}; + + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(l_ocmb)) + { + //Don't run if there are no dimms on the port + if (mss::count_dimm(l_port) == 0) + { + continue; + } + + // Set the thermal power throttle + //Set the PMIC current slope, intercept and limit + FAPI_TRY( mss::power_thermal::get_power_attrs (l_throttle_type, + l_port, + l_thermal_power_slope_v, + l_thermal_power_intecept_v, + l_thermal_power_limit_v, + l_current_curve_with_limit_v, + l_slope, + l_intercept, + l_limit) ); + + FAPI_TRY(mss::attr::set_total_pwr_slope(l_port, l_slope)); + FAPI_TRY(mss::attr::set_total_pwr_intercept(l_port, l_intercept)); + FAPI_TRY(mss::attr::set_dimm_thermal_limit(l_port, l_limit)); + FAPI_TRY(mss::attr::set_mem_watt_target(l_port, l_limit)); + + for ( const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(l_port) ) + { + const uint8_t l_dimm_pos = mss::index(l_dimm); + FAPI_INF( "DIMM (%d) slope is %d, intercept is %d, limit is %d for %s", + l_dimm_pos, l_slope[l_dimm_pos], l_intercept[l_dimm_pos], + l_limit[l_dimm_pos], mss::c_str(l_port)); + } + } + + FAPI_INF("Starting pwr_throttles(%s)", mss::throttle_type::POWER == l_throttle_type ? "POWER" : "THERMAL"); + //get the power limits, done per dimm and set to worst case for the slot and port throttles + FAPI_TRY(mss::power_thermal::pwr_throttles(l_ocmb, l_throttle_type)); + } + + // Equalizes the throttles to the lowest of runtime and the lowest slot-throttle value + FAPI_TRY(mss::power_thermal::equalize_throttles(i_targets, l_throttle_type)); + + for ( const auto& l_ocmb : i_targets) + { + //Set runtime throttles to worst case between ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_SLOT + //and ATTR_EXP_MEM_RUNTIME_THROTTLED_N_COMMANDS_PER_SLOT and the _PORT equivalents also + FAPI_TRY( mss::power_thermal::update_runtime_throttle(l_ocmb), "Error in exp_mss_eff_config_thermal for %d", + mss::c_str(l_ocmb)); + } + } + + //Done + FAPI_INF( "End exp_mss_eff_config_thermal"); + + fapi_try_exit: + return fapi2::current_err; + } + +} //extern C diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.H new file mode 100644 index 000000000..bcc43f565 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.H @@ -0,0 +1,55 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_eff_config_thermal.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_eff_config_thermal.H +/// @brief The explorer thermal/power config +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: Memory +#ifndef EXP_MSS_EFF_CONFIG_THERMAL_H_ +#define EXP_MSS_EFF_CONFIG_THERMAL_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*exp_mss_eff_config_thermal_FP_t) (const + std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >&); + +extern "C" +{ + + /// + /// @brief Config the thermal/power throttle setting + /// @param[in] i_target vector of OCMB chip + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_mss_eff_config_thermal( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& + i_targets); +} + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.C new file mode 100644 index 000000000..f2452efdd --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.C @@ -0,0 +1,71 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_memdiag.C +/// @brief HW Procedure pattern testing +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <exp_mss_memdiag.H> +#include <lib/shared/exp_defaults.H> + +#include <lib/dimm/exp_rank.H> +#include <lib/mc/exp_port.H> +#include <lib/mcbist/exp_memdiags.H> +#include <lib/mcbist/exp_mcbist_traits.H> + +extern "C" +{ + /// + /// @brief Initializes memory and sets firs + /// @param[in] i_target OCMB Chip + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_mss_memdiag( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) + { + uint8_t l_post_memdiags_subtest = 0; + + FAPI_INF("Start exp_mss_memdiag on: %s", mss::c_str( i_target )); + FAPI_TRY(mss::memdiags::mss_initialize_memory(i_target)); + + FAPI_TRY(mss::attr::get_post_memdiags_read_subtest(i_target, l_post_memdiags_subtest)); + + // Perform subtest if attribute is set to + if (l_post_memdiags_subtest == fapi2::ENUM_ATTR_MSS_POST_MEMDIAGS_READ_SUBTEST_ENABLE) + { + FAPI_TRY(mss::exp::memdiags::perform_read_only_subtest(i_target)); + } + + fapi_try_exit: + FAPI_INF("End exp_mss_memdiag on %s", mss::c_str( i_target )); + return fapi2::current_err; + } +} diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.H index 5e8291a21..6650f2292 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.H $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,42 +23,30 @@ /* */ /* IBM_PROLOG_END_TAG */ +/// @file exp_mss_memdiag.H +/// @brief Mainstore pattern testing /// -/// @file mcbist/sim.H -/// @brief MCBIST/memdiags functions for when we're in simulation mode -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#ifndef _MSS_MCBIST_SIM_H_ -#define _MSS_MCBIST_SIM_H_ +#ifndef __EXP_MSS_MEMDIAG__ +#define __EXP_MSS_MEMDIAG__ #include <fapi2.H> -namespace mss -{ - -namespace mcbist -{ +typedef fapi2::ReturnCode (*exp_mss_memdiag_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); -namespace sim +extern "C" { - /// -/// @brief Perform a sim version of initializing memory -/// @param T a fapi2::TargetType -/// @param[in] i_target -/// @param[in] i_pattern an index representing a pattern to use to initize memory (defaults to 0) +/// @brief Pattern test the DRAM +/// @param[in] i_target the memory controller of the dram you're training /// @return FAPI2_RC_SUCCESS iff ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode sf_init( const fapi2::Target<T>& i_target, const uint64_t i_pattern ); + fapi2::ReturnCode exp_mss_memdiag( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ); +} -} // ns sim -} // ns mcbist -} // ns mss #endif - diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.mk index 07adb9c70..32649e24e 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.mk @@ -1,11 +1,11 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config_thermal.mk $ +# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_memdiag.mk $ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # @@ -24,8 +24,8 @@ # IBM_PROLOG_END_TAG # Include the macros and things for MSS procedures --include 00p9a_common.mk +-include 00exp_common.mk -PROCEDURE=p9a_mss_eff_config_thermal -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +PROCEDURE=exp_mss_memdiag +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.C new file mode 100644 index 000000000..d52ac1ba6 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.C @@ -0,0 +1,90 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_thermal_init.C +/// @brief Procedure definition to initialize thermal sensor +/// +// *HWP HWP Owner: Sharath Manjunath <shamanj4@in.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <generic/memory/lib/utils/find.H> +#include <lib/exp_mss_thermal_init_utils.H> +#include <lib/inband/exp_inband.H> +#include <exp_mss_thermal_init.H> + +extern "C" +{ + +/// +/// @brief Initializes thermal sensor +/// @param[in] i_target the controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode exp_mss_thermal_init( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) + { + FAPI_INF("%s Start thermal_init", mss::c_str(i_target)); + +#if 0 +// Skip EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ until it's available in Explorer FW + // Declare variables + host_fw_command_struct l_cmd_sensor; + host_fw_response_struct l_response; + std::vector<uint8_t> l_rsp_data; + + // Sets up EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ cmd params + mss::exp::setup_sensor_interval_read_cmd_params(l_cmd_sensor); + + // Enable sensors + FAPI_TRY( mss::exp::ib::putCMD(i_target, l_cmd_sensor), + "Failed putCMD() for %s", mss::c_str(i_target) ); + + FAPI_TRY( mss::exp::ib::getRSP(i_target, l_response, l_rsp_data), + "Failed getRSP() for %s", mss::c_str(i_target) ); + + FAPI_TRY( mss::exp::check::sensor_response(i_target, l_response), + "Failed sensor_response() for %s", mss::c_str(i_target) ); +#endif + +#ifdef __HOSTBOOT_MODULE + // Prior to starting OCC, we go into "safemode" throttling + // After OCC is started, they can change throttles however they want + // We don't want to do this in Cronus mode + FAPI_TRY (mss::exp::mc::setup_emergency_throttles(i_target)); +#endif + // Clear the emergency mode throttle bit + FAPI_TRY (mss::exp::mc::disable_safe_mode_throttles(i_target)); + + FAPI_INF("%s End thermal_init", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: + FAPI_ERR("%s Error executing thermal_init", mss::c_str(i_target)); + return fapi2::current_err; + } +} //extern C diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.H new file mode 100644 index 000000000..9ed3d1213 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_thermal_init.H +/// @brief Procedure declaration to initialize thermal sensor +/// +// *HWP HWP Owner: Sharath Manjunath <shamanj4@in.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_EXP_THERMAL_INIT__ +#define __MSS_EXP_THERMAL_INIT__ + +#include <fapi2.H> +#include <lib/exp_mss_thermal_init_utils.H> + +typedef fapi2::ReturnCode (*exp_mss_thermal_init_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ +/// +/// @brief Initializes thermal sensor +/// @param[in] i_target the controller target (MCS) +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode exp_mss_thermal_init( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ); +} +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.mk new file mode 100644 index 000000000..270920f4f --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.mk @@ -0,0 +1,31 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_mss_thermal_init.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2018,2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# Include the macros and things for MSS EXP procedures +-include 00exp_common.mk + +PROCEDURE=exp_mss_thermal_init +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.C index 27b9f403a..40c253590 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,10 +34,13 @@ #include <exp_omi_init.H> #include <exp_oc_regs.H> -#include <exp_inband.H> +#include <lib/inband/exp_inband.H> #include <chips/common/utils/chipids.H> #include <mss_explorer_attribute_getters.H> #include <mss_p9a_attribute_getters.H> +#include <generic/memory/mss_git_data_helper.H> +#include <lib/workarounds/exp_omi_workarounds.H> +#include <generic/memory/lib/utils/find.H> /// /// @brief Verify we know how to talk to the connected device @@ -55,6 +58,7 @@ fapi2::ReturnCode omiDeviceVerify(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CH FAPI_ASSERT(l_data == ((POWER_OCID::EXPLORER << 16) | (POWER_OCID::VENDOR_IBM)), fapi2::OCMB_IS_NOT_EXPLORER() + .set_OCMB_TARGET(i_target) .set_TARGET(i_target) .set_ID(l_data), "Explorer ID was not found"); @@ -507,6 +511,42 @@ fapi2::ReturnCode omiSetACTagPASIDMetaData(const fapi2::Target<fapi2::TARGET_TYP l_meta_data_ena, "Metadata requested but not supported", l_meta_data_ena)); + // If we plan on enabling metadata, make sure either upstream templates 5 or 9 are enabled + if (l_meta_data_ena) + { + uint8_t l_enable_template_5 = 0; + uint8_t l_enable_template_9 = 0; + uint8_t l_enable_template_4 = 0; + + const auto& l_mcc = mss::find_target<fapi2::TARGET_TYPE_MCC>(i_target); + + FAPI_TRY(mss::attr::get_explr_enable_us_tmpl_5(i_target, l_enable_template_5)); + FAPI_TRY(mss::attr::get_explr_enable_us_tmpl_9(i_target, l_enable_template_9)); + + FAPI_ASSERT((l_enable_template_5 == fapi2::ENUM_ATTR_EXPLR_ENABLE_US_TMPL_5_ENABLED) || + (l_enable_template_9 == fapi2::ENUM_ATTR_EXPLR_ENABLE_US_TMPL_9_ENABLED), + fapi2::METADATA_ENABLE_REQUIRES_TEMPLATE_5_OR_9() + .set_TARGET(i_target) + .set_TMPL_5(l_enable_template_5) + .set_TMPL_9(l_enable_template_9), + "%s METADATA_ENABLE requires upstream template either 5 or 9 to be set. " + "TMPL_5: %u TMPL_9: %u", + mss::c_str(i_target), + l_enable_template_5, + l_enable_template_9) + + // Check for downstream template 4 as well. We won't bomb out here, just have an error printout if not enabled + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_4, l_mcc, l_enable_template_4), + "Error from FAPI_ATTR_GET (ATTR_PROC_ENABLE_DL_TMPL_4)"); + + if (l_enable_template_4 != fapi2::ENUM_ATTR_PROC_ENABLE_DL_TMPL_4_ENABLED) + { + FAPI_ERR("%s Expected MCC %s TMPL_4 to be enabled for metadata enabling. Was not enabled: may be incorrectly configured", + mss::c_str(i_target), + mss::c_str(l_mcc)); + } + } + l_value.insertFromRight<EXPLR_OC_OCTRLPID_MSB_METADATA_ENABLED, EXPLR_OC_OCTRLPID_MSB_METADATA_ENABLED_LEN> (l_meta_data_ena); @@ -602,7 +642,10 @@ fapi_try_exit: /// fapi2::ReturnCode exp_omi_init(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { + mss::display_git_commit_info("exp_omi_init"); + FAPI_DBG("Start"); + FAPI_TRY(mss::exp::workarounds::omi::gem_setup_config(i_target)); FAPI_TRY(omiDeviceVerify(i_target)); FAPI_TRY(omiSetUpstreamTemplates(i_target)); FAPI_TRY(omiValidateDownstream(i_target)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.mk index 7458548da..ff0e0a5ff 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_init.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -25,8 +25,6 @@ # Makefile for exp_omi_init HWP PROCEDURE=exp_omi_init $(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) -lib$(PROCEDURE)_DEPLIBS+=mss_generic -lib$(PROCEDURE)_DEPLIBS+=exp_inband $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/common/include) $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/common/inband) $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9/procedures/hwp/nest) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C index e17271c93..ac783f35b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_setup.C @@ -34,9 +34,16 @@ // *HWP Consumed by: Memory #include <fapi2.H> +#include <exp_omi_setup.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/exp_attribute_accessors_manual.H> #include <lib/omi/exp_omi_utils.H> +#include <lib/workarounds/exp_omi_workarounds.H> +#include <lib/i2c/exp_i2c.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_system_attribute_getters.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> extern "C" { @@ -48,29 +55,79 @@ extern "C" /// fapi2::ReturnCode exp_omi_setup( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { + mss::display_git_commit_info("exp_omi_setup"); + uint8_t l_gem_menterp_workaround = 0; + // Declares variables - fapi2::buffer<uint64_t> l_data; - bool l_is_enterprise = false; - bool l_is_half_dimm = false; + std::vector<uint8_t> l_boot_config_data; + + // BOOT CONFIG 0 + uint8_t l_dl_layer_boot_mode = fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_DL_LAYER_BOOT_MODE_NON_DL_TRAINING; + + // Gets the data setup + FAPI_TRY(mss::exp::omi::train::setup_fw_boot_config(i_target, l_boot_config_data)); + + // Sanity check: set dl_layer_boot_mode to NON DL TRAINING (0b00 == default) + FAPI_TRY(mss::exp::i2c::boot_cfg::set_dl_layer_boot_mode( i_target, l_boot_config_data, l_dl_layer_boot_mode )); + + // Issues the command and checks for completion + // Note: This does not kick off OMI training + FAPI_TRY(mss::exp::i2c::boot_config(i_target, l_boot_config_data)); + + // Check FW status for success + FAPI_TRY(mss::exp::i2c::fw_status(i_target, mss::DELAY_1MS, 100)); + + FAPI_TRY(mss::exp::workarounds::omi::gem_menterp(i_target, l_gem_menterp_workaround)); + + // If no workaround (explorer), we can perform menterp reads/writes + // If workaround (gemini). we need to bypass menterp. Can also bypass dlx_config1 too since it's a noop + if (l_gem_menterp_workaround) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + // Set up DLX_CONFIG1 + { + fapi2::buffer<uint64_t> l_data; + fapi2::buffer<uint64_t> l_dlx_config1_data; + + uint8_t l_edpl_disable = 0; + uint8_t l_enterprise_attr = 0; + bool l_is_half_dimm = false; + bool l_is_enterprise = false; + + // Gets the configuration information from attributes + FAPI_TRY(mss::attr::get_ocmb_enterprise_mode(i_target, l_enterprise_attr)); + l_is_enterprise = (l_enterprise_attr == fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_MODE_ENTERPRISE); + + FAPI_TRY(mss::half_dimm_mode(i_target, l_is_enterprise, l_is_half_dimm)); + FAPI_TRY(mss::attr::get_mss_omi_edpl_disable(l_edpl_disable)); + + // Prints out the data + FAPI_INF("%s is %s enterprise mode, and %s-DIMM mode", mss::c_str(i_target), l_is_enterprise ? "" : "non", + l_is_half_dimm ? "half" : "full"); - // Gets the configuration information from attributes - FAPI_TRY(mss::enterprise_mode(i_target, l_is_enterprise)); - FAPI_TRY(mss::half_dimm_mode(i_target, l_is_half_dimm)); + // Sets up the register + mss::exp::omi::set_enterprise_set_bit(l_data, l_is_enterprise); + mss::exp::omi::set_half_dimm_mode(l_data, l_is_half_dimm); - // Prints out the data - FAPI_INF("%s %s enterprise mode %s-DIMM mode", mss::c_str(i_target), l_is_enterprise ? "is" : "isn't", - l_is_half_dimm ? "half" : "full"); + // Writes the data to the register + FAPI_TRY(mss::exp::omi::write_enterprise_config(i_target, l_data)); - // Sets up the register - mss::exp::omi::set_enterprise_set_bit(l_data, l_is_enterprise); - mss::exp::omi::set_half_dimm_mode(l_data, l_is_half_dimm); + // Checks that the chip is configured correctly + FAPI_TRY(mss::exp::omi::read_enterprise_config(i_target, l_data)); + FAPI_TRY(mss::exp::omi::check_enterprise_mode(i_target, l_is_enterprise, l_data)); - // Writes the data to the register - FAPI_TRY(mss::exp::omi::write_enterprise_config(i_target, l_data)); + // Set the EDPL according the attribute + FAPI_TRY(mss::exp::omi::read_dlx_config1(i_target, l_dlx_config1_data)); + mss::exp::omi::set_edpl_enable_bit(l_dlx_config1_data, !l_edpl_disable); + FAPI_TRY(mss::exp::omi::write_dlx_config1(i_target, l_dlx_config1_data)); + FAPI_INF("%s EDPL enable: %s", mss::c_str(i_target), l_edpl_disable ? "false" : "true"); + } - // Checks that the chip is configured correctly - FAPI_TRY(mss::exp::omi::read_enterprise_config(i_target, l_data)); - FAPI_TRY(mss::exp::omi::check_enterprise_mode(i_target, l_is_enterprise, l_data)); + // Perform p9a workaround + // Train mode 6 (state 3) + FAPI_TRY(mss::exp::workarounds::omi::pre_training_prbs(i_target)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train.C index 2865af091..0e21e87ef 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,12 @@ #include <generic/memory/lib/utils/c_str.H> #include <lib/omi/exp_omi_utils.H> #include <lib/i2c/exp_i2c.H> +#include <lib/exp_attribute_accessors_manual.H> +#include <lib/workarounds/exp_omi_workarounds.H> #include <exp_omi_train.H> +#include <generic/memory/mss_git_data_helper.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> extern "C" { @@ -49,14 +54,43 @@ extern "C" /// fapi2::ReturnCode exp_omi_train(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { - std::vector<uint8_t> l_data; + mss::display_git_commit_info("exp_omi_train"); - // Gets the data setup - FAPI_TRY(mss::exp::omi::train::setup_fw_boot_config(i_target, l_data)); + // Perform p9a workaround + // Train mode 1 (PATTERN_A) + FAPI_TRY(mss::exp::workarounds::omi::training_prbs(i_target)); - // Issues the command and checks for completion - // Note: the status check also checks for the OMI training completion, so after we run this command, we're good to go - FAPI_TRY(mss::exp::i2c::boot_config(i_target, l_data)); + // BOOT CONFIG 1 + { + bool l_ocmb_is_explorer = false; + + std::vector<uint8_t> l_data; + uint8_t l_dl_layer_boot_mode = fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_DL_LAYER_BOOT_MODE_ONLY_DL_TRAINING; + + // Gets the data setup + FAPI_TRY(mss::exp::omi::train::setup_fw_boot_config(i_target, l_data)); + + // Sets DL_TRAIN field + FAPI_TRY(mss::exp::i2c::boot_cfg::set_dl_layer_boot_mode( i_target, l_data, l_dl_layer_boot_mode )); + + // Issues the command and checks for completion + FAPI_TRY(mss::exp::i2c::boot_config(i_target, l_data)); + + // Check for expected busy status (this won't work for gemini) + FAPI_TRY(mss::exp::workarounds::omi::ocmb_is_explorer(i_target, l_ocmb_is_explorer)); + + if (l_ocmb_is_explorer) + { + // Explorer & P9A environment should see a busy status until auto train is kicked off from both sides + FAPI_TRY(mss::exp::i2c::check_fw_status_busy(i_target)); + } + else + { + // Gemini should return success code + FAPI_TRY(mss::exp::i2c::fw_status(i_target, mss::DELAY_1MS, 100)); + } + + } fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.C new file mode 100644 index 000000000..08b4247bf --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.C @@ -0,0 +1,141 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file exp_omi_train_check.C +/// @brief Check that omi training was successful from explorer side +/// +/// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +/// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 2 +/// *HWP Consumed by: HB + +#include <fapi2.H> +#include <exp_omi_train_check.H> +#include <lib/omi/exp_omi_utils.H> +#include <generic/memory/mss_git_data_helper.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/find.H> +#include <lib/i2c/exp_i2c.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> + +/// +/// @brief Check that the OCMB's omi state machine is in its expected state after OMI training +/// @param[in] i_target the OCMB target to check +/// @return FAPI2_RC_SUCCESS iff ok +/// @note the functionality of this procedure was made to match that of p9a_omi_train_check +/// +fapi2::ReturnCode exp_omi_train_check(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + mss::display_git_commit_info("exp_omi_train_check"); + + FAPI_INF("%s Start exp_omi_train_check", mss::c_str(i_target)); + + // Const + constexpr uint8_t STATE_MACHINE_SUCCESS = 0b111; // This value is from Lonny Lambrecht + constexpr uint8_t MAX_LOOP_COUNT = 10; // Retry times + const auto& l_omi = mss::find_target<fapi2::TARGET_TYPE_OMI>(i_target); + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); + + // Declares variables + fapi2::buffer<uint64_t> l_omi_status; + fapi2::buffer<uint64_t> l_omi_training_status; + fapi2::buffer<uint64_t> l_dl0_error_hold; + fapi2::buffer<uint64_t> l_expected_dl0_error_hold; + fapi2::buffer<uint64_t> l_dl0_config1; + uint8_t l_state_machine_state = 0; + uint8_t l_tries = 0; + uint32_t l_omi_freq = 0; + + do + { + // Delay + fapi2::delay(500 * mss::DELAY_1MS, 10 * mss::DELAY_1MS); + + // Check OMI training status + FAPI_TRY(mss::exp::omi::train::omi_train_status(i_target, l_state_machine_state, l_omi_status)); + l_tries++; + + } + while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS); + + // Note: this is very useful debug information while trying to debug training during polling + FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_TRAINING_STATUS, l_omi_training_status)); + FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_CONFIG1, l_dl0_config1)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_OMI_MHZ, l_proc, l_omi_freq)); + + + FAPI_ASSERT(l_state_machine_state == STATE_MACHINE_SUCCESS, + fapi2::EXP_OMI_TRAIN_ERR() + .set_OCMB_TARGET(i_target) + .set_OMI_TARGET(l_omi) + .set_EXPECTED_SM_STATE(STATE_MACHINE_SUCCESS) + .set_ACTUAL_SM_STATE(l_state_machine_state) + .set_DL0_STATUS(l_omi_status) + .set_DL0_TRAINING_STATUS(l_omi_training_status) + .set_DL0_CONFIG1(l_dl0_config1) + .set_OMI_FREQ(l_omi_freq), + "%s EXP OMI Training Failure, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", + mss::c_str(i_target), + STATE_MACHINE_SUCCESS, + l_state_machine_state, + l_omi_status, + l_omi_training_status + ); + + // Finally, make sure fw_status is good + FAPI_TRY(mss::exp::i2c::fw_status(i_target, mss::common_timings::DELAY_1MS, 100)); + + // Check for errors in ERROR_HOLD until we get a proper FIR API setup + FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_ERROR_HOLD, l_dl0_error_hold)); + + // Training done bit + l_expected_dl0_error_hold.setBit<EXPLR_DLX_DL0_ERROR_HOLD_CERR_39>(); + + if (l_dl0_error_hold != l_expected_dl0_error_hold) + { + // To get to this point, we had to have completed training, so these errors are not catastrophic + // We don't need to assert out, but let's make sure we print them out + FAPI_INF("%s EXPLR_DLX_DL0_ERROR_HOLD REG 0x%016llx " + "did not match expected value. REG contents: 0x%016llx Expected: 0x%016llx", + mss::c_str(i_target), + EXPLR_DLX_DL0_ERROR_HOLD, + l_dl0_error_hold, + l_expected_dl0_error_hold); + } + + FAPI_DBG("%s End exp_omi_train_check, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", + mss::c_str(i_target), + STATE_MACHINE_SUCCESS, + l_state_machine_state, + l_omi_status, + l_omi_training_status); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; + +}// exp_omi_train_check diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.H new file mode 100644 index 000000000..0adb51ce9 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// @file exp_omi_train_check.C +/// @brief Check that omi training was successful from explorer side +/// +/// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +/// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +/// *HWP Team: Memory +/// *HWP Level: 2 +/// *HWP Consumed by: HB + +#ifndef _EXP_OMI_TRAIN_CHECK_H_ +#define _EXP_OMI_TRAIN_CHECK_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*exp_omi_train_check_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ + + /// + /// @brief Check that the OCMB's omi state machine is in its expected state after OMI training + /// @param[in] i_target the OCMB target to check + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_omi_train_check(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); +} + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.mk index 22abeb618..93566fadd 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.mk @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.mk $ +# $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_omi_train_check.mk $ # # OpenPOWER HostBoot Project # @@ -22,3 +22,8 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +-include 00exp_common.mk + +PROCEDURE=exp_omi_train_check +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scominit.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scominit.C index 3c6767a94..e3e01d788 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scominit.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scominit.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,6 +38,7 @@ #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/find.H> #include <explorer_scom.H> +#include <generic/memory/mss_git_data_helper.H> extern "C" { @@ -49,6 +50,8 @@ extern "C" /// fapi2::ReturnCode exp_scominit( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) { + mss::display_git_commit_info("exp_scominit"); + if (mss::count_dimm(i_target) == 0) { FAPI_INF("... skipping mss_scominit %s - no DIMM ...", mss::c_str(i_target)); diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.C index 6f6ee8caf..ca588d8d2 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,41 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_scrub.C +/// @brief Begin background scrub +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <lib/shared/exp_defaults.H> +#include <exp_scrub.H> +#include <lib/utils/mss_exp_conversions.H> +#include <lib/mcbist/exp_memdiags.H> + +extern "C" +{ + + /// + /// @brief Begin background scrub + /// @param[in] i_target OCMB chip + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_scrub(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) + { + FAPI_INF("Start exp scrub for %s", mss::c_str(i_target)); + // Initialize memory and set firs accordingly + FAPI_TRY(mss::memdiags::mss_initialize_memory(i_target)); + // Kickoff background scrub and unmask firs + FAPI_TRY(mss::memdiags::mss_background_scrub_helper(i_target)); + + fapi_try_exit: + FAPI_INF("End exp scrub for %s", mss::c_str(i_target)); + return fapi2::current_err; + } + +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.H index d3e650254..73affcb60 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.H @@ -22,3 +22,34 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_scrub.H +/// @brief Procedure declaration to begin background scrub +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_EXP_SCRUB__ +#define __MSS_EXP_SCRUB__ + +#include <fapi2.H> + +// Required for Cronus +typedef fapi2::ReturnCode (*exp_scrub_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ + + /// + /// @brief Begin background scrub + /// @param[in] i_target the controller + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode exp_scrub(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +}// extern C +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.mk b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.mk index ef1c8a17d..9067611e3 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.mk +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_scrub.mk @@ -22,3 +22,10 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + +# Include the macros and things for MSS EXP procedures +-include 00exp_common.mk + +PROCEDURE=exp_scrub +$(eval $(call ADD_EXP_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C new file mode 100644 index 000000000..26855282e --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C @@ -0,0 +1,166 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_explorer.C +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> + +#include <lib/shared/exp_defaults.H> +#include <lib/ccs/ccs_traits_explorer.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/ccs/ccs_explorer.H> +#include <lib/utils/mss_exp_conversions.H> + +// Generates linkage +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_N[]; +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::EXPLORER>::CS_ND[]; + +namespace mss +{ +namespace ccs +{ + +/// +/// @brief Cleans up from a CCS execution - multiple ports - EXPLORER specialization +/// @param[in] i_program the vector of instructions +/// @param[in] i_ports the vector of ports +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode cleanup_from_execute<fapi2::TARGET_TYPE_MEM_PORT, mss::mc_type::EXPLORER> +(const ccs::program& i_program, + const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& i_ports) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Determine the CCS failure type +/// @param[in] i_target OCMB target +/// @param[in] i_type the failure type +/// @param[in] i_port The port the CCS instruction is training +/// @return ReturnCode associated with the fail. +/// @note FFDC is handled here, caller doesn't need to do it +/// +template<> +fapi2::ReturnCode fail_type( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_type, + const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port ) +{ + typedef ccsTraits<mss::mc_type::EXPLORER> TT; + + // Including the PORT_TARGET here and below at CAL_TIMEOUT since these problems likely lie at the MCA level + // So we disable the PORT and hopefully that's it + // If the problem lies with the MCBIST, it'll just have to loop + FAPI_ASSERT(TT::STAT_READ_MISCOMPARE != i_type, + fapi2::MSS_EXP_CCS_READ_MISCOMPARE() + .set_MC_TARGET(i_target) + .set_FAIL_TYPE(i_type) + .set_PORT_TARGET(i_port), + "%s CCS FAIL Read Miscompare", mss::c_str(i_port)); + + // This error is likely due to a bad CCS engine/ MCBIST + FAPI_ASSERT(TT::STAT_UE_SUE != i_type, + fapi2::MSS_EXP_CCS_UE_SUE() + .set_FAIL_TYPE(i_type) + .set_MC_TARGET(i_target), + "%s CCS FAIL UE or SUE Error", mss::c_str(i_target)); + + // Problem with the CCS engine + FAPI_ASSERT(TT::STAT_HUNG != i_type, + fapi2::MSS_EXP_CCS_HUNG().set_MC_TARGET(i_target), + "%s CCS appears hung", mss::c_str(i_target)); +fapi_try_exit: + // Due to the PRD update, we need to check for FIR's + // If any FIR's have lit up, this CCS fail could have been caused by the FIR + // So, let PRD retrigger this step to see if we can resolve the issue + return mss::check::fir_or_pll_fail<mss::mc_type::EXPLORER>(i_target, fapi2::current_err); +} + +/// +/// @brief EXP specialization for modeq_copy_cke_to_spare_cke +/// @param[in] fapi2::Target<TARGET_TYPE_OCMB_CHIP>& the target to effect +/// @param[in,out] the buffer representing the mode register +/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports +/// @note no-op for p9n +/// +template<> +void copy_cke_to_spare_cke<fapi2::TARGET_TYPE_OCMB_CHIP>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&, + fapi2::buffer<uint64_t>&, states ) +{ + return; +} + +/// +/// @brief Updates the initial delays based upon the total delays passed in - EXP specialization +/// @param[in] i_target the target type on which to operate +/// @param[in] i_delay the calculated delays from CCS +/// @param[in,out] io_program the program for which to update the delays +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode update_initial_delays<fapi2::TARGET_TYPE_OCMB_CHIP, mss::mc_type::EXPLORER> +( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_delay, + ccs::program& io_program) +{ + // Check our program for any delays. If there isn't a iv_initial_delay configured, then + // we use the delay we just summed from the instructions. + if (io_program.iv_poll.iv_initial_delay == 0) + { + io_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, i_delay); + } + + if (io_program.iv_poll.iv_initial_sim_delay == 0) + { + io_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(i_delay); + } + + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Select the port(s) to be used by the CCS - EXPLORER specialization +/// @param[in] i_target the target to effect +/// @param[in] i_ports the buffer representing the ports +/// +template<> +fapi2::ReturnCode select_ports<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint64_t i_ports) +{ + // No broadcast mode, only one port, so no port selection + return fapi2::FAPI2_RC_SUCCESS; +} + +} // namespace ccs +} // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H index 051aa214b..e02292508 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/utils/num.H $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_explorer.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,32 +24,30 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file num.H -/// @brief Miscellaneous number checking functions +/// @file ccs_explorer.H +/// @brief Run and manage the CCS engine /// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 -// *HWP Consumed by: HB:FSP +// *HWP Consumed by: FSP:HB -#ifndef _MSS_NUM_H_ -#define _MSS_NUM_H_ +#ifndef _MSS_CCS_EXPLORER_H_ +#define _MSS_CCS_EXPLORER_H_ + +#include <fapi2.H> +#include <lib/ccs/ccs_traits_explorer.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { - -/// -/// @brief Return whether or not a number is odd -/// @param[in] i_number the number to check -/// @return true if i_number is odd -/// -template< typename T > -constexpr bool is_odd(const T i_number) +namespace ccs { - return (i_number & 0x1); -} +// This file ties the two needed header files together + +} // namespace ccs +} // namespace mss -} #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H new file mode 100644 index 000000000..3411a677c --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H @@ -0,0 +1,260 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ccs/ccs_traits_explorer.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_traits_nimbus.H +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_CCS_TRAITS_EXP_H_ +#define _MSS_CCS_TRAITS_EXP_H_ + +#include <fapi2.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/ccs/ccs_traits.H> + +/// +/// @class ccsTraits +/// @brief Explorer CCS Engine traits +/// +template<> +class ccsTraits<mss::mc_type::EXPLORER> +{ + public: + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + static constexpr uint64_t MODEQ_REG = EXPLR_MCBIST_CCS_MODEQ; + static constexpr uint64_t MCB_CNTL_REG = EXPLR_MCBIST_MCB_CNTLQ; + static constexpr uint64_t CNTLQ_REG = EXPLR_MCBIST_CCS_CNTLQ; + static constexpr uint64_t STATQ_REG = EXPLR_MCBIST_CCS_STATQ; + + static constexpr uint64_t PORTS_PER_MC_TARGET = mss::exp::MAX_PORT_PER_OCMB; + static constexpr uint64_t CCS_MAX_DIMM_PER_PORT = mss::exp::MAX_DIMM_PER_PORT; + static constexpr uint64_t CCS_MAX_MRANK_PER_PORT = mss::exp::MAX_MRANK_PER_PORT; + static constexpr uint64_t CCS_MAX_RANK_PER_DIMM = mss::exp::MAX_RANK_PER_DIMM; + static constexpr uint64_t CCS_MAX_RANKS_DIMM1 = mss::exp::MAX_RANKS_DIMM1; + + static constexpr uint64_t NTTM_READ_DELAY = 0x40; + static constexpr uint64_t NTTM_MODE_FORCE_READ = 33; + + + // Command Pass Disable Delay Time for Explorer - really a JEDEC timing + static constexpr uint64_t TIMING_TCPDED = 4; + + enum + { + // Non address values that are needed for helper functions + + // ODT values used for beautification + // Attribute locations + ATTR_ODT_DIMM0_R0 = 0, + ATTR_ODT_DIMM0_R1 = 1, + ATTR_ODT_DIMM1_R0 = 4, + ATTR_ODT_DIMM1_R1 = 5, + + // Right justified output - makes it so we can use insertFromRight + CCS_ODT_DIMM0_R0 = 4, + CCS_ODT_DIMM0_R1 = 5, + CCS_ODT_DIMM1_R0 = 6, + CCS_ODT_DIMM1_R1 = 7, + + // Default ODT cycle length is 5 - one for the preamble and 4 for the data + DEFAULT_ODT_CYCLE_LEN = 5, + + // CCS MODEQ + STOP_ON_ERR = EXPLR_MCBIST_CCS_MODEQ_STOP_ON_ERR, + UE_DISABLE = EXPLR_MCBIST_CCS_MODEQ_UE_DISABLE, + DATA_COMPARE_BURST_SEL = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL, + DATA_COMPARE_BURST_SEL_LEN = EXPLR_MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN, + CFG_PARITY_AFTER_CMD = EXPLR_MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD, + COPY_CKE_TO_SPARE_CKE = EXPLR_MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE, + DISABLE_ECC_ARRAY_CHK = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK, + DISABLE_ECC_ARRAY_CORRECTION = EXPLR_MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION, + CFG_DGEN_FIXED_MODE = EXPLR_MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE, + IDLE_PAT_ADDRESS_0_13 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13, + IDLE_PAT_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN, + IDLE_PAT_ADDRESS_17 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17, + IDLE_PAT_BANK_GROUP_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1, + IDLE_PAT_BANK_0_1 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1, + IDLE_PAT_BANK_0_1_LEN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN, + IDLE_PAT_BANK_GROUP_0 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0, + IDLE_PAT_ACTN = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ACTN, + IDLE_PAT_ADDRESS_16 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16, + IDLE_PAT_ADDRESS_15 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15, + IDLE_PAT_ADDRESS_14 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14, + NTTM_MODE = EXPLR_MCBIST_CCS_MODEQ_NTTM_MODE, + NTTM_RW_DATA_DLY = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY, + NTTM_RW_DATA_DLY_LEN = EXPLR_MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN, + IDLE_PAT_BANK_2 = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2, + DDR_PARITY_ENABLE = EXPLR_MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, + IDLE_PAT_PARITY = EXPLR_MCBIST_CCS_MODEQ_IDLE_PAT_PARITY, + + // CCS CNTL + CCS_START = EXPLR_MCBIST_CCS_CNTLQ_START, + CCS_STOP = EXPLR_MCBIST_CCS_CNTLQ_STOP, + + // CCS STATQ + CCS_IN_PROGRESS = EXPLR_MCBIST_CCS_STATQ_IP, + + // ARR0 + ARR0_DDR_ADDRESS_0_13 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, + ARR0_DDR_ADDRESS_0_13_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN, + ARR0_DDR_ADDRESS_0_9 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, // Useful for rd/wr cmds + ARR0_DDR_ADDRESS_0_9_LEN = 10, // CA bits are 9:0, total length of 10 + ARR0_DDR_ADDRESS_10 = 10, // ADR10 is the 10th bit from the left in Nimbus ARR0 + ARR0_DDR_ADDRESS_17 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17, + ARR0_DDR_BANK_GROUP_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1, + ARR0_DDR_RESETN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_RESETN, + ARR0_DDR_BANK_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1, + ARR0_DDR_BANK_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN, + ARR0_DDR_BANK_GROUP_0 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0, + ARR0_DDR_ACTN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ACTN, + ARR0_DDR_ADDRESS_16 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16, + ARR0_DDR_ADDRESS_15 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15, + ARR0_DDR_ADDRESS_14 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14, + ARR0_DDR_CKE = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE, + ARR0_DDR_CKE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN, + ARR0_DDR_CSN_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1, + ARR0_DDR_CSN_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN, + ARR0_DDR_CID_0_1 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1, + ARR0_DDR_CID_0_1_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN, + ARR0_DDR_CSN_2_3 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3, + ARR0_DDR_CSN_2_3_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN, + ARR0_DDR_CID_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_CID_2, + ARR0_DDR_ODT = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT, + ARR0_DDR_ODT_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN, + ARR0_DDR_PARITY = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_PARITY, + ARR0_DDR_BANK_2 = EXPLR_MCBIST_CCS_INST_ARR0_00_DDR_BANK_2, + ARR0_LOOP_BREAK_MODE = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE, + ARR0_LOOP_BREAK_MODE_LEN = EXPLR_MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN, + + // ARR1 + ARR1_IDLES = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES, + ARR1_IDLES_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_IDLES_LEN, + ARR1_REPEAT_CMD_CNT = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, + ARR1_REPEAT_CMD_CNT_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN, + ARR1_READ_OR_WRITE_DATA = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA, + ARR1_READ_OR_WRITE_DATA_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN, + ARR1_READ_COMPARE_REQUIRED = EXPLR_MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED, + ARR1_END = EXPLR_MCBIST_CCS_INST_ARR1_00_END, + ARR1_GOTO_CMD = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD, + ARR1_GOTO_CMD_LEN = EXPLR_MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN, + + // CCS array constants + CCS_ARRAY_LEN = 32, + CCS_ARR0_START = EXPLR_MCBIST_CCS_INST_ARR0_00, + CCS_ARR1_START = EXPLR_MCBIST_CCS_INST_ARR1_00, + }; + + /// + /// @brief Enums for CCS return codes + /// + enum + { + // Success is defined as done-bit set, no others. + STAT_QUERY_SUCCESS = 0x4000000000000000, + + // Bit positions 3:5 + STAT_ERR_MASK = 0x1800000000000000, + STAT_READ_MISCOMPARE = 0x1000000000000000, + STAT_UE_SUE = 0x0800000000000000, + + // If the fail type isn't one of these, we're hung + STAT_HUNG = 0x0ull, + }; + + + // CSN Regular Settings + static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L, CS1 H, CID0-> L => Rank 0 + { 0b01, 0b00 }, + + // CS0 L, CS1 H, CID0-> H => Rank 1 + { 0b01, 0b11 }, + + // CS0 H, CS1 L, CID0-> L => Rank 2 + { 0b10, 0b00 }, + + // CS0 H, CS1 L, CID0-> H => Rank 3 + { 0b10, 0b11 }, + }; + + + // CSN Setup for Dual Direct Mode + // For DIMM0 .first is the CSN_0_1 setting, .second is the CSN_2_3 setting. + // For DIMM1 .first is the CSN_2_3 setting, .second is the CSN_0_1 setting. + static constexpr std::pair<uint64_t, uint64_t> CS_ND[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L CS1 H => CS2 => H CS3 => H Rank 0 + { 0b01, 0b11 }, + + // CS0 H CS1 L => CS2 => H CS3 => H Rank 1 + { 0b10, 0b11 }, + + // CS0 H CS1 H => CS2 => L CS3 => H Rank 2 + { 0b11, 0b01 }, + + // CS0 H CS1 H => CS2 => H CS3 => L Rank 3 + { 0b11, 0b10 }, + }; + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return SUCCESS iff the code executes successfully + /// + static fapi2::ReturnCode get_rank_config_attr(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + uint8_t (&o_array)[2]) + { + return mss::attr::get_num_master_ranks_per_dimm(i_target, o_array); + } + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return The fully setup nimbus error + /// + static fapi2::EXP_CCS_HUNG_TRYING_TO_STOP setup_trying_to_stop_err(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target) + { + return fapi2::EXP_CCS_HUNG_TRYING_TO_STOP().set_MC_TARGET(i_target); + } + + // Lab values + static constexpr uint64_t LAB_MRS_CMD = 0x000008F000000000; +}; + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H index 781389ae3..56dc34b4f 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/dimm/exp_rank.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,127 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_rank.H +/// @brief Explorer rank definitions +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_RANK_H_ +#define _MSS_EXP_RANK_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/mss_rank.H> + +namespace mss +{ +namespace rank +{ + +/// +/// @brief Rank traits for explorer +/// +template <> +class rankTraits<mss::mc_type::EXPLORER> +{ + public: + static constexpr uint8_t MAX_DIMMS_PER_PORT = 2; + static constexpr uint8_t MAX_RANKS_PER_DIMM = 4; + static constexpr uint8_t RANK_INDEX_STEP = 4; + + // Note! a configuration of 2 4-rank dimms is not possible. + // In this hypothetical scenario, the value for phy-rank would not + // be valid / does not apply, as there will be some rollover. + static constexpr uint8_t PHY_RANK_INDEX_STEP = 2; +}; + +/// +/// @brief Return a vector of rank numbers which represent the primary rank pairs for this port +/// @param[in] i_target port target on which to operate +/// @param[out] o_ranks a vector of ranks +/// @return FAPI@_RC_SUCCESS iff all is ok +inline fapi2::ReturnCode primary_ranks( const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + std::vector< uint64_t >& o_rps ) +{ + o_rps.clear(); + std::vector<mss::rank::info<mss::mc_type::EXPLORER>> l_rank_info_vect; + FAPI_TRY(mss::rank::ranks_on_port<mss::mc_type::EXPLORER>(i_target, l_rank_info_vect)); + + // Loop through and assemble the ranks + for(const auto& l_rank_info : l_rank_info_vect) + { + o_rps.push_back(l_rank_info.get_port_rank()); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Return a vector of rank numbers which represent the primary rank pairs for this dimm +/// @param[in] i_target DIMM target on which to operate +/// @param[out] o_ranks a vector of ranks +/// @return FAPI@_RC_SUCCESS iff all is ok +inline fapi2::ReturnCode primary_ranks( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + std::vector< uint64_t >& o_rps ) +{ + o_rps.clear(); + std::vector<mss::rank::info<mss::mc_type::EXPLORER>> l_rank_info_vect; + FAPI_TRY(mss::rank::ranks_on_dimm<mss::mc_type::EXPLORER>(i_target, l_rank_info_vect)); + + // Loop through and assemble the ranks + for(const auto& l_rank_info : l_rank_info_vect) + { + o_rps.push_back(l_rank_info.get_port_rank()); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Return the *port relative position* of the DIMM which posesses this rank +/// @param[in] i_rank the rank number. +/// @return the relative position of the DIMM which contains this rank. +inline size_t get_dimm_from_rank(const uint64_t i_rank) +{ + using TT = rankTraits<mss::mc_type::EXPLORER>; + return i_rank / TT::MAX_RANKS_PER_DIMM; +} + +/// +/// @brief Return a vector of rank numbers which represent the ranks for this dimm +/// @param[in] i_dimm_target TARGET_TYPE_DIMM +/// @param[out] o_ranks a vector of ranks for dimm (numbers) +/// @return FAPI2_RC_SUCCESS iff all is ok +/// +template<> +inline fapi2::ReturnCode ranks_on_dimm_helper<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_dimm_target, + std::vector<uint64_t>& o_ranks) +{ + std::vector<uint64_t> l_ranks; + std::vector<mss::rank::info<>> l_vect; + + FAPI_TRY( mss::rank::ranks_on_dimm<mss::mc_type::EXPLORER>(i_dimm_target, l_vect) ); + + // Loop through and get ranks or each + for (const auto l_rank_info : l_vect) + { + l_ranks.push_back( l_rank_info.get_dimm_rank() ); + } + + o_ranks = l_ranks; + +fapi_try_exit: + return fapi2::current_err; +} + + +} // namespace rank +} // namespace mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.C index f5bb7b342..15bb6a6cd 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.C @@ -22,3 +22,50 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits_explorer.C +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Matthew Hickman<Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <lib/ecc/ecc_traits_explorer.H> + + +namespace mss +{ + +// we need these declarations here in order for the linker to see the definitions +// in the eccTraits class +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::MAINLINE_NCE_REGS[]; +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::MAINLINE_RCE_REGS[]; +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::MAINLINE_MPE_REGS[]; +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::MAINLINE_UE_REGS[]; +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::MAINLINE_AUE_REGS[]; +constexpr const uint64_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::ERROR_VECTOR_REGS[]; +constexpr const uint8_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::symbol2galois[]; +constexpr const uint8_t eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT>::symbol2dq[]; + +// Definition of the symbol error count registers for Explorer +const std::vector< uint64_t > eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>::SYMBOL_COUNT_REG = +{ + EXPLR_MCBIST_MBSSYMEC0Q, + EXPLR_MCBIST_MBSSYMEC1Q, + EXPLR_MCBIST_MBSSYMEC2Q, + EXPLR_MCBIST_MBSSYMEC3Q, + EXPLR_MCBIST_MBSSYMEC4Q, + EXPLR_MCBIST_MBSSYMEC5Q, + EXPLR_MCBIST_MBSSYMEC6Q, + EXPLR_MCBIST_MBSSYMEC7Q, + EXPLR_MCBIST_MBSSYMEC8Q, + EXPLR_MCBIST_MBSSYMEC9Q, +}; + +} // close namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.H index 9eb24ec19..4ffd0f91b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits_explorer.H @@ -22,3 +22,277 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits_explorer.H +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_ECC_TRAITS_EXPLORER_H_ +#define _MSS_ECC_TRAITS_EXPLORER_H_ + +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <explorer_scom_addresses_fixes.H> +#include <explorer_scom_addresses_fld_fixes.H> +#include <generic/memory/lib/ecc/ecc_traits.H> +#include <lib/shared/exp_consts.H> + +namespace mss +{ + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Axone Mem Port ECC interface +/// +template<> +class eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT> +{ + public: + // MCA ECC registers - must be 64 bits. + static constexpr uint64_t HARDWARE_MS0_REG = EXPLR_RDF_HWMS0; + static constexpr uint64_t HARDWARE_MS1_REG = EXPLR_RDF_HWMS1; + static constexpr uint64_t HARDWARE_MS2_REG = EXPLR_RDF_HWMS2; + static constexpr uint64_t HARDWARE_MS3_REG = EXPLR_RDF_HWMS3; + static constexpr uint64_t HARDWARE_MS4_REG = EXPLR_RDF_HWMS4; + static constexpr uint64_t HARDWARE_MS5_REG = EXPLR_RDF_HWMS5; + static constexpr uint64_t HARDWARE_MS6_REG = EXPLR_RDF_HWMS6; + static constexpr uint64_t HARDWARE_MS7_REG = EXPLR_RDF_HWMS7; + static constexpr uint64_t FIRMWARE_MS0_REG = EXPLR_RDF_FWMS0; + static constexpr uint64_t FIRMWARE_MS1_REG = EXPLR_RDF_FWMS1; + static constexpr uint64_t FIRMWARE_MS2_REG = EXPLR_RDF_FWMS2; + static constexpr uint64_t FIRMWARE_MS3_REG = EXPLR_RDF_FWMS3; + static constexpr uint64_t FIRMWARE_MS4_REG = EXPLR_RDF_FWMS4; + static constexpr uint64_t FIRMWARE_MS5_REG = EXPLR_RDF_FWMS5; + static constexpr uint64_t FIRMWARE_MS6_REG = EXPLR_RDF_FWMS6; + static constexpr uint64_t FIRMWARE_MS7_REG = EXPLR_RDF_FWMS7; + static constexpr uint64_t MARK_SHADOW_REG = EXPLR_RDF_MSR; + static constexpr uint64_t ECC_MAX_MRANK_PER_PORT = exp::MAX_MRANK_PER_PORT; + static constexpr uint64_t ECC_MAX_DQ_BITS = exp::MAX_DQ_BITS_PER_PORT; + static constexpr uint64_t ECC_MAX_SYMBOLS = exp::MAX_SYMBOLS_PER_PORT; + + + // MCBIST ECC registers - Register API uses an MEMPORT target instead + // of MCBIST since MEMPORT's relative position is needed to find + // correct reg+field + constexpr static const uint64_t MAINLINE_NCE_REGS[] = + { + EXPLR_MCBIST_MBNCER0Q, + }; + + constexpr static const uint64_t MAINLINE_RCE_REGS[] = + { + EXPLR_MCBIST_MBRCER0Q, + }; + + constexpr static const uint64_t MAINLINE_MPE_REGS[] = + { + EXPLR_MCBIST_MBMPER0Q, + }; + + constexpr static const uint64_t MAINLINE_UE_REGS[] = + { + EXPLR_MCBIST_MBUER0Q, + }; + + constexpr static const uint64_t MAINLINE_AUE_REGS[] = + { + EXPLR_MCBIST_MBAUER0Q, + }; + + constexpr static const uint64_t ERROR_VECTOR_REGS[] = + { + EXPLR_MCBIST_MBSEVR0Q, + }; + + // Fields, can be any size. + enum + { + HARDWARE_MS_CHIPMARK = EXPLR_RDF_HWMS0_CHIPMARK, + HARDWARE_MS_CHIPMARK_LEN = EXPLR_RDF_HWMS0_CHIPMARK_LEN, + HARDWARE_MS_CONFIRMED = EXPLR_RDF_HWMS0_CONFIRMED, + HARDWARE_MS_EXIT1 = EXPLR_RDF_HWMS0_EXIT_1, + FIRMWARE_MS_MARK = EXPLR_RDF_FWMS0_MARK, + FIRMWARE_MS_MARK_LEN = EXPLR_RDF_FWMS0_MARK_LEN, + FIRMWARE_MS_TYPE = EXPLR_RDF_FWMS0_TYPE, + FIRMWARE_MS_REGION = EXPLR_RDF_FWMS0_REGION, + FIRMWARE_MS_REGION_LEN = EXPLR_RDF_FWMS0_REGION_LEN, + FIRMWARE_MS_ADDRESS = EXPLR_RDF_FWMS0_ADDRESS, + FIRMWARE_MS_ADDRESS_LEN = EXPLR_RDF_FWMS0_ADDRESS_LEN, + FIRMWARE_MS_EXIT1 = EXPLR_RDF_FWMS0_EXIT_1, + NCE_ADDR_TRAP = EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP, + NCE_ADDR_TRAP_LEN = EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN, + NCE_ON_RCE = EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE, + NCE_IS_TCE = EXPLR_MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE, + RCE_ADDR_TRAP = EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP, + RCE_ADDR_TRAP_LEN = EXPLR_MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN, + MPE_ADDR_TRAP = EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP, + MPE_ADDR_TRAP_LEN = EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN, + MPE_ON_RCE = EXPLR_MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE, + UE_ADDR_TRAP = EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP, + UE_ADDR_TRAP_LEN = EXPLR_MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN, + AUE_ADDR_TRAP = EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP, + AUE_ADDR_TRAP_LEN = EXPLR_MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN, + P0_NCE_GALOIS = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD, + P0_NCE_GALOIS_LEN = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN, + P0_NCE_MAGNITUDE = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD, + P0_NCE_MAGNITUDE_LEN = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, + P0_TCE_GALOIS = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD, + P0_TCE_GALOIS_LEN = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN, + P0_TCE_MAGNITUDE = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD, + P0_TCE_MAGNITUDE_LEN = EXPLR_MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, + CURRENT_ADDR_TRAP = EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP, + CURRENT_ADDR_TRAP_LEN = EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN, + CURRENT_PORT = EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP, + CURRENT_PORT_LEN = EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN, + CURRENT_DIMM = EXPLR_MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP, + SHADOW_CHIPMARK = EXPLR_RDF_MSR_CHIPMARK, + SHADOW_CHIPMARK_LEN = EXPLR_RDF_MSR_CHIPMARK_LEN, + SHADOW_RANK = EXPLR_RDF_MSR_RANK, + SHADOW_RANK_LEN = EXPLR_RDF_MSR_RANK_LEN, + + }; + + // Symbol to Galois code mapping table for Explorer + constexpr static const uint8_t symbol2galois[] = + { + 0x80, 0xa0, 0x90, 0xf0, + 0x08, 0x0a, 0x09, 0x0f, + 0x98, 0xda, 0xb9, 0x7f, + 0x91, 0xd7, 0xb2, 0x78, + 0x28, 0xea, 0x49, 0x9f, + 0x9a, 0xd4, 0xbd, 0x76, + 0x60, 0xb0, 0xc0, 0x20, + 0x06, 0x0b, 0x0c, 0x02, + 0xc6, 0xfb, 0x1c, 0x42, + 0xca, 0xf4, 0x1d, 0x46, + 0xd6, 0x8b, 0x3c, 0xc2, + 0xcb, 0xf3, 0x1f, 0x4e, + 0xe0, 0x10, 0x50, 0xd0, + 0x0e, 0x01, 0x05, 0x0d, + 0x5e, 0x21, 0xa5, 0x3d, + 0x5b, 0x23, 0xaf, 0x3e, + 0xfe, 0x61, 0x75, 0x5d, + 0x51, 0x27, 0xa2, 0x38 + }; + + // Symbol to DQ index mapping table for Explorer + constexpr static const uint8_t symbol2dq[] = + { + 39, 38, 37, 36, + 35, 34, 33, 32, + 79, 78, 77, 76, + 71, 70, 69, 68, + 63, 62, 61, 60, + 55, 54, 53, 52, + 31, 30, 29, 28, + 23, 22, 21, 20, + 15, 14, 13, 12, + 7, 6, 5, 4, + 75, 74, 73, 72, + 67, 66, 65, 64, + 59, 58, 57, 56, + 51, 50, 49, 48, + 27, 26, 25, 24, + 19, 18, 17, 16, + 11, 10, 9, 8, + 3, 2, 1, 0 + }; + +}; + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Axone MC ECC interface +/// +template<> +class eccTraits<mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> +{ + public: + // MCBIST ECC registers - must be 64 bits. + static constexpr uint64_t READ_ERROR_COUNT_REG0 = EXPLR_MCBIST_MBSEC0Q; + static constexpr uint64_t READ_ERROR_COUNT_REG1 = EXPLR_MCBIST_MBSEC1Q; + static constexpr uint64_t MARK_SYMBOL_COUNT_REG = EXPLR_MCBIST_MBSMSECQ; + static constexpr uint64_t MODAL_SYM_COUNT0_REG = EXPLR_MCBIST_MBSSYMEC0Q; + static constexpr uint64_t MODAL_SYM_COUNT1_REG = EXPLR_MCBIST_MBSSYMEC1Q; + static constexpr uint64_t MODAL_SYM_COUNT2_REG = EXPLR_MCBIST_MBSSYMEC2Q; + static constexpr uint64_t MODAL_SYM_COUNT3_REG = EXPLR_MCBIST_MBSSYMEC3Q; + static constexpr uint64_t MODAL_SYM_COUNT4_REG = EXPLR_MCBIST_MBSSYMEC4Q; + static constexpr uint64_t MODAL_SYM_COUNT5_REG = EXPLR_MCBIST_MBSSYMEC5Q; + static constexpr uint64_t MODAL_SYM_COUNT6_REG = EXPLR_MCBIST_MBSSYMEC6Q; + static constexpr uint64_t MODAL_SYM_COUNT7_REG = EXPLR_MCBIST_MBSSYMEC7Q; + static constexpr uint64_t MODAL_SYM_COUNT8_REG = EXPLR_MCBIST_MBSSYMEC8Q; + static constexpr uint64_t MODAL_SYM_COUNT9_REG = EXPLR_MCBIST_MBSSYMEC9Q; + static constexpr uint64_t MPE_ADDR_TRAP_REG = EXPLR_MCBIST_MCBMCATQ; + static constexpr uint64_t ECC_MAX_MRANK_PER_PORT = exp::MAX_MRANK_PER_PORT; + static constexpr uint64_t ECC_MAX_DQ_BITS = exp::MAX_DQ_BITS_PER_PORT; + static constexpr uint64_t ECC_MAX_SYMBOLS = exp::MAX_SYMBOLS_PER_PORT; + + // Stores the symbol counter registers in a vector for easier access for MCBIST + static constexpr uint64_t REQUIRED_NUMBER_OF_SYMBOL_REGS = 10; + static const std::vector<uint64_t> SYMBOL_COUNT_REG; + + // Fields, can be any size. + enum + { + INTERMITTENT_CE_COUNT = EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT, + INTERMITTENT_CE_COUNT_LEN = EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN, + SOFT_CE_COUNT = EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT, + SOFT_CE_COUNT_LEN = EXPLR_MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN, + HARD_CE_COUNT = EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT, + HARD_CE_COUNT_LEN = EXPLR_MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN, + INTERMITTENT_MCE_COUNT = EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT, + INTERMITTENT_MCE_COUNT_LEN = EXPLR_MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN, + SOFT_MCE_COUNT = EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT, + SOFT_MCE_COUNT_LEN = EXPLR_MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN, + HARD_MCE_COUNT = EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT, + HARD_MCE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN, + ICE_COUNT = EXPLR_MCBIST_MBSEC1Q_ICE_COUNT, + ICE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_ICE_COUNT_LEN, + UE_COUNT = EXPLR_MCBIST_MBSEC1Q_UE_COUNT, + UE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_UE_COUNT_LEN, + AUE_COUNT = EXPLR_MCBIST_MBSEC1Q_AUE, + AUE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_AUE_LEN, + RCE_COUNT = EXPLR_MCBIST_MBSEC1Q_RCE_COUNT, + RCE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_RCE_COUNT_LEN, + SYMBOL0_COUNT = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT, + SYMBOL0_COUNT_LEN = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN, + SYMBOL1_COUNT = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT, + SYMBOL1_COUNT_LEN = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN, + SYMBOL2_COUNT = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT, + SYMBOL2_COUNT_LEN = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN, + SYMBOL3_COUNT = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT, + SYMBOL3_COUNT_LEN = EXPLR_MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN, + MODAL_SYMBOL_COUNTER_00 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00, + MODAL_SYMBOL_COUNTER_00_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN, + MODAL_SYMBOL_COUNTER_01 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01, + MODAL_SYMBOL_COUNTER_01_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN, + MODAL_SYMBOL_COUNTER_02 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02, + MODAL_SYMBOL_COUNTER_02_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN, + MODAL_SYMBOL_COUNTER_03 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03, + MODAL_SYMBOL_COUNTER_03_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN, + MODAL_SYMBOL_COUNTER_04 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04, + MODAL_SYMBOL_COUNTER_04_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN, + MODAL_SYMBOL_COUNTER_05 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05, + MODAL_SYMBOL_COUNTER_05_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN, + MODAL_SYMBOL_COUNTER_06 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06, + MODAL_SYMBOL_COUNTER_06_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN, + MODAL_SYMBOL_COUNTER_07 = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07, + MODAL_SYMBOL_COUNTER_07_LEN = EXPLR_MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN, + + // FROM NIMBUS, UNSURE IF STILL ACCURATE OR NEEDED + // and a couple constants + NUM_MBSSYM_REGS = 10, + MODAL_SYMBOL_COUNTERS_PER_REG = 8, + }; + +}; + +} // close namespace mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_mbs_error_vector_trap.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_mbs_error_vector_trap.H new file mode 100644 index 000000000..cf0665d32 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_mbs_error_vector_trap.H @@ -0,0 +1,205 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_mbs_error_vector_trap.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mbs_error_vector_trap.H +/// @brief Subroutines for the MC MBS error vector trap registers (MBSEVR*Q) +/// +// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _EXP_MSS_MBS_ERROR_VECTOR_TRAP_H_ +#define _EXP_MSS_MBS_ERROR_VECTOR_TRAP_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/scom.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/ecc/ecc_traits.H> +#include <generic/memory/lib/ecc/mbs_error_vector_trap.H> + +namespace mss +{ + +namespace ecc +{ + +namespace mbs_error_vector_trap +{ + +/// +/// @brief set_nce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void set_nce_galois( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + io_data.insertFromRight<TT::P0_NCE_GALOIS, TT::P0_NCE_GALOIS_LEN>(i_value); + + FAPI_INF("%s set_nce_galois: 0x%016lx", mss::c_str(i_target), i_value); +} + +/// +/// @brief get_nce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void get_nce_galois( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + i_data.extractToRight<TT::P0_NCE_GALOIS, TT::P0_NCE_GALOIS_LEN>(o_value); + + FAPI_INF("%s get_nce_galois: 0x%016lx", mss::c_str(i_target), o_value); +} + +/// +/// @brief set_nce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void set_nce_magnitude( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + io_data.insertFromRight<TT::P0_NCE_MAGNITUDE, TT::P0_NCE_MAGNITUDE_LEN>(i_value); + + FAPI_INF("%s set_nce_magnitude: 0x%016lx", mss::c_str(i_target), i_value); +} + +/// +/// @brief get_nce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void get_nce_magnitude( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + i_data.extractToRight<TT::P0_NCE_MAGNITUDE, TT::P0_NCE_MAGNITUDE_LEN>(o_value); + + FAPI_INF("%s get_nce_magnitude: 0x%016lx", mss::c_str(i_target), o_value); +} + +/// +/// @brief set_tce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void set_tce_galois( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + io_data.insertFromRight<TT::P0_TCE_GALOIS, TT::P0_TCE_GALOIS_LEN>(i_value); + + FAPI_INF("%s set_tce_galois: 0x%016lx", mss::c_str(i_target), i_value); +} + +/// +/// @brief get_tce_galois +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void get_tce_galois( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + i_data.extractToRight<TT::P0_TCE_GALOIS, TT::P0_TCE_GALOIS_LEN>(o_value); + + FAPI_INF("%s get_tce_galois: 0x%016lx", mss::c_str(i_target), o_value); +} + +/// +/// @brief set_tce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in, out] io_data the register value +/// @param[in] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void set_tce_magnitude( const fapi2::Target<T>& i_target, + fapi2::buffer<uint64_t>& io_data, + const uint64_t i_value) +{ + io_data.insertFromRight<TT::P0_TCE_MAGNITUDE, TT::P0_TCE_MAGNITUDE_LEN>(i_value); + + FAPI_INF("%s set_tce_magnitude: 0x%016lx", mss::c_str(i_target), i_value); +} + +/// +/// @brief get_tce_magnitude +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<mc_type::EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the register value +/// @param[out] i_value the value of the field +/// +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline void get_tce_magnitude( const fapi2::Target<T>& i_target, + const fapi2::buffer<uint64_t>& i_data, + uint64_t& o_value) +{ + i_data.extractToRight<TT::P0_TCE_MAGNITUDE, TT::P0_TCE_MAGNITUDE_LEN>(o_value); + + FAPI_INF("%s get_tce_magnitude: 0x%016lx", mss::c_str(i_target), o_value); +} + +} // close namespace mbs_error_vector_trap + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_modal_symbol_count.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_modal_symbol_count.H new file mode 100644 index 000000000..dd9431a3d --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_modal_symbol_count.H @@ -0,0 +1,245 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/exp_modal_symbol_count.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_modal_symbol_count.H +/// @brief Subroutines for the MC modal symbol count (MBSSYMEC*Q) registers +/// +// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _EXP_MSS_MODAL_SYMBOL_COUNT_H_ +#define _EXP_MSS_MODAL_SYMBOL_COUNT_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/scom.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/ecc/ecc_traits.H> +#include <generic/memory/lib/ecc/modal_symbol_count.H> + +namespace mss +{ + +namespace ecc +{ + +namespace modal_symbol_count +{ + +/// +/// @brief Read modal symbol count (MBSSYMEC*Q) register +/// @tparam N the register index (0-8) +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<DEFAULT_MC_TYPE, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t N, fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline fapi2::ReturnCode read_index( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + static_assert((N < TT::NUM_MBSSYM_REGS), "Modal symbol count reg index failed range check"); + FAPI_TRY( mss::getScom(i_target, (TT::MODAL_SYM_COUNT0_REG + N), o_data) ); + FAPI_INF("read_index<%d>: 0x%016lx", N, o_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Read modal symbol count (MBSSYMEC*Q) 9 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode read_index9( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + return ( read_index<9>(i_target, o_data) ); +} + +/// +/// @brief Read modal symbol count (MBSSYMEC*Q) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_index the register index +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TARGET_TYPE_OCMB_CHIP > +inline fapi2::ReturnCode read( const fapi2::TARGET_TYPE_OCMB_CHIP i_target, + const uint64_t i_index, + fapi2::buffer<uint64_t>& o_data ) +{ + switch (i_index) + { + case(0): + return ( read_index0(i_target, o_data) ); + + case(1): + return ( read_index1(i_target, o_data) ); + + case(2): + return ( read_index2(i_target, o_data) ); + + case(3): + return ( read_index3(i_target, o_data) ); + + case(4): + return ( read_index4(i_target, o_data) ); + + case(5): + return ( read_index5(i_target, o_data) ); + + case(6): + return ( read_index6(i_target, o_data) ); + + case(7): + return ( read_index7(i_target, o_data) ); + + case(8): + return ( read_index8(i_target, o_data) ); + + case(9): + return ( read_index9(i_target, o_data) ); + + default: + FAPI_ASSERT( false, + fapi2::MSS_INVALID_INDEX_PASSED() + .set_INDEX(i_index) + .set_FUNCTION(SYMBOL_COUNT_READ), + "%s Invalid index passed to fwms::ecc::modal_symbol_count::read (%d)", + mss::c_str(i_target), + i_index); + } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write modal symbol count (MBSSYMEC*Q) register +/// @tparam N the register index (0-8) +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @tparam TT traits type defaults to eccTraits<EXPLORER, T> +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t N, fapi2::TargetType T, typename TT = eccTraits<mc_type::EXPLORER, T> > +inline fapi2::ReturnCode write_index( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + static_assert((N < TT::NUM_MBSSYM_REGS), "Modal symbol count reg index failed range check"); + FAPI_TRY( mss::putScom(i_target, (TT::MODAL_SYM_COUNT0_REG + N), i_data) ); + FAPI_INF("write_index<%d>: 0x%016lx", N, i_data); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write modal symbol count (MBSSYMEC*Q) 9 register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T > +inline fapi2::ReturnCode write_index9( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + return ( write_index<9>(i_target, i_data) ); +} + +/// +/// @brief Write Hardware Mark Store (HWMS) register +/// @tparam T fapi2 Target Type - derived from i_target's type +/// @param[in] i_target the fapi2 target of the mc +/// @param[in] i_index the register index +/// @param[in] i_data the value to write to the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TARGET_TYPE_OCMB_CHIP > +inline fapi2::ReturnCode write( const fapi2::TARGET_TYPE_OCMB_CHIP i_target, + const uint64_t i_index, + const fapi2::buffer<uint64_t>& i_data ) +{ + switch (i_index) + { + case(0): + return ( write_index0(i_target, i_data) ); + + case(1): + return ( write_index1(i_target, i_data) ); + + case(2): + return ( write_index2(i_target, i_data) ); + + case(3): + return ( write_index3(i_target, i_data) ); + + case(4): + return ( write_index4(i_target, i_data) ); + + case(5): + return ( write_index5(i_target, i_data) ); + + case(6): + return ( write_index6(i_target, i_data) ); + + case(7): + return ( write_index7(i_target, i_data) ); + + case(8): + return ( write_index8(i_target, i_data) ); + + case(9): + return ( write_index9(i_target, i_data) ); + + default: + FAPI_ASSERT( false, + fapi2::MSS_INVALID_INDEX_PASSED() + .set_INDEX(i_index) + .set_FUNCTION(SYMBOL_COUNT_WRITE), + "%s Invalid index passed to fwms::ecc::modal_symbol_count::write (%d)", + mss::c_str(i_target), + i_index); + } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + + +} // close namespace modal_symbol_count + +} // close namespace ecc + +} // close namespace mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H index 3476d51e5..c21838b6a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_attr_engine_traits.H @@ -42,19 +42,25 @@ #include <generic/memory/lib/data_engine/data_engine_traits_def.H> #include <generic/memory/lib/data_engine/data_engine.H> #include <generic/memory/lib/spd/spd_facade.H> -#include <lib/mss_explorer_attribute_getters.H> -#include <lib/mss_explorer_attribute_setters.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <mss_generic_attribute_setters.H> +#include <mss_generic_attribute_getters.H> namespace mss { +//////////////////////////////////////////////////////// +// Explorer specific traits for setTimingTraits +//////////////////////////////////////////////////////// + /// /// @brief Forward declartion of traits for setTimingTraits /// @class setTimingTraits -/// @note attr_eff_engine_fields, SPD_TAA_MIN +/// @note exp::attr_eff_engine_fields, SPD_TAA_MIN /// template< > -struct setTimingTraits< exp::attr_eff_engine_fields, exp::SPD_TAA_MIN > +struct setTimingTraits< exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::SPD_TAA_MIN > { static constexpr const char* TIMING_NAME = "tAAmin"; @@ -62,22 +68,80 @@ struct setTimingTraits< exp::attr_eff_engine_fields, exp::SPD_TAA_MIN > static constexpr spd_facade_fptr get_timing_in_ftb = &spd::facade::fine_offset_min_taa; }; +//////////////////////////////////////////////////////// +// Traits for explorer specific attr_eff_engine_fields +//////////////////////////////////////////////////////// + + /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, ATTR_EFF_BASE_CASE specialization /// NOP for base case needed to trigger partial specialization of attr_engine /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::ATTR_EFF_BASE_CASE> {}; +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::ATTR_EFF_BASE_CASE> {}; + +/// +/// @brief Traits for attr_engine +/// @class attrEngineTraits +/// @tparam P processor type +/// @note attr_eff_engine_fields, ADDRESS_MIRROR specialization +/// +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::ADDRESS_MIRROR> +{ + using attr_type = fapi2::ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EXP_DRAM_ADDRESS_MIRRORING_TargetType; + static constexpr exp::ffdc_codes FFDC_CODE = exp::SET_EXP_DRAM_ADDRESS_MIRRORING; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_exp_dram_address_mirroring(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_exp_dram_address_mirroring(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data EFD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + return i_spd_data.address_mirroring(o_setting); + } +}; /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, BYTE_ENABLES specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::BYTE_ENABLES> { using attr_type = fapi2::ATTR_MEM_EFF_BYTE_ENABLES_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -93,7 +157,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_byte_enables(i_target, o_setting); + return mss::attr::get_byte_enables(i_target, o_setting); } /// @@ -105,7 +169,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_byte_enables(i_target, i_setting); + return mss::attr::set_byte_enables(i_target, i_setting); } /// @@ -124,10 +188,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::BYTE_ENABLES> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, NIBBLE_ENABLES specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::NIBBLE_ENABLES> { using attr_type = fapi2::ATTR_MEM_EFF_NIBBLE_ENABLES_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -143,7 +208,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_nibble_enables(i_target, o_setting); + return mss::attr::get_nibble_enables(i_target, o_setting); } /// @@ -155,7 +220,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_nibble_enables(i_target, i_setting); + return mss::attr::set_nibble_enables(i_target, i_setting); } /// @@ -174,10 +239,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::NIBBLE_ENABLES> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, SPD_TAA_MIN specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::SPD_TAA_MIN> { using attr_type = fapi2::ATTR_MEM_EXP_SPD_TAA_MIN_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -193,7 +259,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_exp_spd_taa_min(i_target, o_setting); + return mss::attr::get_exp_spd_taa_min(i_target, o_setting); } /// @@ -205,7 +271,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_exp_spd_taa_min(i_target, i_setting); + return mss::attr::set_exp_spd_taa_min(i_target, i_setting); } /// @@ -217,17 +283,19 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN> static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, attr_integral_type& o_setting) { - return mss::calc_spd_time_in_ps<exp::attr_eff_engine_fields, exp::SPD_TAA_MIN>(i_spd_data, o_setting); + return mss::calc_spd_time_in_ps<exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::SPD_TAA_MIN>(i_spd_data, + o_setting); } }; /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, FOUR_RANK_MODE specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::FOUR_RANK_MODE> { using attr_type = fapi2::ATTR_MEM_EFF_FOUR_RANK_MODE_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -243,7 +311,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_four_rank_mode(i_target, o_setting); + return mss::attr::get_four_rank_mode(i_target, o_setting); } /// @@ -255,7 +323,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_four_rank_mode(i_target, i_setting); + return mss::attr::set_four_rank_mode(i_target, i_setting); } /// @@ -268,7 +336,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE> attr_integral_type& o_setting) { constexpr auto FOUR_RANK_MODE_BIT = 7; // From SPEC - uint8_t l_spd_four_rank_mode = 0; + attr_integral_type l_spd_four_rank_mode = 0; FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_four_rank_mode)); o_setting = fapi2::buffer<uint8_t>(l_spd_four_rank_mode).getBit<FOUR_RANK_MODE_BIT>(); @@ -281,10 +349,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::FOUR_RANK_MODE> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, DDP_COMPATIBILITY specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::DDP_COMPATIBILITY> { using attr_type = fapi2::ATTR_MEM_EFF_DDP_COMPATIBILITY_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -300,7 +369,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_ddp_compatibility(i_target, o_setting); + return mss::attr::get_ddp_compatibility(i_target, o_setting); } /// @@ -312,7 +381,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_ddp_compatibility(i_target, i_setting); + return mss::attr::set_ddp_compatibility(i_target, i_setting); } /// @@ -325,7 +394,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY> attr_integral_type& o_setting) { constexpr auto DDP_COMPATIBILITY_BIT = 6; // From SPEC - uint8_t l_spd_ddp_compatibility = 0; + attr_integral_type l_spd_ddp_compatibility = 0; FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_ddp_compatibility)); o_setting = fapi2::buffer<uint8_t>(l_spd_ddp_compatibility).getBit<DDP_COMPATIBILITY_BIT>(); @@ -338,10 +407,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::DDP_COMPATIBILITY> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, TSV_8H_SUPPORT specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::TSV_8H_SUPPORT> { using attr_type = fapi2::ATTR_MEM_EFF_TSV_8H_SUPPORT_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -357,7 +427,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_tsv_8h_support(i_target, o_setting); + return mss::attr::get_tsv_8h_support(i_target, o_setting); } /// @@ -369,7 +439,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_tsv_8h_support(i_target, i_setting); + return mss::attr::set_tsv_8h_support(i_target, i_setting); } /// @@ -388,10 +458,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::TSV_8H_SUPPORT> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, PSTATES specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::PSTATES> { using attr_type = fapi2::ATTR_MEM_EFF_PSTATES_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -407,7 +478,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_pstates(i_target, o_setting); + return mss::attr::get_pstates(i_target, o_setting); } /// @@ -419,7 +490,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_pstates(i_target, i_setting); + return mss::attr::set_pstates(i_target, i_setting); } /// @@ -438,10 +509,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::PSTATES> /// /// @brief Traits for attr_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, MRAM_SUPPORT specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::MRAM_SUPPORT> { using attr_type = fapi2::ATTR_MEM_EFF_MRAM_SUPPORT_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -457,7 +529,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_mram_support(i_target, o_setting); + return mss::attr::get_mram_support(i_target, o_setting); } /// @@ -469,7 +541,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_mram_support(i_target, i_setting); + return mss::attr::set_mram_support(i_target, i_setting); } /// @@ -482,7 +554,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> attr_integral_type& o_setting) { constexpr auto MRAM_SUPPORT_BIT = 4; // From SPEC - uint8_t l_spd_ddp_compatibility = 0; + attr_integral_type l_spd_ddp_compatibility = 0; FAPI_TRY(i_spd_data.compatabilty_modes(l_spd_ddp_compatibility)); o_setting = fapi2::buffer<uint8_t>(l_spd_ddp_compatibility).getBit<MRAM_SUPPORT_BIT>(); @@ -495,61 +567,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::MRAM_SUPPORT> /// /// @brief Traits for attr_engine /// @class attrEngineTraits -/// @note attr_eff_engine_fields, HEIGHT_3DS specialization -/// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::HEIGHT_3DS> -{ - using attr_type = fapi2::ATTR_MEM_EXP_3DS_HEIGHT_Type; - using attr_integral_type = std::remove_all_extents<attr_type>::type; - static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EXP_3DS_HEIGHT_TargetType; - static constexpr exp::ffdc_codes FFDC_CODE = exp::SET_3DS_HEIGHT; - - /// - /// @brief attribute getter - /// @param[in] i_target the fapi2 target - /// @param[out] o_setting array to populate - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& o_setting) - { - return attr::get_exp_3ds_height(i_target, o_setting); - } - - /// - /// @brief attribute setter - /// @param[in] i_target the fapi2 target - /// @param[in] i_setting array to set - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, - attr_type& i_setting) - { - return attr::set_exp_3ds_height(i_target, i_setting); - } - - /// - /// @brief Computes setting for attribute - /// @param[in] i_spd_data EFD data - /// @param[out] o_setting value we want to set attr with - /// @return FAPI2_RC_SUCCESS iff okay - /// - static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, - attr_integral_type& o_setting) - { - - return fapi2::FAPI2_RC_SUCCESS; - } -}; - -/// -/// @brief Traits for attr_engine -/// @class attrEngineTraits +/// @tparam P processor type /// @note attr_eff_engine_fields, SPD_CL_SUPPORTED specialization /// -template<> -struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> +template< proc_type P > +struct attrEngineTraits<P, exp::attr_eff_engine_fields, exp::attr_eff_engine_fields::SPD_CL_SUPPORTED> { using attr_type = fapi2::ATTR_MEM_EXP_SPD_CL_SUPPORTED_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -565,7 +587,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& o_setting) { - return attr::get_exp_spd_cl_supported(i_target, o_setting); + return mss::attr::get_exp_spd_cl_supported(i_target, o_setting); } /// @@ -577,7 +599,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, attr_type& i_setting) { - return attr::set_exp_spd_cl_supported(i_target, i_setting); + return mss::attr::set_exp_spd_cl_supported(i_target, i_setting); } /// @@ -591,6 +613,7 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> { uint64_t l_val = 0; FAPI_TRY(i_spd_data.supported_cas_latencies(l_val)); + o_setting = static_cast<attr_integral_type>(l_val); fapi_try_exit: @@ -601,10 +624,11 @@ struct attrEngineTraits<exp::attr_eff_engine_fields, exp::SPD_CL_SUPPORTED> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note AXONE, DIMM_TYPE_METADATA specialization /// -template<> -struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA> +template< proc_type P > +struct attrEngineTraits<P, generic_metadata_fields, generic_metadata_fields::DIMM_TYPE_METADATA> { using attr_type = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -637,8 +661,8 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_TYPE_METADATA> /// /// @brief Computes setting for attribute - /// @param[in] i_spd_data SPD data - /// @param[in] i_setting value we want to set attr with + /// @param[in] i_target the DIMM target + /// @param[out] o_setting value we want to set attr with /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -685,10 +709,11 @@ class dimmPosTraits<mss::mc_type::EXPLORER> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note generic_metadata_fields, DRAM_GEN_METADATA specialization /// -template<> -struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> +template< proc_type P > +struct attrEngineTraits<P, generic_metadata_fields, generic_metadata_fields::DRAM_GEN_METADATA> { using attr_type = fapi2::ATTR_MEM_DRAM_GEN_METADATA_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -721,8 +746,8 @@ struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> /// /// @brief Computes setting for attribute - /// @param[in] i_spd_data SPD data - /// @param[in] i_setting value we want to set attr with + /// @param[in] i_target the DIMM target + /// @param[out] o_setting value we want to set attr with /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -735,10 +760,11 @@ struct attrEngineTraits<generic_metadata_fields, DRAM_GEN_METADATA> /// /// @brief Traits for pre_data_engine /// @class attrEngineTraits +/// @tparam P processor type /// @note generic_metadata_fields, DIMM_POS_METADATA specialization /// -template<> -struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> +template< proc_type P > +struct attrEngineTraits<P, generic_metadata_fields, generic_metadata_fields::DIMM_POS_METADATA> { using attr_type = fapi2::ATTR_MEM_DIMM_POS_METADATA_Type; using attr_integral_type = std::remove_all_extents<attr_type>::type; @@ -771,8 +797,8 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> /// /// @brief Computes setting for attribute - /// @param[in] i_spd_data SPD data - /// @param[in] i_setting value we want to set attr with + /// @param[in] i_target the DIMM target + /// @param[out] o_setting value we want to set attr with /// @return FAPI2_RC_SUCCESS iff okay /// static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, @@ -783,28 +809,6 @@ struct attrEngineTraits<generic_metadata_fields, DIMM_POS_METADATA> } }; -/// -/// @brief Value traits for attr_eff_engine_fields -/// @class attrEngineTraits -/// @note attr_eff_engine_fields -/// -template < > -struct attrEnumTraits<exp::attr_eff_engine_fields> -{ - static constexpr size_t DISPATCHER = exp::ATTR_EFF_DISPATCHER; -}; - -/// -/// @brief Value traits for attr_eff_engine_fields -/// @class attrEngineTraits -/// @note attr_eff_engine_fields -/// -template < > -struct attrEnumTraits<generic_metadata_fields> -{ - static constexpr size_t DISPATCHER = ATTR_METADATA_DISPATCHER; -}; - }//mss #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C new file mode 100644 index 000000000..8aa963ab3 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C @@ -0,0 +1,276 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file explorer_efd_processing.C +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <exp_data_structs.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <lib/eff_config/explorer_efd_processing.H> +#include <generic/memory/lib/mss_generic_attribute_setters.H> + +namespace mss +{ +namespace exp +{ +namespace efd +{ + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_addr_delay_a[DRAMINIT_NUM_ADDR_DELAYS] = {}; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_atxdly_a(l_port, l_addr_delay_a)); + + // Update the values + FAPI_TRY(i_efd_data->cac_delay_a_side_group_0(l_addr_delay_a[0])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_1(l_addr_delay_a[1])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_2(l_addr_delay_a[2])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_3(l_addr_delay_a[3])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_4(l_addr_delay_a[4])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_5(l_addr_delay_a[5])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_6(l_addr_delay_a[6])); + FAPI_TRY(i_efd_data->cac_delay_a_side_group_7(l_addr_delay_a[7])); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_atxdly_a(l_port, l_addr_delay_a)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CAC delay B side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_addr_delay_b[DRAMINIT_NUM_ADDR_DELAYS] = {}; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_atxdly_b(l_port, l_addr_delay_b)); + + // Update the values + FAPI_TRY(i_efd_data->cac_delay_b_side_group_0(l_addr_delay_b[0])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_1(l_addr_delay_b[1])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_2(l_addr_delay_b[2])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_3(l_addr_delay_b[3])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_4(l_addr_delay_b[4])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_5(l_addr_delay_b[5])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_6(l_addr_delay_b[6])); + FAPI_TRY(i_efd_data->cac_delay_b_side_group_7(l_addr_delay_b[7])); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_atxdly_b(l_port, l_addr_delay_b)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the Host INIT RD VREF DQ +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// @note this is pulled in for exp_draminit. The individual fields are pulled into the SI engine +/// +fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // See Byte 44 of SPD Document (Bit 6 from right = Bit 1 from left) + static const uint8_t VREF_RANGE_BIT_LEFT_ALGINED = 1; + + // Get the data + uint8_t l_vref_dq[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; + + uint8_t l_range = 0; + uint8_t l_value = 0; + fapi2::buffer<uint8_t> l_combined_vref; + + FAPI_TRY(mss::attr::get_exp_init_vref_dq(i_target, l_vref_dq)); + + // Piece together the field + FAPI_TRY(i_efd_data->wr_vref_dq_range(l_range)); + FAPI_TRY(i_efd_data->wr_vref_dq_value(l_value)); + + l_combined_vref = l_value; + l_combined_vref.writeBit<VREF_RANGE_BIT_LEFT_ALGINED>(l_range); + + // Insert + l_vref_dq[i_efd_data->get_rank()] = l_combined_vref; + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_init_vref_dq(i_target, l_vref_dq)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the Host INIT PHY VREF +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode init_phy_vref(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_phy_vref[mss::exp::sizes::MAX_RANK_PER_DIMM] = {0}; + + FAPI_TRY(mss::attr::get_exp_init_phy_vref(i_target, l_phy_vref)); + + // Update the values + FAPI_TRY(i_efd_data->init_phy_vref(l_phy_vref[i_efd_data->get_rank()])); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_init_phy_vref(i_target, l_phy_vref)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CS command latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_cmd_latency = 0; + FAPI_TRY(mss::attr::get_cs_cmd_latency(i_target, l_cmd_latency)); + + // Update the values + FAPI_TRY(i_efd_data->bist_ca_latency_mode(l_cmd_latency)); + + // Set the attribute + FAPI_TRY(mss::attr::set_cs_cmd_latency(i_target, l_cmd_latency)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the CA parity latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_ca_parity_latency = 0; + FAPI_TRY(mss::attr::get_ca_parity_latency(i_target, l_ca_parity_latency)); + + // Update the values + FAPI_TRY(i_efd_data->bist_ca_pl_mode(l_ca_parity_latency)); + + // Set the attribute + FAPI_TRY(mss::attr::set_ca_parity_latency(i_target, l_ca_parity_latency)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Processes the DFIMRL_DDRCLK +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode dfimrl_ddrclk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + // Get the data + uint8_t l_dfimrl_ddrclk = 0; + const auto& l_port = mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + FAPI_TRY(mss::attr::get_exp_dfimrl_clk(l_port, l_dfimrl_ddrclk)); + + // Update the values + FAPI_TRY(i_efd_data->dfimrl_ddrclk(l_dfimrl_ddrclk)); + + // Set the attribute + FAPI_TRY(mss::attr::set_exp_dfimrl_clk(l_port, l_dfimrl_ddrclk)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data) +{ + FAPI_TRY(init_vref_dq(i_target, i_efd_data)); + FAPI_TRY(init_phy_vref(i_target, i_efd_data)); + FAPI_TRY(cs_cmd_latency(i_target, i_efd_data)); + FAPI_TRY(ca_parity_latency(i_target, i_efd_data)); + FAPI_TRY(dfimrl_ddrclk(i_target, i_efd_data)); + FAPI_TRY(cac_delay_a(i_target, i_efd_data)); + FAPI_TRY(cac_delay_b(i_target, i_efd_data)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns efd +} // ns exp +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H new file mode 100644 index 000000000..2f7c5cc14 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/explorer_efd_processing.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file explorer_efd_processing.H +/// @brief Processing for EFD for eff config +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_EXPLORER_EFD_PROCESSING_H_ +#define _MSS_EXPLORER_EFD_PROCESSING_H_ + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> + +namespace mss +{ +namespace exp +{ +namespace efd +{ + +/// +/// @brief Processes the Host INIT RD VREF DQ +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// @note this is pulled in for exp_draminit. The individual fields are pulled into the SI engine +/// +fapi2::ReturnCode init_vref_dq(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the Host INIT PHY VREF +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode init_phy_vref(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_a(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CAC delay A side +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cac_delay_b(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CS command latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode cs_cmd_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the CA parity latency +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode ca_parity_latency(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Processes the DFIMRL_DDRCLK +/// @param[in] i_target the target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode dfimrl_ddrclk(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); + +/// +/// @brief Process the EFD data and set attributes +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_efd_data the EFD data to process +/// @return fapi2::FAPI2_RC_SUCCESS iff function completes successfully +/// +fapi2::ReturnCode process(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::shared_ptr<mss::efd::base_decoder>& i_efd_data); +} // ns efd +} // ns exp +} // ns mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_attribute_accessors_manual.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_attribute_accessors_manual.H index 04434c84c..eca4bc6ee 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_attribute_accessors_manual.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_attribute_accessors_manual.H @@ -48,40 +48,72 @@ namespace mss { /// -/// @brief Gets whether the OCMB will be configred to enterprise mode -/// @param[in] i_target OCMB target on which to operate -/// @param[out] o_is_enterprise_mode true if the part is in enterprise mode -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @brief Unit-testable half dimm mode helper function. Calculates half dimm mode based on input params +/// @param[in] i_target OCMB chip +/// @param[in] i_is_enterprise enterprise mode is enabled +/// @param[in] i_half_dimm_attr half dimm mode as obtained from attribute +/// @param[in] i_half_dimm_override_attr half dimm mode override from attribute +/// @param[out] o_is_half_dimm_mode resulting value for half dimm mode after calculations +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code /// -inline fapi2::ReturnCode enterprise_mode( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& - i_target, - bool& o_is_enterprise_mode ) +inline fapi2::ReturnCode half_dimm_mode_helper( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_is_enterprise, + const uint8_t i_half_dimm_attr, + const uint8_t i_half_dimm_override_attr, + bool& o_is_half_dimm_mode ) { - // Constexprs for beautification - constexpr uint8_t ENTERPRISE = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_MODE_ENTERPRISE; - constexpr uint8_t NO_OVERRIDE = fapi2::ENUM_ATTR_MSS_OCMB_NONENTERPRISE_MODE_OVERRIDE_NO_OVERRIDE; + o_is_half_dimm_mode = false; - // Variables - o_is_enterprise_mode = false; - uint8_t l_enterprise = 0; - uint8_t l_override = 0; + bool l_is_half_dimm = 0; + + // First let's assert that ocmb_half_dimm_mode isn't HALF_DIMM when ENTERPRISE is 0 + // Even though this could theoretically be overridden back to FULL_DIMM, we should + // check that the initial value is also valid. + FAPI_ASSERT(!i_half_dimm_attr || i_is_enterprise, + fapi2::MSS_EXP_HALF_DIMM_MODE_NOT_SUPPORTED() + .set_ENTERPRISE_SETTING(i_is_enterprise) + .set_HALF_DIMM_SETTING(i_half_dimm_attr) + .set_OCMB_TARGET(i_target), + "%s Invalid configuration: ATTR_MSS_OCMB_HALF_DIMM_MODE set to HALF_DIMM while enterprise is disabled", + mss::c_str(i_target)); - FAPI_TRY( mss::attr::get_ocmb_enterprise_mode(i_target, l_enterprise) ); - FAPI_TRY( mss::attr::get_ocmb_nonenterprise_mode_override(i_target, l_override) ); + // This might be overwritten below by overrides + l_is_half_dimm = (i_half_dimm_attr == fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_HALF_DIMM); + // Now let's apply the override + if (i_half_dimm_override_attr == fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_OVERRIDE_OVERRIDE_HALF_DIMM) { - const bool l_enterprise_mode = l_enterprise == ENTERPRISE; - const bool l_no_override = l_override == NO_OVERRIDE; - // We will be in enterprise mode (true) IF - // 1) the chip is in enterprise mode (we can't run in enterprise mode if the part is non-enterprise capable) AND - // 2) we do not have the override to non-enterprise mode - o_is_enterprise_mode = l_enterprise_mode && l_no_override; - - FAPI_INF("%s is in %s mode chip is %s override is %s", mss::c_str(i_target), - o_is_enterprise_mode ? "enterprise" : "non-enterprise", l_enterprise_mode ? "enterprise" : "non-enterprise", - l_no_override ? "no override" : "override to non-enterprise"); + l_is_half_dimm = true; + + // Assert once more that this is valid + FAPI_ASSERT(!l_is_half_dimm || i_is_enterprise, + fapi2::MSS_EXP_HALF_DIMM_MODE_NOT_SUPPORTED() + .set_ENTERPRISE_SETTING(i_is_enterprise) + .set_HALF_DIMM_SETTING(l_is_half_dimm) + .set_OCMB_TARGET(i_target), + "%s Invalid configuration: HALF_DIMM_MODE overridden to HALF_DIMM while enterprise is disabled", + mss::c_str(i_target)); + + FAPI_DBG("%s overridden to HALF_DIMM_MODE", mss::c_str(i_target)); } + else if (i_half_dimm_override_attr == fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_OVERRIDE_OVERRIDE_FULL_DIMM) + { + l_is_half_dimm = false; + FAPI_DBG("%s overridden to FULL_DIMM_MODE", mss::c_str(i_target)); + } + + o_is_half_dimm_mode = l_is_half_dimm; + + FAPI_INF("%s %s in enterprise mode, and %s override is present. The chip is in %s (attribute %u)", + mss::c_str(i_target), + i_is_enterprise ? "is" : "is not", + i_half_dimm_override_attr > 0 ? "an" : "no", + o_is_half_dimm_mode ? "half-DIMM mode" : "full-DIMM mode", l_is_half_dimm); + + return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: return fapi2::current_err; } @@ -92,45 +124,22 @@ fapi_try_exit: /// @param[out] o_is_half_dimm_mode true if the part is in half-DIMM mode /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK /// -inline fapi2::ReturnCode half_dimm_mode( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& - i_target, - bool& o_is_half_dimm_mode ) +inline fapi2::ReturnCode half_dimm_mode( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_is_enterprise_mode, + bool& o_is_half_dimm_mode ) { // Variables o_is_half_dimm_mode = false; - bool l_is_enterprise = false; - uint8_t l_half_dimm = 0; - uint8_t l_override = 0; - - FAPI_TRY( enterprise_mode(i_target, l_is_enterprise) ); - - // We're in full DIMM mode if we're in non-enterprise mode - if(!l_is_enterprise) - { - o_is_half_dimm_mode = false; - FAPI_INF("%s is in full-DIMM as the chip is in non-enterprise mode", mss::c_str(i_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - - // Now that we're not in enterprise mode, check for overrides - FAPI_TRY( mss::attr::get_ocmb_half_dimm_mode_override(i_target, l_override) ); - - // If we have an override, set based upon the override - if(l_override != fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_OVERRIDE_NO_OVERRIDE) - { - o_is_half_dimm_mode = l_override == fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_OVERRIDE_OVERRIDE_HALF_DIMM; - FAPI_INF("%s is in enterprise mode %s override is present. The chip is in %s (attribute %u)", mss::c_str(i_target), - "an", o_is_half_dimm_mode ? "half-DIMM mode" : "full-DIMM mode", l_override); - return fapi2::FAPI2_RC_SUCCESS; - } + uint8_t l_half_dimm_attr = 0; + uint8_t l_override_attr = 0; - // No override, so go with the attribute derived from the ECID - FAPI_TRY( mss::attr::get_ocmb_half_dimm_mode(i_target, l_half_dimm) ); + FAPI_TRY( mss::attr::get_ocmb_half_dimm_mode(i_target, l_half_dimm_attr) ); + FAPI_TRY( mss::attr::get_ocmb_half_dimm_mode_override(i_target, l_override_attr) ); - // Set half DIMM mode based upon the the normal attribute - o_is_half_dimm_mode = l_half_dimm == fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_HALF_DIMM; - FAPI_INF("%s is in enterprise mode %s override is present. The chip is in %s (attribute %u)", mss::c_str(i_target), - "no", o_is_half_dimm_mode ? "half-DIMM mode" : "full-DIMM mode", l_half_dimm); + // o_is_half_dimm_mode will be set by the helper function + FAPI_TRY( mss::half_dimm_mode_helper(i_target, i_is_enterprise_mode, l_half_dimm_attr, l_override_attr, + o_is_half_dimm_mode)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C index 30683e5bb..25a23285a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,6 +34,9 @@ #include <generic/memory/lib/utils/c_str.H> #include <lib/exp_draminit_utils.H> +#include <lib/phy/exp_train_display.H> +#include <lib/phy/exp_train_handler.H> +#include <exp_inband.H> namespace mss { @@ -41,23 +44,367 @@ namespace exp { /// -/// @brief host_fw_command_struct structure setup +/// @brief Check that the rsp_data size returned from the PHY_INIT command matches the expected size +/// +/// @param[in] i_target OCMB target +/// @param[in] i_actual_size size enum expected for the given phy init mode +/// @param[in] i_mode phy init mode. Expected to be a valid enum value since we asserted as such in exp_draminit.C +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff matching, else MSS_EXP_INVALID_PHY_INIT_RSP_DATA_LENGTH +/// +fapi2::ReturnCode check_rsp_data_size( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint16_t i_actual_size, + const phy_init_mode i_mode) +{ + uint16_t l_expected_size = 0; + + switch (i_mode) + { + case phy_init_mode::NORMAL: + l_expected_size = sizeof(user_response_msdg_t); + break; + + case phy_init_mode::EYE_CAPTURE_STEP_1: + l_expected_size = sizeof(user_2d_eye_response_1_msdg_t); + break; + + case phy_init_mode::EYE_CAPTURE_STEP_2: + l_expected_size = sizeof(user_2d_eye_response_2_msdg_t); + break; + + default: + // This really can't occur since we asserted phy_init_mode was valid in exp_draminit.C + // We have bigger problems if we get here, implying somehow this bad value was passed to explorer + FAPI_ASSERT(false, + fapi2::MSS_EXP_UNKNOWN_PHY_INIT_MODE() + .set_TARGET(i_target) + .set_VALUE(i_mode), + "%s Value for phy init mode for exp_draminit is unknown: %u expected 0 (NORMAL), 1 (EYE_CAPTURE_STEP_1), 2 (EYE_CAPTURE_STEP_2)", + mss::c_str(i_target), i_mode); + break; + } + + FAPI_ASSERT(l_expected_size == i_actual_size, + fapi2::MSS_EXP_INVALID_PHY_INIT_RSP_DATA_LENGTH() + .set_OCMB_TARGET(i_target) + .set_PHY_INIT_MODE(i_mode) + .set_EXPECTED_LENGTH(l_expected_size) + .set_ACTUAL_LENGTH(i_actual_size), + "%s PHY INIT response data buffer size 0x%x did not match expected size 0x%x for phy_init_mode %u", + mss::c_str(i_target), i_actual_size, l_expected_size, i_mode); + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform normal host FW phy init +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC value +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode host_fw_phy_normal_init(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc) +{ + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + host_fw_command_struct l_cmd; + std::vector<uint8_t> l_rsp_data; + + // Issue full boot mode cmd though EXP-FW REQ buffer + FAPI_TRY(send_host_phy_init_cmd(i_target, i_crc, phy_init_mode::NORMAL, l_cmd)); + FAPI_TRY(mss::exp::check_host_fw_response(i_target, l_cmd, l_rsp_data, l_rc)); + + FAPI_TRY(check_rsp_data_size(i_target, l_rsp_data.size(), phy_init_mode::NORMAL)); + FAPI_TRY(mss::exp::read_and_display_normal_training_repsonse(i_target, l_rsp_data, l_rc)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform host FW phy init with eye capture +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC value +/// @param[in] i_phy_params PHY params struct +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note the goal here is to attempt to send both phy_inits even in the event of a bad return code from the read & display +/// +fapi2::ReturnCode host_fw_phy_init_with_eye_capture(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc, + const user_input_msdg& i_phy_params) +{ + fapi2::ReturnCode l_check_response_1_rc = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_read_display_response_1_rc = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_check_response_2_rc = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_read_display_response_2_rc = fapi2::FAPI2_RC_SUCCESS; + + user_2d_eye_response_1_msdg l_response_1; + user_2d_eye_response_2_msdg l_response_2; + + std::vector<uint8_t> l_rsp_data; + + // First, step 1 + { + host_fw_command_struct l_cmd; + FAPI_TRY(send_host_phy_init_cmd(i_target, i_crc, phy_init_mode::EYE_CAPTURE_STEP_1, l_cmd)); + + // Return code output param is that of check::response + // A fail of getRSP will go to fapi_try_exit + FAPI_TRY(mss::exp::check_host_fw_response(i_target, l_cmd, l_rsp_data, l_check_response_1_rc)); + + l_read_display_response_1_rc = check_rsp_data_size(i_target, + l_rsp_data.size(), + phy_init_mode::EYE_CAPTURE_STEP_1); + + // If the data is the right size, we can read and display it. Otherwise, skip the reading and try step 2 + // Check the return codes at the end + if (l_read_display_response_1_rc == fapi2::FAPI2_RC_SUCCESS) + { + l_read_display_response_1_rc = mss::exp::read_and_display_user_2d_eye_response(i_target, l_rsp_data, l_response_1); + } + } + l_rsp_data.clear(); + + // Next, step 2 + { + host_fw_command_struct l_cmd; + uint32_t l_crc = 0; + + // Put user_input_msdg again for step 2 (overwritten by data buffer from step 1) + FAPI_TRY( mss::exp::ib::putUserInputMsdg(i_target, i_phy_params, l_crc), + "Failed putUserInputMsdg() for %s", mss::c_str(i_target) ); + + // Send cmd + FAPI_TRY(send_host_phy_init_cmd(i_target, l_crc, phy_init_mode::EYE_CAPTURE_STEP_2, l_cmd)); + + // Return code output param is that of check::response + // A fail of getRSP will go to fapi_try_exit + FAPI_TRY(mss::exp::check_host_fw_response(i_target, l_cmd, l_rsp_data, l_check_response_2_rc)); + + l_read_display_response_2_rc = check_rsp_data_size(i_target, + l_rsp_data.size(), + phy_init_mode::EYE_CAPTURE_STEP_2); + + // If the data is the right size, we can read and display it. Otherwise, skip the reading. + // Next, we will check these return codes + if (l_read_display_response_2_rc == fapi2::FAPI2_RC_SUCCESS) + { + l_read_display_response_2_rc = mss::exp::read_and_display_user_2d_eye_response(i_target, l_rsp_data, l_response_2); + } + } + + // Check the return codes + FAPI_TRY(process_eye_capture_return_codes(i_target, + l_response_1, + l_response_2, + l_check_response_1_rc, + l_check_response_2_rc)); + + // Finally, check the display response return codes + FAPI_TRY(l_read_display_response_1_rc, "Error ocurred reading/displaying eye capture response 1 of %s", + mss::c_str(i_target)); + FAPI_TRY(l_read_display_response_2_rc, "Error ocurred reading/displaying eye capture response 2 of %s", + mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Process return codes from PHY init with eye capture operations +/// +/// @param[in] i_target OCMB target +/// @param[in] i_response_1 response struct for EYE_CAPTURE_STEP_1 +/// @param[in] i_response_2 response struct for EYE_CAPTURE_STEP_2 +/// @param[in] i_response_1_rc response from check_host_fw_response from EYE_CAPTURE_STEP_1 +/// @param[in] i_response_2_rc response from check_host_fw_response from EYE_CAPTURE_STEP_2 +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else an error from above as defined in the function algorithm +/// @note return codes are passed by value, caller should not expect these to change +/// +fapi2::ReturnCode process_eye_capture_return_codes(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg& i_response_1, + const user_2d_eye_response_2_msdg& i_response_2, + fapi2::ReturnCode i_response_1_rc, + fapi2::ReturnCode i_response_2_rc) +{ + const bool l_response_1_failed = i_response_1_rc != fapi2::FAPI2_RC_SUCCESS; + const bool l_response_2_failed = i_response_2_rc != fapi2::FAPI2_RC_SUCCESS; + + if (l_response_2_failed) + { + FAPI_ERR("%s check_fw_host_response() for %s returned error code 0x%016llu", + mss::c_str(i_target), "EYE_CAPTURE_STEP_2", uint64_t(i_response_2_rc)); + + mss::exp::bad_bit_interface<user_2d_eye_response_2_msdg> l_interface_2(i_response_2); + FAPI_TRY(mss::record_bad_bits<mss::mc_type::EXPLORER>(i_target, l_interface_2)); + + if (l_response_1_failed) + { + // Log response 2's error, and let's return response 1 + fapi2::logError(i_response_2_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); + + // logError sets the return code& to NULL. Set to FAPI2_RC_SUCCESS in case of use + i_response_2_rc = fapi2::FAPI2_RC_SUCCESS; + } + + FAPI_TRY(i_response_2_rc); + } + + if (l_response_1_failed) + { + FAPI_ERR("%s check_fw_host_response() for %s returned error code 0x%016llu", + mss::c_str(i_target), "EYE_CAPTURE_STEP_1", uint64_t(i_response_1_rc)); + + mss::exp::bad_bit_interface<user_2d_eye_response_1_msdg> l_interface_1(i_response_1); + FAPI_TRY(mss::record_bad_bits<mss::mc_type::EXPLORER>(i_target, l_interface_1)); + + return i_response_1_rc; + } + + // Else, we did not see errors! + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Send PHY init command given the provided phy mode and CRC +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC field +/// @param[in] i_phy_init_mode normal / eye capture step 1 or 2 +/// @param[out] host_fw_command_struct used for initialization +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode send_host_phy_init_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc, + const uint8_t i_phy_init_mode, + host_fw_command_struct& o_cmd) +{ + host_fw_command_struct l_cmd; + + // Issue full boot mode cmd though EXP-FW REQ buffer + FAPI_TRY(setup_cmd_params(i_target, i_crc, sizeof(user_input_msdg), i_phy_init_mode, l_cmd)); + FAPI_TRY(mss::exp::ib::putCMD(i_target, l_cmd), + "Failed putCMD() for %s", mss::c_str(i_target)); + + // Wait a bit for the command (and training) to complete + // Value based on initial Explorer hardware in Cronus in i2c mode. + // Training takes ~10ms with no trace, ~450ms with Explorer UART debug + FAPI_TRY(fapi2::delay((mss::DELAY_1MS * 8), 200)); + + o_cmd = l_cmd; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get and check the host fw response from the explorer +/// +/// @param[in] i_target OCMB chip +/// @param[in] i_cmd host_fw_command_struct used to generate the response +/// @param[out] o_rsp_data response data +/// @param[out] o_rc return code from mss::exp::check::response() +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode check_host_fw_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_command_struct& i_cmd, + std::vector<uint8_t>& o_rsp_data, + fapi2::ReturnCode& o_rc) +{ + host_fw_response_struct l_response; + + FAPI_TRY(mss::exp::ib::getRSP(i_target, l_response, o_rsp_data), + "Failed getRSP() for %s", mss::c_str(i_target)); + + o_rc = mss::exp::check::response(i_target, l_response, i_cmd); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Reads and displays the normal draminit training response +/// +/// @param[in] i_target OCMB target +/// @param[in] i_resp_data RESP data +/// @param[in] i_rc return code from checking response +/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode read_and_display_normal_training_repsonse( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t> i_resp_data, + const fapi2::ReturnCode i_rc) +{ + user_response_msdg l_train_response; + + // Proccesses the response data + FAPI_TRY( mss::exp::read_normal_training_response(i_target, i_resp_data, l_train_response), + "Failed read_normal_training_response for %s", mss::c_str(i_target)); + + // Displays the training response + FAPI_INF("%s displaying user response data version %u", mss::c_str(i_target), l_train_response.version_number) + FAPI_TRY( mss::exp::train::display_normal_info(i_target, l_train_response)); + + if(i_rc != fapi2::FAPI2_RC_SUCCESS) + { + mss::exp::bad_bit_interface<user_response_msdg> l_interface(l_train_response); + FAPI_TRY(mss::record_bad_bits<mss::mc_type::EXPLORER>(i_target, l_interface)); + FAPI_TRY(i_rc, "mss::exp::check::response failed for %s", mss::c_str(i_target)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief host_fw_phy_init_command_struct structure setup +/// +/// @param[in] i_target OCMB target /// @param[in] i_cmd_data_crc the command data CRC +/// @param[in] i_cmd_length the length of the command present in the data buffer (if any) +/// @param[in] i_phy_init_mode PHY init mode /// @param[out] o_cmd the command parameters to set /// -void setup_cmd_params(const uint32_t i_cmd_data_crc, host_fw_command_struct& o_cmd) +fapi2::ReturnCode setup_cmd_params( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_cmd_data_crc, + const uint32_t i_cmd_length, + const uint8_t i_phy_init_mode, + host_fw_command_struct& o_cmd) { + memset(&o_cmd, 0, sizeof(host_fw_command_struct)); // Issue full boot mode cmd though EXP-FW REQ buffer + // Explicit with all of these (including 0 values) to avoid ambiguity o_cmd.cmd_id = mss::exp::omi::EXP_FW_DDR_PHY_INIT; - o_cmd.cmd_flags = 0; - // TK - Fabricated value need to figure out if we'll be creating req_id tables - o_cmd.request_identifier = 0xBB; - o_cmd.cmd_length = 0; + // Retrieve a unique sequence id for this transaction + uint32_t l_counter = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OCMB_COUNTER, i_target, l_counter)); + o_cmd.request_identifier = l_counter; + + // With cmd_length > 0, data exists in the extended data buffer. Must set cmd_flags to 1. However, + // eye capture step 2 needs cmd_flags to be set to zero as defined in MCHP spec section 5.4.3 Eye Capture + // despite having data in the extended data buffer + o_cmd.cmd_flags = ((i_cmd_length > 0) && (i_phy_init_mode != phy_init_mode::EYE_CAPTURE_STEP_2)) ? 1 : 0; + + o_cmd.cmd_length = i_cmd_length; o_cmd.cmd_crc = i_cmd_data_crc; o_cmd.host_work_area = 0; o_cmd.cmd_work_area = 0; - memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); + + // According to the spec Table 5-2, phy_init_mode takes the place of command_argument[0] + o_cmd.command_argument[0] = i_phy_init_mode; + +fapi_try_exit: + return fapi2::current_err; } /// @@ -77,6 +424,7 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C FAPI_TRY(l_rc, "Unable to instantiate phy_params for target %s", mss::c_str(i_target)); // Set the params by fetching them from the attributes + FAPI_TRY(l_set_phy_params.set_version_number(o_phy_params)); FAPI_TRY(l_set_phy_params.setup_DimmType(o_phy_params)); FAPI_TRY(l_set_phy_params.setup_CsPresent(o_phy_params)); FAPI_TRY(l_set_phy_params.setup_DramDataWidth(o_phy_params)); @@ -89,9 +437,11 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C FAPI_TRY(l_set_phy_params.set_SpdCLSupported(o_phy_params)); FAPI_TRY(l_set_phy_params.set_SpdtAAmin(o_phy_params)); FAPI_TRY(l_set_phy_params.set_Rank4Mode(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_EncodedQuadCs(o_phy_params)); FAPI_TRY(l_set_phy_params.set_DDPCompatible(o_phy_params)); FAPI_TRY(l_set_phy_params.set_TSV8HSupport(o_phy_params)); FAPI_TRY(l_set_phy_params.set_MRAMSupport(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_MDSSupport(o_phy_params)); FAPI_TRY(l_set_phy_params.set_NumPStates(o_phy_params)); FAPI_TRY(l_set_phy_params.set_Frequency(o_phy_params)); FAPI_TRY(l_set_phy_params.set_PhyOdtImpedance(o_phy_params)); @@ -133,7 +483,10 @@ fapi2::ReturnCode setup_phy_params(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C FAPI_TRY(l_set_phy_params.set_RcdDBDic(o_phy_params)); FAPI_TRY(l_set_phy_params.set_RcdSlewRate(o_phy_params)); - FAPI_TRY(l_set_phy_params.set_EmulationSupport(o_phy_params)); + + FAPI_TRY(l_set_phy_params.set_DFIMRL_DDRCLK(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ATxDly_A(o_phy_params)); + FAPI_TRY(l_set_phy_params.set_ATxDly_B(o_phy_params)); } return fapi2::FAPI2_RC_SUCCESS; @@ -152,15 +505,29 @@ namespace check /// @return FAPI2_RC_SUCCESS iff okay /// fapi2::ReturnCode response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - const host_fw_response_struct& i_rsp) + const host_fw_response_struct& i_rsp, + const host_fw_command_struct& i_cmd) { + fapi2::buffer<uint32_t> l_error_code; + + l_error_code.insertFromRight<0, BITS_PER_BYTE>(i_rsp.response_argument[4]). + insertFromRight<BITS_PER_BYTE, BITS_PER_BYTE>(i_rsp.response_argument[3]). + insertFromRight<2 * BITS_PER_BYTE, BITS_PER_BYTE>(i_rsp.response_argument[2]). + insertFromRight<3 * BITS_PER_BYTE, BITS_PER_BYTE>(i_rsp.response_argument[1]); + // Check if cmd was successful - FAPI_ASSERT(i_rsp.response_argument[0] == omi::response_arg::SUCCESS, + FAPI_ASSERT(i_rsp.response_argument[0] == omi::response_arg::SUCCESS && + i_rsp.request_identifier == i_cmd.request_identifier, fapi2::MSS_EXP_RSP_ARG_FAILED(). set_TARGET(i_target). set_RSP_ID(i_rsp.response_id). - set_ERROR_CODE(i_rsp.response_argument[1]), - "Failed to initialize the PHY for %s", mss::c_str(i_target)); + set_ERROR_CODE(l_error_code). + set_EXPECTED_REQID(i_cmd.request_identifier). + set_ACTUAL_REQID(i_rsp.request_identifier), + "Failed to initialize the PHY for %s, response=0x%X, error_code=0x%08X " + "RSP RQ ID: %u CMD RQ ID: %u", + mss::c_str(i_target), i_rsp.response_argument[0], l_error_code, + i_rsp.request_identifier, i_cmd.request_identifier); return fapi2::FAPI2_RC_SUCCESS; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H index 7ffe531ce..096cfcd60 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_draminit_utils.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,8 @@ #define __MSS_EXP_DRAMINIT_UTILS__ #include <fapi2.H> +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> #include <lib/shared/exp_consts.H> #include <exp_data_structs.H> #include <mss_generic_attribute_getters.H> @@ -44,6 +46,10 @@ #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/find.H> #include <generic/memory/lib/utils/mss_buffer_utils.H> +#include <lib/phy/exp_train_display.H> +#include <lib/phy/exp_train_handler.H> +#include <exp_data_structs.H> +#include <stdio.h> namespace mss { @@ -51,13 +57,25 @@ namespace exp { /// +/// @brief Phy init mode for host_fw_command struct +/// +enum phy_init_mode +{ + NORMAL = 0, + EYE_CAPTURE_STEP_1 = 1, + EYE_CAPTURE_STEP_2 = 2, +}; + +/// /// @brief defines the supported DIMM types in Explorer /// enum msdg_dimm_types { - MSDG_UDIMM = 0x0000, - MSDG_RDIMM = 0x0001, - MSDG_LRDIMM = 0x0002, + MSDG_UDIMM = 0x0000, + MSDG_RDIMM = 0x0001, + MSDG_LRDIMM = 0x0002, + MSDG_MDS_LRDIMM = 0x0003, + MSDG_MDS = 0x0004 }; /// @@ -71,6 +89,15 @@ enum msdg_dram_data_width }; /// +/// @brief Defines CS encoding mode +/// +enum msdg_cs_encode_mode +{ + MSDG_QUAD_ENCODE_MODE = 1, + MSDG_DUAL_DIRECT_MODE = 0, +}; + +/// /// @brief defines the valid 3DS stack in Explorer /// enum msdg_height_3DS @@ -123,11 +150,154 @@ enum msdg_enable }; /// +/// @brief defines fields for the ODT RD/WR params +/// +enum odt_fields +{ + R2_FLD_LENGTH = 2, // R2 = 2 rank (normal / 2 rank mode: makes use of 2 bits) + R4_FLD_LENGTH = 4, // R4 = 4 rank (4 rank mode: makes use of 4 bits) + ODT_MIDPOINT = 4, + R4_SHIFT = 2, + RANK3 = 12, + RANK2 = 8, + RANK1 = 4, + RANK0 = 0, +}; + +/// +/// @brief Check that the rsp_data size returned from the PHY_INIT command matches the expected size +/// +/// @param[in] i_target OCMB target +/// @param[in] i_actual_size size enum expected for the given phy init mode +/// @param[in] i_mode phy init mode. Expected to be a valid enum value since we asserted as such in exp_draminit.C +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff matching, else MSS_EXP_INVALID_PHY_INIT_RSP_DATA_LENGTH +/// +fapi2::ReturnCode check_rsp_data_size( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint16_t i_actual_size, + const phy_init_mode i_mode); + +/// +/// @brief Perform normal host FW phy init +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC value +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode host_fw_phy_normal_init(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc); + +/// +/// @brief Perform host FW phy init with eye capture +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC value +/// @param[in] i_phy_params PHY params struct +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note the goal here is to attempt to send both phy_inits even in the event of a bad return code from the read & display +/// +fapi2::ReturnCode host_fw_phy_init_with_eye_capture(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc, + const user_input_msdg& i_phy_params); + +/// +/// @brief Process return codes from PHY init with eye capture operations +/// +/// @param[in] i_target OCMB target +/// @param[in] i_response_1 response struct for EYE_CAPTURE_STEP_1 +/// @param[in] i_response_2 response struct for EYE_CAPTURE_STEP_2 +/// @param[in] i_response_1_rc response from check_host_fw_response from EYE_CAPTURE_STEP_1 +/// @param[in] i_response_2_rc response from check_host_fw_response from EYE_CAPTURE_STEP_2 +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else an error from above as defined in the function algorithm +/// @note return codes are passed by value, caller should not expect these to change +/// +fapi2::ReturnCode process_eye_capture_return_codes(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg& i_response_1, + const user_2d_eye_response_2_msdg& i_response_2, + fapi2::ReturnCode i_response_1_rc, + fapi2::ReturnCode i_response_2_rc); + +/// +/// @brief Send PHY init command given the provided phy mode and CRC +/// +/// @param[in] i_target OCMB target +/// @param[in] i_crc CRC field +/// @param[in] i_phy_init_mode normal / eye capture step 1 or 2 +/// @param[out] host_fw_command_struct used for initialization +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode send_host_phy_init_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_crc, + const uint8_t i_phy_init_mode, + host_fw_command_struct& o_cmd); + +/// +/// @brief Get and check the host fw response from the explorer +/// @param[in] i_target OCMB chip +/// @param[in] i_cmd host_fw_command_struct used to generate the response +/// @param[out] o_rsp_data response data +/// @param[out] o_rc return code from mss::exp::check::response() +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode check_host_fw_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + host_fw_command_struct& i_cmd, + std::vector<uint8_t>& o_rsp_data, + fapi2::ReturnCode& o_rc); + +/// +/// @brief Reads and displays the normal draminit training response +/// +/// @param[in] i_target OCMB target +/// @param[in] i_resp_data RESP data +/// @param[in] i_rc return code from checking response +/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode read_and_display_normal_training_repsonse( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t> i_resp_data, + const fapi2::ReturnCode i_rc); + +/// +/// @brief Reads and displays the user 2d eye response 1 +/// +/// @tparam T response struct +/// @param[in] i_target OCMB target +/// @param[in] i_resp_data RESP data +/// @param[out] o_rc return code from checking response +/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff success +/// +template <typename T> +inline fapi2::ReturnCode read_and_display_user_2d_eye_response( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t> i_resp_data, + T& o_train_response) +{ + // Proccesses the response data + FAPI_TRY(mss::exp::read_user_2d_eye_response<T>(i_target, i_resp_data, o_train_response), + "Failed read_training_response for %s", mss::c_str(i_target)); + + // Displays the training response + FAPI_TRY(mss::exp::train::display_user_2d_eye_info<T>(i_target, o_train_response)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief host_fw_command_struct structure setup +/// @param[in] i_target the OCMB being acted upon /// @param[in] i_cmd_data_crc the command data CRC +/// @param[in] i_cmd_length the length of the command present in the data buffer (if any) +/// @param[in] i_phy_init_mode PHY init mode /// @param[out] o_cmd the command parameters to set +/// @return FAPI2_RC_SUCCESS iff okay /// -void setup_cmd_params(const uint32_t i_cmd_data_crc, host_fw_command_struct& o_cmd); +fapi2::ReturnCode setup_cmd_params( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint32_t i_cmd_data_crc, + const uint32_t i_cmd_length, + const uint8_t i_phy_init_mode, + host_fw_command_struct& o_cmd); /// /// @brief user_input_msdg structure setup @@ -148,10 +318,11 @@ struct phy_params_t /// /// Declare variables to be used /// + uint32_t iv_version_number; uint8_t iv_dimm_type[MAX_DIMM_PER_PORT]; - uint16_t iv_chip_select; + uint8_t iv_chip_select[MAX_DIMM_PER_PORT]; uint8_t iv_dram_data_width[MAX_DIMM_PER_PORT]; - uint16_t iv_height_3DS; + uint16_t iv_height_3DS[MAX_DIMM_PER_PORT]; uint16_t iv_dbyte_macro[MAX_DIMM_PER_PORT]; uint32_t iv_nibble[MAX_DIMM_PER_PORT]; uint8_t iv_addr_mirror[MAX_DIMM_PER_PORT]; @@ -160,14 +331,16 @@ struct phy_params_t uint32_t iv_spdcl_support; uint16_t iv_taa_min; uint8_t iv_rank4_mode[MAX_DIMM_PER_PORT]; + uint16_t iv_encoded_quadcs; uint8_t iv_ddp_compatible[MAX_DIMM_PER_PORT]; uint8_t iv_tsv8h[MAX_DIMM_PER_PORT]; uint8_t iv_mram_support[MAX_DIMM_PER_PORT]; + uint8_t iv_mdssupport; uint8_t iv_num_pstate[MAX_DIMM_PER_PORT]; uint64_t iv_frequency; uint8_t iv_odt_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint16_t iv_drv_impedance_pu[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint16_t iv_drv_impedance_pd[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_atx_impedance[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_atx_slew_rate[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; @@ -180,8 +353,8 @@ struct phy_params_t uint8_t iv_dram_dic[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_dram_preamble[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_phy_equalization[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; - uint8_t iv_init_vref_dq; - uint16_t iv_init_phy_vref; + uint8_t iv_init_vref_dq[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; + uint8_t iv_init_phy_vref[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_odt_wr_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_odt_rd_map_cs[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; uint8_t iv_geardown_mode[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]; @@ -193,7 +366,9 @@ struct phy_params_t uint8_t iv_f0rc7x[MAX_DIMM_PER_PORT]; uint8_t iv_f1rc00[MAX_DIMM_PER_PORT]; uint16_t iv_rcd_slew_rate; - uint8_t iv_firmware_mode; + uint8_t iv_dfimrl_ddrclk; + uint8_t iv_atxdly_a[DRAMINIT_NUM_ADDR_DELAYS]; + uint8_t iv_atxdly_b[DRAMINIT_NUM_ADDR_DELAYS]; }; /// @@ -208,6 +383,7 @@ class phy_params fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> iv_target; phy_params_t iv_params; + std::vector<mss::rank::info<>> iv_rank_info; public: @@ -219,17 +395,18 @@ class phy_params /// /// @brief fetch the attributes and initialize it to the params /// @param[in] i_target the fapi2 target - /// @param[in,out] o_rc the fapi2 output + /// @param[out] o_rc the fapi2 output /// phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - fapi2::ReturnCode o_rc): + fapi2::ReturnCode& o_rc): iv_target(i_target) { + uint8_t l_master_ranks[MAX_DIMM_PER_PORT] = {}; // Fetch attributes and populate the member variables FAPI_TRY(mss::attr::get_dimm_type(i_target, iv_params.iv_dimm_type)); - FAPI_TRY(mss::attr::get_exp_cs_present(i_target, iv_params.iv_chip_select)); + FAPI_TRY(mss::attr::get_dimm_ranks_configed(i_target, iv_params.iv_chip_select)); FAPI_TRY(mss::attr::get_dram_width(i_target, iv_params.iv_dram_data_width)); - FAPI_TRY(mss::attr::get_exp_3ds_height(i_target, iv_params.iv_height_3DS)); + FAPI_TRY(mss::attr::get_3ds_height(i_target, iv_params.iv_height_3DS)); FAPI_TRY(mss::attr::get_byte_enables(i_target, iv_params.iv_dbyte_macro)); FAPI_TRY(mss::attr::get_nibble_enables(i_target, iv_params.iv_nibble)); FAPI_TRY(mss::attr::get_exp_dram_address_mirroring(i_target, iv_params.iv_addr_mirror)); @@ -241,6 +418,7 @@ class phy_params FAPI_TRY(mss::attr::get_ddp_compatibility(i_target, iv_params.iv_ddp_compatible)); FAPI_TRY(mss::attr::get_tsv_8h_support(i_target, iv_params.iv_tsv8h)); FAPI_TRY(mss::attr::get_mram_support(i_target, iv_params.iv_mram_support)); + FAPI_TRY(mss::attr::get_dram_mds(i_target, iv_params.iv_mdssupport)); FAPI_TRY(mss::attr::get_pstates(i_target, iv_params.iv_num_pstate)); FAPI_TRY(mss::attr::get_freq(i_target, iv_params.iv_frequency)); FAPI_TRY(mss::attr::get_si_mc_rcv_imp_dq_dqs(i_target, iv_params.iv_odt_impedance)); @@ -271,7 +449,25 @@ class phy_params FAPI_TRY(mss::attr::get_dimm_ddr4_f0rc7x(i_target, iv_params.iv_f0rc7x)); FAPI_TRY(mss::attr::get_dimm_ddr4_f1rc00(i_target, iv_params.iv_f1rc00)); FAPI_TRY(mss::attr::get_exp_rcd_slew_rate(i_target, iv_params.iv_rcd_slew_rate)); - FAPI_TRY(mss::attr::get_exp_firmware_emulation_mode(i_target, iv_params.iv_firmware_mode)); + FAPI_TRY(mss::attr::get_exp_dfimrl_clk(i_target, iv_params.iv_dfimrl_ddrclk)); + FAPI_TRY(mss::attr::get_exp_atxdly_a(i_target, iv_params.iv_atxdly_a)); + FAPI_TRY(mss::attr::get_exp_atxdly_b(i_target, iv_params.iv_atxdly_b)); + + // TK update this if/when Microchip responds + iv_params.iv_version_number = DRAMINIT_STRUCTURE_VERSION; + + // We're in quad encoded mode IF + // 1) 4R per DIMM + // 2) we have an RDIMM + FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_master_ranks)); + { + const bool l_has_rcd = iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM || + iv_params.iv_dimm_type[0] == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM; + const bool l_4r = l_master_ranks[0] == fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R; + iv_params.iv_encoded_quadcs = (l_has_rcd && l_4r) ? MSDG_QUAD_ENCODE_MODE : MSDG_DUAL_DIRECT_MODE; + } + + FAPI_TRY(mss::rank::ranks_on_port(i_target, iv_rank_info)); fapi_try_exit: o_rc = fapi2::current_err; @@ -283,11 +479,14 @@ class phy_params /// @brief Set params as per the value initialized (useful for testing) /// @param[in] i_target the fapi2 target /// @param[in] i_phy_params explorer specific data structure + /// @param[out] o_rc Return code from rank API initialization /// phy_params(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - const phy_params_t& i_phy_params): + const phy_params_t& i_phy_params, + const std::vector<mss::rank::info<>> i_rank_info): iv_target(i_target), - iv_params(i_phy_params) + iv_params(i_phy_params), + iv_rank_info(i_rank_info) {} /// @@ -296,6 +495,129 @@ class phy_params ~phy_params() = default; /// + /// @brief Set the rank-based phy field from the attribute + /// + /// @param[in] i_phy_param_ranks array of pointers to the rank fields to be filled in + /// @param[in] i_phy_param_attr pointer to the iv array indexed by dimm & rank + /// @note this function assumes i_phy_param_ranks is properly populated with 4 fields (1 per phy rank) + /// + void set_phy_field_by_rank(const std::vector<uint16_t*>& i_phy_param_ranks, + const uint8_t (&i_phy_param_attr)[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM]) const + { + // First, zero everything out + for (uint8_t l_rank = 0; l_rank < i_phy_param_ranks.size(); ++l_rank) + { + *i_phy_param_ranks[l_rank] = 0; + } + + // For each rank, the phy rank value (0-4) is what needs to be filled in for draminit + // This maps to the field corresponding to the ATTR index value + // indexed by the rank's dimm index and dimm rank + for (const auto& l_rank : iv_rank_info) + { + const uint8_t l_dimm_index = mss::index(l_rank.get_dimm_target()); + const uint8_t l_dimm_rank = l_rank.get_dimm_rank(); + *i_phy_param_ranks[l_rank.get_phy_rank()] = i_phy_param_attr[l_dimm_index][l_dimm_rank]; + } + } + + /// + /// @brief Maps the ODT RD/WR attributes to the form needed for exp_draminit + /// + /// @param[in] i_odt_rd_wr_attr iv array indexed by dimm & rank + /// @param[out] o_odt_buffer buffer to populate + /// + fapi2::ReturnCode populate_odt_buffer(const uint8_t (&i_odt_rd_wr_attr)[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM], + fapi2::buffer<uint16_t>& o_odt_buffer) const + { + // TK - Update code for encoded quad CS, waiting on SPD + // static constexpr bool ENCODED_QUAD_CS_ENABLE = true; + + // Const vector to map phy ranks to their buffer offset position + const std::vector<uint8_t> l_buffer_rank_offset = + { + odt_fields::RANK0, + odt_fields::RANK1, + odt_fields::RANK2, + odt_fields::RANK3, + }; + + for (const auto& l_rank : iv_rank_info) + { + if (iv_params.iv_rank4_mode[0] == fapi2::ENUM_ATTR_MEM_EFF_FOUR_RANK_MODE_ENABLE) + { + // A & B separate. We need to do a bit if shifting from our attribute + // our attribute is aligned XX00YY00 but we want XXYY0000 + // The attr must be populated this way, as we only have 4 ODTs and they are aligned as such + // Otherwise, we have problems on the SPD/decoder side + // where XX is A0A1 (bits 0,1) and YY is B0B1 (bits 4,5) + + // From MCHP spec: + // OdtRdMapCs BIT [1:0] ODT_A[1:0] value when reading to rank 0 + // OdtRdMapCs BIT [3:2] ODT_B[1:0] value when reading to rank 0 + // ... + + const auto OFFSET = l_buffer_rank_offset[l_rank.get_phy_rank()]; + const auto DIMM_RANK = l_rank.get_dimm_rank(); + const auto DIMM_INDEX = mss::index(l_rank.get_dimm_target()); + + uint8_t l_data = 0; + + // l_data populated as such: + // XX000000 || 0000YY00 << 2 + l_data = i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK]; + l_data |= (i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK] << odt_fields::R4_SHIFT); + + // Sanity check: bitwise and the relevant bits + l_data &= 0b11110000; + + // Now we have XXYY0000 + // Insert into the buffer + FAPI_TRY(o_odt_buffer.insert(l_data, OFFSET, odt_fields::R4_FLD_LENGTH)); + } + // TK: need more information for encoded_quadcs (4U only) + // else if (iv_params.iv_encoded_quadcs == ENCODED_QUAD_CS_ENABLE) + // { + // } + else + { + // For DDIMM: + // A & B together. B0 (ODT2) mirrors A0 (ODT0), B1 (ODT3) mirrors A1 (ODT1) + // ODTA/B [1:0] == [ODT3/1:ODT2/0] + + // From MCHP spec: + // OdtRdMapCs BIT [1:0] ODTA/B[1:0] value when reading to rank 0 + // So it already accounts for any mirroring, we just need to plop in the value + + const auto OFFSET = l_buffer_rank_offset[l_rank.get_phy_rank()]; + const auto DIMM_RANK = l_rank.get_dimm_rank(); + const auto DIMM_INDEX = mss::index(l_rank.get_dimm_target()); + + uint8_t l_data = 0; + l_data = i_odt_rd_wr_attr[DIMM_INDEX][DIMM_RANK]; + + // Finally, put it back + + // Insert l_data (attribute) from the corresponding dimm's position: + // DIMM0 (ODT0, ODT1) (bits 0,1) or DIMM1 ODT0, ODT1 (bits 4,5) (though DIMM1 probably wouldn't be applicable here) + // at the offset to match the draminit field. + // + FAPI_TRY(o_odt_buffer.insert(l_data, OFFSET, odt_fields::R2_FLD_LENGTH, DIMM_INDEX * odt_fields::ODT_MIDPOINT)); + } + } + + // Rest of the buffer should already be zeroed from declaration + // Our attribute values come in left aligned (LSB left), our buffers are left aligned, but MCHP wants things right aligned: + // (rank0 == [1:0], rank1 == [5:4]) + // So we can set it up from the buffer perspective, but then flip the whole buffer, getting the values back to their + // correct form (MSB right aligned) in addition to flipping the rank positions to their expected locations + o_odt_buffer.reverse(); + + fapi_try_exit: + return fapi2::current_err; + } + + /// /// @brief user_input_msdg structure setup for parameter DimmType /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS iff okay @@ -308,6 +630,9 @@ class phy_params io_phy_params.DimmType = MSDG_RDIMM; break; + // TK this will need to be updated for the 4U explorer card + // For 1U/2U (what we're working on now), the DDIMM means an unregistered MC to DRAM interface + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM: case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM: io_phy_params.DimmType = MSDG_UDIMM; break; @@ -316,6 +641,14 @@ class phy_params io_phy_params.DimmType = MSDG_LRDIMM; break; + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_MDS_LRDIMM: + io_phy_params.DimmType = MSDG_MDS_LRDIMM; + break; + + case fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_MDS: + io_phy_params.DimmType = MSDG_MDS; + break; + default: const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(iv_target); FAPI_ASSERT(false, @@ -341,7 +674,14 @@ class phy_params /// fapi2::ReturnCode setup_CsPresent(user_input_msdg& io_phy_params) const { - io_phy_params.CsPresent = iv_params.iv_chip_select; + fapi2::buffer<uint8_t> l_cs_present(iv_params.iv_chip_select[0]); + + // Flip buffer (Needs to be right aligned, currently 0bXXXX0000) + l_cs_present.reverse(); + + // Now extend to 16 bits for phy_params struct + io_phy_params.CsPresent = static_cast<uint16_t>(l_cs_present); + return fapi2::FAPI2_RC_SUCCESS; } @@ -391,21 +731,21 @@ class phy_params /// fapi2::ReturnCode setup_Height3DS(user_input_msdg& io_phy_params) const { - switch (iv_params.iv_height_3DS) + switch (iv_params.iv_height_3DS[0]) { - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_PLANAR: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_PLANAR: io_phy_params.Height3DS = MSDG_PLANAR; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H2: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H2: io_phy_params.Height3DS = MSDG_H2; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H4: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H4: io_phy_params.Height3DS = MSDG_H4; break; - case fapi2::ENUM_ATTR_MEM_EXP_3DS_HEIGHT_H8: + case fapi2::ENUM_ATTR_MEM_3DS_HEIGHT_H8: io_phy_params.Height3DS = MSDG_H8; break; @@ -415,9 +755,9 @@ class phy_params fapi2::MSS_EXP_DRAMINIT_UNSUPPORTED_3DS_HEIGHT(). set_OCMB_TARGET(l_ocmb). set_PORT(iv_target). - set_HEIGHT(iv_params.iv_height_3DS), + set_HEIGHT(iv_params.iv_height_3DS[0]), "%s 3DS Height is not a supported (%d)", - mss::c_str(iv_target), iv_params.iv_height_3DS); + mss::c_str(iv_target), iv_params.iv_height_3DS[0]); break; } @@ -567,7 +907,8 @@ class phy_params /// fapi2::ReturnCode set_Frequency(user_input_msdg& io_phy_params) const { - io_phy_params.Frequency[0] = static_cast<uint16_t>(iv_params.iv_frequency); + // Divide by 2 to convert from DRAM freq to MEMCLK freq + io_phy_params.Frequency[0] = static_cast<uint16_t>(iv_params.iv_frequency / 2); return fapi2::FAPI2_RC_SUCCESS; } @@ -677,10 +1018,15 @@ class phy_params /// fapi2::ReturnCode set_RttNom(user_input_msdg& io_phy_params) const { - io_phy_params.DramRttNomR0[0] = iv_params.iv_dram_rtt_nom[0][0]; - io_phy_params.DramRttNomR1[0] = iv_params.iv_dram_rtt_nom[0][1]; - io_phy_params.DramRttNomR2[0] = iv_params.iv_dram_rtt_nom[0][2]; - io_phy_params.DramRttNomR3[0] = iv_params.iv_dram_rtt_nom[0][3]; + const std::vector<uint16_t*> l_rtt_noms = + { + &io_phy_params.DramRttNomR0[0], + &io_phy_params.DramRttNomR1[0], + &io_phy_params.DramRttNomR2[0], + &io_phy_params.DramRttNomR3[0], + }; + + set_phy_field_by_rank(l_rtt_noms, iv_params.iv_dram_rtt_nom); return fapi2::FAPI2_RC_SUCCESS; } @@ -691,10 +1037,15 @@ class phy_params /// fapi2::ReturnCode set_RttWr(user_input_msdg& io_phy_params) const { - io_phy_params.DramRttWrR0[0] = iv_params.iv_dram_rtt_wr[0][0]; - io_phy_params.DramRttWrR1[0] = iv_params.iv_dram_rtt_wr[0][1]; - io_phy_params.DramRttWrR2[0] = iv_params.iv_dram_rtt_wr[0][2]; - io_phy_params.DramRttWrR3[0] = iv_params.iv_dram_rtt_wr[0][3]; + const std::vector<uint16_t*> l_rtt_wrs = + { + &io_phy_params.DramRttWrR0[0], + &io_phy_params.DramRttWrR1[0], + &io_phy_params.DramRttWrR2[0], + &io_phy_params.DramRttWrR3[0], + }; + + set_phy_field_by_rank(l_rtt_wrs, iv_params.iv_dram_rtt_wr); return fapi2::FAPI2_RC_SUCCESS; } @@ -705,10 +1056,15 @@ class phy_params /// fapi2::ReturnCode set_RttPark(user_input_msdg& io_phy_params) const { - io_phy_params.DramRttParkR0[0] = iv_params.iv_dram_rtt_park[0][0]; - io_phy_params.DramRttParkR1[0] = iv_params.iv_dram_rtt_park[0][1]; - io_phy_params.DramRttParkR2[0] = iv_params.iv_dram_rtt_park[0][2]; - io_phy_params.DramRttParkR3[0] = iv_params.iv_dram_rtt_park[0][3]; + const std::vector<uint16_t*> l_rtt_parks = + { + &io_phy_params.DramRttParkR0[0], + &io_phy_params.DramRttParkR1[0], + &io_phy_params.DramRttParkR2[0], + &io_phy_params.DramRttParkR3[0], + }; + + set_phy_field_by_rank(l_rtt_parks, iv_params.iv_dram_rtt_park); return fapi2::FAPI2_RC_SUCCESS; } @@ -756,7 +1112,7 @@ class phy_params /// fapi2::ReturnCode set_PhyEqualization(user_input_msdg& io_phy_params) const { - io_phy_params.PhyEqualization = iv_params.iv_phy_equalization[0][0]; + io_phy_params.PhyEqualization[0] = iv_params.iv_phy_equalization[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -767,7 +1123,7 @@ class phy_params /// fapi2::ReturnCode set_InitVrefDQ(user_input_msdg& io_phy_params) const { - io_phy_params.InitVrefDQ[0] = iv_params.iv_init_vref_dq; + io_phy_params.InitVrefDQ[0] = iv_params.iv_init_vref_dq[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -778,9 +1134,7 @@ class phy_params /// fapi2::ReturnCode set_InitPhyVref(user_input_msdg& io_phy_params) const { - // Attr Vref = percentage of VDDQ, Receiver Vref = VDDQ*PhyVref[6:0]/128 - // conversion is attr_value * 128 / 100 - io_phy_params.InitPhyVref[0] = iv_params.iv_init_phy_vref * 128 / 100; + io_phy_params.InitPhyVref[0] = iv_params.iv_init_phy_vref[0][0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -791,8 +1145,13 @@ class phy_params /// fapi2::ReturnCode set_OdtWrMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtWrMapCs[0] = iv_params.iv_odt_wr_map_cs[0][0]; - return fapi2::FAPI2_RC_SUCCESS; + fapi2::buffer<uint16_t> odt_wr_map_cs_buff; + + FAPI_TRY(populate_odt_buffer(iv_params.iv_odt_wr_map_cs, odt_wr_map_cs_buff)); + io_phy_params.OdtWrMapCs[0] = odt_wr_map_cs_buff; + + fapi_try_exit: + return fapi2::current_err; } /// @@ -802,8 +1161,13 @@ class phy_params /// fapi2::ReturnCode set_OdtRdMapCs(user_input_msdg& io_phy_params) const { - io_phy_params.OdtRdMapCs[0] = iv_params.iv_odt_rd_map_cs[0][0]; - return fapi2::FAPI2_RC_SUCCESS; + fapi2::buffer<uint16_t> odt_rd_map_cs_buff; + + FAPI_TRY(populate_odt_buffer(iv_params.iv_odt_rd_map_cs, odt_rd_map_cs_buff)); + io_phy_params.OdtRdMapCs[0] = odt_rd_map_cs_buff; + + fapi_try_exit: + return fapi2::current_err; } /// @@ -881,7 +1245,7 @@ class phy_params /// fapi2::ReturnCode set_RcdIBTCtrl(user_input_msdg& io_phy_params) const { - io_phy_params.RcdIBTCtrl = iv_params.iv_f0rc7x[0]; + io_phy_params.RcdIBTCtrl[0] = iv_params.iv_f0rc7x[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -892,7 +1256,7 @@ class phy_params /// fapi2::ReturnCode set_RcdDBDic(user_input_msdg& io_phy_params) const { - io_phy_params.RcdDBDic = iv_params.iv_f1rc00[0]; + io_phy_params.RcdDBDic[0] = iv_params.iv_f1rc00[0]; return fapi2::FAPI2_RC_SUCCESS; } @@ -903,18 +1267,75 @@ class phy_params /// fapi2::ReturnCode set_RcdSlewRate(user_input_msdg& io_phy_params) const { - io_phy_params.RcdSlewRate = iv_params.iv_rcd_slew_rate; + io_phy_params.RcdSlewRate[0] = iv_params.iv_rcd_slew_rate; + return fapi2::FAPI2_RC_SUCCESS; + } + + // Version 2 updates + + /// + /// @brief Get the value for parameter version_number + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_version_number(user_input_msdg& io_phy_params) const + { + io_phy_params.version_number = iv_params.iv_version_number; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter version_number + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_EncodedQuadCs(user_input_msdg& io_phy_params) const + { + io_phy_params.EncodedQuadCs = iv_params.iv_encoded_quadcs; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter MDSSupport + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_MDSSupport(user_input_msdg& io_phy_params) const + { + io_phy_params.MDSSupport = iv_params.iv_mdssupport; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DFIMRL_DDRCLK + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_DFIMRL_DDRCLK(user_input_msdg& io_phy_params) const + { + io_phy_params.DFIMRL_DDRCLK = iv_params.iv_dfimrl_ddrclk; + return fapi2::FAPI2_RC_SUCCESS; + } + + /// + /// @brief Get the value for parameter DFIMRL_DDRCLK + /// @param[in,out] io_phy_params the phy params data struct + /// @return FAPI2_RC_SUCCESS + /// + fapi2::ReturnCode set_ATxDly_A(user_input_msdg& io_phy_params) const + { + memcpy(&io_phy_params.ATxDly_A[0][0], &iv_params.iv_atxdly_a[0], DRAMINIT_NUM_ADDR_DELAYS); return fapi2::FAPI2_RC_SUCCESS; } /// - /// @brief Get the value for parameter EmulationSupport + /// @brief Get the value for parameter DFIMRL_DDRCLK /// @param[in,out] io_phy_params the phy params data struct /// @return FAPI2_RC_SUCCESS /// - fapi2::ReturnCode set_EmulationSupport(user_input_msdg& io_phy_params) const + fapi2::ReturnCode set_ATxDly_B(user_input_msdg& io_phy_params) const { - io_phy_params.EmulationSupport = iv_params.iv_firmware_mode; + memcpy(&io_phy_params.ATxDly_B[0][0], &iv_params.iv_atxdly_b[0], DRAMINIT_NUM_ADDR_DELAYS); return fapi2::FAPI2_RC_SUCCESS; } }; @@ -925,11 +1346,13 @@ namespace check /// /// @brief Checks explorer response argument for a successful command /// @param[in] i_target OCMB target -/// @param[in] i_rsp response command +/// @param[in] i_rsp response from command +/// @param[in] i_cmd original command /// @return FAPI2_RC_SUCCESS iff okay /// fapi2::ReturnCode response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - const host_fw_response_struct& i_rsp); + const host_fw_response_struct& i_rsp, + const host_fw_command_struct& i_cmd); }//check diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.C index dcef63ec8..8c0d62f4e 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.C @@ -36,7 +36,8 @@ #include <lib/i2c/exp_i2c.H> #include <lib/shared/exp_consts.H> #include <explorer_scom_addresses.H> -#include <explorer_scom_addresses_fld.H> +#include <explorer_scom_addresses_fixes.H> +#include <explorer_scom_addresses_fld_fixes.H> #include <mss_explorer_attribute_setters.H> #include <generic/memory/lib/utils/mss_buffer_utils.H> @@ -49,33 +50,21 @@ namespace ecid { /// -/// @brief Determines enterprise and half dimm states from explorer FUSE +/// @brief Determines enterprise state from explorer FUSE /// @param[in] i_target the controller /// @param[out] o_enterprise_mode state -/// @param[out] o_half_dimm_mode state /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode get_enterprise_and_half_dimm_from_fuse( +fapi2::ReturnCode get_enterprise_from_fuse( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - uint8_t& o_enterprise_mode, - uint8_t& o_half_dimm_mode) + bool& o_enterprise_mode) { fapi2::buffer<uint64_t> l_reg_resp_buffer; FAPI_TRY(fapi2::getScom( i_target, static_cast<uint64_t>(EXPLR_EFUSE_IMAGE_OUT_0), l_reg_resp_buffer ), "exp_getecid: could not read explorer fuse register 0x%08x", EXPLR_EFUSE_IMAGE_OUT_0); - // Default to disabled - o_enterprise_mode = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_MODE_NON_ENTERPRISE; // 0 - - // If we support enterprise mode, enable it until otherwise overridden in OMI_SETUP - if(!l_reg_resp_buffer.getBit < EXPLR_EFUSE_IMAGE_OUT_0_ENTERPRISE_MODE_DIS - + mss::exp::ecid_consts::REG_BIT_OFFSET > ()) - { - o_enterprise_mode = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_MODE_ENTERPRISE; // 1, enabled - } - - // half_dimm_mode will remain disabled for P systems - o_half_dimm_mode = fapi2::ENUM_ATTR_MSS_OCMB_HALF_DIMM_MODE_FULL_DIMM; // 0, disabled + // Since the bit is a disable bit, take the opposite to get enable=true, disable=false + o_enterprise_mode = !(l_reg_resp_buffer.getBit<EXPLR_EFUSE_IMAGE_OUT_0_ENTERPRISE_MODE_DIS>()); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.H index cb8600c04..7b8fdfac9 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_getecid_utils.H @@ -47,16 +47,14 @@ namespace ecid { /// -/// @brief Determines enterprise and half dimm states from explorer FUSE +/// @brief Determines enterprise state from explorer FUSE /// @param[in] i_target the controller /// @param[out] o_enterprise_mode state -/// @param[out] o_half_dimm_mode state /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode get_enterprise_and_half_dimm_from_fuse( +fapi2::ReturnCode get_enterprise_from_fuse( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - uint8_t& o_enterprise_mode, - uint8_t& o_half_dimm_mode); + bool& o_enterprise_mode); /// /// @brief Reads ECID into output array from fuse diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.C new file mode 100644 index 000000000..6ddfd5bb7 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.C @@ -0,0 +1,176 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_thermal_init_utils.C +/// @brief Thermal initialization utility functions +/// +// *HWP HWP Owner: Sharath Manjunath <shamanj4@in.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/exp_mss_thermal_init_utils.H> +#include <lib/inband/exp_inband.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/c_str.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> + +namespace mss +{ +namespace exp +{ + +/// +/// @brief host_fw_command_struct structure setup +/// @param[out] o_cmd the command parameters to set +/// +void setup_sensor_interval_read_cmd_params(host_fw_command_struct& o_cmd) +{ + // Sets up EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ cmd params + // Command is used to configure interval read options for temperature sensors + o_cmd.cmd_id = mss::exp::omi::EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ; + o_cmd.cmd_flags = 0; + o_cmd.request_identifier = 0; + o_cmd.cmd_length = 0; + o_cmd.cmd_crc = 0xFFFFFFFF; + o_cmd.host_work_area = 0; + o_cmd.cmd_work_area = 0; + memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); + memset(o_cmd.command_argument, 0, sizeof(o_cmd.command_argument)); + o_cmd.command_argument[0] = 0x30; // i2c address of first sensor 0x30 + o_cmd.command_argument[1] = 0x14; // i2c address register offset 0x05, and size b00 (1 byte) + o_cmd.command_argument[2] = 0x00; // 2 and 3 together defines the interval + o_cmd.command_argument[3] = 0x1E; // interval in ms 30ms for first sensor + o_cmd.command_argument[4] = 0x32; // i2c address of second sensor 0x32 + o_cmd.command_argument[5] = 0x14; // i2c address register offset 0x05, and size b00 (1 byte) + o_cmd.command_argument[6] = 0x00; // 6 and 7 together defines the interval + o_cmd.command_argument[7] = 0x1E; // interval in ms 30ms for second sensor + o_cmd.command_argument[8] = 0x00; // 8 and 9 together defines the interval + o_cmd.command_argument[9] = 0x1E; // interval in ms 30ms for Onchip sensor +} + +namespace mc +{ + +/// +/// @brief set the N/M throttle register to safemode values +/// @param[in] i_target the ocmb target +/// @return fapi2::fapi2_rc_success if ok +/// @Will be overwritten by OCC/cronus later in IPL +/// +fapi2::ReturnCode setup_emergency_throttles(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + fapi2::buffer<uint64_t> l_data; + uint32_t l_n_safemode_throttle_value = 0; + uint32_t l_m_throttle_value = 0; + uint16_t l_nslot_safe = 0; + uint16_t l_nport_safe = 0; + + // Get the required values from the mrw attributes + FAPI_TRY(mss::attr::get_mrw_safemode_dram_databus_util(l_n_safemode_throttle_value), + "Error in setup_emergency_throttles" ); + FAPI_TRY(mss::attr::get_mrw_mem_m_dram_clocks(l_m_throttle_value), "Error in setup_emergency_throttles" ); + + // Get the register to be programmed using getScom + FAPI_TRY(fapi2::getScom(i_target, EXPLR_SRQ_MBA_FARB3Q, l_data), "Error in setup_emergency_throttles" ); + + // Calculate Nslot and Nport throttles and set l_data + // TK to use throttled_cmds function from commit 72525 + l_nslot_safe = (( l_n_safemode_throttle_value * l_m_throttle_value / 100 ) / 100 ) / 4; + l_nport_safe = l_nslot_safe; + l_data.insertFromRight<EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT, EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_SLOT_LEN> + (l_nslot_safe); + l_data.insertFromRight<EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT, EXPLR_SRQ_MBA_FARB3Q_CFG_NM_N_PER_PORT_LEN> + (l_nport_safe); + + // Write it back using putScom + FAPI_TRY(fapi2::putScom(i_target, EXPLR_SRQ_MBA_FARB3Q, l_data), "Error in setup_emergency_throttles" ); + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + FAPI_ERR("Error setting safemode throttles for target %s", mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief disable emergency mode throttle for thermal_init +/// @param[in] i_target the ocmb target +/// @return fapi2::fapi2_rc_success if ok +/// @note clears MB_SIM.SRQ.MBA_FARB7Q bit +/// +fapi2::ReturnCode disable_safe_mode_throttles (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + fapi2::buffer<uint64_t> l_data; + + // Get the register to be cleared + FAPI_TRY(fapi2::getScom(i_target, EXPLR_SRQ_MBA_FARB7Q, l_data)); + + // Clear the register and write it back to the address + l_data.clearBit<EXPLR_SRQ_MBA_FARB7Q_EMER_THROTTLE_IP>(); + FAPI_TRY(fapi2::putScom(i_target, EXPLR_SRQ_MBA_FARB7Q, l_data)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns mc + +namespace check +{ + +/// +/// @brief Checks explorer response argument for a successful command +/// @param[in] i_target OCMB target +/// @param[in] i_rsp response command +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode sensor_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp) +{ + // Check if cmd was successful + FAPI_ASSERT(i_rsp.response_argument[0] == mss::exp::omi::response_arg::SUCCESS, + fapi2::MSS_EXP_SENSOR_CACHE_ENABLE_FAILED(). + set_TARGET(i_target). + set_RSP_ID(i_rsp.response_id). + set_ERROR_CODE(i_rsp.response_argument[1]), + "Failed to enable sensor cache for %s", mss::c_str(i_target)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns check + +} // ns exp + +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.H new file mode 100644 index 000000000..fa9a3cf7b --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.H @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/exp_mss_thermal_init_utils.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mss_thermal_init_utils.H +/// @brief Thermal initialization utility functions +/// +// *HWP HWP Owner: Sharath Manjunath <shamanj4@in.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _EXP_MSS_THERMAL_INIT_UTILS_H_ +#define _EXP_MSS_THERMAL_INIT_UTILS_H_ + +#include <fapi2.H> +#include <mss_generic_attribute_getters.H> +#include <mss_explorer_attribute_getters.H> +#include <exp_data_structs.H> +#include <mss_generic_system_attribute_getters.H> + +namespace mss +{ +namespace exp +{ + +/// +/// @brief host_fw_command_struct structure setup +/// @param[out] o_cmd the command parameters to set +/// +void setup_sensor_interval_read_cmd_params(host_fw_command_struct& o_cmd); + +namespace mc +{ + +/// +/// @brief set the N/M throttle register to safemode values +/// @param[in] i_target the ocmb target +/// @return fapi2::fapi2_rc_success if ok +/// @Will be overwritten by OCC/cronus later in IPL +/// +fapi2::ReturnCode setup_emergency_throttles(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +/// +/// @brief disable emergency mode throttle for thermal_init +/// @param[in] i_target the ocmb target +/// @return fapi2::fapi2_rc_success if ok +/// @note clears MB_SIM.SRQ.MBA_FARB7Q bit +/// +fapi2::ReturnCode disable_safe_mode_throttles (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +} // ns mc + +namespace check +{ + +/// +/// @brief Checks explorer response argument for a successful command +/// @param[in] i_target OCMB target +/// @param[in] i_rsp response command +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode sensor_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp); + +} // ns check + +} // ns exp + +} // ns mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.C index 14054af10..55b5aea01 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/port.H $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H index 182dad7e6..84937976a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,27 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_fir.H +/// @brief Memory subsystem FIR support +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_FIR_H_ +#define _MSS_EXP_FIR_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/fir/gen_mss_fir.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> + +namespace mss +{ + +// FIR Register Traits for Explorer will be here sooner or later. + +} // end mss ns +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H new file mode 100644 index 000000000..3fb3460dc --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_fir_traits.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file exp_fir_traits.H +/// @brief Memory subsystem FIR support +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_FIR_TRAITS_H_ +#define _MSS_EXP_FIR_TRAITS_H_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/fir/gen_mss_fir.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> + +namespace mss +{ + +/// +/// @brief FIR Register Traits for Explorer MCBIST FIR +/// +template <> +struct firTraits<EXPLR_MCBIST_MCBISTFIRQ> +{ + static constexpr uint64_t REG = EXPLR_MCBIST_MCBISTFIRQ; + static constexpr uint64_t ACT0 = EXPLR_MCBIST_MCBISTFIRACT0; + static constexpr uint64_t ACT1 = EXPLR_MCBIST_MCBISTFIRACT1; + static constexpr uint64_t MASK = EXPLR_MCBIST_MCBISTFIRMASK; + static constexpr uint64_t MASK_AND = EXPLR_MCBIST_MCBISTFIRMASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_MCBIST_MCBISTFIRMASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +/// +/// @brief FIR Register Traits for Explorer SRQ FIR +/// +template <> +struct firTraits<EXPLR_SRQ_SRQFIRQ> +{ + static constexpr uint64_t REG = EXPLR_SRQ_SRQFIRQ; + static constexpr uint64_t ACT0 = EXPLR_SRQ_SRQFIR_ACTION0; + static constexpr uint64_t ACT1 = EXPLR_SRQ_SRQFIR_ACTION1; + static constexpr uint64_t MASK = EXPLR_SRQ_SRQFIR_MASK; + static constexpr uint64_t MASK_AND = EXPLR_SRQ_SRQFIR_MASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_SRQ_SRQFIR_MASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +/// +/// @brief FIR Register Traits for Explorer RDF FIR +/// +template <> +struct firTraits<EXPLR_RDF_FIR> +{ + static constexpr uint64_t REG = EXPLR_RDF_FIR; + static constexpr uint64_t ACT0 = EXPLR_RDF_ACTION0; + static constexpr uint64_t ACT1 = EXPLR_RDF_ACTION1; + static constexpr uint64_t MASK = EXPLR_RDF_MASK; + static constexpr uint64_t MASK_AND = EXPLR_RDF_MASK_AND; + static constexpr uint64_t MASK_OR = EXPLR_RDF_MASK_OR; + + // Target type of this register + static constexpr fapi2::TargetType T = fapi2::TARGET_TYPE_OCMB_CHIP; +}; + +} // end mss ns +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C index 701a0d87e..49137f3e2 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,178 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_unmask.C +/// @brief Subroutines for unmasking and setting up MSS FIR +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <lib/shared/exp_defaults.H> +#include <fapi2.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> +#include <generic/memory/lib/utils/scom.H> +#include <lib/fir/exp_fir.H> +#include <lib/fir/exp_fir_traits.H> +#include <generic/memory/lib/utils/fir/gen_mss_unmask.H> + +namespace mss +{ + +namespace unmask +{ + +/// +/// @brief Unmask and setup actions performed after draminit_mc +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_draminit_mc<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target ) +{ + fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc3 = fapi2::FAPI2_RC_SUCCESS; + + // Create registers and check success for MCBISTFIR and SRQFIR and RDFFIR + mss::fir::reg<EXPLR_MCBIST_MCBISTFIRQ> l_exp_mcbist_reg(i_target, l_rc1); + mss::fir::reg<EXPLR_SRQ_SRQFIRQ> l_exp_srq_reg(i_target, l_rc2); + mss::fir::reg<EXPLR_RDF_FIR> l_exp_rdf_reg(i_target, l_rc3); + + FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ); + FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ); + FAPI_TRY(l_rc3, "unable to create fir::reg for %d", EXPLR_RDF_FIR); + + // Write MCBISTFIR register per Explorer unmask spec + FAPI_TRY(l_exp_mcbist_reg.attention<EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE>() + .write()); + + // Write RDF FIR register per Explorer unmask spec + // TK Need to set EXPLR_RDF_FIR_MAINTENANCE_RCD to recoverable for planar/ISDIMM + FAPI_TRY(l_exp_rdf_reg.recoverable_error<EXPLR_RDF_FIR_MAINTENANCE_AUE>() + .recoverable_error<EXPLR_RDF_FIR_MAINTENANCE_IAUE>() + .recoverable_error<EXPLR_RDF_FIR_RDDATA_VALID_ERROR>() + .recoverable_error<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_STATUS>() + .recoverable_error<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_RECOVERABLE>() + .checkstop<EXPLR_RDF_FIR_SCOM_PARITY_CLASS_UNRECOVERABLE>() + .checkstop<EXPLR_RDF_FIR_ECC_CORRECTOR_INTERNAL_PARITY_ERROR>() + .recoverable_error<EXPLR_RDF_FIR_ECC_RBUF_CE_DW0>() + .recoverable_error<EXPLR_RDF_FIR_ECC_RBUF_CE_DW1>() + .checkstop<EXPLR_RDF_FIR_ECC_RBUF_UE_DW0>() + .checkstop<EXPLR_RDF_FIR_ECC_RBUF_UE_DW1>() + .write()); + + // Write SRQ FIR register per Explorer unmask spec + FAPI_TRY(l_exp_srq_reg.recoverable_error<EXPLR_SRQ_SRQFIRQ_REFRESH_OVERRUN>() + .write()); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +/// +/// @brief Unmask and setup actions performed after draminit_training +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_draminit_training<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target ) +{ + fapi2::ReturnCode l_rc1 = fapi2::FAPI2_RC_SUCCESS; + fapi2::ReturnCode l_rc2 = fapi2::FAPI2_RC_SUCCESS; + + // Create registers and check success for MCBISTFIR and SRQFIR + mss::fir::reg<EXPLR_MCBIST_MCBISTFIRQ> l_exp_mcbist_reg(i_target, l_rc1); + mss::fir::reg<EXPLR_SRQ_SRQFIRQ> l_exp_srq_reg(i_target, l_rc2); + + FAPI_TRY(l_rc1, "unable to create fir::reg for %d", EXPLR_MCBIST_MCBISTFIRQ); + FAPI_TRY(l_rc2, "unable to create fir::reg for %d", EXPLR_SRQ_SRQFIRQ); + + // Write MCBISTFIR register per Explorer unmask spec; omit bit 10 cmd_complete until draminit_mc + FAPI_TRY(l_exp_mcbist_reg.recoverable_error<EXPLR_MCBIST_MCBISTFIRQ_COMMAND_ADDRESS_TIMEOUT>() + .checkstop<EXPLR_MCBIST_MCBISTFIRQ_INTERNAL_FSM_ERROR>() + .checkstop<EXPLR_MCBIST_MCBISTFIRQ_CCS_ARRAY_UNCORRECT_CE_OR_UE>() + .recoverable_error<EXPLR_MCBIST_MCBISTFIRQ_SCOM_RECOVERABLE_REG_PE>() + .checkstop<EXPLR_MCBIST_MCBISTFIRQ_SCOM_FATAL_REG_PE>() + .write()); + + // Write SRQ FIR register per Explorer unmask spec + FAPI_TRY(l_exp_srq_reg.recoverable_error<EXPLR_SRQ_SRQFIRQ_NCF_MCB_LOGIC_ERROR>() + .checkstop<EXPLR_SRQ_SRQFIRQ_NCF_MCB_PARITY_ERROR>() + .recoverable_error<EXPLR_SRQ_SRQFIRQ_WRQ_RRQ_HANG_ERR>() + .checkstop<EXPLR_SRQ_SRQFIRQ_SM_1HOT_ERR>() + .checkstop<EXPLR_SRQ_SRQFIRQ_CMD_PARITY_ERROR>() + .checkstop<EXPLR_SRQ_SRQFIRQ_WDF_ERROR2>() + .checkstop<EXPLR_SRQ_SRQFIRQ_WDF_ERROR3>() + .recoverable_error<EXPLR_SRQ_SRQFIRQ_WDF_ERROR7>() + .checkstop<EXPLR_SRQ_SRQFIRQ_NCF_UE>() + .checkstop<EXPLR_SRQ_SRQFIRQ_NCF_LOGIC_ERROR>() + .checkstop<EXPLR_SRQ_SRQFIRQ_NCF_PARITY_ERROR>() + .recoverable_error<EXPLR_SRQ_SRQFIRQ_NCF_CORR_ERROR>() + .write()); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + return fapi2::current_err; +} + +/// +/// @brief Unmask and setup actions performed after mss_scominit +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// TODO: Need to implement this function +template<> +fapi2::ReturnCode after_scominit<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Unmask and setup actions performed after mss_ddr_phy_reset +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// TODO: Need to implement this function +template<> +fapi2::ReturnCode after_phy_reset<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Unmask and setup actions for memdiags related FIR +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// TODO: Need to implement this function +template<> +fapi2::ReturnCode after_memdiags<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Unmask and setup actions for scrub related FIR +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// TODO: Need to implement this function +template<> +fapi2::ReturnCode after_background_scrub<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + +} // end unmask ns +} // end mss ns diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.H deleted file mode 100644 index d147a4096..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/fir/exp_unmask.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/hwp_wrappers_exp.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/hwp_wrappers_exp.C new file mode 100644 index 000000000..03ba1a1de --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/hwp_wrappers_exp.C @@ -0,0 +1,169 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/hwp_wrappers_exp.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file hwp_wrappers_exp.C +/// @brief Main wrapper file for PRD calling Explorer memory procedure code +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include <fapi2.H> +#include <lib/shared/exp_defaults.H> +#include <lib/mcbist/exp_mcbist_traits.H> +#include <lib/dimm/exp_rank.H> +#include <lib/mc/exp_port.H> +#include <lib/mcbist/exp_mcbist.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_memdiags.H> + +/// +/// @brief Memdiags stop command wrapper for Explorer +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode exp_stop( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) +{ + return mss::memdiags::stop<mss::mc_type::EXPLORER>(i_target); +} + +/// +/// @brief Memdiags Super Fast Init command wrapper for Nimbus +/// @param[in] i_target the target behind which all memory should be initialized +/// @param[in] i_pattern an index representing a pattern to use to init memory (defaults to 0) +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode exp_sf_init( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_pattern ) +{ + return mss::memdiags::sf_init<mss::mc_type::EXPLORER>(i_target, i_pattern); +} + +/// +/// @brief Memdiags Super Fast Read command wrapper for Explorer +/// @param[in] i_target the target behind which all memory should be read +/// @param[in] i_stop stop conditions +/// @param[in] i_address mcbist::address representing the address from which to start. +// Defaults to the first address behind the target +/// @param[in] i_end whether to end, and where +/// Defaults to stop after slave rank +/// @param[in] i_end_address mcbist::address representing the address to end. +// Defaults to TT::LARGEST_ADDRESS +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode exp_sf_read( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>& i_stop, + const mss::mcbist::address& i_address, + const mss::mcbist::end_boundary i_end, + const mss::mcbist::address& i_end_address ) +{ + return mss::memdiags::sf_read<mss::mc_type::EXPLORER>(i_target, i_stop, i_address, i_end, i_end_address); +} + +/// +/// @brief Continuous background scrub command wrapper for Explorer +/// @param[in] i_target the target behind which all memory should be scrubbed +/// @param[in] i_stop stop conditions +/// @param[in] i_speed the speed to scrub +/// @param[in] i_address mcbist::address representing the address from which to start. +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode exp_background_scrub( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>& i_stop, + const mss::mcbist::speed i_speed, + const mss::mcbist::address& i_address ) +{ + return mss::memdiags::background_scrub<mss::mc_type::EXPLORER>(i_target, i_stop, i_speed, i_address); +} + +/// +/// @brief Targeted scrub command wrapper for Explorer +/// @param[in] i_target the target behind which all memory should be scrubbed +/// @param[in] i_stop stop conditions +/// @param[in] i_speed the speed to scrub +/// @param[in] i_start_address mcbist::address representing the address from which to start. +/// @param[in] i_end_address mcbist::address representing the address at which to end. +/// @param[in] i_end whether to end, and where +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode exp_targeted_scrub( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>& i_stop, + const mss::mcbist::address& i_start_address, + const mss::mcbist::address& i_end_address, + const mss::mcbist::end_boundary i_end ) +{ + return mss::memdiags::targeted_scrub<mss::mc_type::EXPLORER>(i_target, i_stop, i_start_address, i_end_address, i_end); +} + +/// +/// @brief Continue current command wrapper for Explorer +/// @param[in] i_target the target +/// @param[in] i_end whether to end, and where (default - don't stop at end of rank) +/// @param[in] i_stop stop conditions (default - 0 meaning 'don't change conditions') +/// @param[in] i_speed the speed to scrub (default - SAME_SPEED meaning leave speed untouched) +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode exp_continue_cmd( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::mcbist::end_boundary i_end, + const mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>& i_stop, + const mss::mcbist::speed i_speed ) +{ + return mss::memdiags::continue_cmd<mss::mc_type::EXPLORER>(i_target, i_end, i_stop, i_speed); +} + +/// +/// @brief Broadcast mode check wrapper for Explorer +/// @param[in] i_target the target to effect +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states exp_is_broadcast_capable(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + return mss::states::NO; +} + + +/// +/// @brief Broadcast mode check wrapper for Explorer +/// @param[in] i_targets the vector of targets to analyze +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states exp_is_broadcast_capable(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>>& i_targets) +{ + return mss::states::NO; +} + +/// +/// @brief Broadcast mode check wrapper for Explorer +/// @param[in] i_kinds the dimms to effect +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states exp_is_broadcast_capable(const std::vector<mss::dimm::kind<mss::mc_type::EXPLORER>>& i_kinds) +{ + return mss::states::NO; +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H index d834b102a..c430c650e 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,11 +38,27 @@ #include <fapi2.H> #include <i2c_access.H> - #include <vector> -#include <lib/i2c/exp_i2c_fields.H> -#include <generic/memory/lib/utils/pos.H> -#include <generic/memory/lib/utils/endian_utils.H> + +#ifdef __PPE__ + #include <exp_i2c_fields.H> + #include <endian_utils.H> +#else + #include <generic/memory/lib/utils/poll.H> + #include <lib/i2c/exp_i2c_fields.H> + #include <generic/memory/lib/utils/pos.H> + #include <generic/memory/lib/utils/endian_utils.H> +#endif + + +//Macro +#ifdef __PPE__ + #define TARGIDFORMAT "0x%08X" + #define TARGID i_target.get() +#else + #define TARGIDFORMAT "%s" + #define TARGID mss::c_str(i_target) +#endif namespace mss { @@ -58,24 +74,38 @@ namespace check /// @param[in] i_target the OCMB target /// @param[in] i_cmd_id the command ID /// @param[in] i_data data to check from EXP_FW_STATUS +/// @param[out] o_busy true if explorer returns FW_BUSY status, false otherwise +/// @return FAPI2_RC_SUCCESS iff okay /// inline fapi2::ReturnCode status_code( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint8_t i_cmd_id, - const std::vector<uint8_t>& i_data ) + const std::vector<uint8_t>& i_data, + bool& o_busy ) { + // Set o_busy to false just in case we don't make it to where we check it + o_busy = false; + // Set to a high number to make sure check for SUCCESS (== 0) isn't a fluke uint8_t l_status = ~(0); FAPI_TRY( status::get_status_code(i_target, i_data, l_status) ); + // We need to try again if we get a FW_BUSY status, so set the flag + if (l_status == status_codes::FW_BUSY) + { + o_busy = true; + return fapi2::FAPI2_RC_SUCCESS; + } + // Technically many cmds have their own status code decoding..but SUCCESS is always 0. // If it's anything else we can just look up the status code + FAPI_ASSERT( l_status == status_codes::SUCCESS, fapi2::MSS_EXP_I2C_FW_STATUS_CODE_FAILED(). set_TARGET(i_target). set_STATUS_CODE(l_status). set_CMD_ID(i_cmd_id), - "Status code did not return SUCCESS (%d), received (%d) for %s", - status_codes::SUCCESS, l_status, mss::c_str(i_target) ); + "Status code did not return SUCCESS (%d), received (%d) for " TARGIDFORMAT , + status_codes::SUCCESS, l_status, TARGID ); return fapi2::FAPI2_RC_SUCCESS; @@ -98,12 +128,26 @@ inline void fw_status_setup(size_t& o_size, o_cmd_id.push_back(FW_STATUS); } +#ifndef __PPE__ /// -/// @brief EXP_FW_STATUS +/// @brief EXP_FW_BYPASS_4SEC_TIMEOUT setup helper function +/// @param[out] o_cmd_id the explorer command ID +/// +inline void fw_bypass_download_window_setup(std::vector<uint8_t>& o_cmd_id) +{ + o_cmd_id.clear(); + o_cmd_id.push_back(FW_BYPASS_4SEC_TIMEOUT); +} +#endif + +/// +/// @brief get EXP_FW_STATUS bytes /// @param[in] i_target the OCMB target +/// @param[out] o_data the return data from FW_STATUS command /// @return FAPI2_RC_SUCCESS iff okay /// -inline fapi2::ReturnCode fw_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +inline fapi2::ReturnCode get_fw_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + std::vector<uint8_t>& o_data) { // Retrieve setup data size_t l_size = 0; @@ -111,18 +155,102 @@ inline fapi2::ReturnCode fw_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C fw_status_setup(l_size, l_cmd_id); // Get data and check for errors + FAPI_TRY(fapi2::getI2c(i_target, l_size, l_cmd_id, o_data)); + FAPI_DBG( "status returned ( 5 bytes ) : 0x%.02X 0x%.02X 0x%.02X 0x%.02X 0x%.02X", + o_data[0], o_data[1] , o_data[2], o_data[3], o_data[4]); +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Helper function to check FW_STATUS loop termination, for unit testing +/// @param[in] i_target the OCMB target +/// @param[in] i_busy busy flag from check::status_code +/// @param[in] i_boot_stage boot_stage output from status::get_boot_stage +/// @return true if we should break out of the loop, false otherwise +/// +inline bool fw_status_loop_done(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_busy, + const uint8_t i_boot_stage) +{ + constexpr uint8_t EXPECTED_BOOT_STAGE = boot_stages::RUNTIME_FW; + + if (i_busy) + { + FAPI_DBG( "%s reutrned FW_BUSY status. Retrying...", mss::c_str(i_target) ); + return false; + } + + if (i_boot_stage != EXPECTED_BOOT_STAGE) + { + FAPI_DBG( "%s reutrned non-RUNTIME boot stage (0x%02x). Retrying...", + mss::c_str(i_target), i_boot_stage ); + return false; + } + + return true; +} + +/// +/// @brief EXP_FW_STATUS +/// @param[in] i_target the OCMB target +/// @param[in] i_delay delay between polls +/// @param[in] i_loops number of polling loops to perform +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode fw_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_delay, + const uint64_t i_loops) +{ + constexpr uint8_t EXPECTED_BOOT_STAGE = boot_stages::RUNTIME_FW; + + // So, why aren't we using the memory team's polling API? + // This is a base function that will be utilized by the platform code + // As such, we don't want to pull in more libraries than we need to: it would cause extra dependencies + // So, we're decomposing the polling library below + //fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + bool l_busy = true; + uint8_t l_boot_stage = 0; + uint64_t l_loop = 0; + + // Loop until we max our our loop count or get a non-busy response + for(; l_loop < i_loops; ++l_loop) { std::vector<uint8_t> l_data; - FAPI_TRY(fapi2::getI2c(i_target, l_size, l_cmd_id, l_data)); - FAPI_INF( "status returned ( 5 bytes ) : 0x%.02X 0x%.02X 0x%.02X 0x%.02X 0x%.02X", - l_data[0], l_data[1] , l_data[2], l_data[3], l_data[4]); - FAPI_TRY( check::status_code(i_target, l_cmd_id[0], l_data) ); + FAPI_TRY( get_fw_status(i_target, l_data) ); + FAPI_TRY( check::status_code(i_target, FW_STATUS, l_data, l_busy) ); + FAPI_TRY( status::get_boot_stage(i_target, l_data, l_boot_stage) ); + + if (fw_status_loop_done(i_target, l_busy, l_boot_stage)) + { + break; + } + + FAPI_TRY( fapi2::delay( i_delay, 200) ); } + FAPI_DBG(TARGIDFORMAT " stopped on loop %u/%u", TARGID , l_loop, i_loops); + // Check that Explorer is not still in FW_BUSY state + + FAPI_ASSERT( !l_busy, + fapi2::MSS_EXP_I2C_FW_STATUS_BUSY(). + set_TARGET(i_target), + "Polling timeout on FW_STATUS command (still FW_BUSY) for " TARGIDFORMAT, + TARGID ); + // Check that Explorer is in RUNTIME_FW boot stage + FAPI_ASSERT( (l_boot_stage == EXPECTED_BOOT_STAGE), + fapi2::MSS_EXP_I2C_WRONG_BOOT_STAGE(). + set_TARGET(i_target). + set_BOOT_STAGE(l_boot_stage). + set_EXPECTED_BOOT_STAGE(EXPECTED_BOOT_STAGE), + "Polling timeout on FW_STATUS command (wrong boot stage: 0x%01x, expected 0x%01x) for " TARGIDFORMAT, + l_boot_stage, EXPECTED_BOOT_STAGE, TARGID ); + fapi_try_exit: return fapi2::current_err; } +#ifndef __PPE__ /// /// @brief EXP_FW_BOOT_CONFIG setup /// @param[in,out] io_data the data to go to boot config @@ -159,9 +287,47 @@ inline fapi2::ReturnCode boot_config(const fapi2::Target<fapi2::TARGET_TYPE_OCMB std::vector<uint8_t> l_configured_data(i_data); boot_config_setup(l_configured_data); - // Get data and check for errors + // Send the command FAPI_TRY(fapi2::putI2c(i_target, l_configured_data)); - FAPI_TRY(fw_status(i_target)); + + // Wait a bit for the command (DLL lock and OMI training) to complete + // Value based on initial Explorer hardware. + // The command takes ~300ms and we poll for around 100ms, so wait 250ms here + FAPI_TRY( fapi2::delay( (mss::DELAY_1MS * 250), 200) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check that the FW status code returns a busy status (expected for exp_omi_train) +/// +/// @param[in] i_target OCMB +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff busy and no error code, else, error code +/// +inline fapi2::ReturnCode check_fw_status_busy(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + uint8_t l_status = ~(0); + + std::vector<uint8_t> l_data; + FAPI_TRY(get_fw_status(i_target, l_data)); + + FAPI_TRY(status::get_status_code(i_target, l_data, l_status)); + + // Post bootconfig1, we should see a busy status until p9a_omi_train is kicked off (setting axone to AUTO_TRAIN) + // explorer will return busy status until then. if we have another status, then we may not have executed bootconfig1 + // or some previous command correctly, so we should check it here + // After p9a_omi_train, exp_omi_train_check will check fw_status for success (in addition to checking training completion) + // to make sure things went smoothly + FAPI_ASSERT( l_status == status_codes::FW_BUSY, + fapi2::MSS_EXP_I2C_FW_BOOT_CONFIG_STATUS_CODE_INVALID(). + set_TARGET(i_target). + set_STATUS_CODE(l_status). + set_CMD_ID(FW_STATUS), + "Status code did not return BUSY (%d) as expected post BOOT_CONFIG1, received (%d) for " TARGIDFORMAT , + status_codes::FW_BUSY, l_status, TARGID ); + + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: return fapi2::current_err; @@ -180,13 +346,98 @@ inline fapi2::ReturnCode is_ready(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CH std::vector<uint8_t> l_cmd_id; fw_status_setup(l_size, l_cmd_id); - // We just ignore the data. We'll see FAPI2_RC_SUCCESS if - // the I2C returns an ACK. + // We'll see FAPI2_RC_SUCCESS if the I2C returns an ACK. + // We just ignore the data std::vector<uint8_t> l_data; return fapi2::getI2c(i_target, l_size, l_cmd_id, l_data); } /// +/// @brief EXP_FW_BYPASS_4SEC_TIMEOUT +/// @param[in] i_target the OCMB target +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode fw_bypass_download_window(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + std::vector<uint8_t> l_cmd_id; + fw_bypass_download_window_setup(l_cmd_id); + + // We'll see FAPI2_RC_SUCCESS if the I2C returns an ACK. + return fapi2::putI2c(i_target, l_cmd_id); +} + +/// +/// @brief Helper function for exp_check_for_ready +/// @param[in] i_target the controller +/// @param[in] i_poll_count the number of times to run the fw_status command (default = 200) +/// @param[in] i_delay delay in ns between fw_status command attempts (default = 1ms) +/// @return FAPI2_RC_SUCCESS iff ok +/// +inline fapi2::ReturnCode exp_check_for_ready_helper(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_poll_count = 200, + const uint64_t i_delay = DELAY_1MS) +{ + std::vector<uint8_t> l_data; + uint8_t l_boot_stage = 0; + + // Using using default parameters from class, with overrides for delay and poll_count + mss::poll_parameters l_poll_params(DELAY_10NS, + 200, + i_delay, + 200, + i_poll_count); + + // From MSCC explorer firmware arch spec + // 4.1.5: After power-up, the Explorer Chip will respond with NACK to all incoming I2C requests + // from the HOST until the I2C slave interface is ready to receive commands. + FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool + { + return mss::exp::i2c::is_ready(i_target) == fapi2::FAPI2_RC_SUCCESS; + }), + fapi2::MSS_EXP_I2C_POLLING_TIMEOUT(). + set_TARGET(i_target), + "Failed to see an ACK from I2C -- polling timeout on %s", + mss::c_str(i_target) ); + + // If we're already in RUNTIME_FW stage, due to fuse settings or running procedures manually, + // we can (and should) skip the bypass and polling here + FAPI_TRY( get_fw_status(i_target, l_data) ); + FAPI_TRY( status::get_boot_stage(i_target, l_data, l_boot_stage) ); + + if (l_boot_stage == boot_stages::RUNTIME_FW) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + // MSCC explorer firmware arch spec 4.1.6.5 + // Boot ROM will wait 4 secs and will proceed for normal boot operation. During this time, + // I2C channel will be disabled and Host will see NACK on the bus for subsequent EXP_FW_STATUS + // command. + // Sending FW_BYPASS_4SEC_TIMEOUT command will bypass the 4 secs + // and immediately load the runtime firmware. + FAPI_TRY(fw_bypass_download_window(i_target)); + + // Loop again until we get an ACK from i2c + FAPI_ASSERT( mss::poll(i_target, l_poll_params, [i_target]()->bool + { + return mss::exp::i2c::is_ready(i_target) == fapi2::FAPI2_RC_SUCCESS; + }), + fapi2::MSS_EXP_I2C_POLLING_TIMEOUT(). + set_TARGET(i_target), + "Failed to see an ACK from I2C -- polling timeout on %s", + mss::c_str(i_target) ); + + // Now poll the EXP_FW_STATUS command until it returns SUCCESS and RUNTIME_FW + FAPI_TRY(fw_status(i_target, i_delay, i_poll_count)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +#endif +/// /// @brief Perform a register write operation on the given OCMB chip /// @param[in] i_target the OCMB target /// @param[in] i_addr The translated address on the OCMB chip @@ -199,7 +450,7 @@ inline fapi2::ReturnCode fw_reg_write(const fapi2::Target<fapi2::TARGET_TYPE_OC { // create byte vector that will hold command bytes in sequence that will do the scom std::vector<uint8_t> l_cmd_vector; - std::vector<uint8_t> l_be_vector; + std::vector<uint8_t> l_byte_vector; uint32_t l_input_data = static_cast<uint32_t>(i_data_buffer); @@ -211,14 +462,21 @@ inline fapi2::ReturnCode fw_reg_write(const fapi2::Target<fapi2::TARGET_TYPE_OC // write them directly to the cmd_vector in the same order they // currently are // Byte 2:5 = Address - forceBE(i_addr, l_be_vector); - l_cmd_vector.insert(l_cmd_vector.end(), l_be_vector.begin(), l_be_vector.end()); + forceBE(i_addr, l_byte_vector); + + for(const auto l_byte : l_byte_vector) + { + l_cmd_vector.push_back(l_byte); + } - l_be_vector.clear(); - forceBE(l_input_data, l_be_vector); + l_byte_vector.clear(); + forceBE(l_input_data, l_byte_vector); // Byte 6:9 = Data - l_cmd_vector.insert(l_cmd_vector.end(), l_be_vector.begin(), l_be_vector.end()); + for(const auto l_byte : l_byte_vector) + { + l_cmd_vector.push_back(l_byte); + } // Use fapi2 putI2c interface to execute command FAPI_TRY(fapi2::putI2c(i_target, l_cmd_vector), @@ -226,7 +484,7 @@ inline fapi2::ReturnCode fw_reg_write(const fapi2::Target<fapi2::TARGET_TYPE_OC i_addr, mss::fapi_pos(i_target)); // Check status of operation - FAPI_TRY(fw_status(i_target), + FAPI_TRY(fw_status(i_target, DELAY_1MS, 100), "Invalid Status after FW_REG_WRITE operation to 0x%.8X on OCMB w/ fapiPos = 0x%.8X", i_addr, mss::fapi_pos(i_target)); @@ -248,13 +506,13 @@ inline fapi2::ReturnCode fw_reg_read(const fapi2::Target<fapi2::TARGET_TYPE_OCMB { // create byte vector that will hold command bytes in sequence that will do the scom std::vector<uint8_t> l_cmd_vector; - std::vector<uint8_t> l_tmp_vector; + std::vector<uint8_t> l_byte_vector; // Flush o_data_buffer w/ all 0's to avoid stale data o_data_buffer.flush<0>(); // Force the address to be BE - forceBE(i_addr, l_tmp_vector); + forceBE(i_addr, l_byte_vector); // Build the cmd vector for the Read l_cmd_vector.push_back(FW_REG_ADDR_LATCH); // Byte 0 = 0x03 (FW_REG_ADDR_LATCH) @@ -264,7 +522,11 @@ inline fapi2::ReturnCode fw_reg_read(const fapi2::Target<fapi2::TARGET_TYPE_OCMB // directly to the cmd_vector in the same order it // currently is in // Byte 2:5 = Address - l_cmd_vector.insert(l_cmd_vector.end(), l_tmp_vector.begin(), l_tmp_vector.end()); + + for(const auto l_byte : l_byte_vector) + { + l_cmd_vector.push_back(l_byte); + } // Use fapi2 putI2c interface to execute command FAPI_TRY(fapi2::putI2c(i_target, l_cmd_vector), @@ -272,43 +534,51 @@ inline fapi2::ReturnCode fw_reg_read(const fapi2::Target<fapi2::TARGET_TYPE_OCMB i_addr, mss::fapi_pos(i_target)); // Check i2c status after operation - FAPI_TRY(fw_status(i_target), + FAPI_TRY(fw_status(i_target, DELAY_1MS, 100), "Invalid Status after FW_REG_ADDR_LATCH operation to 0x%.8X on OCMB w/ fapiPos = 0x%.8X", i_addr, mss::fapi_pos(i_target)); - // Clear out the tmp_vector because we will re-use as the read buffer - l_tmp_vector.clear(); - // Clear out cmd vector as i2c op is complete and we must prepare for next l_cmd_vector.clear(); // Cmd vector is a single byte with FW_REG_READ code l_cmd_vector.push_back(FW_REG_READ); // Byte 0 = 0x04 (FW_REG_READ) - l_cmd_vector.push_back(0x4); // Remaining bytes dont matter to HB firmware - l_cmd_vector.push_back(0x0); // but the hw is expecting something there so - l_cmd_vector.push_back(0x0); // we should write something - l_cmd_vector.push_back(0x0); - l_cmd_vector.push_back(0x0); + l_cmd_vector.push_back(0x4); // length of read + + // i_addr was converted to BE above so we can write it + // directly to the cmd_vector in the same order it + // currently is in + // Byte 2:5 = Address + // NOTE: Techinically Explorer says this is not needed but was found + // to be needed in Gemini and Explorer says they don't care why the + // next 4 bytes are so we will fill it in regardless + for(const auto l_byte : l_byte_vector) + { + l_cmd_vector.push_back(l_byte); + } + + // Clear out the tmp_vector because we will re-use as the read buffer + l_byte_vector.clear(); // Use fapi2 getI2c interface to execute command - FAPI_TRY(fapi2::getI2c(i_target, FW_I2C_SCOM_READ_SIZE, l_cmd_vector, l_tmp_vector), + FAPI_TRY(fapi2::getI2c(i_target, FW_I2C_SCOM_READ_SIZE, l_cmd_vector, l_byte_vector), "getI2c returned error for FW_REG_READ operation to 0x%.8X on OCMB w/ fapiPos = 0x%.8X", i_addr, mss::fapi_pos(i_target)); // The first byte returned should be the size of the remaining data // We requested FW_REG_ADDR_LATCH_SIZE bytes so that is what we // expect to see as the first byte. - FAPI_ASSERT( (l_tmp_vector.front() == FW_REG_ADDR_LATCH_SIZE), + FAPI_ASSERT( (l_byte_vector.front() == FW_REG_ADDR_LATCH_SIZE), fapi2::I2C_GET_SCOM_INVALID_READ_SIZE() .set_TARGET(i_target) .set_ADDRESS(i_addr) - .set_SIZE_RETURNED(l_tmp_vector[0]) + .set_SIZE_RETURNED(l_byte_vector[0]) .set_SIZE_REQUESTED(FW_REG_ADDR_LATCH_SIZE), "First byte of read data was expected to be 0x%lx but byte read = 0x%x", - FW_REG_ADDR_LATCH_SIZE, l_tmp_vector[0] ); + FW_REG_ADDR_LATCH_SIZE, l_byte_vector[0] ); // Check i2c status after operation - FAPI_TRY(fw_status(i_target), + FAPI_TRY(fw_status(i_target, DELAY_1MS, 100), "Invalid Status after FW_REG_READ operation to 0x%.8X on OCMB w/ fapiPos = 0x%.8X", i_addr, mss::fapi_pos(i_target)); @@ -316,10 +586,10 @@ inline fapi2::ReturnCode fw_reg_read(const fapi2::Target<fapi2::TARGET_TYPE_OCMB // returned in BE so no translation neccesary. Faster to just access // the 4 bytes and shift than to perform vector operations to pop off front // entry and convert vector to uint32. - o_data_buffer = ( l_tmp_vector[1] << 24 | - l_tmp_vector[2] << 16 | - l_tmp_vector[3] << 8 | - l_tmp_vector[4]); + o_data_buffer = ( l_byte_vector[1] << 24 | + l_byte_vector[2] << 16 | + l_byte_vector[3] << 8 | + l_byte_vector[4]); fapi_try_exit: return fapi2::current_err; } @@ -350,6 +620,56 @@ inline uint32_t trans_micro_i2c_scom_addr(const uint32_t i_addr) return (i_addr | OCMB_UNCACHED_OFFSET) ; } +#ifndef __PPE__ + +/// +/// @brief Issue the DOWNLOAD command to the given OCMB chip +/// @param[in] i_target the OCMB target +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode fw_download(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + // create byte vector that will hold command bytes in sequence that will do the scom + std::vector<uint8_t> l_download_cmd; + std::vector<uint8_t> l_status_data; + uint8_t l_boot_stage = 0; + + // Read status to get the current boot_stage + FAPI_TRY(get_fw_status(i_target, l_status_data)); + + // Extract the boot_stage value + FAPI_TRY(status::get_boot_stage(i_target, l_status_data, l_boot_stage)); + + // Check that we are in the BOOT_ROM or FW_UPGRADE stage of booting. + // The FW_DOWNLOAD command can only be sent in one of these modes + // (see table 13-1, pboot flowchart in FW arch doc for more info) + FAPI_ASSERT(((l_boot_stage == BOOT_ROM_STAGE) || + (l_boot_stage == FW_UPGRADE_MODE)), + fapi2::MSS_EXP_I2C_FW_DOWNLOAD_INVALID_STATE(). + set_TARGET(i_target). + set_BOOT_STAGE(l_boot_stage). + set_STATUS_DATA(l_status_data), + "Invalid boot stage[0x%02x] for FW_DOWNLOAD command on %s", + l_boot_stage, mss::c_str(i_target)); + + // Start building the cmd vector for the write operation + // Byte 0 = 0x06 (FW_DOWNLOAD) + l_download_cmd.push_back(FW_DOWNLOAD); + + // Use fapi2 putI2c interface to execute command + FAPI_TRY(fapi2::putI2c(i_target, l_download_cmd), + "I2C FW_DOWNLOAD op failed to send FW_DOWNLOAD cmd to %s", + mss::c_str(i_target)); + + // NOTE: The EXP_FW_STATUS command will not work after sending the + // EXP_FW_DOWNLOAD because we will be in TWI mode from this point on. + +fapi_try_exit: + return fapi2::current_err; +} + +#endif + }// i2c }// exp }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.C index 822c518d3..c1c9c31a9 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -23,6 +23,7 @@ /* */ /* IBM_PROLOG_END_TAG */ #include <lib/i2c/exp_i2c_fields.H> +#include <generic/memory/lib/utils/find.H> namespace mss { @@ -33,7 +34,7 @@ namespace i2c // If a constexpr static data member (since C++11) is odr-used, // a definition at namespace scope is still required, but it cannot have an initializer. -constexpr mss::field_t<mss::endian::BIG> fields::BOOT_MODE; +constexpr mss::field_t<mss::endian::BIG> fields::DFE_DISABLE; constexpr mss::field_t<mss::endian::BIG> fields::LANE_MODE; constexpr mss::field_t<mss::endian::BIG> fields::SERDES_FREQ; constexpr mss::field_t<mss::endian::BIG> fields::FW_MODE; @@ -44,6 +45,49 @@ constexpr mss::field_t<mss::endian::BIG> fields::CMD_ID; constexpr mss::field_t<mss::endian::BIG> fields::STATUS_CODE; constexpr mss::field_t<mss::endian::BIG> fields::BOOT_STAGE; +namespace boot_cfg +{ + +/// +/// @brief SERDES_FREQ setter +/// @param[in] i_target the OCMB target +/// @param[in,out] io_data the buffer as a reference to a vector +/// @param[in] i_freq frequency to set +/// @return FAPI2_RC_SUCCESS iff okay +/// +fapi2::ReturnCode set_serdes_freq(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + std::vector<uint8_t>& io_data, + const uint32_t i_freq) +{ + static const std::vector< std::pair<uint32_t, uint8_t> > OMI_FREQ_MAP = + { + {fapi2::ENUM_ATTR_FREQ_OMI_MHZ_21330, 1}, + {fapi2::ENUM_ATTR_FREQ_OMI_MHZ_23460, 2}, + {fapi2::ENUM_ATTR_FREQ_OMI_MHZ_25600, 3}, + // All others reserved or not supported + }; + + uint8_t l_setting = 0; + const bool l_is_val_found = mss::find_value_from_key(OMI_FREQ_MAP, i_freq, l_setting); + + FAPI_ASSERT( l_is_val_found, + fapi2::MSS_LOOKUP_FAILED() + .set_KEY(i_freq) + .set_DATA(l_setting) + .set_FUNCTION(SET_SERDES_FREQ) + .set_TARGET(i_target), + "Failed to find a BOOT_CONFIG setting for OMI value %d on %s", + i_freq, + mss::c_str(i_target) ); + + return set_field<fields::SERDES_FREQ>(i_target, io_data, l_setting); + +fapi_try_exit: + return fapi2::current_err; +} + +}// boot_cfg + }// i2c }// exp }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.H index 3098e9e28..a11f0a03d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_fields.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,9 +36,14 @@ #ifndef _MSS_EXP_I2C_FIELDS_H_ #define _MSS_EXP_I2C_FIELDS_H_ -#include <generic/memory/lib/utils/mss_field.H> -#include <lib/shared/exp_consts.H> #include <functional> +#ifdef __PPE__ + #include <mss_field.H> + #include <exp_consts.H> +#else + #include <generic/memory/lib/utils/mss_field.H> + #include <lib/shared/exp_consts.H> +#endif namespace mss { @@ -57,10 +62,11 @@ struct fields // First value is byte index, then buffer extract start bit, and extract data length // Part of EXP_FW_BOOT_CONFIG - static constexpr mss::field_t<mss::endian::BIG> BOOT_MODE{0, 0, 1}; + static constexpr mss::field_t<mss::endian::BIG> DFE_DISABLE{0, 0, 1}; static constexpr mss::field_t<mss::endian::BIG> LANE_MODE{0, 1, 3}; static constexpr mss::field_t<mss::endian::BIG> SERDES_FREQ{0, 4, 4}; - static constexpr mss::field_t<mss::endian::BIG> FW_MODE{1, 2, 1}; + static constexpr mss::field_t<mss::endian::BIG> ADAPTATION_MODE{1, 0, 1}; + static constexpr mss::field_t<mss::endian::BIG> FW_MODE{1, 1, 2}; static constexpr mss::field_t<mss::endian::BIG> LOOPBACK_TEST{1, 3, 1}; static constexpr mss::field_t<mss::endian::BIG> TRANSPORT_LAYER{1, 4, 2}; static constexpr mss::field_t<mss::endian::BIG> DL_LAYER_BOOT_MODE{1, 6, 2}; @@ -108,14 +114,14 @@ struct fieldTraits<fields::LANE_MODE> }; /// -/// @class fieldTraits - BOOT_MODE specialization +/// @class fieldTraits - DFE_DISABLE specialization /// @brief Traits assoiated with the Explorer I2C commands /// template <> -struct fieldTraits<fields::BOOT_MODE> +struct fieldTraits<fields::DFE_DISABLE> { static constexpr uint8_t COMPARISON_VAL = 0x01; - static constexpr const char* FIELD_STR = "Boot mode"; + static constexpr const char* FIELD_STR = "DFE Disable"; template <typename T> using COMPARISON_OP = std::less_equal<T>; @@ -170,7 +176,7 @@ struct fieldTraits<fields::LOOPBACK_TEST> template <> struct fieldTraits<fields::FW_MODE> { - static constexpr uint8_t COMPARISON_VAL = 0x01; + static constexpr uint8_t COMPARISON_VAL = 0x02; static constexpr const char* FIELD_STR = "FW Mode"; template <typename T> @@ -178,6 +184,20 @@ struct fieldTraits<fields::FW_MODE> }; /// +/// @class fieldTraits - ADAPTATION_MODE specialization +/// @brief Traits assoiated with the Explorer I2C commands +/// +template <> +struct fieldTraits<fields::ADAPTATION_MODE> +{ + static constexpr uint8_t COMPARISON_VAL = 0x01; + static constexpr const char* FIELD_STR = "Adaptation Mode"; + + template <typename T> + using COMPARISON_OP = std::less_equal<T>; +}; + +/// /// @class fieldTraits - CMD_ID specialization /// @brief Traits assoiated with the Explorer I2C commands /// @@ -241,6 +261,7 @@ inline fapi2::ReturnCode get_field(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_C return mss::get_field<endian::BIG, F, TT>(i_target, i_data, EXP_I2C_GET_FIELD, o_value); } +#ifndef __PPE__ /// /// @brief Explorer I2C field setter /// @tparam IT Input type @@ -284,15 +305,12 @@ inline fapi2::ReturnCode get_serdes_freq(const fapi2::Target<fapi2::TARGET_TYPE_ /// @brief SERDES_FREQ setter /// @param[in] i_target the OCMB target /// @param[in,out] io_data the buffer as a reference to a vector -/// @param[in] i_setting the value to set +/// @param[in] i_freq frequency to set /// @return FAPI2_RC_SUCCESS iff okay /// -inline fapi2::ReturnCode set_serdes_freq(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - std::vector<uint8_t>& io_data, - const uint8_t i_setting) -{ - return set_field<fields::SERDES_FREQ>(i_target, io_data, i_setting); -} +fapi2::ReturnCode set_serdes_freq(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + std::vector<uint8_t>& io_data, + const uint32_t i_freq); /// /// @brief LANE_MODE getter @@ -323,31 +341,31 @@ inline fapi2::ReturnCode set_lane_mode(const fapi2::Target<fapi2::TARGET_TYPE_OC } /// -/// @brief BOOT_MODE getter +/// @brief DFE_DISABLE getter /// @param[in] i_target the OCMB target /// @param[in] i_data the buffer as a reference to a vector /// @param[out] o_setting /// @return FAPI2_RC_SUCCESS iff okay /// -inline fapi2::ReturnCode get_boot_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - const std::vector<uint8_t>& i_data, - uint8_t& o_setting) +inline fapi2::ReturnCode get_dfe_disable(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + uint8_t& o_setting) { - return get_field<fields::BOOT_MODE>(i_target, i_data, o_setting); + return get_field<fields::DFE_DISABLE>(i_target, i_data, o_setting); } /// -/// @brief BOOT_MODE setter +/// @brief DFE_DISABLE setter /// @param[in] i_target the OCMB target /// @param[in,out] io_data the buffer as a reference to a vector /// @param[in] i_setting the value to set /// @return FAPI2_RC_SUCCESS iff okay /// -inline fapi2::ReturnCode set_boot_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - std::vector<uint8_t>& io_data, - const uint8_t i_setting) +inline fapi2::ReturnCode set_dfe_disable(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + std::vector<uint8_t>& io_data, + const uint8_t i_setting) { - return set_field<fields::BOOT_MODE>(i_target, io_data, i_setting); + return set_field<fields::DFE_DISABLE>(i_target, io_data, i_setting); } /// @brief DL_LAYER_BOOT_MODE getter @@ -377,6 +395,33 @@ inline fapi2::ReturnCode set_dl_layer_boot_mode(const fapi2::Target<fapi2::TARGE return set_field<fields::DL_LAYER_BOOT_MODE>(i_target, io_data, i_setting); } +/// @brief ADAPTATION_MODE getter +/// @param[in] i_target the OCMB target +/// @param[in] i_data the buffer as a reference to a vector +/// @param[out] o_setting +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode get_adaptation_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + uint8_t& o_setting) +{ + return get_field<fields::ADAPTATION_MODE>(i_target, i_data, o_setting); +} + +/// +/// @brief ADAPTATION_MODE setter +/// @param[in] i_target the OCMB target +/// @param[in,out] io_data the buffer as a reference to a vector +/// @param[in] i_setting the value to set +/// @return FAPI2_RC_SUCCESS iff okay +/// +inline fapi2::ReturnCode set_adaptation_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + std::vector<uint8_t>& io_data, + const uint8_t i_setting) +{ + return set_field<fields::ADAPTATION_MODE>(i_target, io_data, i_setting); +} + /// /// @brief DL_LAYER_BOOT_MODE getter /// @param[in] i_target the OCMB target @@ -464,6 +509,8 @@ inline fapi2::ReturnCode set_fw_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB }// boot_cfg +#endif + namespace status { @@ -481,6 +528,7 @@ inline fapi2::ReturnCode get_boot_stage(const fapi2::Target<fapi2::TARGET_TYPE_O return get_field<fields::BOOT_STAGE>(i_target, i_data, o_setting); } + /// /// @brief STATUS_CODE getter /// @param[in] i_target the OCMB target @@ -495,6 +543,7 @@ inline fapi2::ReturnCode get_status_code(const fapi2::Target<fapi2::TARGET_TYPE_ return get_field<fields::STATUS_CODE>(i_target, i_data, o_setting); } +#ifndef __PPE__ /// /// @brief CMD_ID getter /// @param[in] i_target the OCMB target @@ -508,6 +557,7 @@ inline fapi2::ReturnCode get_cmd_id(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_ { return get_field<fields::CMD_ID>(i_target, i_data, o_setting); } +#endif }// status }// i2c diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_pmic.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_pmic.H deleted file mode 100644 index e546dda93..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_pmic.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_pmic.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_scom.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_scom.H index f1d811245..b2813abec 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_scom.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/i2c/exp_i2c_scom.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,11 @@ #ifndef _MSS_EXP_I2C_SCOM_H_ #define _MSS_EXP_I2C_SCOM_H_ -#include <lib/i2c/exp_i2c.H> +#ifdef __PPE__ + #include <exp_i2c.H> +#else + #include <lib/i2c/exp_i2c.H> +#endif namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.C new file mode 100644 index 000000000..f9c17f564 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.C @@ -0,0 +1,139 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file exp_fw_log.C +/// +/// @brief Helpers to access explorer firmware logs + +// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP FW Owner: Matt Derksen <mderkse1@us.ibm.com> +// *HWP Team: +// *HWP Level: 2 +// *HWP Consumed by: HB + +#include <exp_fw_log.H> +#include <fapi2.H> +#include <exp_inband.H> +#include <lib/shared/exp_consts.H> +#include <exp_data_structs.H> +#include <generic/memory/lib/utils/c_str.H> + + +namespace mss +{ +namespace exp +{ +namespace ib +{ + +/// +/// @brief Response parameters of Explorer Log commands +/// This is found in the response_argument field +typedef struct +{ + uint8_t op; /**< Firmware error log sub-cmd operation */ + uint8_t status; /**< Operation status */ + uint32_t err_code; /**< Specific error code if operation failed */ + uint32_t num_bytes_returned; /**< Number of bytes returned */ +} exp_fw_log_rsp_parms_struct_t; + +/// +/// @brief Operation status values +/// +enum +{ + STATUS_OP_FAILED = 0x00, + STATUS_OP_SUCCESSFUL = 0x01, +}; + +/// See header +void build_log_cmd( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const exp_log_sub_cmd_op i_sub_op, + host_fw_command_struct& o_cmd ) +{ + // Issue EXP_FW_LOG cmd though EXP-FW REQ buffer + o_cmd.cmd_id = mss::exp::omi::EXP_FW_LOG; + o_cmd.cmd_flags = 0; + + // Host generated id number (returned in response packet) + // @todo RTC 210371 + //uint32_t l_counter = 0; + //FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OCMB_COUNTER, i_target, l_counter)); + o_cmd.request_identifier = 0xabcd; + + if (i_sub_op == SUB_CMD_READ_SAVED_LOG) + { + o_cmd.request_identifier = 0xabce; + } + + o_cmd.cmd_length = 0; + + o_cmd.cmd_crc = 0xffffffff; + o_cmd.host_work_area = 0; + o_cmd.cmd_work_area = 0; + memset(o_cmd.padding, 0, sizeof(o_cmd.padding)); + + // Set the sub-command ID in the command argument field + o_cmd.command_argument[0] = i_sub_op; +} + +/// See header +fapi2::ReturnCode check_log_cmd_response( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp ) +{ + std::vector<uint8_t> resp_arg; + uint32_t index = 0; + exp_fw_log_rsp_parms_struct_t l_rsp_args; + + //copy response_argument field into a vector that can be + //used by readCrctEndian() + resp_arg.assign(i_rsp.response_argument, + i_rsp.response_argument + ARGUMENT_SIZE); + + //convert fields to native endianness + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, l_rsp_args.op)); + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, l_rsp_args.status)); + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, l_rsp_args.err_code)); + FAPI_TRY(mss::exp::ib::readCrctEndian(resp_arg, index, l_rsp_args.num_bytes_returned)); + + // check if command was successful + FAPI_ASSERT(l_rsp_args.status == STATUS_OP_SUCCESSFUL, + fapi2::MSS_EXP_RSP_ARG_FAILED(). + set_TARGET(i_target). + set_RSP_ID(i_rsp.response_id). + set_ERROR_CODE(l_rsp_args.err_code), + "EXP_FW_LOG command 0x%02X failed for %s. " + "Status: 0x%02X, err_code 0x%04X, num_bytes_returned 0x%04X", + l_rsp_args.op, mss::c_str(i_target), l_rsp_args.status, + l_rsp_args.err_code, l_rsp_args.num_bytes_returned); + +fapi_try_exit: + return fapi2::current_err; +} + +}//ib namespace +}//exp namespace +}//mss namespace diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.H new file mode 100644 index 000000000..3817640be --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.H @@ -0,0 +1,104 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_fw_log.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file exp_fw_log.H +/// @brief Helpers to access explorer firmware logs +/// The Explorer firmware modules log pertinent data regarding +/// operations and errors, and the Host manages and accesses this +/// information by using the EXP_FW_LOG API command. The firmware +/// maintains the log in a circular buffer in RAM and in the event +/// of a processor exception, firmware assert, or other critical +/// condition the firmware saves the data in RAM to SPI flash. +/// Having the log stored in non-volatile memory allows post-analysis +/// of the log even if it requires a power-cycle to recover the system. +/// +// *HWP HWP Owner: Matt Derksen <mderkse1@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_EXP_FW_LOG__ +#define __MSS_EXP_FW_LOG__ + +#include <fapi2.H> +#include <vector> +#include <exp_data_structs.H> + +namespace mss +{ +namespace exp +{ +namespace ib +{ +/// +/// @brief Defines the sub-commands available for the +/// EXP_FW_LOG command +/// +enum exp_log_sub_cmd_op +{ + // This is used to read log entries from the active + // firmware logfile stored in Explorer RAM + SUB_CMD_READ_ACTIVE_LOG = 0x01, + + // This is used to read log entries from the saved + // firmware logfile stored in Explorer SPI flash + SUB_CMD_READ_SAVED_LOG = 0x02, + + // This is used to clear the active logfile in Explorer RAM + SUB_CMD_CLEAR_ACTIVE_LOG = 0x03, + + // This is used to erase the saved logfile in Explorer SPI flash + SUB_CMD_ERASE_SAVED_LOG = 0x04, +}; + +/// +/// @brief Sets the command_argument fields for EXP_FW_LOG command +/// +/// @param[in] i_target - OCMB target +/// @param[in] i_sub_op - what sub-command of EXP_FW_LOG to use +/// @param[out] o_cmd - command packet to update +/// +void build_log_cmd(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const exp_log_sub_cmd_op i_sub_op, + host_fw_command_struct& o_cmd ); + + +/// +/// @brief Checks the response of the EXP_FW_LOG command +/// +/// @param[in] i_target - OCMB target +/// @param[in] i_rsp - response portion of EXP_FW_ERROR_LOG (from getRsp()) +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode check_log_cmd_response( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const host_fw_response_struct& i_rsp ); + +}//exp +}//mss +}//ib + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.C index ff24bc76c..b871c9682 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.C $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,7 @@ // *HWP Level: 2 // *HWP Consumed by: HB -#include <exp_inband.H> +#include <lib/inband/exp_inband.H> #include <lib/omi/crc32.H> #include <lib/shared/exp_consts.H> @@ -63,7 +63,7 @@ namespace ib fapi2::ReturnCode putMMIO64( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - const fapi2::buffer<uint64_t>& i_data ) + const fapi2::buffer<uint64_t>& i_data) { uint64_t l_v = static_cast<uint64_t>(i_data); std::vector<uint8_t> l_wd; @@ -71,9 +71,6 @@ fapi2::ReturnCode putMMIO64( return fapi2::putMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 8, l_wd); } - - - /// @brief Writes 32 bits of data to MMIO space to the selected Explorer /// /// @param[in] i_target The Explorer chip to write @@ -84,7 +81,7 @@ fapi2::ReturnCode putMMIO64( fapi2::ReturnCode putMMIO32( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - const fapi2::buffer<uint32_t>& i_data ) + const fapi2::buffer<uint32_t>& i_data) { uint32_t l_v = static_cast<uint32_t>(i_data); std::vector<uint8_t> l_wd; @@ -92,9 +89,6 @@ fapi2::ReturnCode putMMIO32( return fapi2::putMMIO(i_target, EXPLR_IB_MMIO_OFFSET | i_addr, 4, l_wd); } - - - /// @brief Writes 64 bits of data to SCOM MMIO space /// /// @param[in] i_target The Explorer chip to write @@ -112,9 +106,6 @@ fapi2::ReturnCode putScom( return putMMIO64(i_target, l_scomAddr, i_data); } - - - /// @brief Writes 32 bits of data to OpenCAPI config space /// /// @param[in] i_target The Explorer chip to write @@ -127,18 +118,35 @@ fapi2::ReturnCode putOCCfg( const uint64_t i_cfgAddr, const fapi2::buffer<uint32_t>& i_data) { + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; uint32_t l_v = static_cast<uint32_t>(i_data); std::vector<uint8_t> l_wd; - forceLE(l_v, l_wd); - return fapi2::putMMIO(i_target, i_cfgAddr, 4, l_wd); -} + fapi2::ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL_Type l_endian; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL, + FAPI_SYSTEM, l_endian)); + if (l_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL_LITTLE_ENDIAN) + { + forceLE(l_v, l_wd); + } + else + { + forceBE(l_v, l_wd); + } + + FAPI_TRY(fapi2::putMMIO(i_target, i_cfgAddr, 4, l_wd)); +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); + return fapi2::current_err; +} fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_input, std::vector<uint8_t>& o_data, uint32_t& o_crc) { + o_data.clear(); + FAPI_TRY(forceCrctEndian(i_input.version_number, o_data)); FAPI_TRY(forceCrctEndian(i_input.DimmType, o_data)); FAPI_TRY(forceCrctEndian(i_input.CsPresent, o_data)); FAPI_TRY(forceCrctEndian(i_input.DramDataWidth, o_data)); @@ -151,9 +159,11 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu FAPI_TRY(forceCrctEndian(i_input.SpdCLSupported, o_data)); FAPI_TRY(forceCrctEndian(i_input.SpdtAAmin, o_data)); FAPI_TRY(forceCrctEndian(i_input.Rank4Mode, o_data)); + FAPI_TRY(forceCrctEndian(i_input.EncodedQuadCs, o_data)); FAPI_TRY(forceCrctEndian(i_input.DDPCompatible, o_data)); FAPI_TRY(forceCrctEndian(i_input.TSV8HSupport, o_data)); FAPI_TRY(forceCrctEndian(i_input.MRAMSupport, o_data)); + FAPI_TRY(forceCrctEndian(i_input.MDSSupport, o_data)); FAPI_TRY(forceCrctEndian(i_input.NumPStates, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.Frequency, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.PhyOdtImpedance, MSDG_MAX_PSTATE, o_data)); @@ -180,7 +190,7 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu FAPI_TRY(forceCrctEndianArray(i_input.DramDic, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.DramWritePreamble, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.DramReadPreamble, MSDG_MAX_PSTATE, o_data)); - FAPI_TRY(forceCrctEndian(i_input.PhyEqualization, o_data)); + FAPI_TRY(forceCrctEndianArray(i_input.PhyEqualization, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.InitVrefDQ, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.InitPhyVref, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.OdtWrMapCs, MSDG_MAX_PSTATE, o_data)); @@ -191,17 +201,29 @@ fapi2::ReturnCode user_input_msdg_to_little_endian(const user_input_msdg& i_inpu FAPI_TRY(forceCrctEndianArray(i_input.BistCAParityLatency, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.RcdDic, MSDG_MAX_PSTATE, o_data)); FAPI_TRY(forceCrctEndianArray(i_input.RcdVoltageCtrl, MSDG_MAX_PSTATE, o_data)); - FAPI_TRY(forceCrctEndian(i_input.RcdIBTCtrl, o_data)); - FAPI_TRY(forceCrctEndian(i_input.RcdDBDic, o_data)); - FAPI_TRY(forceCrctEndian(i_input.RcdSlewRate, o_data)); - FAPI_TRY(forceCrctEndian(i_input.EmulationSupport, o_data)); + FAPI_TRY(forceCrctEndianArray(i_input.RcdIBTCtrl, MSDG_MAX_PSTATE, o_data)); + FAPI_TRY(forceCrctEndianArray(i_input.RcdDBDic, MSDG_MAX_PSTATE, o_data)); + FAPI_TRY(forceCrctEndianArray(i_input.RcdSlewRate, MSDG_MAX_PSTATE, o_data)); + FAPI_TRY(forceCrctEndian(i_input.DFIMRL_DDRCLK, o_data)); + + for (uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate) + { + FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_A[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data)); + } + + for (uint8_t l_pstate = 0; l_pstate < MSDG_MAX_PSTATE; ++l_pstate) + { + FAPI_TRY(forceCrctEndianArray(i_input.ATxDly_B[l_pstate], DRAMINIT_NUM_ADDR_DELAYS, o_data)); + } o_crc = crc32_gen(o_data); + padCommData(o_data); FAPI_TRY(correctMMIOEndianForStruct(o_data)); + FAPI_TRY(correctMMIOword_order(o_data)); fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } @@ -224,12 +246,10 @@ fapi2::ReturnCode putUserInputMsdg( FAPI_TRY(fapi2::putMMIO(i_target, EXPLR_IB_DATA_ADDR, BUFFER_TRANSACTION_SIZE, l_data)); fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - fapi2::ReturnCode host_fw_command_struct_to_little_endian(const host_fw_command_struct& i_input, std::vector<uint8_t>& o_data) { @@ -248,10 +268,12 @@ fapi2::ReturnCode host_fw_command_struct_to_little_endian(const host_fw_command_ l_cmd_header_crc = crc32_gen(o_data); FAPI_DBG("Command header crc: %xl", l_cmd_header_crc); FAPI_TRY(forceCrctEndian(l_cmd_header_crc, o_data)); + padCommData(o_data); FAPI_TRY(correctMMIOEndianForStruct(o_data)); + FAPI_TRY(correctMMIOword_order(o_data)); fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } @@ -272,23 +294,28 @@ fapi2::ReturnCode putCMD( // Clear the doorbell l_scom.setBit<EXPLR_MMIO_MDBELLC_MDBELL_MDBELL>(); - FAPI_TRY(mss::exp::ib::putScom(i_target, EXPLR_MMIO_MDBELLC, l_scom)); + FAPI_DBG("Clearing the inbound doorbell..."); + FAPI_TRY(fapi2::putScom(i_target, EXPLR_MMIO_MDBELLC, l_scom), "Failed to clear inbound doorbell register"); + + // Clear the response doorbell, just in case the last response didn't get cleared + FAPI_TRY(clear_outbound_doorbell(i_target)); // Set the command - FAPI_TRY(fapi2::putMMIO(i_target, EXPLR_IB_CMD_ADDR, BUFFER_TRANSACTION_SIZE, l_data)) + FAPI_DBG("Writing the command..."); + FAPI_TRY(fapi2::putMMIO(i_target, EXPLR_IB_CMD_ADDR, BUFFER_TRANSACTION_SIZE, l_data), + "Failed to write to the command buffer"); // Ring the doorbell - aka the bit that interrupts the microchip FW and tells it to do the thing l_scom.flush<0>(); l_scom.setBit<EXPLR_MMIO_MDBELL_MDBELL>(); - FAPI_TRY(mss::exp::ib::putScom(i_target, EXPLR_MMIO_MDBELL, l_scom)); + FAPI_DBG("Setting the inbound doorbell..."); + FAPI_TRY(fapi2::putScom(i_target, EXPLR_MMIO_MDBELL, l_scom), "Failed to set inbound doorbell bit"); fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - //-------------------------------------------------------------------------------- // Read operations //-------------------------------------------------------------------------------- @@ -312,13 +339,10 @@ fapi2::ReturnCode getMMIO64( readLE(l_data, l_idx, l_rd); o_data = l_rd; fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - - /// @brief Reads 32 bits of data from MMIO space on the selected Explorer /// /// @param[in] i_target The Explorer chip to read data from @@ -338,13 +362,10 @@ fapi2::ReturnCode getMMIO32( readLE(l_data, l_idx, l_rd); o_data = l_rd; fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - - /// @brief Reads 64 bits of data from SCOM MMIO space on the selected Explorer /// /// @param[in] i_target The Explorer chip to read data from @@ -362,9 +383,6 @@ fapi2::ReturnCode getScom( return getMMIO64(i_target, l_scomAddr, o_data); } - - - /// @brief Reads 32 bits of data from OpenCAPI config space on the selected Explorer /// /// @param[in] i_target The Explorer chip to read data from @@ -377,18 +395,32 @@ fapi2::ReturnCode getOCCfg( const uint64_t i_cfgAddr, fapi2::buffer<uint32_t>& o_data) { + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; uint32_t l_rd = 0; std::vector<uint8_t> l_data(4); uint32_t l_idx = 0; + fapi2::ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL_Type l_endian; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL, + FAPI_SYSTEM, l_endian)); + FAPI_TRY(fapi2::getMMIO(i_target, i_cfgAddr, 4, l_data)); - readLE(l_data, l_idx, l_rd); + + if (l_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL_LITTLE_ENDIAN) + { + readLE(l_data, l_idx, l_rd); + } + else + { + readBE(l_data, l_idx, l_rd); + } + o_data = l_rd; fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - /// /// @brief Converts a little endian data array to a host_fw_response_struct /// @param[in] i_data little endian data to process @@ -401,19 +433,37 @@ fapi2::ReturnCode host_fw_response_struct_from_little_endian(std::vector<uint8_t host_fw_response_struct& o_response) { uint32_t l_idx = 0; + + uint8_t l_response_id = 0; + uint8_t l_response_flags = 0; + uint16_t l_request_identifier = 0; + uint32_t l_response_length = 0; + uint32_t l_response_crc = 0; + uint32_t l_host_work_area = 0; + uint32_t l_response_header_crc = 0; + FAPI_TRY(correctMMIOEndianForStruct(i_data)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_id)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_flags)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.request_identifier)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_length)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_crc)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.host_work_area)); + FAPI_TRY(correctMMIOword_order(i_data)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_id)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_flags)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_request_identifier)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_length)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_crc)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_host_work_area)); FAPI_TRY(readCrctEndianArray(i_data, RSP_PADDING_SIZE, l_idx, o_response.padding)); FAPI_TRY(readCrctEndianArray(i_data, ARGUMENT_SIZE, l_idx, o_response.response_argument)); + o_response.response_id = l_response_id; + o_response.response_flags = l_response_flags; + o_response.request_identifier = l_request_identifier; + o_response.response_length = l_response_length; + o_response.response_crc = l_response_crc; + o_response.host_work_area = l_host_work_area; + o_crc = crc32_gen(i_data, l_idx); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_response.response_header_crc)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_response_header_crc)); + o_response.response_header_crc = l_response_header_crc; fapi_try_exit: return fapi2::current_err; @@ -434,15 +484,17 @@ fapi2::ReturnCode host_fw_response_struct_from_little_endian(const fapi2::Target { uint32_t l_crc = 0; fapi2::current_err = host_fw_response_struct_from_little_endian(i_data, l_crc, o_response); - FAPI_ASSERT( fapi2::current_err == fapi2::FAPI2_RC_SUCCESS, - fapi2::EXP_INBAND_LE_DATA_RANGE() - .set_TARGET(i_target) - .set_FUNCTION(mss::exp::READ_HOST_FW_RESPONSE_STRUCT) - .set_DATA_SIZE(i_data.size()) - .set_MAX_INDEX(sizeof(host_fw_response_struct)), - "%s Failed to convert from data to host_fw_response_struct data size %u expected size %u", - mss::c_str(i_target), i_data.size(), sizeof(host_fw_response_struct)); - + FAPI_ASSERT(fapi2::current_err == fapi2::FAPI2_RC_SUCCESS, + fapi2::EXP_INBAND_LE_DATA_RANGE() + .set_TARGET(i_target) + .set_FUNCTION(mss::exp::READ_HOST_FW_RESPONSE_STRUCT) + .set_DATA_SIZE(i_data.size()) + .set_MAX_INDEX(sizeof(host_fw_response_struct)), + "%s Failed to convert from data to host_fw_response_struct data size %u expected size %u", + mss::c_str(i_target), i_data.size(), sizeof(host_fw_response_struct)); + +//TODO CQ: SW461052 Correct MMIO CRC responses +#ifndef CONFIG_AXONE_BRING_UP FAPI_ASSERT(l_crc == o_response.response_header_crc, fapi2::EXP_INBAND_RSP_CRC_ERR() .set_COMPUTED(l_crc) @@ -450,6 +502,73 @@ fapi2::ReturnCode host_fw_response_struct_from_little_endian(const fapi2::Target .set_OCMB_TARGET(i_target), "%s Response CRC failed to validate computed: 0x%08x got: 0x%08x", mss::c_str(i_target), l_crc, o_response.response_header_crc); +#endif + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Polls for response ready door bell bit +/// @param[in] i_target the OCMB target on which to operate +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode poll_for_response_ready(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + // NUM_LOOPS is based on EXP_FW_DDR_PHY_INIT command, which completes in ~370ms in HW. + // We initially delay 8ms, so we should only need to poll for ~360ms here. + // We're waiting 20ms between polls, so we should only need about 18 loops here, + // but we make it 200 to be safe. Max timeout is (200 x 20ms) = 4 seconds + constexpr uint64_t NUM_LOOPS = 200; + + // So, why aren't we using the memory team's polling API? + // This is a base function that will be utilized by the platform code + // As such, we don't want to pull in more libraries than we need to: it would cause extra dependencies + // So, we're decomposing the polling library below + bool l_doorbell_response = false; + uint64_t l_loop = 0; + fapi2::buffer<uint64_t> l_data; + + // Loop until we max our our loop count or get a doorbell response + for (; l_loop < NUM_LOOPS && !l_doorbell_response; ++l_loop) + { + FAPI_TRY(fapi2::getScom(i_target, EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1, l_data)); + l_doorbell_response = l_data.getBit<EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1_DOORBELL>(); + FAPI_TRY(fapi2::delay(20 * DELAY_1MS, 200)); + } + + FAPI_DBG("%s stopped on loop%u/%u data:0x%016lx %u", + mss::c_str(i_target), l_loop, NUM_LOOPS, l_data, l_doorbell_response); + + // Error check - doorbell response should be true + FAPI_ASSERT(l_doorbell_response, + fapi2::EXP_INBAND_RSP_NO_DOORBELL() + .set_OCMB_TARGET(i_target) + .set_DATA(l_data) + .set_NUM_LOOPS(l_loop), + "%s doorbell timed out after %u loops: data 0x%016lx", + mss::c_str(i_target), l_loop, l_data); + + // Ding-dong! the doorbell is rung and the response is ready + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Clears outbound (response ready) door bell bit +/// @param[in] i_target the OCMB target on which to operate +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode clear_outbound_doorbell(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + fapi2::buffer<uint64_t> l_data; + + // Doorbell is cleared by writing a '1' to the doorbell bit + l_data.setBit<EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1_DOORBELL>(); + + FAPI_DBG("%s Clearing outbound doorbell...", mss::c_str(i_target)); + FAPI_TRY(fapi2::putScom(i_target, EXPLR_MIPS_TO_OCMB_INTERRUPT_REGISTER1, l_data)); fapi_try_exit: return fapi2::current_err; @@ -464,36 +583,46 @@ fapi_try_exit: /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode getRSP( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - host_fw_response_struct& o_rsp, std::vector<uint8_t>& o_data) + host_fw_response_struct& o_rsp, + std::vector<uint8_t>& o_data) { std::vector<uint8_t> l_data(static_cast<int>(sizeof(o_rsp))); - FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_RSP_ADDR, BUFFER_TRANSACTION_SIZE, l_data)); + // Polls for the response to be ready first + FAPI_TRY(poll_for_response_ready(i_target)); + + FAPI_DBG("Reading the response buffer..."); + FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_RSP_ADDR, BUFFER_TRANSACTION_SIZE, l_data)); FAPI_TRY(host_fw_response_struct_from_little_endian(i_target, l_data, o_rsp)); + FAPI_DBG("Checking if we have response data..."); + // If response data in buffer portion, return that too if (o_rsp.response_length > 0) { // make sure expected size is a multiple of 8 - o_data.resize( o_rsp.response_length + - (8 - (o_rsp.response_length % 8)) ); + const uint32_t l_padding = ((o_rsp.response_length % 8) > 0) ? (8 - (o_rsp.response_length % 8)) : 0; + o_data.resize(o_rsp.response_length + l_padding); + FAPI_DBG("Reading response data..."); - FAPI_TRY( fapi2::getMMIO(i_target, EXPLR_IB_DATA_ADDR, BUFFER_TRANSACTION_SIZE, o_data) ); + FAPI_TRY(fapi2::getMMIO(i_target, EXPLR_IB_DATA_ADDR, BUFFER_TRANSACTION_SIZE, o_data)); + FAPI_TRY(correctMMIOEndianForStruct(o_data)); + FAPI_TRY(correctMMIOword_order(o_data)); } else { + FAPI_DBG("No response data returned..."); // make sure no buffer data is returned o_data.clear(); } + FAPI_TRY(clear_outbound_doorbell(i_target)); + fapi_try_exit: - FAPI_DBG("%s Exiting with return code : 0x%08X...", mss::c_str(i_target), (uint64_t) fapi2::current_err); + FAPI_DBG("%s Exiting with return code : 0x%08X...", mss::c_str(i_target), (uint64_t)fapi2::current_err); return fapi2::current_err; } - - - /// /// @brief Converts a little endian data array to a sensor_cache_struct /// @param[in] i_data little endian data to process @@ -504,25 +633,59 @@ fapi_try_exit: fapi2::ReturnCode sensor_cache_struct_from_little_endian(std::vector<uint8_t>& i_data, sensor_cache_struct& o_data) { + // Local variables to avoid error in passing packed struct fields by reference uint32_t l_idx = 0; + uint16_t l_status = 0; + uint16_t l_ocmb_dts = 0; + uint16_t l_mem_dts0 = 0; + uint16_t l_mem_dts1 = 0; + uint32_t l_mba_reads = 0; + uint32_t l_mba_writes = 0; + uint32_t l_mba_activations = 0; + uint32_t l_mba_powerups = 0; + uint8_t l_self_timed_refresh = 0; + uint32_t l_frame_count = 0; + uint32_t l_mba_arrival_histo_base = 0; + uint32_t l_mba_arrival_histo_low = 0; + uint32_t l_mba_arrival_histo_med = 0; + uint32_t l_mba_arrival_histo_high = 0; + uint8_t l_initial_packet1 = 0; FAPI_TRY(correctMMIOEndianForStruct(i_data)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.status)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.ocmb_dts)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mem_dts0)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mem_dts1)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_reads)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_writes)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_activations)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_powerups)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.self_timed_refresh)); + FAPI_TRY(correctMMIOword_order(i_data)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_status)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_ocmb_dts)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mem_dts0)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mem_dts1)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_reads)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_writes)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_activations)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_powerups)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_self_timed_refresh)); FAPI_TRY(readCrctEndianArray(i_data, SENSOR_CACHE_PADDING_SIZE_0, l_idx, o_data.reserved0)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.frame_count)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_base)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_low)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_med)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.mba_arrival_histo_high)); - FAPI_TRY(readCrctEndian(i_data, l_idx, o_data.initial_packet1)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_frame_count)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_base)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_low)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_med)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_mba_arrival_histo_high)); + FAPI_TRY(readCrctEndian(i_data, l_idx, l_initial_packet1)); + + o_data.frame_count = l_frame_count; + o_data.mba_arrival_histo_base = l_mba_arrival_histo_base; + o_data.mba_arrival_histo_low = l_mba_arrival_histo_low; + o_data.mba_arrival_histo_med = l_mba_arrival_histo_med; + o_data.mba_arrival_histo_high = l_mba_arrival_histo_high; + o_data.initial_packet1 = l_initial_packet1; + o_data.status = l_status; + o_data.ocmb_dts = l_ocmb_dts; + o_data.mem_dts0 = l_mem_dts0; + o_data.mem_dts1 = l_mem_dts1; + o_data.mba_reads = l_mba_reads; + o_data.mba_writes = l_mba_writes; + o_data.mba_activations = l_mba_activations; + o_data.mba_powerups = l_mba_powerups; + o_data.self_timed_refresh = l_self_timed_refresh; + FAPI_TRY(readCrctEndianArray(i_data, SENSOR_CACHE_PADDING_SIZE_1, l_idx, o_data.reserved1)); fapi_try_exit: @@ -569,62 +732,106 @@ fapi2::ReturnCode getSensorCache( FAPI_TRY(sensor_cache_struct_from_little_endian(i_target, l_data, o_data)); fapi_try_exit: - FAPI_DBG("%s Exiting with return code : 0x%08X...", mss::c_str(i_target), (uint64_t) fapi2::current_err); + FAPI_DBG("%s Exiting with return code : 0x%08X...", mss::c_str(i_target), (uint64_t)fapi2::current_err); return fapi2::current_err; } +/// +/// @brief UT helper for correctMMIOEndianForStruct +/// +/// @param[in] i_endian_ctrl value of ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL +/// @param[in,out] io_data value to swizzle +/// +void correctMMIOEndianForStruct_helper(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL_Type i_endian_ctrl, + std::vector<uint8_t>& io_data) +{ + size_t l_loops = 0; + if (i_endian_ctrl == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL_SWAP) + { + l_loops = io_data.size() / BUFFER_TRANSACTION_SIZE; + for (size_t l_idx = 0; l_idx < l_loops; l_idx++) + { + for (int l_bidx = BUFFER_TRANSACTION_SIZE - 1; l_bidx >= 0; l_bidx--) + { + io_data.push_back(io_data.at(l_bidx)); + } + io_data.erase(io_data.begin(), io_data.begin() + BUFFER_TRANSACTION_SIZE); + } + } +} +/// /// @brief We will use 4 or 8 byte reads via fapi2::put/getMMIO for buffer /// data structures. The byte order of the 4 or 8 byte reads should be little /// endian. In order to represent the data structure in its proper layout /// the endianness of each 4 or 8 byte read must be corrected. -/// /// @param[in,out] io_data Either data structure in proper byte order that we /// want to swizzle prior to writing to the buffer, or the data returned /// from reading the buffer that we want to unsizzle. -/// /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// fapi2::ReturnCode correctMMIOEndianForStruct(std::vector<uint8_t>& io_data) { fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL_Type l_endian_ctrl; - size_t l_loops = 0; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL, - FAPI_SYSTEM, l_endian_ctrl)); - if (l_endian_ctrl == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL_NO_SWAP) - { - goto fapi_try_exit; - } + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL, + FAPI_SYSTEM, l_endian_ctrl)); + correctMMIOEndianForStruct_helper(l_endian_ctrl, io_data); - while ((io_data.size() % BUFFER_TRANSACTION_SIZE) != 0) - { - io_data.push_back(0); - } - - l_loops = io_data.size() / BUFFER_TRANSACTION_SIZE; +fapi_try_exit: + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); + return fapi2::current_err; +} - for (size_t l_idx = 0; l_idx < l_loops; l_idx++) +/// +/// @brief UT helper for correctMMIOword_order +/// @param[in] i_word_swap value of ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP +/// @param[in,out] io_data value to swizzle +/// +void correctMMIOword_order_helper(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP_Type i_word_swap, + std::vector<uint8_t>& io_data) +{ + if (i_word_swap == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP_SWAP) { - for (int l_bidx = BUFFER_TRANSACTION_SIZE - 1; l_bidx >= 0; l_bidx--) + for (size_t l_idx = 0; l_idx < io_data.size(); l_idx += BUFFER_TRANSACTION_SIZE) { - io_data.push_back(io_data.at(l_bidx)); + for (size_t l_bidx = l_idx; l_bidx < l_idx + BUFFER_TRANSACTION_SIZE / 2; l_bidx++) + { + uint8_t l_temp_first_word = io_data.at(l_bidx); + uint8_t l_temp_second_word = io_data.at(l_bidx + BUFFER_TRANSACTION_SIZE / 2); + io_data[l_bidx] = l_temp_second_word; + io_data[l_bidx + BUFFER_TRANSACTION_SIZE / 2] = l_temp_first_word; + } } - - io_data.erase(io_data.begin(), io_data.begin() + BUFFER_TRANSACTION_SIZE); } +} + +/// +/// @brief Because of how the AXI bridge in Explorer breaks up the transaction, +/// we might need to swap 32-bit word order +/// @param[in,out] io_data Either data structure in proper byte order that we +/// want to swizzle prior to writing to the buffer, or the data returned +/// from reading the buffer that we want to unsizzle. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode correctMMIOword_order(std::vector<uint8_t>& io_data) +{ + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP_Type l_word_swap; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP, + FAPI_SYSTEM, l_word_swap)); + correctMMIOword_order_helper(l_word_swap, io_data); fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - /// /// @brief Forces native data into the correct endianness necessary for Explorer /// buffer data structures. @@ -632,14 +839,14 @@ fapi_try_exit: /// @param[in] i_input inputted data to process /// @param[in,out] io_data vector to append data to /// -template < typename T > +template <typename T> fapi2::ReturnCode forceCrctEndian(const T& i_input, std::vector<uint8_t>& io_data) { fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_Type l_struct_endian; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, - FAPI_SYSTEM, l_struct_endian)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, + FAPI_SYSTEM, l_struct_endian)); if (l_struct_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_LITTLE_ENDIAN) { @@ -651,12 +858,10 @@ fapi2::ReturnCode forceCrctEndian(const T& i_input, std::vector<uint8_t>& io_dat } fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - /// /// @brief Forces native data into the correct endianness for an array buffer /// data structures. @@ -665,14 +870,14 @@ fapi_try_exit: /// @param[in] i_size size of the array /// @param[in,out] io_data vector to append data to /// -template < typename T > +template <typename T> fapi2::ReturnCode forceCrctEndianArray(const T* i_input, const uint64_t i_size, std::vector<uint8_t>& io_data) { fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_Type l_struct_endian; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, - FAPI_SYSTEM, l_struct_endian)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, + FAPI_SYSTEM, l_struct_endian)); if (l_struct_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_LITTLE_ENDIAN) { @@ -684,12 +889,10 @@ fapi2::ReturnCode forceCrctEndianArray(const T* i_input, const uint64_t i_size, } fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - /// /// @brief Converts endianness of data read from Explorer buffer data structures // into native order. @@ -699,14 +902,14 @@ fapi_try_exit: /// @param[out] o_data data that has been converted into native endianness /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// -template < typename T > +template <typename T> fapi2::ReturnCode readCrctEndian(const std::vector<uint8_t>& i_input, uint32_t& io_idx, T& o_data) { fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_Type l_struct_endian; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, - FAPI_SYSTEM, l_struct_endian)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, + FAPI_SYSTEM, l_struct_endian)); if (l_struct_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_LITTLE_ENDIAN) { @@ -732,21 +935,19 @@ fapi2::ReturnCode readCrctEndian(const std::vector<uint8_t>& i_input, uint32_t& } fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } - - -template < typename T > +template <typename T> fapi2::ReturnCode readCrctEndianArray(const std::vector<uint8_t>& i_input, const uint32_t i_size, uint32_t& io_idx, T* o_data) { fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_Type l_struct_endian; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, - FAPI_SYSTEM, l_struct_endian)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN, + FAPI_SYSTEM, l_struct_endian)); if (l_struct_endian == fapi2::ENUM_ATTR_MSS_OCMB_EXP_STRUCT_ENDIAN_LITTLE_ENDIAN) { @@ -772,13 +973,12 @@ fapi2::ReturnCode readCrctEndianArray(const std::vector<uint8_t>& i_input, const } fapi_try_exit: - FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t) fapi2::current_err); + FAPI_DBG("Exiting with return code : 0x%08X...", (uint64_t)fapi2::current_err); return fapi2::current_err; } +} // namespace ib -} // ns ib - -} // ns exp +} // namespace exp -} // ns mss +} // namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.H index 7c88ff45b..9b562ed0b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/inband/exp_inband.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -87,6 +87,8 @@ #include <exp_data_structs.H> #include <explorer_scom_addresses.H> #include <explorer_scom_addresses_fld.H> +#include <explorer_scom_addresses_fixes.H> +#include <explorer_scom_addresses_fld_fixes.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> namespace mss @@ -101,9 +103,9 @@ namespace ib static const size_t BUFFER_TRANSACTION_SIZE = 8; static const uint64_t EXPLR_IB_CONFIG_OFFSET = 0x0000000000000000ull; -static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; // 4GB -static const uint64_t EXPLR_IB_BAR_SIZE = 0b01111111; // 4GB Depends on EXPLR_IB_MMIO_OFFSET -static const uint64_t EXPLR_IB_BAR_B_BIT = EXPLR_IB_MMIO_OFFSET >> 1; // 2GB AND with A == 0, AND with B != 0 +static const uint64_t EXPLR_IB_MMIO_OFFSET = 0x0000000100000000ull; // 4GB +static const uint64_t EXPLR_IB_BAR_SIZE = 0b01111111; // 4GB Depends on EXPLR_IB_MMIO_OFFSET +static const uint64_t EXPLR_IB_BAR_B_BIT = EXPLR_IB_MMIO_OFFSET >> 1; // 2GB AND with A == 0, AND with B != 0 static const uint64_t EXPLR_IB_BAR_MASK_ZERO = (EXPLR_IB_BAR_B_BIT - 1); // AND with BAR must == 0 //-------------------------------------------------------------------------------- @@ -117,13 +119,13 @@ static const uint64_t EXPLR_IB_BAR_MASK_ZERO = (EXPLR_IB_BAR_B_BIT - 1); // AND /// Response Buffer 0xA103 FF00 BAR + 0x0103 FF00 0xA103 FF00 /// Data Buffer 0xA102 FF00 BAR + 0x0102 FF00 0xA102 FF00 /// -static const uint64_t EXPLR_IB_SRAM_BASE = 0x01000000; // MSCCRNGE 01000000 020FFFFF -static const uint64_t EXPLR_IB_CMD_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF40; -static const uint64_t EXPLR_IB_RSP_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF00; +static const uint64_t EXPLR_IB_SRAM_BASE = 0x01000000; // MSCCRNGE 01000000 020FFFFF +static const uint64_t EXPLR_IB_CMD_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF40; +static const uint64_t EXPLR_IB_RSP_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x03FF00; static const uint64_t EXPLR_IB_DATA_SRAM_ADDR = EXPLR_IB_SRAM_BASE | 0x02FF00; -static const uint64_t EXPLR_IB_CMD_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_CMD_SRAM_ADDR; -static const uint64_t EXPLR_IB_RSP_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_RSP_SRAM_ADDR; +static const uint64_t EXPLR_IB_CMD_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_CMD_SRAM_ADDR; +static const uint64_t EXPLR_IB_RSP_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_RSP_SRAM_ADDR; static const uint64_t EXPLR_IB_DATA_ADDR = EXPLR_IB_MMIO_OFFSET | EXPLR_IB_DATA_SRAM_ADDR; static const uint64_t EXPLR_IB_SENSOR_CACHE_ADDR = EXPLR_IB_MMIO_OFFSET | 0x40084200; @@ -212,10 +214,7 @@ fapi2::ReturnCode sensor_cache_struct_from_little_endian(const fapi2::Target<fap fapi2::ReturnCode putMMIO64( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - const fapi2::buffer<uint64_t>& i_data ) ; - - - + const fapi2::buffer<uint64_t>& i_data); /// @brief Writes 32 bits of data to MMIO space to the selected Explorer /// @@ -227,10 +226,7 @@ fapi2::ReturnCode putMMIO64( fapi2::ReturnCode putMMIO32( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - const fapi2::buffer<uint32_t>& i_data ) ; - - - + const fapi2::buffer<uint32_t>& i_data); /// @brief Writes 64 bits of data to SCOM MMIO space /// @@ -242,10 +238,7 @@ fapi2::ReturnCode putMMIO32( fapi2::ReturnCode putScom( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_scomAddr, - const fapi2::buffer<uint64_t>& i_data) ; - - - + const fapi2::buffer<uint64_t>& i_data); /// @brief Writes 32 bits of data to OpenCAPI config space /// @@ -257,10 +250,7 @@ fapi2::ReturnCode putScom( fapi2::ReturnCode putOCCfg( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_cfgAddr, - const fapi2::buffer<uint32_t>& i_data) ; - - - + const fapi2::buffer<uint32_t>& i_data); /// @brief Writes user_input_msdg to the data buffer /// @@ -274,9 +264,6 @@ fapi2::ReturnCode putUserInputMsdg( const user_input_msdg& i_data, uint32_t& o_crc); - - - /// @brief Writes a command to the command buffer and issues interrupt /// /// @param[in] i_target The Explorer chip to issue the command to @@ -285,9 +272,7 @@ fapi2::ReturnCode putUserInputMsdg( /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode putCMD( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - const host_fw_command_struct& i_cmd) ; - - + const host_fw_command_struct& i_cmd); //-------------------------------------------------------------------------------- // Read operations @@ -303,10 +288,7 @@ fapi2::ReturnCode putCMD( fapi2::ReturnCode getMMIO64( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - fapi2::buffer<uint64_t>& o_data) ; - - - + fapi2::buffer<uint64_t>& o_data); /// @brief Reads 32 bits of data from MMIO space on the selected Explorer /// @@ -318,10 +300,7 @@ fapi2::ReturnCode getMMIO64( fapi2::ReturnCode getMMIO32( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_addr, - fapi2::buffer<uint32_t>& o_data) ; - - - + fapi2::buffer<uint32_t>& o_data); /// @brief Reads 64 bits of data from SCOM MMIO space on the selected Explorer /// @@ -333,10 +312,7 @@ fapi2::ReturnCode getMMIO32( fapi2::ReturnCode getScom( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_scomAddr, - fapi2::buffer<uint64_t>& o_data) ; - - - + fapi2::buffer<uint64_t>& o_data); /// @brief Reads 32 bits of data from OpenCAPI config space on the selected Explorer /// @@ -348,10 +324,21 @@ fapi2::ReturnCode getScom( fapi2::ReturnCode getOCCfg( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const uint64_t i_cfgAddr, - fapi2::buffer<uint32_t>& o_data) ; - + fapi2::buffer<uint32_t>& o_data); +/// +/// @brief Polls for response ready door bell bit +/// @param[in] i_target the OCMB target on which to operate +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode poll_for_response_ready(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); +/// +/// @brief Clears outbound (response ready) door bell bit +/// @param[in] i_target the OCMB target on which to operate +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode clear_outbound_doorbell(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); /// @brief Reads a response from the response buffer /// @@ -363,10 +350,8 @@ fapi2::ReturnCode getOCCfg( /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode getRSP( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - host_fw_response_struct& o_rsp, std::vector<uint8_t>& o_data) ; - - - + host_fw_response_struct& o_rsp, + std::vector<uint8_t>& o_data); /// @brief Reads the complete 64 byte sensor cache on the selected Explorer /// @@ -376,12 +361,51 @@ fapi2::ReturnCode getRSP( /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode getSensorCache( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - sensor_cache_struct& o_data) ; + sensor_cache_struct& o_data); //-------------------------------------------------------------------------------- // Command/Response/Data structure Endian handling //-------------------------------------------------------------------------------- +/// +/// @brief UT helper for correctMMIOEndianForStruct +/// +/// @param[in] i_endian_ctrl value of ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL +/// @param[in,out] io_data value to swizzle +/// +void correctMMIOEndianForStruct_helper(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_ENDIAN_CTRL_Type i_endian_ctrl, + std::vector<uint8_t>& io_data); + +/// +/// @brief We will use 4 or 8 byte reads via fapi2::put/getMMIO for buffer +/// data structures. The byte order of the 4 or 8 byte reads should be little +/// endian. In order to represent the data structure in its proper layout +/// the endianness of each 4 or 8 byte read must be corrected. +/// @param[in,out] io_data Either data structure in proper byte order that we +/// want to swizzle prior to writing to the buffer, or the data returned +/// from reading the buffer that we want to unsizzle. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode correctMMIOEndianForStruct(std::vector<uint8_t>& io_data); + +/// +/// @brief UT helper for correctMMIOword_order +/// @param[in] i_word_swap value of ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP +/// @param[in,out] io_data value to swizzle +/// +void correctMMIOword_order_helper(fapi2::ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP_Type i_word_swap, + std::vector<uint8_t>& io_data); + +/// +/// @brief Because of how the AXI bridge in Explorer breaks up the transaction, +/// we might need to swap 32-bit word order +/// @param[in,out] io_data Either data structure in proper byte order that we +/// want to swizzle prior to writing to the buffer, or the data returned +/// from reading the buffer that we want to unsizzle. +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode correctMMIOword_order(std::vector<uint8_t>& io_data); + /// @brief We will use 4 or 8 byte reads via fapi2::put/getMMIO for buffer /// data structures. The byte order of the 4 or 8 byte reads should be little /// endian. In order to represent the data structure in its proper layout @@ -394,6 +418,30 @@ fapi2::ReturnCode getSensorCache( /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. fapi2::ReturnCode correctMMIOEndianForStruct(std::vector<uint8_t>& io_data); +/// @brief Because of how the AXI bridge in Explorer breaks up the transaction, +/// we might need to swap 32-bit word order +/// @param[in,out] io_data Either data structure in proper byte order that we +/// want to swizzle prior to writing to the buffer, or the data returned +/// from reading the buffer that we want to unsizzle. +/// +/// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. +fapi2::ReturnCode correctMMIOword_order(std::vector<uint8_t>& io_data); + +/// @brief Ensure data is an even multiple of 8 (BUFFER_TRANSACTION_SIZE). +/// If (sizeof(buffer) % BUFFER_TRANSACTION_SIZE != 0) ; then pad +/// buffer with zeros until statement is true. +/// +/// @param[in,out] io_data Communication data , either CMD or RSP buffer +/// +/// @return void +inline void padCommData(std::vector<uint8_t>& io_data) +{ + while ((io_data.size() % BUFFER_TRANSACTION_SIZE) != 0) + { + io_data.push_back(0); + } +} + /// /// @brief Forces native data into the correct endianness necessary for Explorer /// buffer data structures. @@ -402,7 +450,7 @@ fapi2::ReturnCode correctMMIOEndianForStruct(std::vector<uint8_t>& io_data); /// @param[in,out] io_data vector to append data to /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// -template < typename T > +template <typename T> fapi2::ReturnCode forceCrctEndian(const T& i_input, std::vector<uint8_t>& io_data); /// @@ -414,7 +462,7 @@ fapi2::ReturnCode forceCrctEndian(const T& i_input, std::vector<uint8_t>& io_dat /// @param[in,out] io_data vector to append data to /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// -template < typename T > +template <typename T> fapi2::ReturnCode forceCrctEndianArray(const T* i_input, const uint64_t i_size, std::vector<uint8_t>& io_data); /// @@ -426,7 +474,7 @@ fapi2::ReturnCode forceCrctEndianArray(const T* i_input, const uint64_t i_size, /// @param[out] o_data data that has been converted into native endianness /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// -template < typename T > +template <typename T> fapi2::ReturnCode readCrctEndian(const std::vector<uint8_t>& i_input, uint32_t& io_idx, T& o_data); /// @@ -439,16 +487,16 @@ fapi2::ReturnCode readCrctEndian(const std::vector<uint8_t>& i_input, uint32_t& /// @param[out] o_data data that has been converted into native endianness /// @return fapi2::ReturnCode. FAPI2_RC_SUCCESS if success, else error code. /// -template < typename T > +template <typename T> fapi2::ReturnCode readCrctEndianArray(const std::vector<uint8_t>& i_input, const uint32_t i_size, uint32_t& io_idx, T* o_data); //-------------------------------------------------------------------------------- -} // ns ib +} // namespace ib -} // ns exp +} // namespace exp -} // ns mss +} // namespace mss #endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C new file mode 100644 index 000000000..e4d733180 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C @@ -0,0 +1,81 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_port.C +/// @brief Code to support ports +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include <fapi2.H> +#include <lib/shared/exp_defaults.H> +#include <exp_port.H> + +namespace mss +{ + +/// +/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc) +/// @param[in] i_target the target +/// @param[in,out] io_data contents of RECR register +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note mc_type::EXPLORER specialization +/// +template< > +fapi2::ReturnCode ecc_reg_settings_draminit_mc<mss::mc_type::EXPLORER>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + fapi2::buffer<uint64_t>& io_data ) +{ + using TT = portTraits<mss::mc_type::EXPLORER>; + fapi2::buffer<uint64_t> l_ctcr_data; + + // Explorer specific settings for RECR + io_data.setBit<TT::RECR_ENABLE_MPE_NOISE_WINDOW>(); + io_data.setBit<TT::RECR_RETRY_UNMARKED_ERRORS>(); + io_data.clearBit<TT::RECR_CFG_MAINT_USE_TIMERS>(); + + // Set up CTCR timers to 20x4^3 (1280 clock cycles; typical read latency is 120ish, so this is about 10x) + // This is a preliminary guess from the design team. Also enable UE lockout window + // CTCR -> 51A8E00000000000 + FAPI_TRY( mss::getScom(i_target, TT::CTCR_REG, l_ctcr_data) ); + + l_ctcr_data.insertFromRight<TT::CTCR_MPE_TIMER, TT::CTCR_MPE_TIMER_LEN>(0b010100); + l_ctcr_data.insertFromRight<TT::CTCR_MPE_TIMEBASE, TT::CTCR_MPE_TIMEBASE_LEN>(0b011); + l_ctcr_data.insertFromRight<TT::CTCR_UE_TIMER, TT::CTCR_UE_TIMER_LEN>(0b010100); + l_ctcr_data.insertFromRight<TT::CTCR_UE_TIMEBASE, TT::CTCR_UE_TIMEBASE_LEN>(0b011); + l_ctcr_data.setBit<TT::CTCR_UE_LOCKOUT_ENABLE>(); + + FAPI_TRY( mss::putScom(i_target, TT::CTCR_REG, l_ctcr_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +}// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H index a65375672..57646e97a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,31 +39,22 @@ #include <fapi2.H> #include <explorer_scom_addresses.H> #include <explorer_scom_addresses_fld.H> +#include <explorer_scom_addresses_fld_fixes.H> #include <lib/exp_attribute_accessors_manual.H> +#include <lib/utils/mss_exp_conversions.H> +#include <mss_explorer_attribute_getters.H> #include <lib/shared/exp_consts.H> +#include <lib/dimm/exp_rank.H> #include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> -#include <mss_explorer_attribute_getters.H> +#include <mss_generic_attribute_getters.H> namespace mss { -/// -/// @brief ATTR_MSS_MEM_MVPD_FWMS getter -/// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> -/// @param[out] uint32_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Mark store records from MPVD Lx -/// keyword -/// -template<> -inline fapi2::ReturnCode mvpd_fwms(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - uint32_t (&o_array)[mss::MARK_STORE_COUNT]) -{ - return mss::attr::get_mvpd_fwms(i_target, o_array); -} - +////////////////////////////////////////////////////////////// +// Traits values for EXPLORER +////////////////////////////////////////////////////////////// /// /// @class Traits and policy class for port code - specialization for Explorer. The target of registers is TARGET_TYPE_OCMB_CHIP /// @@ -71,6 +62,9 @@ template<> class portTraits< mss::mc_type::EXPLORER > { public: + // PORT_TYPE + static constexpr fapi2::TargetType PORT_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + // scom register definition static constexpr uint64_t MBARPC0Q_REG = EXPLR_SRQ_MBARPC0Q; @@ -78,8 +72,11 @@ class portTraits< mss::mc_type::EXPLORER > static constexpr uint64_t FARB5Q_REG = EXPLR_SRQ_MBA_FARB5Q; static constexpr uint64_t FARB6Q_REG = EXPLR_SRQ_MBA_FARB6Q; static constexpr uint64_t FARB9Q_REG = EXPLR_SRQ_MBA_FARB9Q; + static constexpr uint64_t PMU8Q_REG = EXPLR_SRQ_MBA_PMU8Q; static constexpr uint64_t REFRESH_REG = EXPLR_SRQ_MBAREF0Q; + static constexpr uint64_t STR0Q_REG = EXPLR_SRQ_MBASTR0Q; static constexpr uint64_t ECC_REG = EXPLR_RDF_RECR; + static constexpr uint64_t CTCR_REG = EXPLR_RDF_CTCR; static constexpr uint64_t DSM0Q_REG = EXPLR_SRQ_MBA_DSM0Q; static constexpr uint64_t FWMS_REG = EXPLR_RDF_FWMS0; @@ -96,23 +93,45 @@ class portTraits< mss::mc_type::EXPLORER > CFG_CCS_INST_RESET_ENABLE = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE, CFG_DDR_RESETN = EXPLR_SRQ_MBA_FARB5Q_CFG_DDR_RESETN, CFG_CCS_ADDR_MUX_SEL = EXPLR_SRQ_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL, - //TODO: It's not defined in scom register header file. Change this once it's available in scom address header file - CFG_INIT_COMPLETE = 32, //EXPLR_SRQ_MBA_FARB6Q_CFG_INIT_COMPLETE, + CFG_INIT_COMPLETE = EXPLR_SRQ_MBA_PMU8Q_CFG_INIT_COMPLETE, CFG_ZQ_PER_CAL_ENABLE = EXPLR_SRQ_MBA_FARB9Q_CFG_ZQ_PER_CAL_ENABLE, REFRESH_ENABLE = EXPLR_SRQ_MBAREF0Q_CFG_REFRESH_ENABLE, + CFG_FORCE_STR = EXPLR_SRQ_MBASTR0Q_CFG_FORCE_STR, + ECC_CHECK_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CHECK_CORRECT, ECC_CORRECT_DISABLE = EXPLR_RDF_RECR_MBSECCQ_DISABLE_MEMORY_ECC_CORRECT, ECC_USE_ADDR_HASH = EXPLR_RDF_RECR_MBSECCQ_USE_ADDRESS_HASH, PORT_FAIL_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE, - DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_MISR_FEEDBACK_ENABLE, + DFI_INIT_START = EXPLR_SRQ_MBA_FARB0Q_CFG_INIT_START, RCD_RECOVERY_DISABLE = EXPLR_SRQ_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY, + BW_WINDOW_SIZE = EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE, + BW_WINDOW_SIZE_LEN = EXPLR_SRQ_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN, + BW_SNAPSHOT = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT, + BW_SNAPSHOT_LEN = EXPLR_SRQ_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN, + RECR_ENABLE_MPE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_MPE_NOISE_WINDOW, + RECR_ENABLE_UE_NOISE_WINDOW = EXPLR_RDF_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = EXPLR_RDF_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_MBSECCQ_DATA_INVERSION = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION, RECR_MBSECCQ_DATA_INVERSION_LEN = EXPLR_RDF_RECR_MBSECCQ_DATA_INVERSION_LEN, + RECR_RETRY_UNMARKED_ERRORS = EXPLR_RDF_RECR_RETRY_UNMARKED_ERRORS, + RECR_CFG_MAINT_USE_TIMERS = EXPLR_RDF_RECR_CFG_MAINT_USE_TIMERS, + RECR_MBSECCQ_MAINT_NO_RETRY_UE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_UE, + RECR_MBSECCQ_MAINT_NO_RETRY_MPE = EXPLR_RDF_RECR_MBSECCQ_MAINT_NO_RETRY_MPE, + + CTCR_MPE_TIMER = EXPLR_RDF_CTCR_MPE_TIMER, + CTCR_MPE_TIMER_LEN = EXPLR_RDF_CTCR_MPE_TIMER_LEN, + CTCR_MPE_TIMEBASE = EXPLR_RDF_CTCR_MPE_TIMEBASE, + CTCR_MPE_TIMEBASE_LEN = EXPLR_RDF_CTCR_MPE_TIMEBASE_LEN, + CTCR_UE_TIMER = EXPLR_RDF_CTCR_UE_TIMER, + CTCR_UE_TIMER_LEN = EXPLR_RDF_CTCR_UE_TIMER_LEN, + CTCR_UE_TIMEBASE = EXPLR_RDF_CTCR_UE_TIMEBASE, + CTCR_UE_TIMEBASE_LEN = EXPLR_RDF_CTCR_UE_TIMEBASE_LEN, + CTCR_UE_LOCKOUT_ENABLE = EXPLR_RDF_CTCR_UE_LOCKOUT_ENABLE, + DSM0Q_RDTAG_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = EXPLR_SRQ_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, DSM0Q_WRDONE_DLY = EXPLR_SRQ_MBA_DSM0Q_CFG_WRDONE_DLY, @@ -129,6 +148,60 @@ class portTraits< mss::mc_type::EXPLORER > }; }; +/// +/// @brief ATTR_MSS_MEM_MVPD_FWMS getter +/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP +/// @param[out] uint32_t&[] array reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Mark store records from OCMB VPD. The array dimension is [port][mark]. Explorer +/// only has one port so only [0][mark] is used in explorer. +/// +template<> +inline fapi2::ReturnCode mvpd_fwms< mss::mc_type::EXPLORER >( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint32_t (&o_array)[mss::MARK_STORE_COUNT]) +{ + return mss::attr::get_mvpd_fwms(i_target, o_array); +} + +/// @brief Get the attributes for the reorder queue setting +/// @param[in] const ref to the mc target +/// @param[out] uint8_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Contains the settings for write/read reorder +/// queue +/// +template< > +inline fapi2::ReturnCode reorder_queue_setting<mss::mc_type::EXPLORER>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint8_t& o_value) +{ + return mss::attr::get_reorder_queue_setting(i_target, o_value); +} + +/// +/// @brief Change the state of the force_str bit - mc_type::EXPLORER specialization +/// @tparam MC the memory controller type +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +template< > +inline fapi2::ReturnCode change_force_str<DEFAULT_MC_TYPE>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const states i_state ) +{ + using TT = portTraits<mss::mc_type::EXPLORER>; + fapi2::buffer<uint64_t> l_data; + + FAPI_DBG("Change force_str to %s %s", (i_state == HIGH ? "high" : "low"), mss::c_str(i_target)); + FAPI_TRY( mss::getScom(i_target, TT::STR0Q_REG, l_data) ); + l_data.writeBit<TT::CFG_FORCE_STR>(i_state); + FAPI_TRY( mss::putScom(i_target, TT::STR0Q_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port_traits.H index c552c0454..e76d5b70d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port_traits.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.C $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mc/exp_port_traits.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/address.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/address.H deleted file mode 100644 index 6f300a2ce..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/address.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/address.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_address.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_address.H index af8933ce4..6cf1c5a71 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_address.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_address.H @@ -22,3 +22,28 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_address.H +/// @brief Class for mcbist related addresses (addresses below the hash translation) +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_MCBIST_EXP_ADDRESS_H_ +#define _MSS_MCBIST_EXP_ADDRESS_H_ + +#include <fapi2.H> +#include <utility> +#include <lib/shared/exp_consts.H> +#include <lib/ecc/ecc_traits_explorer.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_traits.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_ecc_trap_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_fwms_address.H> + + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.C index 47d9da4af..02da32e8f 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.C @@ -22,3 +22,202 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mcbist.C +/// @brief Run and manage the MCBIST engine +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/shared/exp_defaults.H> +#include <lib/shared/exp_consts.H> +#include <lib/mcbist/exp_mcbist.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <mss_generic_attribute_getters.H> + +namespace mss +{ + +/// +/// @brief Gets the attribute for freq +/// @param[in] const ref to the target +/// @param[out] uint64_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Frequency of this memory channel in MT/s (Mega Transfers per second) +/// +template<> +fapi2::ReturnCode freq<mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint64_t& o_value) +{ + // Each OCMB only has one MEM_PORT + for (const auto l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + return attr::get_freq(l_port, o_value); + } + + o_value = 0; + return ~fapi2::FAPI2_RC_SUCCESS; +} + +const std::pair<uint64_t, uint64_t> mcbistTraits<mss::mc_type::EXPLORER>::address_pairs[] = +{ + { START_ADDRESS_0, END_ADDRESS_0 }, + { START_ADDRESS_1, END_ADDRESS_1 }, + { START_ADDRESS_2, END_ADDRESS_2 }, + { START_ADDRESS_3, END_ADDRESS_3 }, +}; + +const std::vector< mss::mcbist::op_type > mcbistTraits<mss::mc_type::EXPLORER>::FIFO_MODE_REQUIRED_OP_TYPES = +{ + mss::mcbist::op_type::WRITE , + mss::mcbist::op_type::READ , + mss::mcbist::op_type::READ_WRITE , + mss::mcbist::op_type::WRITE_READ , + mss::mcbist::op_type::READ_WRITE_READ , + mss::mcbist::op_type::READ_WRITE_WRITE , + mss::mcbist::op_type::RAND_SEQ , + mss::mcbist::op_type::READ_READ_WRITE , +}; + +// These valus are pulled out of the MCBIST specification - page 41 10-DEC-19 +// The index is the fixed width - the value is the LFSR_MASK value to be used +const std::vector< uint64_t > mcbistTraits<mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP>::LFSR_MASK_VALUES = +{ + 0x000000031, + 0x00000001F, + 0x001000000, + 0x100000000, + 0x004000003, + 0x000080000, + 0x040000018, + 0x008000000, + 0x010006000, + 0x004000000, + 0x001000000, + 0x003200000, + 0x001880000, + 0x000200000, + 0x000610000, + 0x000100000, + 0x000040000, + 0x000010000, + 0x000023000, + 0x000002000, + 0x000000400, + 0x000002000, + 0x000005008, + 0x000002000, + 0x000001088, + 0x000000B00, + 0x0000004A0, + 0x000000100, + 0x000000040, + 0x000000010, + 0x000000038, + 0x000000008, + 0x000000010, + 0x000000004, + 0x000000004, + 0x000000002, + 0x000000001, +}; + +namespace mcbist +{ +/// +/// @brief Get a list of ports involved in the program +/// Specialization for program<> +/// @param[in] i_target the target for this program +/// @return vector of port targets +/// +template<> +std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>> + program<>::get_port_list( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target ) const +{ + + return mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target); +} +/// +/// @brief Configures broadcast mode, if it is needed +/// @param[in] i_target the target to effect +/// @param[in,out] io_program the mcbist::program +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode configure_broadcast_mode(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + mcbist::program<mss::mc_type::EXPLORER>& io_program) +{ + // No broadcast mode for explorer + return fapi2::FAPI2_RC_SUCCESS; +} + +/// +/// @brief Read entries from MCBIST Read Buffer (RB) array +/// Specialization for fapi2::TARGET_TYPE_MEM_PORT +/// @param[in] i_target the target to effect +/// @param[in] i_start_addr the array address to read first +/// @param[in] i_num_entries the number of array entries to read +/// @param[out] o_data vector of output data +/// @param[out] o_ecc_data vector of ecc data +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode read_rb_array(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const uint64_t i_start_addr, + const uint64_t i_num_entries, + std::vector< fapi2::buffer<uint64_t> >& o_data, + std::vector< fapi2::buffer<uint64_t> >& o_ecc_data) +{ + using TT = mcbistTraits<DEFAULT_MC_TYPE, fapi2::TARGET_TYPE_OCMB_CHIP>; + + fapi2::buffer<uint64_t> l_data; + uint64_t l_array_addr = i_start_addr; + + const auto& l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + // Clear out any stale values from output vectors + o_data.clear(); + o_ecc_data.clear(); + + for (uint8_t l_index = 0; l_index < i_num_entries; ++l_index) + { + fapi2::buffer<uint64_t> l_control_value; + + // set start address + l_control_value.insertFromRight<TT::RB_ADDRESS, TT::RB_ADDRESS_LEN>(l_array_addr); + + FAPI_INF("Setting the RB array access control register."); + FAPI_TRY( mss::putScom(l_ocmb, TT::RD_BUF_CTL_REG, l_control_value) ); + + + // We setup the address to what we need it to be, so let's continue + FAPI_TRY( mss::getScom(i_target, TT::RD_BUF_DATA_REG, l_data) ); + FAPI_INF("RB data index %d is: 0x%016lx", l_array_addr, l_data); + o_data.push_back(l_data); + + // Need to read ecc register to increment array index + FAPI_TRY( mss::getScom(i_target, TT::RD_BUF_ECC_REG, l_data) ); + o_ecc_data.push_back(l_data); + ++l_array_addr; + + // Array address automatically rolls over if we go beyond NUM_COMPARE_LOG_ENTRIES + if (l_array_addr >= TT::NUM_COMPARE_LOG_ENTRIES) + { + l_array_addr = 0; + } + + } + +fapi_try_exit: + return fapi2::current_err; +} + +} // namespace mcbist +} // namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.H index f4d8a8bb1..13dd0ba6d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,66 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mcbist.H +/// @brief Run and manage the MCBIST engine +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_EXP_MCBIST_H_ +#define _MSS_EXP_MCBIST_H_ + +#include <fapi2.H> + +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> + +#include <lib/shared/exp_consts.H> +#include <lib/ecc/ecc_traits_explorer.H> +#include <lib/mcbist/exp_mcbist_traits.H> +#include <lib/mc/exp_port.H> +#include <lib/utils/mss_exp_conversions.H> +#include <generic/memory/lib/utils/poll.H> +#include <generic/memory/lib/utils/memory_size.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_patterns.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_settings.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist.H> + +namespace mss +{ + +namespace mcbist +{ + +/// +/// @brief Load MCBIST ECC (and?) spare data pattern given a pattern - explorer specialization +/// @param[in] i_target the target to effect +/// @param[in] i_pattern an mcbist::patterns +/// @param[in] i_invert whether to invert the pattern or not +/// @return FAPI2_RC_SUCCSS iff ok +/// +template< > +inline fapi2::ReturnCode load_eccspare_pattern<mss::mc_type::EXPLORER>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const pattern& i_pattern, + const bool i_invert ) +{ + // First up assemble the pattern + const auto l_pattern = generate_eccspare_pattern(i_pattern, i_invert); + + FAPI_TRY(fapi2::putScom(i_target, EXPLR_MCBIST_MCBFDQ, l_pattern)); + FAPI_TRY(fapi2::putScom(i_target, EXPLR_MCBIST_MCBFDSPQ, l_pattern)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns mss + +} // ns mcbist +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H index 3c848de59..72f06be05 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_mcbist_traits.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,627 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_mcbist_traits.H +/// @brief Run and manage the MCBIST engine +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_EXP_MCBIST_TRAITS_H_ +#define _MSS_EXP_MCBIST_TRAITS_H_ + +#include <fapi2.H> + +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> + +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist.H> + +namespace mss +{ + +/// +/// @class mcbistMCTraits +/// @brief A MC to MC_TARGET_TYPE mapping specialization for EXPLORER +/// +template<> +class mcbistMCTraits< mss::mc_type::EXPLORER> +{ + public: + static constexpr fapi2::TargetType MC_TARGET_TYPE = fapi2::TARGET_TYPE_OCMB_CHIP; + static constexpr fapi2::TargetType FWMS_ADDR_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + + /// + /// @brief Returns an error for memdiags compare error in last pattern + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN memdiags_compare_error_in_last_pattern() + { + return fapi2::EXP_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN(); + } + + /// + /// @brief Returns an error for memdiags error in last pattern + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_ERROR_IN_LAST_PATTERN memdiags_error_in_last_pattern() + { + return fapi2::EXP_MEMDIAGS_ERROR_IN_LAST_PATTERN(); + } + + /// + /// @brief Returns an error if memdiags failed to start + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_MCBIST_FAILED_TO_START memdiags_failed_to_start() + { + return fapi2::EXP_MEMDIAGS_MCBIST_FAILED_TO_START(); + } + + /// + /// @brief Returns an error if memdiags failed to stop + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_MCBIST_FAILED_TO_STOP memdiags_failed_to_stop() + { + return fapi2::EXP_MEMDIAGS_MCBIST_FAILED_TO_STOP(); + } + + /// + /// @brief Returns an error if memdiags has a non-functional port + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_PORT_NOT_FUNCTIONAL memdiags_port_not_functional() + { + return fapi2::EXP_MEMDIAGS_PORT_NOT_FUNCTIONAL(); + } + + /// + /// @brief Returns an error if memdiags super fast init failed to init + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT memdiags_sf_init_failed_init() + { + return fapi2::EXP_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags super fast read failed to init + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT memdiags_sf_read_failed_init() + { + return fapi2::EXP_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags super fast read failed to init + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT memdiags_continuous_scrub_failed_init() + { + return fapi2::EXP_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags targeted scrub failed to init + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT memdiags_targeted_scrub_failed_init() + { + return fapi2::EXP_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags is already at a boundary + /// @return memdiags error + /// + static fapi2::EXP_MEMDIAGS_ALREADY_AT_BOUNDARY memdiags_already_at_boundary() + { + return fapi2::EXP_MEMDIAGS_ALREADY_AT_BOUNDARY(); + } + + /// + /// @brief Returns an error if MCBIST timesout + /// @return MCBIST error + /// + static fapi2::EXP_MCBIST_TIMEOUT mcbist_timeout() + { + return fapi2::EXP_MCBIST_TIMEOUT(); + } + + /// + /// @brief Returns an error if MCBIST has an unknown failure + /// @return MCBIST error + /// + static fapi2::EXP_MCBIST_UNKNOWN_FAILURE mcbist_unknown_failure() + { + return fapi2::EXP_MCBIST_UNKNOWN_FAILURE(); + } + + /// + /// @brief Returns an error if MCBIST has a data miscompare + /// @return MCBIST error + /// + static fapi2::EXP_MCBIST_DATA_FAIL mcbist_data_fail() + { + return fapi2::EXP_MCBIST_DATA_FAIL(); + } +}; + +/// +/// @class mcbistTraits +/// @brief a collection of traits associated with the Explorer MCBIST engine or hardware +/// +template<> +class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_OCMB_CHIP> +{ + public: + + // PORT_TYPE used in continuous_scrub_operation + static constexpr fapi2::TargetType PORT_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + + // ATTN support + static constexpr mss::states CFG_ENABLE_ATTN_SUPPORT = mss::states::NO; + static constexpr mss::states BROADCAST_CAPABLE = mss::states::NO; + + // Multi-ports, dimms + static constexpr mss::states MULTI_PORTS = mss::states::NO; + + // Subtest + static constexpr size_t SUBTEST_PER_REG = 4; + static constexpr size_t SUBTEST_PER_PROGRAM = 32; + static constexpr size_t BITS_IN_SUBTEST = 16; // 2 Bytes + static constexpr size_t LEFT_SHIFT = (sizeof(uint64_t) * 8) - BITS_IN_SUBTEST; + + // LARGEST_ADDRESS. port select (bit0~1) are always 0 so shift 2 more bits. + static constexpr uint64_t LARGEST_ADDRESS = ~0 >> (mss::mcbist::address::MAGIC_PAD + 2); + + // Length of expected patterns + static constexpr uint64_t EXPECTED_PATTERN_SIZE = 4; + + // Size + static constexpr size_t PORTS_PER_MCBIST = mss::exp::MAX_PORT_PER_OCMB; + static constexpr size_t MAX_DIMM_PER_PORT = mss::exp::MAX_DIMM_PER_PORT; + // Closest we've got to primary rank + static constexpr size_t MAX_PRIMARY_RANKS_PER_PORT = mss::exp::MAX_RANK_PER_DIMM; + static constexpr size_t MAX_DQ_BITS = 80; + static constexpr size_t MAX_DQ_NIBBLES = MAX_DQ_BITS / BITS_PER_NIBBLE; + static constexpr size_t MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_BYTE; + static constexpr size_t MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE; + + /// MCBIST "memory registers" - config for subtests. + static constexpr uint64_t MCBMR0_REG = EXPLR_MCBIST_MCBMR0Q; + static constexpr uint64_t MCBMR1_REG = EXPLR_MCBIST_MCBMR1Q; + static constexpr uint64_t MCBMR2_REG = EXPLR_MCBIST_MCBMR2Q; + static constexpr uint64_t MCBMR3_REG = EXPLR_MCBIST_MCBMR3Q; + static constexpr uint64_t MCBMR4_REG = EXPLR_MCBIST_MCBMR4Q; + static constexpr uint64_t MCBMR5_REG = EXPLR_MCBIST_MCBMR5Q; + static constexpr uint64_t MCBMR6_REG = EXPLR_MCBIST_MCBMR6Q; + static constexpr uint64_t MCBMR7_REG = EXPLR_MCBIST_MCBMR7Q; + static constexpr uint64_t CFGQ_REG = EXPLR_MCBIST_MCBCFGQ; + static constexpr uint64_t CNTLQ_REG = EXPLR_MCBIST_MCB_CNTLQ; + static constexpr uint64_t STATQ_REG = EXPLR_MCBIST_MCB_CNTLSTATQ; + static constexpr uint64_t MCBSTATQ_REG = EXPLR_MCBIST_MCBSTATQ; + static constexpr uint64_t MCBPARMQ_REG = EXPLR_MCBIST_MCBPARMQ; + static constexpr uint64_t MCBAGRAQ_REG = EXPLR_MCBIST_MCBAGRAQ; + static constexpr uint64_t SRERR0_REG = EXPLR_MCBIST_MBSEC0Q; + static constexpr uint64_t SRERR1_REG = EXPLR_MCBIST_MBSEC1Q; + static constexpr uint64_t THRESHOLD_REG = EXPLR_MCBIST_MBSTRQ; + static constexpr uint64_t FIRQ_REG = EXPLR_MCBIST_MCBISTFIRQ; + static constexpr uint64_t LAST_ADDR_REG = EXPLR_MCBIST_MCBMCATQ; + + static constexpr uint64_t MCBAMR0A0Q_REG = EXPLR_MCBIST_MCBAMR0A0Q; + static constexpr uint64_t MCBAMR1A0Q_REG = EXPLR_MCBIST_MCBAMR1A0Q; + static constexpr uint64_t MCBAMR2A0Q_REG = EXPLR_MCBIST_MCBAMR2A0Q; + static constexpr uint64_t MCBAMR3A0Q_REG = EXPLR_MCBIST_MCBAMR3A0Q; + static constexpr uint64_t LFSR_REG = EXPLR_MCBIST_MCBLFSRA0Q; + static const std::vector<uint64_t> LFSR_MASK_VALUES; + + // All of the pattern registers are calculated off of this base + static constexpr uint64_t PATTERN0_REG = EXPLR_MCBIST_MCBFD0Q; + static constexpr uint64_t PATTERN1_REG = EXPLR_MCBIST_MCBFD1Q; + static constexpr uint64_t PATTERN2_REG = EXPLR_MCBIST_MCBFD2Q; + static constexpr uint64_t PATTERN3_REG = EXPLR_MCBIST_MCBFD3Q; + static constexpr uint64_t PATTERN4_REG = EXPLR_MCBIST_MCBFD4Q; + static constexpr uint64_t PATTERN5_REG = EXPLR_MCBIST_MCBFD5Q; + static constexpr uint64_t PATTERN6_REG = EXPLR_MCBIST_MCBFD6Q; + static constexpr uint64_t PATTERN7_REG = EXPLR_MCBIST_MCBFD7Q; + + static constexpr uint64_t DATA_ROTATE_CNFG_REG = EXPLR_MCBIST_MCBDRCRQ; + static constexpr uint64_t DATA_ROTATE_SEED_REG = EXPLR_MCBIST_MCBDRSRQ; + + static constexpr uint16_t MAX_ADDRESS_START_END_REGISTERS = 4; + static constexpr uint64_t START_ADDRESS_0 = EXPLR_MCBIST_MCBSA0Q; + static constexpr uint64_t START_ADDRESS_1 = EXPLR_MCBIST_MCBSA1Q; + static constexpr uint64_t START_ADDRESS_2 = EXPLR_MCBIST_MCBSA2Q; + static constexpr uint64_t START_ADDRESS_3 = EXPLR_MCBIST_MCBSA3Q; + + static constexpr uint64_t END_ADDRESS_0 = EXPLR_MCBIST_MCBEA0Q; + static constexpr uint64_t END_ADDRESS_1 = EXPLR_MCBIST_MCBEA1Q; + static constexpr uint64_t END_ADDRESS_2 = EXPLR_MCBIST_MCBEA2Q; + static constexpr uint64_t END_ADDRESS_3 = EXPLR_MCBIST_MCBEA3Q; + + static constexpr uint64_t RANDOM_DATA_SEED0 = EXPLR_MCBIST_MCBRDS0Q; + static constexpr uint64_t RANDOM_DATA_SEED1 = EXPLR_MCBIST_MCBRDS1Q; + + static constexpr uint64_t MBSTRQ_CFG_PAUSE_ON_MPE = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE; + + // MCBIST Compare Masks, used to setup the ECC traps + static constexpr uint64_t COMPARE_MASK = EXPLR_RDF_MCBCM; + + static constexpr uint64_t PATTERN_COUNT = 4; + + // Sometimes we want to access the start/end address registers based off + // of an index, like master rank. This allows us to do that. + static const std::pair<uint64_t, uint64_t> address_pairs[]; + static constexpr uint64_t ADDRESS_PAIRS = 4; + + // Subtest types that need to be run in FIFO mode + static const std::vector< mss::mcbist::op_type > FIFO_MODE_REQUIRED_OP_TYPES; + + // Which bit in the end boundary which siginifies this is a slave rank detect situation + static constexpr uint64_t SLAVE_RANK_INDICATED_BIT = 61; + + enum + { + // The start/end address config registers have common lengths and bits, just including 1 below + MCB_ADDR_CONFIG = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0, + MCB_ADDR_CONFIG_LEN = EXPLR_MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN, + + // Subtest control bits. These are the same in all '16 bit subtest' field + COMPL_1ST_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, + COMPL_2ND_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD, + COMPL_3RD_CMD = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD, + ADDR_REV_MODE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE, + ADDR_RAND_MODE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE, + + // Goto subtests use the compl_1st - rand_mode to define the subtest to jump to + GOTO_SUBTEST = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, + GOTO_SUBTEST_LEN = 5, + + ECC_MODE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE, + DATA_MODE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE, + DATA_MODE_LEN = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN, + ADDR_SEL = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL, + ADDR_SEL_LEN = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN, + OP_TYPE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE, + OP_TYPE_LEN = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN, + DONE = EXPLR_MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE, + + // No broadcast in explorer due to only one port per MCBIST + // SYNC_EN + // SYNC_WAIT + // SYNC_WAIT_LEN + + // No port sel in explorer due to only one port per MCBIST + PORT_SEL = 0, + PORT_SEL_LEN = 1, + + MCBIST_START = EXPLR_MCBIST_MCB_CNTLQ_START, + MCBIST_STOP = EXPLR_MCBIST_MCB_CNTLQ_STOP, + MCBIST_RESUME = EXPLR_MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE, + MCBIST_RESET_ERRORS = EXPLR_MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS, + + MCBIST_IN_PROGRESS = EXPLR_MCBIST_MCB_CNTLSTATQ_IP, + MCBIST_DONE = EXPLR_MCBIST_MCB_CNTLSTATQ_DONE, + MCBIST_FAIL = EXPLR_MCBIST_MCB_CNTLSTATQ_FAIL, + + MIN_CMD_GAP = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP, + MIN_CMD_GAP_LEN = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN, + MIN_GAP_TIMEBASE = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE, + MIN_CMD_GAP_BLIND_STEER = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER, + MIN_CMD_GAP_BLIND_STEER_LEN = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN, + MIN_GAP_TIMEBASE_BLIND_STEER = EXPLR_MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER, + RANDCMD_WGT = EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT, + RANDCMD_WGT_LEN = EXPLR_MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN, + // No clock monitor for explorer + // CLOCK_MONITOR_EN + EN_RANDCMD_GAP = EXPLR_MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP, + RANDGAP_WGT = EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT, + RANDGAP_WGT_LEN = EXPLR_MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN, + BC4_EN = EXPLR_MCBIST_MCBPARMQ_CFG_BC4_EN, + + FIXED_WIDTH = EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH, + FIXED_WIDTH_LEN = EXPLR_MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN, + ADDR_COUNTER_MODE = EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE, + ADDR_COUNTER_MODE_LEN = EXPLR_MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN, + MAINT_ADDR_MODE_EN = EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN, + + // No broadcast in explorer due to only one port per MCBIST + //MAINT_BROADCAST_MODE_EN + MAINT_DETECT_SRANK_BOUNDARIES = EXPLR_MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES, + + CFG_CMD_TIMEOUT_MODE = EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE, + CFG_CMD_TIMEOUT_MODE_LEN = EXPLR_MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN, + RESET_KEEPER = EXPLR_MCBIST_MCBCFGQ_RESET_KEEPER, + CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = EXPLR_MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS, + CFG_CCS_RETRY_DIS = EXPLR_MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS, + CFG_RESET_CNTS_START_OF_RANK = EXPLR_MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK, + CFG_LOG_COUNTS_IN_TRACE = EXPLR_MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE, + SKIP_INVALID_ADDR_DIMM_DIS = EXPLR_MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS, + REFRESH_ONLY_SUBTEST_EN = EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN, + REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL, + REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = EXPLR_MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN, + RAND_ADDR_ALL_ADDR_MODE_EN = EXPLR_MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN, + MCBIST_CFG_REF_WAIT_TIME = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME, + MCBIST_CFG_REF_WAIT_TIME_LEN = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN, + CFG_MCB_LEN64 = EXPLR_MCBIST_MCBCFGQ_CFG_MCB_LEN64, + CFG_PAUSE_ON_ERROR_MODE = EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE, + CFG_PAUSE_ON_ERROR_MODE_LEN = EXPLR_MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN, + MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST, + MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR, + MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST, + + // No ATTN in explorer + CFG_ENABLE_SPEC_ATTN = 0, + CFG_ENABLE_HOST_ATTN = 0, + MCBIST_CFG_PAUSE_AFTER_RANK = EXPLR_MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK, + + LOGGED_ERROR_ON_PORT_INDICATOR = EXPLR_MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR, + LOGGED_ERROR_ON_PORT_INDICATOR_LEN = 1, + SUBTEST_NUM_INDICATOR = EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR, + SUBTEST_NUM_INDICATOR_LEN = EXPLR_MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN, + + UE_COUNT = EXPLR_MCBIST_MBSEC1Q_UE_COUNT, + UE_COUNT_LEN = EXPLR_MCBIST_MBSEC1Q_UE_COUNT_LEN, + + MBSTRQ_CFG_MAINT_RCE_WITH_CE = EXPLR_MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE, + + CFG_AMAP_DIMM_SELECT = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT, + CFG_AMAP_DIMM_SELECT_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN, + CFG_AMAP_MRANK0 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0, + CFG_AMAP_MRANK0_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN, + CFG_AMAP_MRANK1 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1, + CFG_AMAP_MRANK1_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN, + CFG_AMAP_SRANK0 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0, + CFG_AMAP_SRANK0_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN, + CFG_AMAP_SRANK1 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1, + CFG_AMAP_SRANK1_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN, + CFG_AMAP_SRANK2 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2, + CFG_AMAP_SRANK2_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN, + CFG_AMAP_BANK2 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2, + CFG_AMAP_BANK2_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN , + CFG_AMAP_BANK1 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1, + CFG_AMAP_BANK1_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN , + CFG_AMAP_BANK0 = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0, + CFG_AMAP_BANK0_LEN = EXPLR_MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN , + + CFG_AMAP_BANK_GROUP1 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1, + CFG_AMAP_BANK_GROUP1_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN , + CFG_AMAP_BANK_GROUP0 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0, + CFG_AMAP_BANK_GROUP0_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN , + CFG_AMAP_ROW17 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17, + CFG_AMAP_ROW17_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN, + CFG_AMAP_ROW16 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16, + CFG_AMAP_ROW16_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN, + CFG_AMAP_ROW15 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15, + CFG_AMAP_ROW15_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN, + CFG_AMAP_ROW14 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14, + CFG_AMAP_ROW14_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN, + CFG_AMAP_ROW13 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13, + CFG_AMAP_ROW13_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN, + CFG_AMAP_ROW12 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12, + CFG_AMAP_ROW12_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN, + CFG_AMAP_ROW11 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11, + CFG_AMAP_ROW11_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN, + CFG_AMAP_ROW10 = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10, + CFG_AMAP_ROW10_LEN = EXPLR_MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN, + + CFG_AMAP_ROW9 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9, + CFG_AMAP_ROW9_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN, + CFG_AMAP_ROW8 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8, + CFG_AMAP_ROW8_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN, + CFG_AMAP_ROW7 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7, + CFG_AMAP_ROW7_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN, + CFG_AMAP_ROW6 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6, + CFG_AMAP_ROW6_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN, + CFG_AMAP_ROW5 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5, + CFG_AMAP_ROW5_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN, + CFG_AMAP_ROW4 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4, + CFG_AMAP_ROW4_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN, + CFG_AMAP_ROW3 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3, + CFG_AMAP_ROW3_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN, + CFG_AMAP_ROW2 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2, + CFG_AMAP_ROW2_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN, + CFG_AMAP_ROW1 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1, + CFG_AMAP_ROW1_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN, + CFG_AMAP_ROW0 = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0, + CFG_AMAP_ROW0_LEN = EXPLR_MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN, + + CFG_AMAP_COL9 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9, + CFG_AMAP_COL9_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN, + CFG_AMAP_COL8 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8, + CFG_AMAP_COL8_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN, + CFG_AMAP_COL7 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7, + CFG_AMAP_COL7_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN, + CFG_AMAP_COL6 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6, + CFG_AMAP_COL6_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN, + CFG_AMAP_COL5 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5, + CFG_AMAP_COL5_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN, + CFG_AMAP_COL4 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4, + CFG_AMAP_COL4_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN, + CFG_AMAP_COL3 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3, + CFG_AMAP_COL3_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN, + CFG_AMAP_COL2 = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2, + CFG_AMAP_COL2_LEN = EXPLR_MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN, + + LFSR_MASK = EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0, + LFSR_MASK_LEN = EXPLR_MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN, + + CFG_DATA_ROT_SEED1 = EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED, + CFG_DATA_ROT_SEED1_LEN = EXPLR_MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN, + CFG_DATA_ROT = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT, + CFG_DATA_ROT_LEN = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN, + CFG_DATA_ROT_SEED2 = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED, + CFG_DATA_ROT_SEED2_LEN = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN, + CFG_DATA_SEED_MODE = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE, + CFG_DATA_SEED_MODE_LEN = EXPLR_MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN, + + CFG_TRAP_CE_ENABLE = EXPLR_RDF_MCBCM_MCBIST_TRAP_CE_ENABLE, + CFG_TRAP_UE_ENABLE = EXPLR_RDF_MCBCM_MCBIST_TRAP_UE_ENABLE, + CFG_TRAP_MPE_ENABLE = EXPLR_RDF_MCBCM_MCBIST_TRAP_MPE_ENABLE, + + CFG_DGEN_RNDD_SEED0 = EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0, + CFG_DGEN_RNDD_SEED0_LEN = EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN, + CFG_DGEN_RNDD_SEED1 = EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1, + CFG_DGEN_RNDD_SEED1_LEN = EXPLR_MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN, + CFG_DGEN_RNDD_SEED2 = EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2, + CFG_DGEN_RNDD_SEED2_LEN = EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN, + CFG_DGEN_RNDD_DATA_MAPPING = EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING, + CFG_DGEN_RNDD_DATA_MAPPING_LEN = EXPLR_MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN, + + // THRESHOLD control bits + MBSTRQ_CFG_THRESH_MAG_NCE_INT = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT, + MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN, + MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT, + MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN, + MBSTRQ_CFG_THRESH_MAG_NCE_HARD = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD, + MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN, + MBSTRQ_CFG_THRESH_MAG_RCE = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE, + MBSTRQ_CFG_THRESH_MAG_RCE_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN, + MBSTRQ_CFG_THRESH_MAG_ICE = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE, + MBSTRQ_CFG_THRESH_MAG_ICE_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_INT = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT, + MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT, + MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_HARD = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD, + MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = EXPLR_MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN, + MBSTRQ_CFG_PAUSE_ON_SCE = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE, + // NO MBSTRQ_CFG_PAUSE_ON_MCE + // MBSTRQ_CFG_PAUSE_ON_MCE + MBSTRQ_CFG_PAUSE_ON_UE = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_UE, + MBSTRQ_CFG_PAUSE_ON_SUE = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE, + MBSTRQ_CFG_PAUSE_ON_AUE = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE, + MBSTRQ_CFG_PAUSE_ON_RCD = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD, + MBSTRQ_CFG_SYMBOL_COUNTER_MODE = EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE, + MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = EXPLR_MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN, + MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_PAUSE_MCB_ERROR = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR, + MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = EXPLR_MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL, + MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = EXPLR_MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE, + + // Bit mapping for MCBIST error log control data + ERROR_LOG_SUBTEST = 0, + ERROR_LOG_SUBTEST_LEN = 5, + ERROR_LOG_SUBCMD = 5, + ERROR_LOG_SUBCMD_LEN = 2, + ERROR_LOG_ADDR_DIMM = 7, + ERROR_LOG_ADDR_MRANK = 8, + ERROR_LOG_ADDR_MRANK_LEN = 2, + ERROR_LOG_ADDR_SRANK = 10, + ERROR_LOG_ADDR_SRANK_LEN = 3, + ERROR_LOG_ADDR_BANK_GROUP = 13, + ERROR_LOG_ADDR_BANK_GROUP_LEN = 2, + ERROR_LOG_ADDR_BANK = 15, + ERROR_LOG_ADDR_BANK_LEN = 3, + ERROR_LOG_ADDR_ROW = 18, + ERROR_LOG_ADDR_ROW_LEN = 18, + ERROR_LOG_ADDR_COLUMN = 36, + ERROR_LOG_ADDR_COLUMN_LEN = 8, + ERROR_LOG_BEAT = 44, + ERROR_LOG_BEAT_LEN = 2, + ERROR_LOG_TYPE = 46, + ERROR_LOG_TYPE_LEN = 2, + + //MCBIST FIR mask + MCB_PROGRAM_COMPLETE = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE, + MCB_WAT_DEBUG_ATTN = EXPLR_MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN, + MCB_DATA_ERROR = EXPLR_MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR, + + //XLT address valid offset + XLT0_SLOT1_D_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID, + XLT0_SLOT0_M1_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_M1_VALID, + XLT0_SLOT0_M0_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_M0_VALID, + XLT0_SLOT0_S2_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_S2_VALID, + XLT0_SLOT0_S1_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_S1_VALID, + XLT0_SLOT0_S0_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_S0_VALID, + XLT0_SLOT0_ROW17_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW17_VALID, + XLT0_SLOT0_ROW16_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW16_VALID, + XLT0_SLOT0_ROW15_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_ROW15_VALID, + + }; + + // MCBIST error log related registers + static constexpr uint64_t RD_BUF_CTL_REG = EXPLR_RDF_AACR; + static constexpr uint64_t RD_BUF_DATA_REG = EXPLR_RDF_AADR; + static constexpr uint64_t RD_BUF_ECC_REG = EXPLR_RDF_AAER; + + enum + { + // Register field constants + RB_ADDRESS = EXPLR_RDF_AACR_ADDRESS, + RB_ADDRESS_LEN = EXPLR_RDF_AACR_ADDRESS_LEN, + RB_AUTOINC = EXPLR_RDF_AACR_AUTOINC, + + // Other constants + NUM_COMPARE_LOG_ENTRIES = 64, + }; +}; + + +/// +/// @class mcbistTraits +/// @brief a collection of traits associated with the Explorer MEM_PORT +/// +template<> +class mcbistTraits< mss::mc_type::EXPLORER, fapi2::TARGET_TYPE_MEM_PORT> +{ + public: + // MCBIST error log related registers + static constexpr uint64_t ERROR_LOG_PTR_REG = EXPLR_RDF_ELPR; + static constexpr uint64_t RMW_WRT_BUF_CTL_REG = EXPLR_WDF_AACR; + static constexpr uint64_t RMW_WRT_BUF_DATA_REG = EXPLR_WDF_AADR; + static constexpr uint64_t RMW_WRT_BUF_ECC_REG = EXPLR_WDF_AAER; + + static constexpr uint64_t XLTATE0 = EXPLR_MCBIST_MBXLT0Q; + static constexpr uint64_t XLTATE1 = EXPLR_MCBIST_MBXLT1; + static constexpr uint64_t XLTATE2 = EXPLR_MCBIST_MBXLT2; + + // Maintenance data location within the array + static constexpr uint64_t MAINT_DATA_INDEX_START = 0b000000000; + static constexpr uint64_t MAINT_DATA_INDEX_END = 0b000001000; + + enum + { + // Register field constants + ERROR_LOG_PTR = EXPLR_RDF_ELPR_LOG_POINTER, + ERROR_LOG_PTR_LEN = EXPLR_RDF_ELPR_LOG_POINTER_LEN, + ERROR_LOG_FULL = EXPLR_RDF_ELPR_LOG_FULL, + RMW_WRT_BUFFER_SEL = EXPLR_WDF_AACR_BUFFER, + RMW_WRT_ADDRESS = EXPLR_WDF_AACR_ADDRESS, + RMW_WRT_ADDRESS_LEN = EXPLR_WDF_AACR_ADDRESS_LEN, + RMW_WRT_AUTOINC = EXPLR_WDF_AACR_AUTOINC, + RMW_WRT_ECCGEN = EXPLR_WDF_AACR_ECCGEN, + + XLTATE_SLOT0_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT0_VALID, + XLTATE_SLOT1_VALID = EXPLR_MCBIST_MBXLT0Q_SLOT1_VALID, + + // Constants used for field settings + SELECT_RMW_BUFFER = 0, + SELECT_WRT_BUFFER = 1, + + // Other constants + NUM_COMPARE_LOG_ENTRIES = 64, + // In compare mode, there is one "info" entry per 4 data (log) entries + // so compare mode only uses 16 info entries total in the rmw array + NUM_COMPARE_DATA_PER_INFO_LOG = 4, + NUM_COMPARE_INFO_ENTRIES = 16, + }; +}; + +}// mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C index 540de3b0f..0c879abe9 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,168 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_memdiags.C +/// @brief Run and manage the MEMDIAGS engine +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> + +#include <lib/shared/exp_defaults.H> +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> + +#include <lib/dimm/exp_rank.H> +#include <lib/mcbist/exp_memdiags.H> +#include <lib/mcbist/exp_mcbist.H> +#include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/utils/poll.H> + + +namespace mss +{ + +namespace memdiags +{ + +/// +/// @brief memdiags multi-port init internal. +/// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes +/// in subclassed constructors more easily. +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +template<> +fapi2::ReturnCode operation<mss::mc_type::EXPLORER>::multi_port_init_internal() +{ + return single_port_init(); +} + +/// +/// @brief Set up memory controller specific settings for pre-maint mode read +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::EXPLORER specialization +/// +template<> +fapi2::ReturnCode pre_maint_read_settings<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target ) +{ + using TT = mss::portTraits<mss::mc_type::EXPLORER>; + fapi2::buffer<uint64_t> l_data; + + // Set up Explorer specific settings + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + + l_data.setBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_UE>(); + l_data.setBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_MPE>(); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Set up memory controller specific settings for pre-scrub +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::EXPLORER specialization +/// +template<> +fapi2::ReturnCode pre_scrub_settings<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target ) +{ + using TT = mss::portTraits<mss::mc_type::EXPLORER>; + fapi2::buffer<uint64_t> l_data; + + // Set up Explorer specific settings + FAPI_TRY( mss::getScom(i_target, TT::ECC_REG, l_data) ); + + l_data.clearBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_UE>(); + l_data.clearBit<TT::RECR_MBSECCQ_MAINT_NO_RETRY_MPE>(); + + FAPI_TRY( mss::putScom(i_target, TT::ECC_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +} // namespace memdiags + +namespace exp +{ + +namespace memdiags +{ + +/// +/// @brief Process the result from the mcbist sf_read subtest after memdiags +/// +/// @param[in] i_target OCMB target for traces +/// @param[in] l_fail_behavior_attr +/// @param[in,out] io_rc ReturnCode from sf_read +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode process_subtest_result(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t l_fail_behavior_attr, + fapi2::ReturnCode& io_rc) +{ + // Check RC + if ((l_fail_behavior_attr == fapi2::ENUM_ATTR_MSS_POST_MEMDIAGS_READ_SUBTEST_FAIL_BEHAVIOR_TRACE) + && (io_rc != fapi2::FAPI2_RC_SUCCESS)) + { + // Trace + Bad RC: Log as recovered, return success, set io_rc back to success + FAPI_ERR("%s Error code 0x%08lx from post-memdiags mcbist read subtest", mss::c_str(i_target), uint32_t(io_rc)); + fapi2::logError(io_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED); + + io_rc = fapi2::FAPI2_RC_SUCCESS; + + return fapi2::FAPI2_RC_SUCCESS; + } + + // Else, we will just try the RC as-is + FAPI_TRY(io_rc, "%s Error from post-memdiags mcbist read subtest", mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform a read only mcbist subtest at the end of memdiags +/// +/// @param[in] i_target OCMB Chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode perform_read_only_subtest(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + uint8_t l_fail_behavior = 0; + + auto l_stop_conditions = mss::mcbist::stop_conditions<mss::mc_type::EXPLORER>(); + + // Pause on unrecoverable error + l_stop_conditions.set_pause_on_ue(mss::ON); + + // sf_read will run, poll for completion and return result ReturnCode + l_rc = mss::memdiags::sf_read<mss::mc_type::EXPLORER>(i_target, l_stop_conditions); + + // Get fail behavior attr and process the result + FAPI_TRY(mss::attr::get_post_memdiags_read_subtest(i_target, l_fail_behavior)); + FAPI_TRY(process_subtest_result(i_target, l_fail_behavior, l_rc)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +} // memdiags +} // exp + +} // namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.H index 496b97f80..a53b7c312 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_memdiags.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,58 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_memdiags.H +/// @brief API for memory diagnostics +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP +// + +#ifndef _MSS_EXP_MEMDIAGS_H_ +#define _MSS_EXP_MEMDIAGS_H_ + +#include <fapi2.H> + +#include <lib/shared/exp_consts.H> +#include <lib/mcbist/exp_mcbist.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_memdiags.H> + +// This file is still necessary to put traits and generic code together + +namespace mss +{ +namespace exp +{ +namespace memdiags +{ + +/// +/// @brief Process the result from the mcbist sf_read subtest after memdiags +/// +/// @param[in] i_target OCMB target for traces +/// @param[in] l_fail_behavior_attr +/// @param[in, out] i_rc ReturnCode from sf_read +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode process_subtest_result(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t l_fail_behavior_attr, + fapi2::ReturnCode& io_rc); + +/// +/// @brief Perform a read only mcbist subtest at the end of memdiags +/// +/// @param[in] i_target OCMB Chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode perform_read_only_subtest(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +} // memdiags +} // exp +} // mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_settings.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_settings.H index ed1703ecb..dc1c42c4b 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_settings.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/exp_settings.H @@ -22,3 +22,26 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file exp_settings.H +/// @brief MCBIST settings, like stop conditions, thresholds, etc +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_MCBIST_EXP_SETTINGS_H_ +#define _MSS_MCBIST_EXP_SETTINGS_H_ + +#include <fapi2.H> + +#include <lib/shared/exp_consts.H> +#include <lib/ecc/ecc_traits_explorer.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_traits.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_settings.H> + +// This file is still necessary to put traits and generic code together + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.C deleted file mode 100644 index e6284b618..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.C +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.H deleted file mode 100644 index 87c62e802..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist_traits.H deleted file mode 100644 index 446ab46e9..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist_traits.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/mcbist_traits.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.C deleted file mode 100644 index b85c12fc4..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.C +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.H deleted file mode 100644 index 999a83ced..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/memdiags.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/settings.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/settings.H deleted file mode 100644 index 1bdb23803..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/settings.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/mcbist/settings.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H index c6a6793aa..8d34537e4 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/crc32.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,73 +38,42 @@ #include <stdint.h> #include <vector> -// CRC32 lookup table can be found online via multiple websites +// CRC32 lookup table to match the table used in Microchip firmware +// Note that this table is known as CRC32_BZIP2 in some texts static const uint32_t crc32_lookup_table[] = { - 0x00000000ul, 0x77073096ul, 0xEE0E612Cul, 0x990951BAul, - 0x076DC419ul, 0x706AF48Ful, 0xE963A535ul, 0x9E6495A3ul, - 0x0EDB8832ul, 0x79DCB8A4ul, 0xE0D5E91Eul, 0x97D2D988ul, - 0x09B64C2Bul, 0x7EB17CBDul, 0xE7B82D07ul, 0x90BF1D91ul, - 0x1DB71064ul, 0x6AB020F2ul, 0xF3B97148ul, 0x84BE41DEul, - 0x1ADAD47Dul, 0x6DDDE4EBul, 0xF4D4B551ul, 0x83D385C7ul, - 0x136C9856ul, 0x646BA8C0ul, 0xFD62F97Aul, 0x8A65C9ECul, - 0x14015C4Ful, 0x63066CD9ul, 0xFA0F3D63ul, 0x8D080DF5ul, - 0x3B6E20C8ul, 0x4C69105Eul, 0xD56041E4ul, 0xA2677172ul, - 0x3C03E4D1ul, 0x4B04D447ul, 0xD20D85FDul, 0xA50AB56Bul, - 0x35B5A8FAul, 0x42B2986Cul, 0xDBBBC9D6ul, 0xACBCF940ul, - 0x32D86CE3ul, 0x45DF5C75ul, 0xDCD60DCFul, 0xABD13D59ul, - 0x26D930ACul, 0x51DE003Aul, 0xC8D75180ul, 0xBFD06116ul, - 0x21B4F4B5ul, 0x56B3C423ul, 0xCFBA9599ul, 0xB8BDA50Ful, - 0x2802B89Eul, 0x5F058808ul, 0xC60CD9B2ul, 0xB10BE924ul, - 0x2F6F7C87ul, 0x58684C11ul, 0xC1611DABul, 0xB6662D3Dul, - 0x76DC4190ul, 0x01DB7106ul, 0x98D220BCul, 0xEFD5102Aul, - 0x71B18589ul, 0x06B6B51Ful, 0x9FBFE4A5ul, 0xE8B8D433ul, - 0x7807C9A2ul, 0x0F00F934ul, 0x9609A88Eul, 0xE10E9818ul, - 0x7F6A0DBBul, 0x086D3D2Dul, 0x91646C97ul, 0xE6635C01ul, - 0x6B6B51F4ul, 0x1C6C6162ul, 0x856530D8ul, 0xF262004Eul, - 0x6C0695EDul, 0x1B01A57Bul, 0x8208F4C1ul, 0xF50FC457ul, - 0x65B0D9C6ul, 0x12B7E950ul, 0x8BBEB8EAul, 0xFCB9887Cul, - 0x62DD1DDFul, 0x15DA2D49ul, 0x8CD37CF3ul, 0xFBD44C65ul, - 0x4DB26158ul, 0x3AB551CEul, 0xA3BC0074ul, 0xD4BB30E2ul, - 0x4ADFA541ul, 0x3DD895D7ul, 0xA4D1C46Dul, 0xD3D6F4FBul, - 0x4369E96Aul, 0x346ED9FCul, 0xAD678846ul, 0xDA60B8D0ul, - 0x44042D73ul, 0x33031DE5ul, 0xAA0A4C5Ful, 0xDD0D7CC9ul, - 0x5005713Cul, 0x270241AAul, 0xBE0B1010ul, 0xC90C2086ul, - 0x5768B525ul, 0x206F85B3ul, 0xB966D409ul, 0xCE61E49Ful, - 0x5EDEF90Eul, 0x29D9C998ul, 0xB0D09822ul, 0xC7D7A8B4ul, - 0x59B33D17ul, 0x2EB40D81ul, 0xB7BD5C3Bul, 0xC0BA6CADul, - 0xEDB88320ul, 0x9ABFB3B6ul, 0x03B6E20Cul, 0x74B1D29Aul, - 0xEAD54739ul, 0x9DD277AFul, 0x04DB2615ul, 0x73DC1683ul, - 0xE3630B12ul, 0x94643B84ul, 0x0D6D6A3Eul, 0x7A6A5AA8ul, - 0xE40ECF0Bul, 0x9309FF9Dul, 0x0A00AE27ul, 0x7D079EB1ul, - 0xF00F9344ul, 0x8708A3D2ul, 0x1E01F268ul, 0x6906C2FEul, - 0xF762575Dul, 0x806567CBul, 0x196C3671ul, 0x6E6B06E7ul, - 0xFED41B76ul, 0x89D32BE0ul, 0x10DA7A5Aul, 0x67DD4ACCul, - 0xF9B9DF6Ful, 0x8EBEEFF9ul, 0x17B7BE43ul, 0x60B08ED5ul, - 0xD6D6A3E8ul, 0xA1D1937Eul, 0x38D8C2C4ul, 0x4FDFF252ul, - 0xD1BB67F1ul, 0xA6BC5767ul, 0x3FB506DDul, 0x48B2364Bul, - 0xD80D2BDAul, 0xAF0A1B4Cul, 0x36034AF6ul, 0x41047A60ul, - 0xDF60EFC3ul, 0xA867DF55ul, 0x316E8EEFul, 0x4669BE79ul, - 0xCB61B38Cul, 0xBC66831Aul, 0x256FD2A0ul, 0x5268E236ul, - 0xCC0C7795ul, 0xBB0B4703ul, 0x220216B9ul, 0x5505262Ful, - 0xC5BA3BBEul, 0xB2BD0B28ul, 0x2BB45A92ul, 0x5CB36A04ul, - 0xC2D7FFA7ul, 0xB5D0CF31ul, 0x2CD99E8Bul, 0x5BDEAE1Dul, - 0x9B64C2B0ul, 0xEC63F226ul, 0x756AA39Cul, 0x026D930Aul, - 0x9C0906A9ul, 0xEB0E363Ful, 0x72076785ul, 0x05005713ul, - 0x95BF4A82ul, 0xE2B87A14ul, 0x7BB12BAEul, 0x0CB61B38ul, - 0x92D28E9Bul, 0xE5D5BE0Dul, 0x7CDCEFB7ul, 0x0BDBDF21ul, - 0x86D3D2D4ul, 0xF1D4E242ul, 0x68DDB3F8ul, 0x1FDA836Eul, - 0x81BE16CDul, 0xF6B9265Bul, 0x6FB077E1ul, 0x18B74777ul, - 0x88085AE6ul, 0xFF0F6A70ul, 0x66063BCAul, 0x11010B5Cul, - 0x8F659EFFul, 0xF862AE69ul, 0x616BFFD3ul, 0x166CCF45ul, - 0xA00AE278ul, 0xD70DD2EEul, 0x4E048354ul, 0x3903B3C2ul, - 0xA7672661ul, 0xD06016F7ul, 0x4969474Dul, 0x3E6E77DBul, - 0xAED16A4Aul, 0xD9D65ADCul, 0x40DF0B66ul, 0x37D83BF0ul, - 0xA9BCAE53ul, 0xDEBB9EC5ul, 0x47B2CF7Ful, 0x30B5FFE9ul, - 0xBDBDF21Cul, 0xCABAC28Aul, 0x53B39330ul, 0x24B4A3A6ul, - 0xBAD03605ul, 0xCDD70693ul, 0x54DE5729ul, 0x23D967BFul, - 0xB3667A2Eul, 0xC4614AB8ul, 0x5D681B02ul, 0x2A6F2B94ul, - 0xB40BBE37ul, 0xC30C8EA1ul, 0x5A05DF1Bul, 0x2D02EF8Dul + 0x0, 0x4c11db7, 0x9823b6e, 0xd4326d9, 0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005, + 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, + 0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75, + 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd, + 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, + 0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d, + 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95, + 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, + 0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072, + 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13, 0x54bf6a4, 0x808d07d, 0xcc9cdca, + 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, + 0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba, + 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692, + 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, + 0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2, + 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a, + 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, + 0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53, + 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b, + 0x315d626, 0x7d4cb91, 0xa97ed48, 0xe56f0ff, 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, + 0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b, + 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3, + 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, + 0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3, + 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c, + 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, + 0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35, 0x65e2082, 0xb1d065b, 0xfdc1bec, + 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654, + 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, + 0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4, + 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c, + 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4, }; /// @@ -123,8 +92,8 @@ inline uint32_t crc32_gen(const std::vector<uint8_t>& i_data, const uint64_t i_l for (uint64_t i = 0; i < i_data.size() && i < i_len; ++i) { const uint8_t l_data = i_data[i]; - const uint32_t l_tmp = l_crc ^ static_cast<uint32_t>(l_data); - l_crc = (l_crc >> 8) ^ crc32_lookup_table[ l_tmp & 0xFF ]; + const uint32_t l_tmp = (l_crc >> 24) ^ static_cast<uint32_t>(l_data); + l_crc = (l_crc << 8) ^ crc32_lookup_table[ l_tmp & 0xFF ]; } return l_crc ^ 0xFFFFFFFFul; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C index e58f134cb..f8133bafb 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,10 +33,14 @@ // *HWP Level: 3 // *HWP Consumed by: Memory +#include <generic/memory/lib/utils/find.H> #include <lib/omi/exp_omi_utils.H> #include <lib/shared/exp_consts.H> #include <lib/i2c/exp_i2c_fields.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> #include <mss_explorer_attribute_getters.H> +#include <generic/memory/lib/mss_generic_system_attribute_getters.H> +#include <lib/shared/exp_consts.H> namespace mss { @@ -44,6 +48,47 @@ namespace exp { namespace omi { + +/// +/// @brief Set the OMI_DL0 configuration register for a given mode +/// +/// @param[in] i_target OCMB target +/// @param[in] i_train_mode mode to use +/// @param[in] i_dl_x4_backoff_en backoff enable bit +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note Algorithm from p9a_omi_train.C +/// +fapi2::ReturnCode setup_omi_dl0_config0( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t i_train_mode, + const uint8_t i_dl_x4_backoff_en) +{ + fapi2::buffer<uint64_t> l_config0; + + // Get the "reset" values so we can just overwrite with the changes + FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_CONFIG0, l_config0), + "Error reading EXPLR_DLX_DL0_CONFIG0 on %s", mss::c_str(i_target)); + + // CFG_DL0_HALF_WIDTH_BACKOFF_ENABLE: dl0 x4 backoff enabled + l_config0.writeBit<EXPLR_DLX_DL0_CONFIG0_CFG_HALF_WIDTH_BACKOFF_ENABLE>(i_dl_x4_backoff_en); + + // CFG_DL0_TRAIN_MODE: dl0 train mode + l_config0.insertFromRight<EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE, + EXPLR_DLX_DL0_CONFIG0_CFG_TRAIN_MODE_LEN>(i_train_mode); + + l_config0.writeBit<EXPLR_DLX_DL0_CONFIG0_CFG_PWRMGT_ENABLE>(0); + + FAPI_DBG("Writing 0x%16llx to EXPLR_DLX_DL0_CONFIG0 (0x%16llx) of %s", + l_config0, EXPLR_DLX_DL0_CONFIG0, mss::c_str(i_target)); + + // All other bits will be left at their default values + FAPI_TRY( fapi2::putScom(i_target, EXPLR_DLX_DL0_CONFIG0, l_config0), + "Error writing EXPLR_DLX_DL0_CONFIG0 on %s", mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + namespace train { @@ -61,11 +106,16 @@ fapi2::ReturnCode setup_fw_boot_config( const fapi2::Target<fapi2::TARGET_TYPE_O uint8_t l_loopback_test = 0; uint8_t l_transport_layer = 0; uint8_t l_dl_layer_boot_mode = 0; - uint8_t l_boot_mode = 0; + uint8_t l_dfe_disable = 0; uint8_t l_lane_mode = 0; - uint8_t l_serdes_freq = 0; + uint8_t l_adaptation_mode = 0; + uint32_t l_omi_freq = 0; + + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); // Read the EXP_FW_BOOT_CONFIG from the attributes + FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_adaptation_mode(i_target, l_adaptation_mode)); + FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_fw_mode(i_target, l_fw_mode)); FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_opencapi_loopback_test(i_target, l_loopback_test)); @@ -74,24 +124,51 @@ fapi2::ReturnCode setup_fw_boot_config( const fapi2::Target<fapi2::TARGET_TYPE_O FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_dl_layer_boot_mode(i_target, l_dl_layer_boot_mode)); - FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_boot_mode(i_target, l_boot_mode)); + FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_dfe_disable(i_target, l_dfe_disable)); FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_lane_mode(i_target, l_lane_mode)); - FAPI_TRY(mss::attr::get_ocmb_exp_boot_config_serdes_frequency(i_target, l_serdes_freq)); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_OMI_MHZ, l_proc, l_omi_freq) ); // Clears o_data, just in case o_data.clear(); o_data.assign(mss::exp::i2c::FW_BOOT_CONFIG_BYTE_LEN, 0); - FAPI_TRY(mss::exp::i2c::boot_cfg::set_serdes_freq( i_target, o_data, l_serdes_freq )); + FAPI_TRY(mss::exp::i2c::boot_cfg::set_serdes_freq( i_target, o_data, l_omi_freq )); FAPI_TRY(mss::exp::i2c::boot_cfg::set_lane_mode( i_target, o_data, l_lane_mode )); - FAPI_TRY(mss::exp::i2c::boot_cfg::set_boot_mode( i_target, o_data, l_boot_mode )); + FAPI_TRY(mss::exp::i2c::boot_cfg::set_dfe_disable( i_target, o_data, l_dfe_disable )); FAPI_TRY(mss::exp::i2c::boot_cfg::set_dl_layer_boot_mode( i_target, o_data, l_dl_layer_boot_mode )); FAPI_TRY(mss::exp::i2c::boot_cfg::set_transport_layer( i_target, o_data, l_transport_layer )); FAPI_TRY(mss::exp::i2c::boot_cfg::set_loopback_test( i_target, o_data, l_loopback_test )); FAPI_TRY(mss::exp::i2c::boot_cfg::set_fw_mode( i_target, o_data, l_fw_mode )); + FAPI_TRY(mss::exp::i2c::boot_cfg::set_adaptation_mode( i_target, o_data, l_adaptation_mode )); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Check the OMI train status on the OCMB chip +/// +/// @param[in] i_target OCMB chil +/// @param[out] o_state_machine_state training state mahcine +/// @param[out] o_omi_training_status training status +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode omi_train_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint8_t& o_state_machine_state, + fapi2::buffer<uint64_t>& o_omi_training_status) +{ + fapi2::buffer<uint64_t> l_omi_status; + + // Check OMI training status + FAPI_TRY(fapi2::getScom(i_target, EXPLR_DLX_DL0_STATUS, l_omi_status)); + + o_omi_training_status = l_omi_status; + o_state_machine_state = 0; + l_omi_status.extractToRight<EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE, + EXPLR_DLX_DL0_STATUS_STS_TRAINING_STATE_MACHINE_LEN>(o_state_machine_state); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H index 1faf02014..5022271ee 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/omi/exp_omi_utils.H @@ -103,6 +103,27 @@ inline bool get_enterprise_config( const fapi2::buffer<uint64_t>& i_data ) return i_data.getBit<EXPLR_MMIO_MENTERP_CFG_ENTERPRISE_MODE>(); } + +/// +/// @brief Get edpl enable bit +/// @param[in] i_data the register data +/// @return The register's EDPL_ENA bit +/// +inline bool get_edpl_enable_bit( const fapi2::buffer<uint64_t>& i_data ) +{ + return i_data.getBit<EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_ENA>(); +} + +/// +/// @brief Set edpl enable bit +/// @param[in,out] io_data the register data +/// @param[in] i_enable The register's EDPL_ENA bit +/// +inline void set_edpl_enable_bit( fapi2::buffer<uint64_t>& io_data, const bool i_enable ) +{ + io_data.writeBit<EXPLR_DLX_DL0_CONFIG1_CFG_EDPL_ENA>(i_enable); +} + /// /// @brief Checks if the enterprise config bit is in the correct mode /// @param[in] i_target target on which we are operating - for logging @@ -115,6 +136,7 @@ inline fapi2::ReturnCode check_enterprise_mode( const fapi2::Target<fapi2::TARGE fapi2::buffer<uint64_t>& i_data ) { const bool l_actual = mss::exp::omi::get_enterprise_config(i_data); + FAPI_ASSERT(l_actual == i_is_enterprise, fapi2::MSS_EXP_ENTERPRISE_SETUP_ERROR() .set_EXPECTED(i_is_enterprise) @@ -124,6 +146,8 @@ inline fapi2::ReturnCode check_enterprise_mode( const fapi2::Target<fapi2::TARGE "%s failed to setup enterprise mode properly expected: %u actual: %u register data 0x%016lx", mss::c_str(i_target), i_is_enterprise, l_actual, i_data); + return fapi2::FAPI2_RC_SUCCESS; + fapi_try_exit: return fapi2::current_err; } @@ -157,6 +181,44 @@ inline fapi2::ReturnCode write_enterprise_config( const fapi2::Target<fapi2::TAR return fapi2::putScom(i_target, EXPLR_MMIO_MENTERP, i_data); } +/// +/// @brief Reads the EXPLR_DLX_DL0_CONFIG1 register using I2C +/// @param[in] i_target the OCMB target on which to operate +/// @param[out] o_data the register contents +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// +inline fapi2::ReturnCode read_dlx_config1( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + fapi2::buffer<uint64_t>& o_data ) +{ + return fapi2::getScom(i_target, EXPLR_DLX_DL0_CONFIG1, o_data); +} + +/// +/// @brief Writes the EXPLR_DLX_DL0_CONFIG1 register using I2C +/// @param[in] i_target the OCMB target on which to operate +/// @param[in] i_data the register contents +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// +inline fapi2::ReturnCode write_dlx_config1( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const fapi2::buffer<uint64_t>& i_data ) +{ + return fapi2::putScom(i_target, EXPLR_DLX_DL0_CONFIG1, i_data); +} + +/// +/// @brief Set the OMI_DL0 configuration register for a given mode +/// +/// @param[in] i_target OCMB target +/// @param[in] i_train_mode mode to use +/// @param[in] i_dl_x4_backoff_en backoff enable bit +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note Algorithm from p9a_omi_train.C +/// +fapi2::ReturnCode setup_omi_dl0_config0( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint8_t i_train_mode, + const uint8_t i_dl_x4_backoff_en); + namespace train { @@ -169,6 +231,18 @@ namespace train fapi2::ReturnCode setup_fw_boot_config( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, std::vector<uint8_t>& o_data ); +/// +/// @brief Check the OMI train status on the OCMB chip +/// +/// @param[in] i_target OCMB chil +/// @param[out] o_state_machine_state training state mahcine +/// @param[out] o_omi_training_status training status +/// @return fapi2::ReturnCode +/// +fapi2::ReturnCode omi_train_status(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + uint8_t& o_state_machine_state, + fapi2::buffer<uint64_t>& o_omi_training_status); + } // ns train } // ns omi diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C new file mode 100644 index 000000000..f7fbad41a --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C @@ -0,0 +1,239 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_train_display.C +/// @brief Procedures used to display the training response information +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/index.H> +#include <generic/memory/lib/utils/c_str.H> +#include <exp_data_structs.H> +#include <lib/phy/exp_train_display.H> + +namespace mss +{ +namespace exp +{ +namespace train +{ +/// +/// @brief Displays training information +/// @param[in] i_target the OCMB target +/// @param[in] i_lane the lane for the training information +/// @param[in] i_data the training data for this lane +/// +void display_lane_results(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_lane, + const uint16_t i_data) +{ + // Extracts the per-rank information + fapi2::buffer<uint16_t> l_data(i_data); + uint8_t l_rank0 = 0; + uint8_t l_rank1 = 0; + uint8_t l_rank2 = 0; + uint8_t l_rank3 = 0; + + l_data.extractToRight<0, BITS_PER_NIBBLE>(l_rank3) + .extractToRight<BITS_PER_NIBBLE, BITS_PER_NIBBLE>(l_rank2) + .extractToRight<BITS_PER_NIBBLE * 2, BITS_PER_NIBBLE>(l_rank1) + .extractToRight<BITS_PER_NIBBLE * 3, BITS_PER_NIBBLE>(l_rank0); + + constexpr uint16_t CLEAN = 0; + + // If we passed, display the information as only as MFG - we don't want to clutter the screen with too much information + if(CLEAN == i_data) + { + FAPI_MFG("%s lane: %u PASSING R0:%u R1:%u R2:%u R3:%u", + mss::c_str(i_target), i_lane, + l_rank0, l_rank1, l_rank2, l_rank3); + } + + // If we failed, display the information as INF + else + { + FAPI_INF("%s lane: %u FAILING R0:%u R1:%u R2:%u R3:%u", + mss::c_str(i_target), i_lane, + l_rank0, l_rank1, l_rank2, l_rank3); + } +} + +/// +/// @brief Display train_2d_read_eye_msdg_t response struct +/// +/// @param[in] i_target OCMB target +/// @param[in] i_training_info training info struct +/// +void display_train_2d_read_eye(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg_t& i_training_info) +{ + FAPI_MFG("%s %s (EYE MIN/MAX):", mss::c_str(i_target), "VrefDAC0"); + + for (uint8_t l_rank = 0; l_rank < TRAINING_RESPONSE_NUM_RANKS; ++l_rank) + { + for (uint8_t l_dbyte = 0; l_dbyte < DBYTE_N_SIZE; ++l_dbyte) + { + for (uint8_t l_bit = 0; l_bit < BIT_N_SIZE; ++l_bit) + { + for (uint8_t l_eye_index = 0; l_eye_index < EYE_MIN_MAX_SIZE; ++l_eye_index) + { + const auto l_eye_min = i_training_info.read_2d_eye_resp.VrefDAC0[l_rank][l_dbyte][l_bit].eye_min[l_eye_index]; + const auto l_eye_max = i_training_info.read_2d_eye_resp.VrefDAC0[l_rank][l_dbyte][l_bit].eye_max[l_eye_index]; + + FAPI_MFG("%s %s RANK %u, DBYTE %u BIT %u EYE INDEX %u -- MIN: %u MAX: %u", + mss::c_str(i_target), "VrefDAC0", l_rank, l_dbyte, l_bit, l_eye_index, l_eye_min, l_eye_max); + } + } + } + } + + FAPI_MFG("%s %s_Center:", mss::c_str(i_target), "VrefDAC0"); + + for (uint8_t l_dbyte = 0; l_dbyte < DBYTE_N_SIZE; ++l_dbyte) + { + for (uint8_t l_bit = 0; l_bit < BIT_N_SIZE; ++l_bit) + { + const auto l_vref_dac0_center = i_training_info.read_2d_eye_resp.VrefDAC0_Center[l_dbyte][l_bit]; + FAPI_MFG("%s %s DBYTE %u, BIT %u: %u", mss::c_str(i_target), "VrefDAC0_Center", l_dbyte, l_bit, l_vref_dac0_center); + } + } + + FAPI_MFG("%s %s_Center:", mss::c_str(i_target), "RxClkDly"); + + for (uint8_t l_rank = 0; l_rank < TRAINING_RESPONSE_NUM_RANKS; ++l_rank) + { + for (uint8_t l_nibble = 0; l_nibble < NIBBLE_N_SIZE; ++l_nibble) + { + const auto l_rxclkdly_center = i_training_info.read_2d_eye_resp.RxClkDly_Center[l_rank][l_nibble]; + FAPI_MFG("%s %s RANK %u, NIBBLE %u: %u", mss::c_str(i_target), "RxClkDly_Center", l_rank, l_nibble, l_rxclkdly_center); + } + } +} + +/// +/// @brief Display train_2d_write_eye_msdg_t response struct +/// +/// @param[in] i_target OCMB target +/// @param[in] i_training_info training info struct +/// +void display_train_2d_write_eye(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_2_msdg_t& i_training_info) +{ + FAPI_MFG("%s %s (EYE MIN/MAX):", mss::c_str(i_target), "VrefDQ"); + + for (uint8_t l_rank = 0; l_rank < TRAINING_RESPONSE_NUM_RANKS; ++l_rank) + { + for (uint8_t l_dbyte = 0; l_dbyte < DBYTE_N_SIZE; ++l_dbyte) + { + for (uint8_t l_bit = 0; l_bit < BIT_N_SIZE; ++l_bit) + { + for (uint8_t l_eye_index = 0; l_eye_index < EYE_MIN_MAX_SIZE; ++l_eye_index) + { + const auto l_eye_min = i_training_info.write_2d_eye_resp.VrefDQ[l_rank][l_dbyte][l_bit].eye_min[l_eye_index]; + const auto l_eye_max = i_training_info.write_2d_eye_resp.VrefDQ[l_rank][l_dbyte][l_bit].eye_max[l_eye_index]; + + FAPI_MFG("%s %s RANK %u, DBYTE %u BIT %u EYE INDEX %u -- MIN: %u MAX: %u", + mss::c_str(i_target), "VrefDQ", l_rank, l_dbyte, l_bit, l_eye_index, l_eye_min, l_eye_max); + } + } + } + } + + FAPI_MFG("%s %s_Center:", mss::c_str(i_target), "VrefDQ"); + + for (uint8_t l_rank = 0; l_rank < TRAINING_RESPONSE_NUM_RANKS; ++l_rank) + { + for (uint8_t l_nibble = 0; l_nibble < NIBBLE_N_SIZE; ++l_nibble) + { + const auto l_vrefdq_center = i_training_info.write_2d_eye_resp.VrefDQ_Center[l_rank][l_nibble]; + FAPI_MFG("%s %s RANK %u, NIBBLE %u: %u", mss::c_str(i_target), "VrefDQ_Center", l_rank, l_nibble, l_vrefdq_center); + } + } + + FAPI_MFG("%s %s_Center:", mss::c_str(i_target), "TxDqDly"); + + for (uint8_t l_rank = 0; l_rank < TRAINING_RESPONSE_NUM_RANKS; ++l_rank) + { + for (uint8_t l_dbyte = 0; l_dbyte < DBYTE_N_SIZE; ++l_dbyte) + { + for (uint8_t l_bit = 0; l_bit < BIT_N_SIZE; ++l_bit) + { + const auto l_txdqdly_center = i_training_info.write_2d_eye_resp.TxDqDly_Center[l_rank][l_dbyte][l_bit]; + FAPI_MFG("%s %s RANK %u, DBYTE %u BIT %u: %u", mss::c_str(i_target), "TxDqDly_Center", l_rank, l_dbyte, l_bit, + l_txdqdly_center); + } + } + } +} + +/// +/// @brief Displays all training information +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +template <> +fapi2::ReturnCode display_user_2d_eye_info<user_2d_eye_response_1_msdg_t>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg_t& i_training_info) +{ + FAPI_INF("%s displaying user 2d eye response 1 data version %u", mss::c_str(i_target), i_training_info.version_number) + display_train_2d_read_eye(i_target, i_training_info); + FAPI_TRY(display_normal_info(i_target, i_training_info)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Displays all training information +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +template <> +fapi2::ReturnCode display_user_2d_eye_info<user_2d_eye_response_2_msdg_t>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_2_msdg_t& i_training_info) +{ + FAPI_INF("%s displaying user 2d eye response 2 data version %u", mss::c_str(i_target), i_training_info.version_number) + display_train_2d_write_eye(i_target, i_training_info); + FAPI_TRY(display_normal_info(i_target, i_training_info)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns train +} // ns exp +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.H index f4afb90f7..abd131559 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_display.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,16 @@ #define _EXP_TRAIN_DISPLAY_H_ #include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <generic/memory/lib/utils/index.H> #include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/find.H> #include <exp_data_structs.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> + namespace mss { @@ -49,18 +55,346 @@ namespace exp namespace train { /// -/// @brief Displays all training information +/// @brief Displays training information +/// @param[in] i_target the OCMB target +/// @param[in] i_lane the lane for the training information +/// @param[in] i_data the training data for this lane +/// +void display_lane_results(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_lane, + const uint16_t i_data); + +/// +/// @brief Displays RCW information for a single 8-bit RCW +/// @param[in] i_target the OCMB target +/// @param[in] i_dimm the dimm number associated w/ the RCW +/// @param[in] i_func_space the function space for the RCW +/// @param[in] i_rcw_number RCW number +/// @param[in] i_data data associated with the RCW +/// +inline void display_rcw_8bit(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_dimm, + const uint64_t i_func_space, + const uint64_t i_rcw_number, + const uint8_t i_data) +{ + const uint64_t l_rcw_print_number = i_rcw_number - exp_struct_sizes::RCW_8BIT_CUTOFF; + FAPI_MFG("%s DIMM%u F%uRC%xX: 0x%02x", mss::c_str(i_target), i_dimm, i_func_space, l_rcw_print_number, i_data); +} + +/// +/// @brief Displays RCW information for a single 4-bit RCW +/// @param[in] i_target the OCMB target +/// @param[in] i_dimm the dimm number associated w/ the RCW +/// @param[in] i_func_space the function space for the RCW +/// @param[in] i_rcw_number RCW number +/// @param[in] i_data data associated with the RCW +/// +inline void display_rcw_4bit(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const uint64_t i_dimm, + const uint64_t i_func_space, + const uint64_t i_rcw_number, + const uint8_t i_data) +{ + FAPI_MFG("%s DIMM%u F%uRC%02x: 0x%02x", mss::c_str(i_target), i_dimm, i_func_space, i_rcw_number, i_data); +} + + +/// +/// @brief Displays lane failure information after training +/// @tparam T response struct +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// +template <typename T> +void display_lane_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info) +{ + for(uint8_t l_lane = 0; l_lane < exp_struct_sizes::TRAINING_RESPONSE_NUM_LANES; ++l_lane) + { + display_lane_results( i_target, l_lane, i_training_info.err_resp.Failure_Lane[l_lane]); + } +} + +/// +/// @brief Displays MR information +/// @tparam T response struct +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// +template <typename T> +fapi2::ReturnCode display_mrs_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info) +{ + // Loop through all ports + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + // Rank info object for + std::vector<mss::rank::info<>> l_rank_info_vect; + uint8_t l_dram_width[mss::exp::sizes::MAX_DIMM_PER_PORT] = {}; + FAPI_TRY(mss::rank::ranks_on_port<>(l_port, l_rank_info_vect)); + FAPI_TRY(mss::attr::get_dram_width(l_port, l_dram_width)); + + // Loops through all of the ranks + for (const auto& l_rank_info : l_rank_info_vect) + { + const uint8_t l_phy_rank = l_rank_info.get_phy_rank(); + const uint8_t l_port_rank = l_rank_info.get_port_rank(); + const uint8_t l_dram_width_for_dimm = l_dram_width[mss::index(l_rank_info.get_dimm_target())]; + // MR0->5 are easy, just display the value + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 0, i_training_info.mrs_resp.MR0); + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 1, i_training_info.mrs_resp.MR1[l_phy_rank]); + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 2, i_training_info.mrs_resp.MR2[l_phy_rank]); + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 3, i_training_info.mrs_resp.MR3); + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 4, i_training_info.mrs_resp.MR4); + FAPI_MFG("%s rank%u MR%u 0x%04x", mss::c_str(i_target), l_port_rank, 5, i_training_info.mrs_resp.MR5[l_phy_rank]); + + // The number of the DRAM's and the position to access each DRAM changes based upon x4 vs x8 + const auto l_num_dram = l_dram_width_for_dimm == fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X4 ? + mss::exp::generic_consts::EXP_NUM_DRAM_X4 : mss::exp::generic_consts::EXP_NUM_DRAM_X8; + // The correction factor is used to determine the correct DRAM position, as x8 DRAM's take up two entries + const auto l_correction_factor = l_dram_width_for_dimm == fapi2::ENUM_ATTR_MEM_EFF_DRAM_WIDTH_X4 ? 1 : 2; + + for (uint64_t l_dram = 0; l_dram < l_num_dram; ++l_dram) + { + const auto l_dram_pos = l_correction_factor * l_dram; + FAPI_MFG("%s rank%u MR6 dram%u 0x%04x", mss::c_str(i_target), l_port_rank, l_dram, + i_training_info.mrs_resp.MR6[l_phy_rank][l_dram_pos]); + } + } + } + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Displays all RCW information +/// @tparam T response struct +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// +template <typename T> +void display_rcw_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info) +{ + constexpr uint64_t FUNC_SPACE0 = 0; + constexpr uint64_t FUNC_SPACE1 = 1; + + // Only display the DIMM's that exist + const auto& l_dimms = mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target); + + // Display DIMM0 + if(l_dimms.size() >= 1) + { + // Display all of function space 0 + // Display all 4-bit numbers + for(uint8_t l_rcw = 0; l_rcw < exp_struct_sizes::RCW_8BIT_CUTOFF; ++l_rcw) + { + display_rcw_4bit( i_target, 0, FUNC_SPACE0, l_rcw, i_training_info.rc_resp.F0RC_D0[l_rcw]); + } + + // Display all 8-bit numbers + for(uint8_t l_rcw = exp_struct_sizes::RCW_8BIT_CUTOFF; l_rcw < exp_struct_sizes::TRAINING_RESPONSE_NUM_RC; ++l_rcw) + { + display_rcw_8bit( i_target, 0, FUNC_SPACE0, l_rcw, i_training_info.rc_resp.F0RC_D0[l_rcw]); + } + + // Display all of function space 1 + // Display all 4-bit numbers + for(uint8_t l_rcw = 0; l_rcw < exp_struct_sizes::RCW_8BIT_CUTOFF; ++l_rcw) + { + display_rcw_4bit( i_target, 0, FUNC_SPACE1, l_rcw, i_training_info.rc_resp.F1RC_D0[l_rcw]); + } + + // Display all 8-bit numbers + for(uint8_t l_rcw = exp_struct_sizes::RCW_8BIT_CUTOFF; l_rcw < exp_struct_sizes::TRAINING_RESPONSE_NUM_RC; ++l_rcw) + { + display_rcw_8bit( i_target, 0, FUNC_SPACE1, l_rcw, i_training_info.rc_resp.F1RC_D0[l_rcw]); + } + } + + // Display DIMM1 + if(l_dimms.size() == 2) + { + // Display all of function space 0 + // Display all 4-bit numbers + for(uint8_t l_rcw = 0; l_rcw < exp_struct_sizes::RCW_8BIT_CUTOFF; ++l_rcw) + { + display_rcw_4bit( i_target, 1, FUNC_SPACE0, l_rcw, i_training_info.rc_resp.F0RC_D1[l_rcw]); + } + + // Display all 8-bit numbers + for(uint8_t l_rcw = exp_struct_sizes::RCW_8BIT_CUTOFF; l_rcw < exp_struct_sizes::TRAINING_RESPONSE_NUM_RC; ++l_rcw) + { + display_rcw_8bit( i_target, 1, FUNC_SPACE0, l_rcw, i_training_info.rc_resp.F0RC_D1[l_rcw]); + } + + // Display all of function space 1 + // Display all 4-bit numbers + for(uint8_t l_rcw = 0; l_rcw < exp_struct_sizes::RCW_8BIT_CUTOFF; ++l_rcw) + { + display_rcw_4bit( i_target, 1, FUNC_SPACE1, l_rcw, i_training_info.rc_resp.F1RC_D1[l_rcw]); + } + + // Display all 8-bit numbers + for(uint8_t l_rcw = exp_struct_sizes::RCW_8BIT_CUTOFF; l_rcw < exp_struct_sizes::TRAINING_RESPONSE_NUM_RC; ++l_rcw) + { + display_rcw_8bit( i_target, 1, FUNC_SPACE1, l_rcw, i_training_info.rc_resp.F1RC_D1[l_rcw]); + } + } +} + +/// +/// @brief Displays command to command response timing +/// @tparam T response struct /// @param[in] i_target the OCMB target /// @param[in] i_training_info the training information to display /// @return returns FAPI2_RC_SUCCESS iff the procedure executes successfully -/// @note This is a place holder to help avoid merge conflicts /// -inline fapi2::ReturnCode display_info(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - const user_response_msdg_t& i_training_info) +template <typename T> +inline fapi2::ReturnCode display_response_timing(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info) { + // Loop through all ports + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + // Rank info object for + std::vector<mss::rank::info<>> l_rank_info_vect; + FAPI_TRY(mss::rank::ranks_on_port<>(l_port, l_rank_info_vect)); + + // DFIMRL_DDRCLK_trained training result + FAPI_MFG("%s DFIMRL_DDRCLK_trained: %u", mss::c_str(i_target), i_training_info.tm_resp.DFIMRL_DDRCLK_trained); + + // RD to RD + FAPI_MFG("%s RD-to-RD : 0 1 2 3", mss::c_str(i_target)); + + for(const auto& l_rank : l_rank_info_vect) + { + const auto l_phy_rank = l_rank.get_phy_rank(); + const auto l_port_rank = l_rank.get_port_rank(); + FAPI_MFG("%s RD-to-RD rank%u: %2i %2i %2i %2i", mss::c_str(i_target), l_port_rank, + i_training_info.tm_resp.CDD_RR[l_phy_rank][0], i_training_info.tm_resp.CDD_RR[l_phy_rank][1], + i_training_info.tm_resp.CDD_RR[l_phy_rank][2], i_training_info.tm_resp.CDD_RR[l_phy_rank][3]); + } + + // WR to WR + FAPI_MFG("%s WR-to-WR : 0 1 2 3", mss::c_str(i_target)); + + for(const auto& l_rank : l_rank_info_vect) + { + const auto l_phy_rank = l_rank.get_phy_rank(); + const auto l_port_rank = l_rank.get_port_rank(); + FAPI_MFG("%s WR-to-WR rank%u: %2i %2i %2i %2i", mss::c_str(i_target), l_port_rank, + i_training_info.tm_resp.CDD_WW[l_phy_rank][0], i_training_info.tm_resp.CDD_WW[l_phy_rank][1], + i_training_info.tm_resp.CDD_WW[l_phy_rank][2], i_training_info.tm_resp.CDD_WW[l_phy_rank][3]); + } + + // WR to RD + FAPI_MFG("%s WR-to-RD : 0 1 2 3", mss::c_str(i_target)); + + for(const auto& l_rank : l_rank_info_vect) + { + const auto l_phy_rank = l_rank.get_phy_rank(); + const auto l_port_rank = l_rank.get_port_rank(); + FAPI_MFG("%s WR-to-RD rank%u: %2i %2i %2i %2i", mss::c_str(i_target), l_port_rank, + i_training_info.tm_resp.CDD_WR[l_phy_rank][0], i_training_info.tm_resp.CDD_WR[l_phy_rank][1], + i_training_info.tm_resp.CDD_WR[l_phy_rank][2], i_training_info.tm_resp.CDD_WR[l_phy_rank][3]); + } + + // RD to WR + FAPI_MFG("%s RD-to-WR : 0 1 2 3", mss::c_str(i_target)); + + for(const auto& l_rank : l_rank_info_vect) + { + const auto l_phy_rank = l_rank.get_phy_rank(); + const auto l_port_rank = l_rank.get_port_rank(); + FAPI_MFG("%s RD-to-WR rank%u: %2i %2i %2i %2i", mss::c_str(i_target), l_port_rank, + i_training_info.tm_resp.CDD_RW[l_phy_rank][0], i_training_info.tm_resp.CDD_RW[l_phy_rank][1], + i_training_info.tm_resp.CDD_RW[l_phy_rank][2], i_training_info.tm_resp.CDD_RW[l_phy_rank][3]); + } + } + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Display train_2d_read_eye_msdg_t response struct +/// +/// @param[in] i_target OCMB target +/// @param[in] i_training_info training info struct +/// +void display_train_2d_read_eye(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg_t& i_training_info); + +/// +/// @brief Display train_2d_write_eye_msdg_t response struct +/// +/// @param[in] i_target OCMB target +/// @param[in] i_training_info training info struct +/// +void display_train_2d_write_eye(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_2_msdg_t& i_training_info); + +/// +/// @brief Displays all training information common to all response structs +/// @tparam T response struct +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return returns FAPI2_RC_SUCCESS iff the procedure executes successfully +/// +template <typename T> +inline fapi2::ReturnCode display_normal_info( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info) +{ + // Target trace & FAPI_INF moved to the caller(s) such that we can call this from the eye capture functions + display_rcw_info(i_target, i_training_info); + FAPI_TRY(display_mrs_info(i_target, i_training_info)); + display_lane_info(i_target, i_training_info); + FAPI_TRY(display_response_timing(i_target, i_training_info)); + +fapi_try_exit: + return fapi2::current_err; } +/// +/// @brief Displays all training information +/// @tparam T response struct +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +template <typename T> +fapi2::ReturnCode display_user_2d_eye_info( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const T& i_training_info); + +/// +/// @brief Displays all training information for eye response 1 +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +template <> +fapi2::ReturnCode display_user_2d_eye_info<user_2d_eye_response_1_msdg_t>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_1_msdg_t& i_training_info); + +/// +/// @brief Displays all training information for eye response 2 +/// @param[in] i_target the OCMB target +/// @param[in] i_training_info the training information to display +/// @return fapi2::FAPI2_RC_SUCCESS iff success +/// +template <> +fapi2::ReturnCode display_user_2d_eye_info<user_2d_eye_response_2_msdg_t>( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const user_2d_eye_response_2_msdg_t& i_training_info); } // ns train } // ns exp diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C index 0418b59d1..82a538c32 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -46,17 +46,40 @@ namespace mss { /// -/// @brief A generic bad bits setter -/// @tparam MC type memory controller type +/// @brief Bad bit getter - Explorer specialization /// @param[in] i_target the fapi2 target oon which training was conducted -/// @param[in] i_array the bad bits to set +/// @param[out] o_array the bad bits +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +template <> +fapi2::ReturnCode get_bad_dq_bitmap<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT]) +{ + return mss::attr::get_bad_dq_bitmap(i_target, o_array); +} + +/// +/// @brief Bad bit setter - Explorer specialization +/// @param[in] i_target the fapi2 target oon which training was conducted +/// @param[in] i_array the bad bits to append /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if bad bits can be repaired /// template <> fapi2::ReturnCode set_bad_dq_bitmap<mss::mc_type::EXPLORER>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t (&i_array)[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT]) { - return mss::attr::set_bad_dq_bitmap(i_target, i_array); + uint8_t l_current_data[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT] = {}; + + // Get existing bad bits data + FAPI_TRY(mss::attr::get_bad_dq_bitmap(i_target, l_current_data)); + + // Now, or the new bits and any existing bits together + mss::combine_bad_bits(l_current_data, i_array); + + FAPI_TRY(mss::attr::set_bad_dq_bitmap(i_target, i_array)); + +fapi_try_exit: + return fapi2::current_err; } namespace check @@ -72,12 +95,11 @@ namespace check // TK update this when FIR's are fully reviewed template<> fapi2::ReturnCode bad_fir_bits<mss::mc_type::EXPLORER>( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, - fapi2::ReturnCode& io_rc, bool& o_fir_error ) { - io_rc = fapi2::FAPI2_RC_SUCCESS; + FAPI_ERR("%s Checking for FIR's is currently unimplemented. Passing back the discovered RC", mss::c_str(i_target)); o_fir_error = false; return fapi2::FAPI2_RC_SUCCESS; } @@ -94,52 +116,17 @@ namespace exp /// @param[out] o_resp the processed training response class /// @return FAPI2_RC_SUCCESS if ok /// -fapi2::ReturnCode read_training_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, +fapi2::ReturnCode read_normal_training_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, const std::vector<uint8_t>& i_data, user_response_msdg& o_resp) { - - // True if we pass // We assert at the end to avoid LOTS of fapi asserts uint32_t l_idx = 0; - bool l_pass = readLE(i_data, l_idx, o_resp.version_number); - - // Reads in the timing portion of the training response - l_pass &= readLE(i_data, l_idx, o_resp.tm_resp.DFIMRL_DDRCLK_trained); - l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_RR[0][0]); - l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_WW[0][0]); - l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_RW[0][0]); - l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &o_resp.tm_resp.CDD_WR[0][0]); - - // Error response - l_pass &= readLEArray(i_data, 80, l_idx, o_resp.err_resp.Failure_Lane); - - // MRS response - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR0); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR1); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR2); - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR3); - l_pass &= readLE(i_data, l_idx, o_resp.mrs_resp.MR4); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, o_resp.mrs_resp.MR5); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_MR6_SIZE, l_idx, &o_resp.mrs_resp.MR6[0][0]); - - // Register Control Word (RCW) response - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F0RC_D0); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F1RC_D0); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F0RC_D1); - l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, o_resp.rc_resp.F1RC_D1); - - // Check if we have errors - FAPI_ASSERT( l_pass, - fapi2::EXP_INBAND_LE_DATA_RANGE() - .set_TARGET(i_target) - .set_FUNCTION(mss::exp::READ_TRAINING_RESPONSE_STRUCT) - .set_DATA_SIZE(i_data.size()) - .set_MAX_INDEX(sizeof(user_response_msdg)), - "%s Failed to convert from data to host_fw_response_struct data size %u expected size %u", - mss::c_str(i_target), i_data.size(), sizeof(user_response_msdg)); + uint32_t l_version_number = 0; + bool l_pass = readLE(i_data, l_idx, l_version_number); + o_resp.version_number = l_version_number; - return fapi2::FAPI2_RC_SUCCESS; + FAPI_TRY(read_tm_err_mrs_rc_response<user_response_msdg>(i_target, i_data, l_idx, l_pass, o_resp)); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H index 41c868946..dc599616c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/phy/exp_train_handler.H @@ -38,7 +38,10 @@ #include <fapi2.H> #include <lib/shared/exp_consts.H> +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> #include <exp_data_structs.H> +#include <generic/memory/lib/utils/endian_utils.H> #include <generic/memory/lib/utils/mss_bad_bits.H> #include <generic/memory/lib/mss_generic_attribute_setters.H> #include <generic/memory/lib/mss_generic_attribute_getters.H> @@ -49,20 +52,204 @@ namespace exp { /// -/// @brief Reads the training response structure -/// @param[in] i_target the target associated with the response data -/// @param[in] i_data the response data to read -/// @param[out] o_resp the processed training response class -/// @return FAPI2_RC_SUCCESS if ok +/// @brief Read eye capture response data from explorer data buffer +/// +/// @tparam T Response struct type +/// @param[in] i_target OCMB target +/// @param[in] i_data Raw data bytes +/// @param[in,out] io_current_idx Current parsing index +/// @param[in,out] io_pass any errors occurred during reading/endian-swapping +/// @param[in,out] io_resp response struct +/// @note this function expects io_current_index to be set correctly to the start of eye capture data +/// +template <typename T> +void read_eye_capture_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + uint32_t& io_current_idx, + bool& io_pass, + T& io_resp); + +/// +/// @brief Read eye capture response data from explorer data buffer (eye capture step 1) +/// +/// @param[in] i_target OCMB target +/// @param[in] i_data Raw data bytes +/// @param[in,out] io_current_idx Current parsing index +/// @param[in,out] io_pass any errors occurred during reading/endian-swapping +/// @param[in,out] io_resp train_2d_read_eye_msdg +/// @note this function expects io_current_index to be set correctly to the start of eye capture data /// -fapi2::ReturnCode read_training_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, +template<> +inline void read_eye_capture_response<user_2d_eye_response_1_msdg>(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target, const std::vector<uint8_t>& i_data, - user_response_msdg& o_resp); + uint32_t& io_current_idx, + bool& io_pass, + user_2d_eye_response_1_msdg& io_resp) +{ + // Eye capture step 1 struct + uint32_t l_idx = io_current_idx; + bool l_pass = io_pass; + + // VrefDAC0: 3D array of 2 1D arrays + for (uint8_t l_num_ranks = 0; l_num_ranks < TRAINING_RESPONSE_NUM_RANKS; ++l_num_ranks) + { + for (uint8_t l_dbyte_n_size = 0; l_dbyte_n_size < DBYTE_N_SIZE; ++ l_dbyte_n_size) + { + for (uint8_t l_bit_n_sze = 0; l_bit_n_sze < BIT_N_SIZE; ++ l_bit_n_sze) + { + l_pass &= readLEArray(i_data, EYE_MIN_MAX_SIZE, l_idx, + &io_resp.read_2d_eye_resp.VrefDAC0[l_num_ranks][l_dbyte_n_size][l_bit_n_sze].eye_min[0]); + l_pass &= readLEArray(i_data, EYE_MIN_MAX_SIZE, l_idx, + &io_resp.read_2d_eye_resp.VrefDAC0[l_num_ranks][l_dbyte_n_size][l_bit_n_sze].eye_max[0]); + } + } + } + + // 2D array VrefDAC0_Center [DBYTE_N_SIZE][BIT_N_SIZE] + l_pass &= readLEArray(i_data, (DBYTE_N_SIZE * BIT_N_SIZE), l_idx, + &io_resp.read_2d_eye_resp.VrefDAC0_Center[0][0]); + + // 2D array RxClkDly_Center [TRAINING_RESPONSE_NUM_RANKS][NIBBLE_N_SIZE] + l_pass &= readLEArray(i_data, (TRAINING_RESPONSE_NUM_RANKS * NIBBLE_N_SIZE), l_idx, + &io_resp.read_2d_eye_resp.RxClkDly_Center[0][0]); + + io_pass = l_pass; + io_current_idx = l_idx; +} + +/// +/// @brief Read eye capture response data from explorer data buffer (eye capture step 2) +/// +/// @param[in] i_target OCMB target +/// @param[in] i_data Raw data bytes +/// @param[in,out] io_current_idx Current parsing index +/// @param[in,out] io_pass any errors occurred during reading/endian-swapping +/// @param[in,out] io_resp user_2d_eye_response_2_msdg +/// @note this function expects io_current_index to be set correctly to the start of eye capture data +/// +template<> +inline void read_eye_capture_response<user_2d_eye_response_2_msdg>(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& + i_target, + const std::vector<uint8_t>& i_data, + uint32_t& io_current_idx, + bool& io_pass, + user_2d_eye_response_2_msdg& io_resp) +{ + + // Eye capture step 1 struct + uint32_t l_idx = io_current_idx; + bool l_pass = io_pass; + + // VrefDQ: 3D array of 2 1D arrays + for (uint8_t l_num_ranks = 0; l_num_ranks < TRAINING_RESPONSE_NUM_RANKS; ++l_num_ranks) + { + for (uint8_t l_dbyte_n_size = 0; l_dbyte_n_size < DBYTE_N_SIZE; ++ l_dbyte_n_size) + { + for (uint8_t l_bit_n_sze = 0; l_bit_n_sze < BIT_N_SIZE; ++ l_bit_n_sze) + { + l_pass &= readLEArray(i_data, EYE_MIN_MAX_SIZE, l_idx, + &io_resp.write_2d_eye_resp.VrefDQ[l_num_ranks][l_dbyte_n_size][l_bit_n_sze].eye_min[0]); + l_pass &= readLEArray(i_data, EYE_MIN_MAX_SIZE, l_idx, + &io_resp.write_2d_eye_resp.VrefDQ[l_num_ranks][l_dbyte_n_size][l_bit_n_sze].eye_max[0]); + } + } + } + + // 2D array VrefDQ_Center [TRAINING_RESPONSE_NUM_RANKS][NIBBLE_N_SIZE] + l_pass &= readLEArray(i_data, (TRAINING_RESPONSE_NUM_RANKS * NIBBLE_N_SIZE), l_idx, + &io_resp.write_2d_eye_resp.VrefDQ_Center[0][0]); + + // 3D array TxDqDly_Center [TRAINING_RESPONSE_NUM_RANKS][DBYTE_N_SIZE][DBYTE_N_SIZE] + l_pass &= readLEArray(i_data, (TRAINING_RESPONSE_NUM_RANKS * DBYTE_N_SIZE * BIT_N_SIZE), l_idx, + &io_resp.write_2d_eye_resp.TxDqDly_Center[0][0][0]); + + io_pass = l_pass; + io_current_idx = l_idx; + + return; +} + +/// +/// @brief Read the common block of fields from the training response structs +/// +/// @tparam T training repsonse struct type +/// @param[in] i_target OCMB chip +/// @param[in] i_data response data +/// @param[in] i_current_idx last index left off +/// @param[in] i_pass response parsing success thus far +/// @param[in,out] io_resp response struct +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +template <typename T> +fapi2::ReturnCode read_tm_err_mrs_rc_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + const uint32_t i_current_idx, + const bool i_pass, + T& io_resp) +{ + uint32_t l_idx = i_current_idx; + bool l_pass = i_pass; + + uint16_t l_DFIMRL_DDRCLK_trained = 0; + + // Reads in the timing portion of the training response + l_pass &= readLE(i_data, l_idx, l_DFIMRL_DDRCLK_trained); + l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &io_resp.tm_resp.CDD_RR[0][0]); + l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &io_resp.tm_resp.CDD_WW[0][0]); + l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &io_resp.tm_resp.CDD_RW[0][0]); + l_pass &= readLEArray(i_data, TIMING_RESPONSE_2D_ARRAY_SIZE, l_idx, &io_resp.tm_resp.CDD_WR[0][0]); + + // Write to user_response_msdg + io_resp.tm_resp.DFIMRL_DDRCLK_trained = l_DFIMRL_DDRCLK_trained; + + // Error response + l_pass &= readLEArray(i_data, 80, l_idx, io_resp.err_resp.Failure_Lane); + + uint16_t l_MR0 = 0; + uint16_t l_MR3 = 0; + uint16_t l_MR4 = 0; + + // MRS response + l_pass &= readLE(i_data, l_idx, l_MR0); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, io_resp.mrs_resp.MR1); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, io_resp.mrs_resp.MR2); + l_pass &= readLE(i_data, l_idx, l_MR3); + l_pass &= readLE(i_data, l_idx, l_MR4); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RANKS, l_idx, io_resp.mrs_resp.MR5); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_MR6_SIZE, l_idx, &io_resp.mrs_resp.MR6[0][0]); + + io_resp.mrs_resp.MR0 = l_MR0; + io_resp.mrs_resp.MR3 = l_MR3; + io_resp.mrs_resp.MR4 = l_MR4; + + // Register Control Word (RCW) response + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, io_resp.rc_resp.F0RC_D0); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, io_resp.rc_resp.F1RC_D0); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, io_resp.rc_resp.F0RC_D1); + l_pass &= readLEArray(i_data, TRAINING_RESPONSE_NUM_RC, l_idx, io_resp.rc_resp.F1RC_D1); + + // Check if we have errors + FAPI_ASSERT( l_pass, + fapi2::EXP_INBAND_LE_DATA_RANGE() + .set_TARGET(i_target) + .set_FUNCTION(mss::exp::READ_TRAINING_RESPONSE_STRUCT) + .set_DATA_SIZE(i_data.size()) + .set_MAX_INDEX(sizeof(T)), + "%s Failed to convert from data to host_fw_response_struct data size %u expected size %u", + mss::c_str(i_target), i_data.size(), sizeof(T)); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Explorer's bad bit interface class -/// @brief Explorer's bad bit interface class +/// @tparam T user response struct type /// +template <typename T> class bad_bit_interface { public: @@ -83,7 +270,7 @@ class bad_bit_interface /// @brief Constructor /// @param[in] i_response response data from training /// - bad_bit_interface(const user_response_msdg_t& i_response ) + bad_bit_interface(const T& i_response ) { // First, clear everything std::fill(&iv_bad_bits[0][0], &iv_bad_bits[0][0] + sizeof(iv_bad_bits), 0); @@ -154,28 +341,12 @@ class bad_bit_interface fapi2::ReturnCode record_bad_bits_interface( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t (&o_bad_dq)[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT]) const { - // Gets the rank offset for this DIMM - const uint64_t DIMM_OFFSET = mss::index(i_target) == 0 ? 0 : 2; - - // Loops through all of the ranks on this DIMM - uint8_t l_num_ranks = 0; - FAPI_TRY(mss::attr::get_num_master_ranks_per_dimm(i_target, l_num_ranks)); + std::vector<mss::rank::info<>> l_ranks; + FAPI_TRY(mss::rank::ranks_on_dimm(i_target, l_ranks)); - // TK Add in num ranks check here - // TK update for the ranks API - - for(uint64_t l_rank = 0; l_rank < l_num_ranks; ++l_rank) + for(const auto& l_rank : l_ranks) { - const uint64_t RANK = DIMM_OFFSET + l_rank; - FAPI_ASSERT(RANK < mss::exp::MAX_RANK_PER_DIMM, - fapi2::MSS_EXP_DRAMINIT_BAD_NUM_RANKS() - .set_NUM_RANKS(RANK) - .set_MAX_RANKS(mss::exp::MAX_RANK_PER_DIMM) - .set_TARGET(i_target), - "%s bad number of ranks passed num:%u, max:%u", - mss::c_str(i_target), RANK, mss::exp::MAX_RANK_PER_DIMM); - - memcpy(&o_bad_dq[RANK], &iv_bad_bits[RANK], sizeof(uint8_t[BAD_DQ_BYTE_COUNT])); + memcpy(&o_bad_dq[l_rank.get_phy_rank()], &iv_bad_bits[l_rank.get_phy_rank()], sizeof(uint8_t[BAD_DQ_BYTE_COUNT])); } return fapi2::FAPI2_RC_SUCCESS; @@ -185,6 +356,48 @@ class bad_bit_interface } }; + +/// +/// @brief Reads the training response structure +/// @param[in] i_target the target associated with the response data +/// @param[in] i_data the response data to read +/// @param[out] o_resp the processed training response class +/// @return FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode read_normal_training_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + user_response_msdg& o_resp); + +/// +/// @brief Reads user 2d eye response 1 +/// @tparam T response struct +/// @param[in] i_target the target associated with the response data +/// @param[in] i_data the response data to read +/// @param[out] o_resp the processed training response class +/// @return FAPI2_RC_SUCCESS if ok +/// +template <typename T> +inline fapi2::ReturnCode read_user_2d_eye_response(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const std::vector<uint8_t>& i_data, + T& o_resp) +{ + // First let's erase the struct + memset(&o_resp, 0, sizeof(T)); + // We assert at the end to avoid LOTS of fapi asserts + uint32_t l_idx = 0; + uint32_t l_version_number = 0; + bool l_pass = readLE(i_data, l_idx, l_version_number); + o_resp.version_number = l_version_number; + + read_eye_capture_response<T>(i_target, i_data, l_idx, l_pass, o_resp); + + FAPI_TRY(read_tm_err_mrs_rc_response<T>(i_target, i_data, l_idx, l_pass, o_resp)); + +fapi_try_exit: + return fapi2::current_err; +} + + } // ns exp } // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.C new file mode 100644 index 000000000..7d833b2ff --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.C @@ -0,0 +1,155 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_plug_rules.C +/// @brief Plug rules enforcement for explorer +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/plug_rules/exp_plug_rules.H> +#include <mss_explorer_attribute_getters.H> + +namespace mss +{ +namespace exp +{ +namespace plug_rule +{ + +/// +/// @brief Determine enterprise mode from given attribute/fuse values +/// +/// @param[in] i_target OCMB chip target +/// @param[in] i_enterprise_fuse enterprise as determined from fuse +/// @param[in] i_enterprise_policy enterprise policy system attribute value +/// @param[in] i_non_enterprise_override override attribute value +/// @param[out] o_is_enterprise_mode resulting state for enterprise mode +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// @note this helper function exists for unit testing purposes +/// +fapi2::ReturnCode enterprise_mode_helper( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_enterprise_fuse, + const uint8_t i_enterprise_policy, + const uint8_t i_non_enterprise_override, + bool& o_is_enterprise_mode) +{ + o_is_enterprise_mode = false; + + // Constexprs to make things easier on the eyes + constexpr uint8_t REQUIRE_ENTERPRISE = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_POLICY_REQUIRE_ENTERPRISE; + constexpr uint8_t FORCE_NONENTERPRISE = fapi2::ENUM_ATTR_MSS_OCMB_ENTERPRISE_POLICY_FORCE_NONENTERPRISE; + + // Truth table: + // Enterprise (fuse): 0=Disabled 1=Enabled (inverted from fuse logic) + // Policy: 0=ALLOW_ENTERPRISE (allow any) 1=REQUIRE_ENTERPRISE 2=FORCE_NONENTERPRISE + // Override OFF: 0=NO_OVERRIDE 1=OVERRIDE_TO_NONENTERPRISE + // + // Enterprise (fuse) Policy Override OFF Result Description + // 0 0 0 0 + // 0 0 1 0 + // 1 0 0 1 + // 1 0 1 0 + // 0 1 0 Error: We don't support enterprise + // 0 1 1 Error: We don't support enterprise + // 1 1 0 1 + // 1 1 1 0 Override beats policy + // 0 2 0 0 + // 0 2 1 0 + // 1 2 0 Error: Policy does not allow for enterprise dimm plugged in + // 1 2 1 Error: Policy does not allow for enterprise dimm plugged in + + // Check if we have one of the error configurations + const bool l_invalid_config = ((!i_enterprise_fuse) && (i_enterprise_policy == REQUIRE_ENTERPRISE)) || + ((i_enterprise_fuse) && (i_enterprise_policy == FORCE_NONENTERPRISE)); + + // For the below assert, i_enterprise_policy must be 1 or 2 to assert out, + // so we can use the ternary operator to generate a string description from these two cases + FAPI_ASSERT(!l_invalid_config, + fapi2::MSS_EXP_ENTERPRISE_INVALID_CONFIGURATION() + .set_OCMB_TARGET(i_target) + .set_ENTERPRISE_SUPPORTED(i_enterprise_fuse) + .set_POLICY(i_enterprise_policy), + "%s The enterprise supported bit from the Explorer efuse: %u conflicts with the enterprise " + "policy attribute setting: %s", + mss::c_str(i_target), + i_enterprise_fuse, + (i_enterprise_policy == FORCE_NONENTERPRISE ? "FORCE_NONENTERPRISE" : "REQUIRE_ENTERPRISE")); + + // Now generate the resulting value from the remaining truth table entries + // We are non-enterprise whenever i_enterprise_policy is 2, or i_non_enterprise_override. + // Otherwise, we use the value of i_enterprise_fuse + o_is_enterprise_mode = i_enterprise_fuse && !((i_enterprise_policy == FORCE_NONENTERPRISE) + || (i_non_enterprise_override)); + + FAPI_INF("%s is in %s mode. (OCMB chip is %s, with %s)", + mss::c_str(i_target), + o_is_enterprise_mode ? "enterprise" : "non-enterprise", + i_enterprise_fuse ? "enterprise" : "non-enterprise", + i_non_enterprise_override ? "override to non-enterprise" : "no override"); + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Gets whether the OCMB will be configred to enterprise mode, will assert out if policy/override do not agree +/// @param[in] i_target OCMB target on which to operate +/// @param[in] i_enterprise_fuse enterprise as determined from fuse +/// @param[out] o_is_enterprise_mode true if the part is in enterprise mode +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// +fapi2::ReturnCode enterprise_mode( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_enterprise_fuse, + bool& o_is_enterprise_mode ) +{ + o_is_enterprise_mode = false; + + // Variables + uint8_t l_enterprise_policy = 0; + uint8_t l_override_attr = 0; + + FAPI_TRY( mss::attr::get_ocmb_enterprise_policy(l_enterprise_policy) ); + FAPI_TRY( mss::attr::get_ocmb_nonenterprise_mode_override(i_target, l_override_attr) ); + + // This function will populate o_is_enterprise_mode accordingly + FAPI_TRY(enterprise_mode_helper(i_target, i_enterprise_fuse, l_enterprise_policy, l_override_attr, + o_is_enterprise_mode)); + +fapi_try_exit: + return fapi2::current_err; +} +} // plug_rule +} // exp +} // mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.H index de58c465c..2fbc0d7df 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.C $ */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/plug_rules/exp_plug_rules.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,45 +24,59 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file ecc_traits.C -/// @brief Traits class for the MC ECC syndrome registers +/// @file exp_plug_rules.H +/// @brief Plug rules enforcement for explorer /// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory -// *HWP Level: 3 +// *HWP Level: 2 // *HWP Consumed by: FSP:HB +#ifndef _EXP_PLUG_RULES_H_ +#define _EXP_PLUG_RULES_H_ + #include <fapi2.H> -#include <lib/ecc/ecc_traits.H> namespace mss { +namespace exp +{ +namespace plug_rule +{ -// we need these declarations here in order for the linker to see the definitions -// in the eccTraits class -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_NCE_REGS[]; -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_RCE_REGS[]; -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_MPE_REGS[]; -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_UE_REGS[]; -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::MAINLINE_AUE_REGS[]; -constexpr const uint64_t eccTraits<fapi2::TARGET_TYPE_MCA>::ERROR_VECTOR_REGS[]; +/// +/// @brief Determine enterprise mode from given attribute/fuse values +/// +/// @param[in] i_target OCMB chip target +/// @param[in] i_enterprise_fuse enterprise as determined from fuse +/// @param[in] i_enterprise_policy enterprise policy system attribute value +/// @param[in] i_non_enterprise_override override attribute value +/// @param[out] o_is_enterprise_mode resulting state for enterprise mode +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// @note this helper function exists for unit testing purposes +/// +fapi2::ReturnCode enterprise_mode_helper( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_enterprise_fuse, + const uint8_t i_enterprise_policy, + const uint8_t i_non_enterprise_override, + bool& o_is_enterprise_mode); -constexpr const uint8_t eccTraits<fapi2::TARGET_TYPE_MCA>::symbol2galois[]; -constexpr const uint8_t eccTraits<fapi2::TARGET_TYPE_MCA>::symbol2dq[]; +/// +/// @brief Gets whether the OCMB will be configred to enterprise mode, will assert out if policy/override do not agree +/// @param[in] i_target OCMB target on which to operate +/// @param[in] i_enterprise_fuse enterprise as determined from fuse +/// @param[out] o_is_enterprise_mode true if the part is in enterprise mode +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// +fapi2::ReturnCode enterprise_mode( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const bool i_enterprise_fuse, + bool& o_is_enterprise_mode ); -// Definition of the symbol error count registers -const std::vector< uint64_t > eccTraits<fapi2::TARGET_TYPE_MCBIST>::SYMBOL_COUNT_REG = -{ - MCBIST_MBSSYMEC0Q, - MCBIST_MBSSYMEC1Q, - MCBIST_MBSSYMEC2Q, - MCBIST_MBSSYMEC3Q, - MCBIST_MBSSYMEC4Q, - MCBIST_MBSSYMEC5Q, - MCBIST_MBSSYMEC6Q, - MCBIST_MBSSYMEC7Q, - MCBIST_MBSSYMEC8Q, -}; +} // plug_rule +} // exp +} // mss -} // close namespace mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/pmic/exp_pmic_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/pmic/exp_pmic_consts.H deleted file mode 100644 index 497dd52ff..000000000 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/pmic/exp_pmic_consts.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/pmic/exp_pmic_consts.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.C index eedfafe84..ea703b9e7 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.C @@ -22,3 +22,285 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_decoder.C +/// @brief Decode MRW attributes for DIMM power curves and power limits +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <lib/shared/exp_defaults.H> +// fapi2 +#include <fapi2.H> +#include <vector> +#include <utility> + +#include <lib/shared/exp_consts.H> +#include <lib/power_thermal/exp_decoder.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/utils/power_thermal/gen_decoder.H> + +namespace mss +{ +namespace power_thermal +{ + +const std::vector< std::pair<uint8_t , uint8_t> > throttle_traits<mss::mc_type::EXPLORER>::DIMM_TYPE_MAP = +{ + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM, 0b00}, + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM, 0b01}, + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM, 0b10}, + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM, 0b11}, + {ANY_TYPE, 0b111} +}; + +/// +/// @brief Finds a value for the power curve slope attributes by matching the generated hashes +/// @param[in] i_slope vector of generated key-values from MRW power curve attriutes +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful +/// @note populates iv_vddr_slope, iv_total_slope +/// +template<> +fapi2::ReturnCode decoder<mss::mc_type::EXPLORER>::find_slope ( + const std::vector< const std::vector<uint64_t>* >& i_slope) +{ + using TT = throttle_traits<mss::mc_type::EXPLORER>; + + // For explorer, two attribute are used to get slope (i_slope[0], i_slope[1]) + // ATTR_MSS_MRW_OCMB_PWR_SLOPE is for thermal power slope + // ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT is for power slope + FAPI_ASSERT(i_slope.size() == 2, + fapi2::MSS_POWER_THERMAL_ATTR_VECTORS_INCORRECT() + .set_FUNCTION(SLOPE) + .set_INPUT_SIZE(i_slope.size()) + .set_EXPECTED_SIZE(2), + "The attributes vectors size is incorrect for find_slope input:%d, expected:%d", + i_slope.size(), + 2); + + // To get thermal power slope + FAPI_TRY( (get_power_thermal_value<TT::THERMAL_START, TT::THERMAL_LENGTH, SLOPE>( + *i_slope[0], + "ATTR_MSS_MRW_OCMB_PWR_SLOPE", + iv_total_slope)) ); + + // To get power slope + FAPI_TRY( (get_power_thermal_value<TT::POWER_SLOPE_START, TT::POWER_SLOPE_LENGTH, SLOPE>( + *i_slope[1], + "ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT", + iv_vddr_slope)) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Finds a value for power curve intercept attributes by matching the generated hashes +/// @param[in] i_intercept vector of generated key-values from MRW power curve attributes +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful +/// @note populates iv_vddr_intercept, iv_total_intercept +/// +template<> +fapi2::ReturnCode decoder<mss::mc_type::EXPLORER>::find_intercept ( + const std::vector< const std::vector<uint64_t>* >& i_intercept) +{ + using TT = throttle_traits<mss::mc_type::EXPLORER>; + + // For explorer, two attribute are used to get slope (i_slope[0], i_slope[1]) + // ATTR_MSS_MRW_OCMB_PWR_INTERCEPT is for thermal power intercept + // ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT is for power intercept + FAPI_ASSERT(i_intercept.size() == 2, + fapi2::MSS_POWER_THERMAL_ATTR_VECTORS_INCORRECT() + .set_FUNCTION(INTERCEPT) + .set_INPUT_SIZE(i_intercept.size()) + .set_EXPECTED_SIZE(2), + "The attributes vectors size is incorrect for find_intercept input:%d, expected:%d", + i_intercept.size(), + 2); + + // To get thermal power intercept + FAPI_TRY( (get_power_thermal_value<TT::THERMAL_START, TT::THERMAL_LENGTH, INTERCEPT>( + *i_intercept[0], + "ATTR_MSS_MRW_OCMB_PWR_INTERCEPT", + iv_total_intercept)) ); + + // To get power intercept + FAPI_TRY( (get_power_thermal_value<TT::POWER_INTERCEPT_START, TT::POWER_INTERCEPT_LENGTH, INTERCEPT>( + *i_intercept[1], + "ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT", + iv_vddr_intercept)) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief Finds a value for the power limit attributes by matching the generated hashes +/// @param[in] i_thermal_limits is a vector of the generated values from MRW power limit attributes +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful +/// @note populates iv_thermal_power_limit, iv_power_limit +/// +template<> +fapi2::ReturnCode decoder<mss::mc_type::EXPLORER>::find_thermal_power_limit ( + const std::vector< const std::vector<uint64_t>* >& i_thermal_limits) +{ + using TT = throttle_traits<mss::mc_type::EXPLORER>; + + // For explorer, two attribute are used to get slope (i_slope[0], i_slope[1]) + // ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT is for thermal power limit + // ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT is for power limit + FAPI_ASSERT(i_thermal_limits.size() == 2, + fapi2::MSS_POWER_THERMAL_ATTR_VECTORS_INCORRECT() + .set_FUNCTION(INTERCEPT) + .set_INPUT_SIZE(i_thermal_limits.size()) + .set_EXPECTED_SIZE(2), + "The attributes vectors size is incorrect for find_thermal_power_limit input:%d, expected:%d", + i_thermal_limits.size(), + 2); + + // To get thermal power limit + FAPI_TRY( (get_power_thermal_value<TT::THERMAL_START, TT::THERMAL_LENGTH, POWER_LIMIT>( + *i_thermal_limits[0], + "ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT", + iv_thermal_power_limit)) ); + + // To get regulator power or current limit + FAPI_TRY( (get_power_thermal_value<TT::POWER_LIMIT_START, TT::POWER_LIMIT_LENGTH, POWER_LIMIT>( + *i_thermal_limits[1], + "ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT", + iv_power_limit)) ); + +fapi_try_exit: + return fapi2::current_err; +} + + +/// +/// @brief find the power curve attributes for each dimm on an MEM_PORT target +/// @param[in] i_throttle_type specifies whether this is for power or thermal throttling +/// @param[in] i_port vector of MEM_PORT targets on which dimm attrs will be set +/// @param[in] i_slope vector of generated hashes for encoding the values for memory power curve slopes +/// @param[in] i_intercept vector of generated hashes for encoding the values for memory power curve intercepts +/// @param[in] i_thermal_power_limit vector of generated hashes for encoding the values for memory power limits +/// @param[in] i_current_curve_with_limit vector of generated hashes for encoding the values for regulator power curves and limits +/// @param[out] o_slope the power curve slope for each dimm +/// @param[out] o_intercept the power curve intercept for each dimm +/// @param[out] o_limit the power limit for the dimm +/// @return FAPI2_RC_SUCCESS iff ok +/// @note used to set power curve attributes in calling function +/// @note decodes the attribute "encoding" to get the power curves and power limits for a dimm +/// +fapi2::ReturnCode get_power_attrs (const mss::throttle_type i_throttle_type, + const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + const std::vector< uint64_t >& i_slope, + const std::vector< uint64_t >& i_intercept, + const std::vector< uint64_t >& i_thermal_power_limit, + const std::vector< uint64_t >& i_current_curve_with_limit, + uint16_t o_slope [throttle_traits<>::DIMMS_PER_PORT], + uint16_t o_intercept [throttle_traits<>::DIMMS_PER_PORT], + uint32_t o_limit [throttle_traits<>::DIMMS_PER_PORT]) +{ + using TT = throttle_traits<mss::mc_type::EXPLORER>; + + for (const auto& l_dimm : find_targets <fapi2::TARGET_TYPE_DIMM> (i_port)) + { + const auto l_dimm_pos = mss::index (l_dimm); + mss::dimm::kind<> l_kind (l_dimm); + mss::power_thermal::decoder<> l_decoder(l_kind); + fapi2::buffer<uint64_t> l_attr_value; + + // DDIMMs mrw slope/intercept/limit attribute values are for whole DDIMM, so divide these by total number of virtual DIMMs + // to get it to a DIMM level. This will get the DIMM count to use in later calculations. + // ISDIMMs use a value of 1 since mrw attribute values are at the DIMM level + uint8_t l_number_dimm_for_attr_value = (l_kind.iv_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM) ? + mss::count_dimm(mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(l_dimm)) : + 1; + + FAPI_TRY( l_decoder.generate_encoding(), "%s Error in get_power_attrs", mss::c_str(l_dimm) ); + + // The first entry into these arrays must be valid + // If we don't find any values, the attributes aren't found so go with some defaults + l_attr_value = i_slope[0]; + + if (i_slope.empty() || !l_attr_value.getBit<TT::POWER_LIMIT_START, TT::POWER_LENGTH>()) + { + FAPI_INF("%s ATTR_MSS_MRW_OCMB_PWR_SLOPE not found or has zero values", mss::c_str(l_dimm)); + + o_slope[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? TT::POWER_SLOPE : TT::TOTAL_SLOPE) / + l_number_dimm_for_attr_value; + } + else + { + const std::vector< const std::vector<uint64_t>* > l_slope {&i_slope, &i_current_curve_with_limit}; + + FAPI_TRY( l_decoder.find_slope(l_slope), "%s Error in get_power_attrs", mss::c_str(l_dimm) ); + + o_slope[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? l_decoder.iv_vddr_slope : l_decoder.iv_total_slope) / + l_number_dimm_for_attr_value; + } + + l_attr_value = i_intercept[0]; + + if (i_intercept.empty() || !l_attr_value.getBit<TT::POWER_LIMIT_START, TT::POWER_LENGTH>()) + { + FAPI_INF("%s ATTR_MSS_MRW_OCMB_PWR_INTERCEPT not found or has zero values", mss::c_str(l_dimm)); + + o_intercept[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? TT::POWER_INT : TT::TOTAL_INT) / + l_number_dimm_for_attr_value; + } + else + { + const std::vector< const std::vector<uint64_t>* > l_intercept {&i_intercept, &i_current_curve_with_limit}; + + FAPI_TRY( l_decoder.find_intercept(l_intercept), "%s Error in get_power_attrs", mss::c_str(l_dimm) ); + + o_intercept[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? l_decoder.iv_vddr_intercept : l_decoder.iv_total_intercept) / + l_number_dimm_for_attr_value; + } + + l_attr_value = i_thermal_power_limit[0]; + + if (i_thermal_power_limit.empty() || !l_attr_value.getBit<TT::THERMAL_START, TT::THERMAL_LENGTH>()) + { + FAPI_INF("%s ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT not found or has zero values", mss::c_str(l_dimm)); + + // The unit of limit and intercept is cA but limit is dA in mss::throttle_type::POWER + // So we need to transfer them to the same unit + o_limit[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? TT::POWER_LIMIT* DECI_TO_CENTI : TT::THERMAL_LIMIT) / + l_number_dimm_for_attr_value; + } + else + { + std::vector< const std::vector<uint64_t>* > l_thermal_power_limit {&i_thermal_power_limit, &i_current_curve_with_limit}; + + FAPI_TRY( l_decoder.find_thermal_power_limit(l_thermal_power_limit), + "%s Error in get_power_attrs", mss::c_str(l_dimm) ); + // The unit of limit and intercept is cA but limit is dA in mss::throttle_type::POWER + // So we need to transfer them to the same unit + o_limit[l_dimm_pos] = + ((i_throttle_type == mss::throttle_type::POWER) ? + l_decoder.iv_power_limit* DECI_TO_CENTI : l_decoder.iv_thermal_power_limit + ) / + l_number_dimm_for_attr_value; + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +} //ns power_thermal +} // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.H index 3ce2f3ed3..9f49ee70f 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_decoder.H @@ -22,3 +22,61 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_decoder.H +/// @brief Decoder for ATTR_MSS_MRW_PWR_CURVE_SLOPE and _INTERCEPT and THERMAL_POWER_LIMIT +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_POWER_EXP_DECODER__ +#define _MSS_POWER_EXP_DECODER__ + +#include <fapi2.H> + +#include <lib/shared/exp_consts.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <lib/power_thermal/exp_throttle.H> +#include <generic/memory/lib/utils/power_thermal/gen_decoder.H> + + +namespace mss +{ + +namespace power_thermal +{ + + +/// +/// @brief find the power curve attributes for each dimm on an MCS target +/// @param[in] i_targets vector of MCS targets on which dimm attrs will be set +/// @param[in] i_slope vector of generated hashes for encoding and values for MSS_MRW_POWER_SLOPE +/// @param[in] i_intercept vector of generated hashes for encoding and values for MSS_MRW_POWER_INTERCEPT +/// @param[in] i_thermal_power_limit vector of generated hashes for encoding and values for MSS_MRW_THERMAL_MEMORY_POWER_LIMIT +/// @param[out] o_vddr_slope the VDDR power curve slope for each dimm +/// @param[out] o_vddr_int the VDDR power curve intercept for each dimm +/// @param[out] o_total_slope the VDDR+VPP power curve slope for each dimm +/// @param[out] o_total_int the VDDR+VPP power curve intercept for each dimm +/// @param[out] o_thermal_power the thermal power limit for the dimm +/// @return FAPI2_RC_SUCCESS iff ok +/// @note used to set power curve attributes in calling function +/// @note decodes the attribute "encoding" to get the vddr and vddr/vpp power curves for a dimm +/// +fapi2::ReturnCode get_power_attrs (const mss::throttle_type i_throttle_type, + const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_port, + const std::vector< uint64_t >& i_slope, + const std::vector< uint64_t >& i_intercept, + const std::vector< uint64_t >& i_thermal_power_limit, + const std::vector< uint64_t >& i_current_curve_with_limit, + uint16_t o_slope [throttle_traits<>::DIMMS_PER_PORT], + uint16_t o_intercept [throttle_traits<>::DIMMS_PER_PORT], + uint32_t o_limit [throttle_traits<>::DIMMS_PER_PORT]); + + +} // power_thermal +} // mss +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.C index b3114480e..9c3a484f4 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,129 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_throttle.C +/// @brief Determine throttle settings for memory +/// +// *HWP HWP Owner: Andre A. Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <lib/shared/exp_defaults.H> +// fapi2 +#include <fapi2.H> + +#include <lib/shared/exp_consts.H> +#include <lib/power_thermal/exp_throttle.H> +#include <mss_explorer_attribute_getters.H> +#include <mss_explorer_attribute_setters.H> +#include <generic/memory/lib/utils/count_dimm.H> + +namespace mss +{ +namespace power_thermal +{ +/// +/// @brief Calcuate the throttle values based on throttle type +/// @param[in] i_target +/// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Called in p9_mss_bulk_pwr_throttles +/// @note determines the throttle levels based off of the port's power curve, +/// sets the slot throttles to the same +/// @note Enums are POWER for power egulator throttles and THERMAL for thermal throttles +/// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value +/// +fapi2::ReturnCode pwr_throttles( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::throttle_type i_throttle_type) +{ + if (mss::count_dimm (i_target) == 0) + { + return fapi2::FAPI2_RC_SUCCESS; + } + + uint16_t l_slot = 0; + uint16_t l_port = 0; + uint32_t l_power = 0; + + for (const auto& l_port_target : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + //Don't run if there are no dimms on the port + if (mss::count_dimm(l_port_target) == 0) + { + continue; + } + + mss::power_thermal::throttle<> l_pwr_struct(l_port_target, l_rc); + FAPI_TRY(l_rc, "Error constructing mss:power_thermal::throttle object for target %s", + mss::c_str(l_port_target)); + + //Let's do the actual work now + if ( i_throttle_type == mss::throttle_type::THERMAL) + { + FAPI_TRY (l_pwr_struct.thermal_throttles()); + } + else + { + FAPI_TRY (l_pwr_struct.power_regulator_throttles()); + } + + l_slot = l_pwr_struct.iv_n_slot; + l_port = l_pwr_struct.iv_n_port; + l_power = l_pwr_struct.iv_calc_port_maxpower; + + FAPI_INF("For target %s Calculated power is %d, throttle per slot is %d, throttle per port is %d", + mss::c_str(l_port_target), l_power, l_slot, l_port); + + FAPI_TRY(mss::attr::set_port_maxpower( l_port_target, l_power)); + FAPI_TRY(mss::attr::set_mem_throttled_n_commands_per_slot( l_port_target, l_slot)); + FAPI_TRY(mss::attr::set_mem_throttled_n_commands_per_port( l_port_target, l_port)); + } + + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("Error calculating pwr_throttles using %s throttling", + ((i_throttle_type == mss::throttle_type::POWER) ? "power" : "thermal")); + return fapi2::current_err; +} + +/// +/// @brief Equalize the throttles among OCMB chips +/// @param[in] i_targets vector of OCMB chips +/// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value +/// +fapi2::ReturnCode equalize_throttles( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& i_targets, + const mss::throttle_type i_throttle_type) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> > l_exceeded_power; + + // Set all of the throttles to the lowest value per port for performance reasons + FAPI_TRY(mss::power_thermal::equalize_throttles(i_targets, i_throttle_type, l_exceeded_power)); + + // Report any port that exceeded the max power limit, and return a failing RC if we have any + for (const auto& l_port : l_exceeded_power) + { + FAPI_ERR(" MEM_PORT %s estimated power exceeded the maximum allowed", mss::c_str(l_port) ); + fapi2::current_err = fapi2::FAPI2_RC_FALSE; + } + + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("Error calculating equalize_throttles using %s throttling", + ((i_throttle_type == mss::throttle_type::POWER) ? "power" : "thermal")); + return fapi2::current_err; +} + + + +}//namespace power_thermal +}//namespace mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.H index 83559db83..17f8a7dbc 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle.H @@ -22,3 +22,61 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_throttle.H +/// @brief throttle API +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_THROTTLE_ +#define _MSS_EXP_THROTTLE_ + +#include <fapi2.H> +#include <lib/shared/exp_consts.H> +#include <lib/power_thermal/exp_throttle.H> +#include <mss_explorer_attribute_setters.H> +#include <mss_explorer_attribute_getters.H> +#include <lib/power_thermal/exp_throttle_traits.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <generic/memory/lib/utils/power_thermal/gen_throttle.H> + +namespace mss +{ +namespace power_thermal +{ + +/// +/// @brief Set ATTR_EXP_PORT_MAXPOWER, ATTR_OCMB_EXP_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, +/// ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_PORT +/// @param[in] i_target +/// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Called in p9_mss_bulk_pwr_throttles +/// @note determines the throttle levels based off of the port's power curve, +/// sets the slot throttles to the same +/// @note Enums are POWER for power egulator throttles and THERMAL for thermal throttles +/// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value +/// +fapi2::ReturnCode pwr_throttles( const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target, + const mss::throttle_type i_throttle_type); + +/// +/// @brief Equalize the throttles among OCMB chips +/// @param[in] i_targets vector of OCMB chips +/// @param[in] i_throttle_type thermal boolean to determine whether to calculate throttles based on the power regulator or thermal limits +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note equalizes the throttles to the lowest of runtime and the lowest slot-throttle value +/// +fapi2::ReturnCode equalize_throttles( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& i_targets, + const mss::throttle_type i_throttle_type); + +}//power_thermal +}// mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle_traits.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle_traits.H index 1c8945f89..0b0d06572 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle_traits.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/power_thermal/exp_throttle_traits.H @@ -22,3 +22,147 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_throttle_traits.H +/// @brief throttle API +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_EXP_THROTTLE_TRAITS_ +#define _MSS_EXP_THROTTLE_TRAITS_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/power_thermal/gen_throttle_traits.H> + +namespace mss +{ +namespace power_thermal +{ + +/// +/// @class Traits and policy class for throttle code - specialization for the Explorer mc type +/// +template<> +class throttle_traits<mss::mc_type::EXPLORER> +{ + public: + ////////////////////////////////////////////////////////////// + // Target types + ////////////////////////////////////////////////////////////// + static constexpr fapi2::TargetType MC_TARGET_TYPE = fapi2::TARGET_TYPE_OCMB_CHIP; + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + + ////////////////////////////////////////////////////////////// + // Traits values + ////////////////////////////////////////////////////////////// + // MIN_UTIL is in c% + static const uint64_t MIN_UTIL = 2500; + // IDLE_UTIL is in c% + static const uint64_t IDLE_UTIL = 0; + // Minimum throttle allowed for the port and or slot. If we set to 0, we brick the port + static const uint64_t MIN_THROTTLE = 1; + + enum size_of_attrs : size_t + { + // Thermal power (OCMB+DRAM) + SIZE_OF_THERMAL_LIMIT_ATTR = 25, + SIZE_OF_THERMAL_SLOPE_ATTR = 50, + SIZE_OF_THERMAL_INTERCEPT_ATTR = 50, + + // Power (PMIC) + SIZE_OF_CURRENT_CURVE_WITH_LIMIT_ATTR = 25, + }; + + enum default_power + { + //Values are the worst case defaults for power curves + //They are the default/ catch-all values from the power curve attributes + //Shouldn't be used if system is set up correctly and attributes are available + //This will throttle the DIMMs to ~76% dram data bus utilization + //(using the mrw regulator current limit of 100 dA cW and thermal power limit here of 2175 cW). + // Thermal power (OCMB+DRAM) + TOTAL_SLOPE = 0x462, + TOTAL_INT = 0x526, + THERMAL_LIMIT = 0x87F, + + // Power (PMIC) + POWER_SLOPE = 0x152, + POWER_INT = 0x94, + POWER_LIMIT = 0x64, + + }; + + enum + { + PORTS_PER_MC = 1, + DIMMS_PER_PORT = 2, + }; + + //Bit positions for different section of the attribute + //first 32 bits are the encoding, second are for values + enum DECODE_BUFFER_POS + { + ENCODING_START = 0, + ENCODING_LENGTH = 32, + + // Thermal total power (OCMB+DRAM) + THERMAL_START = 32, + THERMAL_LENGTH = 16, + + // Current power (PMIC) + POWER_LIMIT_START = 32, + POWER_LIMIT_LENGTH = 8, + POWER_SLOPE_START = 40, + POWER_SLOPE_LENGTH = 12, + POWER_INTERCEPT_START = 52, + POWER_INTERCEPT_LENGTH = 12, + POWER_LENGTH = 32, + }; + + //Positions and lengths of the encodings + enum ATTR_DECODE_INFO + { + DIMM_SIZE_START = 0, + DIMM_SIZE_LEN = 4, + + DRAM_GEN_START = 4, + DRAM_GEN_LEN = 2, + + DIMM_TYPE_START = 6, + DIMM_TYPE_LEN = 3, + + DRAM_WIDTH_START = 9, + DRAM_WIDTH_LEN = 3, + + DRAM_DENSITY_START = 12, + DRAM_DENSITY_LEN = 3, + + DRAM_STACK_TYPE_START = 15, + DRAM_STACK_TYPE_LEN = 2, + + DRAM_MFGID_START = 17, + DRAM_MFGID_LEN = 3, + + DIMM_MODULE_HEIGHT_START = 20, + DIMM_MODULE_HEIGHT_LEN = 2, + + // Invalid for Explorer but compile will fail without them + DIMMS_PER_PORT_START = 0, + DIMMS_PER_PORT_LEN = 1, + }; + + // Definition is in chip folder + static const std::vector< std::pair<uint8_t , uint8_t> > DIMM_TYPE_MAP; + +}; +}//power_thermal +}// mss + + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H index c55d2d4d5..9051c946a 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_consts.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,9 @@ #ifndef MSS_EXP_CONSTS_H #define MSS_EXP_CONSTS_H -#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#ifndef __PPE__ + #include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#endif namespace mss { @@ -46,10 +48,54 @@ namespace exp constexpr uint32_t OCMB_ADDR_SHIFT = 3; +#ifndef __PPE__ +/// +/// @brief enum list for the indexes for the address delays +/// @note Taken from 07-MAY-19 firwmare document +/// +enum attr_delay_index +{ + ODT1 = 0, + ODT0 = 0, + CS_N0 = 0, + CS_N1 = 0, + ADDR13 = 1, + ADDR5 = 1, + BG0 = 1, + CKE1 = 1, + ADDR17 = 2, + ADDR7 = 2, + BA0 = 2, + ADDR16 = 2, + ADDR8 = 3, + BG1 = 3, + CID1 = 3, + CID0 = 3, + ADDR1 = 4, + ADDR9 = 4, + ADDR2 = 4, + CAPARITY = 4, + ADDR12 = 5, + ADDR3 = 5, + ADDR4 = 5, + ADDR0 = 5, + CKE0 = 6, + ADDR15 = 6, + ACT_N = 6, + ADDR10 = 6, + ADDR11 = 7, + ADDR6 = 7, + BA1 = 7, + ADDR14 = 7, +}; + /// -/// @brief enum list of explorer eff attributes to set +/// @brief enum list of explorer SPD derived attributes to set +/// @note these attrs are strictly derived from SPD +/// @warning wrapped in exp namesapce to be distinguished from +/// the exp::attr_eff_engine_fields /// -enum attr_eff_engine_fields +enum class attr_eff_engine_fields { // Template recursive base case ATTR_EFF_BASE_CASE = 0, @@ -63,11 +109,11 @@ enum attr_eff_engine_fields TSV_8H_SUPPORT = 6, PSTATES = 7, MRAM_SUPPORT = 8, - HEIGHT_3DS = 9, - SPD_CL_SUPPORTED = 10, + SPD_CL_SUPPORTED = 9, + ADDRESS_MIRROR = 10, // Dispatcher set to last enum value - ATTR_EFF_DISPATCHER = SPD_CL_SUPPORTED, + DISPATCHER = ADDRESS_MIRROR, }; /// @@ -75,11 +121,19 @@ enum attr_eff_engine_fields /// enum sizes { + MAX_PORT_PER_OCMB = 1, MAX_DIMM_PER_PORT = 2, MAX_RANK_PER_DIMM = 4, - MAX_BITS_PER_PORT = 80, + MAX_DQ_BITS_PER_PORT = 80, + MAX_SYMBOLS_PER_PORT = 72, + MAX_RANKS_DIMM1 = 2, + MAX_MRANK_PER_PORT = MAX_DIMM_PER_PORT * MAX_RANK_PER_DIMM, + MAX_BYTES_PER_PORT = MAX_DQ_BITS_PER_PORT / BITS_PER_BYTE, + MAX_NIBBLES_PER_PORT = MAX_DQ_BITS_PER_PORT / BITS_PER_NIBBLE, }; +#endif + /// /// @brief explorer ffdc codes /// @@ -92,6 +146,7 @@ enum ffdc_codes READ_CRCT_ENDIAN = 0x0005, READ_TRAINING_RESPONSE_STRUCT = 0x0006, + SET_EXP_DRAM_ADDRESS_MIRRORING = 0x1040, SET_BYTE_ENABLES = 0x1041, SET_NIBBLE_ENABLES = 0x1042, SET_TAA_MIN = 0x1043, @@ -101,8 +156,8 @@ enum ffdc_codes SET_VREF_DQ_TRAIN_RANGE = 0x1047, SET_PSTATES = 0x1048, SET_MRAM_SUPPORT = 0x1049, - SET_3DS_HEIGHT = 0x1050, - SET_SPD_CL_SUPPORTED = 0x1051, + SET_SPD_CL_SUPPORTED = 0x1050, + SET_SERDES_FREQ = 0x1051, }; /// @@ -114,25 +169,70 @@ enum ecid_consts DATA_IN_SIZE = 16, // TK - Will need to be changed once ATTR_ECID is made larger ATTR_ECID_SIZE = 2, - // 32 bit registers with getScom/putScom use the right-most 32 bits - REG_BIT_OFFSET = 32, +}; + +/// +/// @brief constants for getidec procedure +/// +enum idec_consts +{ + EXPLR_CHIP_INFO_REG = 0x2134, + LOCATION_BIT_START = 44, + LOCATION_BIT_LENGTH = 4, + CHIPID_BIT_START = 56, + CHIPID_BIT_LENGTH = 8, + + REVISION_BIT_START = 50, + REVISION_BIT_LENGTH = 4, +}; + + + +/// +/// @brief generic explorer constants +/// +enum generic_consts +{ + // Number of DRAM for x4 vs x8 + EXP_NUM_DRAM_X4 = 20, + EXP_NUM_DRAM_X8 = 10, }; namespace i2c { +/// /// @brief List of explorer I2C commands /// enum cmd_id : uint8_t { - FW_BOOT_CONFIG = 0x01, - FW_STATUS = 0x02, - FW_REG_ADDR_LATCH = 0x03, - FW_REG_READ = 0x04, - FW_REG_WRITE = 0x05, - FW_DOWNLOAD = 0x06, - FW_CONT_REG_READ = 0x07, - FW_CONT_REG_WRITE = 0x08, + FW_BOOT_CONFIG = 0x01, + FW_STATUS = 0x02, + FW_REG_ADDR_LATCH = 0x03, + FW_REG_READ = 0x04, + FW_REG_WRITE = 0x05, + FW_DOWNLOAD = 0x06, + FW_CONT_REG_READ = 0x07, + FW_CONT_REG_WRITE = 0x08, + FW_BYPASS_4SEC_TIMEOUT = 0x09, + FW_PQM_LANE_SET = 0x0A, + FW_PQM_LANE_GET = 0x0B, + FW_PQM_FREQ_SET = 0x0C, + FW_PQM_FREQ_GET = 0x0D, + FW_PQM_LANE_TRAINING = 0x0E, + FW_PQM_TRAINING_RESET = 0x0F, + FW_PQM_RX_ADAPTATION_OBJ_READ = 0x10, + FW_PQM_RX_CALIBRATION_VALUE_READ = 0x11, + FW_PQM_CSU_CALIBRATION_VALUE_STATUS_READ = 0x12, + FW_PQM_PRBS_PATTERN_MODE_SET = 0x13, + FW_PQM_PRBS_USER_DEFINED_PATTERN_SET = 0x14, + FW_PQM_PRBS_MONITOR_CONTROL = 0x15, + FW_PQM_PRBS_GENERATOR_CONTROL = 0x16, + FW_PQM_PRBS_ERR_COUNT_READ = 0x17, + FW_PQM_HORIZONTAL_BATHTUB_GET = 0x18, + FW_PQM_VERTICAL_BATHTUB_GET = 0x19, + FW_PQM_2D_BATHTUB_GET = 0x1A, + EXP_FW_PQM_FORCE_DELAY_LINE_UPDATE = 0x22, }; /// @@ -163,8 +263,10 @@ enum status_codes SUCCESS = 0x00, ADDRESS_OUT_OF_RANGE = 0x01, ADDRESS_PROHIBITED = 0x02, + FW_BUSY = 0xFE, }; +#ifndef __PPE__ /// /// @brief status codes for FW_BOOT_CONFIG /// @@ -182,6 +284,7 @@ enum fw_boot_cfg_status FW_BOOT_CFG_UNSUPPORTED_SERDES_FREQ = 0x04, }; +#endif /// /// @brief I2C boot stage options /// @note certain cmds work in certain boot stages @@ -229,9 +332,9 @@ enum addrSide RHS = 0x01 }; - }// i2c +#ifndef __PPE__ namespace omi { @@ -249,10 +352,10 @@ enum cmd_and_response_id EXP_FW_DDR_PHY_INIT = 0x02, // read temperature sensor - EXP_FW_FW_TEMP_SENSOR_PASS_THROUGH_READ = 0x03, + EXP_FW_TEMP_SENSOR_PASS_THROUGH_READ = 0x03, // configure temperature sensor - EXP_FW_FW_TEMP_SENSOR_PASS_THROUGH_WRITE = 0x04, + EXP_FW_TEMP_SENSOR_PASS_THROUGH_WRITE = 0x04, // configure interval read mechanism EXP_FW_TEMP_SENSOR_CONFIG_INTERVAL_READ = 0x05, @@ -272,8 +375,17 @@ enum cmd_and_response_id // find the flash loader version information EXP_FW_FLASH_LOADER_VERSION_INFO = 0x09, - // read the error logs from various modules of Explorer block - EXP_FW_ERROR_LOG_GET = 0x0A, + // read the FW logs from various modules of Explorer block + EXP_FW_LOG = 0x0A, +}; + +/// +/// @brief Command flag definitions +/// +enum cmd_flags +{ + NO_FLAGS = 0, + ADDITIONAL_DATA = 1, }; /// @@ -286,6 +398,7 @@ enum response_arg }; }// omi +#endif }// exp }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H index 999e93425..d4bfd3387 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/shared/exp_defaults.H @@ -25,7 +25,7 @@ /// /// @file exp_defaults.H -/// @brief default types associated with Nimbus system +/// @brief default types associated with Explorer system /// // *HWP HWP Owner: Andre A. Marin <aamarin@us.ibm.com> // *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> @@ -33,15 +33,18 @@ // *HWP Level: 2 // *HWP Consumed by: CI -#ifndef _MSS_NIMBUS_DEFAULTS_H_ -#define _MSS_NIMBUS_DEFAULTS_H_ +#ifndef _MSS_EXPLORER_DEFAULTS_H_ +#define _MSS_EXPLORER_DEFAULTS_H_ +#include <fapi2.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> namespace mss { constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::EXPLORER; +constexpr fapi2::TargetType DEFAULT_MC_TARGET = fapi2::TARGET_TYPE_OCMB_CHIP; +constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MEM_PORT; } // ns mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C index 9d1393cb4..9803640c0 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/explorer_pos.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,6 @@ namespace mss { /// -/// /// @brief Return a DIMM's relative position from a port /// @param[in] i_target a target representing the target in question /// @return The position relative to chiplet R @@ -90,4 +89,18 @@ relative_pos<fapi2::TARGET_TYPE_MEM_PORT>(const fapi2::Target<fapi2::TARGET_TYPE return 0; } +/// +/// @brief Return a mem_port's relative position from a proc_chip +/// @param[in] i_target a target representing the target in question +/// @return The position relative to chiplet R +/// +template<> +posTraits<fapi2::TARGET_TYPE_MEM_PORT>::pos_type +relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) +{ + typedef mcTypeTraits<mc_type::EXPLORER> TT; + return fapi_pos(i_target) % (TT::PORTS_PER_OCMB * TT::OCMB_PER_OMI * TT::OMI_PER_MCC * TT::MCC_PER_MI * TT::MI_PER_MC * + TT::MC_PER_PROC); +} + }// mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/mss_exp_conversions.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/mss_exp_conversions.H index 85347c950..44df49cde 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/mss_exp_conversions.H +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/utils/mss_exp_conversions.H @@ -22,3 +22,192 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file mss_exp_conversions.H +/// @brief Functions to convert units +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_EXPLORER_CONVERSIONS_H_ +#define _MSS_EXPLORER_CONVERSIONS_H_ + +#include <mss_generic_attribute_getters.H> +#include <generic/memory/lib/utils/conversions.H> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ + +/// +/// @brief Return the number of cycles contained in a count of picoseconds +/// @tparam T the target type from which to get the mt/s +/// @tparam OT the output type, derrived from the parameters +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_ps the number of picoseconds to convert +/// @return uint64_t, the number of cycles +/// +template< fapi2::TargetType T, typename OT > +inline OT ps_to_cycles(const fapi2::Target<T>& i_target, const OT i_ps) +{ + // The frequency in MT/s + uint64_t l_freq = 0; + uint64_t l_clock_period = 0; + + // Each OCMB only has one MEM_PORT + for (const auto l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + FAPI_TRY(attr::get_freq(l_port, l_freq)); + } + + // No time if MT/s is 0 (well, infinite really but shut up) + if (l_freq == 0) + { + return 0; + } + + // Hoping the compiler figures out how to do these together. + FAPI_TRY( freq_to_ps(l_freq, l_clock_period) ); + + return ps_to_cycles( l_clock_period, i_ps ); + +fapi_try_exit: + // We simply can't work if we can't get the frequency or + // if we get an unsupported value that can't be converted to a valid tCK (clock period) + // ...so this should be ok + FAPI_ERR("Can't get MSS_FREQ or obtained an invalid MSS_FREQ (%d) - stopping", l_freq); + fapi2::Assert(false); + + // Keeps compiler happy + return 0; +} + +/// +/// @brief Return the number of ps contained in a count of cycles +/// @tparam T the target type from which to get the mt/s +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_cycles the number of cycles to convert +/// @return uint64_t, the number of picoseconds +/// +template< fapi2::TargetType T > +inline uint64_t cycles_to_ps(const fapi2::Target<T>& i_target, const uint64_t i_cycles) +{ + // The frequency in MHZ + uint64_t l_freq = 0; + uint64_t l_clock_period = 0; + + // Each OCMB only has one MEM_PORT + for (const auto l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + FAPI_TRY(attr::get_freq(l_port, l_freq)); + } + + FAPI_TRY( freq_to_ps(l_freq, l_clock_period) ); + return cycles_to_ps(l_clock_period, i_cycles); + +fapi_try_exit: + + // We simply can't work if we can't get the frequency or + // if we get an unsupported value that can't be converted to a valid tCK (clock period) + // ...so this should be ok + FAPI_ERR("Can't get MSS_FREQ or obtained an invalid MSS_FREQ (%d) - stopping", l_freq); + fapi2::Assert(false); + + // Keeps compiler happy + return 0; +} + +/// +/// @brief Return the number of cycles contained in a count of microseconds +/// @tparam T the target type from which to get the mt/s +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_us the number of microseconds to convert +/// @return uint64_t, the number of cycles +/// +template< fapi2::TargetType T > +inline uint64_t us_to_cycles(const fapi2::Target<T>& i_target, const uint64_t i_us) +{ + return ps_to_cycles(i_target, i_us * CONVERT_PS_IN_A_US); +} + +/// +/// @brief Return the number of cycles contained in a count of nanoseconds +/// @tparam T the target type from which to get the mt/s +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_ps the number of nanoseconds to convert +/// @return uint64_t, the number of cycles +/// +template< fapi2::TargetType T > +inline uint64_t ns_to_cycles(const fapi2::Target<T>& i_target, const uint64_t i_ns) +{ + return ps_to_cycles(i_target, i_ns * CONVERT_PS_IN_A_NS); +} + +/// +/// @brief Return the amount of unit time contained in a count of cycles +/// @tparam T the target type from which to get the mt/s +/// @tparam D the time conversion (NS_IN_PS, etc) +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_cycles the number of cycles to convert +/// @return uint64_t, the number of microseconds +/// +template< uint64_t D, fapi2::TargetType T > +inline uint64_t cycles_to_time(const fapi2::Target<T>& i_target, const uint64_t i_cycles) +{ + // Hoping the compiler figures out how to do these together. + uint64_t l_dividend = cycles_to_ps(i_target, i_cycles); + uint64_t l_quotient = l_dividend / ((D == 0) ? 1 : D); + uint64_t l_remainder = l_dividend % ((D == 0) ? 1 : D); + + // Make sure we add time if there wasn't an even number of cycles + return l_quotient + (l_remainder == 0 ? 0 : 1); +} + +/// +/// @brief Return the number of nanoseconds contained in a count of cycles +/// @tparam T the target type from which to get the mt/s +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_cycles the number of cycles to convert +/// @return uint64_t, the number of nanoseconds +/// +template< fapi2::TargetType T > +inline uint64_t cycles_to_ns(const fapi2::Target<T>& i_target, const uint64_t i_cycles) +{ + uint64_t l_ns = cycles_to_time<CONVERT_PS_IN_A_NS>(i_target, i_cycles); + return l_ns; +} + +/// +/// @brief Return the number of microseconds contained in a count of cycles +/// @tparam T the target type from which to get the mt/s +/// @param[in] i_target target for the frequency attribute +/// @param[in] i_cycles the number of cycles to convert +/// @return uint64_t, the number of microseconds +/// +template< fapi2::TargetType T > +inline uint64_t cycles_to_us(const fapi2::Target<T>& i_target, const uint64_t i_cycles) +{ + uint64_t l_us = cycles_to_time<CONVERT_PS_IN_A_US>(i_target, i_cycles); + return l_us; +} + +/// +/// @brief Return the maximum of two values *in clocks*, the first in clocks the second in ns +/// @tparam T the fapi2::TargetType of a type from which we can get MT/s +/// @param[in] i_target +/// @param[in] i_clocks a value in clocks +/// @param[in] i_time a value in nanoseconds +/// @return max( iclocks nCK, i_time ) in clocks +/// +template< fapi2::TargetType T > +inline uint64_t max_ck_ns(const fapi2::Target<T>& i_target, const uint64_t i_clocks, const uint64_t i_time) +{ + return std::max( i_clocks, ns_to_cycles(i_target, i_time) ); +} + +} // ns mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C new file mode 100644 index 000000000..eae18dd1f --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C @@ -0,0 +1,201 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_omi_workarounds.C +/// @brief Workarounds for exp_omi_* procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: Memory + +#include <fapi2.H> +#include <generic/memory/lib/utils/find.H> +#include <lib/workarounds/exp_omi_workarounds.H> +#include <lib/shared/exp_consts.H> +#include <lib/omi/exp_omi_utils.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_system_attribute_getters.H> +#include <lib/inband/exp_inband.H> +#include <exp_oc_regs.H> + +namespace mss +{ +namespace exp +{ +namespace workarounds +{ +namespace omi +{ + +/// +/// @brief Determine if the OCMB is an explorer +/// +/// @param[in] i_ocmb_chip OCMB chip +/// @param[out] o_explorer true/false is explorer +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note Used for exp_omi_train procedure to differentiate fw_status behavior with gemini +/// +fapi2::ReturnCode ocmb_is_explorer(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_chip, bool& o_explorer) +{ + uint8_t l_name = 0; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, l_name)); + + o_explorer = (l_name == fapi2::ENUM_ATTR_NAME_EXPLORER); + +fapi_try_exit: + return fapi2::current_err; +} +/// +/// @brief Set configurable delay based on the PRBS ATTR and SIM mode +/// +/// @param[in] i_ocmb_chip OCMB target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_chip) +{ + uint8_t l_sim = 0; + uint32_t l_prbs_time = 0; + uint64_t l_prbs_time_scaled = 0; + + FAPI_TRY( mss::attr::get_is_simulation( l_sim) ); + + FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(mss::find_target<fapi2::TARGET_TYPE_OMI>(i_ocmb_chip), l_prbs_time), + "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); + l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; + + FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); + FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", + (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Determine if we need to bypass MENTERP register reads/writes +/// +/// @param[in] i_target OCMB chip +/// @param[out] o_workaround true (1) for gemini, else false (0) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode gem_menterp(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_target, + uint8_t& o_workaround) +{ + o_workaround = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_GEMINI_MENTERP_WORKAROUND, i_target, o_workaround), + "Error getting ATTR_CHIP_EC_FEATURE_GEMINI_MENTERP_WORKAROUND"); + +fapi_try_exit: + return fapi2::current_err; +} + +/// @brief Determine if / perform the gemini workaround to setup the OMI config registers +/// +/// @param[in] i_target OCMB (gemini) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// @note Gemini workaround to setup METADATA and TEMPLATE bits before doing reads +/// +fapi2::ReturnCode gem_setup_config(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + uint8_t l_gemini_config_workaround = 0; + + // Check if gemini workaround should be performed + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_GEMINI_OMI_SETUP_CONFIG_WORKAROUND, i_target, + l_gemini_config_workaround), + "Error getting ATTR_CHIP_EC_FEATURE_GEMINI_OMI_SETUP_CONFIG_WORKAROUND"); + + if (l_gemini_config_workaround) + { + // Set metadata bits + fapi2::buffer<uint32_t> l_value; + l_value.setBit<EXPLR_OC_OCTRLPID_MSB_METADATA_SUPPORTED>(); + l_value.setBit<EXPLR_OC_OCTRLPID_MSB_METADATA_ENABLED>(); + FAPI_TRY(mss::exp::ib::putOCCfg(i_target, EXPLR_OC_OCTRLPID_MSB, l_value)); + + // Set template bits + l_value.flush<0>(); + l_value.setBit<EXPLR_OC_OTTCFG_MSB_TEMPLATE_0>(); + l_value.setBit<EXPLR_OC_OTTCFG_MSB_TEMPLATE_5>(); + FAPI_TRY(mss::exp::ib::putOCCfg(i_target, EXPLR_OC_OTTCFG_MSB, l_value)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Workaround for exp_omi_train to perform dlx_config0 setup +/// +/// @param[in] i_target OCMB chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode training_prbs(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + uint8_t l_dl_x4_backoff_en = 0; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, i_target, l_dl_x4_backoff_en), + "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); + + // Train mode 1 (PATTERN_A) + FAPI_TRY(mss::exp::omi::setup_omi_dl0_config0(i_target, + mss::omi::train_mode::TX_PATTERN_A, + l_dl_x4_backoff_en)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Workaround for exp_omi_setup to perform dlx_config0 setup +/// +/// @param[in] i_target OCMB chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_training_prbs(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + uint8_t l_dl_x4_backoff_en = 0; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, i_target, l_dl_x4_backoff_en), + "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); + + // State 6 + FAPI_TRY(mss::exp::omi::setup_omi_dl0_config0(i_target, + mss::omi::train_mode::TX_TRAINING_STATE3, + l_dl_x4_backoff_en)); + + // Set configurable delay based on the PRBS ATTR and SIM mode + FAPI_TRY(prbs_delay(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // omi +} // workarounds +} // exp +} // mss diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H new file mode 100644 index 000000000..f99eceda5 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H @@ -0,0 +1,106 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/workarounds/exp_omi_workarounds.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file exp_omi_workarounds.H +/// @brief Workarounds for exp_omi_* procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: Memory + +#ifndef _EXP_OMI_WORKAROUNDS_H_ +#define _EXP_OMI_WORKAROUNDS_H_ + +#include <fapi2.H> + +namespace mss +{ +namespace exp +{ +namespace workarounds +{ +namespace omi +{ + +/// +/// @brief Determine if the OCMB is an explorer +/// +/// @param[in] i_ocmb_chip OCMB chip +/// @param[out] o_explorer true/false is explorer +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// @note Used for exp_omi_train procedure to differentiate fw_status behavior with gemini +/// +fapi2::ReturnCode ocmb_is_explorer(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_chip, bool& o_explorer); + +/// +/// @brief Set configurable delay based on the PRBS ATTR and SIM mode +/// +/// @param[in] i_ocmb_chip OCMB target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_ocmb_chip); + +/// +/// @brief Determine if we need to bypass MENTERP register reads/writes +/// +/// @param[in] i_target OCMB chip +/// @param[out] o_workaround true (1) for gemini, else false (0) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode gem_menterp(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_target, + uint8_t& o_workaround); + +/// @brief Determine if / perform the gemini workaround to setup the OMI config registers +/// +/// @param[in] i_target OCMB (gemini) +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error +/// +fapi2::ReturnCode gem_setup_config(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +/// +/// @brief Workaround for exp_omi_train to perform dlx_config0 setup +/// +/// @param[in] i_target OCMB chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode training_prbs(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +/// +/// @brief Workaround for exp_omi_setup to perform dlx_config0 setup +/// +/// @param[in] i_target OCMB chip +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_training_prbs(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +} // omi +} // workarounds +} // exp +} // mss + +#endif diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml index e19cfe5be..61ff45e98 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -29,7 +29,6 @@ <!-- --> <!-- *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> --> <!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> --> -<!-- *HWP FW Owner: Bill Hoffa <wghoffa@us.ibm.com> --> <!-- *HWP Team: Memory --> <!-- *HWP Level: 2 --> <!-- *HWP Consumed by: FSP:HB --> @@ -56,6 +55,31 @@ </attribute> <attribute> + <id>ATTR_MSS_OCMB_ENTERPRISE_POLICY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Indicates whether the OCMB is allowed to run in enterprise + mode, commodity mode, or either. + + ALLOW_ENTERPRISE = Most permissive, uses whatever is installed in + the way it is intended to be used. + REQUIRE_ENTERPRISE = Throws an error for any commodity dimms that + are installed. + FORCE_NONENTERPRISE = Throws an error for any enterprise dimms that + are installed. + </description> + <valueType>uint8</valueType> + <enum> + ALLOW_ENTERPRISE = 0, + REQUIRE_ENTERPRISE = 1, + FORCE_NONENTERPRISE = 2 + </enum> + <platInit/> + <default>ALLOW_ENTERPRISE</default> + <mssAccessorName>ocmb_enterprise_policy</mssAccessorName> + </attribute> + + <attribute> <id>ATTR_MSS_OCMB_NONENTERPRISE_MODE_OVERRIDE</id> <targetType>TARGET_TYPE_OCMB_CHIP</targetType> <description> @@ -77,7 +101,6 @@ <targetType>TARGET_TYPE_OCMB_CHIP</targetType> <description> Indicates whether the OCMB should be run in half DIMM mode or not - Note: needs to be setup by the get ECID functionality </description> <initToZero></initToZero> <valueType>uint8</valueType> @@ -85,7 +108,7 @@ FULL_DIMM = 0, HALF_DIMM = 1 </enum> - <writeable/> + <platInit/> <mssAccessorName>ocmb_half_dimm_mode</mssAccessorName> </attribute> @@ -122,18 +145,6 @@ <!-- user_input_msdg attribute overrides start --> <attribute> - <id>ATTR_MEM_EXP_CS_PRESENT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Indicate presence of DRAM at each Chip Select for PHY - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <writeable/> - <mssAccessorName>exp_cs_present</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_EXP_INIT_VREF_DQ</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> @@ -142,6 +153,7 @@ <valueType>uint8</valueType> <initToZero></initToZero> <writeable/> + <array>2 4</array> <mssAccessorName>exp_init_vref_dq</mssAccessorName> </attribute> @@ -151,9 +163,10 @@ <description> Initial DQ Vref setting of PHY before training </description> - <valueType>uint16</valueType> + <valueType>uint8</valueType> <initToZero></initToZero> <writeable/> + <array>2 4</array> <mssAccessorName>exp_init_phy_vref</mssAccessorName> </attribute> @@ -209,19 +222,6 @@ </attribute> <attribute> - <id>ATTR_MEM_EXP_3DS_HEIGHT</id> - <targetType>TARGET_TYPE_MEM_PORT</targetType> - <description> - Explorer setting for 3DS stack - </description> - <initToZero></initToZero> - <valueType>uint16</valueType> - <enum>PLANAR = 0, H2 = 2, H4 = 4, H8 = 8</enum> - <writeable/> - <mssAccessorName>exp_3ds_height</mssAccessorName> - </attribute> - - <attribute> <id>ATTR_MEM_EXP_SPD_CL_SUPPORTED</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> <description> @@ -246,6 +246,21 @@ <mssAccessorName>exp_spd_taa_min</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MSS_EXP_REORDER_QUEUE_SETTING</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Contains the settings for write/read reorder queue + </description> + <default>REORDER</default> + <initToZero></initToZero> + <writeable/> + <enum>REORDER = 0, FIFO = 1</enum> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>exp_reorder_queue_setting</mssAccessorName> + </attribute> + <attribute> <id>ATTR_MEM_EXP_FIRMWARE_EMULATION_MODE</id> <targetType>TARGET_TYPE_MEM_PORT</targetType> @@ -274,7 +289,7 @@ SWAP = 0, NO_SWAP = 1 </enum> - <writeable/> + <platInit/> </attribute> <attribute> @@ -291,7 +306,40 @@ BIG_ENDIAN = 0, LITTLE_ENDIAN = 1 </enum> - <writeable/> + <platInit/> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_EXP_STRUCT_MMIO_WORD_SWAP</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Controls whether or not the first and second half of MMIO + transactions are swapped before and after mmio accesses to + the buffer. + </description> + <valueType>uint8</valueType> + <enum> + SWAP = 0, + NO_SWAP = 1 + </enum> + <platInit/> + <default>NO_SWAP</default> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_EXP_OMI_CFG_ENDIAN_CTRL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Controls whether OMI CFG reg accesses + are considered big or little endian. + </description> + <valueType>uint8</valueType> + <enum> + LITTLE_ENDIAN = 0, + BIG_ENDIAN = 1 + </enum> + <platInit/> + <default>LITTLE_ENDIAN</default> </attribute> <attribute> @@ -307,4 +355,172 @@ <mssAccessorName>ocmb_ecid</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MEM_EXP_DFIMRL_CLK</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + timing parameter for the DFIMRL clock + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <mssAccessorName>exp_dfimrl_clk</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_ATXDLY_A</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[ADDRESS INDEX] + ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] + ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] + ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] + ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] + ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY + ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] + ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] + ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>8</array> + <mssAccessorName>exp_atxdly_a</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MEM_EFF_ATXDLY_B</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + ARRAY[ADDRESS INDEX] + ATxDly_A/B[0]: ODT[1],ODT[0],CS_N[0],CS_N[1] + ATxDly_A/B[1]: ADDR[13],ADDR[5],BG[0],CKE[1] + ATxDly_A/B[2]: ADDR[17],ADDR[7],BA[0],ADDR[16] + ATxDly_A/B[3]: ADDR[8],BG[1],CID[1],CID[0] + ATxDly_A/B[4]: ADDR[1],ADDR[9],ADDR[2],CAPARITY + ATxDly_A/B[5]: ADDR[12],ADDR[3],ADDR[4],ADDR[0] + ATxDly_A/B[6]: CKE[0],ADDR[15],ACT_N,ADDR[10] + ATxDly_A/B[7]: ADDR[11],ADDR[6],BA[1],ADDR[14] + </description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <array>8</array> + <mssAccessorName>exp_atxdly_b</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_PHY_INIT_MODE</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Mode for PHY initialization. + </description> + <valueType>uint8</valueType> + <initToZero></initToZero> + <enum> + NORMAL = 0, + WITH_EYE_CAPTURE = 1 + </enum> + <writeable/> + <mssAccessorName>exp_phy_init_mode</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The obj_handle value to send on ocmb checkstop + </description> + <valueType>uint64</valueType> + <default>0x0</default> + <platInit/> + <mrwHide/> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_RECOV_OBJ_HANDLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The obj_handle value to send on ocmb recoverable errors + </description> + <valueType>uint64</valueType> + <default>0x1</default> + <platInit/> + <mrwHide/> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The obj_handle value to send on ocmb special attention + </description> + <valueType>uint64</valueType> + <default>0x2</default> + <platInit/> + <mrwHide/> + </attribute> + + <attribute> + <id>ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The obj_handle value to send on ocmb application interrupt + </description> + <valueType>uint64</valueType> + <default>0x3</default> + <platInit/> + <mrwHide/> + </attribute> + + <attribute> + <id>ATTR_MSS_CHECK_FOR_READY_TIMEOUT</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Timeout (in msec) for polling for FW_STATUS reply during + exp_check_for_ready. Default is 400msec, from lab experimentation + </description> + <valueType>uint16</valueType> + <default>400</default> + <platInit/> + <mrwHide/> + <mssAccessorName>check_for_ready_timeout</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MSS_POST_MEMDIAGS_READ_SUBTEST</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Whether to run post-memdiags read-only subtest + </description> + <valueType>uint8</valueType> + <enum> + DISABLE = 0, + ENABLE = 1 + </enum> + <default>ENABLE</default> + <platInit/> + <overrideOnly/> + <mssAccessorName>post_memdiags_read_subtest</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_MSS_POST_MEMDIAGS_READ_SUBTEST_FAIL_BEHAVIOR</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Behvaior to perform if read subtest post-memdiags does not get a good result. + EXIT = fapi_try_exit out with error code + TRACE = FAPI_ERR that test failed, return success code + </description> + <valueType>uint8</valueType> + <enum> + EXIT = 0, + TRACE = 1 + </enum> + <default>EXIT</default> + <platInit/> + <overrideOnly/> + <mssAccessorName>post_memdiags_read_subtest_fail_behavior</mssAccessorName> + </attribute> + </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml index e8880095e..75b9f968b 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_omi_train.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -44,10 +44,12 @@ <valueType>uint8</valueType> <enum> NORMAL_MODE = 0, - MANUFACTURING_MODE = 1 + MANUFACTURING_MODE = 1, + PRODUCT_QUALIFICATION_MODE = 2 </enum> <initToZero/> - <writeable/> + <platInit/> + <overrideOnly/> <mssAccessorName>ocmb_exp_boot_config_fw_mode</mssAccessorName> </attribute> @@ -63,7 +65,8 @@ PERFORM_LOOPBACK_TESTING = 1 </enum> <initToZero/> - <writeable/> + <platInit/> + <overrideOnly/> <mssAccessorName>ocmb_exp_boot_config_opencapi_loopback_test</mssAccessorName> </attribute> @@ -80,7 +83,8 @@ JTAG = 2 </enum> <initToZero/> - <writeable/> + <platInit/> + <overrideOnly/> <mssAccessorName>ocmb_exp_boot_config_transport_layer</mssAccessorName> </attribute> @@ -93,28 +97,30 @@ </description> <valueType>uint8</valueType> <enum> - BOOT_RIGHT_AFTER_CONFIG = 0, - WAIT_FOR_HOST_CMD = 1 + NON_DL_TRAINING = 0, + ONLY_DL_TRAINING = 1 </enum> + <platInit/> <initToZero/> - <writeable/> + <overrideOnly/> <mssAccessorName>ocmb_exp_boot_config_dl_layer_boot_mode</mssAccessorName> </attribute> <attribute> - <id>ATTR_MSS_OCMB_EXP_BOOT_CONFIG_BOOT_MODE</id> + <id>ATTR_MSS_OCMB_EXP_BOOT_CONFIG_DFE_DISABLE</id> <targetType>TARGET_TYPE_OCMB_CHIP</targetType> <description> - Indicates the full boot or step-by-step boot + Set to enable or disable DFE </description> <valueType>uint8</valueType> <enum> - FULL_BOOT = 0, - STEP_BY_STEP_BOOT = 1 + DISABLE = 0, + ENABLE = 1 </enum> - <initToZero/> - <writeable/> - <mssAccessorName>ocmb_exp_boot_config_boot_mode</mssAccessorName> + <default>ENABLE</default> + <platInit/> + <overrideOnly/> + <mssAccessorName>ocmb_exp_boot_config_dfe_disable</mssAccessorName> </attribute> <attribute> @@ -130,7 +136,6 @@ </enum> <default>1</default> <platInit/> - <writeable/> <mssAccessorName>ocmb_exp_boot_config_lane_mode</mssAccessorName> </attribute> @@ -148,8 +153,22 @@ </enum> <default>3</default> <platInit/> - <writeable/> <mssAccessorName>ocmb_exp_boot_config_serdes_frequency</mssAccessorName> </attribute> + <attribute> + <id>ATTR_MSS_OCMB_EXP_BOOT_CONFIG_ADAPTATION_MODE</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Indicates whether to enable adaptation + </description> + <valueType>uint8</valueType> + <enum> + DISABLE = 0, + ENABLE = 1 + </enum> + <default>ENABLE</default> + <platInit/> + <mssAccessorName>ocmb_exp_boot_config_adaptation_mode</mssAccessorName> + </attribute> </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_power_thermal.xml b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_power_thermal.xml index eaa83be48..8b50d2594 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_power_thermal.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/attribute_info/exp_power_thermal.xml @@ -23,4 +23,168 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> + <attribute> + <id>ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + This is the throttled N commands per window + of M DRAM clocks setting for cfg_nm_n_per_port. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssAccessorName>mem_throttled_n_commands_per_port</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>This is the throttle numerator setting for cfg_nm_n_per_slot</description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssAccessorName>mem_throttled_n_commands_per_slot</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Runtime throttled N commands per + M DRAM clocks setting for cfg_nm_n_per_port. + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssAccessorName>runtime_mem_throttled_n_commands_per_port</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Runtime throttle numerator setting for cfg_nm_n_per_slot</description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <mssAccessorName>runtime_mem_throttled_n_commands_per_slot</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Safe mode throttle value for numerator cfg_nm_n_per_port + Set to below optimum value/ rate. + On a per port basis + Also used for emergency mode throttle MBA_FARB4Q_EMERGENCY_N + Used to thermally protect the system in all supported environmental conditions when OCC is not functional + </description> + <valueType>uint16</valueType> + <default>32</default> + <platInit/> + <initToZero/> + <mssAccessorName>safemode_mem_throttled_n_commands_per_port</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_RUNTIME_MEM_M_DRAM_CLOCKS</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Runtime for M DRAM clocks setting for cfg_nm_m</description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_EXP_MEM_PORT_POS_OF_FAIL_THROTTLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + This is the fapi position of the port that failed to calculate + memory throttles given the passed in watt target and or utilization + </description> + <initToZero></initToZero> + <valueType>uint64</valueType> + <writeable/> + </attribute> + + <attribute> + <id>ATTR_EXP_MEM_WATT_TARGET</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Total memory power used to throttle for each dimm + Used to compute the throttles on the channel and/or dimms for OCC + OCC sets after IPL + </description> + <initToZero></initToZero> + <mssUnit>cW</mssUnit> + <valueType>uint32</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>mem_watt_target</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_TOTAL_PWR_SLOPE</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + VDDR+VPP Power slope value for dimm + creator: mss_eff_config + consumer: mss_bulk_pwr_throttles + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>total_pwr_slope</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_TOTAL_PWR_INTERCEPT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + VDDR+VPP Power intercept value for dimm + </description> + <initToZero></initToZero> + <valueType>uint16</valueType> + <writeable/> + <array>2</array> + <mssAccessorName>total_pwr_intercept</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_DATABUS_UTIL</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + Databus utilization per port limit used to calculate memory throttles and power limit + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssAccessorName>databus_util</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_PORT_MAXPOWER</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description>Channel Pair Max Power output from thermal procedures</description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssAccessorName>port_maxpower</mssAccessorName> + </attribute> + + <attribute> + <id>ATTR_EXP_DIMM_THERMAL_LIMIT</id> + <targetType>TARGET_TYPE_MEM_PORT</targetType> + <description> + DIMM Max Power based on a thermal limit + Decoded from ATTR_MSS_MRW_THERMAL_POWER_LIMIT + </description> + <initToZero></initToZero> + <valueType>uint32</valueType> + <writeable/> + <mssUnit>cW</mssUnit> + <array>2</array> + <mssAccessorName>dimm_thermal_limit</mssAccessorName> + </attribute> </attributes> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_collect_explorer_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_collect_explorer_errors.xml new file mode 100644 index 000000000..d605771eb --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_collect_explorer_errors.xml @@ -0,0 +1,49 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_collect_explorer_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_COLLECT_EXPLORER_ERROR</rc> + <description>Collects error log data from Explorer chip</description> + <collectFfdc>exp_collect_explorer_active_log, OCMB_CHIP_TARGET, EXP_ACTIVE_LOG_SIZE</collectFfdc> + <collectFfdc>exp_collect_explorer_saved_log, OCMB_CHIP_TARGET, EXP_SAVED_LOG_SIZE</collectFfdc> + <ffdc>OCMB_CHIP_TARGET</ffdc> + <ffdc>EXP_ACTIVE_LOG_SIZE</ffdc> + <ffdc>EXP_SAVED_LOG_SIZE</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_EXPLORER_ACTIVE_ERROR_LOG</rc> + <description>Collect active explorer errors during exp_collect_explorer_active_log</description> + <ffdc>UNIT_FFDC_EXP_ERROR</ffdc> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_EXPLORER_SAVED_ERROR_LOG</rc> + <description>Collect saved explorer errors during exp_collect_explorer_saved_log</description> + <ffdc>UNIT_FFDC_EXP_ERROR</ffdc> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_fw_update_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_fw_update_errors.xml new file mode 100644 index 000000000..dffdca189 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_fw_update_errors.xml @@ -0,0 +1,154 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_fw_update_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + + <hwpError> + <rc>RC_EXP_UPDATE_INVALID_IMAGE_SIZE</rc> + <description> + Explorer firmware image must be less than 16MB + </description> + <ffdc>IMAGE_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_UPDATE_CMD_FAILED</rc> + <description> + The response_argument field of the host_fw_response_struct returned a FAILURE + </description> + <ffdc>RSP_ID</ffdc> + <ffdc>REQ_ID</ffdc> + <ffdc>ERROR_CODE</ffdc> + <ffdc>RSP_DATA</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_EXP_TWI_INVALID_STATUS_ID</rc> + <description> + The status_id field of the TWI status was invalid + </description> + <ffdc>TARGET</ffdc> + <ffdc>STATUS_ID</ffdc> + <ffdc>STATUS_WORD32</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_EXP_TWI_UNEXPECTED_STATUS</rc> + <description> + Received unexpected TWI status + </description> + <ffdc>TARGET</ffdc> + <ffdc>EXPECTED_STATUS</ffdc> + <ffdc>STATUS</ffdc> + <ffdc>STATUS_WORD32</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_EXP_TWI_UNEXPECTED_WRITE_OFFSET</rc> + <description> + Received unexpected TWI write offset + </description> + <ffdc>TARGET</ffdc> + <ffdc>EXPECTED_OFFSET</ffdc> + <ffdc>WRITE_OFFSET</ffdc> + <ffdc>STATUS_WORD32</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_EXP_TWI_INVALID_IMAGE_SIZE</rc> + <description> + Explorer TWI firmware image must be less than 256KB + </description> + <ffdc>TARGET</ffdc> + <ffdc>MAX_SIZE</ffdc> + <ffdc>ACTUAL_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_I2C_FW_DOWNLOAD_INVALID_STATE</rc> + <description> + Must be in BOOT_ROM or FW_UPGRADE boot stage to issue FW_DOWNLOAD command + </description> + <ffdc>TARGET</ffdc> + <ffdc>BOOT_STAGE</ffdc> + <ffdc>STATUS_DATA</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + +</hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_pmic_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_getidec.xml index 8e1ede29e..f5060138c 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_pmic_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_getidec.xml @@ -1,11 +1,11 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_pmic_errors.xml $ --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_getidec.xml $ --> <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -22,5 +22,29 @@ <!-- permissions and limitations under the License. --> <!-- --> <!-- IBM_PROLOG_END_TAG --> + <hwpErrors> + + <hwpError> + <rc>RC_EXP_UNKNOWN_REVISION</rc> + <description> + The Explorer revision does not match a known DD level. + </description> + <ffdc>TARGET</ffdc> + <ffdc>REVISION</ffdc> + <ffdc>CHIP_INFO_REG</ffdc> + <ffdc>EFUSE_IMAGE_OUT_3</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>MEDIUM</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml index f69b3dd8e..1a337a57f 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_inband_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -70,4 +70,18 @@ </callout> </hwpError> + <hwpError> + <rc>RC_EXP_INBAND_RSP_NO_DOORBELL</rc> + <description> + Doorbell is low when expecting a response + </description> + <ffdc>DATA</ffdc> + <ffdc>NUM_LOOPS</ffdc> + <ffdc>OCMB_TARGET</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_init_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_init_errors.xml index 7654fe832..eba974e3b 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_init_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -83,4 +83,16 @@ <ffdc>A</ffdc> </hwpError> <!-- ******************************************************************** --> + <hwpError> + <rc>RC_METADATA_ENABLE_REQUIRES_TEMPLATE_5_OR_9</rc> + <description> + Procedure: exp_omi_init.C + Upstream template 5 or 9 need to be enabled for + metadata enable. + </description> + <ffdc>TARGET</ffdc> + <ffdc>TMPL_5</ffdc> + <ffdc>TMPL_9</ffdc> + </hwpError> + <!-- ******************************************************************** --> </hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_train_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_train_errors.xml new file mode 100644 index 000000000..9b735dd02 --- /dev/null +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_train_errors.xml @@ -0,0 +1,55 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/ocmb/explorer/procedures/xml/error_info/exp_omi_train_errors.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_EXP_OMI_TRAIN_ERR</rc> + <description> + exp_omi_train_check did not see expected trained status from OCMB DL0 status register + </description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>EXPECTED_SM_STATE</ffdc> + <ffdc>ACTUAL_SM_STATE</ffdc> + <ffdc>DL0_STATUS</ffdc> + <ffdc>DL0_TRAINING_STATUS</ffdc> + <ffdc>DL0_CONFIG1</ffdc> + <ffdc>OMI_FREQ</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <bus>OMI_TARGET, OCMB_TARGET</bus> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + <gard> + <target>OCMB_TARGET</target> + </gard> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml index d2b864abf..702c0aef1 100644 --- a/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml +++ b/src/import/chips/ocmb/explorer/procedures/xml/error_info/mss_exp_errors.xml @@ -24,6 +24,260 @@ <!-- IBM_PROLOG_END_TAG --> <hwpErrors> + <registerFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <scomRegister>EXPLR_MCBIST_MCBMR0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBCFGQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCB_CNTLQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCB_CNTLSTATQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBSTATQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBMCATQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBPARMQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBAGRAQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MBSEC1Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MBSTRQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBISTFIRQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBAMR0A0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBAMR1A0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBAMR2A0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBAMR3A0Q</scomRegister> + + <scomRegister>EXPLR_MCBIST_MCBFD0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD1Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD2Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD3Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD4Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD5Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD6Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBFD7Q</scomRegister> + + <scomRegister>EXPLR_MCBIST_MCBSA0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBSA1Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBSA2Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBSA3Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBEA0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBEA1Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBEA2Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBEA3Q</scomRegister> + </registerFfdc> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN</rc> + <description>A miscompare error was caused by the last MCBIST pattern</description> + <ffdc>PORT</ffdc> + <ffdc>SUBTEST</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_ERROR_IN_LAST_PATTERN</rc> + <description>An error was caused by the last MCBIST pattern</description> + <ffdc>STATUS0</ffdc> + <ffdc>STATUS1</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_MCBIST_FAILED_TO_START</rc> + <description>The MCBIST engine failed to start its program</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_PORT_NOT_FUNCTIONAL</rc> + <description>The port used in an MCBIST program is not functional</description> + <ffdc>RELATIVE_PORT_POSITION</ffdc> + <ffdc>ADDRESS</ffdc> + <ffdc>MC_TARGET</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT</rc> + <description>A superfast init operation failed initialization</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT</rc> + <description>A superfast read operation failed initialization</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_MCBIST_FAILED_TO_STOP</rc> + <description>The MCBIST engine failed to stop its program</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <ffdc>POLL_COUNT</ffdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT</rc> + <description>A continuous scrub operation failed initialization</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT</rc> + <description>A continuous scrub operation failed initialization</description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MEMDIAGS_ALREADY_AT_BOUNDARY</rc> + <description>A continue request asked to stop at a boundary, but we are there already</description> + <ffdc>MC_TARGET</ffdc> + <ffdc>BOUNDARY</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_MCBIST_TIMEOUT</rc> + <description> + MCBIST program failed to return in the time allowed + Software timer, MCBIST has not finished in the time allowed + </description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_EXP_MCBIST_DATA_FAIL</rc> + <description> + MCBIST program appeared to have failed, but set conflicting bits in the status register + </description> + <ffdc>STATUS_REGISTER</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_EXP_MCBIST_UNKNOWN_FAILURE</rc> + <description>MCBIST program reported a failure but no error status was found</description> + <ffdc>STATUS_REGISTER</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + <hwpError> <rc>RC_MSS_EXP_DRAMINIT_BAD_NUM_RANKS</rc> <description>Bad number of ranks were passed in the bad bits functionality</description> @@ -82,6 +336,39 @@ </hwpError> <hwpError> + <rc>RC_MSS_EXP_HALF_DIMM_MODE_NOT_SUPPORTED</rc> + <description> + The enterprise settings do not support half dimm mode. + </description> + <ffdc>ENTERPRISE_SETTING</ffdc> + <ffdc>HALF_DIMM_SETTING</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_ENTERPRISE_INVALID_CONFIGURATION</rc> + <description> + The enterprise supported bit from explorer fuse + conflicts with the enterprise policy setting. + </description> + <ffdc>ENTERPRISE_SUPPORTED</ffdc> + <ffdc>POLICY</ffdc> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> <rc>RC_MSS_EXP_ENTERPRISE_SETUP_ERROR</rc> <description>The enterprise mode bit is in the incorrect state</description> <ffdc>EXPECTED</ffdc> @@ -102,6 +389,29 @@ Explorer status code for command ID EXP_FW_STATUS did not return SUCCESS </description> + <ffdc>TARGET</ffdc> + <ffdc>STATUS_CODE</ffdc> + <ffdc>CMD_ID</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_I2C_FW_BOOT_CONFIG_STATUS_CODE_INVALID</rc> + <description> + Unexpected Explorer status code returned during OMI link training pattern handshake. + Expected FW_BUSY, but received STATUS_CODE in FFDC data + </description> + <ffdc>TARGET</ffdc> <ffdc>STATUS_CODE</ffdc> <ffdc>CMD_ID</ffdc> <callout> @@ -118,6 +428,49 @@ </hwpError> <hwpError> + <rc>RC_MSS_EXP_I2C_FW_STATUS_BUSY</rc> + <description> + Received FW_BUSY status after polling timeout for + command ID EXP_FW_STATUS + </description> + <ffdc>TARGET</ffdc> + <ffdc>STATUS_CODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_I2C_WRONG_BOOT_STAGE</rc> + <description> + Received incorrect boot stage from + command ID EXP_FW_STATUS + </description> + <ffdc>TARGET</ffdc> + <ffdc>BOOT_STAGE</ffdc> + <ffdc>EXPECTED_BOOT_STAGE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <hwpError> <rc>RC_MSS_EXP_I2C_POLLING_TIMEOUT</rc> <description> Polling the explorer I2C slave interface for an ACK @@ -162,6 +515,8 @@ </description> <ffdc>RSP_ID</ffdc> <ffdc>ERROR_CODE</ffdc> + <ffdc>EXPECTED_REQID</ffdc> + <ffdc>ACTUAL_REQID</ffdc> <callout> <procedure>CODE</procedure> <priority>MEDIUM</priority> @@ -175,4 +530,242 @@ </deconfigure> </hwpError> + <hwpError> + <rc>RC_MSS_EXP_SENSOR_CACHE_ENABLE_FAILED</rc> + <description> + The response_argument field of the host_fw_response_struct returned + a FAILURE for enabling sensor cache + </description> + <ffdc>RSP_ID</ffdc> + <ffdc>ERROR_CODE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>TARGET</target> + </deconfigure> + </hwpError> + + <registerFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <scomRegister>EXPLR_MCBIST_CCS_MODEQ</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_STATQ</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_CNTLQ</scomRegister> + <scomRegister>EXPLR_MCBIST_MCBMCATQ</scomRegister> + + <!-- Instructions --> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_00</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_01</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_02</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_03</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_04</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_05</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_06</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_07</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_08</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_09</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_10</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_11</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_12</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_13</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_14</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_15</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_16</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_17</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_18</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_19</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_20</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_21</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_22</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_23</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_24</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_25</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_26</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_27</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_28</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_29</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_30</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR0_31</scomRegister> + + <!-- Control array --> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_00</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_01</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_02</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_03</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_04</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_05</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_06</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_07</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_08</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_09</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_10</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_11</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_12</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_13</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_14</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_15</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_16</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_17</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_18</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_19</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_20</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_21</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_22</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_23</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_24</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_25</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_26</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_27</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_28</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_29</scomRegister> + + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_30</scomRegister> + <scomRegister>EXPLR_MCBIST_CCS_INST_ARR1_31</scomRegister> + + <!-- to get the CCS state machine hung state --> + <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT0Q</scomRegister> + <scomRegister>EXPLR_MCBIST_MBA_MCBERRPT1Q</scomRegister> + </registerFfdc> + + <hwpError> + <rc>RC_MSS_EXP_CCS_READ_MISCOMPARE</rc> + <description> + CCS reports a read miscompare. + </description> + <ffdc>FAIL_TYPE</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>PORT_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>PORT_TARGET</target> + </deconfigure> + <gard> + <target>PORT_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_CCS_UE_SUE</rc> + <description> + CCS reports a UE or SUE in the CCS program array + Chould be an indicator of corruption in the CCS program + </description> + <ffdc>FAIL_TYPE</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_CCS_HUNG</rc> + <description> + Software reported that the machine is not seeing the CCS finish in the alloted time + </description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_EXP_CCS_HUNG_TRYING_TO_STOP</rc> + <description> + CCS failed to return from in-progress status while trying to stop a previous program + Software reported that CCS did not finish in alloted time after manually triggering stop + </description> + <collectRegisterFfdc> + <id>REG_FFDC_EXP_CCS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + </collectRegisterFfdc> + <callout> + <target>MC_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_UNKNOWN_PHY_INIT_MODE</rc> + <description> + The PHY init mode value was an unknown value. + </description> + <ffdc>TARGET</ffdc> + <ffdc>VALUE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_EXP_INVALID_PHY_INIT_RSP_DATA_LENGTH</rc> + <description> + The data buffer vector retrieved from the EXP_FW_DDR_PHY_INIT response did not match the expected length + </description> + <ffdc>OCMB_TARGET</ffdc> + <ffdc>PHY_INIT_MODE</ffdc> + <ffdc>EXPECTED_LENGTH</ffdc> + <ffdc>ACTUAL_LENGTH</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <callout> + <target>OCMB_TARGET</target> + <priority>HIGH</priority> + </callout> + <deconfigure> + <target>OCMB_TARGET</target> + </deconfigure> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.C b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.C index 548ee2de6..275ae67c6 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.C +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.C @@ -22,3 +22,39 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file gem_draminit.C +/// @brief Procedure definition to initialize DRAM +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/gem_draminit_utils.H> +#include <generic/memory/mss_git_data_helper.H> + +extern "C" +{ + /// + /// @brief Initializes DRAM + /// @param[in] i_target the OCMB chip (Gemini) + /// @return FAPI2_RC_SUCCESS iff ok, else fapi2::current_err + /// + fapi2::ReturnCode gem_draminit(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) + { + mss::display_git_commit_info("gem_draminit"); + + FAPI_TRY(mss::gem::poll_check_calibration(i_target)); + FAPI_TRY(mss::gem::init_memory(i_target)); + + return fapi2::FAPI2_RC_SUCCESS; + + fapi_try_exit: + return fapi2::current_err; + } + +} // extern "C" diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.H b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.H index 61da5bde8..bfe86b631 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.H +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.H @@ -22,3 +22,34 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file gem_draminit.H +/// @brief Procedure definition to initialize DRAM +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_GEM_DRAMINIT__ +#define __MSS_GEM_DRAMINIT__ + +#include <fapi2.H> + +// Required for Cronus +typedef fapi2::ReturnCode (*gem_draminit_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ + +/// +/// @brief Initializes DRAM +/// @param[in] i_target the controller +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode gem_draminit(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +}// extern C +#endif diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.mk b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.mk index 84a97f3ab..ea64e2617 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.mk +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_draminit.mk @@ -22,3 +22,10 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG + +# Include the macros and things for MSS GEMINI procedures +-include 00gem_common.mk + +PROCEDURE=gem_draminit +$(eval $(call ADD_GEM_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.C b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.C index 8deac2c76..dc92bb1ab 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.C +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.C @@ -22,3 +22,44 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +#include <fapi2.H> +#include <gem_getecid.H> +#include <mss_explorer_attribute_setters.H> +#include <generic/memory/mss_git_data_helper.H> + +extern "C" +{ + + /// + /// @brief Gets gemini ECID + /// @param[in] i_target the controller + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode gem_getecid(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) + { + mss::display_git_commit_info("gem_getecid"); + + // Address defined here as gemini SCOM address library does not exist + static constexpr uint64_t GEMINI_ECID_REGISTER = 0x0801240E; + fapi2::buffer<uint64_t> l_data_buffer; + + FAPI_TRY(fapi2::getScom(i_target, GEMINI_ECID_REGISTER, l_data_buffer), + "Failed getScom() for %s", mss::spd::c_str(i_target)); + + { + // Set ATTR_ECID + // TK - Update once ATTR_ECID array size is updated to be larger than 2 + static constexpr uint32_t ECID_ARRAY_SIZE = 2; + uint64_t l_attr_ecid[ECID_ARRAY_SIZE] = {l_data_buffer, 0}; + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_ECID, i_target, l_attr_ecid), + "exp_getecid: Could not set ATTR_ECID on %s", mss::c_str(i_target) ); + } + + // omi_setup not used by GEMINI, so not setting ocmb enterprise mode and half-dimm mode attributes + + fapi_try_exit: + return fapi2::current_err; + } +} // extern "C" diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.H b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.H index 20b8d4bb6..3ee0d7403 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.H +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.H @@ -22,3 +22,24 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +#ifndef __MSS_GEM_GETECID__ +#define __MSS_GEM_GETECID__ + +#include <fapi2.H> + +// Required for Cronus +typedef fapi2::ReturnCode (*gem_getecid_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>&); + +extern "C" +{ + +/// +/// @brief Gets gemini ECID +/// @param[in] i_target the controller +/// @return FAPI2_RC_SUCCESS iff ok +/// + fapi2::ReturnCode gem_getecid(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +}// extern C +#endif diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.mk b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.mk index 339fd149e..efd3e49a3 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.mk +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/gem_getecid.mk @@ -22,3 +22,8 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +-include 00gemini_common.mk + +PROCEDURE=gem_getecid +$(eval $(call ADD_GEM_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.C b/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.C index c9f1a9b63..771ecfbc2 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.C +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.C @@ -22,3 +22,126 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file gem_draminit_utils.C +/// @brief Procedure definition to initialize DRAM +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/poll.H> +#include <mss_generic_attribute_getters.H> +#include <generic/memory/lib/utils/count_dimm.H> +#include <mss_generic_attribute_setters.H> +#include <lib/gem_draminit_utils.H> + +namespace mss +{ +namespace gem +{ + +/// +/// @brief Polls DRAM calibration register to check for complete +/// @param[in] i_target the controller +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode poll_check_calibration(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + // Address defined here as gemini SCOM address library does not exist + + // Using default parameters + mss::poll_parameters l_poll_params; + + fapi2::buffer<uint64_t> l_data_buffer; + + bool l_poll_success = + mss::poll(i_target, GEMINI_ICETRAP4, l_poll_params, + [&l_data_buffer](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool + { + FAPI_DBG("Polling: Gemini calibration status 0x%llx, remaining: %d", stat_reg, poll_remaining); + l_data_buffer = stat_reg; + + return l_data_buffer.getBit<FLD_ICETRAP4_CALIBRATION_STATUS_BIT_1>() + && l_data_buffer.getBit<FLD_ICETRAP4_CALIBRATION_STATUS_BIT_2>(); + }); + + FAPI_ASSERT(l_poll_success == true, + fapi2::MSS_GEM_DRAMINIT_CALIBRATION_DID_NOT_COMPLETE() + .set_TARGET(i_target) + .set_REGISTER(GEMINI_ICETRAP4) + .set_CONTENTS(l_data_buffer), + "Calibration check timed out for target %s", mss::spd::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; + +} + +/// +/// @brief Write bit to initialize memory and then poll for completion +/// +/// @param[in] i_target gemini target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode init_memory(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target) +{ + // Polling needs to occur for at least 5 seconds. Doing 7 seconds with delay of 0.25 seconds + static constexpr uint32_t QUARTER_SECOND_POLL_DELAY = 250000000; // NS + static constexpr uint32_t SEVEN_SECOND_POLL_COUNT = 28; + + fapi2::buffer<uint64_t> l_reg_contents; + mss::poll_parameters l_poll_params; + + l_poll_params.iv_delay = QUARTER_SECOND_POLL_DELAY; + l_poll_params.iv_poll_count = SEVEN_SECOND_POLL_COUNT; + + // Init memory to address as data + FAPI_TRY(fapi2::getScom(i_target, GEMINI_ICECFG1, l_reg_contents)); + + if (l_reg_contents.getBit<FLD_ICECFG1_MEMORY_INIT_START>()) + { + // Init bit is stuck. We need to clear it before we can set the bit again + FAPI_INF("gem_draminit(): Memory appears to be already initialized for %s , Clearing bit before continuing", + mss::c_str(i_target)); + l_reg_contents.clearBit<FLD_ICECFG1_MEMORY_INIT_START>(); + FAPI_TRY(fapi2::putScom(i_target, GEMINI_ICECFG1, l_reg_contents)); + } + + l_reg_contents.setBit<FLD_ICECFG1_INIT_ZERO>(); + FAPI_TRY(fapi2::putScom(i_target, GEMINI_ICECFG1, l_reg_contents)); + + l_reg_contents.setBit<FLD_ICECFG1_MEMORY_INIT_START>(); + FAPI_TRY(fapi2::putScom(i_target, GEMINI_ICECFG1, l_reg_contents)); + + l_reg_contents.flush<0>(); + { + bool l_poll_success = mss::poll(i_target, GEMINI_ICETRAP4, l_poll_params, + [&l_reg_contents](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool + { + FAPI_DBG("Polling: Gemini calibration status 0x%016x for memory init, remaining: %d", + stat_reg, poll_remaining); + l_reg_contents = stat_reg; + + return l_reg_contents.getBit<FLD_ICETRAP4_MEMORY_INIT_COMPELTE>(); + }); + + FAPI_ASSERT(l_poll_success, + fapi2::MSS_GEM_DRAMINIT_MEM_INIT_DID_NOT_COMPLETE() + .set_TARGET(i_target) + .set_REGISTER(GEMINI_ICETRAP4) + .set_CONTENTS(l_reg_contents), + "Calibration check timed out for target %s", mss::spd::c_str(i_target)); + } + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +}// exp +}// mss diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.H b/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.H index 346eabb40..9a3c4f1b6 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.H +++ b/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/gem_draminit_utils.H @@ -22,3 +22,51 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file gem_draminit_utils.H +/// @brief Procedure definition to initialize DRAM +/// +// *HWP HWP Owner: Mark Pizzutillo <aamarin@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef __MSS_GEM_DRAMINIT_UTILS__ +#define __MSS_GEM_DRAMINIT_UTILS__ + +#include <fapi2.H> + +namespace mss +{ +namespace gem +{ + +static constexpr uint64_t GEMINI_ICETRAP4 = 0x08012428; +static constexpr uint64_t GEMINI_ICECFG1 = 0x0801240D; +static constexpr uint64_t FLD_ICETRAP4_CALIBRATION_STATUS_BIT_1 = 0x0; +static constexpr uint64_t FLD_ICETRAP4_CALIBRATION_STATUS_BIT_2 = 0x1; +static constexpr uint64_t FLD_ICETRAP4_MEMORY_INIT_COMPELTE = 32; +static constexpr uint64_t FLD_ICECFG1_INIT_ZERO = 8; +static constexpr uint64_t FLD_ICECFG1_MEMORY_INIT_START = 7; + +/// +/// @brief Polls DRAM calibration register to check for complete +/// @param[in] i_target gemini target +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode poll_check_calibration(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +/// +/// @brief Write bit to initialize memory and then poll for completion +/// +/// @param[in] i_target gemini target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode init_memory(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& i_target); + +}// exp +}// mss + +#endif diff --git a/src/import/chips/ocmb/gemini/procedures/xml/error_info/gem_draminit_errors.xml b/src/import/chips/ocmb/gemini/procedures/xml/error_info/gem_draminit_errors.xml index a8cdc5e7d..d47d3b3af 100644 --- a/src/import/chips/ocmb/gemini/procedures/xml/error_info/gem_draminit_errors.xml +++ b/src/import/chips/ocmb/gemini/procedures/xml/error_info/gem_draminit_errors.xml @@ -23,4 +23,35 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> + + <hwpError> + <rc>RC_MSS_GEM_DRAMINIT_CALIBRATION_DID_NOT_COMPLETE</rc> + <description> + During gemini dram initialization, the calibration process + did not complete as reported by the Gemini calibration status register. + </description> + <ffdc>TARGET</ffdc> + <ffdc>REGISTER</ffdc> + <ffdc>CONTENTS</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + + <hwpError> + <rc>RC_MSS_GEM_DRAMINIT_MEM_INIT_DID_NOT_COMPLETE</rc> + <description> + During gemini dram initialization, the memory initialization process + did not complete as reported by the Gemini calibration status register. + </description> + <ffdc>TARGET</ffdc> + <ffdc>REGISTER</ffdc> + <ffdc>CONTENTS</ffdc> + <callout> + <target>TARGET</target> + <priority>HIGH</priority> + </callout> + </hwpError> + </hwpErrors> diff --git a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C index 764f38274..964485726 100644 --- a/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C +++ b/src/import/chips/ocmb/procedures/hwp/initfiles/explorer_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,8 +32,9 @@ using namespace fapi2; constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_3 = 3; constexpr uint64_t literal_0 = 0; -constexpr uint64_t literal_9 = 9; +constexpr uint64_t literal_11 = 11; constexpr uint64_t literal_4 = 4; +constexpr uint64_t literal_9 = 9; constexpr uint64_t literal_14 = 14; constexpr uint64_t literal_7 = 7; constexpr uint64_t literal_2 = 2; @@ -42,7 +43,6 @@ constexpr uint64_t literal_5 = 5; constexpr uint64_t literal_266 = 266; constexpr uint64_t literal_1866 = 1866; constexpr uint64_t literal_2668 = 2668; -constexpr uint64_t literal_11 = 11; constexpr uint64_t literal_2934 = 2934; constexpr uint64_t literal_12 = 12; constexpr uint64_t literal_13 = 13; @@ -96,6 +96,7 @@ constexpr uint64_t literal_0b01010 = 0b01010; constexpr uint64_t literal_0b00000 = 0b00000; constexpr uint64_t literal_0b00010 = 0b00010; constexpr uint64_t literal_0b00011 = 0b00011; +constexpr uint64_t literal_0b0001 = 0b0001; fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT2, @@ -105,6 +106,8 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP fapi2::ATTR_IS_SIMULATION_Type l_TGT2_ATTR_IS_SIMULATION; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT2, l_TGT2_ATTR_IS_SIMULATION)); uint64_t l_def_IS_MICROSEMI_SIM = (l_TGT2_ATTR_IS_SIMULATION == literal_1); + fapi2::ATTR_MEM_EXP_DFIMRL_CLK_Type l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EXP_DFIMRL_CLK, TGT1, l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK)); fapi2::ATTR_MEM_RDIMM_BUFFER_DELAY_Type l_TGT1_ATTR_MEM_RDIMM_BUFFER_DELAY; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_RDIMM_BUFFER_DELAY, TGT1, l_TGT1_ATTR_MEM_RDIMM_BUFFER_DELAY)); fapi2::ATTR_MEM_EFF_DIMM_TYPE_Type l_TGT1_ATTR_MEM_EFF_DIMM_TYPE; @@ -115,6 +118,7 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP fapi2::ATTR_MEM_EFF_DRAM_CL_Type l_TGT1_ATTR_MEM_EFF_DRAM_CL; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_CL, TGT1, l_TGT1_ATTR_MEM_EFF_DRAM_CL)); uint64_t l_def_IS_IBM_SIM = literal_0; + uint64_t l_def_IS_HW = (l_TGT2_ATTR_IS_SIMULATION == literal_0); fapi2::ATTR_MEM_DRAM_CWL_Type l_TGT1_ATTR_MEM_DRAM_CWL; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_CWL, TGT1, l_TGT1_ATTR_MEM_DRAM_CWL)); fapi2::ATTR_MEM_EFF_FREQ_Type l_TGT1_ATTR_MEM_EFF_FREQ; @@ -172,10 +176,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1]); uint64_t l_def_NUM_MRANKS_0 = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] == literal_0x0) | l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0]); - fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM_Type l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_NUM_RANKS_PER_DIMM, TGT1, l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM)); - uint64_t l_def_NUM_SRANKS_1 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] / l_def_NUM_MRANKS_1); - uint64_t l_def_NUM_SRANKS_0 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] / l_def_NUM_MRANKS_0); + fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM_Type l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM, TGT1, l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM)); + uint64_t l_def_NUM_SRANKS_1 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] / l_def_NUM_MRANKS_1); + uint64_t l_def_NUM_SRANKS_0 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] / l_def_NUM_MRANKS_0); uint64_t l_def_disable_fast_act = ((((l_def_NUM_SRANKS_0 > literal_1) || (l_def_NUM_SRANKS_1 > literal_1)) && ((l_def_NUM_MRANKS_0 == literal_4) || (l_def_NUM_MRANKS_1 == literal_4))) || l_def_half_dimm_mode); fapi2::ATTR_MSS_MRW_DRAM_2N_MODE_Type l_TGT2_ATTR_MSS_MRW_DRAM_2N_MODE; @@ -186,16 +190,24 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, TGT0, l_TGT0_ATTR_MEM_MRW_IS_PLANAR)); uint64_t l_def_SLOT0_DENOMINATOR = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] == literal_0x0) | l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0]); - uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] / l_def_SLOT0_DENOMINATOR); + uint64_t l_def_SLOT0_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] / + l_def_SLOT0_DENOMINATOR); uint64_t l_def_SLOT1_DENOMINATOR = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1] == literal_0x0) | l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1]); - uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] / l_def_SLOT1_DENOMINATOR); + uint64_t l_def_SLOT1_DRAM_STACK_HEIGHT = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] / + l_def_SLOT1_DENOMINATOR); fapi2::ATTR_MEM_SI_ODT_RD_Type l_TGT1_ATTR_MEM_SI_ODT_RD; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_RD, TGT1, l_TGT1_ATTR_MEM_SI_ODT_RD)); + uint64_t l_def_dual_drop = ((l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_0] > literal_0) + && (l_TGT1_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM[literal_1] > literal_0)); + fapi2::ATTR_MEM_EFF_FOUR_RANK_MODE_Type l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_FOUR_RANK_MODE, TGT1, l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE)); + uint64_t l_def_four_rank_mode = (l_TGT1_ATTR_MEM_EFF_FOUR_RANK_MODE[literal_0] == literal_1); + uint64_t l_def_cs_tied = ((l_def_four_rank_mode == literal_0) && (l_def_dual_drop == literal_0)); fapi2::ATTR_MEM_SI_ODT_WR_Type l_TGT1_ATTR_MEM_SI_ODT_WR; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_SI_ODT_WR, TGT1, l_TGT1_ATTR_MEM_SI_ODT_WR)); - uint64_t l_def_NUM_RANKS = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] + - l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1]); + uint64_t l_def_NUM_RANKS = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] + + l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1]); uint64_t l_def_NUM_RANKS_DENOMINATOR = ((l_def_NUM_RANKS == literal_0x0) | l_def_NUM_RANKS); fapi2::ATTR_MEM_EFF_DRAM_TREFI_Type l_TGT1_ATTR_MEM_EFF_DRAM_TREFI; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_EFF_DRAM_TREFI, TGT1, l_TGT1_ATTR_MEM_EFF_DRAM_TREFI)); @@ -219,8 +231,8 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP uint64_t l_def_row_bit16_val_1 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_1] >= literal_17); uint64_t l_def_row_bit17_val_0 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_0] >= literal_18); uint64_t l_def_row_bit17_val_1 = (l_TGT1_ATTR_MEM_EFF_DRAM_ROW_BITS[literal_1] >= literal_18); - uint64_t l_def_slot_val_0 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] > literal_0); - uint64_t l_def_slot_val_1 = (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] > literal_0); + uint64_t l_def_slot_val_0 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] > literal_0); + uint64_t l_def_slot_val_1 = (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] > literal_0); uint64_t l_def_m0_val_0 = (l_def_NUM_MRANKS_0 > literal_2); uint64_t l_def_m1_val_0 = (l_def_NUM_MRANKS_0 >= literal_2); uint64_t l_def_m0_val_1 = (l_def_NUM_MRANKS_1 > literal_2); @@ -229,18 +241,32 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_def_m0_val_0) + l_def_m1_val_0) + l_def_s0_val_0) + l_def_s1_val_0) + l_def_s2_val_0); uint64_t l_def_num_of_bitvals_1 = (((((((l_def_row_bit17_val_1 + l_def_row_bit16_val_1) + l_def_row_bit15_val_1) + l_def_m0_val_1) + l_def_m1_val_1) + l_def_s0_val_1) + l_def_s1_val_1) + l_def_s2_val_1); + fapi2::ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE_Type l_TGT2_ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE, TGT2, l_TGT2_ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE)); + fapi2::ATTR_MSS_OCMB_RECOV_OBJ_HANDLE_Type l_TGT2_ATTR_MSS_OCMB_RECOV_OBJ_HANDLE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_RECOV_OBJ_HANDLE, TGT2, l_TGT2_ATTR_MSS_OCMB_RECOV_OBJ_HANDLE)); + fapi2::ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE_Type l_TGT2_ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE, TGT2, l_TGT2_ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE)); + fapi2::ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE_Type l_TGT2_ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE, TGT2, l_TGT2_ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE)); fapi2::buffer<uint64_t> l_scom_buffer; { FAPI_TRY(fapi2::getScom( TGT0, 0x801140cull, l_scom_buffer )); if (l_def_IS_MICROSEMI_SIM) { - l_scom_buffer.insert<36, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) ); + l_scom_buffer.insert<36, 6, 58, uint64_t>((((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_11) + l_def_RDIMM_Add_latency) + + l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK) ); } else if (l_def_IS_IBM_SIM) { l_scom_buffer.insert<36, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<36, 6, 58, uint64_t>((((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_11) + l_def_RDIMM_Add_latency) + + l_TGT1_ATTR_MEM_EXP_DFIMRL_CLK) ); + } if (l_def_IS_MICROSEMI_SIM) { @@ -250,6 +276,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<47, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<47, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) ); + } if (l_def_IS_MICROSEMI_SIM) { @@ -259,6 +289,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<42, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_4) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<42, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - literal_9) + l_def_RDIMM_Add_latency) ); + } if (l_def_IS_MICROSEMI_SIM) { @@ -268,6 +302,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_9) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<30, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_14) + l_def_RDIMM_Add_latency) ); + } if (l_def_IS_MICROSEMI_SIM) { @@ -277,6 +315,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<57, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_2) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<57, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_7) + l_def_RDIMM_Add_latency) ); + } if (l_def_IS_MICROSEMI_SIM) { @@ -286,6 +328,10 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<52, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_2) + l_def_RDIMM_Add_latency) ); } + else if (l_def_IS_HW) + { + l_scom_buffer.insert<52, 5, 59, uint64_t>(((l_TGT1_ATTR_MEM_DRAM_CWL - literal_7) + l_def_RDIMM_Add_latency) ); + } l_scom_buffer.insert<24, 6, 58, uint64_t>(literal_24 ); l_scom_buffer.insert<0, 6, 58, uint64_t>(((l_TGT1_ATTR_MEM_EFF_DRAM_CL - l_TGT1_ATTR_MEM_DRAM_CWL) + @@ -589,12 +635,20 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_scom_buffer.insert<0, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_7) ); l_scom_buffer.insert<1, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_6) ); - l_scom_buffer.insert<2, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_3) ); - l_scom_buffer.insert<3, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_2) ); + l_scom_buffer.insert<2, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_3) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) ); + l_scom_buffer.insert<3, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_2) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_0] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) ); l_scom_buffer.insert<4, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_7) ); l_scom_buffer.insert<5, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_6) ); - l_scom_buffer.insert<6, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_3) ); - l_scom_buffer.insert<7, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_2) ); + l_scom_buffer.insert<6, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_3) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) ); + l_scom_buffer.insert<7, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_2) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_1] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) ); l_scom_buffer.insert<8, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_7) ); l_scom_buffer.insert<9, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_6) ); l_scom_buffer.insert<10, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_0][literal_2] >> literal_3) ); @@ -621,12 +675,20 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_scom_buffer.insert<31, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_RD[literal_1][literal_3] >> literal_2) ); l_scom_buffer.insert<32, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_7) ); l_scom_buffer.insert<33, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_6) ); - l_scom_buffer.insert<34, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_3) ); - l_scom_buffer.insert<35, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_2) ); + l_scom_buffer.insert<34, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_3) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) ); + l_scom_buffer.insert<35, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_2) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_0] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) ); l_scom_buffer.insert<36, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_7) ); l_scom_buffer.insert<37, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_6) ); - l_scom_buffer.insert<38, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_3) ); - l_scom_buffer.insert<39, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_2) ); + l_scom_buffer.insert<38, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_3) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_7) & literal_0b1) && (l_def_cs_tied == literal_1))) ); + l_scom_buffer.insert<39, 1, 63, uint64_t>(((((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_2) & + literal_0b1) && (l_def_cs_tied == literal_0)) + || (((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_1] >> literal_6) & literal_0b1) && (l_def_cs_tied == literal_1))) ); l_scom_buffer.insert<40, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_7) ); l_scom_buffer.insert<41, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_6) ); l_scom_buffer.insert<42, 1, 63, uint64_t>((l_TGT1_ATTR_MEM_SI_ODT_WR[literal_0][literal_2] >> literal_3) ); @@ -775,70 +837,71 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP } l_scom_buffer.insert<46, 11, 53, uint64_t>(l_def_REFRESH_INTERVAL ); + l_scom_buffer.insert<62, 1, 63, uint64_t>(literal_1 ); FAPI_TRY(fapi2::putScom(TGT0, 0x8011437ull, l_scom_buffer)); } { FAPI_TRY(fapi2::getScom( TGT0, 0x801186full, l_scom_buffer )); - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01011 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01100 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01100 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01101 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01100 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01101 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01101 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<54, 5, 59, uint64_t>(literal_0b01110 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01101 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01110 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01110 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<49, 5, 59, uint64_t>(literal_0b01111 ); } @@ -1298,92 +1361,92 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_scom_buffer.insert<38, 5, 59, uint64_t>(literal_0b10011 ); } - if (((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] < literal_2) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] < literal_2))) + if (((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] < literal_2) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] < literal_2))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b00110 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_1) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01100 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_2) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01101 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_3) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01110 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_4) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01111 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_5) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10000 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_6) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10001 ); } else if (((l_def_half_dimm_mode == literal_1) && ((l_def_num_of_bitvals_0 == literal_7) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10010 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_1) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01101 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_2) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01110 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_3) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b01111 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_4) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10000 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_5) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10001 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_6) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10010 ); } else if (((l_def_half_dimm_mode == literal_0) && ((l_def_num_of_bitvals_0 == literal_7) - && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] >= literal_2) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] >= literal_2))))) + && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] >= literal_2) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] >= literal_2))))) { l_scom_buffer.insert<33, 5, 59, uint64_t>(literal_0b10011 ); } @@ -1429,76 +1492,76 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP { l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00101 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00110 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<35, 5, 59, uint64_t>(literal_0b00111 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00110 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00111 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b00111 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<43, 5, 59, uint64_t>(literal_0b01000 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b00111 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01000 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01000 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<51, 5, 59, uint64_t>(literal_0b01001 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01000 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01001 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01001 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<59, 5, 59, uint64_t>(literal_0b01010 ); } @@ -1646,50 +1709,83 @@ fapi2::ReturnCode explorer_scom(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP l_scom_buffer.insert<19, 5, 59, uint64_t>(literal_0b00101 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01001 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01010 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01010 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<3, 5, 59, uint64_t>(literal_0b01011 ); } - if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + if (((l_def_half_dimm_mode == literal_1) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01010 ); } - else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_1) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01011 ); } - else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] == literal_1) - || (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] == literal_1)))) + else if (((l_def_half_dimm_mode == literal_0) && ((l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] == literal_1) + || (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] == literal_1)))) { l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01011 ); } - else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_0] != literal_1)) - && (l_TGT1_ATTR_MEM_EFF_NUM_RANKS_PER_DIMM[literal_1] != literal_1))) + else if ((((l_def_half_dimm_mode == literal_0) && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_0] != literal_1)) + && (l_TGT1_ATTR_MEM_EFF_LOGICAL_RANKS_PER_DIMM[literal_1] != literal_1))) { l_scom_buffer.insert<11, 5, 59, uint64_t>(literal_0b01100 ); } FAPI_TRY(fapi2::putScom(TGT0, 0x8011871ull, l_scom_buffer)); } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x801240dull, l_scom_buffer )); + + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0001 ); + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0001 ); + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0001 ); + l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0001 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x801240dull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x8012410ull, l_scom_buffer )); + + l_scom_buffer.insert<0, 64, 0, uint64_t>(l_TGT2_ATTR_MSS_OCMB_CHECKSTOP_OBJ_HANDLE ); + FAPI_TRY(fapi2::putScom(TGT0, 0x8012410ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x8012411ull, l_scom_buffer )); + + l_scom_buffer.insert<0, 64, 0, uint64_t>(l_TGT2_ATTR_MSS_OCMB_RECOV_OBJ_HANDLE ); + FAPI_TRY(fapi2::putScom(TGT0, 0x8012411ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x8012412ull, l_scom_buffer )); + + l_scom_buffer.insert<0, 64, 0, uint64_t>(l_TGT2_ATTR_MSS_OCMB_SPECATTN_OBJ_HANDLE ); + FAPI_TRY(fapi2::putScom(TGT0, 0x8012412ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x8012413ull, l_scom_buffer )); + + l_scom_buffer.insert<0, 64, 0, uint64_t>(l_TGT2_ATTR_MSS_OCMB_APPINTR_OBJ_HANDLE ); + FAPI_TRY(fapi2::putScom(TGT0, 0x8012413ull, l_scom_buffer)); + } }; fapi_try_exit: diff --git a/src/import/chips/p9/common/include/p9_frequency_buckets.H b/src/import/chips/p9/common/include/p9_frequency_buckets.H index ab6af1b5d..2ac8574d5 100644 --- a/src/import/chips/p9/common/include/p9_frequency_buckets.H +++ b/src/import/chips/p9/common/include/p9_frequency_buckets.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -65,6 +65,30 @@ const uint32_t MEM_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = 2666 }; +// OMI bucket descriptor +struct OmiBucketDescriptor_t +{ + uint32_t omifreq; // OMI Frequency in MHz + uint32_t vco; // VCO selector + + uint32_t mcafreq; // MCA Frequency in MHz +}; + +//MC PLL frequency in MHz for Axone +// index is bucket number +// OMI -> ATTR_FREQ_OMI_MHZ +// VCO -> ATTR_OMI_PLL_VCO +// MCA -> ATTR_FREQ_MCA_MHZ +const OmiBucketDescriptor_t OMI_PLL_FREQ_LIST[MEM_PLL_FREQ_BUCKETS] = +{ + // OMI VCO MCA Data rate + { 19200, 0, 1200 }, // ->DDR4-2400 + { 21330, 0, 1333 }, // ->DDR4-2667 + { 23460, 0, 1466 }, // ->DDR4-2933 + { 23460, 1, 1466 }, // ->DDR4-2933 + { 25600, 1, 1600 } // ->DDR4-3200 +}; + // constant definining number of OBUS PLL frequency options ('buckets') // to be built into unsigned HW image const uint8_t OBUS_PLL_FREQ_BUCKETS = 3; diff --git a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h index b8d4c030e..0a51fbca3 100644 --- a/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h +++ b/src/import/chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h @@ -41,7 +41,8 @@ extern "C" { #endif -#define HCODE_OCC_SHARED_MAGIC_NUMBER 0x4F505330 //OPS0 +#define HCODE_OCC_SHARED_MAGIC_NUMBER_OPS0 0x4F505330 //OPS0 +#define HCODE_OCC_SHARED_MAGIC_NUMBER_OPS1 0x4F505331 //OPS1 //--------------- // IPC from 405 @@ -409,17 +410,9 @@ typedef struct // ----------------------------------------------------------------------------- // Start Error Log Table -/// Maximum number of error log entries available -#define MAX_HCODE_ELOG_ENTRIES 4 - -/// Index into the array of error log entries -enum elog_entry_index -{ - ELOG_PGPE_CRITICAL = 0, - ELOG_PGPE_INFO = 1, - ELOG_SGPE_CRITICAL = 2, - ELOG_SGPE_INFO = 3, -}; +/// Maximum number of error log entries available, 1 UE per SPGE & PGPE +#define MAX_HCODE_ELOG_ENTRIES 2 +#define HCODE_ELOG_TABLE_MAGIC_WORD 0x454C5443 // "ELTC" /// Structure of an individual error log entry typedef struct @@ -461,7 +454,7 @@ typedef struct hcode_error_table } fields; } dw0; - /// Array of error log entries (index with enum elog_entry_index) + /// Array of error log entries hcode_elog_entry_t elog[MAX_HCODE_ELOG_ENTRIES]; } hcode_error_table_t; @@ -491,9 +484,6 @@ typedef struct //PGPE WOF Values pgpe_wof_values_t pgpe_wof_values; - //Reserved - uint64_t reserved1; - /// Hcode Error Log Index hcode_error_table_t errlog_idx; diff --git a/src/import/chips/p9/common/scominfo/p9_cu.H b/src/import/chips/p9/common/scominfo/p9_cu.H index 620e072a9..180828620 100644 --- a/src/import/chips/p9/common/scominfo/p9_cu.H +++ b/src/import/chips/p9/common/scominfo/p9_cu.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -68,7 +68,8 @@ extern "C" PU_PPE_CHIPUNIT, ///< PPE PU_SBE_CHIPUNIT, ///< SBE PU_CAPP_CHIPUNIT, ///< CAPP - PU_MC_CHIPUNIT, ///< mc + PU_MC_CHIPUNIT, ///< mc + PU_NPU_CHIPUNIT, ///< NPU NONE, ///< None/Invalid } p9ChipUnits_t; diff --git a/src/import/chips/p9/common/scominfo/p9_scom_addr.H b/src/import/chips/p9/common/scominfo/p9_scom_addr.H index 513cf0db6..b3d1186c0 100644 --- a/src/import/chips/p9/common/scominfo/p9_scom_addr.H +++ b/src/import/chips/p9/common/scominfo/p9_scom_addr.H @@ -452,6 +452,13 @@ extern "C" P9A_MC_OMI2_FRST_LANE = 0x10, ///< First lane of OMI % 3 = 2 } p9a_mc_lane_t; + typedef enum + { + P9A_NPU_2_RING_ID = 0x7, + P9A_NPU_2_FIR_RING_ID = 0x8, + P9A_NPU_0_FIR_RING_ID = 0xF, + } p9a_npu_ring_id_t; + // 8 7 6 5 4 3 2 1 // // |0 1 2 3| |4 5 6 7| |8 9 10 11| |12 13 14 15| |16 17 18 19| |20 21 22 23| |24 25 26 27| |28 29 30 31| diff --git a/src/import/chips/p9/common/scominfo/p9_scominfo.C b/src/import/chips/p9/common/scominfo/p9_scominfo.C index 0039625ca..ff80a3161 100644 --- a/src/import/chips/p9/common/scominfo/p9_scominfo.C +++ b/src/import/chips/p9/common/scominfo/p9_scominfo.C @@ -646,6 +646,66 @@ extern "C" break; + case PU_NPU_CHIPUNIT: + + // NPU0 and NPU1 exist on the N3 chiplet, NPU2 exists on the N1 chiplet instead + l_chiplet_id = ( 2 == i_chipUnitNum ) ? N1_CHIPLET_ID : N3_CHIPLET_ID ; + l_scom.set_chiplet_id( l_chiplet_id ); + + // Covers the following addresses: + // NPU0: 05011000 to 050113FF + // NPU1: 05011400 to 050117FF + // NPU2: 03011C00 to 03011FFF + if ( N3_NPU_0_RING_ID == l_ring || + N3_NPU_1_RING_ID == l_ring || + P9A_NPU_2_RING_ID == l_ring ) + { + // NPU0/NPU1 + if ( N3_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( N3_NPU_0_RING_ID + i_chipUnitNum ); + } + // NPU2 + else if ( N1_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_2_RING_ID ); + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + } + // Covers the following addresses: + // NPU0: 05013C00 to 05013C8F + // NPU1: 05013CC0 to 05013D4F + // NPU2: 03012000 to 0301208F + else if ( P9A_NPU_0_FIR_RING_ID == l_ring || + P9A_NPU_2_FIR_RING_ID == l_ring ) + { + // NPU0/NPU1 + if ( N3_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_0_FIR_RING_ID ); + l_scom.set_sat_id( (l_sat_id % 3) + (3 * i_chipUnitNum) ); + } + // NPU2 + else if ( N1_CHIPLET_ID == l_chiplet_id ) + { + l_scom.set_ring( P9A_NPU_2_FIR_RING_ID ); + l_scom.set_sat_id( l_sat_id % 3 ); + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + } + else + { + l_scom.set_addr( FAILED_TRANSLATION ); + } + + break; + default: l_scom.set_addr(FAILED_TRANSLATION); break; @@ -1179,7 +1239,7 @@ extern "C" } } - if (P9A_MC_OMIC0_PPE_RING_ID <= l_ring && l_ring < P9A_MC_OMIC2_PPE_RING_ID && l_port == UNIT_PORT_ID) + if (P9A_MC_OMIC0_PPE_RING_ID <= l_ring && l_ring <= P9A_MC_OMIC2_PPE_RING_ID && l_port == UNIT_PORT_ID) { o_chipUnitRelated = true; o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_OMIC_CHIPUNIT, @@ -1498,6 +1558,37 @@ extern "C" o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_PPE_CHIPUNIT, (l_chiplet_id - OB0_CHIPLET_ID) + PPE_IO_OB0_CHIPUNIT_NUM)); } + + // PU_NPU_CHIPUNIT + // npu: 0..1 + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N3_CHIPLET_ID) && + (N3_NPU_0_RING_ID <= l_ring && l_ring <= N3_NPU_1_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, + (l_ring - N3_NPU_0_RING_ID))); + } + + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N3_CHIPLET_ID) && + (l_ring == P9A_NPU_0_FIR_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, + (l_sat_id / 3))); + } + + // PU_NPU_CHIPUNIT + // npu: 2 + if ( (l_port == UNIT_PORT_ID) && + (l_chiplet_id == N1_CHIPLET_ID) && + (l_ring == P9A_NPU_2_RING_ID || l_ring == P9A_NPU_2_FIR_RING_ID) ) + { + o_chipUnitRelated = true; + o_chipUnitPairing.push_back(p9_chipUnitPairing_t(PU_NPU_CHIPUNIT, 2)); + } + } return (!l_scom.is_valid()); diff --git a/src/import/chips/p9/initfiles/p9a.int.scan.initfile b/src/import/chips/p9/initfiles/p9a.int.scan.initfile new file mode 100644 index 000000000..745c936d3 --- /dev/null +++ b/src/import/chips/p9/initfiles/p9a.int.scan.initfile @@ -0,0 +1,47 @@ +#-- *!*************************************************************************** +#-- *! +#-- *! OWNER NAME : David Kauer (dmkauer@us.ibm.com) +#-- *! +#-- *!*************************************************************************** + + +SyntaxVersion = 3 + +target_type 0 TARGET_TYPE_PROC_CHIP; + +# Enabled for DD1 only +ispy INT.INT_PC_LBS1_CMD_MMIO_LDST_CS [when=L && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + bits, spyv; + 5, 0b1; + 6, 0b1; +} + +# Defect HW378025 / Nimbus DD1 only +ispy INT.INT_PC_LBS1_REGS_CLOCKGATE_DIS_CS [when=L && ATTR_CHIP_EC_FEATURE_HW378025] { + spyv; + 0b1; +} + +# Defect HW930007 / Nimbus DD1 only +ispy INT.INT_PC.LBS2.VPC.P1.LCBCNTL_BLK.CLOCKGATE_DISABLE [when=L && ATTR_CHIP_EC_FEATURE_HW930007] { + spyv; + 0b1; +} + +# Defect HW408972 / Nimbus DD1 & DD2 +ispy INT.INT_PC_LBS1_CRESP_MAC_CS [when=L && ATTR_CHIP_EC_FEATURE_HW408972] { + bits, spyv, expr; + 3, 0b1, ((ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 1) || (ATTR_CHIP_EC_FEATURE_P9N_INT_DD20 == 1)); + 4, 0b1, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD21 == 1); +} + +# Defect HW388874 +espy BRIDGE.PSIHB.ESB_OR_LSI_INTERRUPTS [when=L] { + spyv, expr; + ON, (ATTR_CHIP_EC_FEATURE_HW388874 == 0); +} +# HW441771 - Axone init to return to P9 behavior +ispy INT.INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS [when=L && ATTR_CHIP_EC_FEATURE_AXONE_HW441771] { + spyv; + 0b1; +} diff --git a/src/import/chips/p9/initfiles/p9a.int.scom.initfile b/src/import/chips/p9/initfiles/p9a.int.scom.initfile new file mode 100644 index 000000000..5b0ff1886 --- /dev/null +++ b/src/import/chips/p9/initfiles/p9a.int.scom.initfile @@ -0,0 +1,178 @@ +#- *!*************************************************************************** +#-- *! +#-- *! OWNER NAME : David Kauer (dmkauer@us.ibm.com) +#-- *! +#-- *!*************************************************************************** + +SyntaxVersion = 3 + +target_type 0 TARGET_TYPE_PROC_CHIP; +target_type 1 TARGET_TYPE_SYSTEM; + +ispy INT.INT_PC.INT_PC_AIB_TX_CRD_RSD_CRD_VPC_LD_RMT [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0b00; +} + +ispy INT.INT_VC.INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG [when=S] { + spyv; + 0x5BBF; +} + +ispy INT.INT_VC.INT_VC_IRQ_TO_EQC_CREDITS [when=S] { + spyv; + 0x6262220242160000; +} + +# SW437676 / SW445631 +ispy INT.INT_VC.INT_VC_AIB_TIMEOUT [when=S] { + spyv; + 0x18; +} + +ispy INT.INT_PC.INT_PC_DBG_TMOT_ARX_TIMEOUT [when=S] { + spyv; + 0x18; +} + +ispy INT.INT_PC.INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT [when=S] { + spyv; + 0x18; +} + +# Defect HW372116 / Nimbus DD1 only +ispy INT.INT_CQ.INT_CQ_AIB_CTL [when=S && ATTR_CHIP_EC_FEATURE_HW372116] { + spyv; + 0x0070000072040140; +} + +# Defect HW395947 / Nimbus DD1 only +espy INT.INT_VC.INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR_ORDERING_DMA [when=S && ATTR_CHIP_EC_FEATURE_HW395947] { + spyv; + OFF; +} + +espy INT.INT_PC.INT_PC_AIB_TX_ORDER_RELAXED_WR_ORDERING [when=S && ATTR_CHIP_EC_FEATURE_HW395947] { + spyv; + OFF; +} + +# Error Configuration +ispy INT.INT_PC.INT_PC_ERR0_CFG0_ERROR_CONFIG0 [when=S] { + spyv, expr; + 0x010003FF00100020, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x050043EF00100020, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.INT_PC_ERR0_CFG1_ERROR_CONFIG0 [when=S] { + spyv, expr; + 0xD8DFB200DFAFFFD7, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0xFADFBB8CFFAFFFD7, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.INT_PC_ERR1_CFG0_ERROR_CONFIG0 [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x0008002000002002; +} + +ispy INT.INT_PC.INT_PC_ERR1_CFG1_ERROR_CONFIG0 [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0xEF6417D2DE7DD3FD; +} + +ispy INT.INT_PC.LBS2.INT_PC_VPC_ERR_CFG0_ERROR_CONFIG [when=S] { + spyv, expr; + 0x0002000410000000, (ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x0002000610000000, (ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_PC.LBS2.INT_PC_VPC_ERR_CFG1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x7710CCC3E0000701; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G0R0_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0x00001003000002; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G0R1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_P9N_INT_DD10] { + spyv; + 0xFFFFEFFCFFFFFC; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G1R0_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW411637] { + spyv; + 0x0002C018006; +} + +ispy INT.INT_VC.INT_VC_ERR_CFG_G1R1_ERROR_CONFIG [when=S && ATTR_CHIP_EC_FEATURE_HW411637] { + spyv; + 0xFFFCFFEFFFA; +} + + +# FIR Registers +ispy INT.INT_CQ.INT_CQ_FIRMASK_FIR_MASK [when=S] { + spyv, expr; + 0x2000005C04028000, (ATTR_CHIP_EC_FEATURE_HW411637 == 1 && ATTR_CHIP_EC_FEATURE_HW426891 == 0); + 0x2000005C040281C3, (ATTR_CHIP_EC_FEATURE_HW411637 == 1 && ATTR_CHIP_EC_FEATURE_HW426891 == 1); + 0x0000005C040081C3, (ATTR_CHIP_EC_FEATURE_HW411637 == 0 && ATTR_CHIP_EC_FEATURE_HW426891 == 1); +} + +ispy INT.INT_CQ.INT_CQ_ACTION0_ACTION0 [when=S] { + spyv; + 0x0000000000000000; +} + +ispy INT.INT_CQ.INT_CQ_ACTION1_ACTION1 [when=S] { + spyv, expr; + 0x9554021F80110FCF, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 1); + 0x9554021F80110E0C, (ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == 0); +} + + +# Dependent Dials +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE [when=S] { + spyv; + 0; +} + +ispy INT.INT_CQ.INT_CQ_PBO_CTL_SKIP_G [when=S] { + spyv, expr; + 1 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_GROUP); + 0 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_NODE); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_PUMP_MODE [when=S] { + spyv, expr; + 1 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_GROUP); + 0 , (TGT1.ATTR_PROC_FABRIC_PUMP_MODE == ATTR_PROC_FABRIC_PUMP_MODE::CHIP_IS_NODE); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_ADDR_EXT_MASK_EN_15_21 [when=S && ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE] { + bits, spyv; + 0:3, (TGT1.ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID); + 4:6, (TGT1.ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID); +} + +ispy INT.INT_CQ.INT_CQ_CFG_PB_GEN_SMF_CONFIG_0_1 [when=S && ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED] { + spyv, expr; + 0b10, (TGT1.ATTR_SMF_CONFIG == TGT1.ATTR_SMF_CONFIG::ENABLED); +} + +# disable MCD for HW423589 +espy INT.INT_CQ.INT_CQ_PBO_CTL_DISABLE_G [when=S && ATTR_CHIP_EC_FEATURE_HW423589_OPTION1] { + spyv; + ON; +} + +espy INT.INT_CQ.INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS [when=S && ATTR_CHIP_EC_FEATURE_HW423589_OPTION1] { + spyv; + ON; +} +# HW441771 - Axone init to return to P9 behavior +ispy INT.INT_CQ.INT_CQ_PBI_CTL_RESERVED_25_31 [when=S && ATTR_CHIP_EC_FEATURE_AXONE_HW441771] { + spyv; + 0b1000000; +} diff --git a/src/import/chips/p9/procedures/hwp/accessors/ddimm_get_efd.C b/src/import/chips/p9/procedures/hwp/accessors/ddimm_get_efd.C index 058067490..9480b341f 100644..100755 --- a/src/import/chips/p9/procedures/hwp/accessors/ddimm_get_efd.C +++ b/src/import/chips/p9/procedures/hwp/accessors/ddimm_get_efd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -82,6 +82,8 @@ const uint16_t SPD_EFD_COUNT_MASK = 0x003F; // Offset to the EFD meta data within the SPD. // size is 128 bytes; address 288 to 415; 32 EFD meta data's sized 4 bytes each const size_t SPD_EFD_META_DATA_ADDR = 288; +// Offset to Host Interface Speed Supported within the SPD. +const size_t SPD_SUPPORTED_HOST_SPEEDS_ADDR = 205; /// SPD - EFD meta data constants // Size of the EFD meta data's within the SPD @@ -151,11 +153,15 @@ const size_t SPD_DDR4_SIZE = 512; // This value is extrapolated from the JEDEC document // 0x29 is for for Microsemi // size is 2 bytes -const uint16_t SPD_DDR4_EXPECTED_DMB_MFG_ID = 0x2980; +const uint16_t SPD_DDR4_DMB_MFG_ID_MICROCHIP = 0x2980; +const uint16_t SPD_DDR4_DMB_MFG_ID_IBM = 0xA480; // SPD - DDR4 expected value for the DMB revision. // Currently at initial revision - revision 0 // size is 1 byte -const uint8_t SPD_DDR4_EXPECTED_DMB_REVISION = 0x00; +const uint8_t SPD_DDR4_EXPECTED_DMB_REVISION_0_MICROCHIP = 0x00; +const uint8_t SPD_DDR4_EXPECTED_DMB_REVISION_A0_MICROCHIP = 0xA0; +const uint8_t SPD_DDR4_EXPECTED_DMB_REVISION_A1_MICROCHIP = 0xA1; +const uint8_t SPD_DDR4_EXPECTED_DMB_REVISION_IBM = 0x00; // Maximum number of FFDC elements we will save off // (should stay in sync with error xml) @@ -196,6 +202,50 @@ enum DDR_MASTER_RANK : uint8_t DDR_MR_BIT_MASK_3 = 0x08, }; +/// +/// @brief Check that MFG ID matches possible values +/// +/// @param[in] i_mfg_id MFG ID +/// @return boolean valid/invalid +/// @note Can be expanded for future MFG IDs +/// +bool check_valid_mfg_id(const uint16_t i_mfg_id) +{ + return (SPD_DDR4_DMB_MFG_ID_MICROCHIP == i_mfg_id || + SPD_DDR4_DMB_MFG_ID_IBM == i_mfg_id); +} + +/// +/// @brief Gets the expected DMB revision of a particular MFG ID +/// +/// @param[in] i_mfg_id MFG ID +/// @param[in] i_dmb_revision DMB revision +/// @return expected DMB revision for ID +/// +bool check_valid_dmb_revision(const uint16_t i_mfg_id, const uint8_t i_dmb_revision) +{ + if (i_mfg_id == SPD_DDR4_DMB_MFG_ID_IBM) + { + FAPI_DBG("ddr4_get_efd: SPD DMB revision = 0x%.2X, expected DMB revision = 0x%.2X", + i_dmb_revision, SPD_DDR4_EXPECTED_DMB_REVISION_IBM); + + return (i_dmb_revision == SPD_DDR4_EXPECTED_DMB_REVISION_IBM); + } + else // == SPD_DDR4_EXPECTED_DMB_REVISION_MICROCHIP + { + // We asserted earlier that we are either MCHP or IBM mfg ID + FAPI_DBG("ddr4_get_efd: SPD DMB revision = 0x%.2X, expected DMB revision = 0x%.2X or 0x%.2X or 0x%.2X", + i_dmb_revision, + SPD_DDR4_EXPECTED_DMB_REVISION_0_MICROCHIP, + SPD_DDR4_EXPECTED_DMB_REVISION_A0_MICROCHIP, + SPD_DDR4_EXPECTED_DMB_REVISION_A1_MICROCHIP); + + return ((i_dmb_revision == SPD_DDR4_EXPECTED_DMB_REVISION_0_MICROCHIP) || + (i_dmb_revision == SPD_DDR4_EXPECTED_DMB_REVISION_A0_MICROCHIP) || + (i_dmb_revision == SPD_DDR4_EXPECTED_DMB_REVISION_A1_MICROCHIP)); + } +} + /// Local utilities // @brief Maps the frequency numeric value to it's bit mask equivalent // Uses the enums in DDR_FREQUENCY above @@ -409,6 +459,7 @@ extern "C" uint16_t l_efdCount{0}; // The number of EFDs size_t l_efdSize{0}; // The size of an EFD, not EFD meta data uint16_t l_dmbMfgId{0}; // The DMB manufacture ID + uint8_t l_dmb_revision{0}; uint16_t l_freqMask{0}; // The frequency mask as found in EFD uint8_t l_rankMask{0}; // The rank mask as found in EFD size_t ii{0}; // A loop index @@ -420,6 +471,8 @@ extern "C" const uint8_t* l_efdMetaDataNptr(nullptr); // Pointer to an individual EFD const uint8_t* l_efdDataNptr(nullptr); + // Host Interface Supported Speeds field + uint16_t l_supportedSpeeds(0); // Fill in a data buffer for FFDC purposes that contains // the first 8 bytes from the SPD (freq,rank,channel,dimms) @@ -597,25 +650,19 @@ extern "C" // Swap endianess to host format. l_dmbMfgId = le16toh(l_dmbMfgId); - FAPI_DBG ( "ddr4_get_efd: SPD DMB manufacturer ID = 0x%.4X, " - "expected DMB manufacturer ID = 0x%.4X", - l_dmbMfgId, - SPD_DDR4_EXPECTED_DMB_MFG_ID ); + FAPI_DBG ( "ddr4_get_efd: SPD DMB manufacturer ID = 0x%.4X", l_dmbMfgId); // Confirm the DMB manufacturer ID value is what is expected - FAPI_ASSERT( (SPD_DDR4_EXPECTED_DMB_MFG_ID == l_dmbMfgId), - fapi2::DDIMM_GET_EFD_UNSUPPORTED_DMB_MFG_ID(). - set_DMB_MFG_ID(static_cast<uint32_t>(l_dmbMfgId)). - set_EXPECTED(static_cast<uint32_t> - (SPD_DDR4_EXPECTED_DMB_MFG_ID)). - set_OCMB_CHIP_TARGET(i_ocmbFapi2Target). - set_VPD_TYPE(io_vpdInfo.iv_vpd_type). - set_DDR_TYPE(static_cast<uint32_t> - (i_spdBuffer[SPD_MEM_TYPE_ADDR])), - "ddr4_get_efd: SPD DMB manufacturer ID 0x%.4X is not the " - "expected DMB manufacturer ID 0x%.4X ", - l_dmbMfgId, - SPD_DDR4_EXPECTED_DMB_MFG_ID); + FAPI_ASSERT(check_valid_mfg_id(l_dmbMfgId), + fapi2::DDIMM_GET_EFD_UNSUPPORTED_DMB_MFG_ID(). + set_DMB_MFG_ID(static_cast<uint32_t>(l_dmbMfgId)). + set_OCMB_CHIP_TARGET(i_ocmbFapi2Target). + set_VPD_TYPE(io_vpdInfo.iv_vpd_type). + set_DDR_TYPE(static_cast<uint32_t> + (i_spdBuffer[SPD_MEM_TYPE_ADDR])), + "ddr4_get_efd: SPD DMB manufacturer ID 0x%.4X is not of " + "expected DMB manufacturer IDs MCHP: 0x%.4X or IBM: 0x%.4X", + l_dmbMfgId, SPD_DDR4_DMB_MFG_ID_MICROCHIP, SPD_DDR4_DMB_MFG_ID_IBM); // Set the outgoing DMB manufacturer ID io_vpdInfo.iv_dmb_mfg_id = l_dmbMfgId; @@ -623,29 +670,28 @@ extern "C" FAPI_DBG ( "ddr4_get_efd: SPD DMB manufacturer ID = 0x%.4X", io_vpdInfo.iv_dmb_mfg_id); - FAPI_DBG ( "ddr4_get_efd: SPD DMB revision = 0x%.2X, " - "expected DMB revision = 0x%.2X", - i_spdBuffer[SPD_DMB_REVISION_ADDR], - SPD_DDR4_EXPECTED_DMB_REVISION ); + l_dmb_revision = *reinterpret_cast<const uint8_t*>(&i_spdBuffer[SPD_DMB_REVISION_ADDR]); // Confirm that the DMB revision is what is expected - FAPI_ASSERT( (SPD_DDR4_EXPECTED_DMB_REVISION == - i_spdBuffer[SPD_DMB_REVISION_ADDR]), + FAPI_ASSERT( check_valid_dmb_revision(l_dmbMfgId, l_dmb_revision), fapi2::DDIMM_GET_EFD_UNSUPPORTED_DMB_REVISION(). set_DMB_REVISION(static_cast<uint32_t> - (SPD_DDR4_EXPECTED_DMB_REVISION)). - set_EXPECTED(static_cast<uint32_t>(SPD_DMB_REVISION_ADDR)). + (l_dmb_revision)). set_OCMB_CHIP_TARGET(i_ocmbFapi2Target). set_VPD_TYPE(io_vpdInfo.iv_vpd_type). set_DDR_TYPE(static_cast<uint32_t> (i_spdBuffer[SPD_MEM_TYPE_ADDR])), - "ddr4_get_efd: SPD DMB revision 0x%.2X is not the expected " - "revision 0x%.2X", - i_spdBuffer[SPD_DMB_REVISION_ADDR], - SPD_DDR4_EXPECTED_DMB_REVISION); + "ddr4_get_efd: SPD DMB revision 0x%.2X is not an expected revision: " + "IBM expected: 0x%.2X " + "MCHP expected: 0x%.2X or 0x%.2X or 0x%.2X", + l_dmb_revision, + SPD_DDR4_EXPECTED_DMB_REVISION_IBM, + SPD_DDR4_EXPECTED_DMB_REVISION_0_MICROCHIP, + SPD_DDR4_EXPECTED_DMB_REVISION_A0_MICROCHIP, + SPD_DDR4_EXPECTED_DMB_REVISION_A1_MICROCHIP); // Set the outgoing DMB revision - io_vpdInfo.iv_dmb_revision = SPD_DDR4_EXPECTED_DMB_REVISION; + io_vpdInfo.iv_dmb_revision = l_dmb_revision; FAPI_DBG ( "ddr4_get_efd: SPD DMB revision = 0x%.2X", io_vpdInfo.iv_dmb_revision); @@ -659,7 +705,7 @@ extern "C" // No need to swap endian, already in host format l_freqMask = ddrFrequencyToBitMask(io_vpdInfo.iv_omi_freq_mhz); - FAPI_DBG ( "ddr4_get_efd: Caller supplied frquency = %d", + FAPI_DBG ( "ddr4_get_efd: Caller supplied frequency = %d", io_vpdInfo.iv_omi_freq_mhz ); // Confirm that mapping the frequency succeeded @@ -667,6 +713,8 @@ extern "C" { // If no value for freq, then mapping of frequency was unsuccessful + // Note we don't want to produce FFDC if the ffdc_enabled flag is not set + // i.e. if we're just probing the EFD for its supported frequencies FAPI_ASSERT( ( !io_vpdInfo.iv_is_config_ffdc_enabled ), fapi2::DDIMM_GET_EFD_UNSUPPORTED_FREQUENCY(). set_UNSUPPORTED_FREQ(static_cast<uint32_t> @@ -695,7 +743,7 @@ extern "C" FAPI_TRY(fapi2::FAPI2_RC_FALSE); } - FAPI_DBG ("ddr4_get_efd: Caller supplied frquency = %d, " + FAPI_DBG ("ddr4_get_efd: Caller supplied frequency = %d, " "converted to frequency bit value mask = 0x%.4X", io_vpdInfo.iv_omi_freq_mhz, l_freqMask); @@ -707,6 +755,8 @@ extern "C" if ( !l_rankMask) { // If no value for MR, then mapping of MR was unsuccessful + // Note we don't want to produce FFDC if the ffdc_enabled flag is not set + // i.e. if we're just probing the EFD for its supported frequencies FAPI_ASSERT( ( !io_vpdInfo.iv_is_config_ffdc_enabled ), fapi2::DDIMM_GET_EFD_UNSUPPORTED_RANK(). set_UNSUPPORTED_RANK(static_cast<uint32_t> @@ -743,6 +793,36 @@ extern "C" //// Fourthly, find the EFD that matches the given frequency //// and master rank + // Check the master list of supported frequencies before walking + // through the EFDs + l_supportedSpeeds = *reinterpret_cast<const uint16_t*> + (i_spdBuffer + SPD_SUPPORTED_HOST_SPEEDS_ADDR); + l_supportedSpeeds = le16toh(l_supportedSpeeds); + + if (!(l_freqMask & l_supportedSpeeds)) + { + // Note we don't want to produce FFDC if the ffdc_enabled flag is not set + // i.e. if we're just probing the EFD for its supported frequencies + FAPI_ASSERT( !io_vpdInfo.iv_is_config_ffdc_enabled, + fapi2::DDIMM_UNSUPPORTED_FREQUENCY(). + set_UNSUPPORTED_FREQ(static_cast<uint32_t> + (io_vpdInfo.iv_omi_freq_mhz)). + set_SUPPORTED_FREQS(l_supportedSpeeds). + set_OCMB_CHIP_TARGET(i_ocmbFapi2Target). + set_VPD_TYPE(io_vpdInfo.iv_vpd_type). + set_DDR_TYPE(static_cast<uint32_t> + (i_spdBuffer[SPD_MEM_TYPE_ADDR])), + "Invalid frequency for this DIMM - request=%d, supported mask=%.4X", + io_vpdInfo.iv_omi_freq_mhz, l_supportedSpeeds ); + + // If unable to collect FFDC and assert, at least trace out and exit with false + FAPI_INF ("ddr4_get_efd: Unsupported frequency %d (frequency bit mask = 0x%.4X, " + "supported mask = 0x%.4X)", + io_vpdInfo.iv_omi_freq_mhz, l_freqMask, l_supportedSpeeds); + + FAPI_TRY(fapi2::FAPI2_RC_FALSE); + } + // Point to the beginning of the EFD meta data, AKA EFD[0] meta data. l_efdMetaDataPtr = i_spdBuffer + SPD_EFD_META_DATA_ADDR; @@ -810,12 +890,12 @@ extern "C" // If the 'is implemented flag' is true for the EFD, AND if the EFD // frequency mask contains the frequency mask we are looking for AND - // the EFD master rank matches the master rank we are looking for + // the EFD master rank bitmap includes the master rank we are looking for // then copy the EFD block for the caller. if ( (l_efdMetaDataNptr[SPD_EFD_META_DATA_EFD_BYTE_3_OFFSET] & SPD_EFD_META_DATA_EFD_IS_IMPLEMENTED_MASK) && (l_efdFreqMask & l_freqMask) && - (l_efdDataNptr[EFD_DDR4_MASTER_RANK_ADDR] == l_rankMask) ) + (l_efdDataNptr[EFD_DDR4_MASTER_RANK_ADDR] & l_rankMask) ) { // io_vpdInfo.iv_size and EFD block size compatibility // have been verified above @@ -863,6 +943,8 @@ extern "C" { // Did not find an EFD to match frequency and master rank criteria // Collect FFDC and assert if iv_is_config_ffdc_enabled is true + // Note we don't want to produce FFDC if the ffdc_enabled flag is not set + // i.e. if we're just probing the EFD for its supported frequencies FAPI_ASSERT( ( !io_vpdInfo.iv_is_config_ffdc_enabled ), fapi2::DDIMM_GET_EFD_EFD_NOT_FOUND(). set_FREQUENCY(io_vpdInfo.iv_omi_freq_mhz). diff --git a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C index 27b1877ba..b6412b206 100644 --- a/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C +++ b/src/import/chips/p9/procedures/hwp/customize/p9_xip_customize.C @@ -305,6 +305,7 @@ fapi2::ReturnCode writeMboxRegs ( MBOX_ATTR_WRITE (ATTR_PROC_EPS_WRITE_CYCLES_T2, FAPI_SYSTEM, i_image); MBOX_ATTR_WRITE (ATTR_LPC_CONSOLE_CNFG, i_procTarget, i_image); MBOX_ATTR_WRITE (ATTR_SBE_NVDIMM_IN_PORT, i_procTarget, i_image); + MBOX_ATTR_WRITE (ATTR_SMF_CONFIG, FAPI_SYSTEM, i_image); // for backwards compatiblity with images that don't contain // the OB/MC PLL bucket attributes, ensure that the item exists @@ -2614,8 +2615,9 @@ ReturnCode p9_xip_customize ( if ((uint32_t)l_fapiRc == RC_XIPC_IMAGE_WOULD_OVERFLOW) { - FAPI_INF("p9_xip_customize(): Image is full. Ran out of space appending VPD rings" - " to the .rings section"); + FAPI_INF("p9_xip_customize(): Image is full. Ran out of space appending VPD" + " rings to the .rings section. Now checking if min required cores" + " is satisfied."); // Check the bootCoreMask to determine if enough cores have been configured. uint8_t attrMinReqdEcs = 0; @@ -2655,11 +2657,14 @@ ReturnCode p9_xip_customize ( "Image buffer would overflow before reaching the minimum required" " number of EC boot cores" ); + fapi2::current_err = FAPI2_RC_SUCCESS; + } + else + { + fapi2::current_err = l_fapiRc; } - fapi2::current_err = l_fapiRc; goto fapi_try_exit; - } // More size code sanity checks of section and image sizes. diff --git a/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.C b/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.C new file mode 100644 index 000000000..843da913f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.C @@ -0,0 +1,253 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +//------------------------------------------------------------------------------ +/// @file exp_collect_explorer_log.C +/// +/// @brief Collects and adds Explorer logs to rc +//------------------------------------------------------------------------------ +// *HWP HW Owner : Matt Derksen +// *HWP HW Backup Owner : <> +// *HWP FW Owner : <> +// *HWP Level : 2 +// *HWP Consumed by : SE:HB +//------------------------------------------------------------------------------ + +#include <fapi2.H> +#include "exp_collect_explorer_log.H" +#include <exp_fw_log_data.H> + +struct explog_section_header_t +{ + uint16_t packet_num; // ordering byte (0 = first packet) + uint32_t offset_exp_log; // offset where data portion started in full explorer log + uint16_t error_data_size; // size of data portion following header + + explog_section_header_t() + : packet_num(0), + offset_exp_log(0), + error_data_size(0) + {} +} __attribute__((__packed__)); + +// 1st entry is most relevant traces so make it a small size so +// it won't be truncated from HWP error log +const size_t FIRST_PACKET_SIZE = 0x100; + +// Use a larger packet size for the rest of the remaining error data +// These aren't as important since they are older trace logs +const size_t FOLLOWING_PACKET_SIZE = 0x200; + +/** + * @brief Explorer Log type? + * + * The firmware maintains the log in a circular buffer in RAM (ACTIVE_LOG) and + * in the event of a processor exception, firmware assert, or other critical + * condition the firmware saves the data in RAM to SPI flash (SAVED_LOG). + * Having the log stored in non-volatile memory allows post-analysis + * of the log even if it requires a power-cycle to recover the system. + */ +enum exp_log_type : uint8_t +{ + ACTIVE_LOG = 1, // RAM error section + SAVED_LOG = 2 // SPI flash error section +}; + +/** + * @brief Main procedure to grab log traces from Explorer chip + * and append the trace data to HWP error (o_rc) + * + * @param[in] i_ocmb_chip - OCMB chip target + * @param[in] i_size - allowable total size (add entries upto this size) + * @param[in] i_log_type - what kind of explorer log to grab + * @param[out] o_rc - return code to add FFDC data to. + * + * @return FAPI2_RC_SUCCESS iff ok + */ +fapi2::ReturnCode exp_collect_explorer_logs(const fapi2::ffdc_t& i_ocmb_chip, + const fapi2::ffdc_t& i_size, + const exp_log_type i_log_type, + fapi2::ReturnCode& o_rc) +{ + fapi2::ReturnCode l_rc = fapi2::FAPI2_RC_SUCCESS; + + // This variable is reused multiple times to build up a unique section + // identifier to split the log data read from the OCMB before we add + // each section to the HWP error + explog_section_header_t l_header_meta; + + // target from which to grab the error log data + fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> l_target_ocmb = + *(reinterpret_cast<const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> *> + (i_ocmb_chip.ptr())); + + // How much explorer log data are we allowed to add to the HWP error? + uint32_t l_allowable_size = *(reinterpret_cast<const uint32_t*>(i_size.ptr())); + + std::vector<uint8_t>l_explorer_log_data; // full Explorer log data + fapi2::ffdc_t UNIT_FFDC_EXP_ERROR; // filled in for RC_EXPLORER_ERROR_LOG + + FAPI_INF( "exp_collect_explorer_logs: Entering ... " + "(log type: %s, max data size: 0x%04X)", + i_log_type == ACTIVE_LOG ? "Active" : "Saved", l_allowable_size ); + + if ( ACTIVE_LOG == i_log_type ) + { + FAPI_EXEC_HWP(l_rc, exp_active_log, l_target_ocmb, l_explorer_log_data); + } + else + { + FAPI_EXEC_HWP(l_rc, exp_saved_log, l_target_ocmb, l_explorer_log_data); + } + + if (l_rc != fapi2::FAPI2_RC_SUCCESS) + { + FAPI_ERR("exp_collect_explorer_logs: error 0x%04X from exp_%s_log", + (uint32_t)l_rc, i_log_type == ACTIVE_LOG ? "active" : "saved"); + } + else + { + // Variable to store how much Explorer data we have remaining + uint32_t l_explorer_bytes_left = l_explorer_log_data.size(); + + // Add this much explorer log data (as maximum amount, could be less) + l_header_meta.error_data_size = FIRST_PACKET_SIZE; + + // We read from the end since the most recent logs are the last + // entries returned in the full Explorer log data + auto l_end_ptr = l_explorer_log_data.end(); + + // This is where we start iterating through the Explorer log data + // and break it into sections that are added to the HWP error + while ( l_explorer_bytes_left ) + { + // ---------------------------------------------------------------- + // Calculate how much explorer data to add for this section entry + // ---------------------------------------------------------------- + // Verify there is enough space left in the allowable HWP error + // so we can add another full data section + if ( l_allowable_size > l_header_meta.error_data_size) + { + // We can add at least a packet of data, if we have that + // much to add + if (l_explorer_bytes_left < l_header_meta.error_data_size) + { + FAPI_INF("exp_collect_explorer_logs: %d) reduce packet size to include the last explorer log bytes" + "(l_explorer_bytes_left %d, Initial packet size %d)", l_header_meta.packet_num, + l_explorer_bytes_left, l_header_meta.error_data_size); + + // reduce the packet size to include the last explorer log bytes + l_header_meta.error_data_size = l_explorer_bytes_left; + } + + // else, have enough data and space, so add full data size + } + else if ( l_allowable_size ) // Any space left? + { + // Note: if here, we cannot add a full section size of data + + // Is allowable size remaining less than the explorer bytes available? + if ( l_allowable_size < l_explorer_bytes_left ) + { + // use up the rest of the allowable space available + FAPI_INF("exp_collect_explorer_logs: %d) use up rest of space available" + "(l_explorer_bytes_left %d, l_allowable_size %d)", l_header_meta.packet_num, + l_explorer_bytes_left, l_allowable_size); + l_header_meta.error_data_size = l_allowable_size; + } + else + { + // reduce the packet size to include the last explorer log bytes + l_header_meta.error_data_size = l_explorer_bytes_left; + } + } + else + { + // reached allowable size + break; + } + + // ---------------------------------------------------------------- + + // offset where the data is starting from out of the whole Explorer log data + l_header_meta.offset_exp_log = l_explorer_bytes_left - l_header_meta.error_data_size; + + FAPI_INF("exp_collect_explorer_logs: %d) starting offset 0x%08X " + "(data size: %d)", l_header_meta.packet_num, + l_header_meta.offset_exp_log, l_header_meta.error_data_size); + + // Adding header with meta data + auto const ptr = reinterpret_cast<uint8_t*>(&l_header_meta); + std::vector<uint8_t>l_error_log_entry ( ptr, ptr + sizeof(l_header_meta)); + + // Now append the explorer error section to the section entry + // Note: working backwards from the end of the Explorer log data + l_error_log_entry.insert( l_error_log_entry.end(), + l_end_ptr - l_header_meta.error_data_size, + l_end_ptr ); + + // Add the section entry to the HWP error log + UNIT_FFDC_EXP_ERROR.ptr() = l_error_log_entry.data(); + UNIT_FFDC_EXP_ERROR.size() = l_error_log_entry.size(); + + if (ACTIVE_LOG == i_log_type) + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_EXPLORER_ACTIVE_ERROR_LOG); + } + else + { + FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_EXPLORER_SAVED_ERROR_LOG); + } + + // Update to next packet of Explorer error log data + l_header_meta.packet_num++; + l_explorer_bytes_left -= l_header_meta.error_data_size; + l_end_ptr -= l_header_meta.error_data_size; // point to beginning of last data inserted + l_allowable_size -= l_header_meta.error_data_size; + l_header_meta.error_data_size = FOLLOWING_PACKET_SIZE; + } + } + + FAPI_INF("exp_collect_explorer_logs: Exiting ..."); + + return l_rc; +} + +/// See header +fapi2::ReturnCode exp_collect_explorer_active_log( + const fapi2::ffdc_t& i_ocmb_chip, + const fapi2::ffdc_t& i_size, + fapi2::ReturnCode& o_rc ) +{ + return exp_collect_explorer_logs(i_ocmb_chip, i_size, ACTIVE_LOG, o_rc); +} + +/// See header +fapi2::ReturnCode exp_collect_explorer_saved_log( + const fapi2::ffdc_t& i_ocmb_chip, + const fapi2::ffdc_t& i_size, + fapi2::ReturnCode& o_rc ) +{ + return exp_collect_explorer_logs(i_ocmb_chip, i_size, SAVED_LOG, o_rc); +} diff --git a/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.H b/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.H new file mode 100644 index 000000000..adba2eee2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.H @@ -0,0 +1,109 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/ffdc/exp_collect_explorer_log.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// @file exp_collect_explorer_log.H +/// +/// @brief Collects and adds Explorer debug logs to rc +// ---------------------------------------- +// *HWP HWP Owner: Matt Derksen <mderkse1@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB +// ---------------------------------------- +#ifndef _COLLECT_EXPLORER_LOG_H_ +#define _COLLECT_EXPLORER_LOG_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <return_code.H> +#include <error_info_defs.H> + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*exp_collect_explorer_active_log_FP_t)( + const fapi2::ffdc_t&, + const fapi2::ffdc_t&, + fapi2::ReturnCode& ); + +typedef fapi2::ReturnCode (*exp_collect_explorer_saved_log_FP_t)( + const fapi2::ffdc_t&, + const fapi2::ffdc_t&, + fapi2::ReturnCode& ); + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +extern "C" +{ +/// +/// @brief Procedure to grab active (RAM) log traces from Explorer chip +/// and add those traces to the HWP error +/// @param[in] i_ocmb_chip - OCMB chip target +/// @param[in] i_size - allowable total size (add entries upto this size) +/// @param[out] o_rc - return code to add FFDC data to. +/// +/// @return FAPI2_RC_SUCCESS iff ok +/// +/// NOTE: All input parameters must be of type fapi2::ffdc_t and converted +/// to the correct type inside the function. +/// + fapi2::ReturnCode exp_collect_explorer_active_log( + const fapi2::ffdc_t& i_ocmb_chip, + const fapi2::ffdc_t& i_size, + fapi2::ReturnCode& o_rc ); + + +/// +/// @brief Procedure to grab saved (SPI flash) log traces from Explorer chip +/// and add those traces to the HWP error +/// @param[in] i_ocmb_chip - OCMB chip target +/// @param[in] i_size - allowable total size (add entries upto this size) +/// @param[out] o_rc - return code to add FFDC data to. +/// +/// @return FAPI2_RC_SUCCESS iff ok +/// +/// NOTE: All input parameters must be of type fapi2::ffdc_t and converted +/// to the correct type inside the function. +/// + fapi2::ReturnCode exp_collect_explorer_saved_log( + const fapi2::ffdc_t& i_ocmb_chip, + const fapi2::ffdc_t& i_size, + fapi2::ReturnCode& o_rc ); + + +} // extern "C" + + +#endif // _COLLECT_EXPLORER_LOG_H_ diff --git a/src/import/chips/p9/procedures/hwp/ffdc/ffdc_includes.H b/src/import/chips/p9/procedures/hwp/ffdc/ffdc_includes.H index c84739fb4..2336e59bf 100644 --- a/src/import/chips/p9/procedures/hwp/ffdc/ffdc_includes.H +++ b/src/import/chips/p9/procedures/hwp/ffdc/ffdc_includes.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,4 +35,8 @@ #include <p9_collect_ppe_state.H> #include <p9_eq_clear_atomic_lock.H> #include <p9_collect_lpc_regs.H> + +// needed for collectFfdc to work for adding Explorer log data +#include <exp_collect_explorer_log.H> + #endif diff --git a/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_lpc_regs.C b/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_lpc_regs.C index 4e8ee34b2..f17dcffcb 100644 --- a/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_lpc_regs.C +++ b/src/import/chips/p9/procedures/hwp/ffdc/p9_collect_lpc_regs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,7 +32,7 @@ #include "p9_misc_scom_addresses.H" #include "p9_misc_scom_addresses_fld.H" -#include "../perv/p9_lpc_utils.H" +#include <p9_lpc_utils.H> static void lpc_dump( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip, diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp1_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp1_scom.C index 6f65f5fe5..896614802 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp1_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp1_scom.C @@ -149,6 +149,10 @@ fapi2::ReturnCode p9_fbc_cd_hp1_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_CORE_CEILING_RATIO, TGT1, l_TGT1_ATTR_PROC_FABRIC_CORE_CEILING_RATIO)); uint64_t l_def_CORE_CEILING_RATIO_8_8 = (l_TGT1_ATTR_PROC_FABRIC_CORE_CEILING_RATIO == ENUM_ATTR_PROC_FABRIC_CORE_CEILING_RATIO_RATIO_8_8); + fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS_Type l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS, TGT0, + l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS)); + uint64_t l_def_IS_AXONE = (l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS != literal_0); fapi2::buffer<uint64_t> l_scom_buffer; { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -1200,11 +1204,21 @@ fapi2::ReturnCode p9_fbc_cd_hp1_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC l_scom_buffer.insert<34, 8, 56, uint64_t>(literal_0b11111110 ); } - if (literal_1) + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<42, 2, 62, uint64_t>(literal_0b10 ); + } + + if (( ! l_def_IS_AXONE)) { l_scom_buffer.insert<42, 8, 56, uint64_t>(literal_0b11111110 ); } + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<44, 6, 58, uint64_t>(literal_0b000000 ); + } + if (literal_1) { l_scom_buffer.insert<50, 2, 62, uint64_t>(literal_0b01 ); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp2_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp2_scom.C index 42e21b5f9..456de5563 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp2_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp2_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,9 +40,11 @@ constexpr uint64_t literal_0b1111 = 0b1111; constexpr uint64_t literal_0b011 = 0b011; constexpr uint64_t literal_0b010 = 0b010; constexpr uint64_t literal_0b11111110 = 0b11111110; +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_0b10 = 0b10; +constexpr uint64_t literal_0b000000 = 0b000000; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b00 = 0b00; -constexpr uint64_t literal_0b10 = 0b10; fapi2::ReturnCode p9_fbc_cd_hp2_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) @@ -59,6 +61,10 @@ fapi2::ReturnCode p9_fbc_cd_hp2_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC fapi2::ATTR_PROC_FABRIC_X_LINKS_CNFG_Type l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_LINKS_CNFG, TGT0, l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG)); uint64_t l_def_NUM_X_LINKS_CFG = l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG; + fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS_Type l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS, TGT0, + l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS)); + uint64_t l_def_IS_AXONE = (l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS != literal_0); fapi2::buffer<uint64_t> l_scom_buffer; { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -184,11 +190,21 @@ fapi2::ReturnCode p9_fbc_cd_hp2_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC l_scom_buffer.insert<34, 8, 56, uint64_t>(literal_0b11111110 ); } - if (literal_1) + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<42, 2, 62, uint64_t>(literal_0b10 ); + } + + if (( ! l_def_IS_AXONE)) { l_scom_buffer.insert<42, 8, 56, uint64_t>(literal_0b11111110 ); } + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<44, 6, 58, uint64_t>(literal_0b000000 ); + } + if (literal_1) { l_scom_buffer.insert<50, 2, 62, uint64_t>(literal_0b01 ); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp3_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp3_scom.C index 9790095c3..3488465f2 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp3_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_cd_hp3_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,9 +40,11 @@ constexpr uint64_t literal_0b1 = 0b1; constexpr uint64_t literal_0b011 = 0b011; constexpr uint64_t literal_0b010 = 0b010; constexpr uint64_t literal_0b11111110 = 0b11111110; +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_0b10 = 0b10; +constexpr uint64_t literal_0b000000 = 0b000000; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b00 = 0b00; -constexpr uint64_t literal_0b10 = 0b10; fapi2::ReturnCode p9_fbc_cd_hp3_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) @@ -59,6 +61,10 @@ fapi2::ReturnCode p9_fbc_cd_hp3_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC fapi2::ATTR_PROC_FABRIC_X_LINKS_CNFG_Type l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_X_LINKS_CNFG, TGT0, l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG)); uint64_t l_def_NUM_X_LINKS_CFG = l_TGT0_ATTR_PROC_FABRIC_X_LINKS_CNFG; + fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS_Type l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS, TGT0, + l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS)); + uint64_t l_def_IS_AXONE = (l_TGT0_ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS != literal_0); fapi2::buffer<uint64_t> l_scom_buffer; { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) @@ -184,11 +190,21 @@ fapi2::ReturnCode p9_fbc_cd_hp3_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC l_scom_buffer.insert<34, 8, 56, uint64_t>(literal_0b11111110 ); } - if (literal_1) + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<42, 2, 62, uint64_t>(literal_0b10 ); + } + + if (( ! l_def_IS_AXONE)) { l_scom_buffer.insert<42, 8, 56, uint64_t>(literal_0b11111110 ); } + if (l_def_IS_AXONE) + { + l_scom_buffer.insert<44, 6, 58, uint64_t>(literal_0b000000 ); + } + if (literal_1) { l_scom_buffer.insert<50, 2, 62, uint64_t>(literal_0b01 ); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.C new file mode 100644 index 000000000..da89cd6ef --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.C @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9_fbc_ioo_dl_npu_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + + +fapi2::ReturnCode p9_fbc_ioo_dl_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT2) +{ + { + fapi2::ATTR_EC_Type l_chip_ec; + fapi2::ATTR_NAME_Type l_chip_id; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT1, l_chip_id)); + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT1, l_chip_ec)); + fapi2::ATTR_PROC_NPU_REGION_ENABLED_Type l_TGT1_ATTR_PROC_NPU_REGION_ENABLED; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU_REGION_ENABLED, TGT1, l_TGT1_ATTR_PROC_NPU_REGION_ENABLED)); + fapi2::ATTR_OPTICS_CONFIG_MODE_Type l_TGT0_ATTR_OPTICS_CONFIG_MODE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_OPTICS_CONFIG_MODE, TGT0, l_TGT0_ATTR_OPTICS_CONFIG_MODE)); + uint64_t l_def_OBUS_NV_ENABLED = ((l_TGT0_ATTR_OPTICS_CONFIG_MODE == fapi2::ENUM_ATTR_OPTICS_CONFIG_MODE_NV) + && l_TGT1_ATTR_PROC_NPU_REGION_ENABLED); + fapi2::buffer<uint64_t> l_scom_buffer; + { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x901080cull, l_scom_buffer )); + + if (l_def_OBUS_NV_ENABLED) + { + constexpr auto l_PB_IOO_LL0_CONFIG_NV0_NPU_ENABLED_ON = 0x1; + l_scom_buffer.insert<60, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV0_NPU_ENABLED_ON ); + } + + if (l_def_OBUS_NV_ENABLED) + { + constexpr auto l_PB_IOO_LL0_CONFIG_NV1_NPU_ENABLED_ON = 0x1; + l_scom_buffer.insert<61, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV1_NPU_ENABLED_ON ); + } + + if (l_def_OBUS_NV_ENABLED) + { + constexpr auto l_PB_IOO_LL0_CONFIG_NV2_NPU_ENABLED_ON = 0x1; + l_scom_buffer.insert<62, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV2_NPU_ENABLED_ON ); + } + + if (l_def_OBUS_NV_ENABLED) + { + constexpr auto l_PB_IOO_LL0_CONFIG_NV3_NPU_ENABLED_ON = 0x1; + l_scom_buffer.insert<63, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV3_NPU_ENABLED_ON ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x901080cull, l_scom_buffer)); + } + } + + }; +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.H new file mode 100644 index 000000000..144dc1165 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_npu_scom.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9_FBC_IOO_DL_NPU_SCOM_PROCEDURE_H_ +#define _INIT_P9_FBC_IOO_DL_NPU_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9_fbc_ioo_dl_npu_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_OBUS>&, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); + +extern "C" +{ + + fapi2::ReturnCode p9_fbc_ioo_dl_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT2); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C index f724cdb5a..384d9070f 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_ioo_dl_scom.C @@ -116,33 +116,6 @@ fapi2::ReturnCode p9_fbc_ioo_dl_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS { FAPI_TRY(fapi2::getScom( TGT0, 0x901080cull, l_scom_buffer )); - if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) - { - if (l_def_OBUS_NV_ENABLED) - { - constexpr auto l_PB_IOO_LL0_CONFIG_NV0_NPU_ENABLED_ON = 0x1; - l_scom_buffer.insert<60, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV0_NPU_ENABLED_ON ); - } - } - - if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) - { - if (l_def_OBUS_NV_ENABLED) - { - constexpr auto l_PB_IOO_LL0_CONFIG_NV1_NPU_ENABLED_ON = 0x1; - l_scom_buffer.insert<61, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV1_NPU_ENABLED_ON ); - } - } - - if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) - { - if (l_def_OBUS_NV_ENABLED) - { - constexpr auto l_PB_IOO_LL0_CONFIG_NV2_NPU_ENABLED_ON = 0x1; - l_scom_buffer.insert<62, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV2_NPU_ENABLED_ON ); - } - } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) @@ -179,15 +152,6 @@ fapi2::ReturnCode p9_fbc_ioo_dl_scom(const fapi2::Target<fapi2::TARGET_TYPE_OBUS } } - if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) - { - if (l_def_OBUS_NV_ENABLED) - { - constexpr auto l_PB_IOO_LL0_CONFIG_NV3_NPU_ENABLED_ON = 0x1; - l_scom_buffer.insert<63, 1, 63, uint64_t>(l_PB_IOO_LL0_CONFIG_NV3_NPU_ENABLED_ON ); - } - } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_no_hp_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_no_hp_scom.C index d368c5b07..44bc30c3f 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_no_hp_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_fbc_no_hp_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -128,6 +128,13 @@ fapi2::ReturnCode p9_fbc_no_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ constexpr auto l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 = 0x2aaaa; l_scom_buffer.insert<30, 6, 46, uint64_t>(l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 ); + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + constexpr auto l_PB_COM_PB_CFG_NP2_EN_ON = 0x7; + l_scom_buffer.insert<49, 1, 61, uint64_t>(l_PB_COM_PB_CFG_NP2_EN_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x501180aull, l_scom_buffer)); } { @@ -168,6 +175,13 @@ fapi2::ReturnCode p9_fbc_no_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ constexpr auto l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 = 0x2aaaa; l_scom_buffer.insert<30, 6, 52, uint64_t>(l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 ); + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + constexpr auto l_PB_COM_PB_CFG_NP2_EN_ON = 0x7; + l_scom_buffer.insert<49, 1, 62, uint64_t>(l_PB_COM_PB_CFG_NP2_EN_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x5011c0aull, l_scom_buffer)); } { @@ -1710,6 +1724,13 @@ fapi2::ReturnCode p9_fbc_no_hp_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_ constexpr auto l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 = 0x2aaaa; l_scom_buffer.insert<30, 6, 58, uint64_t>(l_PB_COM_PB_CFG_LCL_HW_MARK_CNT_42 ); + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + constexpr auto l_PB_COM_PB_CFG_NP2_EN_ON = 0x7; + l_scom_buffer.insert<49, 1, 63, uint64_t>(l_PB_COM_PB_CFG_NP2_EN_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x501200aull, l_scom_buffer)); } diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C index e36053acd..f81fb7abd 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_npu_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,12 +44,14 @@ constexpr uint64_t literal_0x200 = 0x200; constexpr uint64_t literal_0x300 = 0x300; constexpr uint64_t literal_0xFFF = 0xFFF; constexpr uint64_t literal_0x8 = 0x8; +constexpr uint64_t literal_0x7E = 0x7E; constexpr uint64_t literal_0x0 = 0x0; constexpr uint64_t literal_0xE000000000000000 = 0xE000000000000000; constexpr uint64_t literal_0x0000740000000000 = 0x0000740000000000; constexpr uint64_t literal_0x7F60B04500AC0000 = 0x7F60B04500AC0000; constexpr uint64_t literal_0xAAA70A55F0000000 = 0xAAA70A55F0000000; constexpr uint64_t literal_0x5550740000000000 = 0x5550740000000000; +constexpr uint64_t literal_0x0FFE6FC00FF1B000 = 0x0FFE6FC00FF1B000; constexpr uint64_t literal_0x009A48180F01FFFF = 0x009A48180F01FFFF; constexpr uint64_t literal_0xFFFFFFFFFFFFFFFF = 0xFFFFFFFFFFFFFFFF; constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000; @@ -61,8 +63,8 @@ constexpr uint64_t literal_0x0000F4000FFFFFFF = 0x0000F4000FFFFFFF; constexpr uint64_t literal_0xFFF70A5DF0000000 = 0xFFF70A5DF0000000; constexpr uint64_t literal_0x000801A200000000 = 0x000801A200000000; constexpr uint64_t literal_0xFFFF0BFFF0000000 = 0xFFFF0BFFF0000000; -constexpr uint64_t literal_0xF000003FF00C0FFF = 0xF000003FF00C0FFF; -constexpr uint64_t literal_0x0000100000024000 = 0x0000100000024000; +constexpr uint64_t literal_0xF001803FF00C0FFF = 0xF001803FF00C0FFF; +constexpr uint64_t literal_0x0FFE7FC00FF3F000 = 0x0FFE7FC00FF3F000; constexpr uint64_t literal_0xF = 0xF; constexpr uint64_t literal_0b001000 = 0b001000; constexpr uint64_t literal_0b000001 = 0b000001; @@ -70,7 +72,6 @@ constexpr uint64_t literal_0x66 = 0x66; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0x67 = 0x67; constexpr uint64_t literal_0x4B = 0x4B; -constexpr uint64_t literal_0x7E = 0x7E; constexpr uint64_t literal_0x009A48180F63FFFF = 0x009A48180F63FFFF; constexpr uint64_t literal_0x009A48180F03FFFF = 0x009A48180F03FFFF; constexpr uint64_t literal_0x8005000200100000 = 0x8005000200100000; @@ -133,6 +134,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } @@ -218,6 +229,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } @@ -303,6 +324,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } @@ -388,6 +419,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } @@ -558,6 +599,32 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) { + FAPI_TRY(fapi2::getScom( TGT0, 0x3011e2aull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x3011e2aull, l_scom_buffer)); + } + } + { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x3011e5aull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x3011e5aull, l_scom_buffer)); + } + } + { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { FAPI_TRY(fapi2::getScom( TGT0, 0x3011ef5ull, l_scom_buffer )); if ((l_def_NVLINK_ACTIVE == literal_1)) @@ -641,6 +708,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) { + FAPI_TRY(fapi2::getScom( TGT0, 0x3011fb0ull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE6FC00FF1B000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x3011fb0ull, l_scom_buffer)); + } + } + { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { FAPI_TRY(fapi2::getScom( TGT0, 0x3012003ull, l_scom_buffer )); if ((l_def_NVLINK_ACTIVE == literal_1)) @@ -751,7 +831,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF000003FF00C0FFF ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF001803FF00C0FFF ); } else if ((l_def_NVLINK_ACTIVE == literal_0)) { @@ -781,7 +861,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000100000024000 ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE7FC00FF3F000 ); } FAPI_TRY(fapi2::putScom(TGT0, 0x3012087ull, l_scom_buffer)); @@ -878,6 +958,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -1862,6 +1955,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -2590,6 +2696,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -2955,6 +3074,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -5526,22 +5658,22 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { FAPI_TRY(fapi2::getScom( TGT0, 0x501138aull, l_scom_buffer )); - if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) + || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) + && (l_chip_ec == 0x13)) ) { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x7F60B04500AC0000 ); + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); } } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) - || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) - && (l_chip_ec == 0x13)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x10)) ) { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x7F60B04500AC0000 ); } } @@ -5575,6 +5707,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& } } { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x50113b0ull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE6FC00FF1B000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x50113b0ull, l_scom_buffer)); + } + } + { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) @@ -5670,6 +5815,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -6378,6 +6536,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -6970,6 +7141,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + } + + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } } @@ -7090,6 +7274,16 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { + l_scom_buffer.insert<26, 1, 63, uint64_t>(literal_0x1 ); + } + + if (literal_1) + { + l_scom_buffer.insert<6, 1, 63, uint64_t>(literal_0x1 ); + } + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { l_scom_buffer.insert<32, 1, 63, uint64_t>(literal_0x1 ); } @@ -7230,11 +7424,14 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { FAPI_TRY(fapi2::getScom( TGT0, 0x501158aull, l_scom_buffer )); - if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) + || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) + && (l_chip_ec == 0x13)) ) { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<1, 3, 61, uint64_t>(literal_0x4 ); + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); } } @@ -7242,7 +7439,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<4, 10, 54, uint64_t>(literal_0x100 ); + l_scom_buffer.insert<1, 3, 61, uint64_t>(literal_0x4 ); } } @@ -7250,7 +7447,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<14, 10, 54, uint64_t>(literal_0x200 ); + l_scom_buffer.insert<4, 10, 54, uint64_t>(literal_0x100 ); } } @@ -7258,18 +7455,15 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<24, 10, 54, uint64_t>(literal_0x300 ); + l_scom_buffer.insert<14, 10, 54, uint64_t>(literal_0x200 ); } } - if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) - && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) - || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) - && (l_chip_ec == 0x13)) ) + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + l_scom_buffer.insert<24, 10, 54, uint64_t>(literal_0x300 ); } } @@ -7300,6 +7494,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& } } { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501162aull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x501162aull, l_scom_buffer)); + } + } + { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) @@ -7321,6 +7528,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& } } { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501165aull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<32, 8, 56, uint64_t>(literal_0x7E ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x501165aull, l_scom_buffer)); + } + } + { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) @@ -7449,6 +7669,22 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& } } { + if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) + && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) + || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) + && (l_chip_ec == 0x13)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5011700ull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE6FC00FF1B000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5011700ull, l_scom_buffer)); + } + } + { if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) { FAPI_TRY(fapi2::getScom( TGT0, 0x5011733ull, l_scom_buffer )); @@ -7514,6 +7750,19 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& } } { + if (((l_chip_id == 0x7) && (l_chip_ec == 0x10)) ) + { + FAPI_TRY(fapi2::getScom( TGT0, 0x50117b0ull, l_scom_buffer )); + + if ((l_def_NVLINK_ACTIVE == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE6FC00FF1B000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x50117b0ull, l_scom_buffer)); + } + } + { if (((l_chip_id == 0x5) && (l_chip_ec == 0x20)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x21)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x22)) || ((l_chip_id == 0x5) && (l_chip_ec == 0x23)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x10)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x11)) || ((l_chip_id == 0x6) && (l_chip_ec == 0x12)) || ((l_chip_id == 0x6) @@ -7794,7 +8043,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF000003FF00C0FFF ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF001803FF00C0FFF ); } else if ((l_def_NVLINK_ACTIVE == literal_0)) { @@ -7806,7 +8055,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF000003FF00C0FFF ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF001803FF00C0FFF ); } else if ((l_def_NVLINK_ACTIVE == literal_0)) { @@ -7862,7 +8111,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000100000024000 ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE7FC00FF3F000 ); } } @@ -7870,7 +8119,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& { if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000100000024000 ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE7FC00FF3F000 ); } } @@ -8003,7 +8252,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF000003FF00C0FFF ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xF001803FF00C0FFF ); } else if ((l_def_NVLINK_ACTIVE == literal_0)) { @@ -8033,7 +8282,7 @@ fapi2::ReturnCode p9_npu_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& if ((l_def_NVLINK_ACTIVE == literal_1)) { - l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000100000024000 ); + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0FFE7FC00FF3F000 ); } FAPI_TRY(fapi2::putScom(TGT0, 0x5013d47ull, l_scom_buffer)); diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C index 1442041f7..fc00dc42a 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g0_scom.C @@ -43,10 +43,13 @@ constexpr uint64_t literal_0b0000011 = 0b0000011; constexpr uint64_t literal_0b000000 = 0b000000; constexpr uint64_t literal_0b100111 = 0b100111; constexpr uint64_t literal_0b1010 = 0b1010; +constexpr uint64_t literal_0b00 = 0b00; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b11 = 0b11; +constexpr uint64_t literal_0b01010000 = 0b01010000; constexpr uint64_t literal_0b01011100 = 0b01011100; constexpr uint64_t literal_0b01100110 = 0b01100110; +constexpr uint64_t literal_0b00110111 = 0b00110111; constexpr uint64_t literal_0b00111101 = 0b00111101; constexpr uint64_t literal_0b01000100 = 0b01000100; constexpr uint64_t literal_0b0010000 = 0b0010000; @@ -61,7 +64,6 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000; constexpr uint64_t literal_0b01111111 = 0b01111111; constexpr uint64_t literal_0b10 = 0b10; constexpr uint64_t literal_0b1100 = 0b1100; -constexpr uint64_t literal_0b00 = 0b00; constexpr uint64_t literal_0b01110 = 0b01110; fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0, @@ -80,6 +82,9 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_CHAN_EQ, TGT0, l_TGT0_ATTR_IO_XBUS_CHAN_EQ)); fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297)); + fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND_Type l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND, TGT2, + l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)); fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE)); uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1); @@ -3213,7 +3218,15 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& { FAPI_TRY(fapi2::getScom( TGT0, 0x8008c00006010c3full, l_scom_buffer )); - l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 ); + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 ); + } + else if (( true )) + { + l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 ); + } + constexpr auto l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF ); l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 ); @@ -3238,7 +3251,11 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& { FAPI_TRY(fapi2::getScom( TGT0, 0x8008d00006010c3full, l_scom_buffer )); - if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 ); + } + else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) { l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 ); } @@ -3247,7 +3264,11 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 ); } - if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 ); + } + else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) { l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 ); } @@ -3377,6 +3398,12 @@ fapi2::ReturnCode p9_xbus_g0_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& constexpr auto l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0; l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX0_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF ); + + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x800b800006010c3full, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C index c8052a2ca..ef24c37e6 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9_xbus_g1_scom.C @@ -44,10 +44,13 @@ constexpr uint64_t literal_0b000000 = 0b000000; constexpr uint64_t literal_0b100111 = 0b100111; constexpr uint64_t literal_0b000001 = 0b000001; constexpr uint64_t literal_0b1010 = 0b1010; +constexpr uint64_t literal_0b00 = 0b00; constexpr uint64_t literal_0b01 = 0b01; constexpr uint64_t literal_0b11 = 0b11; +constexpr uint64_t literal_0b01010000 = 0b01010000; constexpr uint64_t literal_0b01011100 = 0b01011100; constexpr uint64_t literal_0b01100110 = 0b01100110; +constexpr uint64_t literal_0b00110111 = 0b00110111; constexpr uint64_t literal_0b00111101 = 0b00111101; constexpr uint64_t literal_0b01000100 = 0b01000100; constexpr uint64_t literal_0b0010000 = 0b0010000; @@ -62,7 +65,6 @@ constexpr uint64_t literal_0b0000000000000000 = 0b0000000000000000; constexpr uint64_t literal_0b01111111 = 0b01111111; constexpr uint64_t literal_0b10 = 0b10; constexpr uint64_t literal_0b1100 = 0b1100; -constexpr uint64_t literal_0b00 = 0b00; constexpr uint64_t literal_0b01110 = 0b01110; fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& TGT0, @@ -81,6 +83,9 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_CHAN_EQ, TGT0, l_TGT0_ATTR_IO_XBUS_CHAN_EQ)); fapi2::ATTR_CHIP_EC_FEATURE_HW393297_Type l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW393297, TGT2, l_TGT2_ATTR_CHIP_EC_FEATURE_HW393297)); + fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND_Type l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND, TGT2, + l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND)); fapi2::ATTR_IO_XBUS_MASTER_MODE_Type l_TGT0_ATTR_IO_XBUS_MASTER_MODE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_XBUS_MASTER_MODE, TGT0, l_TGT0_ATTR_IO_XBUS_MASTER_MODE)); uint64_t l_def_is_master = (l_TGT0_ATTR_IO_XBUS_MASTER_MODE == literal_1); @@ -3212,9 +3217,22 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& FAPI_TRY(fapi2::putScom(TGT0, 0x8008402006010c3full, l_scom_buffer)); } { + FAPI_TRY(fapi2::getScom( TGT0, 0x8008c00006010c3full, l_scom_buffer )); + + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b00 ); + } + else if (( true )) + { + l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x8008c00006010c3full, l_scom_buffer)); + } + { FAPI_TRY(fapi2::getScom( TGT0, 0x8008c02006010c3full, l_scom_buffer )); - l_scom_buffer.insert<48, 2, 62, uint64_t>(literal_0b01 ); constexpr auto l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PEAK_TUNE_OFF ); l_scom_buffer.insert<57, 2, 62, uint64_t>(literal_0b11 ); @@ -3239,7 +3257,11 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& { FAPI_TRY(fapi2::getScom( TGT0, 0x8008d02006010c3full, l_scom_buffer )); - if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01010000 ); + } + else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) { l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01011100 ); } @@ -3248,7 +3270,11 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& l_scom_buffer.insert<48, 8, 56, uint64_t>(literal_0b01100110 ); } - if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00110111 ); + } + else if ((l_TGT0_ATTR_IO_XBUS_CHAN_EQ & ENUM_ATTR_IO_XBUS_CHAN_EQ_LOWER_VGA_GAIN_TARGET)) { l_scom_buffer.insert<56, 8, 56, uint64_t>(literal_0b00111101 ); } @@ -3378,6 +3404,12 @@ fapi2::ReturnCode p9_xbus_g1_scom(const fapi2::Target<fapi2::TARGET_TYPE_XBUS>& constexpr auto l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF = 0x0; l_scom_buffer.insert<60, 1, 63, uint64_t>(l_IOF1_RX_RX1_RXCTL_DATASM_DATASM_REGS_RX_CTL_DATASM_CLKDIST_PDWN_OFF ); + + if (l_TGT2_ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0b0010 ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x800b802006010c3full, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.C new file mode 100644 index 000000000..f35a145d7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.C @@ -0,0 +1,72 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9a_int_scan.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_0b1 = 0b1; + +fapi2::ReturnCode p9a_int_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0) +{ + { + fapi2::ATTR_EC_Type l_chip_ec; + fapi2::ATTR_NAME_Type l_chip_id; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id)); + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); + fapi2::ATTR_CHIP_EC_FEATURE_HW388874_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW388874; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW388874, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW388874)); + bool l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_update = false; + fapi2::variable_buffer l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS(1); + fapi2::variable_buffer l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_CARE(1); + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW388874 == literal_0)) + { + constexpr auto l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_ON = 0x1; + l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS.insertFromRight<uint64_t>(l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_ON, 0, 1); + l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_update = true; + } + + if ( l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "BRIDGE.PSIHB.ESB_OR_LSI_INTERRUPTS", l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS, + l_BRIDGE_PSIHB_ESB_OR_LSI_INTERRUPTS_CARE)); + } + + fapi2::variable_buffer l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS(1); + fapi2::variable_buffer l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS_CARE(1); + l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS.insertFromRight<uint64_t>(literal_0b1, 0, 1); + l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "INT.INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS", + l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS, l_INT_INT_VC_LBS6_ARX_CS_AXONE_DISABLE_CILOAD_ORDERINGS_CARE)); + + }; +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/memory_size.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.H index ddcb6f94a..470e17d7d 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/memory_size.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.H @@ -1,7 +1,7 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/eff_config/memory_size.C $ */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ @@ -22,3 +22,26 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9A_INT_SCAN_PROCEDURE_H_ +#define _INIT_P9A_INT_SCAN_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + +#ifdef IFCOMPILER_PLAT +#define INITFILE_PROCEDURE \ + p9a_int_scan(TGT0); +#endif + +typedef fapi2::ReturnCode (*p9a_int_scan_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +extern "C" +{ + + fapi2::ReturnCode p9a_int_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.mk b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.mk new file mode 100644 index 000000000..6fcb57af4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.mk @@ -0,0 +1,36 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scan.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +PROCEDURE=p9a_int_scan +lib$(PROCEDURE)_COMMONFLAGS+=-DFAPI_SUPPORT_SPY_AS_STRING=1 +$(call BUILD_PROCEDURE) + +PROCEDURE=p9a_int_scan_ifCompiler +lib$(PROCEDURE)_COMMONFLAGS+=-DFAPI_SUPPORT_SPY_AS_STRING=1 +lib$(PROCEDURE)_COMMONFLAGS+=-DIFCOMPILER_PLAT=1 +FAPI=2_IFCOMPILER +OBJS+=p9a_int_scan.o +lib$(PROCEDURE)_LIBPATH=$(LIBPATH)/ifCompiler +lib$(PROCEDURE)_COMMONFLAGS+=-fno-var-tracking-assignments +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.C new file mode 100644 index 000000000..aa6143eb6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.C @@ -0,0 +1,228 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9a_int_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_1 = 1; +constexpr uint64_t literal_0b10 = 0b10; +constexpr uint64_t literal_0b1000000 = 0b1000000; +constexpr uint64_t literal_0x2000005C04028000 = 0x2000005C04028000; +constexpr uint64_t literal_0x2000005C040281C3 = 0x2000005C040281C3; +constexpr uint64_t literal_0x0000005C040081C3 = 0x0000005C040081C3; +constexpr uint64_t literal_0x0000000000000000 = 0x0000000000000000; +constexpr uint64_t literal_0x9554021F80110FCF = 0x9554021F80110FCF; +constexpr uint64_t literal_0x9554021F80110E0C = 0x9554021F80110E0C; +constexpr uint64_t literal_0x18 = 0x18; +constexpr uint64_t literal_0x010003FF00100020 = 0x010003FF00100020; +constexpr uint64_t literal_0x050043EF00100020 = 0x050043EF00100020; +constexpr uint64_t literal_0xD8DFB200DFAFFFD7 = 0xD8DFB200DFAFFFD7; +constexpr uint64_t literal_0xFADFBB8CFFAFFFD7 = 0xFADFBB8CFFAFFFD7; +constexpr uint64_t literal_0x0002000410000000 = 0x0002000410000000; +constexpr uint64_t literal_0x0002000610000000 = 0x0002000610000000; +constexpr uint64_t literal_0x6262220242160000 = 0x6262220242160000; +constexpr uint64_t literal_0x5BBF = 0x5BBF; + +fapi2::ReturnCode p9a_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) +{ + { + fapi2::ATTR_EC_Type l_chip_ec; + fapi2::ATTR_NAME_Type l_chip_id; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT0, l_chip_id)); + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT0, l_chip_ec)); + fapi2::ATTR_PROC_FABRIC_PUMP_MODE_Type l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_FABRIC_PUMP_MODE, TGT1, l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID)); + fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID_Type l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID, TGT1, l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID)); + fapi2::ATTR_SMF_CONFIG_Type l_TGT1_ATTR_SMF_CONFIG; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, TGT1, l_TGT1_ATTR_SMF_CONFIG)); + fapi2::ATTR_CHIP_EC_FEATURE_HW426891_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW426891, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891)); + fapi2::ATTR_CHIP_EC_FEATURE_HW411637_Type l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW411637, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637)); + fapi2::ATTR_CHIP_EC_FEATURE_P9N_INT_DD10_Type l_TGT0_ATTR_CHIP_EC_FEATURE_P9N_INT_DD10; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9N_INT_DD10, TGT0, l_TGT0_ATTR_CHIP_EC_FEATURE_P9N_INT_DD10)); + fapi2::buffer<uint64_t> l_scom_buffer; + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501300aull, l_scom_buffer )); + + l_scom_buffer.insert<0, 1, 63, uint64_t>(literal_0 ); + + if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP)) + { + l_scom_buffer.insert<1, 1, 63, uint64_t>(literal_1 ); + } + else if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE)) + { + l_scom_buffer.insert<1, 1, 63, uint64_t>(literal_0 ); + } + + l_scom_buffer.insert<5, 4, 60, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID ); + l_scom_buffer.insert<9, 3, 61, uint64_t>(l_TGT1_ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID ); + + if ((l_TGT1_ATTR_SMF_CONFIG == fapi2::ENUM_ATTR_SMF_CONFIG_ENABLED)) + { + l_scom_buffer.insert<12, 2, 62, uint64_t>(literal_0b10 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x501300aull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013020ull, l_scom_buffer )); + + l_scom_buffer.insert<25, 7, 57, uint64_t>(literal_0b1000000 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x5013020ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013021ull, l_scom_buffer )); + + if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_GROUP)) + { + l_scom_buffer.insert<49, 1, 63, uint64_t>(literal_1 ); + } + else if ((l_TGT1_ATTR_PROC_FABRIC_PUMP_MODE == fapi2::ENUM_ATTR_PROC_FABRIC_PUMP_MODE_CHIP_IS_NODE)) + { + l_scom_buffer.insert<49, 1, 63, uint64_t>(literal_0 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013021ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013033ull, l_scom_buffer )); + + if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637 == literal_1) && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_0))) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x2000005C04028000 ); + } + else if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637 == literal_1) && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_1))) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x2000005C040281C3 ); + } + else if (((l_TGT0_ATTR_CHIP_EC_FEATURE_HW411637 == literal_0) && (l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_1))) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000005C040081C3 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013033ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013036ull, l_scom_buffer )); + + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0000000000000000 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x5013036ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013037ull, l_scom_buffer )); + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x9554021F80110FCF ); + } + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_P9N_INT_DD10 == literal_0)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x9554021F80110E0C ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013037ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013130ull, l_scom_buffer )); + + l_scom_buffer.insert<2, 6, 58, uint64_t>(literal_0x18 ); + l_scom_buffer.insert<10, 6, 58, uint64_t>(literal_0x18 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x5013130ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013140ull, l_scom_buffer )); + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_0)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x010003FF00100020 ); + } + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x050043EF00100020 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013140ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013141ull, l_scom_buffer )); + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_0)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xD8DFB200DFAFFFD7 ); + } + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0xFADFBB8CFFAFFFD7 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013141ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013178ull, l_scom_buffer )); + + if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_0)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0002000410000000 ); + } + else if ((l_TGT0_ATTR_CHIP_EC_FEATURE_HW426891 == literal_1)) + { + l_scom_buffer.insert<0, 64, 0, uint64_t>(literal_0x0002000610000000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x5013178ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501320eull, l_scom_buffer )); + + l_scom_buffer.insert<0, 48, 0, uint64_t>(literal_0x6262220242160000 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x501320eull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x5013214ull, l_scom_buffer )); + + l_scom_buffer.insert<16, 16, 48, uint64_t>(literal_0x5BBF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x5013214ull, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x501322bull, l_scom_buffer )); + + l_scom_buffer.insert<58, 6, 58, uint64_t>(literal_0x18 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x501322bull, l_scom_buffer)); + } + + }; +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.H new file mode 100644 index 000000000..50fb3b02e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9A_INT_SCOM_PROCEDURE_H_ +#define _INIT_P9A_INT_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9a_int_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); + +extern "C" +{ + + fapi2::ReturnCode p9a_int_scom(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1); + +} + +#endif diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/00gem_common.mk b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.mk index 15fcba892..8242855ad 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/00gem_common.mk +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.mk @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/import/chips/ocmb/gemini/procedures/hwp/memory/00gem_common.mk $ +# $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_int_scom.mk $ # # OpenPOWER HostBoot Project # @@ -22,3 +22,6 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +PROCEDURE=p9a_int_scom +lib$(PROCEDURE)_COMMONFLAGS+=-fno-var-tracking-assignments +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.C index 974ffb124..887cafdca 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.C @@ -30,8 +30,25 @@ using namespace fapi2; constexpr uint64_t literal_8 = 8; +constexpr uint64_t literal_1 = 1; +constexpr uint64_t literal_12 = 12; +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_0b0100 = 0b0100; +constexpr uint64_t literal_28 = 28; +constexpr uint64_t literal_0x1 = 0x1; +constexpr uint64_t literal_4 = 4; +constexpr uint64_t literal_6 = 6; +constexpr uint64_t literal_0b1100111111111111111111111 = 0b1100111111111111111111111; +constexpr uint64_t literal_24 = 24; +constexpr uint64_t literal_0x3 = 0x3; +constexpr uint64_t literal_0x5 = 0x5; +constexpr uint64_t literal_0x7 = 0x7; +constexpr uint64_t literal_0x26 = 0x26; +constexpr uint64_t literal_0x33 = 0x33; +constexpr uint64_t literal_0x40 = 0x40; -fapi2::ReturnCode p9a_mcc_omi_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0) +fapi2::ReturnCode p9a_mcc_omi_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1) { { fapi2::ATTR_EC_Type l_chip_ec; @@ -70,6 +87,773 @@ fapi2::ReturnCode p9a_mcc_omi_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_C FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC23.CHAN3.ATCL.CL.CLSCOM.MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT", l_MC23_CHAN0_ATCL_CL_CLSCOM_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT, l_MC23_CHAN0_ATCL_CL_CLSCOM_MCPERF0_WR_RSVD_LOWER_OR_STATIC_LIMIT_CARE)); + uint64_t l_def_ENABLE_AMO_CLEAN_LINES = literal_1; + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN(1); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE(1); + + if ((l_def_ENABLE_AMO_CLEAN_LINES == literal_1)) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_ON = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_ON, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCAMOC_ENABLE_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCAMOC_ENABLE_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCAMOC_ENABLE_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCAMOC_ENABLE_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN(6); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE(6); + + if ((l_def_ENABLE_AMO_CLEAN_LINES == literal_1)) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN.insertFromRight<uint64_t>(literal_12, 0, 6); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE.insertFromRight<uint64_t>(0x3f, 0, 6); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_NUM_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_NUM_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_NUM_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_NUM_CLEAN", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_CLEAN_CARE)); + } + + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M(4); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE(4); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M.insertFromRight<uint64_t>(literal_0, 0, 4); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE.insertFromRight<uint64_t>(0xf, 0, 4); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_ALT_M", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_ALT_M", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_ALT_M", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_ALT_M", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_ALT_M_CARE)); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL(4); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE(4); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL.insertFromRight<uint64_t>(literal_0b0100, 0, 4); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE.insertFromRight<uint64_t>(0xf, 0, 4); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_SQ_LFSR_CNTL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_SQ_LFSR_CNTL_CARE)); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF(5); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE(5); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF.insertFromRight<uint64_t>(literal_28, 0, 5); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE.insertFromRight<uint64_t>(0x1f, 0, 5); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_NUM_RMW_BUF", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_NUM_RMW_BUF_CARE)); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON.insertFromRight<uint64_t>(literal_0x1, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_JITTER_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_JITTER_EPSILON_CARE)); + fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0)); + uint64_t l_def_MC_EPSILON_CFG_T0 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 + literal_6) / literal_4); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON.insertFromRight<uint64_t>(l_def_MC_EPSILON_CFG_T0, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_LOCAL_NODE_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_LOCAL_NODE_EPSILON_CARE)); + fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1)); + uint64_t l_def_MC_EPSILON_CFG_T1 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 + literal_6) / literal_4); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON.insertFromRight<uint64_t>(l_def_MC_EPSILON_CFG_T1, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_NEAR_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_NEAR_NODAL_EPSILON_CARE)); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON.insertFromRight<uint64_t>(l_def_MC_EPSILON_CFG_T1, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_GROUP_EPSILON_CARE)); + fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2)); + uint64_t l_def_MC_EPSILON_CFG_T2 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 + literal_6) / literal_4); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON.insertFromRight<uint64_t>(l_def_MC_EPSILON_CFG_T2, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_REMOTE_NODAL_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_REMOTE_NODAL_EPSILON_CARE)); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON(8); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE(8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON.insertFromRight<uint64_t>(l_def_MC_EPSILON_CFG_T2, 0, 8); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE.insertFromRight<uint64_t>(0xff, 0, 8); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE)); + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCEPSQ_VECTOR_GROUP_EPSILON", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCEPSQ_VECTOR_GROUP_EPSILON_CARE)); + uint64_t l_def_ENABLE_AMO_CACHING = literal_1; + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES(25); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE(25); + + if (l_def_ENABLE_AMO_CACHING) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES.insertFromRight<uint64_t> + (literal_0b1100111111111111111111111, 0, 25); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE.insertFromRight<uint64_t>(0x1ffffff, 0, 25); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCAMOC_WRTO_AMO_COLLISION_RULES", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_WRTO_AMO_COLLISION_RULES_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE(3); + + if (l_def_ENABLE_AMO_CACHING) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCAMOC_AMO_SIZE_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT(6); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE(6); + + if (l_def_ENABLE_AMO_CACHING) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT.insertFromRight<uint64_t>(literal_24, 0, 6); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE.insertFromRight<uint64_t>(0x3f, 0, 6); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF0_AMO_LIMIT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF0_AMO_LIMIT_CARE)); + } + + bool l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update = false; + fapi2::variable_buffer l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE(1); + fapi2::variable_buffer l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE(1); + + if (l_def_ENABLE_AMO_CACHING) + { + constexpr auto l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_ON = 0x1; + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE.insertFromRight<uint64_t>(l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_ON, 0, 1); + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update = true; + } + + if ( l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MCP.CHAN0.WRITE.NEW_WRITE_64B_MODE", l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE, + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE)); + } + + if ( l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MCP.CHAN1.WRITE.NEW_WRITE_64B_MODE", l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE, + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE)); + } + + if ( l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MCP.CHAN2.WRITE.NEW_WRITE_64B_MODE", l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE, + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE)); + } + + if ( l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MCP.CHAN3.WRITE.NEW_WRITE_64B_MODE", l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE, + l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL(1); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE(1); + + if (l_def_ENABLE_AMO_CACHING) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_ON = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_ON, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF3_AMO_LIMIT_SEL", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_CARE)); + } + + uint64_t l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC = literal_1; + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE(3); + + if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0.insertFromRight<uint64_t>(literal_0x1, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE0_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE(3); + + if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1.insertFromRight<uint64_t>(literal_0x3, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE1_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE(3); + + if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2.insertFromRight<uint64_t>(literal_0x5, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE2_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE(3); + + if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3.insertFromRight<uint64_t>(literal_0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF2_PF_DROP_VALUE3", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3, l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF2_PF_DROP_VALUE3_CARE)); + } + + uint64_t l_def_ENABLE_MCBUSY = literal_1; + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS(1); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE(1); + + if (l_def_ENABLE_MCBUSY) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCBUSYQ_ENABLE_BUSY_COUNTERS", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT(3); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE(3); + + if (l_def_ENABLE_MCBUSY) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE.insertFromRight<uint64_t>(0x7, 0, 3); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0(10); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE(10); + + if (l_def_ENABLE_MCBUSY) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0.insertFromRight<uint64_t>(literal_0x26, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE.insertFromRight<uint64_t>(0x3ff, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD0", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD0_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1(10); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE(10); + + if (l_def_ENABLE_MCBUSY) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1.insertFromRight<uint64_t>(literal_0x33, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE.insertFromRight<uint64_t>(0x3ff, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD1", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD1_CARE)); + } + + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2(10); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE(10); + + if (l_def_ENABLE_MCBUSY) + { + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2.insertFromRight<uint64_t>(literal_0x40, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE.insertFromRight<uint64_t>(0x3ff, 0, 10); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCBUSYQ_BUSY_COUNTER_THRESHOLD2", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_THRESHOLD2_CARE)); + } + + fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM)); + bool l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update = false; + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY(1); + fapi2::variable_buffer l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE(1); + + if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF)) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON = 0x1; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update = true; + } + else if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON)) + { + constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF = 0x0; + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY.insertFromRight<uint64_t> + (l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE.insertFromRight<uint64_t>(0x1, 0, 1); + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update = true; + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN0.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN1.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN2.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE)); + } + + if ( l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_update) + { + FAPI_TRY(fapi2::putSpyWithCare(TGT0, "MC01.CHAN3.ATCL.CL.CLSCOM.MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY", + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY, + l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_CARE)); + } }; fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.H b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.H index 7ba8bd967..cd0857ff7 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.H +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scan.H @@ -32,15 +32,17 @@ #ifdef IFCOMPILER_PLAT #define INITFILE_PROCEDURE \ - p9a_mcc_omi_scan(TGT0); + p9a_mcc_omi_scan(TGT0, TGT1); #endif -typedef fapi2::ReturnCode (*p9a_mcc_omi_scan_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); +typedef fapi2::ReturnCode (*p9a_mcc_omi_scan_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&); extern "C" { - fapi2::ReturnCode p9a_mcc_omi_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0); + fapi2::ReturnCode p9a_mcc_omi_scan(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1); } diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scom.C index 7f8143749..aee57fe52 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mcc_omi_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -29,28 +29,14 @@ using namespace fapi2; -constexpr uint64_t literal_1 = 1; -constexpr uint64_t literal_24 = 24; -constexpr uint64_t literal_12 = 12; -constexpr uint64_t literal_0 = 0; -constexpr uint64_t literal_0b0100 = 0b0100; -constexpr uint64_t literal_28 = 28; -constexpr uint64_t literal_0x1 = 0x1; -constexpr uint64_t literal_0x3 = 0x3; -constexpr uint64_t literal_0x5 = 0x5; -constexpr uint64_t literal_0x7 = 0x7; -constexpr uint64_t literal_0b1100111111111111111111111 = 0b1100111111111111111111111; -constexpr uint64_t literal_4 = 4; -constexpr uint64_t literal_6 = 6; -constexpr uint64_t literal_0x26 = 0x26; -constexpr uint64_t literal_0x33 = 0x33; -constexpr uint64_t literal_0x40 = 0x40; constexpr uint64_t literal_0b100000 = 0b100000; constexpr uint64_t literal_0b0001 = 0b0001; constexpr uint64_t literal_0b1000000 = 0b1000000; constexpr uint64_t literal_0b011000 = 0b011000; +constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_7 = 7; constexpr uint64_t literal_0b1 = 0b1; +constexpr uint64_t literal_4 = 4; constexpr uint64_t literal_6363 = 6363; constexpr uint64_t literal_10000 = 10000; constexpr uint64_t literal_4500 = 4500; @@ -59,8 +45,10 @@ constexpr uint64_t literal_5800 = 5800; constexpr uint64_t literal_5 = 5; constexpr uint64_t literal_8181 = 8181; constexpr uint64_t literal_7000 = 7000; +constexpr uint64_t literal_6 = 6; constexpr uint64_t literal_9090 = 9090; constexpr uint64_t literal_8000 = 8000; +constexpr uint64_t literal_0 = 0; constexpr uint64_t literal_0b0000110000 = 0b0000110000; fapi2::ReturnCode p9a_mcc_omi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& TGT0, @@ -71,21 +59,6 @@ fapi2::ReturnCode p9a_mcc_omi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& fapi2::ATTR_NAME_Type l_chip_id; FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT3, l_chip_id)); FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT3, l_chip_ec)); - uint64_t l_def_ENABLE_AMO_CACHING = literal_1; - uint64_t l_def_ENABLE_AMO_CLEAN_LINES = literal_1; - uint64_t l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC = literal_1; - fapi2::ATTR_PROC_EPS_READ_CYCLES_T0_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T0, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0)); - uint64_t l_def_MC_EPSILON_CFG_T0 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T0 + literal_6) / literal_4); - fapi2::ATTR_PROC_EPS_READ_CYCLES_T1_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T1, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1)); - uint64_t l_def_MC_EPSILON_CFG_T1 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T1 + literal_6) / literal_4); - fapi2::ATTR_PROC_EPS_READ_CYCLES_T2_Type l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_EPS_READ_CYCLES_T2, TGT1, l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2)); - uint64_t l_def_MC_EPSILON_CFG_T2 = ((l_TGT1_ATTR_PROC_EPS_READ_CYCLES_T2 + literal_6) / literal_4); - uint64_t l_def_ENABLE_MCBUSY = literal_1; - fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM)); uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1; fapi2::ATTR_IS_SIMULATION_Type l_TGT1_ATTR_IS_SIMULATION; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT1, l_TGT1_ATTR_IS_SIMULATION)); @@ -99,137 +72,6 @@ fapi2::ReturnCode p9a_mcc_omi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& uint64_t l_def_ENABLE_HWFM = literal_1; fapi2::buffer<uint64_t> l_scom_buffer; { - FAPI_TRY(fapi2::getScom( TGT0, 0x5010823ull, l_scom_buffer )); - - if (l_def_ENABLE_AMO_CACHING) - { - l_scom_buffer.insert<22, 6, 58, uint64_t>(literal_24 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x5010823ull, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x5010824ull, l_scom_buffer )); - - if ((l_def_ENABLE_AMO_CLEAN_LINES == literal_1)) - { - l_scom_buffer.insert<44, 6, 58, uint64_t>(literal_12 ); - } - - l_scom_buffer.insert<40, 4, 60, uint64_t>(literal_0 ); - l_scom_buffer.insert<28, 4, 60, uint64_t>(literal_0b0100 ); - l_scom_buffer.insert<50, 5, 59, uint64_t>(literal_28 ); - - if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) - { - l_scom_buffer.insert<0, 3, 61, uint64_t>(literal_0x1 ); - } - - if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) - { - l_scom_buffer.insert<3, 3, 61, uint64_t>(literal_0x3 ); - } - - if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) - { - l_scom_buffer.insert<6, 3, 61, uint64_t>(literal_0x5 ); - } - - if (l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC) - { - l_scom_buffer.insert<9, 3, 61, uint64_t>(literal_0x7 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x5010824ull, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x5010825ull, l_scom_buffer )); - - if ((l_def_ENABLE_AMO_CLEAN_LINES == literal_1)) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_ON = 0x1; - l_scom_buffer.insert<0, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_ENABLE_CLEAN_ON ); - } - - if (l_def_ENABLE_AMO_CACHING) - { - l_scom_buffer.insert<4, 25, 39, uint64_t>(literal_0b1100111111111111111111111 ); - } - - if (l_def_ENABLE_AMO_CACHING) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA = 0x1; - l_scom_buffer.insert<29, 3, 61, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCAMOC_AMO_SIZE_SELECT_128B_RW_64B_DATA ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x5010825ull, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x5010826ull, l_scom_buffer )); - - l_scom_buffer.insert<0, 8, 56, uint64_t>(literal_0x1 ); - l_scom_buffer.insert<8, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T0 ); - l_scom_buffer.insert<16, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T1 ); - l_scom_buffer.insert<24, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T1 ); - l_scom_buffer.insert<32, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T2 ); - l_scom_buffer.insert<40, 8, 56, uint64_t>(l_def_MC_EPSILON_CFG_T2 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x5010826ull, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x5010827ull, l_scom_buffer )); - - if (l_def_ENABLE_MCBUSY) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON = 0x1; - l_scom_buffer.insert<0, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_ENABLE_BUSY_COUNTERS_ON ); - } - - if (l_def_ENABLE_MCBUSY) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES = 0x1; - l_scom_buffer.insert<1, 3, 61, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT_1024_CYCLES ); - } - - if (l_def_ENABLE_MCBUSY) - { - l_scom_buffer.insert<4, 10, 54, uint64_t>(literal_0x26 ); - } - - if (l_def_ENABLE_MCBUSY) - { - l_scom_buffer.insert<14, 10, 54, uint64_t>(literal_0x33 ); - } - - if (l_def_ENABLE_MCBUSY) - { - l_scom_buffer.insert<24, 10, 54, uint64_t>(literal_0x40 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x5010827ull, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x501082bull, l_scom_buffer )); - - if (l_def_ENABLE_AMO_CACHING) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_ON = 0x1; - l_scom_buffer.insert<45, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_AMO_LIMIT_SEL_ON ); - } - - if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_OFF)) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON = 0x1; - l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_ON ); - } - else if ((l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM == fapi2::ENUM_ATTR_ENABLE_MEM_EARLY_DATA_SCOM_ON)) - { - constexpr auto l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF = 0x0; - l_scom_buffer.insert<43, 1, 63, uint64_t>(l_MC01_CHAN0_ATCL_CL_CLSCOM_MCPERF3_ENABLE_CP_M_MDI0_LOCAL_ONLY_OFF ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x501082bull, l_scom_buffer)); - } - { FAPI_TRY(fapi2::getScom( TGT0, 0x701090aull, l_scom_buffer )); l_scom_buffer.insert<2, 6, 58, uint64_t>(literal_0b100000 ); @@ -307,17 +149,6 @@ fapi2::ReturnCode p9a_mcc_omi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& l_scom_buffer.insert<48, 10, 54, uint64_t>(literal_0b0000110000 ); FAPI_TRY(fapi2::putScom(TGT0, 0x7010a13ull, l_scom_buffer)); } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x7012348ull, l_scom_buffer )); - - if (l_def_ENABLE_AMO_CACHING) - { - constexpr auto l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_ON = 0x1; - l_scom_buffer.insert<9, 1, 63, uint64_t>(l_MCP_CHAN0_WRITE_NEW_WRITE_64B_MODE_ON ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x7012348ull, l_scom_buffer)); - } }; fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mi_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mi_scom.C index 20b65bd74..fafc20414 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_mi_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_mi_scom.C @@ -32,6 +32,8 @@ using namespace fapi2; constexpr uint64_t literal_7 = 7; constexpr uint64_t literal_1 = 1; constexpr uint64_t literal_0x19 = 0x19; +constexpr uint64_t literal_0b1111000000 = 0b1111000000; +constexpr uint64_t literal_0b0111111 = 0b0111111; constexpr uint64_t literal_0b0000000000001000 = 0b0000000000001000; constexpr uint64_t literal_0b011 = 0b011; constexpr uint64_t literal_0b01 = 0b01; @@ -43,6 +45,8 @@ fapi2::ReturnCode p9a_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, uint64_t l_def_ENABLE_PREFETCH_DROP_PROMOTE_BASIC = literal_1; fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM_Type l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_ENABLE_MEM_EARLY_DATA_SCOM, TGT1, l_TGT1_ATTR_ENABLE_MEM_EARLY_DATA_SCOM)); + fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY_Type l_TGT1_ATTR_MEM_MIRROR_PLACEMENT_POLICY; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, TGT1, l_TGT1_ATTR_MEM_MIRROR_PLACEMENT_POLICY)); uint64_t l_def_ENABLE_AMO_CACHING = literal_1; uint64_t l_def_ENABLE_MCU_TIMEOUTS = literal_1; fapi2::buffer<uint64_t> l_scom_buffer; @@ -91,6 +95,22 @@ fapi2::ReturnCode p9a_mi_scom(const fapi2::Target<fapi2::TARGET_TYPE_MI>& TGT0, l_scom_buffer.insert<4, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_ENABLE_ECRESP_ON ); } + l_scom_buffer.insert<15, 10, 54, uint64_t>(literal_0b1111000000 ); + l_scom_buffer.insert<25, 7, 57, uint64_t>(literal_0b0111111 ); + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_FORCE_COMMANDLIST_VALID_ON = 0x1; + l_scom_buffer.insert<5, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_FORCE_COMMANDLIST_VALID_ON ); + + if ((l_TGT1_ATTR_MEM_MIRROR_PLACEMENT_POLICY == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_MEM_MAP_MODE_ON = 0x1; + l_scom_buffer.insert<36, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_MEM_MAP_MODE_ON ); + } + else if ((l_TGT1_ATTR_MEM_MIRROR_PLACEMENT_POLICY == fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL)) + { + constexpr auto l_MC01_PBI01_SCOMFIR_MCMODE0_MEM_MAP_MODE_OFF = 0x0; + l_scom_buffer.insert<36, 1, 63, uint64_t>(l_MC01_PBI01_SCOMFIR_MCMODE0_MEM_MAP_MODE_OFF ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x5010811ull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_init_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_init_scom.C index 3801b25b9..68c8df463 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_init_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_init_scom.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,6 +40,8 @@ fapi2::ReturnCode p9a_omi_init_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_7, TGT0, l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_7)); fapi2::ATTR_PROC_ENABLE_DL_TMPL_4_Type l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_4; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_4, TGT0, l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_4)); + fapi2::ATTR_PROC_ENABLE_DL_TMPL_1_Type l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_1; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_ENABLE_DL_TMPL_1, TGT0, l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_1)); fapi2::ATTR_PROC_TMPL_0_PACING_Type l_TGT0_ATTR_PROC_TMPL_0_PACING; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_TMPL_0_PACING, TGT0, l_TGT0_ATTR_PROC_TMPL_0_PACING)); fapi2::ATTR_PROC_TMPL_1_PACING_Type l_TGT0_ATTR_PROC_TMPL_1_PACING; @@ -64,6 +66,12 @@ fapi2::ReturnCode p9a_omi_init_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& l_scom_buffer.insert<6, 1, 63, uint64_t>(l_MCP_CHAN0_DSTL_DSTLCFG_TMPL4_DISABLE_ON ); } + if ((l_TGT0_ATTR_PROC_ENABLE_DL_TMPL_1 == fapi2::ENUM_ATTR_PROC_ENABLE_DL_TMPL_1_DISABLED)) + { + constexpr auto l_MCP_CHAN0_DSTL_DSTLCFG_TMPL1_DIS_ON = 0x1; + l_scom_buffer.insert<3, 1, 63, uint64_t>(l_MCP_CHAN0_DSTL_DSTLCFG_TMPL1_DIS_ON ); + } + FAPI_TRY(fapi2::putScom(TGT0, 0x701090bull, l_scom_buffer)); } { diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.C index 67b67cd85..94a44a309 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.C @@ -36,23 +36,8 @@ constexpr uint64_t literal_0b10000 = 0b10000; constexpr uint64_t literal_0b1011 = 0b1011; constexpr uint64_t literal_0b1010 = 0b1010; constexpr uint64_t literal_0b1100 = 0b1100; -constexpr uint64_t literal_0b000000 = 0b000000; -constexpr uint64_t literal_0x0 = 0x0; -constexpr uint64_t literal_0b010 = 0b010; -constexpr uint64_t literal_0b001 = 0b001; -constexpr uint64_t literal_0b0010 = 0b0010; -constexpr uint64_t literal_0b0001 = 0b0001; -constexpr uint64_t literal_0b101 = 0b101; -constexpr uint64_t literal_0b100 = 0b100; -constexpr uint64_t literal_0b0000 = 0b0000; -constexpr uint64_t literal_0b110 = 0b110; -constexpr uint64_t literal_0b00 = 0b00; -constexpr uint64_t literal_0b01110 = 0b01110; -constexpr uint64_t literal_0b0010101 = 0b0010101; -constexpr uint64_t literal_0b0010110 = 0b0010110; -constexpr uint64_t literal_0b1000110 = 0b1000110; - -fapi2::ReturnCode p9a_omi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>& TGT0, + +fapi2::ReturnCode p9a_omi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2) { { @@ -66,2172 +51,652 @@ fapi2::ReturnCode p9a_omi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>& uint64_t l_def_IS_SIM = (l_TGT1_ATTR_IS_SIMULATION == literal_1); fapi2::buffer<uint64_t> l_scom_buffer; { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000000701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000010701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000020701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000030701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000040701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000050701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000060701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000070701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000080701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000090701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000090701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000a0701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000a0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000b0701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_2_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000b0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000c0701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000c0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000d0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000000701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000d0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000e0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000010701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000e0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000000f0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000020701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_3_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000000f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000030701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000040701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_4_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000110701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000120701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000050701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_0_RXPACK_RD_SLICE_5_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000120701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000130701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000060701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_4_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000130701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000140701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800000070701183full, l_scom_buffer )); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); if (l_def_IS_HW) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); } else if (l_def_IS_SIM) { constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; + l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_0_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); + (l_MCP_OMI2_IOO_CPLT_RX0_RXPACKS_1_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); } l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000140701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800000070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000150701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_1_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000150701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000160701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_2_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800000170701103full, l_scom_buffer )); - - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF = 0x0; - l_scom_buffer.insert<53, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_5_OFF ); - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_6_OFF ); - - if (l_def_IS_HW) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF = 0x0; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_OFF ); - } - else if (l_def_IS_SIM) - { - constexpr auto - l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON = 0x1; - l_scom_buffer.insert<55, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXPACKS_5_RXPACK_RD_SLICE_3_RX_DAC_REGS_RX_DAC_REGS_RX_PL_DATA_DAC_SPARE_MODE_7_ON ); - } - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800000170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028000701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028010701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028020701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028030701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028040701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028050701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028060701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028070701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028080701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028090701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028090701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280a0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280a0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280b0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280b0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280c0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028000701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280c0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280d0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028010701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280d0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280e0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028020701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280e0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000280f0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028030701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000280f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028040701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028050701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028110701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028120701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028060701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028120701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028130701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800028070701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028130701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028140701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028140701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028150701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028150701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028160701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800028170701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800028170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030000701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030010701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030020701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030030701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030040701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030050701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030060701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030070701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030070701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800028070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030080701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030000701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030080701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030090701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030010701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030090701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300a0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030020701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300a0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300b0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030030701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300b0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300c0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030040701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300c0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300d0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030050701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300d0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300e0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030060701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300e0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000300f0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800030070701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000300f0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030100701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030100701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030110701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030110701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030120701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030120701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030130701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030130701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030140701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030140701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030150701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030150701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030160701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800030170701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800030170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098000701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098010701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098020701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098030701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098030701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800030070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098040701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098000701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098040701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098050701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098010701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098050701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098060701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098020701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098060701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098070701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098030701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098070701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098080701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098040701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098080701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098090701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098050701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098090701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980a0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098060701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980a0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980b0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800098070701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980b0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800098070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980c0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980c0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980d0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980d0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980e0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980e0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000980f0701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000980f0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098100701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098100701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098110701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098110701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098120701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098120701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098130701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098130701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098140701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098140701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098150701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098150701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098160701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800098170701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800098170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0000701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0010701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0020701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0030701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0040701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0050701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0060701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0070701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0080701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0090701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0090701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00a0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00a0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00b0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00b0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00c0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00c0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00d0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00d0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00e0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00e0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a00f0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0000701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a00f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0010701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0020701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0110701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0120701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0030701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0120701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0130701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0040701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0130701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0140701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0050701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0140701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0150701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0060701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0150701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0160701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0070701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000a0170701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0000701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0010701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0020701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0030701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0040701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0050701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0060701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0070701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0080701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0090701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0090701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000a0070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00a0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0000701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00a0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00b0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0010701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00b0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00c0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0020701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00c0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00d0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0030701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00d0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00e0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0040701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00e0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c00f0701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0050701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c00f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0060701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0070701183full, l_scom_buffer )); l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0110701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0120701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0120701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0130701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0130701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0140701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0140701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0150701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0150701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0160701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0160701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c0170701103full, l_scom_buffer )); - - l_scom_buffer.insert<52, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<57, 5, 59, uint64_t>(literal_0b10000 ); - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b1011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8000701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8010701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8020701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8030701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8040701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8050701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8060701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8070701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8080701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8090701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8090701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80a0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80a0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80b0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80b0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80c0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80c0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80d0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80d0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80e0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80e0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c80f0701103full, l_scom_buffer )); - - l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c80f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c0070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8000701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8010701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8110701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8120701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8020701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8120701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8130701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8030701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8130701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8140701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8040701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8140701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8150701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8050701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8150701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8160701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8060701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8160701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8170701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x8000c8070701183full, l_scom_buffer )); l_scom_buffer.insert<53, 4, 60, uint64_t>(literal_0b1010 ); l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b0011 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228000701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228010701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228010701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228020701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228020701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228030701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228030701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228040701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228040701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228050701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228050701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228060701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228060701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228070701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228070701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228080701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228080701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228090701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228090701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280a0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280a0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280b0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280b0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280c0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280c0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280d0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280d0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280e0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280e0701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x8002280f0701103full, l_scom_buffer )); - - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x8002280f0701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x8000c8070701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228100701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228000701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228100701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228000701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228110701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228010701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228110701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228010701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228120701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228020701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228120701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228020701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228130701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228030701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228130701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228030701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228140701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228040701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228140701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228040701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228150701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228050701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228150701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228050701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228160701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228060701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228160701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228060701183full, l_scom_buffer)); } { - FAPI_TRY(fapi2::getScom( TGT0, 0x800228170701103full, l_scom_buffer )); + FAPI_TRY(fapi2::getScom( TGT0, 0x800228070701183full, l_scom_buffer )); l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b1100 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800228170701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800800000701103full, l_scom_buffer )); - - constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_4_OFF = 0x0; - l_scom_buffer.insert<52, 1, 63, uint64_t>(l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_4_OFF ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800800000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800808000701103full, l_scom_buffer )); - - l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000000 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800808000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800818000701103full, l_scom_buffer )); - - constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_REQ_DL_MASK_OFF = 0x0; - l_scom_buffer.insert<54, 1, 63, uint64_t>(l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_REQ_DL_MASK_OFF ); - constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_ABORT_DL_MASK_OFF = 0x0; - l_scom_buffer.insert<57, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_ABORT_DL_MASK_OFF ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800818000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800830000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800830000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800840000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0x0 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800840000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800858000701103full, l_scom_buffer )); - - if (l_def_IS_HW) - { - l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b010 ); - } - else if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b001 ); - } - - if (l_def_IS_HW) - { - l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b010 ); - } - else if (l_def_IS_SIM) - { - l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b001 ); - } - - if (l_def_IS_HW) - { - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0010 ); - } - else if (l_def_IS_SIM) - { - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0001 ); - } - - l_scom_buffer.insert<54, 3, 61, uint64_t>(literal_0b101 ); - l_scom_buffer.insert<57, 3, 61, uint64_t>(literal_0b101 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800858000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800860000701103full, l_scom_buffer )); - - l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b010 ); - l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b010 ); - l_scom_buffer.insert<54, 3, 61, uint64_t>(literal_0b010 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800860000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800868000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_HW) - { - l_scom_buffer.insert<60, 3, 61, uint64_t>(literal_0b100 ); - } - else if (l_def_IS_SIM) - { - l_scom_buffer.insert<60, 3, 61, uint64_t>(literal_0b010 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800868000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800878000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0000 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0000 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800878000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800880000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0000 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0000 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800880000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800888000701103full, l_scom_buffer )); - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); - } - - if (l_def_IS_SIM) - { - l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0x0 ); - } - - FAPI_TRY(fapi2::putScom(TGT0, 0x800888000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800970000701103full, l_scom_buffer )); - - constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON = 0x1; - l_scom_buffer.insert<48, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON ); - constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF = 0x0; - l_scom_buffer.insert<51, 1, 63, uint64_t> - (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800970000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800988000701103full, l_scom_buffer )); - - l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b110 ); - l_scom_buffer.insert<51, 2, 62, uint64_t>(literal_0b00 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800988000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800c0c000701103full, l_scom_buffer )); - - l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000000 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800c0c000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800f1c000701103full, l_scom_buffer )); - - l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b01110 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800f1c000701103full, l_scom_buffer)); - } - { - FAPI_TRY(fapi2::getScom( TGT0, 0x800f2c000701103full, l_scom_buffer )); - - if (l_def_IS_HW) - { - l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b0010101 ); - } - else if (l_def_IS_SIM) - { - l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b0010110 ); - } - - l_scom_buffer.insert<55, 7, 57, uint64_t>(literal_0b1000110 ); - FAPI_TRY(fapi2::putScom(TGT0, 0x800f2c000701103full, l_scom_buffer)); + FAPI_TRY(fapi2::putScom(TGT0, 0x800228070701183full, l_scom_buffer)); } }; diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.H index 447304e4f..1bfe9e07a 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.H +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omi_io_scom.H @@ -31,13 +31,13 @@ #include <fapi2.H> -typedef fapi2::ReturnCode (*p9a_omi_io_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>&, +typedef fapi2::ReturnCode (*p9a_omi_io_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_OMI>&, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); extern "C" { - fapi2::ReturnCode p9a_omi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>& TGT0, + fapi2::ReturnCode p9a_omi_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& TGT0, const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2); } diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C new file mode 100644 index 000000000..6cf208fa3 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C @@ -0,0 +1,299 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#include "p9a_omic_io_scom.H" +#include <stdint.h> +#include <stddef.h> +#include <fapi2.H> + +using namespace fapi2; + +constexpr uint64_t literal_0b000000 = 0b000000; +constexpr uint64_t literal_1 = 1; +constexpr uint64_t literal_0x0 = 0x0; +constexpr uint64_t literal_0 = 0; +constexpr uint64_t literal_0b010 = 0b010; +constexpr uint64_t literal_0b001 = 0b001; +constexpr uint64_t literal_0b0010 = 0b0010; +constexpr uint64_t literal_0b0001 = 0b0001; +constexpr uint64_t literal_0b101 = 0b101; +constexpr uint64_t literal_0b100 = 0b100; +constexpr uint64_t literal_0b0000 = 0b0000; +constexpr uint64_t literal_0b110 = 0b110; +constexpr uint64_t literal_0b00 = 0b00; +constexpr uint64_t literal_0b01110 = 0b01110; +constexpr uint64_t literal_0b0010101 = 0b0010101; +constexpr uint64_t literal_0b0010110 = 0b0010110; +constexpr uint64_t literal_0b1000110 = 0b1000110; + +fapi2::ReturnCode p9a_omic_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2) +{ + { + fapi2::ATTR_EC_Type l_chip_ec; + fapi2::ATTR_NAME_Type l_chip_id; + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, TGT2, l_chip_id)); + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_EC, TGT2, l_chip_ec)); + fapi2::ATTR_IS_SIMULATION_Type l_TGT1_ATTR_IS_SIMULATION; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, TGT1, l_TGT1_ATTR_IS_SIMULATION)); + uint64_t l_def_IS_SIM = (l_TGT1_ATTR_IS_SIMULATION == literal_1); + uint64_t l_def_IS_HW = (l_TGT1_ATTR_IS_SIMULATION == literal_0); + fapi2::buffer<uint64_t> l_scom_buffer; + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800800000701103full, l_scom_buffer )); + + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_4_OFF = 0x0; + l_scom_buffer.insert<52, 1, 63, uint64_t>(l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_PG_SPARE_MODE_4_OFF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800800000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800808000701103full, l_scom_buffer )); + + l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000000 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800808000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800818000701103full, l_scom_buffer )); + + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_REQ_DL_MASK_OFF = 0x0; + l_scom_buffer.insert<54, 1, 63, uint64_t>(l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_REQ_DL_MASK_OFF ); + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_ABORT_DL_MASK_OFF = 0x0; + l_scom_buffer.insert<57, 1, 63, uint64_t> + (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RECAL_ABORT_DL_MASK_OFF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800818000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800830000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800830000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800840000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0x0 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800840000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800858000701103full, l_scom_buffer )); + + if (l_def_IS_HW) + { + l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b010 ); + } + else if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b001 ); + } + + if (l_def_IS_HW) + { + l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b010 ); + } + else if (l_def_IS_SIM) + { + l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b001 ); + } + + if (l_def_IS_HW) + { + l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0010 ); + } + else if (l_def_IS_SIM) + { + l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0b0001 ); + } + + l_scom_buffer.insert<54, 3, 61, uint64_t>(literal_0b101 ); + l_scom_buffer.insert<57, 3, 61, uint64_t>(literal_0b101 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800858000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800860000701103full, l_scom_buffer )); + + l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b010 ); + l_scom_buffer.insert<51, 3, 61, uint64_t>(literal_0b010 ); + l_scom_buffer.insert<54, 3, 61, uint64_t>(literal_0b010 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800860000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800868000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_HW) + { + l_scom_buffer.insert<60, 3, 61, uint64_t>(literal_0b100 ); + } + else if (l_def_IS_SIM) + { + l_scom_buffer.insert<60, 3, 61, uint64_t>(literal_0b010 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800868000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800878000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0000 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800878000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800880000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<60, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0b0000 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0b0000 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800880000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800888000701103full, l_scom_buffer )); + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<56, 4, 60, uint64_t>(literal_0x0 ); + } + + if (l_def_IS_SIM) + { + l_scom_buffer.insert<52, 4, 60, uint64_t>(literal_0x0 ); + } + + FAPI_TRY(fapi2::putScom(TGT0, 0x800888000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800970000701103full, l_scom_buffer )); + + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON = 0x1; + l_scom_buffer.insert<48, 1, 63, uint64_t> + (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_CTLE_1ST_LATCH_OFFSET_CAL_ON ); + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF = 0x0; + l_scom_buffer.insert<51, 1, 63, uint64_t> + (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_RC_ENABLE_AUTO_RECAL_OFF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800970000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800978000701103full, l_scom_buffer )); + + constexpr auto l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF = 0x0; + l_scom_buffer.insert<48, 1, 63, uint64_t> + (l_MCP_OMI0_IOO_CPLT_RX0_RXCTL_CTL_REGS_RX_CTL_REGS_RX_DC_ENABLE_CM_COARSE_CAL_OFF ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800978000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800988000701103full, l_scom_buffer )); + + l_scom_buffer.insert<48, 3, 61, uint64_t>(literal_0b110 ); + l_scom_buffer.insert<51, 2, 62, uint64_t>(literal_0b00 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800988000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800c0c000701103full, l_scom_buffer )); + + l_scom_buffer.insert<48, 6, 58, uint64_t>(literal_0b000000 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800c0c000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800f1c000701103full, l_scom_buffer )); + + l_scom_buffer.insert<48, 5, 59, uint64_t>(literal_0b01110 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800f1c000701103full, l_scom_buffer)); + } + { + FAPI_TRY(fapi2::getScom( TGT0, 0x800f2c000701103full, l_scom_buffer )); + + if (l_def_IS_HW) + { + l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b0010101 ); + } + else if (l_def_IS_SIM) + { + l_scom_buffer.insert<48, 7, 57, uint64_t>(literal_0b0010110 ); + } + + l_scom_buffer.insert<55, 7, 57, uint64_t>(literal_0b1000110 ); + FAPI_TRY(fapi2::putScom(TGT0, 0x800f2c000701103full, l_scom_buffer)); + } + + }; +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.H b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.H new file mode 100644 index 000000000..a4d94c54e --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.H @@ -0,0 +1,45 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/initfiles/p9a_omic_io_scom.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +#ifndef _INIT_P9A_OMIC_IO_SCOM_PROCEDURE_H_ +#define _INIT_P9A_OMIC_IO_SCOM_PROCEDURE_H_ + + +#include <stddef.h> +#include <stdint.h> +#include <fapi2.H> + + +typedef fapi2::ReturnCode (*p9a_omic_io_scom_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>&, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>&, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +extern "C" +{ + + fapi2::ReturnCode p9a_omic_io_scom(const fapi2::Target<fapi2::TARGET_TYPE_OMIC>& TGT0, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& TGT1, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& TGT2); + +} + +#endif diff --git a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C index ce08da173..d770b6998 100644 --- a/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C +++ b/src/import/chips/p9/procedures/hwp/initfiles/p9n_mca_scom.C @@ -59,8 +59,8 @@ constexpr uint64_t literal_17 = 17; constexpr uint64_t literal_1867 = 1867; constexpr uint64_t literal_2134 = 2134; constexpr uint64_t literal_2401 = 2401; -constexpr uint64_t literal_2666 = 2666; constexpr uint64_t literal_9 = 9; +constexpr uint64_t literal_2666 = 2666; constexpr uint64_t literal_10 = 10; constexpr uint64_t literal_11 = 11; constexpr uint64_t literal_24 = 24; @@ -144,7 +144,15 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0 fapi2::ATTR_EFF_DRAM_CL_Type l_TGT2_ATTR_EFF_DRAM_CL; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_CL, TGT2, l_TGT2_ATTR_EFF_DRAM_CL)); uint64_t l_def_MSS_FREQ_EQ_2133 = ((l_TGT1_ATTR_MSS_FREQ >= literal_1867) && (l_TGT1_ATTR_MSS_FREQ < literal_2134)); + fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE_Type l_TGT2_ATTR_EFF_HYBRID_MEMORY_TYPE; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, TGT2, l_TGT2_ATTR_EFF_HYBRID_MEMORY_TYPE)); + fapi2::ATTR_EFF_HYBRID_Type l_TGT2_ATTR_EFF_HYBRID; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EFF_HYBRID, TGT2, l_TGT2_ATTR_EFF_HYBRID)); + uint64_t l_def_NOT_NVDIMM = ((l_TGT2_ATTR_EFF_HYBRID[l_def_PORT_INDEX][literal_0] == literal_0) + || (l_TGT2_ATTR_EFF_HYBRID_MEMORY_TYPE[l_def_PORT_INDEX][literal_0] == literal_0)); uint64_t l_def_MSS_FREQ_EQ_2400 = ((l_TGT1_ATTR_MSS_FREQ >= literal_2134) && (l_TGT1_ATTR_MSS_FREQ < literal_2401)); + uint64_t l_def_IS_NVDIMM = ((l_TGT2_ATTR_EFF_HYBRID[l_def_PORT_INDEX][literal_0] == literal_1) + && (l_TGT2_ATTR_EFF_HYBRID_MEMORY_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)); uint64_t l_def_MSS_FREQ_EQ_2666 = (l_TGT1_ATTR_MSS_FREQ >= literal_2666); fapi2::ATTR_MSS_EFF_DPHY_WLO_Type l_TGT2_ATTR_MSS_EFF_DPHY_WLO; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_EFF_DPHY_WLO, TGT2, l_TGT2_ATTR_MSS_EFF_DPHY_WLO)); @@ -447,11 +455,16 @@ fapi2::ReturnCode p9n_mca_scom(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& TGT0 { l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_7 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } - else if ((((l_def_MSS_FREQ_EQ_2400 == literal_1) - && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) + else if (((((l_def_MSS_FREQ_EQ_2400 == literal_1) + && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW) && l_def_NOT_NVDIMM)) { l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_8 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); } + else if (((((l_def_MSS_FREQ_EQ_2400 == literal_1) + && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW) && l_def_IS_NVDIMM)) + { + l_scom_buffer.insert<36, 6, 58, uint64_t>((literal_9 + l_TGT2_ATTR_EFF_DRAM_CL[l_def_PORT_INDEX]) ); + } else if ((((l_def_MSS_FREQ_EQ_2666 == literal_1) && (l_TGT2_ATTR_EFF_DIMM_TYPE[l_def_PORT_INDEX][literal_0] == literal_1)) && l_def_IS_HW)) { diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H b/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H index f98504953..5b5cdac9f 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_regs.H @@ -193,6 +193,14 @@ #define EDIP_RX_BER_TIMEOUT 0x800888000000003f, 56, 4 // rx_ber_timeout, used for when making bit error measurements with a servo op (see workbook table 4.10 for timer settings) #define EDIP_RX_CTL_MODE16_EO_PG 0x800888000000003f, 48, 16 // register -- description #define EDIP_CHAN_FAIL_MASK 0x0000000000000020, 15, 8 // scom mode reg spares. +#define EDIP_RX_PG_SPARE_MODE_0 0x800800000000003f, 48, 1 // per-group spare mode latch. +#define EDIP_RX_PG_SPARE_MODE_1 0x800800000000003f, 49, 1 // per-group spare mode latch. +#define EDIP_RX_PG_SPARE_MODE_2 0x800800000000003f, 50, 1 // per-group spare mode latch. +#define EDIP_RX_RC_ENABLE_CM_FINE_CAL 0x8008b8000000003f, 56, 1 // rx recalibration common mode fine calibration enable +#define EDIP_RX_EO_ENABLE_DAC_H1_CAL 0x8008b0000000003f, 50, 1 // rx eye optimization h! dac calibration to reference +#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL 0x8008b0000000003f, 61, 1 // rx eye optimization h! dac to amplitude dac cross-calibration +#define EDIP_RX_A_INTEG_COARSE_GAIN 0x800028000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments. + #define EDI_RX_WTM_STATE 0x800950000000003f, 48, 5 // main wiretest state machine current state (rjr)): \r\n\tx00: idle \r\n\tx01: drv data wt \r\n\tx02: drv clock wt \r\n\tx03: drv data 0 \r\n\tx04: drv clock 0 \r\n\tx05: rx wt \r\n\tx06: wait all ones \r\n\tx07: reset pll \r\n\tx08: wait pll \r\n\tx09: drive clock \r\n\tx0a: drive data 1 \r\n\tx0b: wait all zeroes \r\n\tx0c: drive data 0 \r\n\tx0d: done \r\n\tx0e: unused \r\n\tx0f: unused \r\n\tx10: wait prev done \r\n\tx11: drv prev done \r\n\tx12: drv all done \r\n\tx13: wait all done \r\n\tx14: init tx fifo \r\n\tx15: unused \r\n\tx16: unused \r\n\tx17: unused \r\n\tx18: set c & d dr strength \r\n\tx19: set data only dr strength \r\n\tx1a: clock fail \r\n\tx1b: all bad lanes \r\n\tx1c: wt timeout fail \r\n\tx1d: pll/dll fail \r\n\tx1e: all ones fail \r\n\tx1f: all zeroes fail \r\n\trjr @@ -2496,7 +2504,6 @@ #define EDIP_RX_A_OFFSET_O0 0x800020000000003f, 48, 7 // this is the vertical offset of the odd low threshold sampling latch. #define EDIP_RX_A_OFFSET_O1 0x800020000000003f, 56, 7 // this is the vertical offset of the odd high threshold sampling latch. #define EDIP_RX_DAC_CNTL4_EO_PL 0x800020000000003f, 48, 16 // register -- description -#define EDIP_RX_A_INTEG_COARSE_GAIN 0x800028000000003f, 48, 4 // this is integrator coarse gain control used in making common mode adjustments. #define EDIP_RX_A_EVEN_INTEG_FINE_GAIN 0x800028000000003f, 52, 5 // this is integrator gain control used in making common mode adjustments. #define EDIP_RX_A_ODD_INTEG_FINE_GAIN 0x800028000000003f, 57, 5 // this is integrator gain control used in making common mode adjustments. #define EDIP_RX_DAC_CNTL5_EO_PL 0x800028000000003f, 48, 16 // register -- description @@ -2703,9 +2710,6 @@ #define EDIP_RX_A_PATH_OFF_EVEN 0x800398000000003f, 48, 6 // eye opt a bank even path offset #define EDIP_RX_A_PATH_OFF_ODD 0x800398000000003f, 54, 6 // eye opt a bank odd path offset #define EDIP_RX_WORK_STAT3_EO_PL 0x800398000000003f, 48, 16 // register -- description -#define EDIP_RX_PG_SPARE_MODE_0 0x800800000000003f, 48, 1 // per-group spare mode latch. -#define EDIP_RX_PG_SPARE_MODE_1 0x800800000000003f, 49, 1 // per-group spare mode latch. -#define EDIP_RX_PG_SPARE_MODE_2 0x800800000000003f, 50, 1 // per-group spare mode latch. #define EDIP_RX_PG_SPARE_MODE_3 0x800800000000003f, 51, 1 // per-group spare mode latch. #define EDIP_RX_PG_SPARE_MODE_4 0x800800000000003f, 52, 1 // chicken switch for hw219893. fix is to prevent the rx_sls_hndshk_state sm and the rx_dyn_recal_hndshk_state sm from ever being allowed to run at the same time. setting the cs turns this feature off. #define EDIP_RX_SPARE_MODE_PG 0x800800000000003f, 48, 16 // register -- description @@ -2803,7 +2807,6 @@ #define EDIP_RX_EO_STEP_CNTL_EDI_ALIAS 0x8008b0000000003f, 48, 16 // rx eye optimization step control edi alias #define EDIP_RX_EO_ENABLE_INTEG_LATCH_OFFSET_CAL 0x8008b0000000003f, 48, 1 // rx eye optimization latch offset adjustment enable with integrator-based disable #define EDIP_RX_EO_ENABLE_CTLE_COARSE_CAL 0x8008b0000000003f, 49, 1 // rx eye optimization coarse ctle/peakin enable -#define EDIP_RX_EO_ENABLE_DAC_H1_CAL 0x8008b0000000003f, 50, 1 // rx eye optimization h! dac calibration to reference #define EDIP_RX_EO_ENABLE_VGA_CAL 0x8008b0000000003f, 51, 1 // rx eye optimization vga gainand offset adjust enable #define EDIP_RX_EO_ENABLE_DFE_H1_CAL 0x8008b0000000003f, 52, 1 // rx eye optimization dfe h1 adjust enable #define EDIP_RX_EO_ENABLE_H1AP_TWEAK 0x8008b0000000003f, 53, 1 // rx eye optimization h1/an pr adjust enable @@ -2814,7 +2817,6 @@ #define EDIP_RX_EO_ENABLE_RESULT_CHECK 0x8008b0000000003f, 58, 1 // rx eye optimization final results check enable #define EDIP_RX_EO_ENABLE_CTLE_EDGE_TRACK_ONLY 0x8008b0000000003f, 59, 1 // rx eye optimization ctle/peakin enable with edge tracking only #define EDIP_RX_EO_ENABLE_DFE_H2_H12_CAL 0x8008b0000000003f, 60, 1 // rx eye optimization dfe h2 to h12 calibration enable -#define EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL 0x8008b0000000003f, 61, 1 // rx eye optimization h! dac to amplitude dac cross-calibration #define EDIP_RX_EO_ENABLE_FINAL_L2U_ADJ 0x8008b0000000003f, 62, 1 // rx eye optimization final rx fifo load-to-unload delay adjustment enable #define EDIP_RX_EO_ENABLE_DONE_SIGNALING 0x8008b0000000003f, 63, 1 // rx eye optimization eye opt done signaling enable #define EDIP_RX_CTL_MODE21_EO_PG 0x8008b0000000003f, 48, 16 // register -- description @@ -2827,7 +2829,6 @@ #define EDIP_RX_RC_ENABLE_H1AP_TWEAK 0x8008b8000000003f, 53, 1 // rx recalibration h1/an pr adjust enable #define EDIP_RX_RC_ENABLE_DDC 0x8008b8000000003f, 54, 1 // rx recalibration dynamic data centering enable #define EDIP_RX_RC_ENABLE_CM_COARSE_CAL 0x8008b8000000003f, 55, 1 // rx recalibration common mode coarse calibration enable -#define EDIP_RX_RC_ENABLE_CM_FINE_CAL 0x8008b8000000003f, 56, 1 // rx recalibration common mode fine calibration enable #define EDIP_RX_RC_ENABLE_BER_TEST 0x8008b8000000003f, 57, 1 // rx recalibration unsupported, leave at 0. bit error rate test enable #define EDIP_RX_RC_ENABLE_RESULT_CHECK 0x8008b8000000003f, 58, 1 // rx recalibration unsupported, leave at 0. final results check enable #define EDIP_RX_RC_ENABLE_CTLE_EDGE_TRACK_ONLY 0x8008b8000000003f, 59, 1 // rx recalibration ctle/peaking enable with edge tracking only diff --git a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C index 8e421dab6..5d2fab537 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C +++ b/src/import/chips/p9/procedures/hwp/io/p9_io_xbus_dccal.C @@ -730,6 +730,58 @@ fapi_try_exit: return fapi2::current_err; } + +/** + * @brief Xbus Common Mode Workaround + * @param[in] i_tgt FAPI2 Target + * @param[in] i_grp Clock Group + * @retval ReturnCode + */ +fapi2::ReturnCode p9x_cm_workaround( const XBUS_TGT i_tgt, const uint8_t i_grp ) +{ + FAPI_IMP( "p9x_cm_workaround: I/O EDI+ Xbus Entering" ); + const uint8_t CMDAC = 5; // Initialize with a CMDAC = 2 + const uint8_t XBUS_LANES = 17; + const uint8_t LN0 = 0; + uint32_t l_cm_crs = 0; + uint64_t l_data = 0; + uint8_t l_workaround_en = 0; + + fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc = + i_tgt.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + + FAPI_TRY( FAPI_ATTR_GET( fapi2::ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND, l_proc, l_workaround_en ) ); + + if( l_workaround_en ) + { + FAPI_DBG( "p9x_cm_workaround: I/O EDI+ Xbus Executing" ); + FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_0, i_tgt, i_grp, LN0, ((CMDAC >> 2) & 0x1))); + FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_1, i_tgt, i_grp, LN0, ((CMDAC >> 1) & 0x1))); + FAPI_TRY( io::rmw( EDIP_RX_PG_SPARE_MODE_2, i_tgt, i_grp, LN0, ((CMDAC >> 0) & 0x1))); + FAPI_TRY( io::rmw( EDIP_RX_RC_ENABLE_CM_FINE_CAL, i_tgt, i_grp, LN0, 0)); + FAPI_TRY( io::rmw( EDIP_RX_EO_ENABLE_DAC_H1_TO_A_CAL, i_tgt, i_grp, LN0, 1)); + FAPI_TRY( io::rmw( EDIP_RX_EO_ENABLE_DAC_H1_CAL, i_tgt, i_grp, LN0, 1)); + + for( uint8_t l_lane = 0; l_lane < XBUS_LANES; ++l_lane ) + { + FAPI_TRY( io::read( EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, i_grp, l_lane, l_data )); + l_cm_crs = io::get( EDIP_RX_A_INTEG_COARSE_GAIN, l_data ); + l_cm_crs = ( l_cm_crs * 5 ) / 10; + FAPI_TRY( io::rmw( EDIP_RX_A_INTEG_COARSE_GAIN, i_tgt, i_grp, l_lane, l_cm_crs)); + } + } + else + { + FAPI_DBG( "p9x_cm_workaround: I/O EDI+ Xbus Skipping" ); + } + +fapi_try_exit: + FAPI_IMP( "p9x_cm_workaround: I/O EDI+ Xbus Exiting" ); + return fapi2::current_err; +} + + + /** * @brief Rx Dc Calibration * @param[in] i_tgt FAPI2 Target @@ -842,6 +894,9 @@ fapi2::ReturnCode rx_dccal_poll_grp( const XBUS_TGT i_tgt, const uint8_t i_grp // Restore the invalid bits, Wiretest will modify these as training is run. FAPI_TRY( set_lanes_invalid( i_tgt, i_grp, 1 ), "Error Setting Lane Invalid to 1" ); + // Data Compression Workaround + FAPI_TRY( p9x_cm_workaround( i_tgt, i_grp ), "p9x_cm_workaround call failed" ); + FAPI_DBG( "I/O EDI+ Xbus Rx Dccal Complete on Group(%d)", i_grp ); diff --git a/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_dccal.C b/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_dccal.C index 10748a148..dff06ace3 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_dccal.C +++ b/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_dccal.C @@ -722,6 +722,46 @@ fapi_try_exit: return fapi2::current_err; } +/** + * @brief Init PHY Tx FIFO Logic + * @param[in] i_tgt FAPI2 Target + * @param[in] i_lave_vector Lanve Vector + * @retval ReturnCode + */ +fapi2::ReturnCode p9_omi_tx_fifo_init(const OMIC_TGT i_tgt, const uint32_t i_lane_vector) +{ + FAPI_IMP("p9_omi_tx_fifo_init: I/O OMI Entering"); + const uint8_t GRP0 = 0; + const uint8_t LANES = 24; + fapi2::buffer<uint64_t> l_data = 0; + + // Power up Per-Lane Registers + for(uint8_t l_lane = 0; l_lane < LANES; ++l_lane) + { + if(((0x1 << l_lane) & i_lane_vector) != 0) + { + // - Clear TX_UNLOAD_CLK_DISABLE + FAPI_TRY(io::read(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data)); + io::set(OPT_TX_UNLOAD_CLK_DISABLE, 0, l_data); + FAPI_TRY(io::write(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data)); + + // - Set TX_FIFO_INIT + l_data.flush<0>(); + io::set(OPT_TX_FIFO_INIT, 1, l_data); + FAPI_TRY(io::write(OPT_TX_CNTL1G_PL, i_tgt, GRP0, l_lane, l_data)); + + // - Set TX_UNLOAD_CLK_DISABLE + FAPI_TRY(io::read(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data)); + io::set(OPT_TX_UNLOAD_CLK_DISABLE, 1, l_data ); + FAPI_TRY(io::write(OPT_TX_MODE2_PL, i_tgt, GRP0, l_lane, l_data)); + } + } + +fapi_try_exit: + FAPI_IMP("p9_omi_tx_fifo_init: I/O OMI Exiting"); + return fapi2::current_err; +} + } // end namespace P9A_IO_OMI_DCCAL using namespace P9A_IO_OMI_DCCAL; @@ -784,6 +824,9 @@ fapi2::ReturnCode p9a_io_omi_dccal(const OMIC_TGT i_tgt, const uint32_t i_lane_v FAPI_TRY(set_omi_flywheel_off(i_tgt, i_lane_vector, 0)); FAPI_TRY(set_omi_pr_edge_track_cntl(i_tgt, i_lane_vector, 0)); + // Run Tx FIFO Init + FAPI_TRY(p9_omi_tx_fifo_init(i_tgt, i_lane_vector)); + fapi_try_exit: FAPI_IMP("p9_io_omi_dccal: I/O OMI Exiting"); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_scominit.C b/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_scominit.C index b73642b5f..06ce72238 100644 --- a/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_scominit.C +++ b/src/import/chips/p9/procedures/hwp/io/p9a_io_omi_scominit.C @@ -52,6 +52,7 @@ #include <p9_io_scom.H> #include <p9_io_regs.H> #include <p9a_omi_io_scom.H> +#include <p9a_omic_io_scom.H> #include <p9a_io_omi_scominit.H> #include <p9_obus_scom_addresses.H> #include <p9a_mc_scom_addresses.H> @@ -78,6 +79,8 @@ fapi2::ReturnCode p9a_io_omi_scominit(const fapi2::Target<fapi2::TARGET_TYPE_OMI // get a proc target fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_proc_target = i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + auto l_omi_lst = i_target.getChildren<fapi2::TARGET_TYPE_OMI>(); + // assert IO reset to power-up bus endpoint logic FAPI_TRY(io::rmw(OPT_IORESET_HARD_BUS0, i_target, GROUP_00, LANE_00, SET_RESET)); @@ -87,9 +90,15 @@ fapi2::ReturnCode p9a_io_omi_scominit(const fapi2::Target<fapi2::TARGET_TYPE_OMI FAPI_TRY(io::rmw(OPT_IORESET_HARD_BUS0, i_target, GROUP_00, LANE_00, CLEAR_RESET)); FAPI_INF("Invoke FAPI procedure core: input_target"); - FAPI_EXEC_HWP(rc, p9a_omi_io_scom, i_target, l_system_target, l_proc_target); + FAPI_EXEC_HWP(rc, p9a_omic_io_scom, i_target, l_system_target, l_proc_target); + + for (auto l_omi_target : l_omi_lst) + { + FAPI_EXEC_HWP(rc, p9a_omi_io_scom, l_omi_target, l_system_target, l_proc_target); + } - // configure FIR + // configure FIR if p9a_omi_io_scom passed + if ( fapi2::current_err == fapi2::FAPI2_RC_SUCCESS ) { FAPI_TRY(fapi2::putScom(i_target, P9A_OMIC_FIR_ACTION0_REG, @@ -106,7 +115,8 @@ fapi2::ReturnCode p9a_io_omi_scominit(const fapi2::Target<fapi2::TARGET_TYPE_OMI } // mark HWP exit - FAPI_INF("p9a_io_omi_scominit: ...Exiting"); + FAPI_INF("p9a_io_omi_scominit: ...Exiting, rc = 0x%X", + (uint32_t)fapi2::current_err); fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H index 67a3240e3..bb3f737d2 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_base.H @@ -46,7 +46,7 @@ /// Image Magic Numbers -HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f312e30)) // CPMR_1.0 +HCD_CONST64(CPMR_MAGIC_NUMBER, ULL(0x43504d525f322e30)) // CPMR_2.0 HCD_CONST64(CME_MAGIC_NUMBER , ULL(0x434d455f5f312e30)) // CME__1.0 HCD_CONST64(QPMR_MAGIC_NUMBER, ULL(0x51504d525f312e30)) // QPMR_1.0 @@ -434,6 +434,7 @@ HCD_CONST(CME_QM_FLAG_SYS_WOF_ENABLE, 0x1000) HCD_CONST(CME_QM_FLAG_SYS_DYN_FMIN_ENABLE, 0x0800) HCD_CONST(CME_QM_FLAG_SYS_DYN_FMAX_ENABLE, 0x0400) HCD_CONST(CME_QM_FLAG_SYS_JUMP_PROTECT, 0x0200) +HCD_CONST(CME_QM_FLAG_PER_QUAD_VDM_ENABLE, 0x0100) HCD_CONST(CME_QM_FLAG_PSTATE_PHANTOM_HALT_EN, 0x0001) /// CME Hcode @@ -460,6 +461,13 @@ HCD_CONST(CME_QUAD_PSTATE_SIZE, HALF_KB) HCD_CONST(CME_REGION_SIZE, (64 * ONE_KB)) + +// HOMER compatibility + +HCD_CONST(STOP_API_CPU_SAVE_VER, 0x02) +HCD_CONST(SELF_SAVE_RESTORE_VER, 0x02) +HCD_CONST(SMF_SUPPORT_SIGNATURE_OFFSET, 0x1300) +HCD_CONST(SMF_SELF_SIGNATURE, (0x5f534d46)) // Debug HCD_CONST(CPMR_TRACE_REGION_OFFSET, (512 * ONE_KB)) diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H index 57323d935..86bd06003 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcd_memmap_occ_sram.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -76,6 +76,7 @@ HCD_CONST(OCC_SRAM_OCC_REGION_SIZE, (512 * ONE_KB)) HCD_CONST(OCC_SRAM_BEFORE_PGPE_REGION_SIZE_TOTAL, (OCC_SRAM_IPC_REGION_SIZE + OCC_SRAM_GPE0_REGION_SIZE + OCC_SRAM_GPE1_REGION_SIZE)) + //-------------------------------------------------------------------------------------- /// PGPE Base @@ -192,5 +193,7 @@ HCD_CONST( OCC_SRAM_PGPE_TRACE_START, (OCC_SRAM_PGPE_HEADER_ADDR + PGPE_HEADER_SIZE)); +HCD_CONST(OCC_SRAM_SHARED_DATA_BASE_ADDR, + (OCC_SRAM_PGPE_BASE_ADDR + OCC_SRAM_PGPE_REGION_SIZE - PGPE_OCC_SHARED_SRAM_SIZE)) #endif /* __P9_HCD_MEMMAP_OCC_SRAM_H__ */ diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H index 64d81508c..618108f22 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H +++ b/src/import/chips/p9/procedures/hwp/lib/p9_hcode_image_defines.H @@ -374,8 +374,10 @@ HCD_HDR_UINT32(g_wof_table_length, 0 ); // WOF Table length HCD_HDR_UINT32(g_pgpe_core_throttle_assert_cnt, 0 ); // Core throttle assert count HCD_HDR_UINT32(g_pgpe_core_throttle_deassert_cnt, 0 ); // Core throttle de-aasert count HCD_HDR_UINT32(g_pgpe_aux_controls, 0 ); // Auxiliary Controls +HCD_HDR_UINT32(g_pgpe_optrace_pointer, 0 ); // Operational Trace OCC SRAM Pointer HCD_HDR_UINT32(g_pgpe_doptrace_offset, 0 ); // Deep Operational Trace Main Memory Buffer Offset HCD_HDR_UINT32(g_pgpe_doptrace_length, 0 ); // Deep Opeartional Trace Main Memory Buffer Length +HCD_HDR_UINT32(g_pgpe_wof_values_address, 0 ); // SRAM address where PGPE Produced WOF values are located #ifdef __ASSEMBLER__ .endm #else diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h index 5f3ebba57..dec2af939 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pm_hcd_flags.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -65,6 +65,7 @@ enum PM_GPE_OCCFLG_DEFS PIB_I2C_MASTER_ENGINE_2_LOCK_BIT1 = 19, //BIT0 ored BIT1 gives the field PIB_I2C_MASTER_ENGINE_3_LOCK_BIT0 = 20, //BIT0 ored BIT1 gives the field PIB_I2C_MASTER_ENGINE_3_LOCK_BIT1 = 21, //BIT0 ored BIT1 gives the field + PGPE_OCS_DIRTY = 26, PGPE_PM_RESET_SUPPRESS = 27, WOF_HCODE_MODE_BIT0 = 28, WOF_HCODE_MODE_BIT1 = 29, @@ -77,6 +78,7 @@ enum PM_GPE_OCCFLG2_DEFS { OCCFLG2_DEAD_CORES_START = 0, OCCFLG2_DEAD_CORES_LENGTH = 24, + OCCFLG2_ENABLE_PRODUCE_WOF_VALUES = 24, OCCFLG2_PGPE_HCODE_FIT_ERR_INJ = 27, PM_CALLOUT_ACTIVE = 28, STOP_RECOVERY_TRIGGER_ENABLE = 29, @@ -127,6 +129,7 @@ enum PM_CME_FLAGS_DEFS CME_FLAGS_DROOP_SUSPEND_ENTRY = 14, CME_FLAGS_SAFE_MODE = 16, CME_FLAGS_PSTATES_SUSPENDED = 17, + CME_FLAGS_DB0_COMM_RECV_STARVATION_CNT_ENABLED = 18, CME_FLAGS_SPWU_CHECK_ENABLE = 22, CME_FLAGS_BLOCK_ENTRY_STOP11 = 23, CME_FLAGS_PSTATES_ENABLED = 24, diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h index d7739af81..373bd8d8d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_cmeqm.h @@ -35,6 +35,7 @@ #define __P9_PSTATES_CME_H__ #include <p9_pstates_common.h> +#include <p9_hcd_memmap_base.H> /// @} @@ -161,6 +162,23 @@ typedef struct uint16_t r_core_header; } resistance_entry_t; +typedef struct __attribute__((packed)) +{ + uint16_t r_package_common; + uint16_t r_quad; + uint16_t r_core; + uint16_t r_quad_header; + uint16_t r_core_header; + uint8_t r_vdm_cal_version; + uint8_t r_avg_min_scale_fact; + uint16_t r_undervolt_vmin_floor_limit; + uint8_t r_min_bin_protect_pc_adder; + uint8_t r_min_bin_protect_bin_adder; + uint8_t r_undervolt_allowed; + uint8_t reserve[10]; +} +resistance_entry_per_quad_t; + typedef struct { poundw_entry_t poundw[NUM_OP_POINTS]; @@ -178,6 +196,35 @@ typedef struct PoundW_data vpd_w_data; } LP_VDMParmBlock; +typedef struct __attribute__((packed)) +{ + uint16_t ivdd_tdp_ac_current_10ma; + uint16_t ivdd_tdp_dc_current_10ma; + uint8_t vdm_overvolt_small_thresholds; + uint8_t vdm_large_extreme_thresholds; + uint8_t vdm_normal_freq_drop; // N_S and N_L Drop + uint8_t vdm_normal_freq_return; // L_S and S_N Return + uint8_t vdm_vid_compare_per_quad[MAX_QUADS_PER_CHIP]; + uint8_t vdm_cal_state_avg_min_per_quad[MAX_QUADS_PER_CHIP]; + uint16_t vdm_cal_state_vmin; + uint8_t vdm_cal_state_avg_core_dts; + uint16_t vdm_cal_state_avg_core_current; + uint16_t vdm_spare; +} +poundw_entry_per_quad_t; + +typedef struct __attribute__((packed)) +{ + poundw_entry_per_quad_t poundw[NUM_OP_POINTS]; + resistance_entry_per_quad_t resistance_data; +} +PoundW_data_per_quad; + + +typedef struct +{ + PoundW_data_per_quad vpd_w_data; +} LP_VDMParmBlock_PerQuad; /// The layout of the data created by the Pstate table creation firmware for /// comsumption by the Pstate GPE. This data will reside in the Quad diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h index b35d2c0ab..92631a91f 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_common.h @@ -240,6 +240,21 @@ typedef struct } SysPowerDistParms; +/// AVSBUS Topology +/// +/// AVS Bus and Rail numbers for VDD, VDN, VCS, and VIO +/// +typedef struct +{ + uint8_t vdd_avsbus_num; + uint8_t vdd_avsbus_rail; + uint8_t vdn_avsbus_num; + uint8_t vdn_avsbus_rail; + uint8_t vcs_avsbus_num; + uint8_t vcs_avsbus_rail; + uint8_t vio_avsbus_num; + uint8_t vio_avsbus_rail; +} AvsBusTopology_t; // // WOF Voltage, Frequency Ratio Tables diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h index 6ef85286e..2fd82683d 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_occ.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -205,6 +205,8 @@ typedef struct // AC tdp vdd nominal uint16_t lac_tdp_vdd_nominal_10ma; + AvsBusTopology_t avs_bus_topology; + } __attribute__((aligned(128))) OCCPstateParmBlock; #ifdef __cplusplus diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h index a1b10e4cc..be48537d3 100644 --- a/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h +++ b/src/import/chips/p9/procedures/hwp/lib/p9_pstates_pgpe.h @@ -350,6 +350,10 @@ typedef struct //Jump-value slopes int16_t PsVDMJumpSlopes[VPD_NUM_SLOPES_REGION][NUM_JUMP_VALUES]; + uint8_t pad2[2]; + + //AvsBusTopology + AvsBusTopology_t avs_bus_topology; // @todo DPLL Droop Settings. These need communication to SGPE for STOP diff --git a/src/import/chips/p9/procedures/hwp/memory/lab/sdk/example/C/mss_lab_sfwrite.C b/src/import/chips/p9/procedures/hwp/memory/lab/sdk/example/C/mss_lab_sfwrite.C index 58b382a97..8fd2fb737 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lab/sdk/example/C/mss_lab_sfwrite.C +++ b/src/import/chips/p9/procedures/hwp/memory/lab/sdk/example/C/mss_lab_sfwrite.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,8 +33,10 @@ // *HWP Level: 3 // *HWP Consumed by: Memory -#include <mss_lab_tools.H> +#include <generic/memory/lab/mss_lab_tools.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/shared/nimbus_defaults.H> #include <generic/memory/lib/utils/poll.H> #include <lib/mcbist/address.H> #include <lib/mcbist/memdiags.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C deleted file mode 100644 index 60dc06bcc..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C +++ /dev/null @@ -1,376 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file ccs.C -/// @brief Run and manage the CCS engine -/// -// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#include <fapi2.H> - -#include <mss.H> -#include <lib/ccs/ccs.H> -#include <lib/fir/check.H> -#include <lib/phy/mss_lrdimm_training.H> - -#ifdef LRDIMM_CAPABLE - #include <lib/workarounds/quad_encode_workarounds.H> -#endif - -using fapi2::TARGET_TYPE_MCBIST; -using fapi2::TARGET_TYPE_MCA; - -using fapi2::FAPI2_RC_SUCCESS; - -namespace mss -{ -namespace ccs -{ - -/// -/// @brief Determines our rank configuration type across all ports -/// @param[in] i_target the MCBIST target on which to operate -/// @param[out] o_rank_config the rank configuration -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode get_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - std::vector<rank_configuration>& o_rank_config) -{ - o_rank_config.clear(); - // Create one per port, we then use relative indexing to get us the number we need - o_rank_config = std::vector<rank_configuration>(PORTS_PER_MCBIST); - - for(const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target)) - { - rank_configuration l_config; - FAPI_TRY(get_rank_config(l_mca, l_config)); - o_rank_config[mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(l_mca)] = l_config; - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Determines our rank configuration type -/// @param[in] i_target the MCA target on which to operate -/// @param[out] o_rank_config the rank configuration -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode get_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - rank_configuration& o_rank_config) -{ - constexpr uint8_t QUAD_RANK_ENABLE = 4; - o_rank_config = rank_configuration::DUAL_DIRECT; - - uint8_t l_num_master_ranks[MAX_DIMM_PER_PORT] = {}; - FAPI_TRY(mss::eff_num_master_ranks_per_dimm(i_target, l_num_master_ranks)); - - // We only need to check DIMM0 - // Our number of ranks should be the same between DIMM's 0/1 - // Check if we have the right number for encoded mode - o_rank_config = l_num_master_ranks[0] == QUAD_RANK_ENABLE ? - rank_configuration::QUAD_ENCODED : - rank_configuration::DUAL_DIRECT; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Start or stop the CCS engine -/// @param[in] i_target The MCBIST containing the CCS engine -/// @param[in] i_start_stop bool MSS_CCS_START for starting, MSS_CCS_STOP otherwise -/// @return FAPI2_RC_SUCCESS iff success -/// -template<> -fapi2::ReturnCode start_stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, const bool i_start_stop ) -{ - typedef ccsTraits<TARGET_TYPE_MCBIST> TT; - - fapi2::buffer<uint64_t> l_buf; - - // Do we need to read this? We are setting the only bit defined in the scomdef? BRS - FAPI_TRY(mss::getScom(i_target, TT::CNTLQ_REG, l_buf)); - - FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, - i_start_stop ? l_buf.setBit<TT::CCS_START>() : l_buf.setBit<TT::CCS_STOP>()) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Determine the CCS failure type -/// @param[in] i_target MCBIST target -/// @param[in] i_type the failure type -/// @param[in] i_mca The port the CCS instruction is training -/// @return ReturnCode associated with the fail. -/// @note FFDC is handled here, caller doesn't need to do it -/// -fapi2::ReturnCode fail_type( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const uint64_t& i_type, - const fapi2::Target<TARGET_TYPE_MCA>& i_mca ) -{ - fapi2::ReturnCode l_failing_rc(fapi2::FAPI2_RC_SUCCESS); - // Including the MCA_TARGET here and below at CAL_TIMEOUT since these problems likely lie at the MCA level - // So we disable the PORT and hopefully that's it - // If the problem lies with the MCBIST, it'll just have to loop - FAPI_ASSERT(STAT_READ_MISCOMPARE != i_type, - fapi2::MSS_CCS_READ_MISCOMPARE() - .set_MCBIST_TARGET(i_target) - .set_FAIL_TYPE(i_type) - .set_MCA_TARGET(i_mca), - "%s CCS FAIL Read Miscompare", mss::c_str(i_mca)); - - // This error is likely due to a bad CCS engine/ MCBIST - FAPI_ASSERT(STAT_UE_SUE != i_type, - fapi2::MSS_CCS_UE_SUE() - .set_FAIL_TYPE(i_type) - .set_MCBIST_TARGET(i_target), - "%s CCS FAIL UE or SUE Error", mss::c_str(i_target)); - - FAPI_ASSERT(STAT_CAL_TIMEOUT != i_type, - fapi2::MSS_CCS_CAL_TIMEOUT() - .set_FAIL_TYPE(i_type) - .set_MCBIST_TARGET(i_target) - .set_MCA_TARGET(i_mca), - "%s CCS FAIL Calibration Operation Time Out", mss::c_str(i_mca)); - - // Problem with the CCS engine - FAPI_ASSERT(STAT_HUNG != i_type, - fapi2::MSS_CCS_HUNG().set_MCBIST_TARGET(i_target), - "%s CCS appears hung", mss::c_str(i_target)); -fapi_try_exit: - // Due to the PRD update, we need to check for FIR's - // If any FIR's have lit up, this CCS fail could have been caused by the FIR - // So, let PRD retrigger this step to see if we can resolve the issue - return mss::check::fir_or_pll_fail<mss::mc_type::NIMBUS>(i_target, fapi2::current_err); -} - -/// -/// @brief Execute the contents of the CCS array -/// @param[in] i_target The MCBIST containing the array -/// @param[in] i_program the MCBIST ccs program - to get the polling parameters -/// @param[in] i_port The port target that the array is for -/// @return FAPI2_RC_SUCCESS iff success -/// -template<> -fapi2::ReturnCode execute_inst_array(const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - ccs::program<TARGET_TYPE_MCBIST>& i_program, - const fapi2::Target<TARGET_TYPE_MCA>& i_port) -{ - typedef ccsTraits<TARGET_TYPE_MCBIST> TT; - - fapi2::buffer<uint64_t> status; - - FAPI_TRY(start_stop(i_target, mss::START), "%s Error in execute_inst_array", mss::c_str(i_port) ); - - mss::poll(i_target, TT::STATQ_REG, i_program.iv_poll, - [&status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_INF("ccs statq 0x%llx, remaining: %d", stat_reg, poll_remaining); - status = stat_reg; - return status.getBit<TT::CCS_IN_PROGRESS>() != 1; - }, - i_program.iv_probes); - - // Check for done and success. DONE being the only bit set. - if (status == STAT_QUERY_SUCCESS) - { - FAPI_INF("%s CCS Executed Successfully.", mss::c_str(i_port) ); - goto fapi_try_exit; - } - - // So we failed or we're still in progress. Mask off the fail bits - // and run this through the FFDC generator. - // TK: Put the const below into a traits class? -- JLH - FAPI_TRY( fail_type(i_target, status & 0x1C00000000000000, i_port), "Error in execute_inst_array" ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Execute a set of CCS instructions -/// @param[in] i_target the target to effect -/// @param[in] i_program the vector of instructions -/// @param[in] i_ports the vector of ports -/// @return FAPI2_RC_SUCCSS iff ok -/// @note assumes the CCS engine has been configured. -/// -template<> -fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - ccs::program<TARGET_TYPE_MCBIST>& i_program, - const std::vector< fapi2::Target<TARGET_TYPE_MCA> >& i_ports) -{ - typedef ccsTraits<TARGET_TYPE_MCBIST> TT; - - // Subtract one for the idle we insert at the end - constexpr size_t CCS_INSTRUCTION_DEPTH = 32 - 1; - constexpr uint64_t CCS_ARR0_ZERO = MCBIST_CCS_INST_ARR0_00; - constexpr uint64_t CCS_ARR1_ZERO = MCBIST_CCS_INST_ARR1_00; - - ccs::instruction_t<TARGET_TYPE_MCBIST> l_des = ccs::des_command<TARGET_TYPE_MCBIST>(); - - FAPI_INF("loading ccs instructions (%d) for %s", i_program.iv_instructions.size(), mss::c_str(i_target)); - - auto l_inst_iter = i_program.iv_instructions.begin(); - - std::vector<rank_configuration> l_rank_configs; - FAPI_TRY(get_rank_config(i_target, l_rank_configs)); - - // Stop the CCS engine just for giggles - it might be running ... - FAPI_TRY( start_stop(i_target, mss::states::STOP), "Error in ccs::execute" ); - - FAPI_ASSERT( mss::poll(i_target, TT::STATQ_REG, poll_parameters(), - [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_INF("ccs statq (stop) 0x%llx, remaining: %d", stat_reg, poll_remaining); - return stat_reg.getBit<TT::CCS_IN_PROGRESS>() != 1; - }), - fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target) ); - - while (l_inst_iter != i_program.iv_instructions.end()) - { - - // Kick off the CCS engine - per port. No broadcast mode for CCS (per Shelton 9/23/15) - for (const auto& p : i_ports) - { - const auto l_port_index = mss::relative_pos<TARGET_TYPE_MCBIST>(p); - size_t l_inst_count = 0; - - uint64_t l_total_delay = 0; - uint64_t l_delay = 0; - uint64_t l_repeat = 0; - uint8_t l_current_cke = 0; - - // Shove the instructions into the CCS engine, in 32 instruction chunks, and execute them - for (; l_inst_iter != i_program.iv_instructions.end() - && l_inst_count < CCS_INSTRUCTION_DEPTH; ++l_inst_count, ++l_inst_iter) - { - // First, update the current instruction's chip selects for the current port - FAPI_TRY(l_inst_iter->configure_rank(p, l_rank_configs[l_port_index]), "Error in rank config"); - - l_inst_iter->arr0.extractToRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); - - // Make sure this instruction leads to the next. Notice this limits this mechanism to pretty - // simple (straight line) CCS programs. Anything with a loop or such will need another mechanism. - l_inst_iter->arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_GOTO_CMD, - MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN>(l_inst_count + 1); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0), "Error in ccs::execute" ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1), "Error in ccs::execute" ); - - // arr1 contains a specification of the delay and repeat after this instruction, as well - // as a repeat. Total up the delays as we go so we know how long to wait before polling - // the CCS engine for completion - l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(l_delay); - l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, - MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT>(l_repeat); - - l_total_delay += l_delay * (l_repeat + 1); - - FAPI_INF("css inst %d: 0x%016lX 0x%016lX (0x%lx, 0x%lx) delay: 0x%x (0x%x) %s", - l_inst_count, l_inst_iter->arr0, l_inst_iter->arr1, - CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, - l_delay, l_total_delay, mss::c_str(i_target)); - } - - // Check our program for any delays. If there isn't a iv_initial_delay configured, then - // we use the delay we just summed from the instructions. - if (i_program.iv_poll.iv_initial_delay == 0) - { - i_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, l_total_delay); - } - - if (i_program.iv_poll.iv_initial_sim_delay == 0) - { - i_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(l_total_delay); - } - - FAPI_INF("executing ccs instructions (%d:%d, %d) for %s", - i_program.iv_instructions.size(), l_inst_count, i_program.iv_poll.iv_initial_delay, mss::c_str(i_target)); - - // Deselect - l_des.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); - - // Insert a DES as our last instruction. DES is idle state anyway and having this - // here as an instruction forces the CCS engine to wait the delay specified in - // the last instruction in this array (which it otherwise doesn't do.) - l_des.arr1.setBit<MCBIST_CCS_INST_ARR1_00_END>(); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0), "Error in ccs::execute" ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1), "Error in ccs::execute" ); - - FAPI_INF("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s", - l_inst_count, l_des.arr0, l_des.arr1, - CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, mss::c_str(i_target)); - - - FAPI_INF("executing CCS array for port %d (%s)", l_port_index, mss::c_str(p)); - FAPI_TRY( select_ports( i_target, l_port_index), "Error in ccs execute" ); - FAPI_TRY( execute_inst_array(i_target, i_program, p), "Error in ccs execute" ); - } - } - -#if LRDIMM_CAPABLE - - if(mss::workarounds::contains_command_mrs(i_program.iv_instructions)) - { - // Get ranks in pair bombs out if we can't get any ranks in this pair, so we should be safe here - for (const auto& p : i_ports) - { - FAPI_TRY(mss::workarounds::fix_shadow_register_corruption(p)); - } - } - -#endif - -fapi_try_exit: - i_program.iv_instructions.clear(); - return fapi2::current_err; -} - -/// -/// @brief Nimbus specialization for modeq_copy_cke_to_spare_cke -/// @param[in] fapi2::Target<TARGET_TYPE_MCBIST>& the target to effect -/// @param[in,out] the buffer representing the mode register -/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports -/// @note no-op for p9n -/// -template<> -void copy_cke_to_spare_cke<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>&, - fapi2::buffer<uint64_t>&, states ) -{ - return; -} - -} // namespace -} // namespace diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H deleted file mode 100644 index 923b84052..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H +++ /dev/null @@ -1,1343 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file ccs.H -/// @brief Run and manage the CCS engine -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _MSS_CCS_H_ -#define _MSS_CCS_H_ - -#include <fapi2.H> - -#include <p9_mc_scom_addresses.H> -#include <p9_mc_scom_addresses_fld.H> - -#include <generic/memory/lib/utils/poll.H> -#include <generic/memory/lib/utils/buffer_ops.H> -#include <lib/mc/port.H> -#include <lib/shared/mss_const.H> -#include <lib/eff_config/timing.H> - -// I have a dream that the CCS engine code can be shared among controllers. So, I drive the -// engine from a set of traits. This might be folly. Allow me to dream. BRS -/// -/// @class ccsTraits -/// @brief Nimbus CCS Engine traits -/// -template< fapi2::TargetType T > -class ccsTraits; - -template<> -class ccsTraits<fapi2::TARGET_TYPE_MEMBUF_CHIP> -{ - public: -}; - -template<> -class ccsTraits<fapi2::TARGET_TYPE_MCBIST> -{ - public: - static constexpr uint64_t MODEQ_REG = MCBIST_CCS_MODEQ; - static constexpr uint64_t MCB_CNTL_REG = MCBIST_MCB_CNTLQ; - static constexpr uint64_t CNTLQ_REG = MCBIST_CCS_CNTLQ; - static constexpr uint64_t STATQ_REG = MCBIST_CCS_STATQ; - static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MCA; - - enum - { - // Non address values that are needed for helper functions - - // ODT values used for beautification - // Attribute locations - ATTR_ODT_DIMM0_R0 = 0, - ATTR_ODT_DIMM0_R1 = 1, - ATTR_ODT_DIMM1_R0 = 4, - ATTR_ODT_DIMM1_R1 = 5, - - // Right justified output - makes it so we can use insertFromRight - CCS_ODT_DIMM0_R0 = 4, - CCS_ODT_DIMM0_R1 = 5, - CCS_ODT_DIMM1_R0 = 6, - CCS_ODT_DIMM1_R1 = 7, - - // Default ODT cycle length is 5 - one for the preamble and 4 for the data - DEFAULT_ODT_CYCLE_LEN = 5, - - // CCS MODEQ - STOP_ON_ERR = MCBIST_CCS_MODEQ_STOP_ON_ERR, - UE_DISABLE = MCBIST_CCS_MODEQ_UE_DISABLE, - DATA_COMPARE_BURST_SEL = MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL, - DATA_COMPARE_BURST_SEL_LEN = MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN, - DDR_CAL_TIMEOUT_CNT = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT, - DDR_CAL_TIMEOUT_CNT_LEN = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN, - CFG_PARITY_AFTER_CMD = MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD, - COPY_CKE_TO_SPARE_CKE = MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE, - DISABLE_ECC_ARRAY_CHK = MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK, - DISABLE_ECC_ARRAY_CORRECTION = MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION, - CFG_DGEN_FIXED_MODE = MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE, - DDR_CAL_TIMEOUT_CNT_MULT = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT, - DDR_CAL_TIMEOUT_CNT_MULT_LEN = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN, - IDLE_PAT_ADDRESS_0_13 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13, - IDLE_PAT_ADDRESS_0_13_LEN = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN, - IDLE_PAT_ADDRESS_17 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17, - IDLE_PAT_BANK_GROUP_1 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1, - IDLE_PAT_BANK_0_1 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1, - IDLE_PAT_BANK_0_1_LEN = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN, - IDLE_PAT_BANK_GROUP_0 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0, - IDLE_PAT_ACTN = MCBIST_CCS_MODEQ_IDLE_PAT_ACTN, - IDLE_PAT_ADDRESS_16 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16, - IDLE_PAT_ADDRESS_15 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15, - IDLE_PAT_ADDRESS_14 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14, - NTTM_MODE = MCBIST_CCS_MODEQ_NTTM_MODE, - NTTM_RW_DATA_DLY = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY, - NTTM_RW_DATA_DLY_LEN = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN, - IDLE_PAT_BANK_2 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2, - DDR_PARITY_ENABLE = MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, - IDLE_PAT_PARITY = MCBIST_CCS_MODEQ_IDLE_PAT_PARITY, - - // MCB_CNTRL - MCB_CNTL_PORT_SEL = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL, - MCB_CNTL_PORT_SEL_LEN = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN, - - // CCS CNTL - CCS_START = MCBIST_CCS_CNTLQ_START, - CCS_STOP = MCBIST_CCS_CNTLQ_STOP, - - // CCS STATQ - CCS_IN_PROGRESS = MCBIST_CCS_STATQ_IP, - - // ARR0 - ARR0_DDR_ADDRESS_0_13 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, - ARR0_DDR_ADDRESS_0_13_LEN = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN, - ARR0_DDR_ADDRESS_0_9 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, // Useful for rd/wr cmds - ARR0_DDR_ADDRESS_0_9_LEN = 10, // CA bits are 9:0, total length of 10 - ARR0_DDR_ADDRESS_10 = 10, // ADR10 is the 10th bit from the left in Nimbus ARR0 - ARR0_DDR_ADDRESS_17 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17, - ARR0_DDR_BANK_GROUP_1 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1, - ARR0_DDR_RESETN = MCBIST_CCS_INST_ARR0_00_DDR_RESETN, - ARR0_DDR_BANK_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1, - ARR0_DDR_BANK_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN, - ARR0_DDR_BANK_GROUP_0 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0, - ARR0_DDR_ACTN = MCBIST_CCS_INST_ARR0_00_DDR_ACTN, - ARR0_DDR_ADDRESS_16 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16, - ARR0_DDR_ADDRESS_15 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15, - ARR0_DDR_ADDRESS_14 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14, - ARR0_DDR_CKE = MCBIST_CCS_INST_ARR0_00_DDR_CKE, - ARR0_DDR_CKE_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN, - ARR0_DDR_CSN_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1, - ARR0_DDR_CSN_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN, - ARR0_DDR_CID_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1, - ARR0_DDR_CID_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN, - ARR0_DDR_CSN_2_3 = MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3, - ARR0_DDR_CSN_2_3_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN, - ARR0_DDR_CID_2 = MCBIST_CCS_INST_ARR0_00_DDR_CID_2, - ARR0_DDR_ODT = MCBIST_CCS_INST_ARR0_00_DDR_ODT, - ARR0_DDR_ODT_LEN = MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN, - ARR0_DDR_CAL_TYPE = MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE, - ARR0_DDR_CAL_TYPE_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN, - ARR0_DDR_PARITY = MCBIST_CCS_INST_ARR0_00_DDR_PARITY, - ARR0_DDR_BANK_2 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_2, - ARR0_LOOP_BREAK_MODE = MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE, - ARR0_LOOP_BREAK_MODE_LEN = MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN, - - // ARR1 - ARR1_IDLES = MCBIST_CCS_INST_ARR1_00_IDLES, - ARR1_IDLES_LEN = MCBIST_CCS_INST_ARR1_00_IDLES_LEN, - ARR1_REPEAT_CMD_CNT = MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, - ARR1_REPEAT_CMD_CNT_LEN = MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN, - ARR1_READ_OR_WRITE_DATA = MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA, - ARR1_READ_OR_WRITE_DATA_LEN = MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN, - ARR1_READ_COMPARE_REQUIRED = MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED, - ARR1_DDR_CAL_RANK = MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK, - ARR1_DDR_CAL_RANK_LEN = MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN, - ARR1_DDR_CALIBRATION_ENABLE = MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE, - ARR1_END = MCBIST_CCS_INST_ARR1_00_END, - ARR1_GOTO_CMD = MCBIST_CCS_INST_ARR1_00_GOTO_CMD, - ARR1_GOTO_CMD_LEN = MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN, - - }; -}; - -namespace mss -{ - -static constexpr uint64_t CKE_HIGH = 0b1111; -static constexpr uint64_t CKE_LOW = 0b0000; - -// CKE setup for rank 0-7 to support -// Currently only support 0, 1, 4, 5 -// Not supported ranks will always get 0 -// For self_refresh_entry_command() -static constexpr uint64_t CKE_ARY_SRE[] = -{ - // 0, 1, 2, 3, - 0b0111, 0b1011, 0, 0, - // 4, 5, 6, 7 - 0b0111, 0b1011, 0, 0 -}; - -// For self_refresh_exit_command() -static constexpr uint64_t CKE_ARY_SRX[] = -{ - // 0, 1, 2, 3, - 0b1000, 0b0100, 0, 0, - // 4, 5, 6, 7 - 0b1000, 0b0100, 0, 0 -}; - -namespace ccs -{ - -enum rank_configuration -{ - DUAL_DIRECT = 0, - QUAD_ENCODED = 1, - // Note: we don't include QUAD_DIRECT in here - // That's because it uses 4 CS and is board wiring dependent - // Not sure if it would use CS23 or CID01 for CS2/3 -}; - -/// -/// @brief Enums for CCS return codes -/// -enum -{ - // Success is defined as done-bit set, no others. - STAT_QUERY_SUCCESS = 0x4000000000000000, - - // Bit positions 3:5 - STAT_READ_MISCOMPARE = 0x1000000000000000, - STAT_UE_SUE = 0x0800000000000000, - STAT_CAL_TIMEOUT = 0x0400000000000000, - - // If the fail type isn't one of these, we're hung - STAT_HUNG = 0x0ull, -}; - -/// -/// @class instruction_t -/// @brief Class for ccs instructions -/// @tparam T fapi2::TargetType representing the target of the CCS instructions -/// @note A ccs instruction is data (array 0) and some control information (array 1)cc -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -class instruction_t -{ - public: - fapi2::buffer<uint64_t> arr0; - fapi2::buffer<uint64_t> arr1; - // The MCA indexed rank on which to operate. If this is invalid, all ranks will be disabled - uint64_t iv_rank; - // We want to have a switch to update rank or not. A user might want to setup CS in some weird way - // In that case, they don't want us "fixing" their CS values - // We'll default the rank to be updated - we want to send out CS properly - bool iv_update_rank; - - /// - /// @brief intstruction_t ctor - /// @param[in] i_rank the rank this instruction is headed for - /// @param[in] i_arr0 the initial value for arr0, defaults to 0 - /// @param[in] i_arr1 the initial value for arr1, defaults to 0 - /// @param[in] i_update_rank true if the rank should be updated before being sent, defaults to true - /// - instruction_t( uint64_t i_rank = NO_CHIP_SELECT_ACTIVE, - const fapi2::buffer<uint64_t> i_arr0 = 0, - const fapi2::buffer<uint64_t> i_arr1 = 0, - const bool i_update_rank = true): - arr0(i_arr0), - arr1(i_arr1), - iv_rank(i_rank), - iv_update_rank(i_update_rank) - { - // Skip setting up the rank if hte user doesn't want us to - if(iv_update_rank) - { - // Set the chip selects to be 1's (not active) - // We'll fix these up before executing the instructions - arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, - TT::ARR0_DDR_CSN_0_1_LEN>(0b11); - arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, - TT::ARR0_DDR_CSN_2_3_LEN>(0b11); - } - } - - /// - /// @brief Updates the rank based upon the passed in rank configuration encoding - /// @param[in] i_target the port target for this instruction - for error logging - /// @param[in] i_rank_config the rank configuration - /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok - /// - fapi2::ReturnCode configure_rank(const fapi2::Target<TT::PORT_TARGET_TYPE>& i_target, - const rank_configuration i_rank_config ) - { - // If this instrunction is set to not update the rank, then don't update the rank - if(!iv_update_rank) - { - return fapi2::FAPI2_RC_SUCCESS; - } - - // Regardless of rank configurations, if we have NO_CHIP_SELECT_ACTIVE, deactivate all CS - if(iv_rank == NO_CHIP_SELECT_ACTIVE) - { - arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(0b11); - arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(0b11); - return fapi2::FAPI2_RC_SUCCESS; - } - - // First, check rank - we need to make sure that we have a valid rank - FAPI_ASSERT(iv_rank < MAX_MRANK_PER_PORT, - fapi2::MSS_INVALID_RANK() - .set_MCA_TARGET(i_target) - .set_RANK(iv_rank) - .set_FUNCTION(ffdc_function_codes::CCS_INST_CONFIGURE_RANK), - "%s rank out of bounds rank%u", mss::c_str(i_target), iv_rank); - - // Now the fun happens and we can deal with the actual encoding - - // If we're quad mode, setup the encoding accordingly - if(i_rank_config == rank_configuration::QUAD_ENCODED) - { - // CS 0/1 are first, while CID0/1 are second - // In quad enabled mode, CID acts as a "package select" - // It selects R0/2 vs R1/3 - // CS0 vs CS1 selects the low vs high rank in the package - // CS0 will select rank 0/1 - // CS1 will select rank 2/3 - - // Note: this is to workaround a Nimbus CCS bug - // 1) Nimbus thinks that CID0 is a CID not part of the CS for encoded mode - // 2) CID1 doesn't matter for quad encode - // 3) we only access ranks 2,3 in encoded mode - // 4) we can fake out parity by adding in another 1, so let's do that with CID1 - // This is easier than calculating our own parity - // CS0 H, CS1 L, CID0-> L => Rank 2 - - static const std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] = - { - // CS0 L, CS1 H, CID0-> L => Rank 0 - { 0b01, 0b00 }, - - // CS0 L, CS1 H, CID0-> H => Rank 1 - { 0b01, 0b11 }, - - // CS0 H, CS1 L, CID0-> L => Rank 2 - { 0b10, 0b00 }, - - // CS0 H, CS1 L, CID0-> H => Rank 3 - { 0b10, 0b11 }, - }; - - const auto l_dimm_rank = mss::index(iv_rank); - const bool l_is_dimm0 = iv_rank < MAX_RANK_PER_DIMM; - constexpr uint64_t NON_DIMM_CS = 0b11; - - // Assigns the CS based upon which DIMM we're at - const auto CS01 = l_is_dimm0 ? CS_N[l_dimm_rank].first : NON_DIMM_CS; - const auto CS23 = l_is_dimm0 ? NON_DIMM_CS : CS_N[l_dimm_rank].first; - - // Setup that rank - arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, - TT::ARR0_DDR_CSN_0_1_LEN>(CS01); - arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, - TT::ARR0_DDR_CSN_2_3_LEN>(CS23); - arr0.insertFromRight<TT::ARR0_DDR_CID_0_1, - TT::ARR0_DDR_CID_0_1_LEN>(CS_N[l_dimm_rank].second); - } - - // Otherwise, setup for dual-direct mode (our only other supported mode at the moment) - else - { - // For DIMM0 .first is the CSN_0_1 setting, .second is the CSN_2_3 setting. - // For DIMM1 .first is the CSN_2_3 setting, .second is the CSN_0_1 setting. - static const std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] = - { - // CS0 L CS1 H => CS2 => H CS3 => H Rank 0 - { 0b01, 0b11 }, - - // CS0 H CS1 L => CS2 => H CS3 => H Rank 1 - { 0b10, 0b11 }, - - // CS0 H CS1 H => CS2 => L CS3 => H Rank 2 - { 0b11, 0b01 }, - - // CS0 H CS1 H => CS2 => H CS3 => L Rank 3 - { 0b11, 0b10 }, - }; - - const auto l_dimm_rank = mss::index(iv_rank); - const bool l_is_dimm0 = iv_rank < MAX_RANK_PER_DIMM; - - // Assigns the CS based upon which DIMM we're at - const auto CS01 = l_is_dimm0 ? CS_N[l_dimm_rank].first : CS_N[l_dimm_rank].second; - const auto CS23 = l_is_dimm0 ? CS_N[l_dimm_rank].second : CS_N[l_dimm_rank].first; - - // Setup that rank - arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, - TT::ARR0_DDR_CSN_0_1_LEN>(CS01); - arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, - TT::ARR0_DDR_CSN_2_3_LEN>(CS23); - - // Check that we don't have a rank out of bounds case here - // We can only have that if - // 1) we are DIMM1 - // 2) our DIMM rank is greater than the maximum allowed number of ranks on DIMM1 - // So, we pass always if we're DIMM0, or if our DIMM rank is less than the maximum number of DIMM's on rank 1 - FAPI_ASSERT(l_dimm_rank < MAX_RANKS_DIMM1 || l_is_dimm0, - fapi2::MSS_INVALID_RANK() - .set_MCA_TARGET(i_target) - .set_RANK(iv_rank) - .set_FUNCTION(ffdc_function_codes::CCS_INST_CONFIGURE_RANK), - "%s rank out of bounds rank%u", mss::c_str(i_target), iv_rank); - } - - return fapi2::FAPI2_RC_SUCCESS; - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Equals comparison operator - /// @param[in] i_rhs - the instruction to compare to - /// @return True if both instructions are equal - /// - inline bool operator==( const instruction_t<T>& i_rhs ) const - { - return arr0 == i_rhs.arr0 && - arr1 == i_rhs.arr1 && - iv_rank == i_rhs.iv_rank && - iv_update_rank == i_rhs.iv_update_rank; - } -}; - -/// -/// @brief Determines our rank configuration type across all ports -/// @param[in] i_target the MCA target on which to operate -/// @param[out] o_rank_config the rank configuration -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode get_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - std::vector<rank_configuration>& o_rank_config); - -/// -/// @brief Determines our rank configuration type -/// @param[in] i_target the MCA target on which to operate -/// @param[out] o_rank_config the rank configuration -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode get_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - rank_configuration& o_rank_config); - -/// -/// @brief A class representing a series of CCS instructions, and the -/// CCS engine parameters associated with running the instructions -/// @tparam T fapi2::TargetType representing the fapi2 target which -/// @tparam P fapi2::TargetType representing the port -/// contains the CCS engine (e.g., fapi2::TARGET_TYPE_MCBIST) -template< fapi2::TargetType T, fapi2::TargetType P = fapi2::TARGET_TYPE_MCA > -class program -{ - public: - // Setup our poll parameters so the CCS executer can see - // whether to use the delays in the instruction stream or not - program(): iv_poll(0, 0) - {} - - // Vector of instructions - std::vector< instruction_t<T> > iv_instructions; - poll_parameters iv_poll; - - // Vector of polling probes - std::vector< poll_probe<P> > iv_probes; -}; - -/// -/// @brief Common setup for all MRS/RCD instructions -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in,out] i_arr0 fapi2::buffer<uint64_t> representing the ARR0 of the instruction -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -static void mrs_rcd_helper( fapi2::buffer<uint64_t>& i_arr0 ) -{ - // - // Generic DDR4 MRS setup (RCD is an MRS) - // - // CKE is high Note: P8 set all 4 of these high - not sure if that's correct. BRS - i_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // ACT is high - i_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS, CAS, WE low - i_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>() - .template clearBit<TT::ARR0_DDR_ADDRESS_15>() - .template clearBit<TT::ARR0_DDR_ADDRESS_14>(); -} - -/// -/// @brief Setup activate command instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> act_command( const uint64_t i_rank) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // Set all CKE to high - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // ACT is high - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ACTN>(); - - // RAS low, CAS low, WE low - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>() - .template clearBit<TT::ARR0_DDR_ADDRESS_15>() - .template clearBit<TT::ARR0_DDR_ADDRESS_14>(); - - // Just leaving the row addresses to all 0 for now - // row, bg, ba set to 0 - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_17>(); - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_0_13, TT::ARR0_DDR_ADDRESS_0_13_LEN>(); - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_1>(); - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_0>(); - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_0_1, TT::ARR0_DDR_BANK_0_1_LEN>(); - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_2>(); - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Create, initialize an RCD (RCW - JEDEC) CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the DIMM this instruction is headed for -/// @param[in] i_turn_on_cke flag that states whether we want CKE on for this RCW (defaulted to true) -/// @return the RCD CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> rcd_command( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const bool i_sim, - const bool i_turn_on_cke = true) -{ - fapi2::buffer<uint64_t> rcd_boilerplate_arr0; - fapi2::buffer<uint64_t> rcd_boilerplate_arr1; - - // - // Generic DDR4 MRS setup (RCD is an MRS) - // - mrs_rcd_helper<fapi2::TARGET_TYPE_MCBIST>(rcd_boilerplate_arr0); - - // Not adding i_turn_on_cke in the mrs_rcd helper because we only need this - // for RCWs and there is no need to complicate/change the MRS cmd API with - // uneeded functionality. Little duplication, but this isolates the change. - if( !i_sim ) - { - const uint64_t l_cke = i_turn_on_cke ? CKE_HIGH : CKE_LOW; - rcd_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_cke); - } - - // - // RCD setup - // - // DDR4: Set BG1 to 0 during an MRS. - // BG0, BA1:BA0 to 0b111 selects RCW (aka MR7). - rcd_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_1>() - .template insertFromRight<TT::ARR0_DDR_BANK_0_1, TT::ARR0_DDR_BANK_0_1_LEN>(0b11) - .template setBit<TT::ARR0_DDR_BANK_GROUP_0>(); - - // RCD always goes to the 0th rank on the DIMM; either 0 or 4. - return instruction_t<T>((mss::index(i_target) == 0) ? 0 : 4, rcd_boilerplate_arr0, rcd_boilerplate_arr1); -} - -/// -/// @brief Create, initialize an MRS CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_mrs the specific MRS -/// @return the MRS CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> mrs_command (const uint64_t i_rank, - const uint64_t i_mrs ) -{ - fapi2::buffer<uint64_t> rcd_boilerplate_arr0; - fapi2::buffer<uint64_t> rcd_boilerplate_arr1; - fapi2::buffer<uint8_t> mrs(i_mrs); - - // - // Generic DDR4 MRS setup (RCD is an MRS) - // - mrs_rcd_helper<fapi2::TARGET_TYPE_MCBIST>(rcd_boilerplate_arr0); - - // - // MRS setup - // - // DDR4: Set BG1 to 0. BG0, BA1:BA0 to i_mrs - rcd_boilerplate_arr0.clearBit<TT::ARR0_DDR_BANK_GROUP_1>(); - mss::swizzle<TT::ARR0_DDR_BANK_0_1, 3, 7>(mrs, rcd_boilerplate_arr0); - FAPI_DBG("mrs rcd boiler 0x%llx 0x%llx", uint8_t(mrs), uint64_t(rcd_boilerplate_arr0)); - return instruction_t<T>(i_rank, rcd_boilerplate_arr0, rcd_boilerplate_arr1); -} - -/// -/// @brief Create, initialize a JEDEC Device Deselect CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_idle the idle time to the next command (default to 0) -/// @return the Device Deselect CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> des_command(const uint16_t i_idle = 0) -{ - fapi2::buffer<uint64_t> rcd_boilerplate_arr0; - fapi2::buffer<uint64_t> rcd_boilerplate_arr1; - - // ACT is high. It's a no-care in the spec but it seems to raise questions when - // people look at the trace, so lets set it high. - rcd_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // CKE is high Note: P8 set all 4 of these high - not sure if that's correct. BRS - rcd_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // Insert idle - rcd_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle ); - - // ACT is high no-care - // RAS, CAS, WE no-care - - // Device Deslect wants CS_n always high (select nothing using rank NO_CHIP_SELECT_ACTIVE) - return instruction_t<T>( NO_CHIP_SELECT_ACTIVE, - rcd_boilerplate_arr0, - rcd_boilerplate_arr1); -} - -/// -/// @brief Converts an ODT attribute to CCS array input -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_attr_value ODT attribute value -/// @return CCS value for the ODT's -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline uint8_t convert_odt_attr_to_ccs(const fapi2::buffer<uint8_t>& i_attr_value) -{ - // ODT value buffer - fapi2::buffer<uint8_t> l_ccs_value; - l_ccs_value.template writeBit<TT::CCS_ODT_DIMM0_R0>(i_attr_value.template getBit<TT::ATTR_ODT_DIMM0_R0>()) - .template writeBit<TT::CCS_ODT_DIMM0_R1>(i_attr_value.template getBit<TT::ATTR_ODT_DIMM0_R1>()) - .template writeBit<TT::CCS_ODT_DIMM0_R0>(i_attr_value.template getBit<TT::ATTR_ODT_DIMM0_R0>()) - .template writeBit<TT::CCS_ODT_DIMM1_R0>(i_attr_value.template getBit<TT::ATTR_ODT_DIMM1_R0>()) - .template writeBit<TT::CCS_ODT_DIMM1_R1>(i_attr_value.template getBit<TT::ATTR_ODT_DIMM1_R1>()); - - return uint8_t(l_ccs_value); -} - -/// -/// @brief Create, initialize a JEDEC Device Deselect CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_odt_values CCS defined ODT values -/// @param[in] i_cycles the number of cycles to hold the ODT for - defaults to DEFAULT_ODT_CYCLE_LEN -/// @return the Device Deselect CCS instruction -/// @note This technically is not a JEDEC command, but is needed for CCS to hold the ODT cycles -/// CCS by design does not repeat or latch ODT's appropriately -/// As such, it's up to the programmers to hold the ODT's appropriately -/// This "command" will greatly help us do that -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> odt_command(const uint8_t i_odt_values, const uint64_t i_cycles = TT::DEFAULT_ODT_CYCLE_LEN) -{ - auto l_odt_cmd = des_command<T>(); - l_odt_cmd.arr0.template insertFromRight<TT::ARR0_DDR_ODT, TT::ARR0_DDR_ODT_LEN>(i_odt_values); - l_odt_cmd.arr1.template insertFromRight<TT::ARR1_REPEAT_CMD_CNT, TT::ARR1_REPEAT_CMD_CNT_LEN>(i_cycles); - - return l_odt_cmd; -} - - -/// -/// @brief Create, initialize a NTTM read CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @return the Device Deselect CCS instruction -/// @note need to setup 4 cycles delay -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> nttm_read_command() -{ - // setup 4 cycles delay - constexpr uint64_t NTTM_READ_DELAY = 4; - // No.. there's no field for this one. it's an undocumented bit - constexpr uint64_t NTTM_MODE_FORCE_READ = 33; - - // get the des_command - auto l_command = des_command<T>(); - // set to CCS_INST_ARR1 register - l_command.arr1.template setBit<NTTM_MODE_FORCE_READ>(); - l_command.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(NTTM_READ_DELAY); - - return l_command; -} - -/// -/// @brief Create, initialize a JEDEC Device Power Down Entry CCS command -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @return the Device Deselect CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> pde_command() -{ - fapi2::buffer<uint64_t> rcd_boilerplate_arr0; - fapi2::buffer<uint64_t> rcd_boilerplate_arr1; - - // Power Down Entry just like a DES, but we set CKE low - instruction_t<T> l_inst = des_command<T>(); - - // CKE is low. Note: P8 set all 4 of these low - not sure if that's correct. - l_inst.arr0.template insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_LOW); - - l_inst.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( mss::tcpded() ); - - return l_inst; -} - -/// -/// @brief Create, initialize an instruction which indicates an initial cal -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rp the rank-pair (rank) to cal -/// @return the initial cal instruction -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> initial_cal_command(const uint64_t i_rp) -{ - // An initial cal arr0 looks just like a DES, but we set the initial cal bits - instruction_t<T> l_inst = des_command<T>(); - - // ACT is low - per Centaur spec (Shelton to confirm for Nimbus) BRS - l_inst.arr0.template clearBit<TT::ARR0_DDR_ACTN>(); - - l_inst.arr0.template insertFromRight<TT::ARR0_DDR_CAL_TYPE, TT::ARR0_DDR_CAL_TYPE_LEN>(0b1100); - l_inst.arr1.template setBit<TT::ARR1_DDR_CALIBRATION_ENABLE>(); - -#ifdef USE_LOTS_OF_IDLES - // Idles is 0xFFFF - per Centaur spec (Shelton to confirm for Nimbus) BRS - l_inst.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(0xFFFF); -#else - l_inst.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(0x0); -#endif - - // The rank we're calibrating is enacoded - it's an int. So rank 3 is 0011 not 0001 - l_inst.arr1.template insertFromRight<TT::ARR1_DDR_CAL_RANK, TT::ARR1_DDR_CAL_RANK_LEN>(i_rp); - - return l_inst; -} - -/// -/// @brief Setup ZQ Long instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the DIMM this instruction is headed for -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_idle the idle time to the next command (default to 0) -/// @return the MRS CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> zqcl_command( const uint64_t i_rank, - const uint16_t i_idle = 0 ) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // CKE is high Note: P8 set all 4 of these high - not sure if that's correct. BRS - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // ACT is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS/CAS high, WE low - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_16>() - .template setBit<TT::ARR0_DDR_ADDRESS_15>() - .template clearBit<TT::ARR0_DDR_ADDRESS_14>(); - - // ADDR10/AP is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_10>(); - - // Insert idle - l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle ); - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup read command helper function -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_bank_addr bank address bits [BG0:BG1] = [62:63] (right aligned) -/// @param[in] i_bank_group_addr bank group address bits [BA0:BA1] = [62:63] (right aligned) -/// @param[in] i_column_addr column address bits [A0:A9] = [54:63] (right aligned) -/// @return the read command CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -static fapi2::buffer<uint64_t> read_cmd_boilerplate( const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_bank_addr = 0, - const fapi2::buffer<uint64_t>& i_bank_group_addr = 0, - const fapi2::buffer<uint64_t>& i_column_addr = 0) -{ - // TODO - RTC 166175 Encapsulate command truth table in a subclass for ccs.H - fapi2::buffer<uint64_t> l_boilerplate_arr0; - - // CKE is high Note: P8 set all 4 of these high - not sure if that's correct. AAM - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, - TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // ACT is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS high, CAS low, WE high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_16>() - .template clearBit<TT::ARR0_DDR_ADDRESS_15>() - .template setBit<TT::ARR0_DDR_ADDRESS_14>(); - - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_BANK_0_1, - TT::ARR0_DDR_BANK_0_1_LEN>(i_bank_addr); - - // Bank Group takes a little effort - the bits aren't contiguous - constexpr uint64_t BG0_BIT = 62; - constexpr uint64_t BG1_BIT = 63; - - l_boilerplate_arr0.writeBit<TT::ARR0_DDR_BANK_GROUP_0>(i_bank_group_addr.getBit<BG0_BIT>()) - .template writeBit<TT::ARR0_DDR_BANK_GROUP_1>(i_bank_group_addr.getBit<BG1_BIT>()); - - // CA is A[0:9] - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_ADDRESS_0_9, - TT::ARR0_DDR_ADDRESS_0_9_LEN>(i_column_addr); - - return l_boilerplate_arr0; -} - -/// -/// @brief Setup write command (Fixed BL8 or BC4) instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_bank_addr bank address bits [BA0:BA1] = [62:63] (right aligned) -/// @param[in] i_bank_group_addr bank group address bits [BG0:BG1] = [62:63] (right aligned) -/// @param[in] i_column_addr column address bits [A0:A9] = [54:63] (right aligned) -/// @return the write command CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> wr_command( const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_bank_addr = 0, - const fapi2::buffer<uint64_t>& i_bank_group_addr = 0, - const fapi2::buffer<uint64_t>& i_column_addr = 0) -{ - // WR's and RD's are very similar, so we just use the RD command boiler plate and modify the command to a WR - fapi2::buffer<uint64_t> l_boilerplate_arr0 = read_cmd_boilerplate<T>(i_rank, - i_bank_addr, - i_bank_group_addr, - i_column_addr); - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // RAS high, CAS low, WE low - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_16>() - .template clearBit<TT::ARR0_DDR_ADDRESS_15>() - .template clearBit<TT::ARR0_DDR_ADDRESS_14>(); - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup read command (Fixed BL8 or BC4) instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_bank_addr bank address bits [BA0:BA1] = [62:63] (right aligned) -/// @param[in] i_bank_group_addr bank group address bits [BG0:BG1] = [62:63] (right aligned) -/// @param[in] i_column_addr column address bits [A0:A9] = [54:63] (right aligned) -/// @return the read command CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> rd_command( const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_bank_addr = 0, - const fapi2::buffer<uint64_t>& i_bank_group_addr = 0, - const fapi2::buffer<uint64_t>& i_column_addr = 0) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - l_boilerplate_arr0 = read_cmd_boilerplate<fapi2::TARGET_TYPE_MCBIST>(i_rank, - i_bank_addr, - i_bank_group_addr, - i_column_addr); - - // Setup ADDR10/AP based on read type - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_10>(); - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup read w/auto precharge command (Fixed BL8 or BC4) instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_bank_addr bank address bits [BG0:BG1] = [62:63] (right aligned) -/// @param[in] i_bank_group_addr bank group address bits [BA0:BA1] = [62:63] (right aligned) -/// @param[in] i_column_addr column address bits [A0:A9] = [54:63] (right aligned) -/// @return the read command CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> rda_command( const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_bank_addr = 0, - const fapi2::buffer<uint64_t>& i_bank_group_addr = 0, - const fapi2::buffer<uint64_t>& i_column_addr = 0) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - l_boilerplate_arr0 = read_cmd_boilerplate<fapi2::TARGET_TYPE_MCBIST>(i_rank, - i_bank_addr, - i_bank_group_addr, - i_column_addr); - - // Setup ADDR10/AP based on read type - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_10>(); - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup precharge all banks command instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_idle the idle time to the next command (default to 0) -/// @return the precharge all banks command CCS instruction -/// @note THIS IS DDR4 ONLY RIGHT NOW. We can (and possibly should) specialize this -/// for the controller (Nimbus v Centaur) and then correct for DRAM generation (not included -/// in this template definition) -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> precharge_all_command( const uint64_t i_rank, - const uint16_t i_idle = 0 ) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // CKE is high Note: P8 set all 4 of these high - not sure if that's correct. AAM - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_HIGH); - - // ACT is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS low, CAS high, WE low - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>() - .template setBit<TT::ARR0_DDR_ADDRESS_15>() - .template clearBit<TT::ARR0_DDR_ADDRESS_14>(); - - // Setup ADDR10/AP high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_10>(); - - // Insert idle - l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle ); - - // From DDR4 Spec table 17: - // All other bits from the command truth table or 'V', for valid (1 or 0) - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup self-refresh entry command instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_idle the idle time to the next command (default to 0) -/// @return the self-refresh entry command CCS instruction -/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> self_refresh_entry_command( const uint64_t i_rank, const uint16_t i_idle = 0 ) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // Set all CKE to high except the rank passed in - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_ARY_SRE[i_rank]); - - // ACT is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS low, CAS low, WE high - l_boilerplate_arr0.clearBit<TT::ARR0_DDR_ADDRESS_16>() - .template clearBit<TT::ARR0_DDR_ADDRESS_15>() - .template setBit<TT::ARR0_DDR_ADDRESS_14>(); - - // Insert idle - l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle ); - - // From DDR4 Spec table 17: - // All other bits from the command truth table are 'V', for valid (1 or 0) - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -/// -/// @brief Setup self-refresh exit using NOP command instruction -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_rank the rank on this dimm -/// @param[in] i_idle the idle time to the next command (default to 0) -/// @return the self-refresh exit command CCS instruction -/// @note Using NOP in case SDRAM is in gear down mode and max power saving mode exit -/// @note THIS IS FOR DDR4 NON-LRDIMM ONLY RIGHT NOW -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline instruction_t<T> self_refresh_exit_command( const uint64_t i_rank, const uint16_t i_idle = 0 ) -{ - fapi2::buffer<uint64_t> l_boilerplate_arr0; - fapi2::buffer<uint64_t> l_boilerplate_arr1; - - // Set all CKE to low except the rank passed in - l_boilerplate_arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(CKE_ARY_SRX[i_rank]); - - // ACT is high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ACTN>(); - - // RAS high, CAS high, WE high - l_boilerplate_arr0.setBit<TT::ARR0_DDR_ADDRESS_16>() - .template setBit<TT::ARR0_DDR_ADDRESS_15>() - .template setBit<TT::ARR0_DDR_ADDRESS_14>(); - - // Insert idle - l_boilerplate_arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>( i_idle ); - - // From DDR4 Spec table 17: - // All other bits from the command truth table are 'V', for valid (1 or 0) - - return instruction_t<T>(i_rank, l_boilerplate_arr0, l_boilerplate_arr1); -} - -// -// These functions are a little sugar to keep callers from doing the traits-dance to get the -// appropriate bit field -// - -/// -/// @brief Select the port(s) to be used by the CCS -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in] i_ports the buffer representing the ports -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline fapi2::ReturnCode select_ports( const fapi2::Target<T>& i_target, uint64_t i_ports) -{ - fapi2::buffer<uint64_t> l_data; - fapi2::buffer<uint64_t> l_ports; - - // Not handling multiple ports here, can't do that for CCS. BRS - FAPI_TRY( l_ports.setBit(i_ports) ); - - FAPI_TRY( mss::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); - l_data.insert<TT::MCB_CNTL_PORT_SEL, TT::MCB_CNTL_PORT_SEL_LEN>(l_ports); - FAPI_TRY( mss::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief User sets to a '1'b to tell the Hdw to stop CCS whenever failure occurs. When a -/// '0'b, Hdw will continue CCS even if a failure occurs. -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @param[in] i_value true iff stop whenever failure occurs. -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline void stop_on_err( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) -{ - io_buffer.writeBit<TT::STOP_ON_ERR>(i_value); -} - -/// -/// @brief Disable ECC checking on the CCS arrays -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline void disable_ecc( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer) -{ - io_buffer.setBit<TT::DISABLE_ECC_ARRAY_CHK>() - .template setBit<TT::DISABLE_ECC_ARRAY_CORRECTION>(); -} - -/// -/// @brief User sets to a '1'b to force the Hdw to ignore any array ue or sue errors -/// during CCS command fetching. -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @param[in] i_value true iff ignore any array ue or sue errors. -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline void ue_disable( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) -{ - io_buffer.writeBit<TT::UE_DISABLE>(i_value); -} - -/// -/// @brief User sets to a '1'b to force the Hdw to delay parity a cycle -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @param[in] i_value mss::ON iff delay parity a cycle -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline void parity_after_cmd( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value) -{ - io_buffer.writeBit<TT::CFG_PARITY_AFTER_CMD>(i_value); -} - -/// -/// @brief DDr calibration counter -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @param[in] i_count the count to wait for DDR cal to complete. -/// @param[in] i_mult the DDR calibration time multiplaction factor -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline void cal_count( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, - const uint64_t i_count, const uint64_t i_mult) -{ - io_buffer.insertFromRight<TT::DDR_CAL_TIMEOUT_CNT, TT::DDR_CAL_TIMEOUT_CNT_LEN>(i_count); - io_buffer.insertFromRight<TT::DDR_CAL_TIMEOUT_CNT_MULT, TT::DDR_CAL_TIMEOUT_CNT_MULT_LEN>(i_mult); -} - -/// -/// @brief Copy CKE signals to CKE Spare on both ports NOTE: DOESN'T APPLY FOR NIMBUS. NO -/// SPARE CHIPS TO COPY TO. 0 - Spare CKEs not copied with values from CKE(0:1) and -/// CKE(4:5) 1 - Port A CKE(0:1) copied to Port A CKE(2:3), Port A CKE(4:5) copied -/// to Port A CKE(6:7), Port B CKE(0:1) copied to Port B CKE(2:3) and Port B CKE(4:5) -/// copied to Port B CKE(6:7) -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the ccsTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @param[in] i_value mss::ON iff Copy CKE signals to CKE Spare on both ports -/// @note no-op for p9n -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -void copy_cke_to_spare_cke( const fapi2::Target<T>&, fapi2::buffer<uint64_t>& io_buffer, const states i_value); - -/// -/// @brief Read the modeq register appropriate for this target -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in,out] io_buffer the buffer representing the mode register -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline fapi2::ReturnCode read_mode( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& io_buffer) -{ - FAPI_DBG("read mode 0x%llx", TT::MODEQ_REG); - return mss::getScom(i_target, TT::MODEQ_REG, io_buffer); -} - -/// -/// @brief Write the modeq register appropriate for this target -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in] i_buffer the buffer representing the mode register -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline fapi2::ReturnCode write_mode( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_buffer) -{ - return mss::putScom(i_target, TT::MODEQ_REG, i_buffer); -} - -/// -/// @brief config the NTTM -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_mcbist the target to operate -/// @param[in] i_nttm_mode NTTM we need to turn on or off (i.e. ON, OFF) -/// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -inline fapi2::ReturnCode configure_nttm( const fapi2::Target<T>& i_target, - const mss::states i_nttm_mode) -{ - fapi2::buffer<uint64_t> l_data; - - FAPI_TRY(read_mode(i_target, l_data)); - - l_data.writeBit<TT::NTTM_MODE>(i_nttm_mode); - - FAPI_TRY(write_mode(i_target, l_data)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Execute a set of CCS instructions - multiple ports -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in] i_program the vector of instructions -/// @param[in] i_ports the vector of ports -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, fapi2::TargetType P, typename TT = ccsTraits<T> > -fapi2::ReturnCode execute( const fapi2::Target<T>& i_target, - ccs::program<T>& i_program, - const std::vector< fapi2::Target<P> >& i_ports); - -/// -/// @brief Execute a set of CCS instructions - single port -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam P the target of the CCS instruction (the port) -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in] i_program the vector of instructions -/// @param[in] i_port The target that's being programmed by the array -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, fapi2::TargetType P, typename TT = ccsTraits<T> > -fapi2::ReturnCode execute( const fapi2::Target<T>& i_target, - ccs::program<T>& i_program, - const fapi2::Target<P>& i_port) -{ - // Mmm. Might want to find a better way to do this - seems expensive. BRS - std::vector< fapi2::Target<P> > l_ports{ i_port }; - return execute(i_target, i_program, l_ports); -} - -/// -/// @brief Execute a CCS array already loaded in to the engine -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam P the target of the CCS instruction (the port) -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target the target to effect -/// @param[in] i_program the MCBIST ccs program - to get the polling parameters -/// @param[in] i_port the port associated with the MCBIST array -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, fapi2::TargetType P, typename TT = ccsTraits<T> > -fapi2::ReturnCode execute_inst_array(const fapi2::Target<T>& i_target, - ccs::program<T>& i_program, - const fapi2::Target<P>& i_port); - -/// -/// @brief Start or stop the CCS engine -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target The MCBIST containing the CCS engine -/// @param[in] i_start_stop bool MSS_CCS_START for starting MSS_CCS_STOP otherwise -/// @return FAPI2_RC_SUCCESS iff success -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -fapi2::ReturnCode start_stop( const fapi2::Target<T>& i_target, const bool i_start_stop ); - -/// -/// @brief Query the status of the CCS engine -/// @tparam T the target type of the chiplet which executes the CCS instruction -/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction -/// @param[in] i_target The MCBIST containing the CCS engine -/// @param[out] io_status The query result first being the result, second the type -/// @return FAPI2_RC_SUCCESS iff success -/// -template< fapi2::TargetType T, typename TT = ccsTraits<T> > -fapi2::ReturnCode status_query( const fapi2::Target<T>& i_target, std::pair<uint64_t, uint64_t>& io_status ); - -/// -/// @brief Determine the CCS failure type -/// @param[in] i_target MCBIST target -/// @param[in] i_type the failure type -/// @param[in] i_mca The port the CCS instruction is training -/// @return ReturnCode associated with the fail. -/// @note FFDC is handled here, caller doesn't need to do it -/// -fapi2::ReturnCode fail_type( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - const uint64_t& i_type, - const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_mca ); - -} // ends namespace ccs -} - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C new file mode 100644 index 000000000..d3725beee --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C @@ -0,0 +1,243 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_nimbus.C +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> + +#include <mss.H> +#include <lib/fir/check.H> +#include <lib/phy/mss_lrdimm_training.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/ccs/ccs_nimbus.H> + +#ifdef LRDIMM_CAPABLE + #include <lib/workarounds/quad_encode_workarounds.H> +#endif + +using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_MCA; +using fapi2::FAPI2_RC_SUCCESS; + +// Generates linkage +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::NIMBUS>::CS_N[]; +constexpr std::pair<uint64_t, uint64_t> ccsTraits<mss::mc_type::NIMBUS>::CS_ND[]; + +namespace mss +{ +namespace ccs +{ + +/// +/// @brief Select the port(s) to be used by the CCS - EXPLORER specialization +/// @param[in] i_target the target to effect +/// @param[in] i_ports the buffer representing the ports +/// +template<> +fapi2::ReturnCode select_ports<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + uint64_t i_ports) +{ + typedef ccsTraits<mss::mc_type::NIMBUS> TT; + fapi2::buffer<uint64_t> l_data; + fapi2::buffer<uint64_t> l_ports; + + // Not handling multiple ports here, can't do that for CCS. BRS + FAPI_TRY( l_ports.setBit(i_ports) ); + + FAPI_TRY( mss::getScom(i_target, TT::MCB_CNTL_REG, l_data) ); + l_data.insert<TT::MCB_CNTL_PORT_SEL, TT::MCB_CNTL_PORT_SEL_LEN>(l_ports); + FAPI_TRY( mss::putScom(i_target, TT::MCB_CNTL_REG, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Execute a set of CCS instructions - multiple ports - NIMBUS specialization +/// @param[in] i_program the vector of instructions +/// @param[in] i_ports the vector of ports +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode cleanup_from_execute<fapi2::TARGET_TYPE_MCA, mss::mc_type::NIMBUS>(const ccs::program& i_program, + const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> >& i_ports) +{ +#if LRDIMM_CAPABLE + + if(mss::workarounds::contains_command_mrs(i_program.iv_instructions)) + { + // Get ranks in pair bombs out if we can't get any ranks in this pair, so we should be safe here + for (const auto& p : i_ports) + { + FAPI_TRY(mss::workarounds::fix_shadow_register_corruption(p)); + } + } + +fapi_try_exit: + return fapi2::current_err; + +#else + return fapi2::FAPI2_RC_SUCCESS; + +#endif +} + +/// +/// @brief Determine the CCS failure type +/// @param[in] i_target MCBIST target +/// @param[in] i_type the failure type +/// @param[in] i_port The port the CCS instruction is training +/// @return ReturnCode associated with the fail. +/// @note FFDC is handled here, caller doesn't need to do it +/// +template<> +fapi2::ReturnCode fail_type( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, + const uint64_t i_type, + const fapi2::Target<TARGET_TYPE_MCA>& i_port ) +{ + typedef ccsTraits<mss::mc_type::NIMBUS> TT; + + fapi2::ReturnCode l_failing_rc(fapi2::FAPI2_RC_SUCCESS); + // Including the MCA_TARGET here and below at CAL_TIMEOUT since these problems likely lie at the MCA level + // So we disable the PORT and hopefully that's it + // If the problem lies with the MCBIST, it'll just have to loop + FAPI_ASSERT(TT::STAT_READ_MISCOMPARE != i_type, + fapi2::MSS_NIMBUS_CCS_READ_MISCOMPARE() + .set_MCBIST_TARGET(i_target) + .set_FAIL_TYPE(i_type) + .set_MCA_TARGET(i_port), + "%s CCS FAIL Read Miscompare", mss::c_str(i_port)); + + // This error is likely due to a bad CCS engine/ MCBIST + FAPI_ASSERT(TT::STAT_UE_SUE != i_type, + fapi2::MSS_NIMBUS_CCS_UE_SUE() + .set_FAIL_TYPE(i_type) + .set_MCBIST_TARGET(i_target), + "%s CCS FAIL UE or SUE Error", mss::c_str(i_target)); + + FAPI_ASSERT(TT::STAT_CAL_TIMEOUT != i_type, + fapi2::MSS_NIMBUS_CCS_CAL_TIMEOUT() + .set_FAIL_TYPE(i_type) + .set_MCBIST_TARGET(i_target) + .set_MCA_TARGET(i_port), + "%s CCS FAIL Calibration Operation Time Out", mss::c_str(i_port)); + + // Problem with the CCS engine + FAPI_ASSERT(TT::STAT_HUNG != i_type, + fapi2::MSS_NIMBUS_CCS_HUNG().set_MCBIST_TARGET(i_target), + "%s CCS appears hung", mss::c_str(i_target)); +fapi_try_exit: + // Due to the PRD update, we need to check for FIR's + // If any FIR's have lit up, this CCS fail could have been caused by the FIR + // So, let PRD retrigger this step to see if we can resolve the issue + return mss::check::fir_or_pll_fail<mss::mc_type::NIMBUS>(i_target, fapi2::current_err); +} + +/// +/// @brief Create, initialize an instruction which indicates an initial cal +/// @tparam TT the CCS traits of the chiplet which executes the CCS instruction +/// @param[in] i_rp the rank-pair (rank) to cal +/// @return the initial cal instruction +/// +instruction_t initial_cal_command(const uint64_t i_rp) +{ + using TT = ccsTraits<mss::mc_type::NIMBUS>; + + // An initial cal arr0 looks just like a DES, but we set the initial cal bits + instruction_t l_inst = des_command(); + + // ACT is low - per Centaur spec (Shelton to confirm for Nimbus) BRS + l_inst.arr0.template clearBit<TT::ARR0_DDR_ACTN>(); + + l_inst.arr0.template insertFromRight<TT::ARR0_DDR_CAL_TYPE, TT::ARR0_DDR_CAL_TYPE_LEN>(0b1100); + l_inst.arr1.template setBit<TT::ARR1_DDR_CALIBRATION_ENABLE>(); + +#ifdef USE_LOTS_OF_IDLES + // Idles is 0xFFFF - per Centaur spec (Shelton to confirm for Nimbus) BRS + l_inst.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(0xFFFF); +#else + l_inst.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(0x0); +#endif + + // The rank we're calibrating is enacoded - it's an int. So rank 3 is 0011 not 0001 + l_inst.arr1.template insertFromRight<TT::ARR1_DDR_CAL_RANK, TT::ARR1_DDR_CAL_RANK_LEN>(i_rp); + + return l_inst; +} + +/// +/// @brief Nimbus specialization for modeq_copy_cke_to_spare_cke +/// @param[in] fapi2::Target<TARGET_TYPE_MCBIST>& the target to effect +/// @param[in,out] the buffer representing the mode register +/// @param[in] mss::states - mss::ON iff Copy CKE signals to CKE Spare on both ports +/// @note no-op for p9n +/// +template<> +void copy_cke_to_spare_cke<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>&, + fapi2::buffer<uint64_t>&, states ) +{ + return; +} + +/// +/// @brief Updates the initial delays based upon the total delays passed in - Nimbus specialization +/// @param[in] i_target the target type on which to operate +/// @param[in] i_delay the calculated delays from CCS +/// @param[in,out] io_program the program for which to update the delays +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode update_initial_delays<fapi2::TARGET_TYPE_MCBIST, mss::mc_type::NIMBUS> +( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const uint64_t i_delay, + ccs::program& io_program) +{ + // Check our program for any delays. If there isn't a iv_initial_delay configured, then + // we use the delay we just summed from the instructions. + if (io_program.iv_poll.iv_initial_delay == 0) + { + io_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, i_delay); + } + + if (io_program.iv_poll.iv_initial_sim_delay == 0) + { + io_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(i_delay); + } + + return fapi2::FAPI2_RC_SUCCESS; +} + +} // namespace ccs +} // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.H index 1154694e9..ec0a73dc7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/utils/dump_regs.H $ */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_nimbus.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,31 +24,35 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file dump_regs.H -/// @brief Dump registers +/// @file ccs_nimbus.C +/// @brief Run and manage the CCS engine /// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> // *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 -// *HWP Consumed by: HB:FSP +// *HWP Consumed by: FSP:HB -#ifndef _MSS_DUMP_REGS_H_ -#define _MSS_DUMP_REGS_H_ +#ifndef _MSS_CCS_NIMBUS_H_ +#define _MSS_CCS_NIMBUS_H_ #include <fapi2.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { +namespace ccs +{ /// -/// @brief Dump the registers of a target -/// @tparam T, the fapi2::TargetType -/// @param[in] i_target the target in question -/// @return fapi2::FAPI2_RC_SUCCESS if ok +/// @brief Create, initialize an instruction which indicates an initial cal +/// @param[in] i_rp the rank-pair (rank) to cal +/// @return the initial cal instruction /// -template< fapi2::TargetType T > -fapi2::ReturnCode dump_regs( const fapi2::Target<T>& i_target ); +instruction_t initial_cal_command(const uint64_t i_rp); + +} // namespace ccs +} // namespace mss -} #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H new file mode 100644 index 000000000..c3b93cd5d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H @@ -0,0 +1,274 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ccs/ccs_traits_nimbus.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file ccs_traits_nimbus.H +/// @brief Run and manage the CCS engine +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_CCS_TRAITS_NIMBUS_H_ +#define _MSS_CCS_TRAITS_NIMBUS_H_ + +#include <fapi2.H> +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <lib/shared/mss_const.H> +#include <lib/mss_attribute_accessors.H> +#include <generic/memory/lib/ccs/ccs_traits.H> + +/// +/// @class ccsTraits +/// @brief Nimbus CCS Engine traits +/// +template<> +class ccsTraits<mss::mc_type::NIMBUS> +{ + public: + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MCA; + static constexpr uint64_t MODEQ_REG = MCBIST_CCS_MODEQ; + static constexpr uint64_t MCB_CNTL_REG = MCBIST_MCB_CNTLQ; + static constexpr uint64_t CNTLQ_REG = MCBIST_CCS_CNTLQ; + static constexpr uint64_t STATQ_REG = MCBIST_CCS_STATQ; + + static constexpr uint64_t PORTS_PER_MC_TARGET = mss::PORTS_PER_MCBIST; + static constexpr uint64_t CCS_MAX_DIMM_PER_PORT = mss::MAX_DIMM_PER_PORT; + static constexpr uint64_t CCS_MAX_MRANK_PER_PORT = mss::MAX_MRANK_PER_PORT; + static constexpr uint64_t CCS_MAX_RANK_PER_DIMM = mss::MAX_RANK_PER_DIMM; + static constexpr uint64_t CCS_MAX_RANKS_DIMM1 = mss::MAX_RANKS_DIMM1; + + static constexpr uint64_t NTTM_READ_DELAY = 0x40; + static constexpr uint64_t NTTM_MODE_FORCE_READ = 33; + + + // Command Pass Disable Delay Time for Nimbus + static constexpr uint64_t TIMING_TCPDED = 4; + + enum + { + // Non address values that are needed for helper functions + + // ODT values used for beautification + // Attribute locations + ATTR_ODT_DIMM0_R0 = 0, + ATTR_ODT_DIMM0_R1 = 1, + ATTR_ODT_DIMM1_R0 = 4, + ATTR_ODT_DIMM1_R1 = 5, + + // Right justified output - makes it so we can use insertFromRight + CCS_ODT_DIMM0_R0 = 4, + CCS_ODT_DIMM0_R1 = 5, + CCS_ODT_DIMM1_R0 = 6, + CCS_ODT_DIMM1_R1 = 7, + + // Default ODT cycle length is 5 - one for the preamble and 4 for the data + DEFAULT_ODT_CYCLE_LEN = 5, + + // CCS MODEQ + STOP_ON_ERR = MCBIST_CCS_MODEQ_STOP_ON_ERR, + UE_DISABLE = MCBIST_CCS_MODEQ_UE_DISABLE, + DATA_COMPARE_BURST_SEL = MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL, + DATA_COMPARE_BURST_SEL_LEN = MCBIST_CCS_MODEQ_DATA_COMPARE_BURST_SEL_LEN, + DDR_CAL_TIMEOUT_CNT = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT, + DDR_CAL_TIMEOUT_CNT_LEN = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_LEN, + CFG_PARITY_AFTER_CMD = MCBIST_CCS_MODEQ_CFG_PARITY_AFTER_CMD, + COPY_CKE_TO_SPARE_CKE = MCBIST_CCS_MODEQ_COPY_CKE_TO_SPARE_CKE, + DISABLE_ECC_ARRAY_CHK = MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CHK, + DISABLE_ECC_ARRAY_CORRECTION = MCBIST_CCS_MODEQ_DISABLE_ECC_ARRAY_CORRECTION, + CFG_DGEN_FIXED_MODE = MCBIST_CCS_MODEQ_CFG_DGEN_FIXED_MODE, + DDR_CAL_TIMEOUT_CNT_MULT = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT, + DDR_CAL_TIMEOUT_CNT_MULT_LEN = MCBIST_CCS_MODEQ_DDR_CAL_TIMEOUT_CNT_MULT_LEN, + IDLE_PAT_ADDRESS_0_13 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13, + IDLE_PAT_ADDRESS_0_13_LEN = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_0_13_LEN, + IDLE_PAT_ADDRESS_17 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_17, + IDLE_PAT_BANK_GROUP_1 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_1, + IDLE_PAT_BANK_0_1 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1, + IDLE_PAT_BANK_0_1_LEN = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_0_1_LEN, + IDLE_PAT_BANK_GROUP_0 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_GROUP_0, + IDLE_PAT_ACTN = MCBIST_CCS_MODEQ_IDLE_PAT_ACTN, + IDLE_PAT_ADDRESS_16 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_16, + IDLE_PAT_ADDRESS_15 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_15, + IDLE_PAT_ADDRESS_14 = MCBIST_CCS_MODEQ_IDLE_PAT_ADDRESS_14, + NTTM_MODE = MCBIST_CCS_MODEQ_NTTM_MODE, + NTTM_RW_DATA_DLY = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY, + NTTM_RW_DATA_DLY_LEN = MCBIST_CCS_MODEQ_NTTM_RW_DATA_DLY_LEN, + IDLE_PAT_BANK_2 = MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2, + DDR_PARITY_ENABLE = MCBIST_CCS_MODEQ_DDR_PARITY_ENABLE, + IDLE_PAT_PARITY = MCBIST_CCS_MODEQ_IDLE_PAT_PARITY, + + // MCB_CNTRL + MCB_CNTL_PORT_SEL = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL, + MCB_CNTL_PORT_SEL_LEN = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN, + + // CCS CNTL + CCS_START = MCBIST_CCS_CNTLQ_START, + CCS_STOP = MCBIST_CCS_CNTLQ_STOP, + + // CCS STATQ + CCS_IN_PROGRESS = MCBIST_CCS_STATQ_IP, + + // ARR0 + ARR0_DDR_ADDRESS_0_13 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, + ARR0_DDR_ADDRESS_0_13_LEN = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13_LEN, + ARR0_DDR_ADDRESS_0_9 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_0_13, // Useful for rd/wr cmds + ARR0_DDR_ADDRESS_0_9_LEN = 10, // CA bits are 9:0, total length of 10 + ARR0_DDR_ADDRESS_10 = 10, // ADR10 is the 10th bit from the left in Nimbus ARR0 + ARR0_DDR_ADDRESS_17 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_17, + ARR0_DDR_BANK_GROUP_1 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_1, + ARR0_DDR_RESETN = MCBIST_CCS_INST_ARR0_00_DDR_RESETN, + ARR0_DDR_BANK_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1, + ARR0_DDR_BANK_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1_LEN, + ARR0_DDR_BANK_GROUP_0 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0, + ARR0_DDR_ACTN = MCBIST_CCS_INST_ARR0_00_DDR_ACTN, + ARR0_DDR_ADDRESS_16 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16, + ARR0_DDR_ADDRESS_15 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15, + ARR0_DDR_ADDRESS_14 = MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14, + ARR0_DDR_CKE = MCBIST_CCS_INST_ARR0_00_DDR_CKE, + ARR0_DDR_CKE_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN, + ARR0_DDR_CSN_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1, + ARR0_DDR_CSN_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1_LEN, + ARR0_DDR_CID_0_1 = MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1, + ARR0_DDR_CID_0_1_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CID_0_1_LEN, + ARR0_DDR_CSN_2_3 = MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3, + ARR0_DDR_CSN_2_3_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3_LEN, + ARR0_DDR_CID_2 = MCBIST_CCS_INST_ARR0_00_DDR_CID_2, + ARR0_DDR_ODT = MCBIST_CCS_INST_ARR0_00_DDR_ODT, + ARR0_DDR_ODT_LEN = MCBIST_CCS_INST_ARR0_00_DDR_ODT_LEN, + ARR0_DDR_CAL_TYPE = MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE, + ARR0_DDR_CAL_TYPE_LEN = MCBIST_CCS_INST_ARR0_00_DDR_CAL_TYPE_LEN, + ARR0_DDR_PARITY = MCBIST_CCS_INST_ARR0_00_DDR_PARITY, + ARR0_DDR_BANK_2 = MCBIST_CCS_INST_ARR0_00_DDR_BANK_2, + ARR0_LOOP_BREAK_MODE = MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE, + ARR0_LOOP_BREAK_MODE_LEN = MCBIST_CCS_INST_ARR0_00_LOOP_BREAK_MODE_LEN, + + // ARR1 + ARR1_IDLES = MCBIST_CCS_INST_ARR1_00_IDLES, + ARR1_IDLES_LEN = MCBIST_CCS_INST_ARR1_00_IDLES_LEN, + ARR1_REPEAT_CMD_CNT = MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, + ARR1_REPEAT_CMD_CNT_LEN = MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT_LEN, + ARR1_READ_OR_WRITE_DATA = MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA, + ARR1_READ_OR_WRITE_DATA_LEN = MCBIST_CCS_INST_ARR1_00_READ_OR_WRITE_DATA_LEN, + ARR1_READ_COMPARE_REQUIRED = MCBIST_CCS_INST_ARR1_00_READ_COMPARE_REQUIRED, + ARR1_DDR_CAL_RANK = MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK, + ARR1_DDR_CAL_RANK_LEN = MCBIST_CCS_INST_ARR1_00_DDR_CAL_RANK_LEN, + ARR1_DDR_CALIBRATION_ENABLE = MCBIST_CCS_INST_ARR1_00_DDR_CALIBRATION_ENABLE, + ARR1_END = MCBIST_CCS_INST_ARR1_00_END, + ARR1_GOTO_CMD = MCBIST_CCS_INST_ARR1_00_GOTO_CMD, + ARR1_GOTO_CMD_LEN = MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN, + + // CCS array constants + CCS_ARRAY_LEN = 32, + CCS_ARR0_START = MCBIST_CCS_INST_ARR0_00, + CCS_ARR1_START = MCBIST_CCS_INST_ARR1_00, + }; + + /// + /// @brief Enums for CCS return codes + /// + enum + { + // Success is defined as done-bit set, no others. + STAT_QUERY_SUCCESS = 0x4000000000000000, + + // Bit positions 3:5 + STAT_ERR_MASK = 0x1C00000000000000, + STAT_READ_MISCOMPARE = 0x1000000000000000, + STAT_UE_SUE = 0x0800000000000000, + STAT_CAL_TIMEOUT = 0x0400000000000000, + + // If the fail type isn't one of these, we're hung + STAT_HUNG = 0x0ull, + }; + + + // CSN Regular Settings + static constexpr std::pair<uint64_t, uint64_t> CS_N[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L, CS1 H, CID0-> L => Rank 0 + { 0b01, 0b00 }, + + // CS0 L, CS1 H, CID0-> H => Rank 1 + { 0b01, 0b11 }, + + // CS0 H, CS1 L, CID0-> L => Rank 2 + { 0b10, 0b00 }, + + // CS0 H, CS1 L, CID0-> H => Rank 3 + { 0b10, 0b11 }, + }; + + + // CSN Setup for Dual Direct Mode + // For DIMM0 .first is the CSN_0_1 setting, .second is the CSN_2_3 setting. + // For DIMM1 .first is the CSN_2_3 setting, .second is the CSN_0_1 setting. + static constexpr std::pair<uint64_t, uint64_t> CS_ND[mss::MAX_RANK_PER_DIMM] = + { + // CS0 L CS1 H => CS2 => H CS3 => H Rank 0 + { 0b01, 0b11 }, + + // CS0 H CS1 L => CS2 => H CS3 => H Rank 1 + { 0b10, 0b11 }, + + // CS0 H CS1 H => CS2 => L CS3 => H Rank 2 + { 0b11, 0b01 }, + + // CS0 H CS1 H => CS2 => H CS3 => L Rank 3 + { 0b11, 0b10 }, + }; + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return SUCCESS iff the code executes successfully + /// + static fapi2::ReturnCode get_rank_config_attr(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint8_t (&o_array)[2]) + { + return mss::eff_num_master_ranks_per_dimm(i_target, o_array); + } + + /// + /// @brief Gets the attribute for checking our rank configuration + /// @param[in] i_target the port target on which to operate + /// @param[out] o_ranks the rank data + /// @return The fully setup nimbus error + /// + static fapi2::MSS_CCS_HUNG_TRYING_TO_STOP setup_trying_to_stop_err(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target) + { + return fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target); + } + + // Lab values + static constexpr uint64_t LAB_MRS_CMD = 0x000008F000000000; +}; + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C index ae62be201..1b42026a4 100755 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,10 +34,15 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> - #include <mss.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/shared/mss_const.H> + #include <lib/dimm/bcw_load.H> #include <lib/dimm/bcw_load_ddr4.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -58,7 +63,7 @@ template<> fapi2::ReturnCode bcw_load<TARGET_TYPE_MCBIST>( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector @@ -91,7 +96,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -121,7 +126,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform bcw_load for %s [expecting lrdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( bcw_load_ddr4(i_target, io_inst), "Failed bcw load for lrdimm %s", mss::c_str(i_target)); @@ -138,7 +143,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_bcw_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("Skipping BCW loading for %s since this is valid only for LRDIMMs", mss::c_str(i_target)); return fapi2::FAPI2_RC_SUCCESS; @@ -152,7 +157,7 @@ fapi2::ReturnCode perform_bcw_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_ /// template<> fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H index be5f1bfc5..4bdfe0033 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,10 +39,14 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> + namespace mss { @@ -113,7 +117,7 @@ struct perform_bcw_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_bcw_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_bcw_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); // // We know we registered overloads for perform_bcw_load, so we need the entry point to @@ -129,7 +133,7 @@ perform_bcw_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// template<> fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Perform the bcw_load operations (DEFAULT_KIND specialization) @@ -139,7 +143,7 @@ fapi2::ReturnCode perform_bcw_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::T /// template<> fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); // // Boilerplate dispatcher @@ -157,7 +161,7 @@ fapi2::ReturnCode perform_bcw_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_bcw_load_overload<K>::available > inline fapi2::ReturnCode perform_bcw_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -182,7 +186,7 @@ inline fapi2::ReturnCode perform_bcw_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_bcw_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { return perform_bcw_load<DEFAULT_KIND>(i_target, io_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C index 266e7ce56..0712939f3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.C @@ -36,11 +36,13 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/utils/mss_nimbus_conversions.H> #include <lib/eff_config/timing.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/bcw_load_ddr4.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> @@ -48,6 +50,7 @@ #include <lib/workarounds/ccs_workarounds.H> #include <generic/memory/lib/spd/spd_utils.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; @@ -67,10 +70,8 @@ namespace mss /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { - constexpr uint64_t SAFE_DELAY = 2000; // Waiting a safe amount of time as the LRDIMM spec - // doesn't give us an explicit value for this delay FAPI_INF("bcw_load_ddr4 %s", mss::c_str(i_target) ); uint8_t l_sim = 0; @@ -104,21 +105,21 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target { FUNC_SPACE_0, DQ_DRIVER_CW, eff_dimm_ddr4_bc03, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_RTT_CW, eff_dimm_ddr4_bc04, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, MDQ_DRIVER_CW, eff_dimm_ddr4_bc05, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, CMD_SPACE_CW, eff_dimm_ddr4_bc06, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works + { FUNC_SPACE_0, RANK_PRESENCE_CW, eff_dimm_ddr4_bc07, BCW_SAFE_DELAY , CW4_DATA_LEN, cw_info::BCW}, // using tmrd_l2 causes an error - safe delay works { FUNC_SPACE_0, RANK_SELECTION_CW, eff_dimm_ddr4_bc08, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, POWER_SAVING_CW, eff_dimm_ddr4_bc09, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, OPERATING_SPEED, eff_dimm_ddr4_bc0a, l_tDLLK , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, VOLT_AND_SLEW_RATE_CW, eff_dimm_ddr4_bc0b, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, eff_dimm_ddr4_bc0c, mss::tmrd_l2() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, LDQ_OPERATION_CW, eff_dimm_ddr4_bc0d, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, PARITY_CW, eff_dimm_ddr4_bc0e, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, { FUNC_SPACE_0, ERROR_STATUS_CW, eff_dimm_ddr4_bc0f, mss::tmrc() , CW4_DATA_LEN, cw_info::BCW}, // 8-bit BCW's now // Function space 0 - we're already there, so that's nice - { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrc(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, BUFF_CONFIG_CW, eff_dimm_ddr4_f0bc1x, mss::tmrd_l2() , CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_0, LRDIMM_OPERATING_SPEED, eff_dimm_ddr4_f0bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 2 { FUNC_SPACE_2, FUNC_SPACE_SELECT_CW, FUNC_SPACE_2, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -126,8 +127,8 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target // Function space 5 { FUNC_SPACE_5, FUNC_SPACE_SELECT_CW, FUNC_SPACE_5, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, - { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, HOST_VREF_CW, eff_dimm_ddr4_f5bc5x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, + { FUNC_SPACE_5, DRAM_VREF_CW, eff_dimm_ddr4_f5bc6x, BCW_SAFE_DELAY, CW8_DATA_LEN, cw_info::BCW}, // Function space 6 { FUNC_SPACE_6, FUNC_SPACE_SELECT_CW, FUNC_SPACE_6, mss::tmrd(), CW8_DATA_LEN, cw_info::BCW}, @@ -142,7 +143,7 @@ fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target }; // DES first - make sure those CKE go high and stay there - io_inst.push_back(mss::ccs::des_command<TARGET_TYPE_MCBIST>()); + io_inst.push_back(mss::ccs::des_command()); // Issues the CW's FAPI_TRY( control_word_engine(i_target, l_bcw_info, l_sim, io_inst), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H index 7e68d32d0..31ef02983 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/bcw_load_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,9 @@ #include <fapi2.H> #include <vector> -#include <lib/ccs/ccs.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -51,6 +53,6 @@ namespace mss /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode bcw_load_ddr4( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H index ab28d5b82..60b3c077b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/control_word_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,9 +40,10 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -276,7 +277,6 @@ struct cw_data /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -284,12 +284,12 @@ struct cw_data /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) + ccs::instruction_t& o_instruction) { // You're probably asking "Why always turn off CKE's? What is this madness?" // Well, due to a vendor sensitivity, we need to have the CKE's off until we run RC09 at the very end @@ -298,7 +298,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM // Therefore, we want to setup all RCW commands to have CKE's off across both DIMM's // We then manually turn on the CKE's associated with a specific DIMM constexpr bool CKE_OFF = false; - ccs::instruction_t<OT> l_inst = ccs::rcd_command<OT>(i_target, i_sim, CKE_OFF); + ccs::instruction_t l_inst = ccs::rcd_command(i_target, i_sim, CKE_OFF); // Turn on the CKE's for the ranks we're not touching, if it's needed // Note: we only have the whole CKE field, not the per DIMM one by default @@ -359,7 +359,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data control word data to send /// @param[in] i_sim true if in simulation mode @@ -367,14 +366,14 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for this RCW (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const cw_data& i_data, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY(control_word_engine<T>(i_target, i_data, i_sim, i_turn_on_cke, l_inst)); io_inst.push_back(l_inst); @@ -386,7 +385,6 @@ fapi_try_exit: /// @brief Control word engine that sets the CCS instruction /// @tparam T the buffer control word type (4 bit or 8 bit) /// @tparam TT traits type defaults to cwTraits<T> -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_data_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -394,11 +392,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< control_word T, typename TT = cwTraits<T>, fapi2::TargetType OT > +template< control_word T, typename TT = cwTraits<T> > fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const std::vector<cw_data>& i_data_list, const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, + std::vector< ccs::instruction_t >& io_inst, const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_data_list.empty(), @@ -495,7 +493,6 @@ struct cw_info /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info control word data and information about how to send it /// @param[in] i_sim true if in simulation mode @@ -503,12 +500,11 @@ struct cw_info /// @param[out] o_instruction CCS instruction we created /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const cw_info& i_info, - const bool i_sim, - const bool i_turn_on_cke, - ccs::instruction_t<OT>& o_instruction) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const cw_info& i_info, + const bool i_sim, + const bool i_turn_on_cke, + ccs::instruction_t& o_instruction) { // BCW 4-bit if(i_info.iv_is_bcw && i_info.iv_data_len == CW4_DATA_LEN) @@ -548,7 +544,6 @@ fapi_try_exit: /// /// @brief Control word engine that sets the CCS instruction -/// @tparam OT the TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_info_list a vector of control word data to send /// @param[in] i_sim true if in simulation mode @@ -556,12 +551,11 @@ fapi_try_exit: /// @param[in] i_turn_on_cke flag that states whether we want CKE on for all RCWs in the vector (defaulted to true) /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType OT > -fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::vector<cw_info>& i_info_list, - const bool i_sim, - std::vector< ccs::instruction_t<OT> >& io_inst, - const bool i_turn_on_cke = true) +inline fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const std::vector<cw_info>& i_info_list, + const bool i_sim, + std::vector< ccs::instruction_t >& io_inst, + const bool i_turn_on_cke = true) { FAPI_ASSERT( !i_info_list.empty(), fapi2::MSS_EMPTY_VECTOR(). @@ -571,7 +565,7 @@ fapi2::ReturnCode control_word_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIM for (const auto& l_info : i_info_list) { - ccs::instruction_t<OT> l_inst; + ccs::instruction_t l_inst; FAPI_TRY( control_word_engine(i_target, l_info, i_sim, i_turn_on_cke, l_inst) ); io_inst.push_back(l_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H index d2bffc509..8cdb81f55 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/data_buffer_ddr4.H @@ -44,6 +44,9 @@ #include <lib/phy/dp16.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -96,6 +99,9 @@ enum db02_def : size_t HOST_VREF_CW = 0x5, // Func space 5 DRAM_VREF_CW = 0x6, // Func space 5 BUFF_TRAIN_CONFIG_CW = 0x4, // Func space 6 + + // Safe delays for BCW's + BCW_SAFE_DELAY = 2000, }; namespace ddr4 @@ -132,7 +138,7 @@ enum command : size_t /// inline fapi2::ReturnCode function_space_select(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const uint64_t i_func_space, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_ASSERT(i_func_space <= MAX_FUNC_SPACE, fapi2::MSS_LRDIMM_FUNC_SPACE_OUT_OF_RANGE() @@ -243,13 +249,13 @@ fapi_try_exit: template< mss::control_word T > static fapi2::ReturnCode settings_boilerplate(const fapi2::Target< fapi2::TARGET_TYPE_DIMM >& i_target, const cw_data& i_data, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_sim = 0; mss::is_simulation(l_sim); // DES first - make sure those CKE go high and stay there - io_inst.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + io_inst.push_back(mss::ccs::des_command()); FAPI_TRY( function_space_select(i_target, i_data.iv_func_space, io_inst), "%s. Failed to select function space %d", @@ -271,17 +277,15 @@ fapi_try_exit: /// /// @brief Sets data buffer training mode control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_mode buffer training mode /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC0C) setting /// -template< fapi2::TargetType T > inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const training i_mode, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // This doesn't need to be reused so it is left local to this function scope static const std::vector< std::pair<training, uint64_t> > BUFF_TRAINING = @@ -302,7 +306,7 @@ inline fapi2::ReturnCode set_buffer_training( const fapi2::Target<fapi2::TARGET_ uint64_t l_encoding = 0; fapi2::Assert(find_value_from_key(BUFF_TRAINING, i_mode, l_encoding)); - cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_TRAIN_MODE_CW, l_encoding, mss::tmrd_l2()); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -362,17 +366,15 @@ fapi_try_exit: /// /// @brief Sets rank presence control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_num_package_ranks num of package ranks for LRDIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC07) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_rank_presence( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_num_package_ranks, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // Helper function handles error checking uint64_t l_encoding = 0; @@ -391,7 +393,6 @@ fapi_try_exit: /// /// @brief Sets Upper/Lower nibble DRAM interface receive enable training control word /// @tparam T the nibble of in training (upper/lower) -/// @tparam OT TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_rank DIMM0 rank [0:3] or DIMM1 rank [4:7] /// @param[in] i_trained_timing the delay MDQS receive enable timing @@ -399,11 +400,11 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word ( F[3:0]BC2x ) setting /// -template< mss::nibble N, fapi2::TargetType OT> +template< mss::nibble N > fapi2::ReturnCode set_mrep_timing_control( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, const uint64_t i_trained_timing, - std::vector< ccs::instruction_t<OT> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr size_t MAX_DELAY = 63; @@ -430,17 +431,15 @@ fapi_try_exit: /// /// @brief Sets command space control word -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_command command name /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets buffer control word (BC06) setting /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const command i_command, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { constexpr uint64_t MAX_VALID_CMD = 4; @@ -453,9 +452,8 @@ inline fapi2::ReturnCode set_command_space( const fapi2::Target<fapi2::TARGET_TY } // From the DDR4DB02 Spec: BC06 - Command Space Control Word - // After issuing a data buffer command via writes to BC06 waiting for tMRC(16 tCK) - // is required before the next DRAM command or BCW write can be issued. - cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, mss::tmrc()); + // Waiting safe delay here as we've seen issues in the lab where the required tMRD_l2 isn't sufficient + cw_data l_data(FUNC_SPACE_0, CMD_SPACE_CW, i_command, BCW_SAFE_DELAY); FAPI_TRY( settings_boilerplate<BCW_4BIT>(i_target, l_data, io_inst) ); fapi_try_exit: @@ -464,17 +462,15 @@ fapi_try_exit: /// /// @brief Sets per buffer addressibility (PBA) mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target the DIMM target /// @param[in] i_state mss::ON or mss::OFF /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff ok /// @note Sets DA0 setting for buffer control word (F0BC1x) /// -template< fapi2::TargetType T> inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mss::states i_state, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { // PBA position is really bit 0, but we're right justified on our bit ordering here, so it's bit7 constexpr uint64_t PBA_POSITION = 7; @@ -495,7 +491,7 @@ inline fapi2::ReturnCode set_pba_mode( const fapi2::Target<fapi2::TARGET_TYPE_DI FAPI_TRY(mss::eff_dimm_ddr4_f0bc1x(i_target, l_nominal_bc_value)); { - cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrc()); + cw_data l_data(FUNC_SPACE_0, BUFF_CONFIG_CW, l_nominal_bc_value, mss::tmrd_l2()); l_data.iv_data.writeBit<PBA_POSITION>(i_state); FAPI_INF("%s data 0x%02x", mss::c_str(i_target), l_data.iv_data); FAPI_TRY( settings_boilerplate<BCW_8BIT>(i_target, l_data, io_inst) ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C index 7676df23b..be59fe5e0 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.C @@ -36,11 +36,15 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> #include <lib/dimm/rank.H> #include <lib/workarounds/ccs_workarounds.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -62,7 +66,7 @@ namespace ddr4 fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // JEDEC has a 3 step latching process for WR VREF // 1) enter into VREFDQ training mode, with the desired range value is XXXXXX @@ -111,7 +115,7 @@ fapi2::ReturnCode latch_wr_vref_commands_by_rank_pair( const fapi2::Target<fapi2 const auto l_mcbist = find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Warning: l_dimm is not a valid Target and will crash Cronus if used before it gets filled in by mss::rank::get_dimm_target_from_rank fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm; - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; std::vector<uint64_t> l_ranks; // Gets the ranks on which to latch the VREF's @@ -173,7 +177,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Check to make sure our ctor worked ok mrs06_data l_mrs06( i_target, fapi2::current_err ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H index 0cb2a285e..4874000b8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/latch_wr_vref.H @@ -38,10 +38,14 @@ #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/eff_config/timing.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -65,7 +69,7 @@ enum wr_vref_override : uint8_t fapi2::ReturnCode add_latch_wr_vref_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_mrs06, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Add latching commands for WR VREF to the instruction array @@ -121,7 +125,7 @@ fapi2::ReturnCode setup_latch_wr_vref_commands_by_rank( const fapi2::Target<fapi const uint64_t i_rank, const uint8_t i_train_range, const uint8_t i_train_value, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // close namespace DDR4 } // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C index 71deb5bbe..0f0229a71 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs00.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -91,7 +96,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +118,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Map from Write Recovery attribute value to bits in the MRS. @@ -202,7 +207,7 @@ fapi_try_exit: /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -248,7 +253,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_burst_length = 0; @@ -264,10 +269,10 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs00_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs00; -fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs00_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs00_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C index 834ee1ead..cc5896c5c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs01.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,12 @@ #include <fapi2.H> #include <mss.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_DIMM; @@ -86,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -108,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Little table to map Output Driver Imepdance Control. 34Ohm is index 0, @@ -188,7 +193,7 @@ fapi_try_exit: /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -226,7 +231,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_dll_enable = 0; @@ -243,10 +248,10 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs01_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs01; -fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs01_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs01_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C index fe819814b..43f90a0ee 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs02.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -81,7 +81,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -105,7 +105,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CWL_LENGTH = 3; @@ -170,7 +170,7 @@ fapi_try_exit: /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -199,7 +199,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_write_crc = 0; @@ -212,10 +212,10 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs02_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs02; -fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs02_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs02_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C index 06b9eb88c..4c797864b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs03.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -106,7 +106,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -130,7 +130,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { //Some consts for the swizzle action @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -228,7 +228,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_mpr_mode = 0; @@ -246,10 +246,10 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs03_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs03; -fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs03_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs03_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C index b28dae69e..736f338de 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs04.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -105,7 +105,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -127,7 +127,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CS_CMD_LATENCY_LENGTH = 3; @@ -186,7 +186,7 @@ fapi_try_exit: /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -232,7 +232,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { uint8_t l_max_pd_mode = 0; @@ -255,10 +255,10 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs04_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs04; -fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs04_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs04_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C index a4c5be8c6..e9be70395 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs05.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -91,7 +91,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -113,7 +113,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { constexpr uint64_t CA_PARITY_LATENCY_LENGTH = 3; @@ -188,7 +188,7 @@ fapi_try_exit: /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -231,7 +231,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank ths rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_ca_parity_latency_buffer; @@ -252,10 +252,10 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs05_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs05; -fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs05_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs05_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C index bfc1fc885..554271727 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs06.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -79,7 +79,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { // Check to make sure our ctor worked ok @@ -101,7 +101,7 @@ fapi_try_exit: /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) { @@ -159,7 +159,7 @@ fapi_try_exit: /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -188,7 +188,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<TARGET_TYPE_MCBIS /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank) { fapi2::buffer<uint8_t> l_tccd_l_buffer; @@ -202,10 +202,10 @@ fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<TARGET_TYPE_MCBIST>& i_i fapi2::ReturnCode (*mrs06_data::make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank) = &mrs06; -fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode (*mrs06_data::decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank) = &mrs06_decode; } // ns ddr4 diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C index cec455f6a..3ac509b6c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -62,7 +62,7 @@ template< > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { FAPI_TRY( mrs_engine(i_target, i_data, i_rank, i_data.iv_delay, io_inst) ); @@ -138,7 +138,7 @@ namespace ddr4 /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("ddr4::mrs_load %s", mss::c_str(i_target)); @@ -146,28 +146,82 @@ fapi2::ReturnCode mrs_load( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const size_t DOUBLE_TMRD = 2 * mss::tmrd(); const size_t DOUBLE_TMOD = 2 * mss::tmod(i_target); - static const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - // JEDEC ordering of MRS per DDR4 power on sequence - { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, - { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, - { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, - { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, - { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, - { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, - // We need to wait tmod before zqcl, a non-mrs command - { 0, mrs00, mrs00_decode, DOUBLE_TMOD }, - }; - - std::vector< uint64_t > l_ranks; - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // Load MRS - for (const auto& d : MRS_DATA) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 power on sequence + { 3, mrs03, mrs03_decode, DOUBLE_TMRD }, + { 6, mrs06, mrs06_decode, DOUBLE_TMRD }, + { 5, mrs05, mrs05_decode, DOUBLE_TMRD }, + { 4, mrs04, mrs04_decode, DOUBLE_TMRD }, + { 2, mrs02, mrs02_decode, DOUBLE_TMRD }, + { 1, mrs01, mrs01_decode, DOUBLE_TMRD }, + // We need to wait tmod before zqcl, a non-mrs command + // Adding Per Glancy's request, to ensure DLL locking time + { 0, mrs00, mrs00_decode, DOUBLE_TMOD + tDLLK }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) + { + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst) +{ + FAPI_INF("ddr4::mrs_load_nvdimm %s", mss::c_str(i_target)); + + // tDLLK to wait for DLL Reset + uint64_t tDLLK = 0; + FAPI_TRY( mss::tdllk(i_target, tDLLK) ); + { - for (const auto& r : l_ranks) + const std::vector< mrs_data<TARGET_TYPE_MCBIST> > MRS_DATA = + { + // JEDEC ordering of MRS per DDR4 NVDIMM restore sequence + // Need to perform DLL off to on procedure (mrs01&mrs00) + // before all the other MRS's + { 1, mrs01, mrs01_decode, mss::tmrd() }, + { 0, mrs00, mrs00_decode, mss::tmod(i_target) + tDLLK }, + { 3, mrs03, mrs03_decode, mss::tmrd() }, + { 6, mrs06, mrs06_decode, mss::tmrd() }, + { 5, mrs05, mrs05_decode, mss::tmrd() }, + { 4, mrs04, mrs04_decode, mss::tmrd() }, + { 2, mrs02, mrs02_decode, mss::tmrd() }, + }; + + std::vector< uint64_t > l_ranks; + FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); + + // Load MRS + for (const auto& d : MRS_DATA) { - FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + for (const auto& r : l_ranks) + { + FAPI_TRY( mrs_engine(i_target, d, r, io_inst) ); + } } } @@ -234,7 +288,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_override(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -274,7 +328,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; @@ -302,7 +356,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_rtt_nom_override_disable = 0; uint8_t l_rtt_nom_value[MAX_RANK_PER_DIMM] = {0}; @@ -335,7 +389,7 @@ fapi_try_exit: template<> fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Get original RTT_WR value uint8_t l_rtt_wr_value[MAX_RANK_PER_DIMM] = {0}; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H index bd8277daa..5e6aa5c35 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/mrs_load_ddr4.H @@ -41,6 +41,9 @@ #include <generic/memory/lib/utils/c_str.H> #include <lib/dimm/mrs_load.H> #include <lib/eff_config/timing.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -99,13 +102,11 @@ enum rtt_nom_settings /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction - implementation -/// @tparam T typename of the ccs::instruction_t /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note written this way so this is easier to test /// -template<fapi2::TargetType T> -void address_mirror_impl(ccs::instruction_t<T>& io_inst) +inline void address_mirror_impl(ccs::instruction_t& io_inst) { // Nothing fancy here, just mirror the bits we're told to mirror in Table 14 — Address Mirroring and Inversion mss::template swap<A3, A4>(io_inst.arr0); @@ -118,17 +119,15 @@ void address_mirror_impl(ccs::instruction_t<T>& io_inst) /// /// @brief Mirror (front to back) the ADR bits of a CCS instruction -/// @tparam T typename of the ccs::instruction_t /// @param[in] i_target target to use to get mirroring attribute /// @param[in] i_rank the rank in question /// @param[in, out] io_inst reference to a CCS instruction to be mirrored /// @return FAPI2_RC_SUCESS iff ok /// @note assumes the input is from an even number rank /// -template<fapi2::TargetType T> -fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - ccs::instruction_t<T>& io_inst) +inline fapi2::ReturnCode address_mirror(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + ccs::instruction_t& io_inst) { // We only mirror if the mirroring attribute is set. uint8_t l_mirror = 0; @@ -147,19 +146,17 @@ fapi_try_exit: /// /// @brief Invert (side to side) the ADR bits of a CCS instruction -/// @tparam T the target type of the ccs instruction /// @param[in] i_target the DIMM target of the ccs command /// @param[in] i_inst const reference to a CCS instruction. /// @param[in] l_is_a17 Boolean for whether A17 bit is enabled or not /// @return ccs instruction with the ADR bits inverted (side-to-side) /// -template<fapi2::TargetType T> -ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const ccs::instruction_t<T>& i_inst, - const bool i_is_a17 = false) +inline ccs::instruction_t address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const ccs::instruction_t& i_inst, + const bool i_is_a17 = false) { // Copy the input as the output doesn't all change. - ccs::instruction_t<T> i_out(i_inst); + ccs::instruction_t i_out(i_inst); // Nothing fancy here, just negate the bits we're told to negate in Table 14 — Address Mirroring and Inversion mss::template negate<A3>(i_out.arr0); @@ -189,7 +186,6 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// /// @brief Helper function to make a CCS instruction for an MRS -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -197,11 +193,11 @@ ccs::instruction_t<T> address_invert(const fapi2::Target<fapi2::TARGET_TYPE_DIMM /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - ccs::instruction_t<T>& io_inst ) + ccs::instruction_t& io_inst ) { FAPI_TRY( D::make_ccs_instruction(i_target, i_data, io_inst, i_rank), "Failed making a CCS instruction for templated MRS data. MR%d rank %d on %s", @@ -219,11 +215,10 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS if and only if ok /// template< > -inline fapi2::ReturnCode make_ccs_helper( - const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, - const uint64_t i_rank, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst ) +inline fapi2::ReturnCode make_ccs_helper( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, + const uint64_t i_rank, + ccs::instruction_t& io_inst ) { FAPI_TRY( i_data.iv_func(i_target, io_inst, i_rank), "Failed making a CCS instruction for mrs_data<TARGET_TYPE_MCBIST> specialization. MR%d rank %d on %s", @@ -235,17 +230,16 @@ fapi_try_exit: /// /// @brief Helper function to decode MRS and trace CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_data the completed MRS data to send /// @param[in] i_rank the rank to send to /// @param[in] i_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > static inline fapi2::ReturnCode decode_helper(const D& i_data, const uint64_t i_rank, - const ccs::instruction_t<T>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( D::decode(i_inst, i_rank), @@ -278,7 +272,7 @@ fapi2::ReturnCode is_a17_needed(const fapi2::Target<T>& i_target, template< > inline fapi2::ReturnCode decode_helper(const mrs_data<fapi2::TARGET_TYPE_MCBIST>& i_data, const uint64_t i_rank, - const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst ) + const ccs::instruction_t& i_inst ) { // Dump out the 'decoded' MRS and trace the CCS instructions. FAPI_TRY( i_data.iv_dumper(i_inst, i_rank), @@ -292,7 +286,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -301,15 +294,15 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, const uint64_t i_delay_in_cycles, - std::vector< ccs::instruction_t<T> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst_a_side = ccs::mrs_command<T>(i_rank, i_data.iv_mrs); - ccs::instruction_t<T> l_inst_b_side; + ccs::instruction_t l_inst_a_side = ccs::mrs_command(i_rank, i_data.iv_mrs); + ccs::instruction_t l_inst_b_side; bool l_is_a17 = false; // Thou shalt send 2 MRS, one for the a-side and the other inverted for the b-side. @@ -355,7 +348,6 @@ fapi_try_exit: /// /// @brief Sets up MRS CCS instructions -/// @tparam T TargetType of the CCS instruction /// @tparam D the mrs data structure to send out /// @param[in] i_target a fapi2::Target DIMM /// @param[in] i_data the completed MRS data to send @@ -363,11 +355,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, typename D > +template< typename D > fapi2::ReturnCode mrs_engine( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const D& i_data, const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); namespace ddr4 { @@ -395,7 +387,7 @@ class mrs06_data; /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -406,7 +398,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -417,7 +409,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs03 @@ -427,7 +419,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs04 @@ -437,7 +429,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs05 @@ -447,7 +439,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// /// @brief Configure the ARR0 of the CCS isntruction for mrs06 @@ -457,7 +449,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @return FAPI2_RC_SUCCESS iff OK /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -478,7 +470,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -491,7 +483,7 @@ fapi2::ReturnCode mrs00(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -504,7 +496,7 @@ fapi2::ReturnCode mrs01(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -517,7 +509,7 @@ fapi2::ReturnCode mrs02(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -530,7 +522,7 @@ fapi2::ReturnCode mrs03(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -543,7 +535,7 @@ fapi2::ReturnCode mrs04(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// @@ -556,7 +548,7 @@ fapi2::ReturnCode mrs05(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); /// }@ @@ -579,7 +571,7 @@ fapi2::ReturnCode mrs06(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// @param[out] o_cas_latency the cas latency /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_burst_length, uint8_t& o_read_burst_type, @@ -595,7 +587,7 @@ fapi2::ReturnCode mrs00_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs00_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -611,7 +603,7 @@ fapi2::ReturnCode mrs00_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_nom the rtt_nom setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_dll_enable, uint8_t& o_wrl_enable, @@ -628,7 +620,7 @@ fapi2::ReturnCode mrs01_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs01_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -641,7 +633,7 @@ fapi2::ReturnCode mrs01_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_wr the rtt_wr setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_write_crc, fapi2::buffer<uint8_t>& o_lpasr, @@ -655,7 +647,7 @@ fapi2::ReturnCode mrs02_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs02_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -672,7 +664,7 @@ fapi2::ReturnCode mrs02_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_read_fromat the mpr read format setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_mpr_mode, uint8_t& o_geardown, @@ -690,7 +682,7 @@ fapi2::ReturnCode mrs03_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs03_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -709,7 +701,7 @@ fapi2::ReturnCode mrs03_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_cs_cmd_latency_buffer the cs to cmd/addr latency mode setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_max_pd_mode, uint8_t& o_temp_refresh_range, @@ -730,7 +722,7 @@ fapi2::ReturnCode mrs04_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs04_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -748,7 +740,7 @@ fapi2::ReturnCode mrs04_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_rtt_park_buffer the rtt_park setting /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_crc_error_clear, uint8_t& o_ca_parity_error_status, @@ -767,7 +759,7 @@ fapi2::ReturnCode mrs05_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs05_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -780,7 +772,7 @@ fapi2::ReturnCode mrs05_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIS /// @param[out] o_vrefdq_train_value_buffer the vrefdq training value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t& i_inst, const uint64_t i_rank, uint8_t& o_vrefdq_train_range, uint8_t& o_vrefdq_train_enable, @@ -794,7 +786,7 @@ fapi2::ReturnCode mrs06_decode_helper(const ccs::instruction_t<fapi2::TARGET_TYP /// @param[in] i_rank the rank in question /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode mrs06_decode(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, +fapi2::ReturnCode mrs06_decode(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -818,10 +810,10 @@ struct mrs00_data // dynaimc polymorphism and I avoid that where possible. static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs00_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -909,10 +901,10 @@ struct mrs01_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs01_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1011,10 +1003,10 @@ struct mrs02_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs02_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1091,10 +1083,10 @@ struct mrs03_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs03_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1196,10 +1188,10 @@ struct mrs04_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs04_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1322,10 +1314,10 @@ struct mrs05_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs05_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1436,10 +1428,10 @@ struct mrs06_data // Helper function needed by the lab tooling to find our instruction maker and our dumper static fapi2::ReturnCode (*make_ccs_instruction)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const mrs06_data& i_data, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst, + ccs::instruction_t& io_inst, const uint64_t i_rank); - static fapi2::ReturnCode (*decode)(const ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& i_inst, + static fapi2::ReturnCode (*decode)(const ccs::instruction_t& i_inst, const uint64_t i_rank); /// @@ -1516,7 +1508,16 @@ struct mrs06_data /// @return FAPI2_RC_SUCCESS if and only if ok /// fapi2::ReturnCode mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); + +/// +/// @brief Perform the mrs_load DDR4 operations for nvdimm restore - TARGET_TYPE_DIMM specialization +/// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> +/// @param[in] io_inst a vector of CCS instructions we should add to +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode mrs_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Sets WR LVL mode @@ -1720,18 +1721,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set WR LVL Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for WR LVL mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const mss::states i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode wr_lvl(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const mss::states i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Spec states we need to use tmod for our delay, so we do const uint64_t l_delay = mss::tmod(i_target); @@ -1754,18 +1753,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1789,7 +1786,6 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set MPR Mode -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode setting for MPR mode /// @param[in] i_rd_format MPR read format @@ -1797,12 +1793,11 @@ fapi_try_exit: /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_mode, - const uint8_t i_rd_format, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_mode, + const uint8_t i_rd_format, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // From DDR4 spec section 4.10.3 MPR Reads: // tMRD and tMOD must be satisfied after enabling/disabling MPR mode @@ -1830,18 +1825,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_NOM value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_NOM /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_nom_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1864,18 +1857,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set RTT_WR value -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_value values to set to RTT_WR /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_value[MAX_RANK_PER_DIMM], - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode rtt_wr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_value[MAX_RANK_PER_DIMM], + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // tMRD (clock cycles) must be satisfied after an MRS command constexpr uint64_t l_delay = mss::tmrd(); @@ -1898,23 +1889,21 @@ fapi_try_exit: /// /// @brief Makes CCS instruction for an MPR read -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_mode MPR location /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_mpr_loc, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_mpr_loc, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { // Right now we only have support for RD and RDA // Unclear if we want the API select the type of read command right now // Note the auto precharge is ignored with MPR mode on so we just do a read cmd - ccs::instruction_t<T> l_inst = ccs::rd_command<T> (i_rank, i_mpr_loc); + ccs::instruction_t l_inst = ccs::rd_command (i_rank, i_mpr_loc); // In MPR Mode: // Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between read commands @@ -1948,18 +1937,16 @@ fapi_try_exit: /// /// @brief Makes CCS instruction to set precharge all command -/// @tparam T TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank DIMM rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - std::vector< ccs::instruction_t<T> >& io_inst ) +inline fapi2::ReturnCode precharge_all( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + std::vector< ccs::instruction_t >& io_inst ) { - ccs::instruction_t<T> l_inst = ccs::precharge_all_command<T> (i_rank); + ccs::instruction_t l_inst = ccs::precharge_all_command (i_rank); // From the DDR4 Spec tRP is the precharge command period uint8_t l_delay = 0; @@ -1995,58 +1982,54 @@ fapi2::ReturnCode rtt_wr_to_rtt_nom_helper(const fapi2::Target<T>& i_target, /// /// @brief Executes CCS instructions to set RTT_WR value into RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_override(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to disable RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_disable(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_NOM /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_nom_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Executes CCS instructions to restore original value to RTT_WR /// @tparam T TargetType of the DIMM -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target a DIMM target /// @param[in] i_rank selected rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS if and only if ok /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode rtt_wr_restore(const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // ddr4 } // mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C index 869e18f25..8c19b99f9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,23 +33,25 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <vector> +#include <lib/shared/mss_const.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/nvdimm_utils.H> #include <lib/mc/mc.H> -#include <lib/ccs/ccs.H> #include <lib/dimm/rank.H> #include <lib/mss_attribute_accessors.H> +#include <lib/mcbist/mcbist.H> +#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/poll.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <lib/mcbist/address.H> #include <lib/mcbist/memdiags.H> -#include <lib/mcbist/mcbist.H> #include <lib/mcbist/settings.H> -#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/pos.H> #include <lib/mc/port.H> #include <lib/phy/dp16.H> @@ -82,7 +84,7 @@ fapi2::ReturnCode get_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_TYPE mss::states& o_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -105,7 +107,7 @@ fapi2::ReturnCode change_maint_addr_mode_en( const fapi2::Target<fapi2::TARGET_T const mss::states i_state ) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; + typedef mcbistTraits<> TT; fapi2::buffer<uint64_t> l_data; FAPI_TRY( mss::getScom(l_mcbist, TT::MCBAGRAQ_REG, l_data), @@ -213,10 +215,10 @@ fapi2::ReturnCode self_refresh_exit_helper( const fapi2::Target<fapi2::TARGET_TY mss::mcbist::address l_start = 0, l_end = 0; mss::mcbist::end_boundary l_end_boundary = mss::mcbist::end_boundary::STOP_AFTER_SLAVE_RANK; l_start.set_port(l_port); - mss::mcbist::stop_conditions l_stop_conditions; + mss::mcbist::stop_conditions<> l_stop_conditions; // Read with targeted scrub - FAPI_TRY ( mss::memdiags::targeted_scrub(l_mcbist, + FAPI_TRY ( mss::memdiags::targeted_scrub<mss::mc_type::NIMBUS>(l_mcbist, l_stop_conditions, l_start, l_end, @@ -264,10 +266,14 @@ template<> fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data; + const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Entry time to 0 for immediate entry constexpr uint64_t l_str_entry_time = 0; + // Stop mcbist (scrub) in case of MPIPL. It will get restarted in the later istep + FAPI_TRY(mss::mcbist::start_stop(l_mcbist, mss::states::STOP)); + // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0, // and disable minimum domain reduction (allow immediate entry of STR) FAPI_TRY(mss::mc::read_mbarpc0(i_target, l_mbarpc0_data)); @@ -322,49 +328,6 @@ fapi_try_exit: } /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) -{ - FAPI_INF("rc09_disable_powerdown %s", mss::c_str(i_target)); - - constexpr uint8_t POWER_DOWN_BIT = 4; - constexpr bool l_sim = false; - constexpr uint8_t FS0 = 0; // Function space 0 - constexpr uint64_t CKE_HIGH = mss::ON; - fapi2::buffer<uint8_t> l_rc09_cw = 0; - std::vector<uint64_t> l_ranks; - - FAPI_TRY(mss::eff_dimm_ddr4_rc09(i_target, l_rc09_cw)); - - // Clear power down enable bit. - l_rc09_cw.clearBit<POWER_DOWN_BIT>(); - - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // DES to ensure we exit powerdown properly - FAPI_DBG("deselect for %s", mss::c_str(i_target)); - io_inst.push_back( ccs::des_command<TARGET_TYPE_MCBIST>() ); - - static const cw_data l_rc09_4bit_data( FS0, 9, l_rc09_cw, mss::tmrd() ); - - // Load RC09 - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), - "Failed to load 4-bit RC09 control word for %s", - mss::c_str(i_target)); - - // Hold the CKE high - mss::ccs::workarounds::hold_cke_high(io_inst); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -373,11 +336,11 @@ fapi_try_exit: /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("rcd_load_nvdimm %s", mss::c_str(i_target)); - constexpr uint64_t CKE_LOW = mss::OFF; + constexpr uint64_t CKE_HIGH = mss::ON; constexpr bool l_sim = false; // Per DDR4RCD02, tSTAB is us. We want this in cycles for the CCS. @@ -425,17 +388,19 @@ fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<TARGET_TYPE_DIMM>& i_targ }; // Load 4-bit data - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_LOW), + // Keeping the CKE high as this will be done not in powerdown/STR mode. Not affected for + // the RCD supplier on nvdimm + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rcd_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit control words for %s", mss::c_str(i_target)); // Load 8-bit data - FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_8BIT>(i_target, l_rcd_8bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 8-bit control words for %s", mss::c_str(i_target)); // Load RC09 with CKE_LOW - FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_LOW), + FAPI_TRY( control_word_engine<RCW_4BIT>(i_target, l_rc09_4bit_data, l_sim, io_inst, CKE_HIGH), "Failed to load 4-bit RC09 control word for %s", mss::c_str(i_target)); @@ -456,34 +421,13 @@ fapi2::ReturnCode rcd_restore( const fapi2::Target<TARGET_TYPE_MCA>& i_target ) std::vector<uint64_t> l_ranks; // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector l_program.iv_poll.iv_initial_delay = 0; l_program.iv_poll.iv_initial_sim_delay = 0; - // We expect to come in with the port in STR. Before proceeding with - // restoring the RCD, power down needs to be disabled first on the RCD so - // the rest of the CWs can be restored with CKE low - for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) - { - FAPI_DBG("rc09_disable_powerdown for %s", mss::c_str(d)); - FAPI_TRY( rc09_disable_powerdown(d, l_program.iv_instructions), - "Failed rc09_disable_powerdown() for %s", mss::c_str(d) ); - }// dimms - - // Exit STR first so CKE is back to high and rcd isn't ignoring us - FAPI_TRY( self_refresh_exit( i_target ) ); - - FAPI_TRY( mss::ccs::workarounds::nvdimm::execute(l_mcbist, l_program, i_target), - "Failed to execute ccs for %s", mss::c_str(i_target) ); - - // Now, drive CKE back to low via STR entry instead of pde (we have data in the drams!) - FAPI_TRY( self_refresh_entry( i_target ) ); - - l_program = ccs::program<TARGET_TYPE_MCBIST>(); //Reset the program - // Now, fill the program with instructions to program the RCD for ( const auto& d : mss::find_targets<TARGET_TYPE_DIMM>(i_target) ) { @@ -513,7 +457,7 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); std::vector<uint64_t> l_ranks; uint8_t l_trp[MAX_DIMM_PER_PORT]; - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Get tRP FAPI_TRY(mss::eff_dram_trp(mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target), l_trp)); @@ -526,9 +470,9 @@ fapi2::ReturnCode post_restore_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA for ( const auto r : l_ranks) { FAPI_DBG("precharge_all_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::precharge_all_command<TARGET_TYPE_MCBIST>(r, l_trp[0]) ); + l_program.iv_instructions.push_back( ccs::precharge_all_command(r, l_trp[0]) ); FAPI_DBG("zqcal_command for %s", mss::c_str(d)); - l_program.iv_instructions.push_back( ccs::zqcl_command<TARGET_TYPE_MCBIST>(r, mss::tzqinit()) ); + l_program.iv_instructions.push_back( ccs::zqcl_command(r, mss::tzqinit()) ); } }// dimms @@ -608,12 +552,12 @@ fapi2::ReturnCode post_restore_transition( const fapi2::Target<fapi2::TARGET_TYP FAPI_TRY(get_refresh_overrun_mask(i_target, l_refresh_overrun_mask)); FAPI_TRY(change_refresh_overrun_mask(i_target, mss::states::ON)); - // Restore the rcd - FAPI_TRY( rcd_restore( i_target ) ); - // Exit STR FAPI_TRY( self_refresh_exit( i_target ) ); + // Restore the rcd + FAPI_TRY( rcd_restore( i_target ) ); + // Load the MRS FAPI_TRY( mss::mrs_load( i_target, NVDIMM_WORKAROUND ) ); @@ -635,6 +579,26 @@ fapi_try_exit: } /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state) +{ + const auto& l_mcs = mss::find_target<fapi2::TARGET_TYPE_MCS>(i_target); + fapi2::buffer<uint64_t> l_data; + + FAPI_TRY( mss::getScom(l_mcs, MCS_MCFGP, l_data) ); + l_data.writeBit<MCS_MCFGP_VALID>(i_state); + FAPI_INF("Changing MCS_MCFGP_VALID to %d on %s", i_state, mss::c_str(l_mcs)); + FAPI_TRY( mss::putScom(l_mcs, MCS_MCFGP, l_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful @@ -643,15 +607,15 @@ fapi_try_exit: /// fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); const auto& l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(i_target); constexpr uint64_t CS_N_ACTIVE = 0b00; uint8_t l_trp = 0; uint16_t l_trfc = 0; std::vector<uint64_t> l_ranks; - ccs::program<TARGET_TYPE_MCBIST> l_program; - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::program l_program; + ccs::instruction_t l_inst; // Get tRP and tRFC FAPI_TRY(mss::eff_dram_trp(i_target, l_trp)); @@ -662,14 +626,14 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Start the program with DES and wait for tRFC // All CKE = high, all CSn = high, Reset_n = high, wait tRFC - l_inst = ccs::des_command<TARGET_TYPE_MCBIST>(l_trfc); + l_inst = ccs::des_command(l_trfc); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); FAPI_INF("des_command() arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); // Precharge all command // All CKE = high, all CSn = low, Reset_n = high, wait tRP - l_inst = ccs::precharge_all_command<TARGET_TYPE_MCBIST>(0, l_trp); + l_inst = ccs::precharge_all_command(0, l_trp); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.setBit<TT::ARR0_DDR_RESETN>(); @@ -678,7 +642,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Self-refresh entry command // All CKE = low, all CSn = low, Reset_n = high, wait tCKSRE - l_inst = ccs::self_refresh_entry_command<TARGET_TYPE_MCBIST>(0, mss::tcksre(l_dimms[0])); + l_inst = ccs::self_refresh_entry_command(0, mss::tcksre(l_dimms[0])); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); l_inst.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(mss::CKE_LOW); @@ -688,7 +652,7 @@ fapi2::ReturnCode preload_epow_sequence( const fapi2::Target<fapi2::TARGET_TYPE_ // Push in an empty instruction for RESETn // All CKE = low, all CSn = high (default), Reset_n = low - l_inst = ccs::instruction_t<TARGET_TYPE_MCBIST>(); + l_inst = ccs::instruction_t(); FAPI_INF("Assert RESETn arr0 = 0x%016lx , arr1 = 0x%016lx", l_inst.arr0, l_inst.arr1); l_program.iv_instructions.push_back(l_inst); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H index a3c4914a4..8345cae05 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/nvdimm_utils.H @@ -34,11 +34,11 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/shared/mss_const.H> -#include <lib/ccs/ccs.H> #include <lib/phy/dp16.H> #include <lib/mc/port.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -182,15 +182,6 @@ template< fapi2::TargetType T > fapi2::ReturnCode self_refresh_exit( const fapi2::Target<T>& i_target ); /// -/// @brief Disable powerdown mode in rc09 -/// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> -/// @param[in,out] io_inst a vector of CCS instructions we should add to -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); - -/// /// @brief Load the rcd control words /// @param[in] i_target, a fapi2::Target<TARGET_TYPE_DIMM> /// @param[in,out] io_inst a vector of CCS instructions we should add to @@ -199,7 +190,7 @@ fapi2::ReturnCode rc09_disable_powerdown( const fapi2::Target<fapi2::TARGET_TYPE /// with NVDIMMs /// fapi2::ReturnCode rcd_load_nvdimm( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Restore the rcd after restoring the nvdimm data @@ -237,6 +228,14 @@ template< fapi2::TargetType T > fapi2::ReturnCode post_restore_transition( const fapi2::Target<T>& i_target ); /// +/// @brief Helper to change the BAR valid state. Consumed by hostboot +/// @param[in] i_target the target associated with this subroutine +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint8_t i_state); + +/// /// @brief Preload the CCS with the EPOW sequence /// @param[in] i_target the target associated with this subroutine /// @return FAPI2_RC_SUCCESS iff setup was successful diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C index c1cab4997..a864ea8d2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.C @@ -35,10 +35,11 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> - +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <lib/phy/phy_cntrl.H> #include <lib/dimm/ddr4/pba.H> @@ -113,7 +114,7 @@ fapi_try_exit: /// fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -145,7 +146,7 @@ fapi_try_exit: /// fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -200,10 +201,10 @@ fapi2::ReturnCode execute_commands( const fapi2::Target<fapi2::TARGET_TYPE_DIMM> // Issue PBA commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Inserts the DES command to ensure we keep our CKE high - l_program.iv_instructions.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + l_program.iv_instructions.push_back(mss::ccs::des_command()); // Makes a copy of the vector, so we can do the function space swaps correctly auto l_bcws = i_bcws; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H index 34706d492..c2d47fed3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pba.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,8 +39,9 @@ #include <fapi2.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <map> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C index a89cee0e2..8eb698a62 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,10 +37,13 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> +#include <lib/mc/port.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/latch_wr_vref.H> @@ -49,6 +52,7 @@ #include <lib/dimm/ddr4/pda.H> #include <lib/workarounds/ccs_workarounds.H> + namespace mss { @@ -209,7 +213,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -232,7 +236,7 @@ fapi_try_exit: fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -261,7 +265,7 @@ fapi_try_exit: /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ) + std::vector< ccs::instruction_t >& io_inst ) { mss::ddr4::mrs03_data l_mrs03( i_target, fapi2::current_err ); FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS03 data from attributes", mss::c_str(i_target)); @@ -284,7 +288,7 @@ fapi_try_exit: fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank ) { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -344,7 +348,7 @@ fapi2::ReturnCode execute_wr_vref_latch( const fapi2::Target<fapi2::TARGET_TYPE_ // Issue MRS commands { - ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; FAPI_TRY(mss::ddr4::add_latch_wr_vref_commands( i_target, i_mrs, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H index 379b0a2ba..c28dcceac 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/pda.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,14 +38,18 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/phy/write_cntrl.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> + #include <map> namespace mss @@ -170,7 +174,7 @@ fapi2::ReturnCode blast_dram_config( const fapi2::Target<fapi2::TARGET_TYPE_MCA> /// fapi2::ReturnCode add_enable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Enters into and configures PDA mode @@ -190,7 +194,7 @@ fapi2::ReturnCode enter( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// fapi2::ReturnCode add_disable( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst ); + std::vector< ccs::instruction_t >& io_inst ); /// /// @brief Exits out of and disables PDA mode @@ -313,7 +317,7 @@ class commands // Check for a valid rank FAPI_ASSERT(mss::rank::is_rank_on_dimm(i_target, i_rank), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). + set_PORT_TARGET(mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target)). set_RANK(i_rank). set_FUNCTION(mss::ffdc_function_codes::PDA_ADD_COMMAND), "%s does not have rank %lu", mss::c_str(i_target), i_rank); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C index 6e53bddd8..e522f970f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,13 +36,17 @@ #include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> +#include <lib/shared/mss_const.H> #include <lib/dimm/ddr4/zqcal.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/eff_config/timing.H> #include <lib/workarounds/ccs_workarounds.H> + using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_DIMM; @@ -61,15 +65,15 @@ namespace mss template<> fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { - ccs::instruction_t<TARGET_TYPE_MCBIST> l_inst; + ccs::instruction_t l_inst; uint64_t tDLLK = 0; FAPI_TRY( mss::tdllk(i_target, tDLLK) ); // Note: this isn't general - assumes Nimbus via MCBIST instruction here BRS - l_inst = ccs::zqcl_command<TARGET_TYPE_MCBIST>(i_rank); + l_inst = ccs::zqcl_command(i_rank); // Doubling tZQ to better margin per lab request { @@ -98,7 +102,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // For LRDIMMs, program BCW to send ZQCal Long command to all data buffers // in broadcast mode @@ -128,7 +132,7 @@ template<> fapi2::ReturnCode setup_and_execute_zqcal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const fapi2::buffer<uint32_t>& i_cal_steps_enabled) { - mss::ccs::program<TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; for ( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target) ) { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H index d78a512f1..d80febc3b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/ddr4/zqcal.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,11 @@ #include <vector> #include <fapi2.H> -#include <lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -46,28 +50,26 @@ namespace mss /// /// @brief Setup DRAM ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in] i_rank the current rank /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_dram_zqcal( const fapi2::Target<T>& i_target, const uint64_t i_rank, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup LRDIMM data buffer ZQCL /// @tparam T the target type associated with this cal -/// @tparam TT the target type of the CCS instruction /// @param[in] i_target the target associated with this cal /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType TT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_data_buffer_zqcal( const fapi2::Target<T>& i_target, - std::vector< ccs::instruction_t<TT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup and execute DRAM ZQCL diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C index 38f6e9bae..2c3a3a757 100755..100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.C @@ -44,13 +44,14 @@ #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/rank.H> #include <lib/utils/mss_nimbus_conversions.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/dimm/eff_dimm.H> #include <lib/dimm/mrs_load.H> #include <lib/shared/mss_kind.H> #include <lib/phy/dp16.H> #include <lib/mss_attribute_accessors_manual.H> #include <generic/memory/lib/utils/freq/gen_mss_freq.H> +#include <lib/workarounds/eff_config_workarounds.H> namespace mss { @@ -366,16 +367,6 @@ enum invalid_freq_function_encoding : uint8_t F0BC6X = 0x60, }; -/// -/// @brief encoding for MSS_INVALID_TIMING so we can look up functions based on encoding -/// -enum invalid_timing_function_encoding : uint8_t -{ - TRRD_S = 0, - TRRD_L = 1, - TFAW = 2, -}; - ///////////////////////// // Non-member function implementations ///////////////////////// @@ -1577,6 +1568,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc03() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x08; fapi2::buffer<uint8_t> l_buffer; uint8_t l_attrs_dimm_rc03[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; @@ -1599,6 +1591,10 @@ fapi2::ReturnCode eff_dimm::dimm_rc03() l_buffer.insertFromRight<CA_START, LEN>(l_ca_output_drive) .insertFromRight<CS_START, LEN>(l_cs_output_drive); } + + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc03(iv_mcs, &l_attrs_dimm_rc03[0][0]) ); @@ -1618,6 +1614,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc04() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x0a; uint8_t l_attrs_dimm_rc04[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; uint8_t l_odt_output_drive = 0; uint8_t l_cke_output_drive = 0; @@ -1641,6 +1638,9 @@ fapi2::ReturnCode eff_dimm::dimm_rc04() .insertFromRight<ODT_START, LEN>(l_odt_output_drive); } + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc04(iv_mcs, &l_attrs_dimm_rc04[0][0]) ); @@ -1660,6 +1660,7 @@ fapi_try_exit: /// fapi2::ReturnCode eff_dimm::dimm_rc05() { + constexpr uint8_t NVDIMM_RCW_WORKAROUND_VALUE = 0x0a; uint8_t l_attrs_dimm_rc05[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; uint8_t l_a_side_output_drive = 0; uint8_t l_b_side_output_drive = 0; @@ -1683,6 +1684,9 @@ fapi2::ReturnCode eff_dimm::dimm_rc05() .insertFromRight<A_START, LEN>(l_a_side_output_drive); } + // Update the value if the NVDIMM workaround is needed + FAPI_TRY(mss::workarounds::eff_config::nvdimm_rc_drive_strength(iv_dimm, NVDIMM_RCW_WORKAROUND_VALUE, l_buffer)); + // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_rc05(iv_mcs, &l_attrs_dimm_rc05[0][0]) ); @@ -2960,36 +2964,44 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::vref_dq_train_value_and_range() { - constexpr uint8_t VREF_73PERCENT = 0x14; - constexpr uint8_t VREF_83PERCENT = 0x24; - constexpr uint8_t TRAIN_VALUE[NUM_VALID_RANKS_CONFIGS] = - { - VREF_73PERCENT, // 2 ranks per DIMM - VREF_83PERCENT, // 4 ranks per DIMM - }; - // Yes, range1 has a value of 0 this is taken from the JEDEC spec - constexpr uint8_t RANGE1 = 0x00; - constexpr uint8_t TRAIN_RANGE[NUM_VALID_RANKS_CONFIGS] = - { - RANGE1, - RANGE1, - }; - - + // Bits for range decode from the SPD + constexpr uint8_t RANK0 = 7; + constexpr uint8_t RANK1 = 6; + constexpr uint8_t RANK2 = 5; + constexpr uint8_t RANK3 = 4; uint8_t l_vref_dq_train_value[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; uint8_t l_vref_dq_train_range[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; + fapi2::buffer<uint8_t > l_range; // Gets the attributes FAPI_TRY( eff_vref_dq_train_value(iv_mcs, &l_vref_dq_train_value[0][0][0]) ); FAPI_TRY( eff_vref_dq_train_range(iv_mcs, &l_vref_dq_train_range[0][0][0]) ); - // Using hardcoded values for 2R settings from the IBM SI team - // It should be good enough to get us going - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) - { - l_vref_dq_train_value[iv_port_index][iv_dimm_index][mss::index(l_rank)] = TRAIN_VALUE[iv_master_ranks_index]; - l_vref_dq_train_range[iv_port_index][iv_dimm_index][mss::index(l_rank)] = TRAIN_RANGE[iv_master_ranks_index]; - } + // Value is easy, just drop the values in from the SPD + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank0(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK0])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank1(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK1])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank2(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK2])); + FAPI_TRY( iv_spd_decoder.dram_vref_dq_rank3(l_vref_dq_train_value[iv_port_index][iv_dimm_index][ATTR_RANK3])); + + // Range requires some decoding + FAPI_TRY( iv_spd_decoder.dram_vref_dq_range(l_range)); + + // Do the decode for each rank + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK0] = l_range.getBit<RANK0>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK1] = l_range.getBit<RANK1>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK2] = l_range.getBit<RANK2>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; + + l_vref_dq_train_range[iv_port_index][iv_dimm_index][ATTR_RANK3] = l_range.getBit<RANK3>() ? + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE2 : + fapi2::ENUM_ATTR_EFF_VREF_DQ_TRAIN_RANGE_RANGE1; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_VREF_DQ_TRAIN_VALUE, iv_mcs, l_vref_dq_train_value), "Failed setting attribute for ATTR_EFF_VREF_DQ_TRAIN_VALUE"); @@ -4090,7 +4102,7 @@ fapi2::ReturnCode eff_dimm::dram_trrd_s() l_trrd_s_in_nck); } - FAPI_TRY( trrd_s( iv_dimm, iv_dram_width, l_jedec_trrd) ); + FAPI_TRY( trrd_s( iv_dimm, iv_dram_width, iv_freq, l_jedec_trrd) ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_trrd != l_trrd_s_in_nck) @@ -4166,7 +4178,7 @@ fapi2::ReturnCode eff_dimm::dram_trrd_l() l_trrd_l_in_nck); } - FAPI_TRY( trrd_l( iv_dimm, iv_dram_width, l_jedec_trrd) ); + FAPI_TRY( trrd_l( iv_dimm, iv_dram_width, iv_freq, l_jedec_trrd) ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_trrd != l_trrd_l_in_nck) @@ -4265,7 +4277,7 @@ fapi2::ReturnCode eff_dimm::dram_tfaw() l_tfaw_in_nck); } - FAPI_TRY( mss::tfaw(iv_dimm, iv_dram_width, l_jedec_tfaw_in_nck), "Failed tfaw()" ); + FAPI_TRY( mss::tfaw(iv_dimm, iv_dram_width, iv_freq, l_jedec_tfaw_in_nck), "Failed tfaw()" ); // Taking the worst case between the required minimum JEDEC value and the proposed value from SPD if (l_jedec_tfaw_in_nck != l_tfaw_in_nck) @@ -4334,11 +4346,15 @@ fapi2::ReturnCode eff_dimm::dram_tras() // which will give the best timing value for the dimm // (like 2400 MT/s) which may be different than the system // speed (if we were being limited by VPD or MRW restrictions) - const uint64_t l_tras_in_ps = mss::tras(iv_dimm); + uint64_t l_tras_in_ps; + uint64_t l_freq = 0; + uint8_t l_tras_in_nck = 0; // Calculate nck std::vector<uint8_t> l_attrs_dram_tras(PORTS_PER_MCS, 0); - uint8_t l_tras_in_nck = 0; + + FAPI_TRY( freq(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(iv_dimm), l_freq) ); + l_tras_in_ps = mss::tras(iv_dimm, l_freq); // Cast needed for calculations to be done on the same integral type // as required by template deduction. We have iv_tCK_in_ps as a signed @@ -4471,20 +4487,22 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_nom() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b111, // 2R - 34Ohm - 0b111, // 4R - 34Ohm - }; + std::vector< uint64_t > l_ranks; + uint8_t l_decoder_val = 0; uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; FAPI_TRY( eff_dram_rtt_nom(iv_mcs, &l_mcs_attrs[0][0][0]) ); - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_nom(iv_freq, l_decoder_val)); + + // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value + // Same value for every rank for LRDIMMs + FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks)); + + for (const auto& l_rank : l_ranks) { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = DRAM_RTT_VALUES[iv_master_ranks_index]; + l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val; } FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_NOM, iv_mcs, l_mcs_attrs) ); @@ -4553,25 +4571,22 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_wr() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b000, // 2R - disable - 0b001, // 4R - 120Ohm - }; + std::vector< uint64_t > l_ranks; + uint8_t l_decoder_val = 0; uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; FAPI_TRY( eff_dram_rtt_wr(iv_mcs, &l_mcs_attrs[0][0][0]) ); - // The host is in charge of ensuring good termination from the buffer to the DRAM - // That means that we need to know and set the settings - // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP - // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be - // Loops through all ranks - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_wr(iv_freq, l_decoder_val)); + + // Plug into every rank position for the attribute so it'll fit the same style as the RDIMM value + // Same value for every rank for LRDIMMs + FAPI_TRY(mss::rank::ranks(iv_dimm, l_ranks)); + + for (const auto& l_rank : l_ranks) { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][l_rank] = DRAM_RTT_VALUES[iv_master_ranks_index]; + l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = l_decoder_val; } // Set the attribute @@ -4632,28 +4647,27 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dram_rtt_park() { - constexpr uint8_t DRAM_RTT_VALUES[NUM_VALID_RANKS_CONFIGS] = - { - 0b000, // 2R - disable - 0b010, // 4R - 120Ohm - }; - uint8_t l_mcs_attrs[PORTS_PER_MCS][MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM] = {}; + uint8_t l_decoder_val_01 = 0; + uint8_t l_decoder_val_23 = 0; FAPI_TRY( eff_dram_rtt_park(iv_mcs, &l_mcs_attrs[0][0][0]) ); - // The host is in charge of ensuring good termination from the buffer to the DRAM - // That means that we need to know and set the settings - // Currently, our SI team thinks that the 2R single drop open power settings will work for BUP - // We're going to hard code in those settings the above story can be used as a catchall to improve settings if need be - // Loops through all ranks - for(uint64_t l_rank = 0; l_rank < MAX_RANK_PER_DIMM; ++l_rank) - { - // Gets the ODT scheme for the DRAM for this DIMM - we only want to toggle ODT to the DIMM we are writing to - // We do a bitwise mask here to only get the ODT for the current DIMM - l_mcs_attrs[iv_port_index][iv_dimm_index][mss::index(l_rank)] = DRAM_RTT_VALUES[iv_master_ranks_index]; - } + // Get the value from the LRDIMM SPD + FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks0_1(iv_freq, l_decoder_val_01), + "%s failed to decode RTT_PARK for ranks 0/1", mss::c_str(iv_mcs) ); + FAPI_TRY( iv_spd_decoder.dram_rtt_park_ranks2_3(iv_freq, l_decoder_val_23), + "%s failed to decode RTT_PARK for ranks 2/3", mss::c_str(iv_mcs) ); + // Setting the four rank values for this dimm + // Rank 0 and 1 have the same value, l_decoder_val_01 + // Rank 2 and 3 have the same value, l_decoder_val_23 + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK0] = l_decoder_val_01; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK1] = l_decoder_val_01; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK2] = l_decoder_val_23; + l_mcs_attrs[iv_port_index][iv_dimm_index][ATTR_RANK3] = l_decoder_val_23; + + // Set the attribute FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_RTT_PARK, iv_mcs, l_mcs_attrs) ); fapi_try_exit: @@ -4956,13 +4970,18 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_bc04() { + uint8_t l_decoder_val = 0; // Retrieve MCS attribute data uint8_t l_attrs_dimm_bc04[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_ddr4_bc04(iv_mcs, &l_attrs_dimm_bc04[0][0]) ); - // Taken from SI spreadsheet and JEDEC - we want 60 Ohms, so 0x01 for a value - l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] = 0x01; + // So the encoding from the SPD is the same as the encoding for the buffer control encoding + // Simple grab and insert + // Value is checked in decoder function for validity + FAPI_TRY( iv_spd_decoder.data_buffer_mdq_rtt(iv_freq, l_decoder_val) ); + l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] = l_decoder_val; + // Update MCS attribute FAPI_INF("%s: BC04 settting (MDQ_RTT): %d", mss::c_str(iv_dimm), l_attrs_dimm_bc04[iv_port_index][iv_dimm_index] ); FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC04, iv_mcs, l_attrs_dimm_bc04) ); @@ -4980,20 +4999,20 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_bc05() { - // Taken from the SI spreadsheet - we want 34 Ohms so 0x01 - fapi2::buffer<uint8_t> l_result(0x01); + uint8_t l_decoder_val = 0; // Retrieve MCS attribute data uint8_t l_attrs_dimm_bc05[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; FAPI_TRY( eff_dimm_ddr4_bc05(iv_mcs, &l_attrs_dimm_bc05[0][0]) ); - // Using a writeBit for clarity sake - // Enabling DQ/DQS drivers - l_result.writeBit<BC05_DRAM_DQ_DRIVER_DISABLE_POS>(BC05_DRAM_DQ_DRIVER_ENABLE); - l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_result; + // Same as BC04, grab from SPD and put into BC + FAPI_TRY( iv_spd_decoder.data_buffer_mdq_drive_strength(iv_freq, l_decoder_val) ); + l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] = l_decoder_val; - FAPI_INF("%s: BC05 settting (MDQ Drive Strength): 0x%02x", mss::c_str(iv_dimm), + FAPI_INF("%s: BC05 settting (MDQ Drive Strength): %d", mss::c_str(iv_dimm), l_attrs_dimm_bc05[iv_port_index][iv_dimm_index] ); + + // Updates the attribute FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_BC05, iv_mcs, l_attrs_dimm_bc05) ); fapi_try_exit: @@ -5514,20 +5533,17 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::dimm_f5bc6x() { - constexpr uint8_t VREF_73PERCENT = 0x14; - constexpr uint8_t VREF_83PERCENT = 0x24; - constexpr uint8_t RD_VREF[NUM_VALID_RANKS_CONFIGS] = - { - VREF_73PERCENT, // 2 ranks per DIMM - VREF_83PERCENT, // 4 ranks per DIMM - }; + uint8_t l_decode = 0; uint8_t l_attrs_dimm_f5bc6x[PORTS_PER_MCS][MAX_DIMM_PER_PORT] = {}; // Retrieve MCS attribute data FAPI_TRY( eff_dimm_ddr4_f5bc6x(iv_mcs, &l_attrs_dimm_f5bc6x[0][0]) ); + // Gets the SPD value + FAPI_TRY( iv_spd_decoder.data_buffer_vref_dq(l_decode)); + // F5BC6x is just the VREF training range - l_attrs_dimm_f5bc6x[iv_port_index][iv_dimm_index] = RD_VREF[iv_master_ranks_index]; + l_attrs_dimm_f5bc6x[iv_port_index][iv_dimm_index] = l_decode; FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_DDR4_F5BC6x, iv_mcs, l_attrs_dimm_f5bc6x), "Failed setting attribute for ATTR_EFF_DIMM_DDR4_F5BC6x"); @@ -5678,7 +5694,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::MT). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD MT keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5702,7 +5718,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::MR). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD MR keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5723,7 +5739,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::CK). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD CK keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5742,7 +5758,7 @@ fapi2::ReturnCode eff_dimm::decode_vpd(const fapi2::Target<TARGET_TYPE_MCS>& i_t set_MAX(mss::VPD_KEYWORD_MAX). set_ACTUAL(l_vpd_info.iv_size). set_KEYWORD(fapi2::MemVpdData::DQ). - set_MCS_TARGET(i_target), + set_VPD_TARGET(i_target), "VPD DQ keyword size retrieved: %d, is larger than max: %d for %s", l_vpd_info.iv_size, mss::VPD_KEYWORD_MAX, mss::c_str(i_target)); @@ -5989,10 +6005,13 @@ fapi_try_exit: /// fapi2::ReturnCode eff_lrdimm::odt_wr() { + // Values were obtained experimentally + // For 2R, opposite termination is ideal + // For 4R, terminating everything is ideal constexpr uint8_t DRAM_ODT_VALUES[NUM_VALID_RANKS_CONFIGS][MAX_RANK_PER_DIMM] = { { 0x44, 0x88, 0x00, 0x00, }, // 2 ranks per DIMM - { 0x44, 0x88, 0x44, 0x88, }, // 4 ranks per DIMM + { 0xcc, 0xcc, 0xcc, 0xcc, }, // 4 ranks per DIMM }; // Masks on the ODT for a specific DIMM diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H index f60adaf7c..477b7114c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/eff_dimm.H @@ -38,7 +38,7 @@ #include <generic/memory/lib/spd/common/rcw_settings.H> #include <lib/spd/spd_factory.H> #include <lib/eff_config/timing.H> -#include <generic/memory/lib/data_engine/pre_data_init.H> +#include <lib/eff_config/pre_data_init.H> #include <generic/memory/lib/spd/spd_utils.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H deleted file mode 100644 index ee707c821..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H +++ /dev/null @@ -1,263 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/kind.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file dimm.H -/// @brief Encapsulation for dimms of all types -/// -// *HWP HWP Owner: Jacob Harvey <jlharvey@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _MSS_DIMM_H_ -#define _MSS_DIMM_H_ - -#include <fapi2.H> - -#include <lib/mss_attribute_accessors.H> -#include <generic/memory/lib/utils/c_str.H> - -namespace mss -{ - -namespace dimm -{ - -/// -/// @class mss::dimm::kind -/// @brief A class containing information about a dimm like ranks, density, configuration - what kind of dimm is it? -/// -class kind -{ - public: - - /// - /// @brief Generate a vector of DIMM kind from a vector of DIMM - /// @param[in] i_dimm a vector of DIMM - /// @return std::vector of dimm::kind relating to the DIMM passed in - /// - static std::vector<kind> vector(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimm) - { - std::vector<kind> l_kinds; - - for (const auto& d : i_dimm) - { - l_kinds.push_back( kind(d) ); - } - - return l_kinds; - } - - /// - /// @brief operator=() - assign kinds (needed to sort vectors of kinds) - /// @param[in] i_rhs the right hand side of the assignment statement - /// @return reference to this - /// - inline kind& operator=(const kind& i_rhs) - { - iv_target = i_rhs.iv_target; - iv_master_ranks = i_rhs.iv_master_ranks; - iv_total_ranks = i_rhs.iv_total_ranks; - iv_dram_density = i_rhs.iv_dram_density; - iv_dram_width = i_rhs.iv_dram_width; - iv_dram_generation = i_rhs.iv_dram_generation; - iv_dimm_type = i_rhs.iv_dimm_type; - iv_rows = i_rhs.iv_rows; - iv_size = i_rhs.iv_size; - iv_mfgid = i_rhs.iv_mfgid; - iv_stack_type = i_rhs.iv_stack_type; - iv_hybrid = i_rhs.iv_hybrid; - iv_hybrid_memory_type = i_rhs.iv_hybrid_memory_type; - iv_rcd_mfgid = i_rhs.iv_rcd_mfgid; - return *this; - } - - /// - /// @brief operator==() - are two kinds the same? - /// @param[in] i_rhs the right hand side of the comparison statement - /// @return bool true iff the two kind are of the same kind - /// @warning this does not compare the targets (iv_target,) just the values - /// Also does not compare the mfgid as that's not really part of the DIMM kind but is additional information - /// - inline bool operator==(const kind& i_rhs) const - { - return ((iv_master_ranks == i_rhs.iv_master_ranks) && - (iv_total_ranks == i_rhs.iv_total_ranks) && - (iv_dram_density == i_rhs.iv_dram_density) && - (iv_dram_width == i_rhs.iv_dram_width) && - (iv_dram_generation == i_rhs.iv_dram_generation) && - (iv_dimm_type == i_rhs.iv_dimm_type) && - (iv_rows == i_rhs.iv_rows) && - (iv_size == i_rhs.iv_size) && - (iv_stack_type == i_rhs.iv_stack_type) && - (iv_hybrid == i_rhs.iv_hybrid) && - (iv_hybrid_memory_type == i_rhs.iv_hybrid_memory_type) && - (iv_rcd_mfgid == i_rhs.iv_rcd_mfgid)); - } - - /// - /// @brief operator!=() - are two kinds different? - /// @param[in] i_rhs the right hand side of the comparison statement - /// @return bool true iff the two kind are of different - /// @warning this does not compare the targets (iv_target,) just the values - /// - inline bool operator!=(const kind& i_rhs) const - { - return !(this->operator==(i_rhs)); - } - - /// - /// @brief Construct a dimm::kind data structure - information about the kind of DIMM this is - /// @param[in] i_target a DIMM target - /// - kind(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target): - iv_target(i_target) - { - FAPI_TRY( mss::eff_dram_gen(i_target, iv_dram_generation) ); - FAPI_TRY( mss::eff_dimm_type(i_target, iv_dimm_type) ); - FAPI_TRY( mss::eff_dram_density(i_target, iv_dram_density) ); - FAPI_TRY( mss::eff_dram_width(i_target, iv_dram_width) ); - FAPI_TRY( mss::eff_num_master_ranks_per_dimm(i_target, iv_master_ranks) ); - FAPI_TRY( mss::eff_num_ranks_per_dimm(i_target, iv_total_ranks) ); - FAPI_TRY( mss::eff_dram_row_bits(i_target, iv_rows) ); - FAPI_TRY( mss::eff_dimm_size(i_target, iv_size) ); - FAPI_TRY( mss::eff_dram_mfg_id(i_target, iv_mfgid) ); - FAPI_TRY( mss::eff_prim_stack_type( i_target, iv_stack_type) ); - FAPI_TRY( mss::eff_hybrid( i_target, iv_hybrid )); - FAPI_TRY( mss::eff_hybrid_memory_type( i_target, iv_hybrid_memory_type )); - FAPI_TRY( mss::eff_rcd_mfg_id(i_target, iv_rcd_mfgid) ); - return; - - fapi_try_exit: - // Not 100% sure what to do here ... - FAPI_ERR("error initializing DIMM structure: %s 0x%016lx", mss::c_str(i_target), uint64_t(fapi2::current_err)); - fapi2::Assert(false); - } - - /// - /// @brief Construct a DIMM kind used to identify this DIMM for tables. - /// @param[in] i_master_ranks number of master ranks on the DIMM - /// @param[in] i_total_ranks total number of ranks on the DIMM - /// @param[in] i_dram_density density of the DRAM - /// @param[in] i_dram_width width of the DRAM - /// @param[in] i_dram_generation DRAM generation - /// @param[in] i_dimm_type DIMM type (e.g. RDIMM) - /// @param[in] i_rows number of rows in the DRAM - /// @param[in] i_size the overal size of the DIMM in GB - /// @param[in] i_mfgid the dram manufacturer id of the dimm, defaulted to 0 - /// @param[in] i_stack_type dram die type, single die package or 3DS - /// @param[in] i_hybrid, default not hybrid - /// @param[in] i_hybrid_memory_type, defult none - /// @param[in] i_rcd_mfgid dimm register and data buffer manufacturer id, default 0 - /// @note can't be constexpr as fapi2::Target doesn't have a constexpr ctor. - /// - kind( const uint8_t i_master_ranks, - const uint8_t i_total_ranks, - const uint8_t i_dram_density, - const uint8_t i_dram_width, - const uint8_t i_dram_generation, - const uint8_t i_dimm_type, - const uint8_t i_rows, - const uint32_t i_size, - const uint16_t i_mfgid = 0, - const uint8_t i_stack_type = fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_SDP, - const uint8_t i_hybrid = fapi2::ENUM_ATTR_EFF_HYBRID_NOT_HYBRID, - const uint8_t i_hybrid_memory_type = fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NONE, - const uint16_t i_rcd_mfgid = 0): - iv_target(0), - iv_master_ranks(i_master_ranks), - iv_total_ranks(i_total_ranks), - iv_dram_density(i_dram_density), - iv_dram_width(i_dram_width), - iv_dram_generation(i_dram_generation), - iv_dimm_type(i_dimm_type), - iv_rows(i_rows), - // TK consider calculating size rather than requiring it be set. - iv_size(i_size), - iv_mfgid(i_mfgid), - iv_stack_type(i_stack_type), - iv_hybrid(i_hybrid), - iv_hybrid_memory_type(i_hybrid_memory_type), - iv_rcd_mfgid(i_rcd_mfgid) - { - // Bit of an idiot-check to be sure a hand-crafted dimm::kind make sense wrt slaves, masters, packages, etc. - // Both of these are checked in eff_config. If they are messed up, they should be caught there - if (iv_master_ranks > iv_total_ranks) - { - FAPI_ERR("Not enough total ranks? master: %d total: %d", - iv_master_ranks, - iv_total_ranks); - fapi2::Assert(false); - } - - if ((iv_total_ranks % iv_master_ranks) != 0) - { - FAPI_ERR("total or master ranks seems incorrect. master: %d total: %d", - iv_master_ranks, - iv_total_ranks); - fapi2::Assert(false); - } - } - - fapi2::Target<fapi2::TARGET_TYPE_DIMM> iv_target; - uint8_t iv_master_ranks; - uint8_t iv_total_ranks; - uint8_t iv_dram_density; - uint8_t iv_dram_width; - uint8_t iv_dram_generation; - uint8_t iv_dimm_type; - uint8_t iv_rows; - uint32_t iv_size; - uint16_t iv_mfgid; - uint8_t iv_stack_type; - uint8_t iv_hybrid; - uint8_t iv_hybrid_memory_type; - uint16_t iv_rcd_mfgid; - - /// - /// @brief equal_config - /// @param[in] i_input_compare the i_kind to compare against - /// @return bool true iff the two kind are of the same kind for xlate purposes - /// @warning this does not compare the targets (iv_target,), mfgid, prim_stack_type nor hybrid type - /// - inline bool equal_config(const kind& i_input_compare) const - { - return ((iv_master_ranks == i_input_compare.iv_master_ranks) && - (iv_total_ranks == i_input_compare.iv_total_ranks) && - (iv_dram_density == i_input_compare.iv_dram_density) && - (iv_dram_width == i_input_compare.iv_dram_width) && - (iv_dram_generation == i_input_compare.iv_dram_generation) && - (iv_dimm_type == i_input_compare.iv_dimm_type) && - (iv_rows == i_input_compare.iv_rows) && - (iv_size == i_input_compare.iv_size)); - } -}; - -} - -} -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C index aae4cce28..8928a6f98 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.C @@ -62,7 +62,7 @@ fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the // instructions in the CCS instruction vector @@ -72,7 +72,17 @@ fapi2::ReturnCode mrs_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA for ( const auto& d : find_targets<TARGET_TYPE_DIMM>(i_target) ) { FAPI_DBG("mrs load for %s", mss::c_str(d)); - FAPI_TRY( perform_mrs_load(d, l_program.iv_instructions) ); + + // TK - break out the nvdimm stuff into function + if (i_nvdimm_workaround) + { + FAPI_DBG("nvdimm workaround detected. loading mrs for restore sequence"); + FAPI_TRY( ddr4::mrs_load_nvdimm(d, l_program.iv_instructions) ); + } + else + { + FAPI_TRY( perform_mrs_load(d, l_program.iv_instructions) ); + } } // We have to configure the CCS engine to let it know which port these instructions are @@ -121,7 +131,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -151,7 +161,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform mrs_load for %s [expecting rdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( ddr4::mrs_load(i_target, io_inst) ); @@ -168,7 +178,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_DBG("perform mrs_load for %s [expecting lrdimm (ddr4)]", mss::c_str(i_target)); FAPI_TRY( ddr4::mrs_load(i_target, io_inst) ); @@ -186,7 +196,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H index f19679bc7..f18050f12 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/mrs_load.H @@ -38,10 +38,13 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -90,15 +93,15 @@ struct mrs_data // The attribute getter. For MRS we pass in the ARR0 of the CCS instruction // as that allows us to encapsulate the attribute processing and the bit // manipulation in one function. - fapi2::ReturnCode (*iv_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t<T>&, const uint64_t); - fapi2::ReturnCode (*iv_dumper)(const ccs::instruction_t<T>&, const uint64_t); + fapi2::ReturnCode (*iv_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t&, const uint64_t); + fapi2::ReturnCode (*iv_dumper)(const ccs::instruction_t&, const uint64_t); // The delay needed after this MRS word is written uint64_t iv_delay; mrs_data( const uint64_t i_mrs, - fapi2::ReturnCode (*i_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t<T>&, const uint64_t), - fapi2::ReturnCode (*i_dumper)(const ccs::instruction_t<T>&, const uint64_t), + fapi2::ReturnCode (*i_func)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>&, ccs::instruction_t&, const uint64_t), + fapi2::ReturnCode (*i_dumper)(const ccs::instruction_t&, const uint64_t), const uint64_t i_delay ): iv_mrs(i_mrs), iv_func(i_func), @@ -174,7 +177,7 @@ struct perform_mrs_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_mrs_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads @@ -186,7 +189,7 @@ perform_mrs_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, /// template<> fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads /// @param[in] i_target the dimm target for the mrs's @@ -197,7 +200,7 @@ fapi2::ReturnCode perform_mrs_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::T /// template<> fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Function to perform mrs load overloads /// @param[in] i_kind the i_target's dimm_kind struct @@ -208,7 +211,7 @@ fapi2::ReturnCode perform_mrs_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_mrs_load_overload<K>::available > inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -232,7 +235,7 @@ inline fapi2::ReturnCode perform_mrs_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_mrs_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { return perform_mrs_load<DEFAULT_KIND>(i_target, io_inst); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H new file mode 100644 index 000000000..6c8d16bc0 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H @@ -0,0 +1,85 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file nimbus_kind.H +/// @brief Encapsulation for dimms of all types +/// +// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_NIMBUS_KIND_H_ +#define _MSS_NIMBUS_KIND_H_ + +#include <fapi2.H> + +#include <lib/shared/mss_const.H> +#include <lib/mss_attribute_accessors.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/dimm/kind.H> + +namespace mss +{ + +namespace dimm +{ + +/// +/// @class mss::dimm::kind specilization for NIMBUS +/// @brief A class containing information about a dimm like ranks, density, configuration - what kind of dimm is it? +/// +template<> +inline kind<mss::mc_type::NIMBUS>::kind(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) : + iv_target(i_target), + iv_module_height(0) +{ + FAPI_TRY( mss::eff_dram_gen(i_target, iv_dram_generation) ); + FAPI_TRY( mss::eff_dimm_type(i_target, iv_dimm_type) ); + FAPI_TRY( mss::eff_dram_density(i_target, iv_dram_density) ); + FAPI_TRY( mss::eff_dram_width(i_target, iv_dram_width) ); + FAPI_TRY( mss::eff_num_master_ranks_per_dimm(i_target, iv_master_ranks) ); + FAPI_TRY( mss::eff_num_ranks_per_dimm(i_target, iv_total_ranks) ); + FAPI_TRY( mss::eff_dram_row_bits(i_target, iv_rows) ); + FAPI_TRY( mss::eff_dimm_size(i_target, iv_size) ); + FAPI_TRY( mss::eff_dram_mfg_id(i_target, iv_mfgid) ); + FAPI_TRY( mss::eff_prim_stack_type( i_target, iv_stack_type) ); + FAPI_TRY( mss::eff_hybrid( i_target, iv_hybrid )); + FAPI_TRY( mss::eff_hybrid_memory_type( i_target, iv_hybrid_memory_type )); + FAPI_TRY( mss::eff_rcd_mfg_id(i_target, iv_rcd_mfgid) ); + return; + +fapi_try_exit: + // Not 100% sure what to do here ... + FAPI_ERR("error initializing DIMM structure: %s 0x%016lx", mss::c_str(i_target), uint64_t(fapi2::current_err)); + fapi2::Assert(false); +} + + +} //ns dimm +} //ns mss +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C index 37af40a5b..1026634b1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -902,6 +902,25 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Return a vector of rank numbers which represent the ranks for this dimm +/// @param[in] i_dimm_target TARGET_TYPE_DIMM +/// @param[out] o_ranks a vector of ranks for dimm (numbers) +/// @return FAPI2_RC_SUCCESS iff all is ok +/// +template<> +fapi2::ReturnCode ranks_on_dimm_helper<mss::mc_type::NIMBUS>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_dimm_target, + std::vector<uint64_t>& o_ranks) +{ + std::vector<uint64_t> l_ranks; + FAPI_TRY( mss::rank::ranks(i_dimm_target, l_ranks) ); + o_ranks = l_ranks; + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace rank } // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H index 901ed1a8c..130697bbb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rank.H @@ -41,7 +41,7 @@ #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> #include <generic/memory/lib/utils/scom.H> -#include <lib/utils/num.H> +#include <generic/memory/lib/utils/num.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/shared/mss_const.H> #include <lib/phy/phy_cntrl.H> @@ -1033,7 +1033,7 @@ inline fapi2::ReturnCode set_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_RANK_FIELD), "%s Invalid rank (%d) in set_rank_field", mss::c_str(i_target), @@ -1101,7 +1101,7 @@ inline fapi2::ReturnCode get_rank_field( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANK_FIELD), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1171,7 +1171,7 @@ inline fapi2::ReturnCode set_pair_valid( const fapi2::Target<T>& i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(SET_PAIR_VALID), "%s Invalid rank (%d) in get_ranks_in_pair", mss::c_str(i_target), @@ -1243,7 +1243,7 @@ inline fapi2::ReturnCode get_pair_valid( const fapi2::Target<T> i_target, FAPI_ASSERT( false, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_PAIR_VALID), "%s Invalid rank (%d) passed into get get_pair_valid", mss::c_str(i_target), @@ -1350,7 +1350,7 @@ fapi2::ReturnCode get_ranks_in_pair( const fapi2::Target<T>& i_target, FAPI_ASSERT( l_ordinal < MAX_RANK_PER_DIMM, fapi2::MSS_INVALID_RANK() .set_RANK(l_ordinal) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(GET_RANKS_IN_PAIR), "%s Invalid rank (%d) in set_ranks_in_pair", mss::c_str(i_target), diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C index c999666cd..17bba3a88 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #include <mss.H> #include <lib/dimm/rcd_load.H> #include <lib/dimm/rcd_load_ddr4.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -60,7 +60,7 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); // A vector of CCS instructions. We'll ask the targets to fill it, and then we'll execute it - ccs::program<TARGET_TYPE_MCBIST> l_program; + ccs::program l_program; uint8_t l_sim = 0; // Clear the initial delays. This will force the CCS engine to recompute the delay based on the @@ -76,7 +76,7 @@ fapi2::ReturnCode rcd_load<TARGET_TYPE_MCA>( const fapi2::Target<TARGET_TYPE_MCA // So we use the power down entry command to achieve this if(!l_sim) { - l_program.iv_instructions.push_back( ccs::pde_command<TARGET_TYPE_MCBIST>() ); + l_program.iv_instructions.push_back( ccs::pde_command() ); } FAPI_DBG("rcd load for %s", mss::c_str(d)); @@ -119,7 +119,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -149,7 +149,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<KIND_RDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_sim = 0; FAPI_TRY( mss::is_simulation(l_sim) ); @@ -170,7 +170,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<KIND_LRDIMM_DDR4>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_sim = 0; FAPI_TRY( mss::is_simulation(l_sim) ); @@ -191,7 +191,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode perform_rcd_load<FORCE_DISPATCH>( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { uint8_t l_type = 0; uint8_t l_gen = 0; @@ -206,4 +206,32 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Helper function to bring CKE high and hold for 400 cycles +/// @param[in] i_target MCA target on which to operate +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode draminit_cke_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + + auto l_des = mss::ccs::des_command(); + mss::ccs::program l_program; + + // Also a Deselect command must be registered as required from the Spec. + // Register DES instruction, which pulls CKE high. Idle 400 cycles, and then begin RCD loading + // Note: This only is sent to one of the MCA as we still have the mux_addr_sel bit set, meaning + // we'll PDE/DES all DIMM at the same time. + l_des.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(400); + l_program.iv_instructions.push_back(l_des); + + FAPI_TRY( mss::ccs::execute(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), + l_program, + i_target), + "%s Failed execute in p9_mss_draminit", + mss::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H index b9ee410d6..bfb73ae92 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,9 +39,11 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> - #include <generic/memory/lib/utils/c_str.H> #include <lib/shared/mss_kind.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> namespace mss { @@ -112,7 +114,7 @@ struct perform_rcd_load_overload< KIND_LRDIMM_DDR4 > template< mss::kind_t K = FORCE_DISPATCH > typename std::enable_if< perform_rcd_load_overload<DEFAULT_KIND>::available, fapi2::ReturnCode>::type perform_rcd_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); // // We know we registered overloads for perform_rcd_load, so we need the entry point to @@ -121,11 +123,11 @@ perform_rcd_load( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, // template<> fapi2::ReturnCode perform_rcd_load<FORCE_DISPATCH>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); template<> fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst); + std::vector< ccs::instruction_t >& i_inst); /// /// @brief Start the rcd_load_dispatch boilerplate -- specialization for recursion dispatcher @@ -137,7 +139,7 @@ fapi2::ReturnCode perform_rcd_load<DEFAULT_KIND>( const fapi2::Target<fapi2::TAR template< kind_t K, bool B = perform_rcd_load_overload<K>::available > inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { // We dispatch to another kind if: // We don't have an overload defined (B == false) @@ -162,10 +164,17 @@ inline fapi2::ReturnCode perform_rcd_load_dispatch( const kind_t& i_kind, template<> inline fapi2::ReturnCode perform_rcd_load_dispatch<DEFAULT_KIND>(const kind_t&, const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& i_inst) + std::vector< ccs::instruction_t >& i_inst) { return perform_rcd_load<DEFAULT_KIND>(i_target, i_inst); } +/// +/// @brief Helper function to bring CKE high and hold for 400 cycles +/// @param[in] i_target MCA target on which to operate +/// @return FAPI2_RC_SUCCESS if and only if ok +/// +fapi2::ReturnCode draminit_cke_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); + } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C index 690b7e180..d9cc10e5b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -60,7 +60,7 @@ namespace mss /// fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { FAPI_INF("rcd_load_ddr4 %s", mss::c_str(i_target)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H index bb70c20b6..0c6f8162c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/dimm/rcd_load_ddr4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,6 +53,6 @@ namespace mss /// fapi2::ReturnCode rcd_load_ddr4( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H deleted file mode 100644 index 5a657edac..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H +++ /dev/null @@ -1,789 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file ecc.H -/// @brief Top level API for MSS ECC -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_ECC_H_ -#define _MSS_ECC_H_ - -#include <fapi2.H> -#include <lib/mcbist/mcbist.H> -#include <lib/mcbist/address.H> -#include <lib/ecc/ecc_traits.H> -#include <lib/ecc/galois.H> -#include <lib/ecc/hw_mark_store.H> -#include <lib/ecc/fw_mark_store.H> -#include <lib/ecc/mainline_nce_trap.H> -#include <lib/ecc/mainline_rce_trap.H> -#include <lib/ecc/mainline_mpe_trap.H> -#include <lib/ecc/mainline_ue_trap.H> -#include <lib/ecc/mainline_aue_trap.H> -#include <lib/ecc/mbs_error_vector_trap.H> -#include <lib/ecc/maint_current_trap.H> -#include <lib/ecc/read_error_count_regs.H> -#include <lib/ecc/modal_symbol_count.H> -#include <lib/ecc/mark_shadow_reg.H> - -namespace mss -{ - -namespace ecc -{ - -/// -/// @brief Get Hardware Mark Store -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[in] i_rank the desired rank -/// @param[out] o_galois the Galois code of the mark -/// @param[out] o_confirmed true if the mark is a chipmark -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_hwms( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - uint64_t& o_galois, - mss::states& o_confirmed ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::hwms::read(i_target, i_rank, l_buffer) ); - mss::ecc::hwms::get_chipmark(l_buffer, o_galois); - mss::ecc::hwms::get_confirmed(l_buffer, o_confirmed); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Set Hardware Mark Store -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[in] i_rank the desired rank -/// @param[in] i_galois the Galois code of the mark, or set to 0 to clear mark -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode set_hwms( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_galois ) -{ - fapi2::buffer<uint64_t> l_buffer; - uint8_t l_symbol = 0; - - // galois value of 0 means to clear the mark so only fill in fields if non-zero - if (i_galois != 0) - { - // check for valid Galois code - FAPI_TRY( mss::ecc::galois_to_symbol( (uint8_t)i_galois, l_symbol) ); - - mss::ecc::hwms::set_chipmark(l_buffer, i_galois); - mss::ecc::hwms::set_confirmed(l_buffer, mss::YES); - mss::ecc::hwms::set_exit_1(l_buffer, mss::YES); - } - - FAPI_TRY( mss::ecc::hwms::write(i_target, i_rank, l_buffer) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Firmware Mark Store -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[in] i_rank the desired rank -/// @param[out] o_galois the Galois code of the mark -/// @param[out] o_type the type code of the mark -/// @param[out] o_region the region code of the mark -/// @param[out] o_address the starting address of the mark -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_fwms( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - uint64_t& o_galois, - mss::ecc::fwms::mark_type& o_type, - mss::ecc::fwms::mark_region& o_region, - mss::mcbist::address& o_address ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::fwms::read(i_target, i_rank, l_buffer) ); - mss::ecc::fwms::get_mark(l_buffer, o_galois); - mss::ecc::fwms::get_type(l_buffer, o_type); - mss::ecc::fwms::get_region(l_buffer, o_region); - mss::ecc::fwms::get_address(l_buffer, o_address); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Set Firmware Mark Store -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[in] i_rank the desired rank -/// @param[in] i_galois the Galois code of the mark, or set to 0 to clear mark -/// @param[in] i_type the type code of the mark -/// @param[in] i_region the region code of the mark -/// @param[in] i_address the starting address of the mark -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode set_fwms( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_galois, - const mss::ecc::fwms::mark_type i_type, - const mss::ecc::fwms::mark_region i_region, - const mss::mcbist::address i_address ) -{ - fapi2::buffer<uint64_t> l_buffer = 0; - uint8_t l_symbol = 0; - - // galois value of 0 means to clear the mark so only fill in fields if non-zero - if (i_galois != 0) - { - // check for valid Galois code - FAPI_TRY( mss::ecc::galois_to_symbol( (uint8_t)i_galois, l_symbol) ); - - mss::ecc::fwms::set_mark(l_buffer, i_galois); - mss::ecc::fwms::set_type(l_buffer, i_type); - mss::ecc::fwms::set_region(l_buffer, i_region); - mss::ecc::fwms::set_address(l_buffer, i_address); - mss::ecc::fwms::set_exit_1(l_buffer, mss::YES); - } - - FAPI_TRY( mss::ecc::fwms::write(i_target, i_rank, l_buffer) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Query Hardware Marks -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_marks vector of Galois codes of any marks set -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// @note no rank information is returned -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_hw_marks( const fapi2::Target<T>& i_target, - std::vector<uint64_t>& o_marks ) -{ - fapi2::buffer<uint64_t> l_buffer; - uint64_t l_galois = 0; - auto l_confirmed = mss::states::NO; - - o_marks.clear(); - - for (uint64_t l_rank = 0; l_rank < MAX_MRANK_PER_PORT; ++l_rank) - { - FAPI_TRY( get_hwms(i_target, l_rank, l_galois, l_confirmed) ); - - if (l_confirmed == mss::states::YES) - { - o_marks.push_back(l_galois); - } - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Query Firmware Marks -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_marks vector of Galois codes of any marks set -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// @note no rank information is returned -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_fw_marks( const fapi2::Target<T>& i_target, - std::vector<uint64_t>& o_marks ) -{ - fapi2::buffer<uint64_t> l_buffer; - uint64_t l_galois = 0; - auto l_type = mss::ecc::fwms::mark_type::CHIP; - auto l_region = mss::ecc::fwms::mark_region::UNIVERSAL; - mss::mcbist::address l_address; - - o_marks.clear(); - - for (uint64_t l_rank = 0; l_rank < MAX_MRANK_PER_PORT; ++l_rank) - { - FAPI_TRY( get_fwms(i_target, l_rank, l_galois, l_type, l_region, l_address) ); - - if (l_region != mss::ecc::fwms::mark_region::DISABLED) - { - o_marks.push_back(l_galois); - } - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline NCE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline nce -/// @param[out] o_on_rce mss::YES if nce is part of an rce -/// @param[out] o_is_tce mss::YES if nce is a tce -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_nce_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address, - mss::states& o_on_rce, - mss::states& o_is_tce ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_nce_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_nce_trap::get_address(l_buffer, o_address); - mss::ecc::mainline_nce_trap::get_nce_on_rce(l_buffer, o_on_rce); - mss::ecc::mainline_nce_trap::get_nce_is_tce(l_buffer, o_is_tce); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline NCE error vector traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_galois the Galois code -/// @param[out] o_magnitude the magnitude of the error -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_nce_error_vector_trap( const fapi2::Target<T>& i_target, - uint64_t& o_galois, - uint64_t& o_magnitude ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mbs_error_vector_trap::read(i_target, l_buffer) ); - mss::ecc::mbs_error_vector_trap::get_nce_galois(i_target, l_buffer, o_galois); - mss::ecc::mbs_error_vector_trap::get_nce_magnitude(i_target, l_buffer, o_magnitude); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline TCE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline nce -/// @param[out] o_on_rce mss::YES if nce is part of an rce -/// @param[out] o_is_tce mss::YES if nce is a tce -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_tce_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address, - mss::states& o_on_rce, - mss::states& o_is_tce ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_nce_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_nce_trap::get_address(l_buffer, o_address); - mss::ecc::mainline_nce_trap::get_nce_on_rce(l_buffer, o_on_rce); - mss::ecc::mainline_nce_trap::get_nce_is_tce(l_buffer, o_is_tce); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline TCE error vector traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_nce_galois the Galois code -/// @param[out] o_nce_magnitude the magnitude of the error -/// @param[out] o_tce_galois the Galois code -/// @param[out] o_tce_magnitude the magnitude of the error -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_tce_error_vector_trap( const fapi2::Target<T>& i_target, - uint64_t& o_nce_galois, - uint64_t& o_nce_magnitude, - uint64_t& o_tce_galois, - uint64_t& o_tce_magnitude ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mbs_error_vector_trap::read(i_target, l_buffer) ); - mss::ecc::mbs_error_vector_trap::get_nce_galois(i_target, l_buffer, o_nce_galois); - mss::ecc::mbs_error_vector_trap::get_nce_magnitude(i_target, l_buffer, o_nce_magnitude); - mss::ecc::mbs_error_vector_trap::get_tce_galois(i_target, l_buffer, o_tce_galois); - mss::ecc::mbs_error_vector_trap::get_tce_magnitude(i_target, l_buffer, o_tce_magnitude); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline MPE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline mpe -/// @param[out] o_on_rce mss::YES if mpe is part of an rce -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_mpe_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address, - mss::states& o_on_rce ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_mpe_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_mpe_trap::get_address(l_buffer, o_address); - mss::ecc::mainline_mpe_trap::get_mpe_on_rce(l_buffer, o_on_rce); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline RCE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline rce -/// @param[out] o_nce_on_rce mss::YES if nce is part of an rce -/// @param[out] o_tce_on_rce mss::YES if tce is part of an rce -/// @param[out] o_mpe_on_rce mss::YES if mpe is part of an rce -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_rce_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address, - mss::states& o_nce_on_rce, - mss::states& o_tce_on_rce, - mss::states& o_mpe_on_rce ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_rce_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_rce_trap::get_address(l_buffer, o_address); - - FAPI_TRY( mss::ecc::mainline_nce_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_nce_trap::get_nce_on_rce(l_buffer, o_nce_on_rce); - mss::ecc::mainline_nce_trap::get_nce_is_tce(l_buffer, o_tce_on_rce); - - FAPI_TRY( mss::ecc::mainline_mpe_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_mpe_trap::get_mpe_on_rce(l_buffer, o_mpe_on_rce); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline UE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline ue -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_ue_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_ue_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_ue_trap::get_address(l_buffer, o_address); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Mainline AUE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the trap address of the last mainline aue -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_aue_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mainline_aue_trap::read(i_target, l_buffer) ); - mss::ecc::mainline_aue_trap::get_address(l_buffer, o_address); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get IMPE address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_chipmark the mark location (Galois code) of the last mark placed -/// @param[out] o_rank the rank of the last mark placed -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_impe_addr_trap( const fapi2::Target<T>& i_target, - uint64_t& o_chipmark, - uint64_t& o_rank ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mark_shadow_reg::read(i_target, l_buffer) ); - mss::ecc::mark_shadow_reg::get_chipmark(l_buffer, o_chipmark); - mss::ecc::mark_shadow_reg::get_rank(l_buffer, o_rank); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Maint Current address traps -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_address the last address executed -/// @param[out] o_port_trap port value if MCBCFGQ_cfg_current_addr_trap_update_dis == 0 -/// @param[out] o_dimm_trap dimm value if MCBCFGQ_cfg_current_addr_trap_update_dis == 0 -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_maint_current_addr_trap( const fapi2::Target<T>& i_target, - mss::mcbist::address& o_address, - uint64_t& o_port_trap, - uint64_t& o_dimm_trap ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::maint_current_trap::read(i_target, l_buffer) ); - mss::ecc::maint_current_trap::get_address(l_buffer, o_address); - mss::ecc::maint_current_trap::get_port(l_buffer, o_port_trap); - mss::ecc::maint_current_trap::get_dimm(l_buffer, o_dimm_trap); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Per Symbol Error Counts -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_error_counts vector of symbol error counts -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode get_per_symbol_error_counts( const fapi2::Target<T>& i_target, - std::vector<uint64_t>& o_error_counts ) -{ - fapi2::buffer<uint64_t> l_buffer; - uint64_t l_count = 0; - o_error_counts.clear(); - - for (uint64_t l_index = 0; l_index < TT::NUM_MBSSYM_REGS; ++l_index) - { - FAPI_TRY( mss::ecc::modal_symbol_count::read(i_target, l_index, l_buffer) ); - - for (uint64_t l_symbol = 0; l_symbol < TT::MODAL_SYMBOL_COUNTERS_PER_REG; ++l_symbol) - { - l_count = 0; - mss::ecc::modal_symbol_count::get_count(l_buffer, l_symbol, l_count); - o_error_counts.push_back(l_count); - } - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Intermittent NCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of intermittent NCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_intermittent_nce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg0::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg0::get_intermittent_ce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Soft NCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of soft NCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_soft_nce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg0::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg0::get_soft_ce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Hard NCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of hard NCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_hard_nce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg0::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg0::get_hard_ce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Intermittent MCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of intermittent MCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_intermittent_mce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg0::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg0::get_intermittent_mce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Soft MCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of soft MCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_soft_mce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg0::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg0::get_soft_mce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get Hard MCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of hard MCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_hard_mce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg1::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg1::get_hard_mce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get ICE (IMPE) error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of ICE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_ice_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg1::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg1::get_ice_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get UE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of UE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_ue_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg1::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg1::get_ue_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get AUE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of AUE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_aue_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg1::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg1::get_aue_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get RCE error count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_count count of RCE events -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_rce_count( const fapi2::Target<T>& i_target, - uint64_t& o_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::read_error_count_reg1::read(i_target, l_buffer) ); - mss::ecc::read_error_count_reg1::get_rce_count(l_buffer, o_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Get MCE symbol count -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @param[out] o_symbol0_count count of symbol 0 errors -/// @param[out] o_symbol1_count count of symbol 1 errors -/// @param[out] o_symbol2_count count of symbol 2 errors -/// @param[out] o_symbol3_count count of symbol 3 errors -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode get_mce_symbol_count( const fapi2::Target<T>& i_target, - uint64_t& o_symbol0_count, - uint64_t& o_symbol1_count, - uint64_t& o_symbol2_count, - uint64_t& o_symbol3_count ) -{ - fapi2::buffer<uint64_t> l_buffer; - - FAPI_TRY( mss::ecc::mark_symbol_count_reg::read(i_target, l_buffer) ); - mss::ecc::mark_symbol_count_reg::get_symbol0_count(l_buffer, o_symbol0_count); - mss::ecc::mark_symbol_count_reg::get_symbol1_count(l_buffer, o_symbol1_count); - mss::ecc::mark_symbol_count_reg::get_symbol2_count(l_buffer, o_symbol2_count); - mss::ecc::mark_symbol_count_reg::get_symbol3_count(l_buffer, o_symbol3_count); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Clear all MAINT.ECC counters -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the fapi2 target -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode clear_all_counters( const fapi2::Target<T>& i_target ) -{ - return ( mss::mcbist::reset_errors(i_target) ); -} - - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H deleted file mode 100644 index 7be0ef146..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H +++ /dev/null @@ -1,331 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file ecc_traits.H -/// @brief Traits class for the MC ECC syndrome registers -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_ECC_TRAITS_H_ -#define _MSS_ECC_TRAITS_H_ - -#include <p9_mc_scom_addresses.H> -#include <p9_mc_scom_addresses_fld.H> -#include <lib/shared/mss_const.H> - -namespace mss -{ - -/// -/// @class eccTraits -/// @brief a collection of traits associated with the MC ECC interface -/// @tparam T fapi2::TargetType representing the memory controller -/// -template< fapi2::TargetType T > -class eccTraits; - -/// -/// @class eccTraits -/// @brief a collection of traits associated with the Centaur MC ECC interface -/// -template<> -class eccTraits<fapi2::TARGET_TYPE_MBA> -{ -}; - -/// -/// @class eccTraits -/// @brief a collection of traits associated with the Nimbus MC ECC interface -/// -template<> -class eccTraits<fapi2::TARGET_TYPE_MCA> -{ - public: - // MCA ECC registers - must be 64 bits. - static constexpr uint64_t HARDWARE_MS0_REG = MCA_HWMS0; - static constexpr uint64_t HARDWARE_MS1_REG = MCA_WDF_HWMS1; - static constexpr uint64_t HARDWARE_MS2_REG = MCA_HWMS2; - static constexpr uint64_t HARDWARE_MS3_REG = MCA_HWMS3; - static constexpr uint64_t HARDWARE_MS4_REG = MCA_HWMS4; - static constexpr uint64_t HARDWARE_MS5_REG = MCA_HWMS5; - static constexpr uint64_t HARDWARE_MS6_REG = MCA_HWMS6; - static constexpr uint64_t HARDWARE_MS7_REG = MCA_HWMS7; - static constexpr uint64_t FIRMWARE_MS0_REG = MCA_FWMS0; - static constexpr uint64_t FIRMWARE_MS1_REG = MCA_WREITE_FWMS1; - static constexpr uint64_t FIRMWARE_MS2_REG = MCA_FWMS2; - static constexpr uint64_t FIRMWARE_MS3_REG = MCA_FWMS3; - static constexpr uint64_t FIRMWARE_MS4_REG = MCA_FWMS4; - static constexpr uint64_t FIRMWARE_MS5_REG = MCA_FWMS5; - static constexpr uint64_t FIRMWARE_MS6_REG = MCA_FWMS6; - static constexpr uint64_t FIRMWARE_MS7_REG = MCA_FWMS7; - static constexpr uint64_t MARK_SHADOW_REG = MCA_MSR; - - // MCBIST ECC registers - Register API uses an MCA target instead - // of MCBIST since MCA's relative position is needed to find - // correct reg+field - constexpr static const uint64_t MAINLINE_NCE_REGS[] = - { - MCBIST_MBNCER0Q, - MCBIST_MBNCER1Q, - MCBIST_MBNCER2Q, - MCBIST_MBNCER3Q, - }; - - constexpr static const uint64_t MAINLINE_RCE_REGS[] = - { - MCBIST_MBRCER0Q, - MCBIST_MBRCER1Q, - MCBIST_MBRCER2Q, - MCBIST_MBRCER3Q - }; - - constexpr static const uint64_t MAINLINE_MPE_REGS[] = - { - MCBIST_MBMPER0Q, - MCBIST_MBMPER1Q, - MCBIST_MBMPER2Q, - MCBIST_MBMPER3Q - }; - - constexpr static const uint64_t MAINLINE_UE_REGS[] = - { - MCBIST_MBUER0Q, - MCBIST_MBUER1Q, - MCBIST_MBUER2Q, - MCBIST_MBUER3Q - }; - - constexpr static const uint64_t MAINLINE_AUE_REGS[] = - { - MCBIST_MBAUER0Q, - MCBIST_MBAUER1Q, - MCBIST_MBAUER2Q, - MCBIST_MBAUER3Q - }; - - // Note that these registers store info for a pair of ports - // (thus the duplication) - constexpr static const uint64_t ERROR_VECTOR_REGS[] = - { - MCBIST_MBSEVR0Q, - MCBIST_MBSEVR0Q, - MCBIST_MBSEVR1Q, - MCBIST_MBSEVR1Q - }; - - // Fields, can be any size. - enum - { - HARDWARE_MS_CHIPMARK = MCA_HWMS0_CHIPMARK, - HARDWARE_MS_CHIPMARK_LEN = MCA_HWMS0_CHIPMARK_LEN, - HARDWARE_MS_CONFIRMED = MCA_HWMS0_CONFIRMED, - HARDWARE_MS_EXIT1 = MCA_HWMS0_EXIT_1, - FIRMWARE_MS_MARK = MCA_FWMS0_MARK, - FIRMWARE_MS_MARK_LEN = MCA_FWMS0_MARK_LEN, - FIRMWARE_MS_TYPE = MCA_FWMS0_TYPE, - FIRMWARE_MS_REGION = MCA_FWMS0_REGION, - FIRMWARE_MS_REGION_LEN = MCA_FWMS0_REGION_LEN, - FIRMWARE_MS_ADDRESS = MCA_FWMS0_ADDRESS, - FIRMWARE_MS_ADDRESS_LEN = MCA_FWMS0_ADDRESS_LEN, - FIRMWARE_MS_EXIT1 = MCA_FWMS0_EXIT_1, - NCE_ADDR_TRAP = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP, - NCE_ADDR_TRAP_LEN = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN, - NCE_ON_RCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE, - NCE_IS_TCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE, - RCE_ADDR_TRAP = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP, - RCE_ADDR_TRAP_LEN = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN, - MPE_ADDR_TRAP = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP, - MPE_ADDR_TRAP_LEN = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN, - MPE_ON_RCE = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE, - UE_ADDR_TRAP = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP, - UE_ADDR_TRAP_LEN = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN, - AUE_ADDR_TRAP = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP, - AUE_ADDR_TRAP_LEN = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN, - P0_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD, - P0_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN, - P0_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD, - P0_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, - P0_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD, - P0_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN, - P0_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD, - P0_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, - P1_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD, - P1_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN, - P1_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD, - P1_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, - P1_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD, - P1_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN, - P1_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD, - P1_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, - CURRENT_ADDR_TRAP = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP, - CURRENT_ADDR_TRAP_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN, - CURRENT_PORT = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP, - CURRENT_PORT_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN, - CURRENT_DIMM = MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP, - SHADOW_CHIPMARK = MCA_MSR_CHIPMARK, - SHADOW_CHIPMARK_LEN = MCA_MSR_CHIPMARK_LEN, - SHADOW_RANK = MCA_MSR_RANK, - SHADOW_RANK_LEN = MCA_MSR_RANK_LEN, - - }; - - // Symbol to Galois code mapping table - // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store - constexpr static const uint8_t symbol2galois[] = - { - 0x80, 0xa0, 0x90, 0xf0, - 0x08, 0x0a, 0x09, 0x0f, - 0x98, 0xda, 0xb9, 0x7f, - 0x91, 0xd7, 0xb2, 0x78, - 0x28, 0xea, 0x49, 0x9f, - 0x9a, 0xd4, 0xbd, 0x76, - 0x60, 0xb0, 0xc0, 0x20, - 0x06, 0x0b, 0x0c, 0x02, - 0xc6, 0xfb, 0x1c, 0x42, - 0xca, 0xf4, 0x1d, 0x46, - 0xd6, 0x8b, 0x3c, 0xc2, - 0xcb, 0xf3, 0x1f, 0x4e, - 0xe0, 0x10, 0x50, 0xd0, - 0x0e, 0x01, 0x05, 0x0d, - 0x5e, 0x21, 0xa5, 0x3d, - 0x5b, 0x23, 0xaf, 0x3e, - 0xfe, 0x61, 0x75, 0x5d, - 0x51, 0x27, 0xa2, 0x38 - }; - - // Symbol to DQ index mapping table - // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store - constexpr static const uint8_t symbol2dq[] = - { - 71, 70, 69, 68, - 67, 66, 65, 64, - 63, 62, 61, 60, - 55, 54, 53, 52, - 47, 46, 45, 44, - 39, 38, 37, 36, - 31, 30, 29, 28, - 23, 22, 21, 20, - 15, 14, 13, 12, - 7, 6, 5, 4, - 59, 58, 57, 56, - 51, 50, 49, 48, - 43, 42, 41, 40, - 35, 34, 33, 32, - 27, 26, 25, 24, - 19, 18, 17, 16, - 11, 10, 9, 8, - 3, 2, 1, 0 - }; - -}; - -/// -/// @class eccTraits -/// @brief a collection of traits associated with the Nimbus MC ECC interface -/// -template<> -class eccTraits<fapi2::TARGET_TYPE_MCBIST> -{ - public: - // MCBIST ECC registers - must be 64 bits. - static constexpr uint64_t READ_ERROR_COUNT_REG0 = MCBIST_MBSEC0Q; - static constexpr uint64_t READ_ERROR_COUNT_REG1 = MCBIST_MBSEC1Q; - static constexpr uint64_t MARK_SYMBOL_COUNT_REG = MCBIST_MBSMSECQ; - static constexpr uint64_t MODAL_SYM_COUNT0_REG = MCBIST_MBSSYMEC0Q; - static constexpr uint64_t MODAL_SYM_COUNT1_REG = MCBIST_MBSSYMEC1Q; - static constexpr uint64_t MODAL_SYM_COUNT2_REG = MCBIST_MBSSYMEC2Q; - static constexpr uint64_t MODAL_SYM_COUNT3_REG = MCBIST_MBSSYMEC3Q; - static constexpr uint64_t MODAL_SYM_COUNT4_REG = MCBIST_MBSSYMEC4Q; - static constexpr uint64_t MODAL_SYM_COUNT5_REG = MCBIST_MBSSYMEC5Q; - static constexpr uint64_t MODAL_SYM_COUNT6_REG = MCBIST_MBSSYMEC6Q; - static constexpr uint64_t MODAL_SYM_COUNT7_REG = MCBIST_MBSSYMEC7Q; - static constexpr uint64_t MODAL_SYM_COUNT8_REG = MCBIST_MBSSYMEC8Q; - - // Stores the symbol counter registers in a vector for easier access for MCBIST - static const std::vector<uint64_t> SYMBOL_COUNT_REG; - - // Fields, can be any size. - enum - { - INTERMITTENT_CE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT, - INTERMITTENT_CE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN, - SOFT_CE_COUNT = MCBIST_MBSEC0Q_SOFT_CE_COUNT, - SOFT_CE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN, - HARD_CE_COUNT = MCBIST_MBSEC0Q_HARD_CE_COUNT, - HARD_CE_COUNT_LEN = MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN, - INTERMITTENT_MCE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT, - INTERMITTENT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN, - SOFT_MCE_COUNT = MCBIST_MBSEC0Q_SOFT_MCE_COUNT, - SOFT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN, - HARD_MCE_COUNT = MCBIST_MBSEC1Q_HARD_MCE_COUNT, - HARD_MCE_COUNT_LEN = MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN, - ICE_COUNT = MCBIST_MBSEC1Q_ICE_COUNT, - ICE_COUNT_LEN = MCBIST_MBSEC1Q_ICE_COUNT_LEN, - UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, - UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, - AUE_COUNT = MCBIST_MBSEC1Q_AUE, - AUE_COUNT_LEN = MCBIST_MBSEC1Q_AUE_LEN, - RCE_COUNT = MCBIST_MBSEC1Q_RCE_COUNT, - RCE_COUNT_LEN = MCBIST_MBSEC1Q_RCE_COUNT_LEN, - SYMBOL0_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT, - SYMBOL0_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN, - SYMBOL1_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT, - SYMBOL1_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN, - SYMBOL2_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT, - SYMBOL2_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN, - SYMBOL3_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT, - SYMBOL3_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN, - MODAL_SYMBOL_COUNTER_00 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00, - MODAL_SYMBOL_COUNTER_00_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN, - MODAL_SYMBOL_COUNTER_01 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01, - MODAL_SYMBOL_COUNTER_01_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN, - MODAL_SYMBOL_COUNTER_02 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02, - MODAL_SYMBOL_COUNTER_02_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN, - MODAL_SYMBOL_COUNTER_03 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03, - MODAL_SYMBOL_COUNTER_03_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN, - MODAL_SYMBOL_COUNTER_04 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04, - MODAL_SYMBOL_COUNTER_04_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN, - MODAL_SYMBOL_COUNTER_05 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05, - MODAL_SYMBOL_COUNTER_05_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN, - MODAL_SYMBOL_COUNTER_06 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06, - MODAL_SYMBOL_COUNTER_06_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN, - MODAL_SYMBOL_COUNTER_07 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07, - MODAL_SYMBOL_COUNTER_07_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN, - - // and a couple constants - NUM_MBSSYM_REGS = 9, - MODAL_SYMBOL_COUNTERS_PER_REG = 8, - }; - -}; - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.C b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.C index 196e6d509..3fd43e6a3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.C @@ -22,3 +22,49 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits_nimbus.C +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/shared/mss_const.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/ecc/ecc_traits_nimbus.H> + +namespace mss +{ + +// we need these declarations here in order for the linker to see the definitions +// in the eccTraits class +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::MAINLINE_NCE_REGS[]; +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::MAINLINE_RCE_REGS[]; +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::MAINLINE_MPE_REGS[]; +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::MAINLINE_UE_REGS[]; +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::MAINLINE_AUE_REGS[]; +constexpr const uint64_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::ERROR_VECTOR_REGS[]; + +constexpr const uint8_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::symbol2galois[]; +constexpr const uint8_t eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA>::symbol2dq[]; + +// Definition of the symbol error count registers +const std::vector< uint64_t > eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST>::SYMBOL_COUNT_REG = +{ + MCBIST_MBSSYMEC0Q, + MCBIST_MBSSYMEC1Q, + MCBIST_MBSSYMEC2Q, + MCBIST_MBSSYMEC3Q, + MCBIST_MBSSYMEC4Q, + MCBIST_MBSSYMEC5Q, + MCBIST_MBSSYMEC6Q, + MCBIST_MBSSYMEC7Q, + MCBIST_MBSSYMEC8Q, +}; + +} // close namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.H index 55acc5ffc..6a13b0c41 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/ecc_traits_nimbus.H @@ -22,3 +22,322 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file ecc_traits_nimbus.H +/// @brief Traits class for the MC ECC syndrome registers +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_ECC_TRAITS_NIMBUS_H_ +#define _MSS_ECC_TRAITS_NIMBUS_H_ + +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> +#include <generic/memory/lib/ecc/ecc_traits.H> + +namespace mss +{ + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Nimbus MC ECC interface +/// +template<> +class eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> +{ + public: + // MCA ECC registers - must be 64 bits. + static constexpr uint64_t HARDWARE_MS0_REG = MCA_HWMS0; + static constexpr uint64_t HARDWARE_MS1_REG = MCA_WDF_HWMS1; + static constexpr uint64_t HARDWARE_MS2_REG = MCA_HWMS2; + static constexpr uint64_t HARDWARE_MS3_REG = MCA_HWMS3; + static constexpr uint64_t HARDWARE_MS4_REG = MCA_HWMS4; + static constexpr uint64_t HARDWARE_MS5_REG = MCA_HWMS5; + static constexpr uint64_t HARDWARE_MS6_REG = MCA_HWMS6; + static constexpr uint64_t HARDWARE_MS7_REG = MCA_HWMS7; + static constexpr uint64_t FIRMWARE_MS0_REG = MCA_FWMS0; + static constexpr uint64_t FIRMWARE_MS1_REG = MCA_WREITE_FWMS1; + static constexpr uint64_t FIRMWARE_MS2_REG = MCA_FWMS2; + static constexpr uint64_t FIRMWARE_MS3_REG = MCA_FWMS3; + static constexpr uint64_t FIRMWARE_MS4_REG = MCA_FWMS4; + static constexpr uint64_t FIRMWARE_MS5_REG = MCA_FWMS5; + static constexpr uint64_t FIRMWARE_MS6_REG = MCA_FWMS6; + static constexpr uint64_t FIRMWARE_MS7_REG = MCA_FWMS7; + static constexpr uint64_t MARK_SHADOW_REG = MCA_MSR; + static constexpr uint64_t ECC_MAX_MRANK_PER_PORT = MAX_MRANK_PER_PORT; + static constexpr uint64_t ECC_MAX_DQ_BITS = MAX_DQ_BITS; + static constexpr uint64_t ECC_MAX_SYMBOLS = MAX_DQ_BITS; + + // MCBIST ECC registers - Register API uses an MCA target instead + // of MCBIST since MCA's relative position is needed to find + // correct reg+field + constexpr static const uint64_t MAINLINE_NCE_REGS[] = + { + MCBIST_MBNCER0Q, + MCBIST_MBNCER1Q, + MCBIST_MBNCER2Q, + MCBIST_MBNCER3Q, + }; + + constexpr static const uint64_t MAINLINE_RCE_REGS[] = + { + MCBIST_MBRCER0Q, + MCBIST_MBRCER1Q, + MCBIST_MBRCER2Q, + MCBIST_MBRCER3Q + }; + + constexpr static const uint64_t MAINLINE_MPE_REGS[] = + { + MCBIST_MBMPER0Q, + MCBIST_MBMPER1Q, + MCBIST_MBMPER2Q, + MCBIST_MBMPER3Q + }; + + constexpr static const uint64_t MAINLINE_UE_REGS[] = + { + MCBIST_MBUER0Q, + MCBIST_MBUER1Q, + MCBIST_MBUER2Q, + MCBIST_MBUER3Q + }; + + constexpr static const uint64_t MAINLINE_AUE_REGS[] = + { + MCBIST_MBAUER0Q, + MCBIST_MBAUER1Q, + MCBIST_MBAUER2Q, + MCBIST_MBAUER3Q + }; + + // Note that these registers store info for a pair of ports + // (thus the duplication) + constexpr static const uint64_t ERROR_VECTOR_REGS[] = + { + MCBIST_MBSEVR0Q, + MCBIST_MBSEVR0Q, + MCBIST_MBSEVR1Q, + MCBIST_MBSEVR1Q + }; + + // Fields, can be any size. + enum + { + HARDWARE_MS_CHIPMARK = MCA_HWMS0_CHIPMARK, + HARDWARE_MS_CHIPMARK_LEN = MCA_HWMS0_CHIPMARK_LEN, + HARDWARE_MS_CONFIRMED = MCA_HWMS0_CONFIRMED, + HARDWARE_MS_EXIT1 = MCA_HWMS0_EXIT_1, + FIRMWARE_MS_MARK = MCA_FWMS0_MARK, + FIRMWARE_MS_MARK_LEN = MCA_FWMS0_MARK_LEN, + FIRMWARE_MS_TYPE = MCA_FWMS0_TYPE, + FIRMWARE_MS_REGION = MCA_FWMS0_REGION, + FIRMWARE_MS_REGION_LEN = MCA_FWMS0_REGION_LEN, + FIRMWARE_MS_ADDRESS = MCA_FWMS0_ADDRESS, + FIRMWARE_MS_ADDRESS_LEN = MCA_FWMS0_ADDRESS_LEN, + FIRMWARE_MS_EXIT1 = MCA_FWMS0_EXIT_1, + NCE_ADDR_TRAP = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP, + NCE_ADDR_TRAP_LEN = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ADDR_TRAP_LEN, + NCE_ON_RCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE, + NCE_IS_TCE = MCBIST_MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE, + RCE_ADDR_TRAP = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP, + RCE_ADDR_TRAP_LEN = MCBIST_MBRCER0Q_PORT_0_MAINLINE_RCE_ADDR_TRAP_LEN, + MPE_ADDR_TRAP = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP, + MPE_ADDR_TRAP_LEN = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ADDR_TRAP_LEN, + MPE_ON_RCE = MCBIST_MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE, + UE_ADDR_TRAP = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP, + UE_ADDR_TRAP_LEN = MCBIST_MBUER0Q_PORT_0_MAINLINE_UE_ADDR_TRAP_LEN, + AUE_ADDR_TRAP = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP, + AUE_ADDR_TRAP_LEN = MCBIST_MBAUER0Q_PORT_0_MAINLINE_AUE_ADDR_TRAP_LEN, + P0_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD, + P0_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_GALOIS_FIELD_LEN, + P0_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD, + P0_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, + P0_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD, + P0_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_GALOIS_FIELD_LEN, + P0_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD, + P0_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_0_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, + P1_NCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD, + P1_NCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_GALOIS_FIELD_LEN, + P1_NCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD, + P1_NCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_NCE_MAGNITUDE_FIELD_LEN, + P1_TCE_GALOIS = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD, + P1_TCE_GALOIS_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_GALOIS_FIELD_LEN, + P1_TCE_MAGNITUDE = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD, + P1_TCE_MAGNITUDE_LEN = MCBIST_MBSEVR0Q_PORT_1_MAINLINE_TCE_MAGNITUDE_FIELD_LEN, + CURRENT_ADDR_TRAP = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP, + CURRENT_ADDR_TRAP_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_ADDR_TRAP_LEN, + CURRENT_PORT = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP, + CURRENT_PORT_LEN = MCBIST_MCBMCATQ_CFG_CURRENT_PORT_TRAP_LEN, + CURRENT_DIMM = MCBIST_MCBMCATQ_CFG_CURRENT_DIMM_TRAP, + SHADOW_CHIPMARK = MCA_MSR_CHIPMARK, + SHADOW_CHIPMARK_LEN = MCA_MSR_CHIPMARK_LEN, + SHADOW_RANK = MCA_MSR_RANK, + SHADOW_RANK_LEN = MCA_MSR_RANK_LEN, + + // Address trap format + TRAP_ADDRESS_PORT = 0, + TRAP_ADDRESS_PORT_LEN = 2, + TRAP_ADDRESS_DIMM = 2, + TRAP_ADDRESS_DIMM_LEN = 1, + TRAP_ADDRESS_MRANK = 3, + TRAP_ADDRESS_MRANK_LEN = 2, + TRAP_ADDRESS_SRANK = 5, + TRAP_ADDRESS_SRANK_LEN = 3, + TRAP_ADDRESS_ROW = 8, + TRAP_ADDRESS_ROW_LEN = 18, + TRAP_ADDRESS_COL = 26, + TRAP_ADDRESS_COL_LEN = 7, + TRAP_ADDRESS_BANK = 33, + TRAP_ADDRESS_BANK_LEN = 3, + TRAP_ADDRESS_BANK_GROUP = 36, + TRAP_ADDRESS_BANK_GROUP_LEN = 2, + + TRAP_ADDRESS = 0, + TRAP_ADDRESS_LEN = 38, + }; + + // Symbol to Galois code mapping table + // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store + constexpr static const uint8_t symbol2galois[] = + { + 0x80, 0xa0, 0x90, 0xf0, + 0x08, 0x0a, 0x09, 0x0f, + 0x98, 0xda, 0xb9, 0x7f, + 0x91, 0xd7, 0xb2, 0x78, + 0x28, 0xea, 0x49, 0x9f, + 0x9a, 0xd4, 0xbd, 0x76, + 0x60, 0xb0, 0xc0, 0x20, + 0x06, 0x0b, 0x0c, 0x02, + 0xc6, 0xfb, 0x1c, 0x42, + 0xca, 0xf4, 0x1d, 0x46, + 0xd6, 0x8b, 0x3c, 0xc2, + 0xcb, 0xf3, 0x1f, 0x4e, + 0xe0, 0x10, 0x50, 0xd0, + 0x0e, 0x01, 0x05, 0x0d, + 0x5e, 0x21, 0xa5, 0x3d, + 0x5b, 0x23, 0xaf, 0x3e, + 0xfe, 0x61, 0x75, 0x5d, + 0x51, 0x27, 0xa2, 0x38 + }; + + // Symbol to DQ index mapping table + // Reference: Nimbus workbook, Section 13.1.6.2: Firmware Mark Store + constexpr static const uint8_t symbol2dq[] = + { + 71, 70, 69, 68, + 67, 66, 65, 64, + 63, 62, 61, 60, + 55, 54, 53, 52, + 47, 46, 45, 44, + 39, 38, 37, 36, + 31, 30, 29, 28, + 23, 22, 21, 20, + 15, 14, 13, 12, + 7, 6, 5, 4, + 59, 58, 57, 56, + 51, 50, 49, 48, + 43, 42, 41, 40, + 35, 34, 33, 32, + 27, 26, 25, 24, + 19, 18, 17, 16, + 11, 10, 9, 8, + 3, 2, 1, 0 + }; + +}; + +/// +/// @class eccTraits +/// @brief a collection of traits associated with the Nimbus MC ECC interface +/// +template<> +class eccTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST> +{ + public: + // MCBIST ECC registers - must be 64 bits. + static constexpr uint64_t READ_ERROR_COUNT_REG0 = MCBIST_MBSEC0Q; + static constexpr uint64_t READ_ERROR_COUNT_REG1 = MCBIST_MBSEC1Q; + static constexpr uint64_t MARK_SYMBOL_COUNT_REG = MCBIST_MBSMSECQ; + static constexpr uint64_t MODAL_SYM_COUNT0_REG = MCBIST_MBSSYMEC0Q; + static constexpr uint64_t MODAL_SYM_COUNT1_REG = MCBIST_MBSSYMEC1Q; + static constexpr uint64_t MODAL_SYM_COUNT2_REG = MCBIST_MBSSYMEC2Q; + static constexpr uint64_t MODAL_SYM_COUNT3_REG = MCBIST_MBSSYMEC3Q; + static constexpr uint64_t MODAL_SYM_COUNT4_REG = MCBIST_MBSSYMEC4Q; + static constexpr uint64_t MODAL_SYM_COUNT5_REG = MCBIST_MBSSYMEC5Q; + static constexpr uint64_t MODAL_SYM_COUNT6_REG = MCBIST_MBSSYMEC6Q; + static constexpr uint64_t MODAL_SYM_COUNT7_REG = MCBIST_MBSSYMEC7Q; + static constexpr uint64_t MODAL_SYM_COUNT8_REG = MCBIST_MBSSYMEC8Q; + static constexpr uint64_t MPE_ADDR_TRAP_REG = MCBIST_MCBMCATQ; + static constexpr uint64_t ECC_MAX_MRANK_PER_PORT = MAX_MRANK_PER_PORT; + static constexpr uint64_t ECC_MAX_DQ_BITS = MAX_DQ_BITS; + static constexpr uint64_t ECC_MAX_SYMBOLS = MAX_DQ_BITS; + + // Stores the symbol counter registers in a vector for easier access for MCBIST + static constexpr uint64_t REQUIRED_NUMBER_OF_SYMBOL_REGS = 9; + static const std::vector<uint64_t> SYMBOL_COUNT_REG; + + // Fields, can be any size. + enum + { + INTERMITTENT_CE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT, + INTERMITTENT_CE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_CE_COUNT_LEN, + SOFT_CE_COUNT = MCBIST_MBSEC0Q_SOFT_CE_COUNT, + SOFT_CE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_CE_COUNT_LEN, + HARD_CE_COUNT = MCBIST_MBSEC0Q_HARD_CE_COUNT, + HARD_CE_COUNT_LEN = MCBIST_MBSEC0Q_HARD_CE_COUNT_LEN, + INTERMITTENT_MCE_COUNT = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT, + INTERMITTENT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_INTERMITTENT_MCE_COUNT_LEN, + SOFT_MCE_COUNT = MCBIST_MBSEC0Q_SOFT_MCE_COUNT, + SOFT_MCE_COUNT_LEN = MCBIST_MBSEC0Q_SOFT_MCE_COUNT_LEN, + HARD_MCE_COUNT = MCBIST_MBSEC1Q_HARD_MCE_COUNT, + HARD_MCE_COUNT_LEN = MCBIST_MBSEC1Q_HARD_MCE_COUNT_LEN, + ICE_COUNT = MCBIST_MBSEC1Q_ICE_COUNT, + ICE_COUNT_LEN = MCBIST_MBSEC1Q_ICE_COUNT_LEN, + UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, + UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, + AUE_COUNT = MCBIST_MBSEC1Q_AUE, + AUE_COUNT_LEN = MCBIST_MBSEC1Q_AUE_LEN, + RCE_COUNT = MCBIST_MBSEC1Q_RCE_COUNT, + RCE_COUNT_LEN = MCBIST_MBSEC1Q_RCE_COUNT_LEN, + SYMBOL0_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT, + SYMBOL0_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL0_COUNT_LEN, + SYMBOL1_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT, + SYMBOL1_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL1_COUNT_LEN, + SYMBOL2_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT, + SYMBOL2_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL2_COUNT_LEN, + SYMBOL3_COUNT = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT, + SYMBOL3_COUNT_LEN = MCBIST_MBSMSECQ_MCE_SYMBOL3_COUNT_LEN, + MODAL_SYMBOL_COUNTER_00 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00, + MODAL_SYMBOL_COUNTER_00_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_00_LEN, + MODAL_SYMBOL_COUNTER_01 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01, + MODAL_SYMBOL_COUNTER_01_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_01_LEN, + MODAL_SYMBOL_COUNTER_02 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02, + MODAL_SYMBOL_COUNTER_02_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_02_LEN, + MODAL_SYMBOL_COUNTER_03 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03, + MODAL_SYMBOL_COUNTER_03_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_03_LEN, + MODAL_SYMBOL_COUNTER_04 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04, + MODAL_SYMBOL_COUNTER_04_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_04_LEN, + MODAL_SYMBOL_COUNTER_05 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05, + MODAL_SYMBOL_COUNTER_05_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_05_LEN, + MODAL_SYMBOL_COUNTER_06 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06, + MODAL_SYMBOL_COUNTER_06_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_06_LEN, + MODAL_SYMBOL_COUNTER_07 = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07, + MODAL_SYMBOL_COUNTER_07_LEN = MCBIST_MBSSYMEC0Q_MODAL_SYMBOL_COUNTER_07_LEN, + + // and a couple constants + NUM_MBSSYM_REGS = 9, + MODAL_SYMBOL_COUNTERS_PER_REG = 8, + }; + +}; + +} // close namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H deleted file mode 100644 index c27603b6b..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H +++ /dev/null @@ -1,619 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/fw_mark_store.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file fw_mark_store.H -/// @brief Subroutines for the MC firmware mark store registers -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_FW_MARK_STORE_H_ -#define _MSS_FW_MARK_STORE_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <lib/ecc/ecc_traits.H> -#include <lib/shared/mss_const.H> - -namespace mss -{ - -namespace ecc -{ - -namespace fwms -{ - -/// -/// @brief chip mark type enums -/// -enum mark_type -{ - SYMBOL = 1, - CHIP = 0 -}; - -/// -/// @brief Chip Mark Region. Used for region field values in the FWMS regs -/// -enum mark_region -{ - DISABLED = 0b000, - RESERVED = 0b001, - BANK = 0b010, - BANKGROUP = 0b011, - SRANK = 0b100, - MRANK = 0b101, - DIMM = 0b110, - UNIVERSAL = 0b111 -}; - -/// -/// @brief Read Firmware Mark Store (FWMS) register -/// @tparam R master rank number -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read_rank( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); - FAPI_TRY( mss::getScom(i_target, (TT::FIRMWARE_MS0_REG + R), o_data) ); - FAPI_INF("read_rank<%d>: 0x%016lx", R, o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<0>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<1>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<2>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<3>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank4( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<4>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank5( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<5>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank6( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<6>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) rank 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank7( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<7>(i_target, o_data) ); -} - -/// -/// @brief Read Firmware Mark Store (FWMS) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_rank the master rank index -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - fapi2::buffer<uint64_t>& o_data ) -{ - switch (i_rank) - { - case(0): - return ( read_rank0(i_target, o_data) ); - - case(1): - return ( read_rank1(i_target, o_data) ); - - case(2): - return ( read_rank2(i_target, o_data) ); - - case(3): - return ( read_rank3(i_target, o_data) ); - - case(4): - return ( read_rank4(i_target, o_data) ); - - case(5): - return ( read_rank5(i_target, o_data) ); - - case(6): - return ( read_rank6(i_target, o_data) ); - - case(7): - return ( read_rank7(i_target, o_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_RANK_PASSED() - .set_RANK(i_rank) - .set_TARGET(i_target) - .set_FUNCTION(FWMS_READ), - "%s Invalid rank passed to fwms::ecc::read (%d)", - mss::c_str(i_target), - i_rank); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write Firmware Mark Store (FWMS) register -/// @tparam R master rank number -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write_rank( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); - FAPI_TRY( mss::putScom(i_target, (TT::FIRMWARE_MS0_REG + R), i_data) ); - FAPI_INF("write_rank<%d>: 0x%016lx", R, i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<0>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<1>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<2>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<3>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank4( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<4>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank5( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<5>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank6( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<6>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) rank 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank7( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<7>(i_target, i_data) ); -} - -/// -/// @brief Write Firmware Mark Store (FWMS) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_rank the master rank index -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_data ) -{ - switch (i_rank) - { - case(0): - return ( write_rank0(i_target, i_data) ); - - case(1): - return ( write_rank1(i_target, i_data) ); - - case(2): - return ( write_rank2(i_target, i_data) ); - - case(3): - return ( write_rank3(i_target, i_data) ); - - case(4): - return ( write_rank4(i_target, i_data) ); - - case(5): - return ( write_rank5(i_target, i_data) ); - - case(6): - return ( write_rank6(i_target, i_data) ); - - case(7): - return ( write_rank7(i_target, i_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_RANK_PASSED() - .set_RANK(i_rank) - .set_TARGET(i_target) - .set_FUNCTION(FWMS_WRITE), - "%s Invalid rank passed to fwms::ecc::write (%d)", - mss::c_str(i_target), - i_rank); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_mark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note FWMS0_MARK: mark (Galois field code) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_mark( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::FIRMWARE_MS_MARK, TT::FIRMWARE_MS_MARK_LEN>(i_value); - FAPI_INF("set_mark: 0x%02lx", i_value); -} - -/// -/// @brief get_mark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note FWMS0_MARK: mark (Galois field code) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_mark( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::FIRMWARE_MS_MARK, TT::FIRMWARE_MS_MARK_LEN>(o_value); - FAPI_INF("get_mark: 0x%02lx", o_value); -} - -/// -/// @brief set_type -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note FWMS0_TYPE: mark type -/// @note Dial enums: -/// @note SYMBOL=>0b1 -/// @note CHIP=>0b0 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_type( fapi2::buffer<uint64_t>& io_data, const mark_type i_value ) -{ - io_data.writeBit<TT::FIRMWARE_MS_TYPE>(i_value); - FAPI_INF("set_type: 0x%01lx", i_value); -} - -/// -/// @brief get_type -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note FWMS0_TYPE: mark type -/// @note Dial enums: -/// @note SYMBOL=>0b1 -/// @note CHIP=>0b0 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_type( const fapi2::buffer<uint64_t>& i_data, mark_type& o_value ) -{ - o_value = mark_type(i_data.getBit<TT::FIRMWARE_MS_TYPE>()); - FAPI_INF("get_type: 0x%01lx", o_value); -} - -/// -/// @brief set_region -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note FWMS0_REGION: Selects mark region (address range to which mark applies) -/// @note Dial enums: -/// @note DISABLED=>0b000 -/// @note RESERVED=>0b001 -/// @note BANK=>0b010 -/// @note BANKGROUP=>0b011 -/// @note SRANK=>0b100 -/// @note MRANK=>0b101 -/// @note DIMM=>0b110 -/// @note UNIVERSAL=>0b111 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_region( fapi2::buffer<uint64_t>& io_data, const mark_region i_value ) -{ - io_data.insertFromRight<TT::FIRMWARE_MS_REGION, TT::FIRMWARE_MS_REGION_LEN>(i_value); - FAPI_INF("set_region: 0x%02lx", i_value); -} - -/// -/// @brief get_region -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note FWMS0_REGION: Selects mark region (address range to which mark applies) -/// @note Dial enums: -/// @note DISABLED=>0b000 -/// @note RESERVED=>0b001 -/// @note BANK=>0b010 -/// @note BANKGROUP=>0b011 -/// @note SRANK=>0b100 -/// @note MRANK=>0b101 -/// @note DIMM=>0b110 -/// @note UNIVERSAL=>0b111 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_region( const fapi2::buffer<uint64_t>& i_data, mark_region& o_value ) -{ - uint64_t l_temp = 0; - i_data.extractToRight<TT::FIRMWARE_MS_REGION, TT::FIRMWARE_MS_REGION_LEN>(l_temp); - o_value = mark_region(l_temp); - FAPI_INF("get_region: 0x%02lx", o_value); -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - // construct fwms::address from mcbist::address - const auto l_addr = address<T>(i_address); - io_data.insert<TT::FIRMWARE_MS_ADDRESS, TT::FIRMWARE_MS_ADDRESS_LEN, TT::FIRMWARE_MS_ADDRESS>(l_addr); - FAPI_INF("set_address: 0x%016lx", uint64_t(l_addr)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - // construct fwms::address from i_data - const auto l_addr = address<T>(uint64_t(i_data)); - // construct mcbist::address from fwms::address - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -/// -/// @brief set_exit_1 -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note FWMS0_EXIT_1: When set, bypass-enabled reads using this mark will use exit 1 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_exit_1( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::FIRMWARE_MS_EXIT1>(i_state); - FAPI_INF("set_exit_1: 0x%01lx", i_state); -} - -/// -/// @brief get_exit_1 -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note FWMS0_EXIT_1: When set, bypass-enabled reads using this mark will use exit 1 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_exit_1( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::FIRMWARE_MS_EXIT1>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_exit_1: 0x%01lx", o_state); -} - -} // close namespace fwms - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H deleted file mode 100644 index 981350955..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H +++ /dev/null @@ -1,190 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/galois.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file galois.H -/// @brief Translate ECC mark Galois codes to symbol and DQ -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: HB:FSP - -#ifndef _MSS_ECC_GALOIS_H_ -#define _MSS_ECC_GALOIS_H_ - -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -/// -/// @brief Return symbol value from a given Galois code -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_galois the Galois code -/// @param[out] o_symbol symbol value represented by given Galois code -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode galois_to_symbol( const uint8_t i_galois, uint8_t& o_symbol ) -{ - const auto& l_p = std::find(TT::symbol2galois, (TT::symbol2galois + MAX_DQ_BITS), i_galois); - - FAPI_ASSERT( l_p != (TT::symbol2galois + MAX_DQ_BITS), - fapi2::MSS_INVALID_GALOIS_TO_SYMBOL() - .set_GALOIS(i_galois), - "Invalid Galois code: 0x%02x", - i_galois); - - o_symbol = (l_p - TT::symbol2galois); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return Galois code from a given symbol value -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_symbol the symbol value -/// @param[out] o_galois Galois code represented by given symbol -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode symbol_to_galois( const uint8_t i_symbol, uint8_t& o_galois ) -{ - FAPI_ASSERT( i_symbol < MAX_DQ_BITS, - fapi2::MSS_INVALID_SYMBOL_FOR_GALOIS() - .set_SYMBOL(i_symbol), - "Invalid symbol: %d", - i_symbol); - - o_galois = TT::symbol2galois[i_symbol]; - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return symbol value from a given DQ index -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_dq the DQ index -/// @param[out] o_symbol symbol value represented by given DQ index -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode dq_to_symbol( const uint8_t i_dq, uint8_t& o_symbol ) -{ - const auto& l_p = std::find(TT::symbol2dq, (TT::symbol2dq + MAX_DQ_BITS), i_dq); - - FAPI_ASSERT( l_p != (TT::symbol2dq + MAX_DQ_BITS), - fapi2::MSS_INVALID_DQ_TO_SYMBOL() - .set_DQ(i_dq), - "Invalid DQ index: %d", - i_dq); - - o_symbol = (l_p - TT::symbol2dq); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return DQ index from a given symbol value -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_symbol the symbol value -/// @param[out] o_dq DQ index represented by given symbol value -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode symbol_to_dq( const uint8_t i_symbol, uint8_t& o_dq ) -{ - FAPI_ASSERT( i_symbol < MAX_DQ_BITS, - fapi2::MSS_INVALID_SYMBOL_TO_DQ() - .set_SYMBOL(i_symbol), - "symbol_to_dq: invalid symbol: %d", - i_symbol); - - o_dq = TT::symbol2dq[i_symbol]; - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return DQ index from a given Galois code -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_galois the Galois code -/// @param[out] o_dq DQ index represented by given Galois code -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode galois_to_dq( const uint8_t i_galois, uint8_t& o_dq ) -{ - uint8_t l_symbol = 0; - - FAPI_TRY( galois_to_symbol<T>(i_galois, l_symbol), "Failed galois_to_symbol"); - FAPI_TRY( symbol_to_dq<T>(l_symbol, o_dq), "Failed symbol_to_dq" ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return Galois code from a given DQ index -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_dq the DQ index -/// @param[out] o_galois Galois code represented by given symbol -/// @return FAPI2_RC_SUCCESS iff all is ok -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -fapi2::ReturnCode dq_to_galois( const uint8_t i_dq, uint8_t& o_galois ) -{ - uint8_t l_symbol = 0; - - FAPI_TRY( mss::ecc::dq_to_symbol<T>(i_dq, l_symbol), "Failed dq_to_symbol"); - FAPI_TRY( mss::ecc::symbol_to_galois<T>(l_symbol, o_galois) , "Failed symbol_to_galois" ); - -fapi_try_exit: - return fapi2::current_err; -} - -} // close namespace ecc - -} // close namespace mss -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H deleted file mode 100644 index 7a206c5bb..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H +++ /dev/null @@ -1,507 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/hw_mark_store.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file hw_mark_store.H -/// @brief Subroutines for the MC hardware mark store registers -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_HW_MARK_STORE_H_ -#define _MSS_HW_MARK_STORE_H_ - -#include <fapi2.H> -#include <lib/ecc/ecc_traits.H> -#include <generic/memory/lib/utils/scom.H> -#include <lib/shared/mss_const.H> - -namespace mss -{ - -namespace ecc -{ - -namespace hwms -{ - -/// -/// @brief Read Hardware Mark Store (HWMS) register -/// @tparam R master rank number -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read_rank( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); - FAPI_TRY( mss::getScom(i_target, (TT::HARDWARE_MS0_REG + R), o_data) ); - FAPI_INF("read_rank<%d>: 0x%016lx", R, o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<0>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<1>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<2>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<3>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank4( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<4>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank5( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<5>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank6( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<6>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) rank 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_rank7( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_rank<7>(i_target, o_data) ); -} - -/// -/// @brief Read Hardware Mark Store (HWMS) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_rank the master rank index -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - fapi2::buffer<uint64_t>& o_data ) -{ - switch (i_rank) - { - case(0): - return ( read_rank0(i_target, o_data) ); - - case(1): - return ( read_rank1(i_target, o_data) ); - - case(2): - return ( read_rank2(i_target, o_data) ); - - case(3): - return ( read_rank3(i_target, o_data) ); - - case(4): - return ( read_rank4(i_target, o_data) ); - - case(5): - return ( read_rank5(i_target, o_data) ); - - case(6): - return ( read_rank6(i_target, o_data) ); - - case(7): - return ( read_rank7(i_target, o_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_RANK_PASSED() - .set_RANK(i_rank) - .set_TARGET(i_target) - .set_FUNCTION(HWMS_READ), - "%s Invalid rank passed to fwms::ecc::hwms::read (%d)", - mss::c_str(i_target), - i_rank); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write Hardware Mark Store (HWMS) register -/// @tparam R master rank number -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t R, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write_rank( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - static_assert((R < MAX_MRANK_PER_PORT), "Master rank index failed range check"); - FAPI_TRY( mss::putScom(i_target, (TT::HARDWARE_MS0_REG + R), i_data) ); - FAPI_INF("write_rank<%d>: 0x%016lx", R, i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<0>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<1>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<2>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<3>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank4( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<4>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank5( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<5>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank6( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<6>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) rank 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_rank7( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_rank<7>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_rank the master rank index -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const fapi2::buffer<uint64_t>& i_data ) -{ - switch (i_rank) - { - case(0): - return ( write_rank0(i_target, i_data) ); - - case(1): - return ( write_rank1(i_target, i_data) ); - - case(2): - return ( write_rank2(i_target, i_data) ); - - case(3): - return ( write_rank3(i_target, i_data) ); - - case(4): - return ( write_rank4(i_target, i_data) ); - - case(5): - return ( write_rank5(i_target, i_data) ); - - case(6): - return ( write_rank6(i_target, i_data) ); - - case(7): - return ( write_rank7(i_target, i_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_RANK_PASSED() - .set_RANK(i_rank) - .set_TARGET(i_target) - .set_FUNCTION(HWMS_WRITE), - "%s Invalid rank passed to fwms::ecc::hwms::write(%d)", - mss::c_str(i_target), - i_rank); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_chipmark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note HWMS0_CHIPMARK: Hardware chipmark (Galois field code) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_chipmark( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::HARDWARE_MS_CHIPMARK, TT::HARDWARE_MS_CHIPMARK_LEN>(i_value); - FAPI_INF("set_chipmark: 0x%02lx", i_value); -} - -/// -/// @brief get_chipmark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note HWMS0_CHIPMARK: Hardware chipmark (Galois field code) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_chipmark( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::HARDWARE_MS_CHIPMARK, TT::HARDWARE_MS_CHIPMARK_LEN>(o_value); - FAPI_INF("get_chipmark: 0x%02lx", o_value); -} - -/// -/// @brief set_confirmed -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note HWMS0_CONFIRMED: chipmark confirmed -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_confirmed( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::HARDWARE_MS_CONFIRMED>(i_state); - FAPI_INF("set_confirmed: 0x%01lx", i_state); -} - -/// -/// @brief get_confirmed -/// @tparam T fapi2 Target Type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note HWMS0_CONFIRMED: chipmark confirmed -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_confirmed( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::HARDWARE_MS_CONFIRMED>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_confirmed: 0x%01lx", o_state); -} - -/// -/// @brief set_exit_1 -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note HWMS0_EXIT_1: When set, bypass-enabled reads using this mark will -/// @note use exit 1; otherwise exit 0 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_exit_1( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::HARDWARE_MS_EXIT1>(i_state); - FAPI_INF("set_exit_1: 0x%01lx", i_state); -} - -/// -/// @brief get_exit_1 -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note HWMS0_EXIT_1: When set, bypass-enabled reads using this mark will -/// @note use exit 1; otherwise exit 0 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_exit_1( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::HARDWARE_MS_EXIT1>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_exit_1: 0x%01lx", o_state); -} - -} // close namespace hwms - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H deleted file mode 100644 index c6d4a239a..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H +++ /dev/null @@ -1,130 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_aue_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_aue_trap.H -/// @brief Subroutines for the MC mainline aue address trap registers (MBAUER*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINLINE_AUE_TRAP_H_ -#define _MSS_MAINLINE_AUE_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mainline_aue_trap -{ - -/// -/// @brief Read MBS Mainline AUE Address Trap (MBAUER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_AUE_REGS[l_port]), o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline AUE Address Trap (MBAUER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_AUE_REGS[l_port]), i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::AUE_ADDR_TRAP, TT::AUE_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::AUE_ADDR_TRAP, TT::AUE_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -} // close namespace mainline_aue_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H deleted file mode 100644 index a8ea60c98..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H +++ /dev/null @@ -1,162 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_mpe_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_mpe_trap.H -/// @brief Subroutines for the MC mainline mpe address trap registers (MBNCER*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINLINE_MPE_TRAP_H_ -#define _MSS_MAINLINE_MPE_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mainline_mpe_trap -{ - -/// -/// @brief Read MBS Mainline MPE Address Trap (MBMPER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline MPE Address Trap (MBMPER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_MPE_REGS[l_port]), i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::MPE_ADDR_TRAP, TT::MPE_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::MPE_ADDR_TRAP, TT::MPE_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -/// -/// @brief set_mpe_on_rce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE: Indicates whether if this error -/// @note came on the retry of a UE, RCD, or AUE as part of an RCE -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_mpe_on_rce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::MPE_ON_RCE>(i_state); - FAPI_INF("set_mpe_on_rce: 0x%01lx", i_state); -} - -/// -/// @brief get_mpe_on_rce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note MBMPER0Q_PORT_0_MAINLINE_MPE_ON_RCE: Indicates whether if this error -/// @note came on the retry of a UE, RCD, or AUE as part of an RCE -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_mpe_on_rce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::MPE_ON_RCE>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_mpe_on_rce: 0x%01lx", o_state); -} - -} // close namespace mainline_mpe_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H deleted file mode 100644 index 038ed1e6e..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H +++ /dev/null @@ -1,195 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_nce_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_nce_trap.H -/// @brief Subroutines for the MC mainline nce address trap registers (MBNCER*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINLINE_NCE_TRAP_H_ -#define _MSS_MAINLINE_NCE_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> -#include <generic/memory/lib/utils/pos.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mainline_nce_trap -{ - -/// -/// @brief Read MBS Mainline NCE Address Trap (MBNCER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline NCE Address Trap (MBNCER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_NCE_REGS[l_port]), i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::NCE_ADDR_TRAP, TT::NCE_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::NCE_ADDR_TRAP, TT::NCE_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -/// -/// @brief set_nce_on_rce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE: Indicates whether if this NCE came on the -/// @note retry of a UE, RCD, or AUE as part of an RCE -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_nce_on_rce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::NCE_ON_RCE>(i_state); - FAPI_INF("set_nce_on_rce: 0x%01lx", i_state); -} - -/// -/// @brief get_nce_on_rce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_ON_RCE: Indicates whether if this NCE came on the -/// @note retry of a UE, RCD, or AUE as part of an RCE -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_nce_on_rce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::NCE_ON_RCE>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_nce_on_rce: 0x%01lx", o_state); -} - -/// -/// @brief set_nce_is_tce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_state mss::YES or mss::NO - desired state -/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE: Indicates if this NCE is actually -/// @note a two symbol error (TCE) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_nce_is_tce( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::NCE_IS_TCE>(i_state); - FAPI_INF("set_nce_is_tce: 0x%01lx", i_state); -} - -/// -/// @brief get_nce_is_tce -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_state mss::YES or mss::NO - representing the state of the field -/// @note MBNCER0Q_PORT_0_MAINLINE_NCE_IS_TCE: Indicates if this NCE is actually -/// @note a two symbol error (TCE) -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_nce_is_tce( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) -{ - o_state = (i_data.getBit<TT::NCE_IS_TCE>() == false) ? mss::NO : mss::YES; - FAPI_INF("get_nce_is_tce: 0x%01lx", o_state); -} - -} // close namespace mainline_nce_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H deleted file mode 100644 index 35a0135b3..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H +++ /dev/null @@ -1,130 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_rce_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_rce_trap.H -/// @brief Subroutines for the MC mainline rce address trap registers (MBRCER*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINLINE_RCE_TRAP_H_ -#define _MSS_MAINLINE_RCE_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mainline_rce_trap -{ - -/// -/// @brief Read MBS Mainline RCE Address Trap (MBRCER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_RCE_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline RCE Address Trap (MBRCER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_RCE_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::RCE_ADDR_TRAP, TT::RCE_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::RCE_ADDR_TRAP, TT::RCE_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -} // close namespace mainline_rce_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H deleted file mode 100644 index 516f9181e..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H +++ /dev/null @@ -1,130 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mainline_ue_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_ue_trap.H -/// @brief Subroutines for the MC mainline ue address trap registers (MBUER*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINLINE_UE_TRAP_H_ -#define _MSS_MAINLINE_UE_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mainline_ue_trap -{ - -/// -/// @brief Read MBS Mainline UE Address Trap (MBUER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::MAINLINE_UE_REGS[l_port]), o_data) ); - FAPI_INF("read: 0x%016lx", o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline UE Address Trap (MBUER*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::MAINLINE_UE_REGS[l_port]), i_data) ); - FAPI_INF("write: 0x%016lx", i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::UE_ADDR_TRAP, TT::UE_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::UE_ADDR_TRAP, TT::UE_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -} // close namespace mainline_ue_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H deleted file mode 100644 index a06a2ccbe..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H +++ /dev/null @@ -1,187 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/maint_current_trap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file maint_current_trap.H -/// @brief Subroutines for the MC maint current address trap register (MCBMCATQ) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MAINT_CURRENT_TRAP_H_ -#define _MSS_MAINT_CURRENT_TRAP_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace maint_current_trap -{ - -/// -/// @brief Read MBS Mainline MPE Address Trap (MCBMCATQ) register -/// @param[in] i_target the fapi2 target of the MCA -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -inline fapi2::ReturnCode read( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, MCBIST_MCBMCATQ, o_data) ); - FAPI_INF("read: 0x%016lx", o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mainline MPE Address Trap (MCBMCATQ) register -/// @param[in] i_target the fapi2 target of the MCA -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -inline fapi2::ReturnCode write( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, MCBIST_MCBMCATQ, i_data) ); - FAPI_INF("write: 0x%016lx", i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_address( fapi2::buffer<uint64_t>& io_data, const mcbist::address& i_address) -{ - io_data.insertFromRight<TT::CURRENT_ADDR_TRAP, TT::CURRENT_ADDR_TRAP_LEN>(uint64_t(i_address)); - FAPI_INF("set_address: 0x%016lx", uint64_t(i_address)); -} - -/// -/// @brief get_address -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_address mcbist::address form of address field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_address( const fapi2::buffer<uint64_t>& i_data, mcbist::address& o_address ) -{ - uint64_t l_addr = 0; - i_data.extractToRight<TT::CURRENT_ADDR_TRAP, TT::CURRENT_ADDR_TRAP_LEN>(l_addr); - o_address = mcbist::address(l_addr); - FAPI_INF("get_address: 0x%016lx", uint64_t(l_addr)); -} - -/// -/// @brief set_port -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value - desired value -/// @note MCBMCATQ_CFG_CURRENT_PORT_TRAP: If MCBCFGQ_cfg_current_addr_trap_update_dis = 0, then this -/// @note field will store port. This field is ONLY valid in maint_addr_mode. Garabage otherwise. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_port( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::CURRENT_PORT, TT::CURRENT_PORT_LEN>(i_value); - FAPI_INF("set_port: 0x%01lx", i_value); -} - -/// -/// @brief get_port -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value - representing the field value -/// @note MCBMCATQ_CFG_CURRENT_PORT_TRAP: If MCBCFGQ_cfg_current_addr_trap_update_dis = 0, then this -/// @note field will store port. This field is ONLY valid in maint_addr_mode. Garabage otherwise. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_port( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::CURRENT_PORT, TT::CURRENT_PORT_LEN>(o_value); - FAPI_INF("get_port: 0x%01lx", o_value); -} - -/// -/// @brief set_dimm -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value - desired value -/// @note MCBMCATQ_CFG_CURRENT_DIMM_TRAP: If MCBCFGQ_cfg_current_addr_trap_update_dis = 0, then this -/// @note field will store dimm select. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_dimm( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.writeBit<TT::CURRENT_DIMM>(i_value); - FAPI_INF("set_dimm: 0x%01lx", i_value); -} - -/// -/// @brief get_dimm -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value - representing the field value -/// @note MCBMCATQ_CFG_CURRENT_DIMM_TRAP: If MCBCFGQ_cfg_current_addr_trap_update_dis = 0, then this -/// @note field will store dimm select. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_dimm( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - o_value = i_data.getBit<TT::CURRENT_DIMM>(); - FAPI_INF("get_dimm: 0x%01lx", o_value); -} - -} // close namespace maint_current_trap - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H deleted file mode 100644 index 6f413559b..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H +++ /dev/null @@ -1,149 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mark_shadow_reg.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mark_shadow_reg.H -/// @brief Subroutines for the MC mark shadow registers (MSR) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MARK_SHADOW_REG_H_ -#define _MSS_MARK_SHADOW_REG_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace mark_shadow_reg -{ - -/// -/// @brief Read Mark Shadow register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - FAPI_TRY( mss::getScom(i_target, TT::MARK_SHADOW_REG, o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write Mark Shadow register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::MARK_SHADOW_REG, i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_chipmark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_chipmark( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SHADOW_CHIPMARK, TT::SHADOW_CHIPMARK_LEN>(i_value); - FAPI_INF("set_chipmark: 0x%016lx", i_value); -} - -/// -/// @brief get_chipmark -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_chipmark( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SHADOW_CHIPMARK, TT::SHADOW_CHIPMARK_LEN>(o_value); - FAPI_INF("get_chipmark: 0x%016lx", o_value); -} - -/// -/// @brief set_rank -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void set_rank( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SHADOW_RANK, TT::SHADOW_RANK_LEN>(i_value); - FAPI_INF("set_rank: 0x%016lx", i_value); -} - -/// -/// @brief get_rank -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = eccTraits<T> > -inline void get_rank( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SHADOW_RANK, TT::SHADOW_RANK_LEN>(o_value); - FAPI_INF("get_rank: 0x%016lx", o_value); -} - -} // close namespace mark_shadow_reg - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H deleted file mode 100644 index f19185fee..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H +++ /dev/null @@ -1,573 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/modal_symbol_count.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file modal_symbol_count.H -/// @brief Subroutines for the MC modal symbol count (MBSSYMEC*Q) registers -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MODAL_SYMBOL_COUNT_H_ -#define _MSS_MODAL_SYMBOL_COUNT_H_ - -#include <fapi2.H> -#include <lib/ecc/ecc_traits.H> -#include <generic/memory/lib/utils/scom.H> -#include <lib/shared/mss_const.H> - -namespace mss -{ - -namespace ecc -{ - -namespace modal_symbol_count -{ - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) register -/// @tparam N the register index (0-8) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t N, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read_index( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - static_assert((N < TT::NUM_MBSSYM_REGS), "Modal symbol count reg index failed range check"); - FAPI_TRY( mss::getScom(i_target, (TT::MODAL_SYM_COUNT0_REG + N), o_data) ); - FAPI_INF("read_index<%d>: 0x%016lx", N, o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index0( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<0>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index1( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<1>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index2( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<2>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index3( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<3>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index4( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<4>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index5( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<5>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index6( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<6>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index7( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<7>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) 8 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read_index8( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - return ( read_index<8>(i_target, o_data) ); -} - -/// -/// @brief Read modal symbol count (MBSSYMEC*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_index the register index -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, - const uint64_t i_index, - fapi2::buffer<uint64_t>& o_data ) -{ - switch (i_index) - { - case(0): - return ( read_index0(i_target, o_data) ); - - case(1): - return ( read_index1(i_target, o_data) ); - - case(2): - return ( read_index2(i_target, o_data) ); - - case(3): - return ( read_index3(i_target, o_data) ); - - case(4): - return ( read_index4(i_target, o_data) ); - - case(5): - return ( read_index5(i_target, o_data) ); - - case(6): - return ( read_index6(i_target, o_data) ); - - case(7): - return ( read_index7(i_target, o_data) ); - - case(8): - return ( read_index8(i_target, o_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_INDEX_PASSED() - .set_INDEX(i_index) - .set_FUNCTION(SYMBOL_COUNT_READ), - "%s Invalid index passed to fwms::ecc::modal_symbol_count::read (%d)", - mss::c_str(i_target), - i_index); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) register -/// @tparam N the register index (0-8) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< uint64_t N, fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write_index( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - static_assert((N < TT::NUM_MBSSYM_REGS), "Modal symbol count reg index failed range check"); - FAPI_TRY( mss::putScom(i_target, (TT::MODAL_SYM_COUNT0_REG + N), i_data) ); - FAPI_INF("write_index<%d>: 0x%016lx", N, i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 0 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index0( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<0>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 1 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index1( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<1>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 2 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index2( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<2>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 3 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index3( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<3>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 4 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index4( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<4>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 5 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index5( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<5>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 6 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index6( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<6>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 7 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index7( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<7>(i_target, i_data) ); -} - -/// -/// @brief Write modal symbol count (MBSSYMEC*Q) 8 register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write_index8( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - return ( write_index<8>(i_target, i_data) ); -} - -/// -/// @brief Write Hardware Mark Store (HWMS) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_index the register index -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, - const uint64_t i_index, - const fapi2::buffer<uint64_t>& i_data ) -{ - switch (i_index) - { - case(0): - return ( write_index0(i_target, i_data) ); - - case(1): - return ( write_index1(i_target, i_data) ); - - case(2): - return ( write_index2(i_target, i_data) ); - - case(3): - return ( write_index3(i_target, i_data) ); - - case(4): - return ( write_index4(i_target, i_data) ); - - case(5): - return ( write_index5(i_target, i_data) ); - - case(6): - return ( write_index6(i_target, i_data) ); - - case(7): - return ( write_index7(i_target, i_data) ); - - case(8): - return ( write_index8(i_target, i_data) ); - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_INDEX_PASSED() - .set_INDEX(i_index) - .set_FUNCTION(SYMBOL_COUNT_WRITE), - "%s Invalid index passed to fwms::ecc::modal_symbol_count::write (%d)", - mss::c_str(i_target), - i_index); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_index the counter index -/// @param[in] i_value the value of the field -/// @note MBSSYMEC*Q_MODAL_SYMBOL_COUNTER_XX: Functional mode determined by MBSTRQ_Symbol_counter_mode: -/// @note if 00, 0:7 = Maint NCE counter for Symbol XX if 01, 0:3 = MCBIST error counter for nibble (XX/4) -/// @note and rank (XX%4)*2 4:7 = MCBIST error counter for nibble (XX/4) and rank ((XX%4)*2)+1 if 10, -/// @note 0:3 = MCBIST error counter for port XX/18 and nibble XX%18 4:7 = MCBIST error rank map for -/// @note port XX/18 and nibble XX%18 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_index, const uint64_t i_value ) -{ - static_assert ( TT::MODAL_SYMBOL_COUNTERS_PER_REG <= 8, - "mss::ecc_count::modal_symbol_count: Modal symbol count field index failed range check" ); - const uint64_t l_field = i_index % TT::MODAL_SYMBOL_COUNTERS_PER_REG; - - switch (l_field) - { - case 0: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_00, TT::MODAL_SYMBOL_COUNTER_00_LEN>(i_value); - break; - - case 1: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_01, TT::MODAL_SYMBOL_COUNTER_01_LEN>(i_value); - break; - - case 2: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_02, TT::MODAL_SYMBOL_COUNTER_02_LEN>(i_value); - break; - - case 3: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_03, TT::MODAL_SYMBOL_COUNTER_03_LEN>(i_value); - break; - - case 4: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_04, TT::MODAL_SYMBOL_COUNTER_04_LEN>(i_value); - break; - - case 5: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_05, TT::MODAL_SYMBOL_COUNTER_05_LEN>(i_value); - break; - - case 6: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_06, TT::MODAL_SYMBOL_COUNTER_06_LEN>(i_value); - break; - - case 7: - io_data.insertFromRight<TT::MODAL_SYMBOL_COUNTER_07, TT::MODAL_SYMBOL_COUNTER_07_LEN>(i_value); - break; - - default: - // Shouldn't happen due to modulo above, but here just in case - JLH - FAPI_ERR("Modal symbol count field index failed range check"); - fapi2::Assert(false); - break; - } - - FAPI_INF("set_count(%d): 0x%02lx", l_field, i_value); -} - -/// -/// @brief get_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[in] i_index the counter index -/// @param[out] o_value the value of the field -/// @note MBSSYMEC*Q_MODAL_SYMBOL_COUNTER_XX: Functional mode determined by MBSTRQ_Symbol_counter_mode: -/// @note if 00, 0:7 = Maint NCE counter for Symbol XX if 01, 0:3 = MCBIST error counter for nibble (XX/4) -/// @note and rank (XX%4)*2 4:7 = MCBIST error counter for nibble (XX/4) and rank ((XX%4)*2)+1 if 10, -/// @note 0:3 = MCBIST error counter for port XX/18 and nibble XX%18 4:7 = MCBIST error rank map for -/// @note port XX/18 and nibble XX%18 -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_count( const fapi2::buffer<uint64_t>& i_data, const uint64_t i_index, uint64_t& o_value ) -{ - const uint64_t l_field = i_index % TT::MODAL_SYMBOL_COUNTERS_PER_REG; - static_assert ( TT::MODAL_SYMBOL_COUNTERS_PER_REG <= 8, - "mss::ecc_count::get_count: Modal symbol count field index failed range check" ); - - switch (l_field) - { - case 0: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_00, TT::MODAL_SYMBOL_COUNTER_00_LEN>(o_value); - break; - - case 1: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_01, TT::MODAL_SYMBOL_COUNTER_01_LEN>(o_value); - break; - - case 2: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_02, TT::MODAL_SYMBOL_COUNTER_02_LEN>(o_value); - break; - - case 3: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_03, TT::MODAL_SYMBOL_COUNTER_03_LEN>(o_value); - break; - - case 4: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_04, TT::MODAL_SYMBOL_COUNTER_04_LEN>(o_value); - break; - - case 5: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_05, TT::MODAL_SYMBOL_COUNTER_05_LEN>(o_value); - break; - - case 6: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_06, TT::MODAL_SYMBOL_COUNTER_06_LEN>(o_value); - break; - - case 7: - i_data.extractToRight<TT::MODAL_SYMBOL_COUNTER_07, TT::MODAL_SYMBOL_COUNTER_07_LEN>(o_value); - break; - - default: - // shouldn't happen due to modulo above, but here just in case - FAPI_ERR("Modal symbol count field index failed range check"); - fapi2::Assert(false); - break; - } - - FAPI_INF("get_count(%d): 0x%02lx", l_field, o_value); -} - -} // close namespace modal_symbol_count - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/nimbus_mbs_error_vector_trap.H index 4ed773988..fe6525231 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/nimbus_mbs_error_vector_trap.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/mbs_error_vector_trap.H $ */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/nimbus_mbs_error_vector_trap.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,22 +24,24 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file mbs_error_vector_trap.H +/// @file nimbus_mbs_error_vector_trap.H /// @brief Subroutines for the MC MBS error vector trap registers (MBSEVR*Q) /// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> +// *HWP HWP Owner: Matt Hickman <Matthew.Hickman@ibm.com> // *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#ifndef _MSS_MBS_ERROR_VECTOR_TRAP_H_ -#define _MSS_MBS_ERROR_VECTOR_TRAP_H_ +#ifndef _NIMBUS_MBS_ERROR_VECTOR_TRAP_H_ +#define _NIMBUS_MBS_ERROR_VECTOR_TRAP_H_ #include <fapi2.H> #include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> +#include <lib/utils/nimbus_find.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/ecc/ecc_traits.H> +#include <generic/memory/lib/ecc/mbs_error_vector_trap.H> namespace mss { @@ -51,54 +53,14 @@ namespace mbs_error_vector_trap { /// -/// @brief Read MBS Error Vector Trap (MBSEVR*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::getScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Error Vector Trap (MBSEVR*Q) register -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mc -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - const auto& l_mcbist_target = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - const auto& l_port = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_target); - - FAPI_TRY( mss::putScom(l_mcbist_target, (TT::ERROR_VECTOR_REGS[l_port]), i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief set_nce_galois /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in, out] io_data the register value /// @param[in] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void set_nce_galois( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& io_data, const uint64_t i_value) @@ -121,12 +83,12 @@ inline void set_nce_galois( const fapi2::Target<T>& i_target, /// /// @brief get_nce_galois /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in] i_data the register value /// @param[out] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void get_nce_galois( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value) @@ -149,12 +111,12 @@ inline void get_nce_galois( const fapi2::Target<T>& i_target, /// /// @brief set_nce_magnitude /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in, out] io_data the register value /// @param[in] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void set_nce_magnitude( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& io_data, const uint64_t i_value) @@ -177,12 +139,12 @@ inline void set_nce_magnitude( const fapi2::Target<T>& i_target, /// /// @brief get_nce_magnitude /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in] i_data the register value /// @param[out] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void get_nce_magnitude( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value) @@ -205,12 +167,12 @@ inline void get_nce_magnitude( const fapi2::Target<T>& i_target, /// /// @brief set_tce_galois /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in, out] io_data the register value /// @param[in] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void set_tce_galois( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& io_data, const uint64_t i_value) @@ -233,12 +195,12 @@ inline void set_tce_galois( const fapi2::Target<T>& i_target, /// /// @brief get_tce_galois /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in] i_data the register value /// @param[out] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void get_tce_galois( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value) @@ -261,12 +223,12 @@ inline void get_tce_galois( const fapi2::Target<T>& i_target, /// /// @brief set_tce_magnitude /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in, out] io_data the register value /// @param[in] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void set_tce_magnitude( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& io_data, const uint64_t i_value) @@ -289,12 +251,12 @@ inline void set_tce_magnitude( const fapi2::Target<T>& i_target, /// /// @brief get_tce_magnitude /// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> +/// @tparam TT traits type defaults to eccTraits<mc_type::NIMBUS, T> /// @param[in] i_target the fapi2 target of the mc /// @param[in] i_data the register value /// @param[out] i_value the value of the field /// -template< fapi2::TargetType T, typename TT = eccTraits<T> > +template< fapi2::TargetType T, typename TT = eccTraits<mc_type::NIMBUS, T> > inline void get_tce_magnitude( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H b/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H deleted file mode 100644 index 834f01b19..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H +++ /dev/null @@ -1,648 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/ecc/read_error_count_regs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mainline_ue_trap.H -/// @brief Subroutines for the MBS Memory Scrub/Read Error Count registers (MBSEC*Q) -/// -// *HWP HWP Owner: Louis Stermole <stermole@us.ibm.com> -// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_READ_ERROR_COUNT_REGS_H_ -#define _MSS_READ_ERROR_COUNT_REGS_H_ - -#include <fapi2.H> -#include <lib/mcbist/address.H> -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace read_error_count_reg0 -{ - -/// -/// @brief Read MBS Memory Scrub/Read Error Count Register 0 (MBSEC0Q) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - FAPI_TRY( mss::getScom(i_target, TT::READ_ERROR_COUNT_REG0, o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Memory Scrub/Read Error Count Register 0 (MBSEC0Q) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::READ_ERROR_COUNT_REG0, i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_intermittent_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_INTERMITTENT_CE_COUNT: Intermittent CE Count This is a 12-bit count of -/// @note intermittent CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_intermittent_ce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::INTERMITTENT_CE_COUNT, TT::INTERMITTENT_CE_COUNT_LEN>(i_value); - FAPI_INF("set_intermittent_ce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_intermittent_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_INTERMITTENT_CE_COUNT: Intermittent CE Count This is a 12-bit count of -/// @note intermittent CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_intermittent_ce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::INTERMITTENT_CE_COUNT, TT::INTERMITTENT_CE_COUNT_LEN>(o_value); - FAPI_INF("get_intermittent_ce_count: 0x%03lx", o_value); -} - -/// -/// @brief set_soft_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_SOFT_CE_COUNT: Soft CE Count This is a 12-bit count of -/// @note soft CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_soft_ce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SOFT_CE_COUNT, TT::SOFT_CE_COUNT_LEN>(i_value); - FAPI_INF("set_soft_ce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_soft_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_SOFT_CE_COUNT: Soft CE Count This is a 12-bit count of -/// @note soft CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_soft_ce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SOFT_CE_COUNT, TT::SOFT_CE_COUNT_LEN>(o_value); - FAPI_INF("get_soft_ce_count: 0x%03lx", o_value); -} - -/// -/// @brief set_hard_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_HARD_CE_COUNT: Hard CE Count This is a 12-bit count of -/// @note hard CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_hard_ce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::HARD_CE_COUNT, TT::HARD_CE_COUNT_LEN>(i_value); - FAPI_INF("set_hard_ce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_hard_ce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_HARD_CE_COUNT: Hard CE Count This is a 12-bit count of -/// @note hard CE events. Will freeze its value upon incrementing to the max -/// @note value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_hard_ce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::HARD_CE_COUNT, TT::HARD_CE_COUNT_LEN>(o_value); - FAPI_INF("get_hard_ce_count: 0x%03lx", o_value); -} - -/// -/// @brief set_intermittent_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_INTERMITTENT_MCE_COUNT: Intermittent MCE Count This is a 12-bit count of -/// @note intermittent Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_intermittent_mce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::INTERMITTENT_MCE_COUNT, TT::INTERMITTENT_MCE_COUNT_LEN>(i_value); - FAPI_INF("set_intermittent_mce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_intermittent_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_INTERMITTENT_MCE_COUNT: Intermittent MCE Count This is a 12-bit count of -/// @note intermittent Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_intermittent_mce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::INTERMITTENT_MCE_COUNT, TT::INTERMITTENT_MCE_COUNT_LEN>(o_value); - FAPI_INF("get_intermittent_mce_count: 0x%03lx", o_value); -} - -/// -/// @brief set_soft_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_SOFT_MCE_COUNT: Soft MCE Count This is a 12-bit count of -/// @note soft Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_soft_mce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SOFT_MCE_COUNT, TT::SOFT_MCE_COUNT_LEN>(i_value); - FAPI_INF("set_soft_mce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_soft_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_SOFT_MCE_COUNT: Soft MCE Count This is a 12-bit count of -/// @note soft Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_soft_mce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SOFT_MCE_COUNT, TT::SOFT_MCE_COUNT_LEN>(o_value); - FAPI_INF("get_soft_mce_count: 0x%03lx", o_value); -} - -} // close namespace read_error_count_reg0 - -namespace read_error_count_reg1 -{ - -/// -/// @brief Read MBS Memory Scrub/Read Error Count Register 1 (MBSEC1Q) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - FAPI_TRY( mss::getScom(i_target, TT::READ_ERROR_COUNT_REG1, o_data) ); - FAPI_INF("%s read: 0x%016lx", mss::c_str(i_target), o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Memory Scrub/Read Error Count Register 1 (MBSEC1Q) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::READ_ERROR_COUNT_REG1, i_data) ); - FAPI_INF("%s write: 0x%016lx", mss::c_str(i_target), i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_hard_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_HARD_MCE_COUNT: Hard MCE Count This is a 12-bit count of -/// @note hard Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_hard_mce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::HARD_MCE_COUNT, TT::HARD_MCE_COUNT_LEN>(i_value); - FAPI_INF("set_hard_mce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_hard_mce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_HARD_MCE_COUNT: Hard MCE Count This is a 12-bit count of -/// @note hard Marked Chip Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_hard_mce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::HARD_MCE_COUNT, TT::HARD_MCE_COUNT_LEN>(o_value); - FAPI_INF("get_hard_mce_count: 0x%03lx", o_value); -} - -/// -/// @brief set_ice_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_ICE_COUNT: ICE (IMPE) Count This is a 12-bit count of -/// @note Intermittent Marked-Placed Chip Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_ice_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::ICE_COUNT, TT::ICE_COUNT_LEN>(i_value); - FAPI_INF("set_ice_count: 0x%03lx", i_value); -} - -/// -/// @brief get_ice_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_ICE_COUNT: ICE (IMPE) Count This is a 12-bit count of -/// @note Intermittent Marked-Placed Chip Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_ice_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::ICE_COUNT, TT::ICE_COUNT_LEN>(o_value); - FAPI_INF("get_ice_count: 0x%03lx", o_value); -} - -/// -/// @brief set_ue_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_UE_COUNT: UE Count This is a 12-bit count of -/// @note Uncorrectable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_ue_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::UE_COUNT, TT::UE_COUNT_LEN>(i_value); - FAPI_INF("set_ue_count: 0x%03lx", i_value); -} - -/// -/// @brief get_ue_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_UE_COUNT: UE Count This is a 12-bit count of -/// @note Uncorrectable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_ue_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::UE_COUNT, TT::UE_COUNT_LEN>(o_value); - FAPI_INF("get_ue_count: 0x%03lx", o_value); -} - -/// -/// @brief set_aue_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_AUE_COUNT: AUE Count This is a 12-bit count of -/// @note AUE Parity Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_aue_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::AUE_COUNT, TT::AUE_COUNT_LEN>(i_value); - FAPI_INF("set_aue_count: 0x%03lx", i_value); -} - -/// -/// @brief get_aue_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_AUE_COUNT: AUE Count This is a 12-bit count of -/// @note AUE Parity Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_aue_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::AUE_COUNT, TT::AUE_COUNT_LEN>(o_value); - FAPI_INF("get_aue_count: 0x%03lx", o_value); -} - -/// -/// @brief set_rce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSEC0Q_RCE_COUNT: RCE Count This is a 12-bit count of -/// @note Retried Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_rce_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::RCE_COUNT, TT::RCE_COUNT_LEN>(i_value); - FAPI_INF("set_rce_count: 0x%03lx", i_value); -} - -/// -/// @brief get_rce_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSEC0Q_RCE_COUNT: RCE Count This is a 12-bit count of -/// @note Retried Correctable Error events. Will freeze its value upon -/// @note incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_rce_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::RCE_COUNT, TT::RCE_COUNT_LEN>(o_value); - FAPI_INF("get_rce_count: 0x%03lx", o_value); -} - -} // close namespace read_error_count_reg1 - -namespace mark_symbol_count_reg -{ - -/// -/// @brief Read MBS Mark Symbol Error Count Register (MBSMSECQ) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[out] o_data the value of the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode read( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - FAPI_TRY( mss::getScom(i_target, TT::MARK_SYMBOL_COUNT_REG, o_data) ); - FAPI_INF("read: 0x%016lx", o_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Write MBS Mark Symbol Error Count Register (MBSMSECQ) -/// @tparam T fapi2 Target Type - derived from i_target's type -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_target the fapi2 target of the mcbist -/// @param[in] i_data the value to write to the register -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -template< fapi2::TargetType T, typename TT = eccTraits<T> > -inline fapi2::ReturnCode write( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::MARK_SYMBOL_COUNT_REG, i_data) ); - FAPI_INF("write: 0x%016lx", i_data); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set_symbol0_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL0_COUNT: MCE Symbol 0 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 0 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_symbol0_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SYMBOL0_COUNT, TT::SYMBOL0_COUNT_LEN>(i_value); - FAPI_INF("set_symbol0_count: 0x%03lx", i_value); -} - -/// -/// @brief get_symbol0_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL0_COUNT: MCE Symbol 0 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 0 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_symbol0_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SYMBOL0_COUNT, TT::SYMBOL0_COUNT_LEN>(o_value); - FAPI_INF("get_symbol0_count: 0x%03lx", o_value); -} - -/// -/// @brief set_symbol1_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL1_COUNT: MCE Symbol 1 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 1 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_symbol1_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SYMBOL1_COUNT, TT::SYMBOL1_COUNT_LEN>(i_value); - FAPI_INF("set_symbol1_count: 0x%03lx", i_value); -} - -/// -/// @brief get_symbol1_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL1_COUNT: MCE Symbol 1 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 1 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_symbol1_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SYMBOL1_COUNT, TT::SYMBOL1_COUNT_LEN>(o_value); - FAPI_INF("get_symbol1_count: 0x%03lx", o_value); -} - -/// -/// @brief set_symbol2_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL2_COUNT: MCE Symbol 2 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 2 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_symbol2_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SYMBOL2_COUNT, TT::SYMBOL2_COUNT_LEN>(i_value); - FAPI_INF("set_symbol2_count: 0x%03lx", i_value); -} - -/// -/// @brief get_symbol2_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL2_COUNT: MCE Symbol 2 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 2 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_symbol2_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SYMBOL2_COUNT, TT::SYMBOL2_COUNT_LEN>(o_value); - FAPI_INF("get_symbol2_count: 0x%03lx", o_value); -} - -/// -/// @brief set_symbol3_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in, out] io_data the register value -/// @param[in] i_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL3_COUNT: MCE Symbol 3 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 3 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void set_symbol3_count( fapi2::buffer<uint64_t>& io_data, const uint64_t i_value ) -{ - io_data.insertFromRight<TT::SYMBOL3_COUNT, TT::SYMBOL3_COUNT_LEN>(i_value); - FAPI_INF("set_symbol3_count: 0x%03lx", i_value); -} - -/// -/// @brief get_symbol3_count -/// @tparam T fapi2 Target Type defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to eccTraits<T> -/// @param[in] i_data the register value -/// @param[out] o_value the value of the field -/// @note MBSMSECQ_MCE_SYMBOL3_COUNT: MCE Symbol 3 Error Count This is a 8-bit count -/// @note that increments on MCE when Symbol 3 under chip mark takes error. Will freeze -/// @note its value upon incrementing to the max value until reset. -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = eccTraits<T> > -inline void get_symbol3_count( const fapi2::buffer<uint64_t>& i_data, uint64_t& o_value ) -{ - i_data.extractToRight<TT::SYMBOL3_COUNT, TT::SYMBOL3_COUNT_LEN>(o_value); - FAPI_INF("get_symbol3_count: 0x%03lx", o_value); -} - -} // close namespace mark_symbol_count_reg - -} // close namespace ecc - -} // close namespace mss - -#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C index 35e1dd62e..61326898d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/memory_size.C @@ -38,7 +38,7 @@ #include <lib/mss_attribute_accessors.H> #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/memory_size.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_mss_voltage.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_mss_voltage.C index d895897ca..df3390257 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_mss_voltage.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_mss_voltage.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,7 +42,7 @@ // Generic libraries #include <generic/memory/lib/utils/shared/mss_generic_consts.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/spd/spd_facade.H> #include <generic/memory/lib/utils/voltage/gen_mss_voltage_traits.H> #include <generic/memory/lib/utils/voltage/gen_mss_volt.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_pre_data_engine.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_pre_data_engine.C index 281fe8c56..d8358a8a5 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_pre_data_engine.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/nimbus_pre_data_engine.C @@ -34,7 +34,7 @@ // *HWP Level: 3 // *HWP Consumed by: CI -#include <generic/memory/lib/data_engine/pre_data_init.H> +#include <lib/eff_config/pre_data_init.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/p9n_data_init_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/p9n_data_init_traits.H new file mode 100644 index 000000000..93d3e43d6 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/p9n_data_init_traits.H @@ -0,0 +1,473 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/eff_config/p9n_data_init_traits.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9n_data_init_traits.H +/// @brief Trait class definitions for Nimbus pre_data_init +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: CI + +#ifndef _MSS_P9N_PRE_DATA_INIT_TRAITS_H_ +#define _MSS_P9N_PRE_DATA_INIT_TRAITS_H_ + +#include <fapi2.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine.H> +#include <lib/mss_attribute_accessors.H> + +namespace mss +{ + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, DIMM_TYPE specialization +/// +template<> +class preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::DIMM_TYPE> +{ + public: + using attr_type = fapi2::ATTR_EFF_DIMM_TYPE_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_DIMM_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_TYPE, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, DRAM_GEN specialization +/// +template<> +class preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::DRAM_GEN> +{ + public: + using attr_type = fapi2::ATTR_EFF_DRAM_GEN_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_DRAM_GEN_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_DRAM_GEN, i_target, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DRAM_GEN, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, HYBRID specialization +/// +template<> +class preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::HYBRID> +{ + public: + using attr_type = fapi2::ATTR_EFF_HYBRID_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_HYBRID_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_HYBRID, i_target, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, HYBRID_MEDIA specialization +/// +template<> +class preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::HYBRID_MEDIA> +{ + public: + using attr_type = fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID_MEDIA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_HYBRID_MEMORY_TYPE, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, MRANKS specialization +/// +template<> +class preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::MRANKS> +{ + public: + using attr_type = fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_MRANKS; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, o_setting) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class preDataInitTraits +/// @note NIMBUS, DIMM_RANKS_CNFG specialization +/// +template<> +struct preDataInitTraits<mss::proc_type::NIMBUS, pre_data_init_fields::DIMM_RANKS_CNFG> +{ + using attr_type = fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED_Type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_EFF_DIMM_RANKS_CONFIGED, i_target, i_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note AXONE, DIMM_TYPE_METADATA specialization +/// +template<> +struct attrEngineTraits<proc_type::NIMBUS, generic_metadata_fields, generic_metadata_fields::DIMM_TYPE_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_TYPE_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_TYPE_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dimm_type(i_target, o_setting); + } +}; + +/// +/// @brief Traits associated with DIMM positioning +/// @class dimmPosTraits - NIMBUS specializattion +/// +template<> +class dimmPosTraits<mss::mc_type::NIMBUS> +{ + private: + using PT = posTraits<fapi2::TARGET_TYPE_DIMM>; + using MT = mss::mcTypeTraits<mc_type::NIMBUS>; + + public: + // Public interface syntatic sugar + using pos_type = PT::pos_type; + + // Proc 0 is DIMM 0-15, proc 2 is 64-79. 64 is the stride between processors + static constexpr auto DIMM_STRIDE_PER_PROC = 64; + static constexpr auto TOTAL_DIMM = MT::MC_PER_MODULE * MT::MCS_PER_MC * MT::PORTS_PER_MCS * MT::DIMMS_PER_PORT; + + /// + /// @brief Return the PROC_CHIP parent of a DIMM + /// @param[in] i_target the dimm target + /// @return the fapi2 proc target + /// + static fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> get_proc(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) + { + // Using fapi2 rather than mss::find as this is pretty low level stuff. + return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DRAM_GEN_METADATA specialization +/// +template<> +struct attrEngineTraits<proc_type::NIMBUS, generic_metadata_fields, generic_metadata_fields::DRAM_GEN_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DRAM_GEN_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DRAM_GEN_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DRAM_GEN_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + return mss::eff_dram_gen(i_target, o_setting); + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note generic_metadata_fields, DIMM_POS_METADATA specialization +/// +template<> +struct attrEngineTraits<proc_type::NIMBUS, generic_metadata_fields, generic_metadata_fields::DIMM_POS_METADATA> +{ + using attr_type = fapi2::ATTR_MEM_DIMM_POS_METADATA_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_DIMM_POS_METADATA_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_POS_METADATA; + + /// + /// @brief attribute getter + /// @param[in] i_target the MCS target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return FAPI_ATTR_GET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the MCS target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return FAPI_ATTR_SET(fapi2::ATTR_MEM_DIMM_POS_METADATA, i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[in] i_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + attr_integral_type& o_setting) + { + using TT = mss::dimmPosTraits<mss::mc_type::NIMBUS>; + return gen::dimm_pos<TT>(i_target, o_setting); + } +}; + +}// mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C index 5a8f25ab3..75c378da8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C @@ -34,6 +34,8 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/shared/mss_const.H> #include <vpd_access.H> #include <mss.H> #include <algorithm> @@ -65,7 +67,7 @@ namespace code /// @return fapi2::FAPI2_RC_SUCCESS if no LRDIMM, otherwise a MSS_PLUG_RULE error code /// @note This function will commit error logs representing the mixing failure /// -fapi2::ReturnCode check_lrdimm( const std::vector<dimm::kind>& i_kinds ) +fapi2::ReturnCode check_lrdimm( const std::vector<dimm::kind<>>& i_kinds ) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -100,7 +102,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_xlate_config(const fapi2::Target<TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { if (i_kinds.size() > 1) { @@ -149,7 +151,7 @@ fapi_try_exit: /// @note The DIMM kind should be a DIMM on the MCA /// fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const dimm::kind& i_kind, + const dimm::kind<>& i_kind, const fapi2::buffer<uint8_t>& i_mrw_supported_list) { // Contains a mapping of the DRAM width to the bitmap value to be checked for support @@ -194,7 +196,7 @@ fapi_try_exit: /// This function will commit error logs if a DIMM has an unsupported DRAM width /// fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -220,7 +222,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -249,7 +251,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_hybrid(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { // Make sure we don't get a stale error fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -295,10 +297,11 @@ fapi_try_exit: fapi2::ReturnCode dimm_slot_is_nv_capable(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, bool& o_is_capable) { - const auto l_pos = mss::pos(i_target); - + uint8_t l_pos = 0; fapi2::buffer<uint64_t> l_plug_rules_bitmap = 0; + FAPI_TRY( mss::mrw_nvdimm_slot_position(i_target, l_pos) ); + FAPI_TRY( mss::mrw_nvdimm_plug_rules(l_plug_rules_bitmap) ); o_is_capable = l_plug_rules_bitmap.getBit(l_pos); @@ -319,7 +322,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_nvdimm(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; bool l_nvdimm_in_port = false; @@ -370,7 +373,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_stack_type(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -473,7 +476,7 @@ bool unsupported_rank_helper(const uint64_t i_dimm0_ranks, /// @note This function will commit error logs representing the mixing failure /// fapi2::ReturnCode dimm_type_mixing(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds) + const std::vector<dimm::kind<>>& i_kinds) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -609,7 +612,7 @@ fapi_try_exit: /// @param[in] i_kinds a vector of DIMM kind structs /// @return fapi2::ReturnCode /// -fapi2::ReturnCode check_gen( const std::vector<dimm::kind>& i_kinds ) +fapi2::ReturnCode check_gen( const std::vector<dimm::kind<>>& i_kinds ) { fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; @@ -641,7 +644,7 @@ fapi_try_exit: /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_rank_config(const fapi2::Target<TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds, + const std::vector<dimm::kind<>>& i_kinds, const uint64_t i_ranks_override) { // We need to keep track of current_err ourselves as the FAPI_ASSERT_NOEXIT macro doesn't. @@ -687,8 +690,8 @@ fapi2::ReturnCode check_rank_config(const fapi2::Target<TARGET_TYPE_MCA>& i_targ // (really probably that's the only case it catches but <shhhhh>.) // I don't think f/w supports std::count ... There aren't many DIMM on this port ... uint64_t l_rank_count = 0; - const dimm::kind* l_dimm0_kind = nullptr; - const dimm::kind* l_dimm1_kind = nullptr; + const dimm::kind<>* l_dimm0_kind = nullptr; + const dimm::kind<>* l_dimm1_kind = nullptr; for (const auto& k : i_kinds) { @@ -766,7 +769,7 @@ fapi_try_exit: /// @return fapi2::FAPI2_RC_SUCCESS if okay, otherwise a MSS_PLUG_RULE error code /// fapi2::ReturnCode check_nvdimm_pairing(const fapi2::Target<fapi2::TARGET_TYPE_MCS> i_target, - const std::vector<dimm::kind>& l_kinds) + const std::vector<dimm::kind<>>& l_kinds) { // 3 scenarios where the pairing rule would fail: // (1). Odd number of NVDIMMs installed @@ -866,7 +869,7 @@ fapi2::ReturnCode plug_rule::enforce_plug_rules(const fapi2::Target<fapi2::TARGE // Enforce the NVDIMM pairing rule { - const auto l_dimm_kinds = mss::dimm::kind::vector(l_dimms); + const auto l_dimm_kinds = mss::dimm::kind<>::vector(l_dimms); FAPI_TRY( plug_rule::check_nvdimm_pairing(i_target, l_dimm_kinds) ); } @@ -895,7 +898,7 @@ fapi2::ReturnCode plug_rule::enforce_plug_rules(const fapi2::Target<fapi2::TARGE // Safe, even though the VPD decoder can get us here before the rest of eff_config has completed. // We'll only use the master rank information to enforce the rank config rules (which will have been // decoded and are valid before VPD was asked for.) - const auto l_dimm_kinds = mss::dimm::kind::vector(l_dimms); + const auto l_dimm_kinds = mss::dimm::kind<>::vector(l_dimms); uint64_t l_ranks_override = 0; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H index a730fa9a4..24da77869 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.H @@ -38,7 +38,7 @@ #include <fapi2.H> #include <cstdint> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> namespace mss { @@ -106,7 +106,7 @@ fapi2::ReturnCode empty_slot_zero(const fapi2::Target<T>& i_target); /// @return std::pair representing the type and the count. /// @note the vector of kinds comes back sorted by DIMM type. /// -std::pair<uint8_t, uint64_t> dimm_type_helper(std::vector<dimm::kind>& io_kinds); +std::pair<uint8_t, uint64_t> dimm_type_helper(std::vector<dimm::kind<>>& io_kinds); /// /// @brief Rank violation helper @@ -142,7 +142,7 @@ inline void rank_violation(const fapi2::Target<T>& i_target, const uint8_t l_dim /// @note This function will commit error logs representing the mixing failure /// fapi2::ReturnCode dimm_type_mixing(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforce rank configs @@ -155,7 +155,7 @@ fapi2::ReturnCode dimm_type_mixing(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds, + const std::vector<dimm::kind<>>& i_kinds, const uint64_t i_ranks_override); /// @@ -167,7 +167,7 @@ fapi2::ReturnCode check_rank_config(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& /// @note The DIMM kind should be a DIMM on the MCA /// fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const dimm::kind& i_kind, + const dimm::kind<>& i_kind, const fapi2::buffer<uint8_t>& i_mrw_supported_list); /// @@ -179,7 +179,7 @@ fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::T /// This function will commit error logs if a DIMM has an unsupported DRAM width /// fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforce DRAM width checks @@ -190,7 +190,7 @@ fapi2::ReturnCode check_system_supported_dram_width(const fapi2::Target<fapi2::T /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforce DRAM stack type checks @@ -201,7 +201,7 @@ fapi2::ReturnCode check_dram_width(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_stack_type(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforce hybrid DIMM checks @@ -212,7 +212,7 @@ fapi2::ReturnCode check_stack_type(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_hybrid(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforces that NVDIMM are plugged in the proper location @@ -223,7 +223,7 @@ fapi2::ReturnCode check_hybrid(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_ta /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_nvdimm(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); /// /// @brief Enforce the NVDIMM pairing per MCS @@ -232,7 +232,7 @@ fapi2::ReturnCode check_nvdimm(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_ta /// @return fapi2::FAPI2_RC_SUCCESS if okay, otherwise a MSS_PLUG_RULE error code /// fapi2::ReturnCode check_nvdimm_pairing(const fapi2::Target<fapi2::TARGET_TYPE_MCS> i_target, - const std::vector<dimm::kind>& l_kinds); + const std::vector<dimm::kind<>>& l_kinds); // Adding in code based plug rules - as supporting code gets added, the following checks can be deleted namespace code @@ -244,7 +244,7 @@ namespace code /// @return fapi2::FAPI2_RC_SUCCESS if no LRDIMM, otherwise a MSS_PLUG_RULE error code /// @note This function will commit error logs representing the mixing failure /// -fapi2::ReturnCode check_lrdimm( const std::vector<dimm::kind>& i_kinds ); +fapi2::ReturnCode check_lrdimm( const std::vector<dimm::kind<>>& i_kinds ); /// /// @brief Enforce equivalent rank and row configs @@ -255,7 +255,7 @@ fapi2::ReturnCode check_lrdimm( const std::vector<dimm::kind>& i_kinds ); /// @note Expects the kind array to represent the DIMM on the port. /// fapi2::ReturnCode check_xlate_config(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const std::vector<dimm::kind>& i_kinds); + const std::vector<dimm::kind<>>& i_kinds); } // code diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/pre_data_init.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/pre_data_init.H new file mode 100644 index 000000000..14d25f63b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/pre_data_init.H @@ -0,0 +1,438 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/eff_config/pre_data_init.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file pre_data_init.H +/// @brief Class to set preliminary eff_config attributes +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: CI + +#ifndef _MSS_PRE_DATA_INIT_H_ +#define _MSS_PRE_DATA_INIT_H_ + +#include <cstring> +#include <fapi2.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <generic/memory/lib/utils/find.H> +#include <lib/eff_config/p9n_data_init_traits.H> +#include <generic/memory/lib/data_engine/data_engine_utils.H> + +namespace mss +{ +// TK - Remove generalizations since this is dubbed Nimbus specific implementation + +/// +/// @class DataSetterTraits2D +/// @brief Traits for setting eff_config data +/// @tparam P proc_type +/// @tparam X size of 1st array index +/// @tparam Y size of 2nd array index +/// +template < proc_type P, size_t X, size_t Y > +struct DataSetterTraits2D; + +/// +/// @class DataSetterTraits - Nimbus, [PORT][DIMM] array specialization +/// @brief Traits for setting eff_config data +/// +template < > +struct DataSetterTraits2D < proc_type::NIMBUS, + mcTypeTraits<mc_type::NIMBUS>::PORTS_PER_MCS, + mcTypeTraits<mc_type::NIMBUS>::DIMMS_PER_PORT + > +{ + static constexpr fapi2::TargetType TARGET = fapi2::TARGET_TYPE_MCA; +}; + +/// +/// @brief Helper function to update a 2D array output +/// @tparam P proc_type +/// @tparam X size of 1st array index +/// @tparam Y size of 2nd array index +/// @tparam T Input/output data type +/// @tparam TT defaulted to DataSetterTraits2D<P, X, Y> +/// @param[in] i_target the DIMM target +/// @param[in] i_setting array to set +/// @param[in] i_ffdc_code FFDC function code +/// @param[out] o_data attribute data structure to set +/// @warning This is Nimbus specific until MCA alias to MEM_PORT +/// +template < proc_type P, + size_t X, + size_t Y, + typename T, + typename TT = DataSetterTraits2D<P, X, Y> + > +fapi2::ReturnCode update_data(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const T i_setting, + const generic_ffdc_codes i_ffdc_code, + T (&o_data)[X][Y]) +{ + // Currenlty only valid for a DIMM target, for Nimbus, traits enforces this at compile time + // Use case is currently for pre_eff_config which is supported in both Axone and Nimbus + const auto l_port_index = mss::index( find_target<TT::TARGET>(i_target) ); + const auto l_dimm_index = mss::index(i_target); + + FAPI_ASSERT( l_port_index < X, + fapi2::MSS_OUT_OF_BOUNDS_INDEXING() + .set_INDEX(l_port_index) + .set_LIST_SIZE(X) + .set_FUNCTION(i_ffdc_code) + .set_TARGET(i_target), + "Port index (%d) was larger than max (%d) on %s", + l_port_index, + X, + mss::spd::c_str(i_target) ); + + FAPI_ASSERT( l_dimm_index < Y, + fapi2::MSS_OUT_OF_BOUNDS_INDEXING() + .set_INDEX(l_dimm_index) + .set_LIST_SIZE(Y) + .set_FUNCTION(i_ffdc_code) + .set_TARGET(i_target), + "DIMM index (%d) was larger than max (%d) on %s", + l_dimm_index, + Y, + mss::spd::c_str(i_target) ); + + o_data[l_port_index][l_dimm_index] = i_setting; + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Sets attr data fields +/// @tparam P proc_type +/// @tparam TT data engine class traits (e.g. preDataInitTraits, etc.) +/// @tparam T FAPI2 target type +/// @tparam IT Input data type +/// @param[in] i_target the FAPI target +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< proc_type P, + typename TT, + fapi2::TargetType T, + typename IT > +inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target, + const IT i_setting) +{ + const auto l_attr_target = mss::find_target<TT::TARGET_TYPE>(i_target); + typename TT::attr_type l_attr_list = {}; + FAPI_TRY( TT::get_attr(l_attr_target, l_attr_list) ); + + FAPI_TRY( update_data<P>(i_target, i_setting, TT::FFDC_CODE, l_attr_list) ); + FAPI_TRY( TT::set_attr(l_attr_target, l_attr_list) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Sets preliminary data fields +/// @tparam P processor type (e.g. NIMBUS, AXONE, etc.) +/// @tparam F pre_data_init_fields +/// @tparam T FAPI2 target type +/// @tparam IT Input data type +/// @tparam TT defaulted to preDataInitTraits<T> +/// @param[in] i_setting value we want to set attr with +/// @return FAPI2_RC_SUCCESS iff okay +/// +template< proc_type P, + pre_data_init_fields F, + fapi2::TargetType T, + typename IT, + typename TT = preDataInitTraits<P, F> + > +inline fapi2::ReturnCode set_field(const fapi2::Target<T>& i_target, + const IT i_setting) +{ + FAPI_TRY( (set_field<P, TT>(i_target, i_setting)), + "Failed set_field() for %s", spd::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Data structure to set pre-effective config data +/// @class pre_data_engine +/// @tparam P supported processor type (e.g. Nimbus, Axone, etc.) +/// +template< proc_type P > +class pre_data_engine +{ + private: + + fapi2::Target<fapi2::TARGET_TYPE_DIMM> iv_dimm; + spd::facade iv_spd_data; + + public: + + static const std::vector<std::pair<uint8_t, uint8_t> > NUM_PACKAGE_RANKS_MAP; + static const std::vector<std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP; + static const std::vector<std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP; + static const std::vector<std::pair<uint8_t, uint8_t> > HYBRID_MAP; + static const std::vector<std::pair<uint8_t, uint8_t> > HYBRID_MEMORY_TYPE_MAP; + + /// + /// @brief ctor + /// @param[in] i_target the DIMM target + /// @param[in] i_spd_data SPD decoder + /// + pre_data_engine(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const spd::facade& i_spd_data): + iv_dimm(i_target), + iv_spd_data(i_spd_data) + {} + + /// + /// @brief default dtor + /// + ~pre_data_engine() = default; + + /// + /// @brief Set ATTR_EFF_DIMM_TYPE + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode set_dimm_type() + { + uint8_t l_base_module_type = 0; + uint8_t l_dimm_type = 0; + + FAPI_TRY(iv_spd_data.base_module(l_base_module_type)); + FAPI_TRY(lookup_table_check(iv_dimm, BASE_MODULE_TYPE_MAP, SET_ATTR_DIMM_TYPE, l_base_module_type, l_dimm_type)); + FAPI_TRY( (set_field<P, pre_data_init_fields::DIMM_TYPE>(iv_dimm, l_dimm_type)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Set ATTR_EFF_DRAM_GEN + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode set_dram_gen() + { + uint8_t l_device_type = 0; + uint8_t l_dram_gen = 0; + + FAPI_TRY(iv_spd_data.device_type(l_device_type)); + FAPI_TRY(lookup_table_check(iv_dimm, DRAM_GEN_MAP, SET_ATTR_DRAM_GEN, l_device_type, l_dram_gen)); + + FAPI_TRY( (set_field<P, pre_data_init_fields::DRAM_GEN>(iv_dimm, l_dram_gen)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Set ATTR_EFF_HYBRID + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode set_hybrid() + { + uint8_t l_spd_hybrid_type = 0; + uint8_t l_hybrid = 0; + + FAPI_TRY(iv_spd_data.hybrid(l_spd_hybrid_type)); + FAPI_TRY(lookup_table_check(iv_dimm, HYBRID_MAP, SET_ATTR_HYBRID, l_spd_hybrid_type, l_hybrid)); + + FAPI_TRY( (set_field<P, pre_data_init_fields::HYBRID>(iv_dimm, l_hybrid)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Set ATTR_EFF_HYBRID_MEMORY_TYPE + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode set_hybrid_media() + { + uint8_t l_hybrid_media = 0; + uint8_t l_spd_hybrid_media = 0; + + FAPI_TRY(iv_spd_data.hybrid_media(l_spd_hybrid_media)); + FAPI_TRY(lookup_table_check(iv_dimm, HYBRID_MAP, SET_ATTR_HYBRID, l_spd_hybrid_media, l_hybrid_media)); + + FAPI_TRY( (set_field<P, pre_data_init_fields::HYBRID_MEDIA>(iv_dimm, l_hybrid_media)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Set ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode set_master_ranks() + { + uint8_t l_master_ranks = 0; + FAPI_TRY( get_master_ranks(l_master_ranks) ); + + FAPI_TRY( (set_field<P, pre_data_init_fields::MRANKS>(iv_dimm, l_master_ranks)) ); + + fapi_try_exit: + return fapi2::current_err; + } + + /// + /// @brief Sets ATTR_EFF_DIMM_RANKS_CONFIGED + /// @return FAPI2_RC_SUCCESS iff okay + /// + fapi2::ReturnCode set_dimm_ranks_configured() + { + // Set configed ranks. Set the bit representing the master rank configured (0 being left most.) So, + // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD. + fapi2::buffer<uint8_t> l_ranks_configed; + + // Make sure the number of master ranks is setup + uint8_t l_master_ranks = 0; + FAPI_TRY( get_master_ranks(l_master_ranks) ); + + FAPI_TRY( l_ranks_configed.setBit(0, l_master_ranks), + "%s. Failed to setBit", spd::c_str(iv_dimm) ); + + FAPI_TRY( (set_field<P, pre_data_init_fields::DIMM_RANKS_CNFG>(iv_dimm, uint8_t(l_ranks_configed))) ); + + fapi_try_exit: + return fapi2::current_err; + } + + private: + + /// + /// @brief Gets master ranks from SPD + /// @param[out] o_output num package ranks per DIMM + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode get_master_ranks(uint8_t& o_output) + { + // Sets up commonly used member variables + uint8_t l_master_ranks_spd = 0; + FAPI_TRY(iv_spd_data.num_package_ranks_per_dimm(l_master_ranks_spd), + "%s failed to get number of package ranks from SPD", spd::c_str(iv_dimm)); + + FAPI_TRY(lookup_table_check(iv_dimm, NUM_PACKAGE_RANKS_MAP, PRE_DATA_ENGINE_CTOR, l_master_ranks_spd, + o_output), "%s failed MASTER_RANKS lookup check", spd::c_str(iv_dimm)); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Sets pre_eff_config attributes +/// @tparam P processor type +/// @param[in] i_target the DIMM target +/// @param[in] i_spd_decoder SPD decoder +/// @return FAPI2_RC_SUCCESS iff ok +/// +template <mss::proc_type P> +inline fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const spd::facade& i_spd_decoder ); + +/// +/// @brief Sets pre_eff_config attributes - NIMBUS specialization +/// @param[in] i_target the DIMM target +/// @param[in] i_spd_decoder SPD decoder +/// @return FAPI2_RC_SUCCESS iff ok +/// +template <> +inline fapi2::ReturnCode set_pre_init_attrs<mss::proc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& + i_target, + const spd::facade& i_spd_decoder ) +{ + // TK explicitly forcing this API to only run in Nimbus, need to move pre_data_engine to Nimbus chip path, + // using template recursive algorithm moving forward + mss::pre_data_engine<mss::proc_type::NIMBUS> l_data_engine(i_target, i_spd_decoder); + + // Set attributes needed before eff_config + // DIMM type and DRAM gen are needed for c_str to aid debugging + FAPI_TRY(l_data_engine.set_dimm_type(), "Failed to set DIMM type %s", mss::spd::c_str(i_target) ); + FAPI_TRY(l_data_engine.set_dram_gen(), "Failed to set DRAM gen %s", mss::spd::c_str(i_target) ); + + // Hybrid and hybrid media help detect hybrid modules, specifically NVDIMMs for Nimbus + FAPI_TRY(l_data_engine.set_hybrid(), "Failed to set Hybrid %s", mss::spd::c_str(i_target) ); + FAPI_TRY(l_data_engine.set_hybrid_media(), "Failed to set Hybrid Media %s", mss::spd::c_str(i_target) ); + + // Number of master ranks needed for VPD decoding + FAPI_TRY(l_data_engine.set_master_ranks(), "Failed to set Master ranks %s", mss::spd::c_str(i_target) ); + + // and dimm_ranks_configured is a PRD attr... + FAPI_TRY(l_data_engine.set_dimm_ranks_configured(), "Failed to set DIMM ranks configured %s", + mss::spd::c_str(i_target) ); + + // Adding metadata c-str fields derived from attrs set above + FAPI_TRY( (mss::gen::attr_engine<proc_type::NIMBUS, mss::generic_metadata_fields>::set(i_target)), + "Failed attr_engine<proc_type::NIMBUS, mss::generic_metadata_fields>::set for %s", mss::spd::c_str(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Sets pre_eff_config attributes +/// @tparam P processor type +/// @tparam T fapi2::TargetType +/// @param[in] i_target the target on which to operate +/// @return FAPI2_RC_SUCCESS iff ok +/// +template <mss::proc_type P, fapi2::TargetType T> +fapi2::ReturnCode set_pre_init_attrs( const fapi2::Target<T>& i_target ) +{ + for( const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) + { + std::vector<uint8_t> l_raw_spd; + FAPI_TRY(mss::spd::get_raw_data(d, l_raw_spd)); + { + // Gets the SPD facade + fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS); + mss::spd::facade l_spd_decoder(d, l_raw_spd, l_rc); + + // Checks that the facade was setup correctly + FAPI_TRY(l_rc, "Failed to initialize SPD facade for %s", mss::spd::c_str(d)); + + // Sets pre-init attributes + FAPI_TRY(mss::set_pre_init_attrs<P>(d, l_spd_decoder), "%s failed to set pre init attrs", mss::spd::c_str(d) ); + } + } + +fapi_try_exit: + return fapi2::current_err; +} + +}//mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C index ebc203f2e..ebf1650ea 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -31,173 +31,10 @@ #include <fapi2.H> #include <mss.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/eff_config/timing.H> namespace mss { -enum temp_mode : uint8_t -{ - NORMAL = 1, - EXTENDED = 2, -}; - -// Proposed DDR4 Full spec update(79-4B) -// Item No. 1716.78C -// pg.46 -// Table 24 - tREFI and tRFC parameters (in ps) -constexpr uint64_t TREFI_BASE = 7800000; - -// Proposed DDR4 3DS Addendum -// Item No. 1727.58A -// pg. 69 - 71 -// Table 42 - Refresh parameters by logical rank density -static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR1 = -{ - // { density in GBs, tRFC4(min) in picoseconds } - {4, 90000}, - {8, 120000}, - {16, 185000}, -}; - -// Proposed DDR4 3DS Addendum -// Item No. 1727.58A -// pg. 69 - 71 -// Table 42 - Refresh parameters by logical rank density -static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR2 = -{ - // { density in GBs, tRFC4(min) in picoseconds } - {4, 55000}, - {8, 90000}, - {16, 120000}, -}; - -// Proposed DDR4 3DS Addendum -// Item No. 1727.58A -// pg. 69 - 71 -// Table 42 - Refresh parameters by logical rank density -static const std::vector<std::pair<uint8_t, uint64_t> > TRFC_DLR4 = -{ - // { density in GBs, tRFC4(min) in picoseconds } - {4, 40000}, - {8, 55000}, - {16, 90000}, -}; - -/// -/// @brief Calculates refresh interval time -/// @param[in] i_mode fine refresh rate mode -/// @param[in] i_refresh_request_rate refresh rate -/// @param[out] o_value timing val in ps -/// @return fapi2::ReturnCode -/// -fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, - const uint8_t i_refresh_request_rate, - uint64_t& o_timing ) -{ - uint64_t l_refresh_request = 0; - constexpr double TEN_PERCENT_FASTER = 0.90; - - switch(i_refresh_request_rate) - { - case fapi2::ENUM_ATTR_MSS_MRW_REFRESH_RATE_REQUEST_SINGLE: - l_refresh_request = TREFI_BASE; - break; - - case fapi2::ENUM_ATTR_MSS_MRW_REFRESH_RATE_REQUEST_DOUBLE: - // We are truncating but there is no remainder with TREFI_BASE, so we are okay - l_refresh_request = TREFI_BASE / 2; - break; - - case fapi2::ENUM_ATTR_MSS_MRW_REFRESH_RATE_REQUEST_SINGLE_10_PERCENT_FASTER: - // We are truncating but there is no remainder with TREFI_BASE, so we are okay - // 10% faster so 100% - 10% = 90% - l_refresh_request = TREFI_BASE * TEN_PERCENT_FASTER; - break; - - case fapi2::ENUM_ATTR_MSS_MRW_REFRESH_RATE_REQUEST_DOUBLE_10_PERCENT_FASTER: - // We are truncating but there is no remainder with TREFI_BASE, so we are okay - // 10% faster so 100% - 10% = 90% - l_refresh_request = (TREFI_BASE / 2) * TEN_PERCENT_FASTER; - break; - - default: - // Will catch incorrect MRW value set - FAPI_ASSERT(false, - fapi2::MSS_INVALID_REFRESH_RATE_REQUEST().set_REFRESH_RATE_REQUEST(i_refresh_request_rate), - "Incorrect refresh request rate received: %d ", i_refresh_request_rate); - break; - } - - o_timing = (l_refresh_request / i_mode); - - FAPI_INF( "tREFI (ps): %d, refresh request (ps): %d, tREFI_base (ps): %d, REF%dX", - o_timing, l_refresh_request, TREFI_BASE, i_mode ); - - // FAPI_ASSERT doesn't set current_err as good - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) -/// @param[in] i_mode fine refresh rate mode -/// @param[in] i_density SDRAM density -/// @param[out] o_trfc_in_ps timing val in ps -/// @return fapi2::FAPI2_RC_SUCCESS iff okay -/// -fapi2::ReturnCode calc_trfc_dlr(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_refresh_mode, - const uint8_t i_density, - uint64_t& o_trfc_in_ps) -{ - bool l_is_val_found = 0; - - // Selects appropriate tRFC based on fine refresh mode - switch(i_refresh_mode) - { - case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_NORMAL: - l_is_val_found = find_value_from_key(TRFC_DLR1, i_density, o_trfc_in_ps); - break; - - case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_2X: - case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_2X: - l_is_val_found = find_value_from_key(TRFC_DLR2, i_density, o_trfc_in_ps); - break; - - case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FIXED_4X: - case fapi2::ENUM_ATTR_MSS_MRW_FINE_REFRESH_MODE_FLY_4X: - l_is_val_found = find_value_from_key(TRFC_DLR4, i_density, o_trfc_in_ps); - break; - - default: - // Fine Refresh Mode will be a platform attribute set by the MRW, - // which they "shouldn't" mess up as long as use "attribute" enums. - // if openpower messes this up we can at least catch it - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FINE_REFRESH() - .set_REFRESH_MODE(i_refresh_mode), - "Incorrect Fine Refresh Mode received: %d ", - i_refresh_mode); - break; - }// switch - - FAPI_ASSERT( l_is_val_found, - fapi2::MSS_FAILED_TO_FIND_TRFC() - .set_SDRAM_DENSITY(i_density) - .set_REFRESH_MODE(i_refresh_mode) - .set_DIMM_TARGET(i_target), - "%s: Unable to find tRFC (ps) from map with SDRAM density key %d with %d refresh mode", - mss::c_str(i_target), - i_density, - i_refresh_mode); - - // Again, FAPI_ASSERT doesn't set current_err to good, only to bad - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - }// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H index 8b8215b96..e09fa1a17 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/timing.H @@ -38,106 +38,15 @@ #include <cstdint> #include <fapi2.H> #include <lib/mss_attribute_accessors.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/dimm/mss_timing.H> #include <lib/utils/mss_nimbus_conversions.H> namespace mss { /// -/// @brief Enums for ffdc error callout so we know which function had the error -/// -enum functions -{ - TRAS = 0, - TFAW_HALF_KB_PAGE_HELPER = 1, - TFAW_ONE_KB_PAGE_HELPER = 2, - TFAW_TW_KB_PAGE_HELPER = 3, - TFAW_SLR_X4_HELPER = 4, - TFAW_SLR_X8_HELPER = 5, - TRRD_S_SLR = 6, - TRRD_L_SLR = 7, - TRRD_L_HALF_AND_1KB_PAGE_HELPER = 8, - TRRD_S_HALF_AND_1KB_PAGE_HELPER = 9, - TRRD_S_2KB_PAGE_HELPER = 10, - TDLLK = 11, -}; - -enum refresh_rate : uint8_t -{ - REF1X = 1, ///< Refresh rate 1X - REF2X = 2, ///< Refresh rate 2X - REF4X = 4, ///< Refresh rate 4X -}; - -namespace spd -{ - -/// -/// @brief Returns clock cycles form picoseconds based on speed bin -/// Uses SPD rounding algorithm for DDR4 -/// @tparam T the target type from which to get the mt/s -/// @tparam OT the output type, derrived from the parameters -/// @param[in] i_target target for the frequency attribute -/// @param[in] timing_in_ps timing parameter in ps -/// @return the clock cycles of timing parameter (provided in ps) -/// @note Uses DDR4 SPD Contents Rounding Algorithm -/// @note Item 2220.46 -/// -template<fapi2::TargetType T, typename OT> -inline OT ps_to_nck( const fapi2::Target<T>& i_target, const OT& i_timing_in_ps) -{ - uint64_t l_freq = 0; - OT l_tck_in_ps = 0; - OT l_temp_nck = 0; - - FAPI_TRY( mss::freq( find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq) ); - - // No time if MT/s is 0 (well, infinite really but shut up) - if (l_freq == 0) - { - return 0; - } - - FAPI_TRY( freq_to_ps(l_freq, l_tck_in_ps), - "Failed freq() accessor" ); - FAPI_TRY( calc_nck(i_timing_in_ps, l_tck_in_ps, spd::INVERSE_DDR4_CORRECTION_FACTOR, l_temp_nck), - "Failed calc_nck()" ); - - return l_temp_nck; - -fapi_try_exit: - // We simply can't work if we can't get the frequency or - // if we get an unsupported value that can't be converted to a valid tCK (clock period) - // ...so this should be ok - FAPI_ERR("Can't get MSS_FREQ, obtained an invalid MSS_FREQ (%d), or overflow occurred - stopping", l_freq); - fapi2::Assert(false); - - // Keeps compiler happy - return 0; -} - -/// -/// @brief Returns clock cycles from nanoseconds -/// Uses SPD rounding algorithm for DDR4 -/// @tparam T the target type from which to get the mt/s -/// @tparam OT the output type, derrived from the parameters -/// @param[in] timing_in_ps timing parameter in ps -/// @param[out] o_value_nck the end calculation in nck -/// @return the clock cycles of timing parameter (provided in ps)F -/// @note Uses DDR4 SPD Contents Rounding Algorithm -/// @note Item 2220.46 -/// -template<fapi2::TargetType T, typename OT> -inline OT ns_to_nck( const fapi2::Target<T>& i_target, const OT& i_timing_in_ns) -{ - return ps_to_nck(i_target, i_timing_in_ns * CONVERT_PS_IN_A_NS); -} - -}// spd - -/// /// @brief Returns application clock period (tCK) based on dimm transfer rate /// @tparam T the fapi2 target /// @tparam OT output type @@ -159,30 +68,6 @@ fapi_try_exit: } /// -/// @brief Calculates refresh interval time -/// @param[in] i_mode fine refresh rate mode -/// @param[in] i_temp_refresh_range temperature refresh range -/// @param[out] o_value timing val in ps -/// @return fapi2::ReturnCode -/// -fapi2::ReturnCode calc_trefi( const refresh_rate i_mode, - const uint8_t i_temp_refresh_range, - uint64_t& o_timing ); - -/// -/// @brief Calculates Minimum Refresh Recovery Delay Time (different logical rank) -/// @param[in] i_target a target for attributes -/// @param[in] i_mode fine refresh rate mode -/// @param[in] i_density SDRAM density -/// @param[out] o_trfc_in_ps timing val in ps -/// @return fapi2::FAPI2_RC_SUCCESS iff okay -/// -fapi2::ReturnCode calc_trfc_dlr( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_refresh_mode, - const uint8_t i_density, - uint64_t& o_trfc_in_ps ); - -/// /// @brief DLL locking time *in clocks* /// @tparam T the fapi2::TargetType of i_target /// @tparam OT the type of the output location @@ -582,602 +467,6 @@ fapi_try_exit: } /// -/// @brief tRTP *in ps* -/// @return constexpr value of RTP = 7500 ps -/// -constexpr uint64_t trtp() -{ - // Per JEDEC spec, defaults to 7500 ps for all frequencies. - // (technically max of 7.5 ns or 4 nclk, which is always 7.5ns for DDR4) - return 7500; -} - -/// -/// @brief Return the minimum allowable tRAS in picoseconds -/// @param[in] i_target the fapi2 target -/// @return value in picoseconds -/// -inline uint64_t tras(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) -{ - uint64_t l_freq = 0; - uint64_t l_tras = 0; - - // Frequency is used to determine tRAS - FAPI_TRY( freq(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq) ); - - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - l_tras = 34000; - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - l_tras = 33000; - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - l_tras = 32000; - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TRAS) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - } - - return l_tras; - -fapi_try_exit: - - // We simply can't work if we can't get the frequency or - // if we get an unsupported value that can't be converted to a valid tCK (clock period) - // ...so this should be ok - FAPI_ERR("Can't get MSS_FREQ or obtained an invalid MSS_FREQ (%d) - stopping", l_freq); - fapi2::Assert(false); - - // Keeps compiler happy - return 0; -} - -/// -/// @brief Helper function to find tFAW based speed (MT/s) for 1/2 KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode tfaw_half_kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability. - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - // static_cast is needed for template deduction of std::max API - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - o_output = std::max( 16, spd::ns_to_nck(i_target, 17) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - o_output = std::max( 16, spd::ns_to_nck(i_target, 15) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - o_output = std::max( 16, spd::ns_to_nck(i_target, 13) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 16, spd::ns_to_nck(i_target, 12) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TFAW_HALF_KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function to find tFAW based speed (MT/s) for 1KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode tfaw_1kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability (and ease of debug?). - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - o_output = std::max( 20, spd::ns_to_nck(i_target, 23) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 20, spd::ns_to_nck(i_target, 21) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TFAW_ONE_KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - break; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function to find tFAW based speed (MT/s) for 2KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode tfaw_2kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability. - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 28, spd::ns_to_nck(i_target, 30) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TFAW_TW_KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - break; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return the minimum allowable tFAW in nck -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[in] i_dram_width the page size -/// @param[out] o_tFAW timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -// -template< fapi2::TargetType T > -fapi2::ReturnCode tfaw( const fapi2::Target<T>& i_target, - const uint8_t i_dram_width, - uint64_t& o_tFAW ) -{ - switch(i_dram_width) - { - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4: - FAPI_TRY( tfaw_half_kb_page_helper(i_target, o_tFAW) ); - break; - - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8: - FAPI_TRY( tfaw_1kb_page_helper(i_target, o_tFAW) ); - break; - - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16: - FAPI_TRY( tfaw_2kb_page_helper(i_target, o_tFAW) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_DRAM_WIDTH() - .set_DRAM_WIDTH(i_dram_width) - .set_DIMM_TARGET(i_target), - "Invalid DRAM width with %d for target %s", - i_dram_width, - mss::c_str(i_target)); - break; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief tFAW_dlr *in nck* -/// @return 16nck -/// @note From DDR4 3DS Spec -/// 12.2 Timing Parameters by Speed Grade -/// -constexpr uint64_t tfaw_dlr() -{ - return 16; -} - -/// -/// @brief tRRD_dlr *in nck* -/// @return 4nck -/// @note From DDR4 3DS Spec -/// 12.2 Timing Parameters by Speed Grade -/// -constexpr uint64_t trrd_dlr() -{ - return 4; -} - -/// -/// @brief Helper function to find tRRD_L based speed (MT/s) for 1KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode trrd_l_half_and_1kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability (and ease of debug?). - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - // From the spec: Max(4nCK,5.3ns) - o_output = std::max( 4, spd::ps_to_nck(i_target, 5300) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - // Max(4nCK,4.9ns) - o_output = std::max( 4, spd::ps_to_nck(i_target, 4900) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TRRD_L_HALF_AND_1KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function to find tRRD_L based speed (MT/s) for 2KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode trrd_l_2kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability (and ease of debug?). - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 4, spd::ps_to_nck(i_target, 6400) ); - break; - - default: - FAPI_TRY(fapi2::FAPI2_RC_INVALID_PARAMETER, "%s Invalid frequency %lu", mss::c_str(i_target), l_freq); - break; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return the minimum allowable tRRD_L in nck -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[in] i_dram_width the page size -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -fapi2::ReturnCode trrd_l( const fapi2::Target<T>& i_target, - const uint8_t i_dram_width, - uint64_t& o_tRRD_L ) -{ - switch(i_dram_width) - { - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4: - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8: - FAPI_TRY( trrd_l_half_and_1kb_page_helper(i_target, o_tRRD_L), "Error calculating trrd l for half and 1kb page" ); - break; - - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16: - FAPI_TRY( trrd_l_2kb_page_helper(i_target, o_tRRD_L) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_PAGE_SIZE() - .set_DRAM_WIDTH(i_dram_width) - .set_DIMM_TARGET(i_target), - "%s Recieved an invalid page size: %lu", - mss::c_str(i_target), - i_dram_width); - break; - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function to find tRRD_S based speed (MT/s) for 1KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode trrd_s_half_and_1kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability (and ease of debug?). - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - o_output = std::max( 4, spd::ps_to_nck(i_target, 4200) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - o_output = std::max( 4, spd::ps_to_nck(i_target, 3700) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - o_output = std::max( 4, spd::ps_to_nck(i_target, 3300) ); - break; - - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 4, spd::ps_to_nck(i_target, 3000) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TRRD_S_HALF_AND_1KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Helper function to find tRRD_S based speed (MT/s) for 2KB page -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[out] o_output timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -static fapi2::ReturnCode trrd_s_2kb_page_helper(const fapi2::Target<T>& i_target, - uint64_t& o_output) -{ - // Values derived from DDR4 Spec (79-4A) - // 13.3 Timing Parameters by Speed Grade - // Table 132. Pg 240 - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - uint64_t l_freq = 0; - FAPI_TRY( freq(find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq), - "Failed to invoke freq accessor" ); - - // It could have been more "efficient" to hand-calculate the answer and - // use compile time constants to return the answer. To avoid magic - // numbers and to align (more closely) with the DDR4 JEDEC spec, - // we let the std library do the work for us for maintainability (and ease of debug?). - // Could have used compile-time constants to denote the numbers below - // but they are "random" and vary. - switch(l_freq) - { - case fapi2::ENUM_ATTR_MSS_FREQ_MT1866: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2133: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2400: - case fapi2::ENUM_ATTR_MSS_FREQ_MT2666: - o_output = std::max( 4, spd::ps_to_nck(i_target, 5300) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_FREQ_PASSED_IN() - .set_FREQ(l_freq) - .set_FUNCTION(TRRD_S_2KB_PAGE_HELPER) - .set_DIMM_TARGET(i_target), - "%s Invalid frequency %lu", - mss::c_str(i_target), - l_freq); - break; - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return the minimum allowable tRRD_S in nck -/// @tparam T the fapi2::TargetType of a type from which we can get MT/s -/// @param[in] i_target the fapi2 target -/// @param[in] i_dram_width the page size -/// @param[out] o_tRRD_S timing in clocks (nck) -/// @return FAPI2_RC_SUCCESS iff okay -/// @note this is only for non-3DS DIMM -/// -template< fapi2::TargetType T > -fapi2::ReturnCode trrd_s( const fapi2::Target<T>& i_target, - const uint8_t i_dram_width, - uint64_t& o_tRRD_S ) -{ - switch(i_dram_width) - { - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4: - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8: - FAPI_TRY( trrd_s_half_and_1kb_page_helper(i_target, o_tRRD_S), "Error calculating trrd_s for half and 1kb page" ); - break; - - case fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16: - FAPI_TRY( trrd_s_2kb_page_helper(i_target, o_tRRD_S) ); - break; - - default: - FAPI_ASSERT( false, - fapi2::MSS_INVALID_PAGE_SIZE() - .set_DRAM_WIDTH(i_dram_width) - .set_DIMM_TARGET(i_target), - "%s Recieved an invalid page size: %lu", - mss::c_str(i_target), - i_dram_width); - break; - } - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief VREF DQ Enter time *in clocks* /// @tparam T the fapi2::TargetType of i_target /// @param[in] i_target a target for attributes @@ -1215,25 +504,5 @@ constexpr uint64_t tccd_s() return 4; } -namespace lrdimm -{ - -/// -/// @brief Return the VREF to VREF change time long -/// @tparam fapi2::TargetType T - type of the target on which to operate -/// @param[in] i_target the fapi2 target -/// @return value in clocks -/// @note VREF time change long is used for changing by more than one VREF tick -/// -template< fapi2::TargetType T > -inline uint64_t vref_time_long(const fapi2::Target<T>& i_target) -{ - // Taken from the LRDIMM spec - constexpr uint64_t VREF_TIME_LONG_NS = 500; - return mss::spd::ns_to_nck(i_target, VREF_TIME_LONG_NS); -} - -} // ns lrdimm - } // mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C index de7b6003b..224dfc050 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/check.C @@ -38,12 +38,12 @@ #include <p9_mc_scom_addresses_fld.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> -#include <generic/memory/lib/utils/find_magic.H> +#include <lib/utils/find_magic.H> #include <generic/memory/lib/utils/scom.H> #include <lib/fir/fir.H> #include <lib/fir/check.H> #include <generic/memory/lib/utils/assert_noexit.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C deleted file mode 100644 index f4ab6727c..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C +++ /dev/null @@ -1,175 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file memdiags_fir.C -/// @brief Subroutines for memdiags/prd FIR -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#include <lib/shared/nimbus_defaults.H> -#include <fapi2.H> -#include <p9_mc_scom_addresses.H> -#include <p9_mc_scom_addresses_fld.H> - -#include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/fir/fir.H> -#include <lib/fir/memdiags_fir.H> -#include <lib/mc/port.H> -#include <lib/workarounds/mcbist_workarounds.H> - -using fapi2::TARGET_TYPE_MCBIST; -using fapi2::TARGET_TYPE_MCA; - -namespace mss -{ - -namespace unmask -{ - -/// -/// @brief Unmask and setup actions for memdiags related FIR -/// @param[in] i_target the fapi2::Target MCBIST -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template<> -fapi2::ReturnCode after_memdiags( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) -{ - fapi2::ReturnCode l_rc; - fapi2::buffer<uint64_t> dsm0_buffer; - fapi2::buffer<uint64_t> l_mnfg_buffer; - uint64_t rd_tag_delay = 0; - uint64_t wr_done_delay = 0; - fapi2::buffer<uint64_t> l_aue_buffer; - fapi2::ATTR_CHIP_EC_FEATURE_HW414700_Type l_checkstop_flag; - constexpr uint64_t MNFG_THRESHOLDS_ATTR = 63; - - // Broadcast mode workaround for UEs causing out of sync - FAPI_TRY(mss::workarounds::mcbist::broadcast_out_of_sync(i_target, mss::ON)); - - for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) - { - fir::reg<MCA_FIR> l_ecc64_fir_reg(p, l_rc); - FAPI_TRY(l_rc, "unable to create fir::reg for %d", MCA_FIR); - - fir::reg<MCA_MBACALFIRQ> l_cal_fir_reg(p, l_rc); - FAPI_TRY(l_rc, "unable to create fir::reg for %d", MCA_MBACALFIRQ); - - // Read out the wr_done and rd_tag delays and find min - // and set the RCD Protect Time to this value - FAPI_TRY (mss::read_dsm0q_register(p, dsm0_buffer) ); - mss::get_wrdone_delay(dsm0_buffer, wr_done_delay); - mss::get_rdtag_delay(dsm0_buffer, rd_tag_delay); - const auto rcd_protect_time = std::min(wr_done_delay, rd_tag_delay); - FAPI_TRY (mss::change_rcd_protect_time(p, rcd_protect_time) ); - - l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_AUE>() - .recoverable_error<MCA_FIR_MAINLINE_UE>() - .checkstop<MCA_FIR_MAINLINE_IAUE>() - .recoverable_error<MCA_FIR_MAINLINE_IUE>(); - - l_cal_fir_reg.recoverable_error<MCA_MBACALFIRQ_PORT_FAIL>(); - - // If ATTR_CHIP_EC_FEATURE_HW414700 is enabled set checkstops - auto l_chip_target = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, l_chip_target, l_checkstop_flag) ); - - // If the system is running DD2 chips override some recoverable firs with checkstop - // Due to a known hardware defect with DD2 certain errors are not handled properly - // As a result, these firs are marked as checkstop for DD2 to avoid any mishandling - if (l_checkstop_flag) - { - l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_UE>() - .checkstop<MCA_FIR_MAINLINE_RCD>(); - l_cal_fir_reg.checkstop<MCA_MBACALFIRQ_PORT_FAIL>(); - } - - // If MNFG FLAG Threshhold is enabled skip IUE unflagging - FAPI_TRY ( mss::mnfg_flags(l_mnfg_buffer) ); - - if ( !(l_mnfg_buffer.getBit<MNFG_THRESHOLDS_ATTR>()) ) - { - l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINTENANCE_IUE>(); - } - - FAPI_TRY(l_ecc64_fir_reg.write(), "unable to write fir::reg %d", MCA_FIR); - FAPI_TRY(l_cal_fir_reg.write(), "unable to write fir::reg %d", MCA_MBACALFIRQ); - - // Change Maint AUE and IAUE to checkstop without unmasking - // Normal setup modifies masked bits in addition to setting checkstop - // This causes issues if error has occured, manually scoming to avoid this - FAPI_TRY( mss::getScom(p, MCA_ACTION1, l_aue_buffer) ); - l_aue_buffer.clearBit<MCA_FIR_MAINTENANCE_AUE>(); - l_aue_buffer.clearBit<MCA_FIR_MAINTENANCE_IAUE>(); - FAPI_TRY( mss::putScom(p, MCA_ACTION1, l_aue_buffer) ); - - // Note: We also want to include the following setup RCD recovery and port fail - FAPI_TRY( mss::change_port_fail_disable(p, mss::LOW) ); - FAPI_TRY( mss::change_rcd_recovery_disable(p, mss::LOW) ); - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Unmask and setup actions for scrub related FIR -/// @param[in] i_target the fapi2::Target MCBIST -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template<> -fapi2::ReturnCode after_background_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) -{ - for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) - { - fapi2::ReturnCode l_rc; - fir::reg<MCA_FIR> l_ecc64_fir_reg(p, l_rc); - FAPI_TRY(l_rc, "unable to create fir::reg for %d", MCA_FIR); - - l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINLINE_MPE_RANK_0_TO_7, - MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN>() - .recoverable_error<MCA_FIR_MAINLINE_NCE>() - .recoverable_error<MCA_FIR_MAINLINE_TCE>() - .recoverable_error<MCA_FIR_MAINLINE_IMPE>() - .recoverable_error<MCA_FIR_MAINTENANCE_IMPE>(); - - FAPI_TRY(l_ecc64_fir_reg.write(), "unable to write fir::reg %d", MCA_FIR); - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -} -} diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C index 3d28935f8..744e7412f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.C @@ -37,9 +37,11 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> -#include <generic/memory/lib/utils/find_magic.H> +#include <lib/utils/find_magic.H> #include <generic/memory/lib/utils/scom.H> +#include <lib/utils/nimbus_find.H> #include <lib/fir/fir.H> +#include <lib/mc/port.H> #include <lib/fir/unmask.H> #include <lib/workarounds/mcbist_workarounds.H> @@ -80,8 +82,6 @@ fapi2::ReturnCode after_draminit_mc<mss::mc_type::NIMBUS>( const fapi2::Target<T // Broadcast mode workaround for UEs causing out of sync FAPI_TRY(mss::workarounds::mcbist::broadcast_out_of_sync(i_target, mss::OFF)); - FAPI_TRY(mss::workarounds::mcbist::wat_debug_attention(i_target)); - for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) { fir::reg<MCA_FIR> l_mca_fir_reg(p, l_rc); @@ -252,5 +252,125 @@ fapi_try_exit: } + +/// +/// @brief Unmask and setup actions for memdiags related FIR +/// @param[in] i_target the fapi2::Target MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_memdiags<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) +{ + fapi2::ReturnCode l_rc1, l_rc2; + fapi2::buffer<uint64_t> dsm0_buffer; + fapi2::buffer<uint64_t> l_mnfg_buffer; + uint64_t rd_tag_delay = 0; + uint64_t wr_done_delay = 0; + fapi2::buffer<uint64_t> l_aue_buffer; + fapi2::ATTR_CHIP_EC_FEATURE_HW414700_Type l_checkstop_flag; + constexpr uint64_t MNFG_THRESHOLDS_ATTR = 63; + + // Broadcast mode workaround for UEs causing out of sync + FAPI_TRY(mss::workarounds::mcbist::broadcast_out_of_sync(i_target, mss::ON)); + + for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) + { + fir::reg<MCA_FIR> l_ecc64_fir_reg(p, l_rc1); + fir::reg<MCA_MBACALFIRQ> l_cal_fir_reg(p, l_rc2); + uint64_t rcd_protect_time = 0; + const auto l_chip_target = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); + + FAPI_TRY(l_rc1, "unable to create fir::reg for %d", MCA_FIR); + FAPI_TRY(l_rc2, "unable to create fir::reg for %d", MCA_MBACALFIRQ); + + // Read out the wr_done and rd_tag delays and find min + // and set the RCD Protect Time to this value + FAPI_TRY (mss::read_dsm0q_register(p, dsm0_buffer) ); + mss::get_wrdone_delay(dsm0_buffer, wr_done_delay); + mss::get_rdtag_delay(dsm0_buffer, rd_tag_delay); + rcd_protect_time = std::min(wr_done_delay, rd_tag_delay); + FAPI_TRY (mss::change_rcd_protect_time(p, rcd_protect_time) ); + + l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_AUE>() + .recoverable_error<MCA_FIR_MAINLINE_UE>() + .checkstop<MCA_FIR_MAINLINE_IAUE>() + .recoverable_error<MCA_FIR_MAINLINE_IUE>(); + + l_cal_fir_reg.recoverable_error<MCA_MBACALFIRQ_PORT_FAIL>(); + + // If ATTR_CHIP_EC_FEATURE_HW414700 is enabled set checkstops + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW414700, l_chip_target, l_checkstop_flag) ); + + // If the system is running DD2 chips override some recoverable firs with checkstop + // Due to a known hardware defect with DD2 certain errors are not handled properly + // As a result, these firs are marked as checkstop for DD2 to avoid any mishandling + if (l_checkstop_flag) + { + l_ecc64_fir_reg.checkstop<MCA_FIR_MAINLINE_UE>() + .checkstop<MCA_FIR_MAINLINE_RCD>(); + l_cal_fir_reg.checkstop<MCA_MBACALFIRQ_PORT_FAIL>(); + } + + // If MNFG FLAG Threshhold is enabled skip IUE unflagging + FAPI_TRY ( mss::mnfg_flags(l_mnfg_buffer) ); + + if ( !(l_mnfg_buffer.getBit<MNFG_THRESHOLDS_ATTR>()) ) + { + l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINTENANCE_IUE>(); + } + + FAPI_TRY(l_ecc64_fir_reg.write(), "unable to write fir::reg %d", MCA_FIR); + FAPI_TRY(l_cal_fir_reg.write(), "unable to write fir::reg %d", MCA_MBACALFIRQ); + + // Change Maint AUE and IAUE to checkstop without unmasking + // Normal setup modifies masked bits in addition to setting checkstop + // This causes issues if error has occured, manually scoming to avoid this + FAPI_TRY( mss::getScom(p, MCA_ACTION1, l_aue_buffer) ); + l_aue_buffer.clearBit<MCA_FIR_MAINTENANCE_AUE>(); + l_aue_buffer.clearBit<MCA_FIR_MAINTENANCE_IAUE>(); + FAPI_TRY( mss::putScom(p, MCA_ACTION1, l_aue_buffer) ); + + // Note: We also want to include the following setup RCD recovery and port fail + FAPI_TRY( mss::change_port_fail_disable(p, mss::LOW) ); + FAPI_TRY( mss::change_rcd_recovery_disable(p, mss::LOW) ); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Unmask and setup actions for scrub related FIR +/// @param[in] i_target the fapi2::Target MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_background_scrub<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target ) +{ + for (const auto& p : mss::find_targets<TARGET_TYPE_MCA>(i_target)) + { + fapi2::ReturnCode l_rc; + fir::reg<MCA_FIR> l_ecc64_fir_reg(p, l_rc); + FAPI_TRY(l_rc, "unable to create fir::reg 0x%016lx for %s", MCA_FIR, mss::c_str(p)); + + l_ecc64_fir_reg.recoverable_error<MCA_FIR_MAINLINE_MPE_RANK_0_TO_7, + MCA_FIR_MAINLINE_MPE_RANK_0_TO_7_LEN>() + .recoverable_error<MCA_FIR_MAINLINE_NCE>() + .recoverable_error<MCA_FIR_MAINLINE_TCE>() + .recoverable_error<MCA_FIR_MAINLINE_IMPE>() + .recoverable_error<MCA_FIR_MAINTENANCE_IMPE>(); + + FAPI_TRY(l_ecc64_fir_reg.write(), "unable to write fir::reg 0x%016lx for %s", MCA_FIR, mss::c_str(p)); + } + + return fapi2::FAPI2_RC_SUCCESS; + +fapi_try_exit: + return fapi2::current_err; +} + } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H index 7a4d271bc..a6ae3863f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/fir/unmask.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -45,7 +45,57 @@ namespace mss namespace unmask { +/// +/// @brief Unmask and setup actions performed after draminit_mc +/// @param[in] i_target the fapi2::Target of the MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_draminit_mc<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + +/// +/// @brief Unmask and setup actions performed after draminit_training +/// @param[in] i_target the fapi2::Target of the MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_draminit_training<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target ); +/// +/// @brief Unmask and setup actions performed after mss_scominit +/// (yeah, it's clearing bits - it's ok) +/// @param[in] i_target the fapi2::Target of the MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_scominit<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + +/// +/// @brief Unmask and setup actions performed after mss_ddr_phy_reset +/// @param[in] i_target the fapi2::Target of the MCBIST +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_phy_reset<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + + +/// +/// @brief Unmask and setup actions for memdiags related FIR +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_memdiags<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + +/// +/// @brief Unmask and setup actions for scrub related FIR +/// @param[in] i_target the fapi2::Target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// +template<> +fapi2::ReturnCode after_background_scrub<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target ); } } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/nimbus_freq_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/freq/nimbus_freq_traits.H index 4818eeeb1..9ef0fc6a3 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/nimbus_freq_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/nimbus_freq_traits.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -57,6 +57,7 @@ class frequency_traits<mss::proc_type::NIMBUS> ////////////////////////////////////////////////////////////// static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MCA; static constexpr fapi2::TargetType FREQ_TARGET_TYPE = fapi2::TARGET_TYPE_MCBIST; + static constexpr fapi2::TargetType FREQ_DOMAIN_TARGET_TYPE = fapi2::TARGET_TYPE_MCBIST; static constexpr fapi2::TargetType VPD_TARGET_TYPE = fapi2::TARGET_TYPE_MCS; ////////////////////////////////////////////////////////////// diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C index 8c9b1ccc5..277847f73 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/freq/sync.C @@ -46,7 +46,7 @@ // Generic libraries #include <generic/memory/lib/utils/assert_noexit.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/spd/spd_facade.H> #include <generic/memory/lib/spd/spd_utils.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C index c56b1ff90..a37418f13 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.C @@ -34,9 +34,11 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> -#include <lib/utils/dump_regs.H> + +#include <lib/shared/nimbus_defaults.H> +#include <generic/memory/lib/utils/dump_regs.H> #include <lib/mc/mc.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCS; @@ -88,8 +90,7 @@ fapi2::ReturnCode set_pwr_cntrl_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& uint8_t l_pwr_cntrl = 0; fapi2::buffer<uint64_t> l_data; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_pwr_cntrl), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(mrw_power_control_requested(l_pwr_cntrl), "Error in set_pwr_cntrl_reg"); FAPI_TRY(read_mbarpc0(i_target, l_data)); l_data.insertFromRight<TT::CFG_MIN_MAX_DOMAINS, TT::CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MINALL); @@ -138,8 +139,7 @@ fapi2::ReturnCode set_str_reg(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_tar uint8_t l_str_enable = 0; fapi2::buffer<uint64_t> l_data; - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_str_enable), "Error in set_pwr_cntrl_reg"); + FAPI_TRY(mrw_power_control_requested(l_str_enable), "Error in set_pwr_cntrl_reg"); FAPI_TRY(read_mbastr0(i_target, l_data)); //Write bit if STR should be enabled diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H index fdef40a8d..b589c0479 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/mc.H @@ -41,7 +41,7 @@ #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> #include <lib/mss_attribute_accessors.H> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/scom.H> @@ -123,6 +123,7 @@ class mcTraits<fapi2::TARGET_TYPE_MCA> EMERGENCY_M = MCA_MBA_FARB4Q_EMERGENCY_M, EMERGENCY_M_LEN = MCA_MBA_FARB4Q_EMERGENCY_M_LEN, CFG_STR_ENABLE = MCA_MBASTR0Q_CFG_STR_ENABLE, + CFG_STR_STATE = MCA_MBA_FARB6Q_CFG_STR_STATE, MIN_DOMAIN_REDUCTION_ENABLE = MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE, MIN_MAX_DOMAINS_ENABLE = MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE, @@ -189,6 +190,43 @@ enum namespace mc { +/// +/// @brief Reads the contents of the FARB6Q +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to mcTraits<T> +/// @param[in] i_target the target on which to operate +/// @param[out] o_data the register data +/// @return fapi2::fapi2_rc_success if ok +/// +template< fapi2::TargetType T, typename TT = mcTraits<T> > +inline fapi2::ReturnCode read_farb6q( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +{ + o_data = 0; + + FAPI_TRY( mss::getScom(i_target, TT::FARB6Q, o_data ), "%s failed to read FARB6Q regiser", mss::c_str(i_target)); + FAPI_DBG("%s FARB6Q has data 0x%016lx", mss::c_str(i_target), o_data); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Writes the contents of the FARB6Q +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to mcTraits<T> +/// @param[in] i_target the target on which to operate +/// @param[in] i_data the register data +/// @return fapi2::fapi2_rc_success if ok +/// +template< fapi2::TargetType T, typename TT = mcTraits<T> > +inline fapi2::ReturnCode write_farb6q( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) +{ + FAPI_TRY( mss::putScom(i_target, TT::FARB6Q, i_data ), "%s failed to write FARB6Q regiser", mss::c_str(i_target)); + FAPI_DBG("%s FARB6Q has data 0x%016lx", mss::c_str(i_target), i_data); + +fapi_try_exit: + return fapi2::current_err; +} /// /// @brief Reads the contents of the MBARPC0 @@ -407,6 +445,20 @@ inline void get_enter_self_time_refresh_time( const fapi2::buffer<uint64_t>& i_d } /// +/// @brief Gets the port self time refresh state +/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCA +/// @tparam TT traits type defaults to mcTraits<T> +/// @param[in] i_data the value of the register +/// @param[out] o_state the current STR state of the given port +/// +template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCA, typename TT = mcTraits<T> > +inline void get_self_time_refresh_state( const fapi2::buffer<uint64_t>& i_data, mss::states& o_state ) +{ + o_state = i_data.getBit<TT::CFG_STR_STATE>() ? mss::states::ON : mss::states::OFF; + FAPI_DBG("get_self_time_refresh_state to %d", o_state); +} + +/// /// @brief set the PWR CNTRL register /// @param[in] i_target the mca target /// @return fapi2::fapi2_rc_success if ok @@ -485,7 +537,7 @@ fapi2::ReturnCode calculate_perf2(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i /// @param[out] fapi2::buffer<uint64_t> o_xlate2 - xlt register 2's value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind>& i_dimm_kinds, +fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind<>>& i_dimm_kinds, fapi2::buffer<uint64_t>& o_xlate0, fapi2::buffer<uint64_t>& o_xlate1, fapi2::buffer<uint64_t>& o_xlate2 ); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C index 62d36ae0b..84ae50e3c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/perf_reg.C @@ -35,6 +35,7 @@ #include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> @@ -42,8 +43,7 @@ #include <lib/shared/mss_const.H> #include <lib/mc/mc.H> #include <generic/memory/lib/utils/scom.H> -#include <lib/dimm/kind.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/pos.H> using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C index 9ca4fae85..fc3f7b568 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,8 +38,9 @@ #include <lib/mc/port.H> #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/scom.H> -#include <lib/ecc/ecc.H> +#include <generic/memory/lib/ecc/ecc.H> #include <lib/workarounds/mca_workarounds.H> +#include <lib/ecc/nimbus_mbs_error_vector_trap.H> namespace mss { @@ -306,207 +307,18 @@ fapi_try_exit: } /// -/// @brief Convert a bitmap from the BAD_DQ_BITMAP attribute to a vector of bad DQ indexes -/// @param[in] i_bad_bits an 8-bit bitmap of bad bits -/// @param[in] i_nibble which nibble of the bitmap to convert -/// @return std::vector of DQ bits marked as bad in the bitmap -/// -std::vector<uint64_t> bad_bit_helper(const uint8_t i_bad_bits, const size_t i_nibble) -{ - std::vector<uint64_t> l_output; - fapi2::buffer<uint8_t> l_bit_buffer(i_bad_bits); - - const size_t l_start = (i_nibble == 0) ? 0 : BITS_PER_NIBBLE; - - for (size_t l_offset = 0; l_offset < BITS_PER_NIBBLE; ++l_offset) - { - if (l_bit_buffer.getBit(l_start + l_offset)) - { - l_output.push_back(l_start + l_offset); - } - } - - return l_output; -} - -/// -/// @brief Place a symbol mark in a Firmware Mark Store register -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq the bad DQ bit -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template<> -fapi2::ReturnCode place_symbol_mark(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - const uint64_t i_dq) -{ - const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); - const auto l_dimm_idx = mss::index(i_target); - const auto l_rank_idx = mss::index(i_rank); - - uint8_t l_galois = 0; - mss::mcbist::address l_addr; - - // For symbol marks, we set the appropriate Firmware Mark Store reg, with the symbol's - // Galois code, mark_type=SYMBOL, mark_region=MRANK, and the address of the DIMM+MRANK - // TODO RTC:165133 Remove static_cast once Galois API is updated to accept uint64_t input - FAPI_TRY( mss::ecc::dq_to_galois(static_cast<uint8_t>(i_dq), l_galois) ); - - l_addr.set_dimm(l_dimm_idx).set_master_rank(l_rank_idx); - - FAPI_INF("%s Setting firmware symbol mark on rank:%d dq:%d galois:0x%02x", - mss::c_str(i_target), i_rank, i_dq, l_galois); - FAPI_TRY( mss::ecc::set_fwms(l_mca, i_rank, l_galois, mss::ecc::fwms::mark_type::SYMBOL, - mss::ecc::fwms::mark_region::MRANK, l_addr) ); - - // Apply workaround for HW474117 if we place a symbol mark - FAPI_TRY( mss::workarounds::disable_bypass(l_mca) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Place a chip mark in a Hardware Mark Store register -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq one of the bad DQ bits in the bad nibble -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template<> -fapi2::ReturnCode place_chip_mark(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint64_t i_rank, - const uint64_t i_dq) -{ - const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); - - uint8_t l_galois = 0; - uint8_t l_symbol = 0; - - // For chip marks, we set the appropriate Hardware Mark Store reg, with the Galois code - // of the first (smallest) symbol in the bad nibble, and both confirmed and exit1 bits set - FAPI_TRY( mss::ecc::dq_to_symbol(static_cast<uint8_t>(i_dq), l_symbol) ); - - // Round down to the nearest "nibble" to get the correct symbol, then get the Galois code for it - l_symbol = (l_symbol / BITS_PER_NIBBLE) * BITS_PER_NIBBLE; - FAPI_TRY( mss::ecc::symbol_to_galois(l_symbol, l_galois) ); - - FAPI_INF("%s Setting hardware (chip) mark on rank:%d galois:0x%02x", mss::c_str(i_target), i_rank, l_galois); - FAPI_TRY( mss::ecc::set_hwms(l_mca, i_rank, l_galois) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Restore symbol and chip marks according to BAD_DQ_BITMAP attribute, helper function for unit testing -/// Specialization for TARGET_TYPE_DIMM -/// @param[in] i_target the DIMM target -/// @param[in] i_bad_bits the bad bits values from the VPD, for the specified DIMM -/// @param[out] o_repairs_applied 8-bit mask, where a bit set means a rank had repairs applied (bit0-7 = rank0-7) -/// @param[out] o_repairs_exceeded 2-bit mask, where a bit set means a DIMM had more bad bits than could be repaired (bit0-1 = DIMM0-1) -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template<> -fapi2::ReturnCode restore_repairs_helper<fapi2::TARGET_TYPE_DIMM, BAD_BITS_RANKS, BAD_DQ_BYTE_COUNT>( - const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const uint8_t i_bad_bits[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT], - fapi2::buffer<uint8_t>& o_repairs_applied, - fapi2::buffer<uint8_t>& o_repairs_exceeded) -{ - FAPI_INF("%s Restore repair marks from bad DQ data", mss::c_str(i_target)); - - std::vector<uint64_t> l_ranks; - const auto l_dimm_idx = mss::index(i_target); - - FAPI_TRY( mss::rank::ranks(i_target, l_ranks) ); - - // loop through ranks - for (const auto l_rank : l_ranks) - { - const auto l_rank_idx = mss::index(l_rank); - - repair_state_machine<fapi2::TARGET_TYPE_DIMM> l_machine; - - // loop through bytes - for (uint64_t l_byte = 0; l_byte < (MAX_DQ_NIBBLES / NIBBLES_PER_BYTE); ++l_byte) - { - for (size_t l_nibble = 0; l_nibble < NIBBLES_PER_BYTE; ++l_nibble) - { - const auto l_bad_dq_vector = bad_bit_helper(i_bad_bits[l_rank_idx][l_byte], l_nibble); - FAPI_DBG("Total bad bits on DIMM:%d rank:%d nibble%d: %d", - l_dimm_idx, l_rank, (l_byte * NIBBLES_PER_BYTE) + l_nibble, l_bad_dq_vector.size()); - - // apply repairs and update repair machine state - // if there are no bad bits (l_bad_dq_vector.size() == 0) no action is necessary - if (l_bad_dq_vector.size() == 1) - { - // l_bad_dq_vector is per byte, so multiply up to get the bad dq's index - const uint64_t l_dq = l_bad_dq_vector[0] + (l_byte * BITS_PER_BYTE); - FAPI_TRY( l_machine.one_bad_dq(i_target, l_rank, l_dq, o_repairs_applied, o_repairs_exceeded) ); - } - else if (l_bad_dq_vector.size() > 1) - { - // l_bad_dq_vector is per byte, so multiply up to get the bad dq's index - const uint64_t l_dq = l_bad_dq_vector[0] + (l_byte * BITS_PER_BYTE); - FAPI_TRY( l_machine.multiple_bad_dq(i_target, l_rank, l_dq, o_repairs_applied, o_repairs_exceeded) ); - } - - // if repairs have been exceeded, we're done - if (o_repairs_exceeded.getBit(l_dimm_idx)) - { - FAPI_INF("Repairs exceeded on DIMM %s", mss::c_str(i_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - } // end loop through nibbles - } // end loop through bytes - } // end loop through ranks - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Restore symbol and chip marks according to BAD_DQ_BITMAP attribute -/// Specialization for TARGET_TYPE_MCA -/// @param[in] i_target A target representing a port -/// @param[out] o_repairs_applied 8-bit mask, where a bit set means a rank had repairs applied (bit0-7 = rank0-7) -/// @param[out] o_repairs_exceeded 2-bit mask, where a bit set means a DIMM had more bad bits than could be repaired (bit0-1 = DIMM0-1) +/// @brief Set up memory controller specific settings for ECC registers (at the end of draminit_mc) +/// @param[in] i_target the target +/// @param[in,out] io_data contents of RECR register /// @return FAPI2_RC_SUCCESS if and only if ok +/// @note mc_type::NIMBUS specialization /// template<> -fapi2::ReturnCode restore_repairs( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - fapi2::buffer<uint8_t>& o_repairs_applied, - fapi2::buffer<uint8_t>& o_repairs_exceeded) +fapi2::ReturnCode ecc_reg_settings_draminit_mc<mss::mc_type::NIMBUS>( + const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + fapi2::buffer<uint64_t>& io_data ) { - uint8_t l_bad_bits[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT] = {}; - - o_repairs_applied = 0; - o_repairs_exceeded = 0; - - for (const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) - { - FAPI_TRY( mss::bad_dq_bitmap(l_dimm, &(l_bad_bits[0][0])) ); - - FAPI_TRY( (restore_repairs_helper<fapi2::TARGET_TYPE_DIMM, BAD_BITS_RANKS, BAD_DQ_BYTE_COUNT>( - l_dimm, l_bad_bits, o_repairs_applied, o_repairs_exceeded)) ); - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Set a new state in the repair state machine -/// @tparam T, the fapi2 target type of the DIMM -/// @param[in,out] io_machine the repair state machine -/// @param[in] i_state shared pointer to the new state to set -/// -template< fapi2::TargetType T > -void repair_state<T>::set_state(repair_state_machine<T>& io_machine, std::shared_ptr<repair_state<T>> i_state) -{ - io_machine.update_state(i_state); + return fapi2::FAPI2_RC_SUCCESS; } /// @@ -802,48 +614,4 @@ fapi2::ReturnCode chip_and_symbol_mark<fapi2::TARGET_TYPE_DIMM>::multiple_bad_dq return fapi2::FAPI2_RC_SUCCESS; } -/// -/// @brief Perform a repair for a single bad DQ bit in a nibble -/// @tparam T, the fapi2 target type of the DIMM -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq the DQ bit index -/// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied -/// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode repair_state_machine<T>::one_bad_dq(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) -{ - FAPI_TRY( iv_repair_state->one_bad_dq(*this, i_target, i_rank, i_dq, io_repairs_applied, io_repairs_exceeded) ); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Perform a repair for multiple bad DQ bits in a nibble -/// @tparam T, the fapi2 target type of the DIMM -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq one of the bad DQ bit indexes -/// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied -/// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode repair_state_machine<T>::multiple_bad_dq(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) -{ - FAPI_TRY( iv_repair_state->multiple_bad_dq(*this, i_target, i_rank, i_dq, io_repairs_applied, io_repairs_exceeded) ); -fapi_try_exit: - return fapi2::current_err; -} - } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H index 33131ad4f..f11f9aafa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/port.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,12 +40,12 @@ #include <lib/mss_attribute_accessors.H> #include <lib/shared/mss_const.H> +#include <lib/utils/mss_nimbus_conversions.H> #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/mc/gen_mss_port.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> -#include <lib/utils/mss_nimbus_conversions.H> #include <lib/dimm/rank.H> #include <lib/mcbist/address.H> @@ -75,9 +75,14 @@ template<> class portTraits<mss::mc_type::NIMBUS> { public: + + // PORT_TYPE + static constexpr enum fapi2::TargetType PORT_TYPE = fapi2::TARGET_TYPE_MCA; + static constexpr uint64_t FARB0Q_REG = MCA_MBA_FARB0Q; static constexpr uint64_t FARB1Q_REG = MCA_MBA_FARB1Q; static constexpr uint64_t FARB5Q_REG = MCA_MBA_FARB5Q; + static constexpr uint64_t FARB6Q_REG = MCA_MBA_FARB6Q; static constexpr uint64_t REFRESH_REG = MCA_MBAREF0Q; static constexpr uint64_t ECC_REG = MCA_RECR; static constexpr uint64_t CAL0Q_REG = MCA_MBA_CAL0Q; @@ -134,6 +139,10 @@ class portTraits<mss::mc_type::NIMBUS> PORT_FAIL_DISABLE = MCA_MBA_FARB0Q_CFG_PORT_FAIL_DISABLE, OE_ALWAYS_ON = MCA_MBA_FARB0Q_CFG_OE_ALWAYS_ON, RCD_RECOVERY_DISABLE = MCA_MBA_FARB0Q_CFG_DISABLE_RCD_RECOVERY, + BW_WINDOW_SIZE = MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE, + BW_WINDOW_SIZE_LEN = MCA_MBA_FARB0Q_CFG_BW_WINDOW_SIZE_LEN, + BW_SNAPSHOT = MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT, + BW_SNAPSHOT_LEN = MCA_MBA_FARB6Q_CFG_BW_SNAPSHOT_LEN, CAL0Q_CAL_INTERVAL_TMR0_ENABLE = MCA_MBA_CAL0Q_CFG_CAL_INTERVAL_TMR0_ENABLE, CAL0Q_TIME_BASE_TMR0 = MCA_MBA_CAL0Q_CFG_TIME_BASE_TMR0, @@ -247,9 +256,9 @@ class portTraits<mss::mc_type::NIMBUS> RECR_ENABLE_UE_NOISE_WINDOW = MCA_RECR_MBSECCQ_ENABLE_UE_NOISE_WINDOW, RECR_TCE_CORRECTION = MCA_RECR_MBSECCQ_ENABLE_TCE_CORRECTION, RECR_READ_POINTER_DLY = MCA_RECR_MBSECCQ_READ_POINTER_DELAY, + RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, RECR_MBSECCQ_DATA_INVERSION = MCA_RECR_MBSECCQ_DATA_INVERSION, RECR_MBSECCQ_DATA_INVERSION_LEN = MCA_RECR_MBSECCQ_DATA_INVERSION_LEN, - RECR_READ_POINTER_DLY_LEN = MCA_RECR_MBSECCQ_READ_POINTER_DELAY_LEN, DSM0Q_RDTAG_DLY = MCA_MBA_DSM0Q_CFG_RDTAG_DLY, DSM0Q_RDTAG_DLY_LEN = MCA_MBA_DSM0Q_CFG_RDTAG_DLY_LEN, DSM0Q_WRDONE_DLY = MCA_MBA_DSM0Q_CFG_WRDONE_DLY, @@ -681,7 +690,7 @@ fapi2::ReturnCode configure_cid_parity( const fapi2::Target<T>& i_target) l_state = mss::states::OFF_N; } - FAPI_DBG( "Change RDTAG_DLY to %d for %s", l_state, mss::c_str(i_target) ); + FAPI_DBG( "Change CID_PARITY to %d for %s", l_state, mss::c_str(i_target) ); FAPI_TRY( read_farb1q_register(i_target, l_data) ); set_cid_parity<T>(l_state, l_data); @@ -814,6 +823,23 @@ template<> fapi2::ReturnCode enable_periodic_cal( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target ); +/// +/// @brief Change the state of the force_str bit - mc_type::NIMBUS specialization +/// @tparam MC the memory controller type +/// @param[in] i_target the target +/// @param[in] i_state the state +/// @return FAPI2_RC_SUCCESS if and only if ok +/// @note This bit doesn't exist on Nimbus, so this is a no-op +/// +template<> +inline fapi2::ReturnCode change_force_str<DEFAULT_MC_TYPE>( + const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const states i_state ) +{ + return fapi2::FAPI2_RC_SUCCESS; +} + + // // We expect to come in to draminit with the following setup: // 1. ENABLE_RESET_N (FARB5Q(6)) 0 @@ -956,558 +982,21 @@ fapi_try_exit: return fapi2::current_err; } +/// @brief Get the attributes for the reorder queue setting +/// @param[in] const ref to the mc target +/// @param[out] uint8_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Contains the settings for write/read reorder +/// queue /// -/// @brief Configures the write reorder queue for MCBIST operations -/// @param[in] i_target the target to effect -/// @param[in] i_state to set the bit too -/// @return FAPI2_RC_SUCCSS iff ok -/// -inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state) -{ - typedef portTraits<mss::mc_type::NIMBUS> TT; - - fapi2::buffer<uint64_t> l_data; - - // Gets the reg - FAPI_TRY(mss::getScom(i_target, TT::WRQ_REG, l_data), "%s failed to getScom from MCA_MBA_WRQ0Q", mss::c_str(i_target)); - - // Sets the bit - l_data.writeBit<TT::WRQ_FIFO_MODE>(i_state == mss::states::ON); - - // Sets the regs - FAPI_TRY(mss::putScom(i_target, TT::WRQ_REG, l_data), "%s failed to putScom to MCA_MBA_WRQ0Q", mss::c_str(i_target)); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Configures the write reorder queue bit -/// @param[in] i_target the target to effect -/// @param[in] i_state to set the bit too -/// @return FAPI2_RC_SUCCSS iff ok -/// -inline fapi2::ReturnCode configure_wrq(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - const mss::states i_state) -{ - // Loops through all MCA targets, hitting all the registers - for( const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target) ) - { - FAPI_TRY(configure_wrq(l_mca, i_state)); - } - - // In case we don't have any MCA's - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configures the read reorder queue for MCBIST operations -/// @param[in] i_target the target to effect -/// @param[in] i_state to set the bit too -/// @return FAPI2_RC_SUCCSS iff ok -/// -inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const mss::states i_state) -{ - typedef portTraits<mss::mc_type::NIMBUS> TT; - - fapi2::buffer<uint64_t> l_data; - - // Gets the reg - FAPI_TRY(mss::getScom(i_target, TT::RRQ_REG, l_data), "%s failed to getScom from MCA_MBA_RRQ0Q", mss::c_str(i_target)); - - // Sets the bit - l_data.writeBit<TT::RRQ_FIFO_MODE>(i_state == mss::states::ON); - - // Sets the regs - FAPI_TRY(mss::putScom(i_target, TT::RRQ_REG, l_data), "%s failed to putScom to MCA_MBA_RRQ0Q", mss::c_str(i_target)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configures the read reorder queue bit -/// @param[in] i_target the target to effect -/// @param[in] i_state to set the bit too -/// @return FAPI2_RC_SUCCSS iff ok -/// -inline fapi2::ReturnCode configure_rrq(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - const mss::states i_state) -{ - // Loops through all MCA targets, hitting all the registers - for( const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target) ) - { - FAPI_TRY(configure_rrq(l_mca, i_state)); - } - - // In case we don't have any MCA's - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Resets the write/read reorder queue values - needs to be called after MCBIST execution -/// @tparam T, the fapi2 target type of the target -/// @param[in] i_target the target to effect -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T> -fapi2::ReturnCode reset_reorder_queue_settings(const fapi2::Target<T>& i_target) +template< > +inline fapi2::ReturnCode reorder_queue_setting<mss::mc_type::NIMBUS>(const + fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + uint8_t& o_value) { - uint8_t l_reorder_queue = 0; - FAPI_TRY(reorder_queue_setting(i_target, l_reorder_queue)); - - // Changes the reorder queue settings - { - // Two settings are FIFO and REORDER. FIFO is a 1 in the registers, while reorder is a 0 state - const mss::states l_state = ((l_reorder_queue == fapi2::ENUM_ATTR_MSS_REORDER_QUEUE_SETTING_FIFO) ? - mss::states::ON : mss::states::OFF); - FAPI_TRY(configure_rrq(i_target, l_state), "%s failed to reset read reorder queue settings", mss::c_str(i_target)); - FAPI_TRY(configure_wrq(i_target, l_state), "%s failed to reset read reorder queue settings", mss::c_str(i_target)); - } - - -fapi_try_exit: - return fapi2::current_err; + return mss::reorder_queue_setting(i_target, o_value); } -/// -/// @brief Convert a bitmap from the BAD_DQ_BITMAP attribute to a vector of bad DQ indexes -/// @param[in] i_bad_bits an 8-bit bitmap of bad bits -/// @param[in] i_nibble which nibble of the bitmap to convert -/// @return std::vector of DQ bits marked as bad in the bitmap -/// -std::vector<uint64_t> bad_bit_helper(const uint8_t i_bad_bits, const size_t i_nibble); - -/// -/// @brief Place a symbol mark in a Firmware Mark Store register -/// @tparam T, the fapi2 target type of the DIMM (derived) -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq the bad DQ bit -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode place_symbol_mark(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq); - -/// -/// @brief Place a chip mark in a Hardware Mark Store register -/// @tparam T, the fapi2 target type of the DIMM (derived) -/// @param[in] i_target the DIMM target -/// @param[in] i_rank the rank -/// @param[in] i_dq one of the bad DQ bits in the bad nibble -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode place_chip_mark(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq); - -// Forward declaration for use in repair_state classes -template< fapi2::TargetType T > -class repair_state_machine; - -/// -/// @class mss::repair_state -/// @brief A class for keeping track of bad bit repair states in a repair_state_machine -/// @tparam T, the fapi2 target type of the DIMM -/// @note this is a base class -/// -template< fapi2::TargetType T > -class repair_state -{ - public: - /// @brief default contructor - repair_state() = default; - /// @brief default destructor - virtual ~repair_state() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - virtual fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) = 0; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - virtual fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) = 0; - - protected: - /// - /// @brief Set a new state in the repair state machine - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_state pointer to the new state to set - /// - void set_state(repair_state_machine<T>& io_machine, std::shared_ptr<repair_state<T>> i_state); -}; - -/// -/// @class mss::no_fails -/// @brief repair_state class for no fails (no marks applied) -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class no_fails : public repair_state<T> -{ - public: - /// @brief default contructor - no_fails() = default; - /// @brief default destructor - ~no_fails() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; -}; - -/// -/// @class mss::symbol_mark_only -/// @brief repair_state class for when only a symbol mark has been used -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class symbol_mark_only : public repair_state<T> -{ - public: - /// @brief default contructor - symbol_mark_only() = default; - /// @brief default destructor - ~symbol_mark_only() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; -}; - -/// -/// @class mss::symbol_mark_plus_unrepaired_dq -/// @brief repair_state class for when only a symbol mark has been used, and one DQ bit remains unrepaired -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class symbol_mark_plus_unrepaired_dq : public repair_state<T> -{ - public: - /// @brief default contructor - symbol_mark_plus_unrepaired_dq() = default; - /// @brief default destructor - ~symbol_mark_plus_unrepaired_dq() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; -}; - -/// -/// @class mss::chip_mark_only -/// @brief repair_state class for when only a chip mark has been used -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class chip_mark_only : public repair_state<T> -{ - public: - /// @brief default contructor - chip_mark_only() = default; - /// @brief default destructor - ~chip_mark_only() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; -}; - -/// -/// @class mss::chip_mark_only -/// @brief repair_state class for when both a chip mark and a symbol mark have been used -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class chip_and_symbol_mark : public repair_state<T> -{ - public: - /// @brief default contructor - chip_and_symbol_mark() = default; - /// @brief default destructor - ~chip_and_symbol_mark() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in,out] io_machine the repair state machine - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(repair_state_machine<T>& io_machine, - const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded) override; -}; - -/// -/// @class mss::repair_state_machine -/// @brief state machine class used in restore_repairs_helper -/// @tparam T, the fapi2 target type of the DIMM -/// -template< fapi2::TargetType T > -class repair_state_machine -{ - public: - /// @brief constructor - repair_state_machine() - : iv_repair_state(std::make_shared<no_fails<T>>()) {} - - /// @brief default destructor - ~repair_state_machine() = default; - - /// - /// @brief Perform a repair for a single bad DQ bit in a nibble - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq the DQ bit index - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode one_bad_dq(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded); - - /// - /// @brief Perform a repair for multiple bad DQ bits in a nibble - /// @param[in] i_target the DIMM target - /// @param[in] i_rank the rank - /// @param[in] i_dq one of the bad DQ bit indexes - /// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied - /// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired - /// @return FAPI2_RC_SUCCESS if and only if ok - /// - fapi2::ReturnCode multiple_bad_dq(const fapi2::Target<T>& i_target, - const uint64_t i_rank, - const uint64_t i_dq, - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded); - - /// - /// @brief Update the state of the state machine - /// @param[in] i_state shared pointer to the new state - /// - void update_state(std::shared_ptr<repair_state<T>> i_state) - { - iv_repair_state = i_state; - } - - private: - std::shared_ptr<repair_state<T>> iv_repair_state; -}; - -// TODO RTC: 157753 tparam R can be pulled from an MCA trait once we have it -/// -/// @brief Restore symbol and chip marks according to BAD_DQ_BITMAP attribute, helper function for unit testing -/// @tparam T, the fapi2 target type of the DIMM (derived) -/// @tparam R the maximum rank per DIMM -/// @tparam B the number of bytes per rank in the bad_dq_bitmap attribute -/// @param[in] i_target A target representing a DIMM -/// @param[in] i_bad_bits the bad bits values from the VPD, for the specified DIMM -/// @param[in,out] io_repairs_applied 8-bit mask, where a bit set means that rank had repairs applied -/// @param[in,out] io_repairs_exceeded 2-bit mask, where a bit set means that DIMM had more bad bits than could be repaired -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T, uint64_t R, uint64_t B > -fapi2::ReturnCode restore_repairs_helper( const fapi2::Target<T>& i_target, - const uint8_t i_bad_bits[R][B], - fapi2::buffer<uint8_t>& io_repairs_applied, - fapi2::buffer<uint8_t>& io_repairs_exceeded); - -/// -/// @brief Restore symbol and chip marks according to BAD_DQ_BITMAP attribute -/// @tparam T, the fapi2 target type of the port (derived) -/// @param[in] i_target A target representing a port -/// @param[out] o_repairs_applied bit mask, where a bit set means a rank had repairs applied (bit0 = rank0, etc) -/// @param[out] o_repairs_exceeded bit mask, where a bit set means a DIMM had more bad bits than could be repaired (bit0 = DIMM0 etc) -/// @return FAPI2_RC_SUCCESS if and only if ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode restore_repairs( const fapi2::Target<T>& i_target, - fapi2::buffer<uint8_t>& o_repairs_applied, - fapi2::buffer<uint8_t>& o_repairs_exceeded); - }// mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C index 31ac6eade..cc13cd96c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.C @@ -35,6 +35,7 @@ #include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> @@ -43,8 +44,8 @@ #include <lib/mc/mc.H> #include <lib/mc/xlate.H> #include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/dimm/kind.H> +#include <lib/utils/nimbus_find.H> +#include <lib/dimm/nimbus_kind.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_DIMM; @@ -59,7 +60,7 @@ static const std::vector<xlate_setup> xlate_map = { // 1R 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -72,7 +73,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -85,7 +86,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -98,7 +99,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -111,7 +112,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -124,7 +125,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -137,7 +138,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -150,7 +151,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -163,7 +164,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -176,7 +177,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -189,7 +190,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -202,7 +203,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -215,7 +216,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -228,7 +229,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -241,7 +242,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -254,7 +255,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -267,7 +268,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -280,7 +281,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -299,7 +300,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -312,7 +313,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -325,7 +326,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -338,7 +339,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -351,7 +352,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -364,7 +365,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 2H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -377,7 +378,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -390,7 +391,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -403,7 +404,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -416,7 +417,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -429,7 +430,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -442,7 +443,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 4H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -455,7 +456,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -468,7 +469,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -481,7 +482,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -494,7 +495,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -507,7 +508,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -520,7 +521,7 @@ static const std::vector<xlate_setup> xlate_map = // 1R 8H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_1R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -533,7 +534,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -546,7 +547,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -559,7 +560,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -572,7 +573,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -585,7 +586,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -598,7 +599,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -611,7 +612,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -624,7 +625,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -637,7 +638,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -650,7 +651,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -663,7 +664,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -676,7 +677,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -689,7 +690,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 4Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -702,7 +703,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 4Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -715,7 +716,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 8Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -728,7 +729,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 8Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -741,7 +742,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 16Gbx8 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, @@ -754,7 +755,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8H 3DS 16Gbx4 DDR4 RDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_16R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -773,7 +774,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 8Gbx4 32GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -786,7 +787,7 @@ static const std::vector<xlate_setup> xlate_map = // 4R 8Gbx4 64GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -803,7 +804,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 8Gbx4 64GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_4G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -816,7 +817,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 8Gbx4 64GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_8G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -829,7 +830,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 2H 3DS 16Gbx4 128GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_4R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -842,7 +843,7 @@ static const std::vector<xlate_setup> xlate_map = // 2R 4H 3DS 16Gbx4 256GB DDR4 LRDIMM { - dimm::kind(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, + dimm::kind<>(fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_2R, fapi2::ENUM_ATTR_EFF_NUM_RANKS_PER_DIMM_8R, fapi2::ENUM_ATTR_EFF_DRAM_DENSITY_16G, fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, @@ -867,7 +868,7 @@ static bool all_slots_1R_helper(const fapi2::Target<TARGET_TYPE_DIMM>& i_target) const auto& l_mca = mss::find_target<TARGET_TYPE_MCA>(i_target); const auto& l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(l_mca); - const std::vector<dimm::kind> l_dimm_kinds = dimm::kind::vector(l_dimms); + const std::vector<dimm::kind<>> l_dimm_kinds = dimm::kind<>::vector(l_dimms); bool l_all_slots_1R = false; // If we only have 1 DIMM, we don't have two slots with 1R DIMM. If we need to check, iterate @@ -993,7 +994,7 @@ fapi_try_exit: /// @note Called for 2R4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1038,7 +1039,7 @@ fapi_try_exit: /// @note Called for 2R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1075,7 +1076,7 @@ fapi_try_exit: /// @note Called for 2R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1112,7 +1113,7 @@ fapi_try_exit: /// @note Called for 2R 2H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1142,7 +1143,7 @@ fapi_try_exit: /// @note Called for 2R 2H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1175,7 +1176,7 @@ fapi_try_exit: /// @note Called for 2R 2H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1208,7 +1209,7 @@ fapi_try_exit: /// @note Called for 2R 4H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1238,7 +1239,7 @@ fapi_try_exit: /// @note Called for 2R 4H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1271,7 +1272,7 @@ fapi_try_exit: /// @note Called for 2R 4H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1304,7 +1305,7 @@ fapi_try_exit: /// @note Called for 2R 8H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1341,7 +1342,7 @@ fapi_try_exit: /// @note Called for 2R 8H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1374,7 +1375,7 @@ fapi_try_exit: /// @note Called for 2R 8H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1408,7 +1409,7 @@ fapi_try_exit: /// @note Called for 1R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1510,7 +1511,7 @@ fapi_try_exit: /// @note Called for 1R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1547,7 +1548,7 @@ fapi_try_exit: /// @note Called for 1R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1584,7 +1585,7 @@ fapi_try_exit: /// @note Called for 1R 2H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1615,7 +1616,7 @@ fapi_try_exit: /// @note Called for 1R 2H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1648,7 +1649,7 @@ fapi_try_exit: /// @note Called for 1R 2H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1681,7 +1682,7 @@ fapi_try_exit: /// @note Called for 1R 4H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1718,7 +1719,7 @@ fapi_try_exit: /// @note Called for 1R 4H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1751,7 +1752,7 @@ fapi_try_exit: /// @note Called for 1R 4H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1784,7 +1785,7 @@ fapi_try_exit: /// @note Called for 1R 8H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1819,7 +1820,7 @@ fapi_try_exit: /// @note Called for 1R 8H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1852,7 +1853,7 @@ fapi_try_exit: /// @note Called for 1R 8H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1885,7 +1886,7 @@ fapi_try_exit: /// @note Called for 4R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1920,7 +1921,7 @@ fapi_try_exit: /// @note Called for 4R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1953,7 +1954,7 @@ fapi_try_exit: /// @note Called for 4R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1983,7 +1984,7 @@ fapi_try_exit: /// @param[out] fapi2::buffer<uint64_t> io_xlate2 - xlt register 2's value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind>& io_dimm_kinds, +fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind<>>& io_dimm_kinds, fapi2::buffer<uint64_t>& io_xlate0, fapi2::buffer<uint64_t>& io_xlate1, fapi2::buffer<uint64_t>& io_xlate2 ) @@ -1999,7 +2000,8 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind>& io_dimm_kinds // However, we need to set that DIMM's D bit in the location of the largest DIMM's D-bit map (I know that's // hard to grok - set the D bit in the smallest DIMM but in the location mapped for the largest.) So we // keep track of the largest DIMM so when we set it up, we make sure to set the D-bit in the other. - std::sort(io_dimm_kinds.begin(), io_dimm_kinds.end(), [](const dimm::kind & a, const dimm::kind & b) -> bool + std::sort(io_dimm_kinds.begin(), io_dimm_kinds.end(), [](const dimm::kind<>& a, + const dimm::kind<>& b) -> bool { return a.iv_size > b.iv_size; }); @@ -2106,7 +2108,7 @@ fapi2::ReturnCode setup_xlate_map(const fapi2::Target<TARGET_TYPE_MCA>& i_target const auto l_dimms = mss::find_targets<TARGET_TYPE_DIMM>(i_target); // We need to keep around specifications of both DIMM as we set the D bit based on the sizes of the DIMM - std::vector<dimm::kind> l_dimm_kinds = dimm::kind::vector(l_dimms); + std::vector<dimm::kind<>> l_dimm_kinds = dimm::kind<>::vector(l_dimms); FAPI_INF("Setting up xlate registers for MCA%d (%d)", mss::pos(i_target), mss::index(i_target)); @@ -2131,7 +2133,7 @@ fapi_try_exit: /// @note Called for 1R 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2156,7 +2158,7 @@ fapi_try_exit: /// @note Called for 1R 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2181,7 +2183,7 @@ fapi_try_exit: /// @note Called for 1R 2H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2206,7 +2208,7 @@ fapi_try_exit: /// @note Called for 1R 2H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2231,7 +2233,7 @@ fapi_try_exit: /// @note Called for 1R 4H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2256,7 +2258,7 @@ fapi_try_exit: /// @note Called for 1R 4H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2281,7 +2283,7 @@ fapi_try_exit: /// @note Called for 1R 8H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2306,7 +2308,7 @@ fapi_try_exit: /// @note Called for 1R 8H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2331,7 +2333,7 @@ fapi_try_exit: /// @note Called for 2R 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2356,7 +2358,7 @@ fapi_try_exit: /// @note Called for 2R16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2381,7 +2383,7 @@ fapi_try_exit: /// @note Called for 2R 2H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2406,7 +2408,7 @@ fapi_try_exit: /// @note Called for 2R 2H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2431,7 +2433,7 @@ fapi_try_exit: /// @note Called for 2R 4H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2456,7 +2458,7 @@ fapi_try_exit: /// @note Called for 2R 4H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2481,7 +2483,7 @@ fapi_try_exit: /// @note Called for 2R 8H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2506,7 +2508,7 @@ fapi_try_exit: /// @note Called for 2R 8H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2531,7 +2533,7 @@ fapi_try_exit: /// @note Called for 4R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2556,7 +2558,7 @@ fapi_try_exit: /// @note Called for 4R 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2581,7 +2583,7 @@ fapi_try_exit: /// @note Called for 1R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2609,7 +2611,7 @@ fapi_try_exit: /// @note Called for 1R 2H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2640,7 +2642,7 @@ fapi_try_exit: /// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2671,7 +2673,7 @@ fapi_try_exit: /// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2702,7 +2704,7 @@ fapi_try_exit: /// @note Called for 2R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2733,7 +2735,7 @@ fapi_try_exit: /// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2764,7 +2766,7 @@ fapi_try_exit: /// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2795,7 +2797,7 @@ fapi_try_exit: /// @note Called for 2R 8H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -2826,7 +2828,7 @@ fapi_try_exit: /// @note Called for 4R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H index 9a168c0b5..5b7db7076 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mc/xlate.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,7 +44,7 @@ #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> namespace mss { @@ -495,8 +495,8 @@ struct xlate_setup /// @param[in] i_kind a DIMM kind structure representing the ... err... kind of DIMM /// @param[in] i_func a function pointer to a function which does the configuring /// - xlate_setup( const dimm::kind i_kind, - fapi2::ReturnCode (*i_func)( const dimm::kind&, const uint64_t, const bool, + xlate_setup( const dimm::kind<> i_kind, + fapi2::ReturnCode (*i_func)( const dimm::kind<>&, const uint64_t, const bool, fapi2::buffer<uint64_t>&, fapi2::buffer<uint64_t>&, fapi2::buffer<uint64_t>& ) ): iv_kind(i_kind), iv_func(i_func) @@ -504,10 +504,10 @@ struct xlate_setup } // Keep around the kind of DIMM this nugget represents - dimm::kind iv_kind; + dimm::kind<> iv_kind; // The function to call to setup the translation registers to setup for our DIMM kind. - fapi2::ReturnCode (*iv_func)( const dimm::kind&, const uint64_t, const bool, + fapi2::ReturnCode (*iv_func)( const dimm::kind<>&, const uint64_t, const bool, fapi2::buffer<uint64_t>&, fapi2::buffer<uint64_t>&, fapi2::buffer<uint64_t>& ); }; @@ -522,7 +522,7 @@ struct xlate_setup /// @note Called for 2R4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -540,7 +540,7 @@ fapi2::ReturnCode xlate_dimm_2R2T4Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -558,7 +558,7 @@ fapi2::ReturnCode xlate_dimm_2R2T8Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -576,7 +576,7 @@ fapi2::ReturnCode xlate_dimm_2R2T16Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 2H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -594,7 +594,7 @@ fapi2::ReturnCode xlate_dimm_2R4T4Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 2H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -612,7 +612,7 @@ fapi2::ReturnCode xlate_dimm_2R4T8Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 2H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -630,7 +630,7 @@ fapi2::ReturnCode xlate_dimm_2R4T16Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 4H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -648,7 +648,7 @@ fapi2::ReturnCode xlate_dimm_2R8T4Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 4H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -666,7 +666,7 @@ fapi2::ReturnCode xlate_dimm_2R8T8Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 4H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -684,7 +684,7 @@ fapi2::ReturnCode xlate_dimm_2R8T16Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 8H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -702,7 +702,7 @@ fapi2::ReturnCode xlate_dimm_2R16T4Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 8H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -719,7 +719,7 @@ fapi2::ReturnCode xlate_dimm_2R16T8Gbx4( const dimm::kind& i_kind, /// @note Called for 2R 8H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -737,7 +737,7 @@ fapi2::ReturnCode xlate_dimm_2R16T16Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -754,7 +754,7 @@ fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -772,7 +772,7 @@ fapi2::ReturnCode xlate_dimm_1R1T8Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -790,7 +790,7 @@ fapi2::ReturnCode xlate_dimm_1R1T16Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 2H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -808,7 +808,7 @@ fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 2H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -826,7 +826,7 @@ fapi2::ReturnCode xlate_dimm_1R2T8Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 2H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -844,7 +844,7 @@ fapi2::ReturnCode xlate_dimm_1R2T16Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 4H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -862,7 +862,7 @@ fapi2::ReturnCode xlate_dimm_1R4T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 4H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -880,7 +880,7 @@ fapi2::ReturnCode xlate_dimm_1R4T8Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 4H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -898,7 +898,7 @@ fapi2::ReturnCode xlate_dimm_1R4T16Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 8H 3DS 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -915,7 +915,7 @@ fapi2::ReturnCode xlate_dimm_1R8T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 8H 3DS 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -933,7 +933,7 @@ fapi2::ReturnCode xlate_dimm_1R8T8Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 8H 3DS 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -951,7 +951,7 @@ fapi2::ReturnCode xlate_dimm_1R8T16Gbx4( const dimm::kind& i_kind, /// @note Called for 4R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -968,7 +968,7 @@ fapi2::ReturnCode xlate_dimm_4R4T4Gbx4( const dimm::kind& i_kind, /// @note Called for 4R 8Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -985,7 +985,7 @@ fapi2::ReturnCode xlate_dimm_4R4T8Gbx4( const dimm::kind& i_kind, /// @note Called for 4R 16Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1000,7 +1000,7 @@ fapi2::ReturnCode xlate_dimm_4R4T16Gbx4( const dimm::kind& i_kind, /// @param[out] fapi2::buffer<uint64_t> o_xlate2 - xlt register 2's value /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind>& i_dimm_kinds, +fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind<>>& i_dimm_kinds, fapi2::buffer<uint64_t>& o_xlate0, fapi2::buffer<uint64_t>& io_xlate1, fapi2::buffer<uint64_t>& io_xlate2 ); @@ -1016,7 +1016,7 @@ fapi2::ReturnCode setup_xlate_map_helper( std::vector<dimm::kind>& i_dimm_kinds, /// @note Called for 1R4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1034,7 +1034,7 @@ fapi2::ReturnCode xlate_dimm_1R1T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 2 total ranks 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1052,7 +1052,7 @@ fapi2::ReturnCode xlate_dimm_1R2T4Gbx4( const dimm::kind& i_kind, /// @note Called for 1R 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1070,7 +1070,7 @@ fapi2::ReturnCode xlate_dimm_1R1T8Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1088,7 +1088,7 @@ fapi2::ReturnCode xlate_dimm_1R1T16Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 2H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1106,7 +1106,7 @@ fapi2::ReturnCode xlate_dimm_1R2T8Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 2H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1124,7 +1124,7 @@ fapi2::ReturnCode xlate_dimm_1R2T16Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 4H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1142,7 +1142,7 @@ fapi2::ReturnCode xlate_dimm_1R4T8Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 4H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1160,7 +1160,7 @@ fapi2::ReturnCode xlate_dimm_1R4T16Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 8H 3DS 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1177,7 +1177,7 @@ fapi2::ReturnCode xlate_dimm_1R8T8Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 8H 3DS 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1195,7 +1195,7 @@ fapi2::ReturnCode xlate_dimm_1R8T16Gbx8( const dimm::kind& i_kind, /// @note Called for 2R8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1213,7 +1213,7 @@ fapi2::ReturnCode xlate_dimm_2R2T8Gbx8( const dimm::kind& i_kind, /// @note Called for 2R16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1231,7 +1231,7 @@ fapi2::ReturnCode xlate_dimm_2R2T16Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 2H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1249,7 +1249,7 @@ fapi2::ReturnCode xlate_dimm_2R4T8Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 2H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1267,7 +1267,7 @@ fapi2::ReturnCode xlate_dimm_2R4T16Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1285,7 +1285,7 @@ fapi2::ReturnCode xlate_dimm_2R8T8Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1303,7 +1303,7 @@ fapi2::ReturnCode xlate_dimm_2R8T16Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 8H 8Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1321,7 +1321,7 @@ fapi2::ReturnCode xlate_dimm_2R16T8Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 8H 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1339,7 +1339,7 @@ fapi2::ReturnCode xlate_dimm_2R16T16Gbx8( const dimm::kind& i_kind, /// @note Called for 4R 4Gbx4 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T8Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T8Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1357,7 +1357,7 @@ fapi2::ReturnCode xlate_dimm_4R4T8Gbx8( const dimm::kind& i_kind, /// @note Called for 4R 16Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1375,7 +1375,7 @@ fapi2::ReturnCode xlate_dimm_4R4T16Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1393,7 +1393,7 @@ fapi2::ReturnCode xlate_dimm_1R1T4Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 2H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1411,7 +1411,7 @@ fapi2::ReturnCode xlate_dimm_1R2T4Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1429,7 +1429,7 @@ fapi2::ReturnCode xlate_dimm_1R4T4Gbx8( const dimm::kind& i_kind, /// @note Called for 1R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1447,7 +1447,7 @@ fapi2::ReturnCode xlate_dimm_1R8T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1465,7 +1465,7 @@ fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1483,7 +1483,7 @@ fapi2::ReturnCode xlate_dimm_2R2T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1501,7 +1501,7 @@ fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 2H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1519,7 +1519,7 @@ fapi2::ReturnCode xlate_dimm_2R4T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1537,7 +1537,7 @@ fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 4H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1555,7 +1555,7 @@ fapi2::ReturnCode xlate_dimm_2R8T4Gbx8( const dimm::kind& i_kind, /// @note Called for 2R 8H 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, @@ -1573,7 +1573,7 @@ fapi2::ReturnCode xlate_dimm_2R16T4Gbx8( const dimm::kind& i_kind, /// @note Called for 4R 4Gbx8 DDR4 RDIMM /// @return FAPI2_RC_SUCCESS iff okay /// -fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind& i_kind, +fapi2::ReturnCode xlate_dimm_4R4T4Gbx8( const dimm::kind<>& i_kind, const uint64_t i_offset, const bool i_largest, fapi2::buffer<uint64_t>& io_xlate0, diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H index 3a7a4ee2c..fcfd9a3e4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/address.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,489 +38,13 @@ #include <fapi2.H> #include <utility> -#include <lib/ecc/ecc_traits.H> - -namespace mss -{ - -namespace ecc -{ - -namespace fwms -{ - -/// -/// @class address -/// @brief Converts Firmware Mark Store ADDRESS field into mcbist::address -/// @tparam T fapi2 Target Type defaults to fapi2::TARGET_TYPE_MCA -/// @tparam TT traits type defaults to eccTraits<T> -/// @note template argument defaults are in forward declaration in lib/mcbist/address.H -/// @note 12 = dimm -/// @note 13:14 = mrank -/// @note 15:17 = srank -/// @note 18:19 = bank group -/// @note 20:22 = bank -/// -// See declaration below -template< fapi2::TargetType T, typename TT = eccTraits<T> > -class address; - -} // close namespace fwms -} // close namespace ecc - -namespace mcbist -{ - -/// -/// @class address -/// @brief Represents a physical address in memory -/// @note -/// 0:1 port select -/// 2 dimm select -/// 3:4 mrank(0 to 1) -/// 5:7 srank(0 to 2) -/// 8:25 row(0 to 17) -/// 26:32 col(3 to 9) -/// 33:35 bank(0 to 2) -/// 36:37 bank_group(0 to 1) -/// -class address -{ - private: - // How far over we shift to align the address in either the register or a buffer - enum { MAGIC_PAD = 26 }; - - public: - - // first is the start bit of the field, second is the length - typedef std::pair<uint64_t, uint64_t> field; - - constexpr static field PORT = {0, 2}; - constexpr static field DIMM = {2, 1}; - constexpr static field MRANK = {3, 2}; - constexpr static field SRANK = {5, 3}; - constexpr static field ROW = {8, 18}; - constexpr static field COL = {26, 7}; - constexpr static field BANK = {33, 3}; - constexpr static field BANK_GROUP = {36, 2}; - constexpr static field LAST_VALID = BANK_GROUP; - - address() = default; - - static constexpr uint64_t LARGEST_ADDRESS = ~0 >> MAGIC_PAD; - - // Used when accessing an integral value containing a port and DIMM combination - static constexpr uint64_t DIMM_BIT = 63; - static constexpr uint64_t PORT_START = 61; - static constexpr uint64_t PORT_LEN = 2; - - /// - /// @brief Construct an address from a uint64_t (scom'ed value) - /// @param[in] i_value representing an address; say from a trap register - /// - /// @note This assumes input has the same bit layout as this address - /// structure, and this is presently not the case for the trap registers (3/16). - /// These are presently unused, however. There is an open defect against the - /// design team to correct this. - /// @warn Assumes right-aligned value; bit 63 is shifted to represent the Bank Group - address( const uint64_t i_value ): - iv_address(i_value << MAGIC_PAD) - { - } - - /// - /// @brief Construct an address from an ecc::fwms::address - /// @tparam T fapi2 Target Type - /// @param[in] i_address representing an address field from a firmware mark store register - /// - template< fapi2::TargetType T > - address( const ecc::fwms::address<T>& i_address ) - { - fapi2::buffer<uint64_t> l_value = uint64_t(i_address); - uint64_t l_temp = 0; - l_value.extractToRight<ecc::fwms::address<T>::DIMM.first, ecc::fwms::address<T>::DIMM.second>(l_temp); - this->set_field<DIMM>(l_temp); - l_value.extractToRight<ecc::fwms::address<T>::MRANK.first, ecc::fwms::address<T>::MRANK.second>(l_temp); - this->set_field<MRANK>(l_temp); - l_value.extractToRight<ecc::fwms::address<T>::SRANK.first, ecc::fwms::address<T>::SRANK.second>(l_temp); - this->set_field<SRANK>(l_temp); - l_value.extractToRight<ecc::fwms::address<T>::BANK_GROUP.first, ecc::fwms::address<T>::BANK_GROUP.second>(l_temp); - this->set_field<BANK_GROUP>(l_temp); - l_value.extractToRight<ecc::fwms::address<T>::BANK.first, ecc::fwms::address<T>::BANK.second>(l_temp); - this->set_field<BANK>(l_temp); - } - - /// - /// @brief Conversion operator to uint64_t - /// @warn Right-aligns the address - /// - inline operator uint64_t() const - { - return iv_address >> MAGIC_PAD; - } - - /// - /// @brief Set a field for an address - /// @tparam F the field to set - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - template< const field& F > - inline address& set_field( const uint64_t i_value ) - { - iv_address.insertFromRight<F.first, F.second>(i_value); - return *this; - } - - /// - /// @brief Get a field from an address - /// @tparam F the field to get - /// @return right-aligned uint64_t representing the value - /// - template< const field& F > - inline uint64_t get_field() const - { - uint64_t l_value = 0; - iv_address.extractToRight<F.first, F.second>(l_value); - return l_value; - } - - /// - /// @brief Get a range of addresses. - /// @tparam[in] F the left-most valid field. So, if the address was for master rank, - /// the left-most valid field would be MRANK - /// @param[out] o_end representing an address to end at - /// @note this pointer is the start address - /// - template< const field& F > - inline void get_range( address& o_end ) const - { - constexpr uint64_t START = F.first + F.second; - constexpr uint64_t LEN = (LAST_VALID.first + LAST_VALID.second) - START; - - // All we need to do is fill in the bits to the right of the last valid field - o_end.iv_address = iv_address; - o_end.iv_address.setBit<START, LEN>(); - } - - - /// - /// @brief Get an end address for sim mode - /// @param[out] o_end representing an address to end at - /// @note this pointer is the start address - /// - inline void get_sim_end_address( address& o_end ) const - { - // This magic number represents a range of addresses which cover all - // cache lines the training algorithms touch. By effecting 0 - this end - // address you'll effect everything which has bad ECC in the sim. - constexpr uint64_t l_magic_sim_number = 0b1000000; - - get_range<COL>(o_end); - o_end.set_column(l_magic_sim_number); - return; - } - - /// - /// @brief Get a range of addresses given a master rank - /// @param[in] i_start representing an address to start from - /// @param[out] o_end representing an address to end at - /// - inline static void get_mrank_range( const address& i_start, address& o_end ) - { - i_start.get_range<MRANK>(o_end); - } - - /// - /// @brief Get a range of addresses given a master rank - /// @param[in] i_port representing the port for the starting address - /// @param[in] i_dimm representing the dimm for the starting address - /// @param[in] i_mrank representing the master rank for the starting address - /// @param[out] o_start representing an address to start from - /// @param[out] o_end representing an address to end at - /// - inline static void get_mrank_range( const uint64_t i_port, const uint64_t i_dimm, const uint64_t i_mrank, - address& o_start, address& o_end ) - { - o_start.set_port(i_port).set_dimm(i_dimm).set_master_rank(i_mrank); - get_mrank_range(o_start, o_end); - } - - /// - /// @brief Get a range of addresses given a slave rank - /// @param[in] i_start representing an address to start from - /// @param[out] o_end representing an address to end at - /// - inline static void get_srank_range( const address& i_start, address& o_end ) - { - i_start.get_range<SRANK>(o_end); - } - - /// - /// @brief Get a range of addresses given a slave rank - /// @param[in] i_port representing the port for the starting address - /// @param[in] i_dimm representing the dimm for the starting address - /// @param[in] i_mrank representing the master rank for the starting address - /// @param[in] i_srank representing the slave rank for the starting address - /// @param[out] o_start representing an address to start from - /// @param[out] o_end representing an address to end at - /// - inline static void get_srank_range( const uint64_t i_port, const uint64_t i_dimm, - const uint64_t i_mrank, const uint64_t i_srank, - address& o_start, address& o_end ) - { - o_start.set_port(i_port).set_dimm(i_dimm).set_master_rank(i_mrank).set_slave_rank(i_srank); - get_srank_range(o_start, o_end); - } - - /// - /// @brief Set the port value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_port( const uint64_t i_value ) - { - return set_field<PORT>(i_value); - } - - /// - /// @brief Get the port value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_port() const - { - return get_field<PORT>(); - } - - /// - /// @brief Set the DIMM value for an address - /// @param[in] i_value the value to set - /// @note 0 is the DIMM[0] != 0 is DIMM[1] - /// @return address& for method chaining - /// - inline address& set_dimm( const uint64_t i_value ) - { - return set_field<DIMM>(i_value); - } - - /// - /// @brief Get the DIMM value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_dimm() const - { - return get_field<DIMM>(); - } - - /// - /// @brief Set the port and DIMM value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// @note Useful for indexing all ports/DIMM on a controller - /// - inline address& set_port_dimm( const fapi2::buffer<uint64_t> i_value ) - { - uint64_t l_read_port = 0; - - i_value.extractToRight<PORT_START, PORT_LEN>(l_read_port); - return set_dimm(i_value.getBit<DIMM_BIT>()).set_port(l_read_port); - } - - /// - /// @brief Get the port and DIMM value for an address - /// @return right-aligned uint64_t representing the value - /// @note Useful for indexing all ports/DIMM on a controller - /// - inline uint64_t get_port_dimm() const - { - fapi2::buffer<uint64_t> l_value; - - l_value.insertFromRight<PORT_START, PORT_LEN>(get_port()); - l_value.writeBit<DIMM_BIT>(get_dimm()); - - return l_value; - } - - /// - /// @brief Set the master rank value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_master_rank( const uint64_t i_value ) - { - return set_field<MRANK>(i_value); - } - - /// - /// @brief Get the master rank value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_master_rank() const - { - return get_field<MRANK>(); - } - - - /// - /// @brief Set the slave rank value for an address - /// @param[in] i_value the value to set - /// - inline void set_slave_rank( const uint64_t i_value ) - { - set_field<SRANK>(i_value); - } - - /// - /// @brief Get the slave rank value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_slave_rank() const - { - return get_field<SRANK>(); - } - - - /// - /// @brief Set the row value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_row( const uint64_t i_value ) - { - return set_field<ROW>(i_value); - } - - /// - /// @brief Get the row value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_row() const - { - return get_field<ROW>(); - } - - - /// - /// @brief Set the column value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_column( const uint64_t i_value ) - { - return set_field<COL>(i_value); - } - - /// - /// @brief Get the column value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_column() const - { - return get_field<COL>(); - } - - - /// - /// @brief Set the bank value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_bank( const uint64_t i_value ) - { - return set_field<BANK>(i_value); - } - - /// - /// @brief Get the bank value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_bank() const - { - return get_field<BANK>(); - } - - /// - /// @brief Set the bank group value for an address - /// @param[in] i_value the value to set - /// @return address& for method chaining - /// - inline address& set_bank_group( const uint64_t i_value ) - { - return set_field<BANK_GROUP>(i_value); - } - - /// - /// @brief Get the bank group value for an address - /// @return right-aligned uint64_t representing the value - /// - inline uint64_t get_bank_group() const - { - return get_field<BANK_GROUP>(); - } - - private: - // We use a fapi2 buffer as it has static compile-time support - fapi2::buffer<uint64_t> iv_address; -}; - -} // close namespace mcbist - -// Documented above in its declaration. -template< fapi2::TargetType T, typename TT > -class ecc::fwms::address -{ - public: - // first is the start bit of the field, second is the length - typedef std::pair<uint64_t, uint64_t> field; - - constexpr static field DIMM = {TT::FIRMWARE_MS_ADDRESS, 1}; - constexpr static field MRANK = {TT::FIRMWARE_MS_ADDRESS + 1, 2}; - constexpr static field SRANK = {TT::FIRMWARE_MS_ADDRESS + 3, 3}; - constexpr static field BANK_GROUP = {TT::FIRMWARE_MS_ADDRESS + 6, 2}; - constexpr static field BANK = {TT::FIRMWARE_MS_ADDRESS + 8, 3}; - constexpr static field LAST_VALID = BANK; - - address() = default; - - /// - /// @brief Construct an address from a uint64_t (scom'ed value) - /// @param[in] i_value representing raw value from FWMS register - /// - address( const uint64_t& i_value ): - iv_value(i_value) - { - } - - /// - /// @brief Construct an address from an mcbist::address - /// @param[in] i_mcbist_address mcbist formatted address - /// @note Construction of mcbist::address from ecc::fwms::address - /// @note located in mcbist::address class - /// - address( const mcbist::address& i_mcbist_address ) - { - iv_value.insertFromRight<DIMM.first, DIMM.second>(i_mcbist_address.get_field<mcbist::address::DIMM>()); - iv_value.insertFromRight<MRANK.first, MRANK.second>(i_mcbist_address.get_field<mcbist::address::MRANK>()); - iv_value.insertFromRight<SRANK.first, SRANK.second>(i_mcbist_address.get_field<mcbist::address::SRANK>()); - iv_value.insertFromRight<BANK_GROUP.first, BANK_GROUP.second> - (i_mcbist_address.get_field<mcbist::address::BANK_GROUP>()); - iv_value.insertFromRight<BANK.first, BANK.second>(i_mcbist_address.get_field<mcbist::address::BANK>()); - } - - /// - /// @brief Conversion operator to uint64_t - /// - inline operator uint64_t() const - { - uint64_t l_temp = 0; - iv_value.extract<TT::FIRMWARE_MS_ADDRESS, TT::FIRMWARE_MS_ADDRESS_LEN, TT::FIRMWARE_MS_ADDRESS>(l_temp); - return l_temp; - } - - private: - fapi2::buffer<uint64_t> iv_value; -}; - -} // close namespace mss +#include <lib/shared/mss_const.H> +#include <lib/ecc/ecc_traits_nimbus.H> +#include <lib/mcbist/mcbist_traits.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_ecc_trap_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_fwms_address.H> + +// This file is still necessary to put traits and generic code together #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C index f5ef0e24c..f002b31e9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.C @@ -35,8 +35,8 @@ #include <lib/shared/nimbus_defaults.H> #include <fapi2.H> +#include <lib/mss_attribute_accessors.H> #include <lib/mcbist/mcbist.H> -#include <lib/utils/dump_regs.H> #include <lib/workarounds/mcbist_workarounds.H> #include <generic/memory/lib/utils/pos.H> @@ -47,7 +47,22 @@ using fapi2::TARGET_TYPE_MCS; namespace mss { -const std::pair<uint64_t, uint64_t> mcbistTraits<fapi2::TARGET_TYPE_MCBIST>::address_pairs[] = +/// +/// @brief Gets the attribute for freq +/// @param[in] const ref to the target +/// @param[out] uint64_t& reference to store the value +/// @note Generated by gen_accessors.pl generate_mc_port_params +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Frequency of this memory channel in MT/s (Mega Transfers per second) +/// +template<> +fapi2::ReturnCode freq<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST>(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target, uint64_t& o_value) +{ + return mss::freq(i_target, o_value); +} + +const std::pair<uint64_t, uint64_t> mcbistTraits<>::address_pairs[] = { { START_ADDRESS_0, END_ADDRESS_0 }, { START_ADDRESS_1, END_ADDRESS_1 }, @@ -55,7 +70,7 @@ const std::pair<uint64_t, uint64_t> mcbistTraits<fapi2::TARGET_TYPE_MCBIST>::add { START_ADDRESS_3, END_ADDRESS_3 }, }; -const std::vector< mss::mcbist::op_type > mcbistTraits<fapi2::TARGET_TYPE_MCBIST>::FIFO_MODE_REQUIRED_OP_TYPES = +const std::vector< mss::mcbist::op_type > mcbistTraits<>::FIFO_MODE_REQUIRED_OP_TYPES = { mss::mcbist::op_type::WRITE , mss::mcbist::op_type::READ , @@ -67,463 +82,63 @@ const std::vector< mss::mcbist::op_type > mcbistTraits<fapi2::TARGET_TYPE_MCBIST mss::mcbist::op_type::READ_READ_WRITE , }; -namespace mcbist -{ - -/// -/// @brief Load MCBIST maint pattern given a pattern -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_pattern an mcbist::patterns -/// @param[in] i_invert whether to invert the pattern or not -/// @note this overload disappears when we have real patterns. -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< > -fapi2::ReturnCode load_maint_pattern( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const pattern& i_pattern, - const bool i_invert ) +// These valus are pulled out of the MCBIST specification +// The index is the fixed width - the value is the LFSR_MASK value to be used +const std::vector< uint64_t > mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST>::LFSR_MASK_VALUES = { - // Init the fapi2 return code - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - // Array access control - fapi2::buffer<uint64_t> l_aacr; - // Array access data - fapi2::buffer<uint64_t> l_aadr; - - // first we must setup the access control register - // Setup the array address - // enable the auto increment bit - // set ecc mode bit on - l_aacr - .writeBit<MCA_WREITE_AACR_BUFFER>(mss::states::OFF) - .insertFromRight<MCA_WREITE_AACR_ADDRESS, MCA_WREITE_AACR_ADDRESS_LEN>(mss::mcbist::rmw_address::DW0) - .writeBit<MCA_WREITE_AACR_AUTOINC>(mss::states::ON) - .writeBit<MCA_WREITE_AACR_ECCGEN>(mss::states::ON); - - // This loop will be run twice to write the pattern twice. Once per 64B write. - // When MCBIST maint mode is in 64B mode it will only use the first 64B when in 128B mode - // MCBIST maint will use all 128B (it will perform two consecutive writes) - const auto l_ports = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - // Init the port map - - for (const auto& p : l_ports) - { - l_aacr.insertFromRight<MCA_WREITE_AACR_ADDRESS, MCA_WREITE_AACR_ADDRESS_LEN>(mss::mcbist::rmw_address::DW0); - - for (auto l_num_reads = 0; l_num_reads < 2; ++l_num_reads) - { - FAPI_INF("Setting the array access control register."); - FAPI_TRY( mss::putScom(p, MCA_WREITE_AACR, l_aacr) ); - - for (const auto& l_cache_line : i_pattern) - { - fapi2::buffer<uint64_t> l_value_first = i_invert ? ~l_cache_line.first : l_cache_line.first; - fapi2::buffer<uint64_t> l_value_second = i_invert ? ~l_cache_line.second : l_cache_line.second; - FAPI_INF("Loading cache line pattern 0x%016lx 0x%016lx", l_value_first, l_value_second); - FAPI_TRY( mss::putScom(p, MCA_AADR, l_value_first) ); - - // In order for the data to actually be written into the RMW buffer, we must issue a putscom to the MCA_AAER register - // This register is used for the ECC, we will just write all zero to this register. The ECC will be auto generated - // when the aacr MCA_WREITE_AACR_ECCGEN bit is set - FAPI_TRY( mss::putScom(p, MCA_AAER, 0) ); - - // No need to increment the address because the logic does it automatically when MCA_WREITE_AACR_AUTOINC is set - FAPI_TRY( mss::putScom(p, MCA_AADR, l_value_second) ); - - // In order for the data to actually be written into the RMW buffer, we must issue a putscom to the MCA_AAER register - // This register is used for the ECC, we will just write all zero to this register. The ECC will be auto generated - // when the aacr MCA_WREITE_AACR_ECCGEN bit is set - FAPI_TRY( mss::putScom(p, MCA_AAER, 0) ); - } - - l_aacr.insertFromRight<MCA_WREITE_AACR_ADDRESS, MCA_WREITE_AACR_ADDRESS_LEN>(mss::mcbist::rmw_address::DW8); - } - } - - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST data compare mask registers -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< > -fapi2::ReturnCode load_data_compare_mask( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const mcbist::program<TARGET_TYPE_MCBIST>& i_program ) -{ - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; - - // Init the fapi2 return code - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - // Load the MCBCM Data compare masks - - const auto l_ports = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); - FAPI_INF("Loading the MCBIST data compare mask registers!"); - - for (const auto& p : l_ports) - { - FAPI_TRY( mss::putScom(p, TT::COMPARE_MASK, i_program.iv_compare_mask) ); - } - -fapi_try_exit: - return fapi2::current_err; - -} - -/// -/// @brief Load MCBIST 24b random data seeds given a pattern index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_random24_data_seed mcbist::random24_data_seed -/// @param[in] i_random24_map mcbist::random24_seed_map -/// @param[in] i_invert whether to invert the pattern or not -/// @note this overload disappears when we have real patterns. -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< > -fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const random24_data_seed& i_random24_data_seed, - const random24_seed_map& i_random24_map, - const bool i_invert ) -{ - // Init the fapi2 return code - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; - - const uint64_t l_random_addr0 = MCBIST_MCBRDS0Q; - const uint64_t l_random_addr1 = MCBIST_MCBRDS1Q; - uint64_t l_index = 0; - uint64_t l_map_index = 0; - uint64_t l_map_offset = 0; - - fapi2::buffer<uint64_t> l_mcbrsd0q; - fapi2::buffer<uint64_t> l_mcbrsd1q; - - - // We are going to loop through the random seeds and load them into the random seed registers - // Because the 24b random data seeds share the same registers as the 24b random data byte LFSR maps - // we will load those as well - - for (const auto& l_seed : i_random24_data_seed) - { - FAPI_INF("Loading 24b random seed index %ld ", l_index); - fapi2::buffer<uint64_t> l_value = i_invert ? ~l_seed : l_seed; - - // Print an informational message to indicate if a random seed is 0 - // TK Do we want an error here? 0 may be used on purpose to hold a byte at all 0 on purpose - if ( l_value == 0 ) - { - FAPI_INF("Warning: Random 24b data seed is set to 0 for seed index %d", l_index); - } - - // If we are processing the first 24b random data seed we will add it to the fapi buffer - // we won't load it yet because the second 24b seed will be loaded into the same register - if ( l_index == 0 ) - { - l_mcbrsd0q.insertFromRight<MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0, MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN>(l_value); - } - // The second 24b random data seed is loaded into the same register as the first seed - // therefore we will add the second seed tothe fapi buffer and then issue the putscom - else if (l_index == 1 ) - { - l_mcbrsd0q.insertFromRight<MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1, MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN>(l_value); - FAPI_INF("Loading 24b random seeds 0 and 1 0x%016lx ", l_mcbrsd0q); - FAPI_TRY( mss::putScom(i_target, l_random_addr0, l_mcbrsd0q) ); - } - // The third 24b random data seed occupies the same register as the random data byte maps. Therefore we first - // add the third random 24b data seed to the register and then loop through all of the byte mappings a total of - // 9. ach of the byte mappings associates a byte of the random data to a byte in the 24b random data LFSRs - // Each byte map is offset by 4 bits in the register. - else - { - l_mcbrsd1q.insertFromRight<MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2, MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN>(l_value); - - for (const auto& l_map : i_random24_map) - { - l_map_offset = MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING + (l_map_index * RANDOM24_SEED_MAP_FIELD_LEN); - l_mcbrsd1q.insertFromRight(l_map, l_map_offset, RANDOM24_SEED_MAP_FIELD_LEN); - FAPI_INF("Loading 24b random seed map index %ld ", l_map_index); - FAPI_ASSERT( l_map_index < mss::mcbist::MAX_NUM_RANDOM24_MAPS, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(l_map_index), - "Attempting to load a 24b random data seed map which does not exist %d", l_map_index ); - ++l_map_index; - } - - FAPI_TRY( mss::putScom(i_target, l_random_addr1, l_mcbrsd1q) ); - } - - FAPI_ASSERT( l_index < MAX_NUM_RANDOM24_SEEDS, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(l_index), - "Attempting to load a 24b random data seed which does not exist %d", l_index ); - ++l_index; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load a set of MCBIST subtests in to the MCBIST registers -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] the target to effect -/// @param[in] the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// @note assumes the MCBIST engine has been configured. -/// -template<> -fapi2::ReturnCode load_mcbmr( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const mcbist::program<TARGET_TYPE_MCBIST>& i_program ) -{ - - // Leave if there are no subtests. - if (0 == i_program.iv_subtests.size()) - { - FAPI_INF("no subtests, nothing to do"); - return fapi2::current_err; - } - - // List of the 8 MCBIST registers - each holds 4 subtests. - static const std::vector< uint64_t > l_memory_registers = - { - MCBIST_MCBMR0Q, MCBIST_MCBMR1Q, MCBIST_MCBMR2Q, MCBIST_MCBMR3Q, - MCBIST_MCBMR4Q, MCBIST_MCBMR5Q, MCBIST_MCBMR6Q, MCBIST_MCBMR7Q, - }; - - std::vector< uint64_t > l_memory_register_buffers = - { - 0, 0, 0, 0, 0, 0, 0, 0, - }; - - static const size_t SUBTEST_PER_REG = 4; - static const size_t SUBTEST_PER_PROGRAM = 32; - - static const auto BITS_IN_SUBTEST = sizeof(mcbist::subtest_t<TARGET_TYPE_MCBIST>().iv_mcbmr) * 8; - static const auto LEFT_SHIFT = (sizeof(uint64_t) * 8) - BITS_IN_SUBTEST; - - ssize_t l_bin = -1; - size_t l_register_shift = 0; - - // We'll shift this in to position to indicate which subtest is the last - static const uint64_t l_done_bit( 0x8000000000000000 >> MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE ); - - // TK: For now limit MCBIST programs to 32 subtests. - const auto l_program_size = i_program.iv_subtests.size(); - FAPI_ASSERT( l_program_size <= SUBTEST_PER_PROGRAM, - fapi2::MSS_MCBIST_PROGRAM_TOO_BIG().set_PROGRAM_LENGTH(l_program_size), - "mcbist program of length %d exceeds arbitrary maximum of %d", l_program_size, SUBTEST_PER_PROGRAM ); - - // Distribute the program over the 8 MCBIST subtest registers - // We need the index, so increment thru i_program.iv_subtests.size() - for (size_t l_index = 0; l_index < l_program_size; ++l_index) - { - l_bin = (l_index % SUBTEST_PER_REG) == 0 ? l_bin + 1 : l_bin; - l_register_shift = (l_index % SUBTEST_PER_REG) * BITS_IN_SUBTEST; - - l_memory_register_buffers[l_bin] |= - (uint64_t(i_program.iv_subtests[l_index].iv_mcbmr) << LEFT_SHIFT) >> l_register_shift; - - FAPI_DBG("putting subtest %d (0x%x) in MCBMR%dQ shifted %d 0x%016llx", - l_index, i_program.iv_subtests[l_index].iv_mcbmr, l_bin, - l_register_shift, l_memory_register_buffers[l_bin]); - } - - // l_bin and l_register_shift are the values for the last subtest we'll tell the MCBIST about. - // We need to set that subtest's done-bit so the MCBIST knows it's the end of the line - l_memory_register_buffers[l_bin] |= l_done_bit >> l_register_shift; - FAPI_DBG("setting MCBMR%dQ subtest %llu as the last subtest 0x%016llx", - l_bin, l_register_shift, l_memory_register_buffers[l_bin]); - - // ... and slam the values in to the registers. - // Could just decrement l_bin, but that scoms the subtests in backwards and is confusing - for (auto l_index = 0; l_index <= l_bin; ++l_index) - { - FAPI_TRY( mss::putScom(i_target, l_memory_registers[l_index], l_memory_register_buffers[l_index]) ); - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Poll the mcbist engine and check for errors -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program, the mcbist program which is executing -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode poll( const fapi2::Target<T>& i_target, const program<T>& i_program ) -{ - fapi2::buffer<uint64_t> l_status; - - static const uint64_t l_done = fapi2::buffer<uint64_t>().setBit<TT::MCBIST_DONE>(); - static const uint64_t l_fail = fapi2::buffer<uint64_t>().setBit<TT::MCBIST_FAIL>(); - static const uint64_t l_in_progress = fapi2::buffer<uint64_t>().setBit<TT::MCBIST_IN_PROGRESS>(); - - // A small vector of addresses to poll during the polling loop - const std::vector<mss::poll_probe<fapi2::TARGET_TYPE_MCBIST>> l_probes = - { - {i_target, "mcbist current address", MCBIST_MCBMCATQ}, - }; - - mss::poll(i_target, TT::STATQ_REG, i_program.iv_poll, - [&l_status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_DBG("mcbist statq 0x%llx, remaining: %d", stat_reg, poll_remaining); - l_status = stat_reg; - return l_status.getBit<TT::MCBIST_IN_PROGRESS>() != 1; - }, - l_probes); - - // Check to see if we're still in progress - meaning we timed out. - FAPI_ASSERT((l_status & l_in_progress) != l_in_progress, - fapi2::MSS_MCBIST_TIMEOUT().set_MCBIST_TARGET(i_target), - "MCBIST timed out %s", mss::c_str(i_target)); - - // The control register has a bit for done-and-happy and a bit for done-and-unhappy - if ( ((l_status & l_done) == l_done) || ((l_status & l_fail) == l_fail) ) - { - FAPI_INF("MCBIST completed, processing errors"); - - // We're done. It doesn't mean that there were no errors. - FAPI_TRY( i_program.process_errors(i_target) ); - - // If we're here there were no errors, but lets report if the fail bit was set anyway. - FAPI_ASSERT( (l_status & l_fail) != l_fail, - fapi2::MSS_MCBIST_UNKNOWN_FAILURE() - .set_MCBIST_TARGET(i_target) - .set_STATUS_REGISTER(l_status), - "%s MCBIST reported a fail, but process_errors didn't find it 0x%016llx", - mss::c_str(i_target), l_status ); - - // And if we're here all is good with the world. - return fapi2::current_err; - } - - FAPI_ASSERT(false, - fapi2::MSS_MCBIST_DATA_FAIL() - .set_MCBIST_TARGET(i_target) - .set_STATUS_REGISTER(l_status), - "%s MCBIST executed but we got corrupted data in the control register 0x%016llx", - mss::c_str(i_target), l_status ); - -fapi_try_exit: - return fapi2::current_err; -} + 0x000000031, + 0x00000001F, + 0x001000000, + 0x100000000, + 0x004000003, + 0x000080000, + 0x040000018, + 0x008000000, + 0x010006000, + 0x004000000, + 0x001000000, + 0x003200000, + 0x001880000, + 0x000200000, + 0x000610000, + 0x000100000, + 0x000040000, + 0x000010000, + 0x000023000, + 0x000002000, + 0x000000400, + 0x000002000, + 0x000005008, + 0x000002000, + 0x000001088, + 0x000000B00, + 0x0000004A0, + 0x000000100, + 0x000000040, + 0x000000010, + 0x000000038, + 0x000000008, + 0x000000010, + 0x000000004, + 0x000000004, + 0x000000002, + 0x000000001, +}; -/// -/// @brief Execute the mcbist program -/// @param[in] i_target the target to effect -/// @param[in] i_program, the mcbist program to execute -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template<> -fapi2::ReturnCode execute( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const program<TARGET_TYPE_MCBIST>& i_program ) +namespace mcbist { - typedef mcbistTraits<TARGET_TYPE_MCBIST> TT; - - fapi2::buffer<uint64_t> l_status; - bool l_poll_result = false; - poll_parameters l_poll_parameters; - - // Before we go off into the bushes, lets see if there are any instructions in the - // program. If not, we can save everyone the hassle - FAPI_ASSERT(0 != i_program.iv_subtests.size(), - fapi2::MSS_MEMDIAGS_NO_MCBIST_SUBTESTS().set_MCBIST_TARGET(i_target), - "Attempt to run an MCBIST program with no subtests on %s", mss::c_str(i_target)); - - // Implement any mcbist work-arounds. - // I'm going to do the unthinkable here - and cast away the const of the mcbist program input. - // The work arounds need to change this, and so it needs to not be const. However, I don't want - // to risk general const-correctness by changing the input parameter to non-const. So, I use - // const_cast<> (ducks out of the way of the flying adjectives.) These are work-arounds ... - FAPI_TRY( workarounds::mcbist::end_of_rank(i_target, const_cast<program<TARGET_TYPE_MCBIST>&>(i_program)) ); - - FAPI_TRY( clear_errors(i_target) ); - - // Configures the write/read FIFO bit - FAPI_TRY( load_fifo_mode( i_target, i_program) ); - - // Slam the address generator config - FAPI_TRY( load_addr_gen(i_target, i_program) ); - - // Slam the parameters in to the mcbist parameter register - FAPI_TRY( load_mcbparm(i_target, i_program) ); - - // Slam the configured address maps down - FAPI_TRY( load_mcbamr( i_target, i_program) ); - - // Slam the config register down - FAPI_TRY( load_config( i_target, i_program) ); - - // Slam the control register down - FAPI_TRY( load_control( i_target, i_program) ); - - // Load the patterns and any associated bits for random, etc - FAPI_TRY( load_data_config( i_target, i_program) ); - - // Load the thresholds - FAPI_TRY( load_thresholds( i_target, i_program) ); - - // Slam the subtests in to the mcbist registers - // Always do this last so the action file triggers see the other bits set - FAPI_TRY( load_mcbmr(i_target, i_program) ); - - // Start the engine, and then poll for completion - FAPI_TRY(start_stop(i_target, mss::START)); - - // Verify that the in-progress bit has been set, so we know we started - // Don't use the program's poll as it could be a very long time. Use the default poll. - l_poll_result = mss::poll(i_target, TT::STATQ_REG, l_poll_parameters, - [&l_status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_DBG("looking for mcbist start, mcbist statq 0x%llx, remaining: %d", stat_reg, poll_remaining); - l_status = stat_reg; - // We're done polling when either we see we're in progress or we see we're done. - return (l_status.getBit<TT::MCBIST_IN_PROGRESS>() == true) || (l_status.getBit<TT::MCBIST_DONE>() == true); - }); - - // So we've either run/are running or we timed out waiting for the start. - FAPI_ASSERT( l_poll_result == true, - fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_START().set_MCBIST_TARGET(i_target), - "The MCBIST engine failed to start its program" ); - - // If the user asked for async mode, we can leave. Otherwise, poll and check for errors - if (!i_program.iv_async) - { - return mcbist::poll(i_target, i_program); - } - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Get a list of ports involved in the program -/// Specialization for program<fapi2::TARGET_TYPE_MCBIST> +/// Specialization for program<> /// @param[in] i_target the target for this program /// @return vector of port targets /// template<> -template<> std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> - program<fapi2::TARGET_TYPE_MCBIST>::get_port_list<fapi2::TARGET_TYPE_MCA>( const - fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) const + program<>::get_port_list( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) const { - typedef mss::mcbistTraits<TARGET_TYPE_MCBIST> TT; + using TT = mss::mcbistTraits<>; std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> l_list; @@ -542,81 +157,6 @@ std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> return l_list; } -/// -/// @brief Read entries from MCBIST Read Modify Write (RMW) array -/// Specialization for fapi2::TARGET_TYPE_MCA -/// @param[in] i_target the target to effect -/// @param[in] i_start_addr the array address to read first -/// @param[in] i_num_entries the number of array entries to read -/// @param[in] i_roll_over_for_compare_mode set to true if only using first -/// NUM_COMPARE_INFO_ENTRIES of array, so array address rolls over at correct value -/// @param[out] o_data vector of output data -/// @param[out] o_ecc_data vector of ecc data -/// @return FAPI2_RC_SUCCSS iff ok -/// @note The number of entries in the array depends on i_roll_over_for_compare_mode parameter: -/// (NUM_COMPARE_LOG_ENTRIES for false, NUM_COMPARE_INFO_ENTRIES for true) but user may read more than -/// that since reads work in a circular buffer fashion -/// -template<> -fapi2::ReturnCode read_rmw_array(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, - const uint64_t i_start_addr, - const uint64_t i_num_entries, - const bool i_roll_over_for_compare_mode, - std::vector< fapi2::buffer<uint64_t> >& o_data, - std::vector< fapi2::buffer<uint64_t> >& o_ecc_data) -{ - typedef mcbistTraits<fapi2::TARGET_TYPE_MCA> TT; - - fapi2::buffer<uint64_t> l_control_value; - fapi2::buffer<uint64_t> l_data; - uint64_t l_array_addr = i_start_addr; - - // Clear out any stale values from output vectors - o_data.clear(); - o_ecc_data.clear(); - - // Set the control register for the RMW array - l_control_value.writeBit<TT::RMW_WRT_BUFFER_SEL>(TT::SELECT_RMW_BUFFER) - // set start address - .insertFromRight<TT::RMW_WRT_ADDRESS, TT::RMW_WRT_ADDRESS_LEN>(l_array_addr) - // enable the auto increment bit - .setBit<TT::RMW_WRT_AUTOINC>() - // set ecc mode bit off - .clearBit<TT::RMW_WRT_ECCGEN>(); - - FAPI_INF("Setting the RMW array access control register."); - FAPI_TRY( mss::putScom(i_target, TT::RMW_WRT_BUF_CTL_REG, l_control_value) ); - - for (uint8_t l_index = 0; l_index < i_num_entries; ++l_index) - { - // Read info out of RMW array and put into output vector - // Note that since we enabled AUTOINC above, reading ECC_REG will increment - // the array pointer so the next DATA_REG read will read the next array entry - FAPI_TRY( mss::getScom(i_target, TT::RMW_WRT_BUF_DATA_REG, l_data) ); - - FAPI_INF("RMW data index %d is: %016lx", l_array_addr, l_data); - o_data.push_back(l_data); - - // Need to read ecc register to increment array index - FAPI_TRY( mss::getScom(i_target, TT::RMW_WRT_BUF_ECC_REG, l_data) ); - o_ecc_data.push_back(l_data); - ++l_array_addr; - - // Need to manually roll over address if we go beyond NUM_COMPARE_INFO_ENTRIES - // Since actual array is bigger than what is used for compare mode - if (i_roll_over_for_compare_mode && - (l_array_addr >= TT::NUM_COMPARE_INFO_ENTRIES)) - { - FAPI_INF("Rolling over the RMW array access control register address from %d to %d.", (i_start_addr + l_index), 0); - l_control_value.clearBit<TT::RMW_WRT_ADDRESS, TT::RMW_WRT_ADDRESS_LEN>(); - FAPI_TRY( mss::putScom(i_target, TT::RMW_WRT_BUF_CTL_REG, l_control_value) ); - l_array_addr = 0; - } - } - -fapi_try_exit: - return fapi2::current_err; -} /// /// @brief Read entries from MCBIST Read Buffer (RB) array @@ -635,7 +175,7 @@ fapi2::ReturnCode read_rb_array(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_t std::vector< fapi2::buffer<uint64_t> >& o_data, std::vector< fapi2::buffer<uint64_t> >& o_ecc_data) { - typedef mcbistTraits<fapi2::TARGET_TYPE_MCS> TT; + using TT = mcbistTraits<DEFAULT_MC_TYPE, fapi2::TARGET_TYPE_MCS>; fapi2::buffer<uint64_t> l_control_value; fapi2::buffer<uint64_t> l_data; @@ -687,7 +227,7 @@ fapi_try_exit: /// @param[in] i_targets the vector of targets to analyze - specialization for MCA target type /// @return l_capable - yes iff these vector of targets are broadcast capable /// -template< > +template<> const mss::states is_broadcast_capable(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>>& i_targets) { // If we don't have MCA's exit out @@ -810,7 +350,7 @@ const mss::states is_broadcast_capable(const fapi2::Target<fapi2::TARGET_TYPE_MC // 2) Check that all of the DIMM kinds are equal - if they are, then we can do broadcast mode const auto l_dimms = mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target); - const auto l_dimm_kinds = mss::dimm::kind::vector(l_dimms); + const auto l_dimm_kinds = mss::dimm::kind<>::vector(l_dimms); const auto l_dimm_kind_check = is_broadcast_capable(l_dimm_kinds); // 3) if both 1/2 are true, then broadcastable, otherwise false @@ -832,7 +372,7 @@ fapi_try_exit: /// @param[in] i_target the target to effect /// @return l_capable - yes iff these vector of targets are broadcast capable /// -const mss::states is_broadcast_capable(const std::vector<mss::dimm::kind>& i_kinds) +const mss::states is_broadcast_capable(const std::vector<mss::dimm::kind<>>& i_kinds) { // If we don't have any DIMM kinds exit out if(i_kinds.size() == 0) @@ -848,7 +388,7 @@ const mss::states is_broadcast_capable(const std::vector<mss::dimm::kind>& i_kin // Now, find if we have any kinds that differ from our first kind // Note: starts on the next DIMM kind due to the fact that something always equals itself const auto l_kind_it = std::find_if(i_kinds.begin() + 1, - i_kinds.end(), [&l_expected_kind]( const mss::dimm::kind & i_rhs) -> bool + i_kinds.end(), [&l_expected_kind]( const mss::dimm::kind<>& i_rhs) -> bool { // If they're different, we found a DIMM that is differs return (l_expected_kind != i_rhs); @@ -911,7 +451,7 @@ fapi_try_exit: /// template< > fapi2::ReturnCode enable_broadcast_mode(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mcbist::program<fapi2::TARGET_TYPE_MCBIST>& io_program) + mcbist::program<>& io_program) { // constexpr's for beautification constexpr bool ENABLE = true; @@ -934,6 +474,52 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Configures broadcast mode, if it is needed +/// @param[in] i_target the target to effect +/// @param[in,out] io_program the mcbist::program +/// @return FAPI2_RC_SUCCSS iff ok +/// +template<> +fapi2::ReturnCode configure_broadcast_mode(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + mcbist::program<>& io_program) +{ + // If we're not capable to do broadcast mode on this target, exit out + const auto l_broadcast_capable = is_broadcast_capable(i_target); + + if(l_broadcast_capable == mss::states::NO) + { + FAPI_INF("%s is not broadcast capable, skipping enablement of broadcast mode", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Enable broadcast mode + FAPI_INF("%s is broadcast capable, enabling broadcast mode", mss::c_str(i_target)); + return enable_broadcast_mode(i_target, io_program); +} + +/// +/// @brief Clear the errors helper. Chip can specialise this +/// function to put any necessary workaround in it. +/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK +/// +template< > +fapi2::ReturnCode clear_error_helper( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const program<>& i_program ) +{ + // Implement any mcbist work-arounds. + // I'm going to do the unthinkable here - and cast away the const of the mcbist program input. + // The work arounds need to change this, and so it needs to not be const. However, I don't want + // to risk general const-correctness by changing the input parameter to non-const. So, I use + // const_cast<> (ducks out of the way of the flying adjectives.) These are work-arounds ... + FAPI_TRY( workarounds::mcbist::end_of_rank(i_target, const_cast<program<>&>(i_program)) ); + + FAPI_TRY( clear_errors(i_target) ); + +fapi_try_exit: + return fapi2::current_err; +} + } // namespace MCBIST // Note: outside of the mcbist namespace diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H index bba494154..f708a8869 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,3156 +42,27 @@ #include <p9_mc_scom_addresses_fld.H> #include <lib/shared/mss_const.H> -#include <generic/memory/lib/utils/find.H> -#include <generic/memory/lib/utils/poll.H> -#include <generic/memory/lib/utils/memory_size.H> +#include <lib/ecc/ecc_traits_nimbus.H> +#include <lib/mc/port.H> #include <lib/utils/mss_nimbus_conversions.H> #include <lib/utils/bit_count.H> -#include <lib/utils/num.H> -#include <lib/mcbist/patterns.H> -#include <lib/mcbist/settings.H> -#include <lib/mc/port.H> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> +#include <lib/mcbist/mcbist_traits.H> +#include <lib/workarounds/mcbist_workarounds.H> +#include <generic/memory/lib/utils/num.H> +#include <generic/memory/lib/utils/poll.H> +#include <generic/memory/lib/utils/memory_size.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_patterns.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_settings.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist.H> +#include <generic/memory/lib/utils/dump_regs.H> namespace mss { - -// I have a dream that the MCBIST engine code can be shared among controllers. So, I drive the -// engine from a set of traits. This might be folly. Allow me to dream. BRS - -/// -/// @class mcbistTraits -/// @brief a collection of traits associated with the MCBIST engine or hardware -/// -template< fapi2::TargetType T > -class mcbistTraits; - -/// -/// @class mcbistTraits -/// @brief a collection of traits associated with the Centaur MCBIST engine or hardware -/// -template<> -class mcbistTraits<fapi2::TARGET_TYPE_MEMBUF_CHIP> -{ -}; - -/// -/// @class mcbistTraits -/// @brief a collection of traits associated with the Nimbus MCBIST engine or hardware -/// -template<> -class mcbistTraits<fapi2::TARGET_TYPE_MCBIST> -{ - public: - /// MCBIST "memory registers" - config for subtests. - static constexpr uint64_t MCBMR0_REG = MCBIST_MCBMR0Q; - static constexpr uint64_t CFGQ_REG = MCBIST_MCBCFGQ; - static constexpr uint64_t CNTLQ_REG = MCBIST_MCB_CNTLQ; - static constexpr uint64_t STATQ_REG = MCBIST_MCB_CNTLSTATQ; - static constexpr uint64_t MCBSTATQ_REG = MCBIST_MCBSTATQ; - static constexpr uint64_t MCBPARMQ_REG = MCBIST_MCBPARMQ; - static constexpr uint64_t MCBAGRAQ_REG = MCBIST_MCBAGRAQ; - static constexpr uint64_t SRERR0_REG = MCBIST_MBSEC0Q; - static constexpr uint64_t SRERR1_REG = MCBIST_MBSEC1Q; - static constexpr uint64_t THRESHOLD_REG = MCBIST_MBSTRQ; - static constexpr uint64_t FIRQ_REG = MCBIST_MCBISTFIRQ; - static constexpr uint64_t LAST_ADDR_REG = MCBIST_MCBMCATQ; - - static constexpr uint64_t MCBAMR0A0Q_REG = MCBIST_MCBAMR0A0Q; - static constexpr uint64_t MCBAMR1A0Q_REG = MCBIST_MCBAMR1A0Q; - static constexpr uint64_t MCBAMR2A0Q_REG = MCBIST_MCBAMR2A0Q; - static constexpr uint64_t MCBAMR3A0Q_REG = MCBIST_MCBAMR3A0Q; - - // MCBIST FIR registers - static constexpr uint64_t MCBFIRMASK_REG = MCBIST_MCBISTFIRMASK; - static constexpr uint64_t MCBFIRQ_REG = MCBIST_MCBISTFIRQ; - - // All of the pattern registers are calculated off of this base - static constexpr uint64_t PATTERN0_REG = MCBIST_MCBFD0Q; - - static constexpr uint64_t DATA_ROTATE_CNFG_REG = MCBIST_MCBDRCRQ; - static constexpr uint64_t DATA_ROTATE_SEED_REG = MCBIST_MCBDRSRQ; - - static constexpr uint64_t START_ADDRESS_0 = MCBIST_MCBSA0Q; - static constexpr uint64_t START_ADDRESS_1 = MCBIST_MCBSA1Q; - static constexpr uint64_t START_ADDRESS_2 = MCBIST_MCBSA2Q; - static constexpr uint64_t START_ADDRESS_3 = MCBIST_MCBSA3Q; - - static constexpr uint64_t END_ADDRESS_0 = MCBIST_MCBEA0Q; - static constexpr uint64_t END_ADDRESS_1 = MCBIST_MCBEA1Q; - static constexpr uint64_t END_ADDRESS_2 = MCBIST_MCBEA2Q; - static constexpr uint64_t END_ADDRESS_3 = MCBIST_MCBEA3Q; - - static constexpr uint64_t RANDOM_DATA_SEED0 = MCBIST_MCBRDS0Q; - static constexpr uint64_t RANDOM_DATA_SEED1 = MCBIST_MCBRDS1Q; - - - // MCBIST Compare Masks, used to setup the ECC traps - // TK there is one reg per port, does writing to this one write to all? - static constexpr uint64_t COMPARE_MASK = MCA_MCBCM; - - static constexpr uint64_t PATTERN_COUNT = 4; - - // Sometimes we want to access the start/end address registers based off - // of an index, like master rank. This allows us to do that. - static const std::pair<uint64_t, uint64_t> address_pairs[]; - - // Subtest types that need to be run in FIFO mode - static const std::vector< mss::mcbist::op_type > FIFO_MODE_REQUIRED_OP_TYPES; - - enum - { - // Subtest control bits. These are the same in all '16 bit subtest' field - COMPL_1ST_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, - COMPL_2ND_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD, - COMPL_3RD_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD, - ADDR_REV_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE, - ADDR_RAND_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE, - - // Goto subtests use the compl_1st - rand_mode to define the subtest to jump to - GOTO_SUBTEST = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, - GOTO_SUBTEST_LEN = 5, - - ECC_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE, - DATA_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE, - DATA_MODE_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN, - ADDR_SEL = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL, - ADDR_SEL_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN, - OP_TYPE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE, - OP_TYPE_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN, - DONE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE, - - SYNC_EN = MCBIST_MCBCFGQ_BROADCAST_SYNC_EN, - SYNC_WAIT = MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT, - SYNC_WAIT_LEN = MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN, - - PORT_SEL = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL, - PORT_SEL_LEN = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN, - - MCBIST_START = MCBIST_MCB_CNTLQ_START, - MCBIST_STOP = MCBIST_MCB_CNTLQ_STOP, - MCBIST_RESUME = MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE, - MCBIST_RESET_ERRORS = MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS, - - MCBIST_IN_PROGRESS = MCBIST_MCB_CNTLSTATQ_IP, - MCBIST_DONE = MCBIST_MCB_CNTLSTATQ_DONE, - MCBIST_FAIL = MCBIST_MCB_CNTLSTATQ_FAIL, - - MIN_CMD_GAP = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP, - MIN_CMD_GAP_LEN = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN, - MIN_GAP_TIMEBASE = MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE, - MIN_CMD_GAP_BLIND_STEER = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER, - MIN_CMD_GAP_BLIND_STEER_LEN = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN, - MIN_GAP_TIMEBASE_BLIND_STEER = MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER, - RANDCMD_WGT = MCBIST_MCBPARMQ_CFG_RANDCMD_WGT, - RANDCMD_WGT_LEN = MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN, - CLOCK_MONITOR_EN = MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN, - EN_RANDCMD_GAP = MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP, - RANDGAP_WGT = MCBIST_MCBPARMQ_CFG_RANDGAP_WGT, - RANDGAP_WGT_LEN = MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN, - BC4_EN = MCBIST_MCBPARMQ_CFG_BC4_EN, - - FIXED_WIDTH = MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH, - FIXED_WIDTH_LEN = MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN, - ADDR_COUNTER_MODE = MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE, - ADDR_COUNTER_MODE_LEN = MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN, - MAINT_ADDR_MODE_EN = MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN, - MAINT_BROADCAST_MODE_EN = MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN, - MAINT_DETECT_SRANK_BOUNDARIES = MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES, - - CFG_CMD_TIMEOUT_MODE = MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE, - CFG_CMD_TIMEOUT_MODE_LEN = MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN, - RESET_KEEPER = MCBIST_MCBCFGQ_RESET_KEEPER, - CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS, - CFG_CCS_RETRY_DIS = MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS, - CFG_RESET_CNTS_START_OF_RANK = MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK, - CFG_LOG_COUNTS_IN_TRACE = MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE, - SKIP_INVALID_ADDR_DIMM_DIS = MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS, - REFRESH_ONLY_SUBTEST_EN = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN, - REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL, - REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN, - RAND_ADDR_ALL_ADDR_MODE_EN = MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN, - MCBIST_CFG_REF_WAIT_TIME = MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME, - MCBIST_CFG_REF_WAIT_TIME_LEN = MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN, - CFG_MCB_LEN64 = MCBIST_MCBCFGQ_CFG_MCB_LEN64, - CFG_PAUSE_ON_ERROR_MODE = MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE, - CFG_PAUSE_ON_ERROR_MODE_LEN = MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN, - MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST, - MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR, - MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST, - CFG_ENABLE_SPEC_ATTN = MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN, - CFG_ENABLE_HOST_ATTN = MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN, - MCBIST_CFG_PAUSE_AFTER_RANK = MCBIST_MCBCFGQ_CFG_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK, - - LOGGED_ERROR_ON_PORT_INDICATOR = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR, - LOGGED_ERROR_ON_PORT_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN, - SUBTEST_NUM_INDICATOR = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR, - SUBTEST_NUM_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN, - - UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, - UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, - - CFG_AMAP_DIMM_SELECT = MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT, - CFG_AMAP_DIMM_SELECT_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN, - CFG_AMAP_MRANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0, - CFG_AMAP_MRANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN, - CFG_AMAP_MRANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1, - CFG_AMAP_MRANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN, - CFG_AMAP_SRANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0, - CFG_AMAP_SRANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN, - CFG_AMAP_SRANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1, - CFG_AMAP_SRANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN, - CFG_AMAP_SRANK2 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2, - CFG_AMAP_SRANK2_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN, - CFG_AMAP_BANK2 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2, - CFG_AMAP_BANK2_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN , - CFG_AMAP_BANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1, - CFG_AMAP_BANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN , - CFG_AMAP_BANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0, - CFG_AMAP_BANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN , - - CFG_AMAP_BANK_GROUP1 = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1, - CFG_AMAP_BANK_GROUP1_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN , - CFG_AMAP_BANK_GROUP0 = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0, - CFG_AMAP_BANK_GROUP0_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN , - CFG_AMAP_ROW17 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17, - CFG_AMAP_ROW17_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN, - CFG_AMAP_ROW16 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16, - CFG_AMAP_ROW16_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN, - CFG_AMAP_ROW15 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15, - CFG_AMAP_ROW15_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN, - CFG_AMAP_ROW14 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14, - CFG_AMAP_ROW14_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN, - CFG_AMAP_ROW13 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13, - CFG_AMAP_ROW13_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN, - CFG_AMAP_ROW12 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12, - CFG_AMAP_ROW12_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN, - CFG_AMAP_ROW11 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11, - CFG_AMAP_ROW11_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN, - CFG_AMAP_ROW10 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10, - CFG_AMAP_ROW10_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN, - - CFG_AMAP_ROW9 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9, - CFG_AMAP_ROW9_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN, - CFG_AMAP_ROW8 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8, - CFG_AMAP_ROW8_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN, - CFG_AMAP_ROW7 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7, - CFG_AMAP_ROW7_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN, - CFG_AMAP_ROW6 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6, - CFG_AMAP_ROW6_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN, - CFG_AMAP_ROW5 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5, - CFG_AMAP_ROW5_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN, - CFG_AMAP_ROW4 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4, - CFG_AMAP_ROW4_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN, - CFG_AMAP_ROW3 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3, - CFG_AMAP_ROW3_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN, - CFG_AMAP_ROW2 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2, - CFG_AMAP_ROW2_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN, - CFG_AMAP_ROW1 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1, - CFG_AMAP_ROW1_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN, - CFG_AMAP_ROW0 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0, - CFG_AMAP_ROW0_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN, - - CFG_AMAP_COL9 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9, - CFG_AMAP_COL9_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN, - CFG_AMAP_COL8 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8, - CFG_AMAP_COL8_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN, - CFG_AMAP_COL7 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7, - CFG_AMAP_COL7_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN, - CFG_AMAP_COL6 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6, - CFG_AMAP_COL6_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN, - CFG_AMAP_COL5 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5, - CFG_AMAP_COL5_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN, - CFG_AMAP_COL4 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4, - CFG_AMAP_COL4_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN, - CFG_AMAP_COL3 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3, - CFG_AMAP_COL3_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN, - CFG_AMAP_COL2 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2, - CFG_AMAP_COL2_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN, - - CFG_DATA_ROT_SEED1 = MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED, - CFG_DATA_ROT_SEED1_LEN = MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN, - CFG_DATA_ROT = MCBIST_MCBDRCRQ_CFG_DATA_ROT, - CFG_DATA_ROT_LEN = MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN, - CFG_DATA_ROT_SEED2 = MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED, - CFG_DATA_ROT_SEED2_LEN = MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN, - CFG_DATA_SEED_MODE = MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE, - CFG_DATA_SEED_MODE_LEN = MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN, - - CFG_TRAP_CE_ENABLE = MCA_MCBCM_MCBIST_TRAP_CE_ENABLE, - CFG_TRAP_UE_ENABLE = MCA_MCBCM_MCBIST_TRAP_UE_ENABLE, - CFG_TRAP_MPE_ENABLE = MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE, - - CFG_DGEN_RNDD_SEED0 = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0, - CFG_DGEN_RNDD_SEED0_LEN = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN, - CFG_DGEN_RNDD_SEED1 = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1, - CFG_DGEN_RNDD_SEED1_LEN = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN, - CFG_DGEN_RNDD_SEED2 = MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2, - CFG_DGEN_RNDD_SEED2_LEN = MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN, - CFG_DGEN_RNDD_DATA_MAPPING = MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING, - CFG_DGEN_RNDD_DATA_MAPPING_LEN = MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN, - - // Bit mapping for MCBIST error log control data (address+ in Nimbus doc) - ERROR_LOG_SUBTEST = 0, - ERROR_LOG_SUBTEST_LEN = 5, - ERROR_LOG_SUBCMD = 5, - ERROR_LOG_SUBCMD_LEN = 2, - ERROR_LOG_ADDR_DIMM = 7, - ERROR_LOG_ADDR_MRANK = 8, - ERROR_LOG_ADDR_MRANK_LEN = 2, - ERROR_LOG_ADDR_SRANK = 10, - ERROR_LOG_ADDR_SRANK_LEN = 3, - ERROR_LOG_ADDR_BANK_GROUP = 13, - ERROR_LOG_ADDR_BANK_GROUP_LEN = 2, - ERROR_LOG_ADDR_BANK = 15, - ERROR_LOG_ADDR_BANK_LEN = 3, - ERROR_LOG_ADDR_ROW = 18, - ERROR_LOG_ADDR_ROW_LEN = 18, - ERROR_LOG_ADDR_COLUMN = 36, - ERROR_LOG_ADDR_COLUMN_LEN = 8, - ERROR_LOG_BEAT = 44, - ERROR_LOG_BEAT_LEN = 2, - ERROR_LOG_TYPE = 46, - ERROR_LOG_TYPE_LEN = 2, - - //MCBIST FIR mask - MCB_PROGRAM_COMPLETE = MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE, - MCB_WAT_DEBUG_ATTN = MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN, - MCB_PROGRAM_COMPLETE_MASK = MCB_PROGRAM_COMPLETE, - MCB_WAT_DEBUG_ATTN_MASK = MCB_WAT_DEBUG_ATTN, - }; - -}; - -/// -/// @class mcbistTraits -/// @brief a collection of traits associated with the Nimbus MCA -/// -template<> -class mcbistTraits<fapi2::TARGET_TYPE_MCA> -{ - public: - // MCBIST error log related registers - static constexpr uint64_t ERROR_LOG_PTR_REG = MCA_ELPR; - static constexpr uint64_t RMW_WRT_BUF_CTL_REG = MCA_WREITE_AACR; - static constexpr uint64_t RMW_WRT_BUF_DATA_REG = MCA_AADR; - static constexpr uint64_t RMW_WRT_BUF_ECC_REG = MCA_AAER; - - enum - { - // Register field constants - ERROR_LOG_PTR = MCA_ELPR_LOG_POINTER, - ERROR_LOG_PTR_LEN = MCA_ELPR_LOG_POINTER_LEN, - ERROR_LOG_FULL = MCA_ELPR_LOG_FULL, - RMW_WRT_BUFFER_SEL = MCA_WREITE_AACR_BUFFER, - RMW_WRT_ADDRESS = MCA_WREITE_AACR_ADDRESS, - RMW_WRT_ADDRESS_LEN = MCA_WREITE_AACR_ADDRESS_LEN, - RMW_WRT_AUTOINC = MCA_WREITE_AACR_AUTOINC, - RMW_WRT_ECCGEN = MCA_WREITE_AACR_ECCGEN, - - // Constants used for field settings - SELECT_RMW_BUFFER = 0, - SELECT_WRT_BUFFER = 1, - - // Other constants - NUM_COMPARE_LOG_ENTRIES = 64, - // In compare mode, there is one "info" entry per 4 data (log) entries - // so compare mode only uses 16 info entries total in the rmw array - NUM_COMPARE_DATA_PER_INFO_LOG = 4, - NUM_COMPARE_INFO_ENTRIES = 16, - }; - -}; - -/// -/// @class mcbistTraits -/// @brief a collection of traits associated with the Nimbus MCS -/// -template<> -class mcbistTraits<fapi2::TARGET_TYPE_MCS> -{ - public: - // MCBIST error log related registers - static constexpr uint64_t RD_BUF_CTL_REG = MCS_PORT02_AACR; - static constexpr uint64_t RD_BUF_DATA_REG = MCS_PORT02_AADR; - static constexpr uint64_t RD_BUF_ECC_REG = MCS_PORT02_AAER; - - enum - { - // Register field constants - RB_BUFFER_SEL = MCS_PORT02_AACR_BUFFER, - RB_ADDRESS = MCS_PORT02_AACR_ADDRESS, - RB_ADDRESS_LEN = MCS_PORT02_AACR_ADDRESS_LEN, - RB_AUTOINC = MCS_PORT02_AACR_AUTOINC, - - // Other constants - NUM_COMPARE_LOG_ENTRIES = 64, - }; - -}; - -/// -/// @brief Return the estimated time an MCBIST subtest will take to complete -/// Useful for initial polling delays, probably isn't accurate for much else -/// as it doesn't take refresh in to account (which will necessarily slow down -/// the program.) -/// @param[in] i_target the target from which to gather memory frequency -/// @param[in] i_bytes number of *bytes* in the address range -/// @param[in] i_64B_per mss::YES if the command is 64B, mss::NO if it's 128B. Defaults to mss::YES -/// @return the initial polling delay for this program in ns -/// -template< fapi2::TargetType T > -inline uint64_t calculate_initial_delay(const fapi2::Target<T>& i_target, - const uint64_t i_bytes, - const bool i_64B_per = mss::YES) -{ - // TODO RTC: 164104 Update MCBIST delay calculator. As we learn more about what - // the lab really needs, we can probably make this function better. - const uint64_t l_bytes_per_cmd = (i_64B_per == mss::YES) ? 64 : 128; - - // Best case is a command takes 4 cycles. Given the number of commands and address space size - // we can get some idea of how long to wait before we start polling. - return cycles_to_ns(i_target, (i_bytes / l_bytes_per_cmd) * mss::CYCLES_PER_CMD); -} - namespace mcbist { -/// -/// @class subtest_t -/// @brief encapsulation of an MCBIST subtest. -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -class subtest_t -{ - public: - subtest_t( const uint16_t i_data = 0 ): - iv_mcbmr(i_data) - {} - - /// - /// @brief Checks if the op type requires FIFO mode to be on - /// @return bool fifo_mode_requried - true if FIFO mode is required to be forced on - /// - inline bool fifo_mode_required() const - { - // Gets the op type for this subtest - uint64_t l_value_to_find = 0; - iv_mcbmr.extractToRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(l_value_to_find); - - // Finds if this op type is in the vector that stores the OP types that require FIFO mode to be run - const auto l_op_type_it = std::find(TT::FIFO_MODE_REQUIRED_OP_TYPES.begin(), TT::FIFO_MODE_REQUIRED_OP_TYPES.end(), - l_value_to_find); - - // If the op type is required (aka was found), it will be less than end - // std::find returns the ending iterator if it was not found, so this will return false in that case - return l_op_type_it != TT::FIFO_MODE_REQUIRED_OP_TYPES.end(); - } - - /// - /// @brief Convert to a 16 bit int - /// @return the subtest as a 16 bit integer, useful for testing - /// - inline operator uint16_t() - { - return uint16_t(iv_mcbmr); - } - - /// - /// @brief Complement the data for the first subcommand - /// @param[in] i_state the desired state (mss::ON or mss::OFF) - /// - inline void change_compliment_1st_cmd( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::COMPL_1ST_CMD>(i_state); - return; - } - - /// - /// @brief Complement the data for the second subcommand - /// @param[in] i_state the desired state (mss::ON or mss::OFF) - /// @return void - /// - inline void change_compliment_2nd_cmd( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::COMPL_2ND_CMD>(i_state); - return; - } - - /// - /// @brief Complement the data for the third subcommand - /// @param[in] i_state the desired state (mss::ON or mss::OFF) - /// @return void - /// - inline void change_compliment_3rd_cmd( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::COMPL_3RD_CMD>(i_state); - return; - } - - /// - /// @brief Enable a specific port for this test - maint address mode - /// @param[in] i_port the port desired to be enabled - int 0, 1, 2, 3 - /// @note The port number is relative to the MCBIST - /// @return void - /// - inline void enable_port( const uint64_t i_port ) - { - constexpr uint64_t l_len = (TT::COMPL_2ND_CMD - TT::COMPL_1ST_CMD) + 1; - iv_mcbmr.template insertFromRight<TT::COMPL_1ST_CMD, l_len>(i_port); - return; - } - - /// - /// @brief Enable a specific dimm for this test - maint address mode - /// @param[in] i_dimm the dimm desired to be enabled - int 0, 1 - /// @return void - /// - inline void enable_dimm( const uint64_t i_dimm ) - { - iv_mcbmr.template writeBit<TT::COMPL_3RD_CMD>(i_dimm); - return; - } - - /// - /// @brief Get the port from this subtest - /// @note The port number is relative to the MCBIST - /// @return the port of the subtest - /// - inline uint64_t get_port() const - { - uint64_t l_port = 0; - constexpr uint64_t l_len = (TT::COMPL_2ND_CMD - TT::COMPL_1ST_CMD) + 1; - iv_mcbmr.template extractToRight<TT::COMPL_1ST_CMD, l_len>(l_port); - return l_port; - } - - /// - /// @brief Get the DIMM from this subtest - /// @return the DIMM this subtest has been configured for - /// - inline uint64_t get_dimm() const - { - return iv_mcbmr.template getBit<TT::COMPL_3RD_CMD>() ? 1 : 0; - } - - /// - /// @brief Add the subtest to go to - /// @param[in] the subtest to jump to - /// @return void - /// - inline void change_goto_subtest( const uint64_t i_jmp_to ) - { - iv_mcbmr.template insertFromRight<TT::GOTO_SUBTEST, TT::GOTO_SUBTEST_LEN>(i_jmp_to); - FAPI_INF("changing subtest to jump to %d (0x%02x)", i_jmp_to, iv_mcbmr); - return; - } - - /// - /// @brief Generate addresses in reverse order - /// @param[in] i_state the desired state of the function; mss:ON, mss::OFF - /// @return void - /// - inline void change_addr_rev_mode( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::ADDR_REV_MODE>(i_state); - return; - } - - /// - /// @brief Generate addresses in random order - /// @param[in] i_state the desired state of the function; mss:ON, mss::OFF - /// @return void - /// - inline void change_addr_rand_mode( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::ADDR_RAND_MODE>(i_state); - return; - } - - /// - /// @brief Generate and check data with ECC - /// @param[in] i_state the desired state of the function; mss:ON, mss::OFF - /// @return void - /// - inline void change_ecc_mode( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::ECC_MODE>(i_state); - return; - } - - /// - /// @brief Set the 'done after this test' bit - /// @param[in] i_state the desired state of the function; mss:ON, mss::OFF - /// @return void - /// - inline void change_done( const mss::states i_state ) - { - iv_mcbmr.template writeBit<TT::DONE>(i_state); - return; - } - - /// - /// @brief Set the data mode for this subtest - /// @param[in] i_mode the desired mcbist::data_mode - /// @return void - /// - inline void change_data_mode( const data_mode i_mode ) - { - iv_mcbmr.template insertFromRight<TT::DATA_MODE, TT::DATA_MODE_LEN>(i_mode); - return; - } - - /// - /// @brief Set the operation type for this subtest - /// @param[in] i_mode the desired mcbist::op_type - /// @return void - /// - inline void change_op_type( const op_type i_type ) - { - iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(i_type); - return; - } - - /// - /// @brief Configure which address registers to use for this subtest - /// @param[in] i_index 0 = MCBSA0Q, 1 = MCBSA1Q, ... - /// @note wraps to 0-3 no matter what value you pass in. - /// @return void - /// - inline void change_addr_sel( const uint16_t i_index ) - { - // Roll the index around - tidy support for an index which is out of range. - constexpr uint16_t MAX_ADDRESS_START_END_REGISTERS = 3 + 1; - iv_mcbmr.template insertFromRight<TT::ADDR_SEL, TT::ADDR_SEL_LEN>(i_index % MAX_ADDRESS_START_END_REGISTERS); - FAPI_INF("changed address select to index %d (0x%x)", i_index, iv_mcbmr); - return; - } - - // - // @brief operator== for mcbist subtests - // @param[in] i_rhs the right hand side of the compare - // @return bool, true iff i_rhs == this - inline bool operator==(const subtest_t<T>& i_rhs) const - { - return i_rhs.iv_mcbmr == iv_mcbmr; - } - - /// The mcbist 'memory register' for this subtest. - // Note that it is only 16 bits. - // Each 64b memory register contains multiple 16 bit subtest definitions. - // As we create a vector of subtests, we'll drop them in to their appropriate - // MCBMR register before executing. - fapi2::buffer<uint16_t> iv_mcbmr; -}; - -/// -/// @brief Return a write subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> write_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0000 - we want subtest type to be a Write (W) - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::WRITE); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 12 = 1 - ecc - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - // 14:15 = 0 address select config registers 0 - - return l_subtest; -} - - -/// -/// @brief Return an alter subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> alter_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 1011 - we want subtest type to be a Alter - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::ALTER); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return an display subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> display_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 1100 - we want subtest type to be a Display - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::DISPLAY); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return an scrub subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> scrub_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 1001 - we want subtest type to be a Scrub - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::SCRUB_RRWR); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a steer subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> steer_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 1010 - we want subtest type to be a Steer - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::STEER_RW); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a read subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> read_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0001 - we want subtest type to be a Read (R) - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a read write subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> read_write_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0010 - we want subtest type to be a Read Write (RW) - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ_WRITE); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a read write read subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> read_write_read_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0100 - we want subtest type to be a Read Write Read (RWR) 7 - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::READ_WRITE_READ); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a random subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> random_subtest() -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0110 - we want subtest type to be a Random Seq, a randomly chosen read or write - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::RAND_SEQ); - - // - Not a special subtest, so no other configs associated - // 4 = 0 - we don't want to complement data for our Writes - // 5:6 = 00 - don't know whether we complement 2nd and 3rd subcommand, caller to fix - // 7 = 0 - forward address generation - // 8 = 0 - non random address generation - // - Don't need to set up anything for LFSRs - // 9:11 = 000 - Fixed data mode - - // 14:15 = 0 address select config registers 0 - - // By default we want to turn on ECC. Caller can turn it off. - l_subtest.change_ecc_mode(mss::ON); - - return l_subtest; -} - -/// -/// @brief Return a goto subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] the subtest we should go to -/// @return mss::mcbist::subtest_t -/// @note Turns on ECC mode for the returned subtest - caller can turn it off -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> goto_subtest( const uint64_t i_jump_to ) -{ - // Starts life full of 0's - subtest_t<T> l_subtest; - - // 0:3 = 0111 - we want subtest type to be a Goto - l_subtest.iv_mcbmr.template insertFromRight<TT::OP_TYPE, TT::OP_TYPE_LEN>(op_type::GOTO_SUBTEST_N); - - // Plug in the subtest the user passed in - l_subtest.change_goto_subtest(i_jump_to); - return l_subtest; -} - -/// -/// @brief Return an init subtest - configured simply -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @return mss::mcbist::subtest_t -/// @note Configures for start/end address select bit as address config register 0 -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline subtest_t<T> init_subtest() -{ - return write_subtest<T>(); -} - -/// -/// @brief A class representing a series of MCBIST subtests, and the -/// MCBIST engine parameters associated with running the subtests -/// @tparam T fapi2::TargetType representing the fapi2 target which -/// contains the MCBIST engine (e.g., fapi2::TARGET_TYPE_MCBIST) -/// @tparam TT, the mssTraits associtated with T -/// @note MCBIST Memory Parameter Register defaults to -/// - issue commands as fast as possible -/// - even weighting of read/write if random addressing -/// - disable clock monitoring -/// - random command gap is disabled -/// - BC4 disabled -/// - no selected ports -/// @note Address Generation Config Register defaults to -/// - 0 fixed slots -/// - All address counter modes on (so addr configs are start + len) -/// - maint address mode enabled -/// - maint broadcast mode disabled -/// - maint slave rank boundary detect disabled -/// @note Config register defaults to -/// - BROADCAST_SYNC_EN disabled -/// - BROADCAST_SYNC_WAIT 0 -/// - TIMEOUT_MODE - wait 524288 cycles until timeout is called -/// - RESET_KEEPER - 0 -/// - CURRENT_ADDR_TRAP_UPDATE_DIS - 0 -/// - CCS_RETRY_DIS - 0 -/// - RESET_CNTS_START_OF_RANK - 0 -/// - LOG_COUNTS_IN_TRACE - 0 -/// - SKIP_INVALID_ADDR_DIMM_DIS - 0 -/// - REFRESH_ONLY_SUBTEST_EN - 0 -/// - REFRESH_ONLY_SUBTEST_TIMEBASE_SEL(0:1) - 0 -/// - RAND_ADDR_ALL_ADDR_MODE_EN - 0 -/// - REF_WAIT_TIME(0:13) - 0 -/// - MCB_LEN64 - 1 -/// - PAUSE_ON_ERROR_MODE(0:1) - don't pause on error -/// - PAUSE_AFTER_CCS_SUBTEST - don't puase after CCS subtest -/// - FORCE_PAUSE_AFTER_ADDR - don't pause after current address -/// - FORCE_PAUSE_AFTER_SUBTEST - no pause after subtest -/// - ENABLE_SPEC_ATTN - disabled -/// - ENABLE_HOST_ATTN - enabled -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -class program -{ - public: - // Setup our poll parameters so the MCBIST executer can see - // whether to use the delays in the instruction stream or not - program(): - iv_parameters(0), - iv_addr_gen(0), - iv_test_type(CENSHMOO), // Used as default in Centaur - iv_addr_map0(0), - iv_addr_map1(0), - iv_addr_map2(0), - iv_addr_map3(0), - iv_data_rotate_cnfg(0), - iv_data_rotate_seed(0), - iv_config(0), - iv_control(0), - iv_async(false), - iv_pattern(PATTERN_0), - iv_random24_data_seed(RANDOM24_SEEDS_0), - iv_random24_seed_map(RANDOM24_SEED_MAP_0), - iv_compare_mask(0) - { - // Enable the maintenance mode addressing - change_maint_address_mode(mss::ON); - - // Enable 64B lengths by default. Commands which need 128B (scrub, steer, alter, display) - // can change this to 128B (mss::OFF). - change_len64(mss::ON); - - // Turn off counting mode for all address configs - iv_addr_gen.insertFromRight<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(0b0000); - - // By default if there's an error, we stop after the errored address - iv_config.insertFromRight<TT::CFG_PAUSE_ON_ERROR_MODE, - TT::CFG_PAUSE_ON_ERROR_MODE_LEN>(end_boundary::STOP_AFTER_ADDRESS); - - // All mcbist attentions are host attentions, special attention bit is already clear - iv_config.setBit<TT::CFG_ENABLE_HOST_ATTN>(); - - } - - /// - /// @brief Change the DIMM select in the address mapping - /// @param[in] i_bitmap DIMM select bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_dimm_select_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_DIMM_SELECT, TT::CFG_AMAP_DIMM_SELECT_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the MRANK0 address mapping when not in 5D mode - /// @param[in] i_bitmap MRANK0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_mrank0_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_MRANK0, TT::CFG_AMAP_MRANK0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the MRANK0 address mapping when in 5D mode - /// @param[in] i_bitmap MRANK0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_mrank0_bit_5d( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK0, TT::CFG_AMAP_SRANK0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the MRANK1 address mapping when not in 5D mode - /// @param[in] i_bitmap MRANK1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_mrank1_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_MRANK1, TT::CFG_AMAP_MRANK1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the MRANK1 address mapping when in 5D mode - /// @param[in] i_bitmap MRANK1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_mrank1_bit_5d( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK1, TT::CFG_AMAP_SRANK1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the MRANK2 address mapping when in 5D mode - /// @param[in] i_bitmap MRANK2 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_mrank2_bit_5d( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK2, TT::CFG_AMAP_SRANK2_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the SRANK0 address mapping when in 5D mode - /// @param[in] i_bitmap SRANK0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_srank0_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK0, TT::CFG_AMAP_SRANK0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the SRANK1 address mapping - /// @param[in] i_bitmap SRANK1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_srank1_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK1, TT::CFG_AMAP_SRANK1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the SRANK2 address mapping - /// @param[in] i_bitmap SRANK2 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_srank2_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_SRANK2, TT::CFG_AMAP_SRANK2_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the BANK2 address mapping - /// @param[in] i_bitmap BANK2 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_bank2_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_BANK2, TT::CFG_AMAP_BANK2_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the BANK1 address mapping - /// @param[in] i_bitmap BANK1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_bank1_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_BANK1, TT::CFG_AMAP_BANK1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the BANK0 address mapping - /// @param[in] i_bitmap BANK0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_bank0_bit( const uint64_t i_bitmap ) - { - iv_addr_map0.insertFromRight<TT::CFG_AMAP_BANK0, TT::CFG_AMAP_BANK0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the BANK_GROUP1 address mapping - /// @param[in] i_bitmap BANK_GROUP1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_bank_group1_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_BANK_GROUP1, TT::CFG_AMAP_BANK_GROUP1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the BANK_GROUP0 address mapping - /// @param[in] i_bitmap BANK_GROUP0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_bank_group0_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_BANK_GROUP0, TT::CFG_AMAP_BANK_GROUP0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW17 address mapping - /// @param[in] i_bitmap ROW17 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row17_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW17, TT::CFG_AMAP_ROW17_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW16 address mapping - /// @param[in] i_bitmap ROW16 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row16_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW16, TT::CFG_AMAP_ROW16_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW15 address mapping - /// @param[in] i_bitmap ROW15 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row15_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW15, TT::CFG_AMAP_ROW15_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW14 address mapping - /// @param[in] i_bitmap ROW14 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row14_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW14, TT::CFG_AMAP_ROW14_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW13 address mapping - /// @param[in] i_bitmap ROW13 bit map in the address counter - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_row13_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW13, TT::CFG_AMAP_ROW13_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW12 address mapping - /// @param[in] i_bitmap ROW12 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row12_bit( const uint64_t i_bitmap ) - { - // CFG_AMAP_ROW12 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12 , - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW12, TT::CFG_AMAP_ROW12_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW11 address mapping - /// @param[in] i_bitmap ROW11 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row11_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW11, TT::CFG_AMAP_ROW11_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW10 address mapping - /// @param[in] i_bitmap ROW10 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row10_bit( const uint64_t i_bitmap ) - { - iv_addr_map1.insertFromRight<TT::CFG_AMAP_ROW10, TT::CFG_AMAP_ROW10_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW9 address mapping - /// @param[in] i_bitmap ROW9 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row9_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW9, TT::CFG_AMAP_ROW9_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW8 address mapping - /// @param[in] i_bitmap ROW8 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row8_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW8, TT::CFG_AMAP_ROW8_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW7 address mapping - /// @param[in] i_bitmap ROW7 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row7_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW7, TT::CFG_AMAP_ROW7_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW6 address mapping - /// @param[in] i_bitmap ROW6 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row6_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW6, TT::CFG_AMAP_ROW6_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW5 address mapping - /// @param[in] i_bitmap ROW5 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row5_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW5, TT::CFG_AMAP_ROW5_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW4 address mapping - /// @param[in] i_bitmap ROW4 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row4_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW4, TT::CFG_AMAP_ROW4_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW3 address mapping - /// @param[in] i_bitmap ROW3 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row3_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW3, TT::CFG_AMAP_ROW3_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW2 address mapping - /// @param[in] i_bitmap ROW2 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row2_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW2, TT::CFG_AMAP_ROW2_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW1 address mapping - /// @param[in] i_bitmap ROW1 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row1_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW1, TT::CFG_AMAP_ROW1_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the ROW0 address mapping - /// @param[in] i_bitmap ROW0 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_row0_bit( const uint64_t i_bitmap ) - { - iv_addr_map2.insertFromRight<TT::CFG_AMAP_ROW0, TT::CFG_AMAP_ROW0_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the COL9 address mapping - /// @param[in] i_bitmap COL9 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col9_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL9, TT::CFG_AMAP_COL9_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the COL8 address mapping - /// @param[in] i_bitmap COL8 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col8_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL8, TT::CFG_AMAP_COL8_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the COL7 address mapping - /// @param[in] i_bitmap COL7 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col7_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL7, TT::CFG_AMAP_COL7_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the COL6 address mapping - /// @param[in] i_bitmap COL6 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col6_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL6, TT::CFG_AMAP_COL6_LEN>(i_bitmap); - return; - } - - /// @brief Change the COL5 address mapping - /// @param[in] i_bitmap COL5 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col5_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL5, TT::CFG_AMAP_COL5_LEN>(i_bitmap); - return; - } - - /// @brief Change the COL4 address mapping - /// @param[in] i_bitmap COL4 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col4_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL4, TT::CFG_AMAP_COL4_LEN>(i_bitmap); - return; - } - - /// @brief Change the COL3 address mapping - /// @param[in] i_bitmap COL3 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col3_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL3, TT::CFG_AMAP_COL3_LEN>(i_bitmap); - return; - } - - /// @brief Change the COL2 address mapping - /// @param[in] i_bitmap COL2 bit map in the address counter - /// @note Assumes data is right-aligned - /// - inline void change_col2_bit( const uint64_t i_bitmap ) - { - iv_addr_map3.insertFromRight<TT::CFG_AMAP_COL2, TT::CFG_AMAP_COL2_LEN>(i_bitmap); - return; - } - - /// - /// @brief Change the mcbist 64/128 byte control - /// @param[in] i_state mss::ON if you want 64B, mss::OFF if you want 128B - /// @return void - /// - inline void change_len64( const mss::states i_state ) - { - iv_config.writeBit<TT::CFG_MCB_LEN64>(i_state); - return; - } - - /// - /// @brief Change the random address all address mode - /// @param[in] i_state mss::ON if you random addressing all addresses, mss::OFF if you don't - /// @return void - /// - inline void random_address_all( const mss::states i_state ) - { - iv_config.writeBit<TT::RAND_ADDR_ALL_ADDR_MODE_EN>(i_state); - return; - } - - /// - /// @brief Change the broadcast sync enable bit - /// @param[in] i_state mss::ON to enable the sync pulse, mss::OFF to disable - /// @return void - /// - inline void broadcast_sync_enable( const mss::states i_state ) - { - iv_config.writeBit<TT::SYNC_EN>(i_state); - return; - } - - /// - /// @brief Change the broadcast mode sync timbase count - /// @param[in] i_broadcast_timebase - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_broadcast_timebase( mss::mcbist::broadcast_timebase i_broadcast_timebase ) - { - iv_config.insertFromRight<TT::SYNC_WAIT, TT::SYNC_WAIT_LEN>(i_broadcast_timebase); - return; - } - - /// - /// @brief Change the mcbist thresholds - /// @param[in] i_thresholds the new thresholds/stop conditions - /// @return void - /// - inline void change_thresholds( const stop_conditions& i_thresholds ) - { - iv_thresholds = i_thresholds; - return; - } - - /// - /// @brief Change the data rotate value - /// @param[in] i_data_rotate - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_data_rotate( mss::mcbist::data_rotate_mode i_data_rotate ) - { - iv_data_rotate_cnfg.insertFromRight<TT::CFG_DATA_ROT, TT::CFG_DATA_ROT_LEN>(i_data_rotate); - return; - } - - /// - /// @brief Get the data rotate value - /// @note Assumes data is right aligned - /// @return the data rotate value config - /// - inline uint64_t get_data_rotate() - { - uint64_t l_data_rotate = 0; - iv_data_rotate_cnfg.extractToRight<TT::CFG_DATA_ROT, TT::CFG_DATA_ROT_LEN>(l_data_rotate); - return l_data_rotate; - } - - /// - /// @brief Change the data seed mode value - /// @param[in] i_data_seed_mode - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_data_seed_mode( const mss::mcbist::data_seed_mode i_data_seed_mode ) - { - iv_data_rotate_cnfg.insertFromRight<TT::CFG_DATA_SEED_MODE, TT::CFG_DATA_SEED_MODE_LEN>(i_data_seed_mode); - return; - } - - /// - /// @brief Get the data seed mode value - /// @note Assumes data is right aligned - /// @return the data seed mode value - /// - inline uint64_t get_data_seed_mode() - { - uint64_t l_data_seed_mode = 0; - iv_data_rotate_cnfg.extractToRight<TT::CFG_DATA_SEED_MODE, TT::CFG_DATA_SEED_MODE_LEN>(l_data_seed_mode); - return l_data_seed_mode; - } - - /// - /// @brief Change the data rotate seed for data bits 0:63 - /// @param[in] i_width - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_data_rotate_seed1( const uint64_t i_data_rotate_seed1 ) - { - iv_data_rotate_seed.insertFromRight<TT::CFG_DATA_ROT_SEED1, TT::CFG_DATA_ROT_SEED1_LEN>(i_data_rotate_seed1); - return; - } - - /// - /// @brief Get the data rotate seed for data bits 0:63 - /// @note Assumes data is right aligned - /// @return the data rotate seed for data bits 0:63 - /// - inline uint64_t get_data_rotate_seed1() - { - uint64_t l_data_rotate_seed1 = 0; - iv_data_rotate_seed.extractToRight<TT::CFG_DATA_ROT_SEED1, TT::CFG_DATA_ROT_SEED1_LEN>(l_data_rotate_seed1); - return l_data_rotate_seed1; - } - - /// - /// @brief Change the data rotate seed for data bits 64:79 - /// @param[in] i_width - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_data_rotate_seed2( const uint64_t i_data_rotate_seed2 ) - { - iv_data_rotate_cnfg.insertFromRight<TT::CFG_DATA_ROT_SEED2, TT::CFG_DATA_ROT_SEED2_LEN>(i_data_rotate_seed2); - return; - } - - /// - /// @brief Get the data rotate seed for data bits 64:79 - /// @note Assumes data is right aligned - /// @return the data rotate seed for data bits 64:79 - /// - inline uint64_t get_data_rotate_seed2() - { - uint64_t l_data_rotate_seed2 = 0; - iv_data_rotate_cnfg.extractToRight<TT::CFG_DATA_ROT_SEED2, TT::CFG_DATA_ROT_SEED2_LEN>(l_data_rotate_seed2); - return l_data_rotate_seed2; - } - - /// - /// @brief Change the compare mask CE trap enable - /// @param[in] i_state mss::ON to enable the trap, mss::OFF to disable the trap - /// @return void - /// - inline void change_ce_trap_enable( const mss::states i_state ) - { - iv_compare_mask.writeBit<TT::CFG_TRAP_CE_ENABLE>(i_state); - return; - } - - /// - /// @brief Change the compare mask UE trap enable - /// @param[in] i_state mss::ON to enable the trap, mss::OFF to disable the trap - /// @return void - /// - inline void change_ue_trap_enable( const mss::states i_state ) - { - iv_compare_mask.writeBit<TT::CFG_TRAP_UE_ENABLE>(i_state); - return; - } - - /// - /// @brief Change the compare mask MPE trap enable - /// @param[in] i_state mss::ON to enable the trap, mss::OFF to disable the trap - /// @return void - /// - inline void change_mpe_trap_enable( const mss::states i_state ) - { - iv_compare_mask.writeBit<TT::CFG_TRAP_MPE_ENABLE>(i_state); - return; - } - - /// - /// @brief Change the forced pause state - /// @param[in] i_end the end_boundary to pause at - /// @return void - /// - inline void change_forced_pause( const end_boundary& i_end ) - { - if (i_end == end_boundary::DONT_CHANGE) - { - return; - } - - // Clear all the forced pause bits so we don't stack pauses - iv_config.clearBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR>(); - iv_config.clearBit<TT::MCBIST_CFG_PAUSE_AFTER_RANK>(); - iv_config.clearBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST>(); - iv_addr_gen.clearBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>(); - - switch (i_end) - { - case end_boundary::STOP_AFTER_ADDRESS: - iv_config.setBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR>(); - break; - - case end_boundary::STOP_AFTER_SLAVE_RANK: - iv_config.setBit<TT::MCBIST_CFG_PAUSE_AFTER_RANK>(); - iv_addr_gen.setBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>(); - break; - - case end_boundary::STOP_AFTER_MASTER_RANK: - iv_config.setBit<TT::MCBIST_CFG_PAUSE_AFTER_RANK>(); - iv_addr_gen.clearBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>(); - break; - - case end_boundary::STOP_AFTER_SUBTEST: - iv_config.setBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST>(); - break; - - // None is all set, we cleared the bits above - case end_boundary::NONE: - break; - - // Default is a no forced pause (as we cleared all the bits) - default: - FAPI_INF("no forced pause state - end state %d unknown", i_end); - break; - }; - - return; - } - - /// - /// @brief Calculate minimum command gap for BG_SCRUB - /// @param[in] i_target the target behind which the memory sits - /// @param[in] i_freq the DRAM frequency - /// @param[in] i_size the sum of all DIMM sizes - /// @param[out] o_min_cmd_gap the setting for MCBPARMQ_CFG_MIN_CMD_GAP - /// @param[out] o_timebase the setting for MCBPARMQ_CFG_MIN_GAP_TIMEBASE - /// - inline void calculate_min_cmd_gap( const fapi2::Target<T>& i_target, - const uint64_t i_freq, - const uint64_t i_size, - uint64_t& o_min_cmd_gap, - mss::states& o_timebase ) - { - constexpr uint64_t l_seconds = SEC_IN_HOUR * BG_SCRUB_IN_HOURS; - constexpr uint64_t MIN_CMD_GAP = 0x001; - - // Sanity check our inputs, just assert if bad since they come directly from eff_config - // this will prevent us from any divide by zero problems - if ((i_freq == 0) || (i_size == 0)) - { - FAPI_ERR("received zero memory freq or size in calculate_min_cmd_gap"); - fapi2::Assert(false); - } - - // MIN CMD GAP = TOTAL CYCLES / TOTAL ADDRESSES - // TOTAL CYCLES = 12 hours x 60 min/hr x 60 sec/min x [DRAM freq] cycles/sec x - // 1/2 (MEM logic runs half DRAM freq) - const uint64_t l_mem_cycles_per_sec = (i_freq * T_PER_MT) / 2; - const uint64_t l_total_cycles = l_seconds * l_mem_cycles_per_sec; - - // TOTAL ADDRESSES = sum over all dimms of ( [DIMM CAPACITY]/128B ) - const uint64_t l_total_addresses = i_size * BYTES_PER_GB / 128; - - const auto l_min_cmd_gap = l_total_cycles / l_total_addresses; - - // If we're greater than the timebase, set the multiplier and divide down to get the gap setting - if (CMD_TIMEBASE < l_min_cmd_gap) - { - o_min_cmd_gap = l_min_cmd_gap / CMD_TIMEBASE; - o_timebase = mss::ON; - return; - } - - // If we're greater than the max gap setting, get as close to 12 hours as we can instead of just truncating - if (l_min_cmd_gap > MAX_CMD_GAP) - { - // work backwards to calculate what the total scrub time would be with the highest cmd gap with no multiplier... - const uint64_t l_scrub_time_fff = (l_total_addresses * MAX_CMD_GAP) / l_mem_cycles_per_sec; - // and with the lowest cmd gap with the multiplier - const uint64_t l_scrub_time_001 = (l_total_addresses * CMD_TIMEBASE) / l_mem_cycles_per_sec; - - if ((l_seconds - l_scrub_time_fff) > (l_scrub_time_001 - l_seconds)) - { - FAPI_INF("%s gap is greater than the field will allow. Setting to: %03x", mss::c_str(i_target), MIN_CMD_GAP); - o_min_cmd_gap = MIN_CMD_GAP; - o_timebase = mss::ON; - } - else - { - FAPI_INF("%s gap is greater than the field will allow. Setting to: %03x", mss::c_str(i_target), MAX_CMD_GAP); - o_min_cmd_gap = MAX_CMD_GAP; - o_timebase = mss::OFF; - } - - return; - } - - // Else, we're good to just set the calculated gap value directly - o_min_cmd_gap = l_min_cmd_gap; - o_timebase = mss::OFF; - } - - /// - /// @brief Change MCBIST Speed - /// @param[in] i_target the target behind which the memory sits - /// @param[in] i_speed the speed eunmeration - /// @return FAPI2_RC_SUCCSS iff ok - /// - inline fapi2::ReturnCode change_speed( const fapi2::Target<T>& i_target, const speed i_speed ) - { - switch (i_speed) - { - case speed::LUDICROUS: - change_min_cmd_gap(0); - change_min_gap_timebase(mss::OFF); - return fapi2::FAPI2_RC_SUCCESS; - break; - - case speed::BG_SCRUB: - { - uint64_t l_freq = 0; - uint64_t l_size = 0; - uint64_t l_min_cmd_gap = 0; - mss::states l_timebase = mss::OFF; - - constexpr uint64_t l_seconds = SEC_IN_HOUR * BG_SCRUB_IN_HOURS; - - FAPI_TRY( mss::freq(i_target, l_freq) ); - FAPI_TRY( mss::eff_memory_size<mss::mc_type::NIMBUS>(i_target, l_size) ); - - calculate_min_cmd_gap(i_target, l_freq, l_size, l_min_cmd_gap, l_timebase); - - FAPI_INF("%s setting bg scrub speed: %dMT/s, memory: %dGB, duration: %ds, gap: %d", - mss::c_str(i_target), l_freq, l_size, l_seconds, l_min_cmd_gap); - - change_min_cmd_gap(l_min_cmd_gap); - change_min_gap_timebase(l_timebase); - - return fapi2::FAPI2_RC_SUCCESS; - } - break; - - // Otherwise it's SAME_SPEED or something else in which case we do nothing - default: - break; - }; - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Get a list of ports involved in the program - /// @tparam P fapi2 target type of port - /// @param[in] i_target the target for this program - /// @return vector of port targets - /// - template< fapi2::TargetType P > - std::vector<fapi2::Target<P>> get_port_list( const fapi2::Target<T>& i_target ) const; - - /// - /// @brief Change MCBIST Stop-on-error conditions (end boundaries) - /// @param[in] i_end the end boundary - /// @note By default the MCBIST is programmed to always stop after an errored address. This API - /// allows the caller to force a stop at a boundary or to force no stopping on errors - /// - inline void change_end_boundary( const end_boundary i_end ) - { - // Which bit in the end boundary which siginifies this is a slave rank detect situation - constexpr uint64_t SLAVE_RANK_INDICATED_BIT = 61; - - // If there's no change, just get outta here - if (i_end == DONT_CHANGE) - { - return; - } - - // The values of the enum were crafted so that we can simply insertFromRight into the register. - // We take note of whether to set the slave or master rank indicator and set that as well. - // The hardware has to have a 1 or a 0 - so there is no choice for the rank detection. So it - // doesn't matter that we're processing other end boundaries here - they'll just look like we - // asked for a master rank detect. - iv_config.insertFromRight<TT::CFG_PAUSE_ON_ERROR_MODE, TT::CFG_PAUSE_ON_ERROR_MODE_LEN>(i_end); - - uint64_t l_detect_slave = fapi2::buffer<uint64_t>(i_end).getBit<SLAVE_RANK_INDICATED_BIT>(); - iv_addr_gen.writeBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>( l_detect_slave ); - FAPI_INF("load MCBIST end boundaries 0x%016lx detect slave? %s", - i_end, (l_detect_slave == 1 ? "yes" : "no") ); - } - - /// - /// @brief Change the mcbist min command gap - /// @param[in] i_gap minimum number of cycles between commands when cfg_en_randcmd_gap is a 0 (disabled) - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_min_cmd_gap( const uint64_t i_gap ) - { - iv_parameters.insertFromRight<TT::MIN_CMD_GAP, TT::MIN_CMD_GAP_LEN>(i_gap); - return; - } - - /// - /// @brief Change the mcbist gap timebase - /// @param[in] i_tb When set to mss::ON and cfg_en_randcmd_gap is a 0, then the number of minimum - /// cycles between commands will be cfg_min_cmd_gap multiplied by 2^13. - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_min_gap_timebase( const bool i_tb ) - { - iv_parameters.writeBit<TT::MIN_GAP_TIMEBASE>(i_tb); - return; - } - - /// - /// @brief Change the mcbist min command gap blind steer - /// @param[in] i_gap min gap between commands when doing steering - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_min_cmd_gap_blind_steer( const uint64_t i_gap ) - { - iv_parameters.insertFromRight<TT::MIN_CMD_GAP_BLIND_STEER, TT::MIN_CMD_GAP_BLIND_STEER_LEN>(i_gap); - return; - } - - /// - /// @brief Change the mcbist gap timebase for blind steer - /// @param[in] i_program the program in question - /// @param[in] i_tb When set to mss::ON and cfg_en_randcmd_gap is a 0, then the number of minimum - /// cycles between commands will be cfg_min_cmd_gap multiplied by 2^13. - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_min_gap_timebase_blind_steer( const bool i_tb ) - { - iv_parameters.writeBit<TT::MIN_GAP_TIMEBASE_BLIND_STEER>(i_tb); - return; - } - - /// - /// @brief Change the weights for random mcbist reads, writes - /// @param[in] i_weight - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_randcmd_wgt( const uint64_t i_weight ) - { - iv_parameters.insertFromRight<TT::RANDCMD_WGT, TT::RANDCMD_WGT_LEN>(i_weight); - return; - } - - /// - /// @brief Change the weights for random mcbist command gaps - /// @param[in] i_program the program in question - /// @param[in] i_weight - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_randgap_wgt( const uint64_t i_weight ) - { - iv_parameters.insertFromRight<TT::RANDGAP_WGT, TT::RANDGAP_WGT_LEN>(i_weight); - return; - } - - /// - /// @brief Enable or disable mcbist clock monitoring - /// @param[in] i_monitor mss::ON to monitor - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_clock_monitor_en( const bool i_monitor ) - { - iv_parameters.writeBit<TT::CLOCK_MONITOR_EN>(i_monitor); - return; - } - - /// - /// @brief Enable or disable mcbist random command gaps - /// @param[in] i_rndgap mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_en_randcmd_gap( const bool i_rndgap ) - { - iv_parameters.writeBit<TT::EN_RANDCMD_GAP>(i_rndgap); - return; - } - - /// - /// @brief Enable or disable mcbist BC4 support - /// @param[in] i_bc4 mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_bc4_en( const bool i_bc4 ) - { - iv_parameters.writeBit<TT::BC4_EN>(i_bc4); - return; - } - - /// - /// @brief Change fixed width address generator config - /// @param[in] i_width - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_fixed_width( const uint64_t i_width ) - { - iv_addr_gen.insertFromRight<TT::FIXED_WIDTH, TT::FIXED_WIDTH_LEN>(i_width); - return; - } - - /// - /// @brief Get the fixed width address config - /// @note Assumes data is right aligned - /// @return the fixed width address config - /// - inline uint64_t get_fixed_width() - { - uint64_t l_fixed_width = 0; - iv_addr_gen.extractToRight<TT::FIXED_WIDTH, TT::FIXED_WIDTH_LEN>(l_fixed_width); - return l_fixed_width; - } - - /// - /// @brief Enable or disable address counting mode for address config 0 - /// @param[in] i_mode mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_address_counter_mode0( const bool i_mode ) - { - fapi2::buffer<uint64_t> l_value; - iv_addr_gen.extract<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - l_value.writeBit<0>(i_mode); - iv_addr_gen.insert<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - return; - } - - /// - /// @brief Enable or disable address counting mode for address config 1 - /// @param[in] i_mode mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_address_counter_mode1( const bool i_mode ) - { - fapi2::buffer<uint64_t> l_value; - iv_addr_gen.extract<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - l_value.writeBit<1>(i_mode); - iv_addr_gen.insert<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - return; - } - - /// - /// @brief Enable or disable address counting mode for address config 2 - /// @param[in] i_mode mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_address_counter_mode2( const bool i_mode ) - { - fapi2::buffer<uint64_t> l_value; - iv_addr_gen.extract<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - l_value.writeBit<2>(i_mode); - iv_addr_gen.insert<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - return; - } - - /// - /// @brief Enable or disable address counting mode for address config 3 - /// @param[in] i_program, the program in question - /// @param[in] i_mode mss::ON to enable - /// @note Assumes data is right-aligned - /// @return void - /// - inline void change_address_counter_mode3( const bool i_mode ) - { - fapi2::buffer<uint64_t> l_value; - iv_addr_gen.extract<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - l_value.writeBit<3>(i_mode); - iv_addr_gen.insert<TT::ADDR_COUNTER_MODE, TT::ADDR_COUNTER_MODE_LEN>(l_value); - return; - } - - - /// - /// @brief Enable or disable maint address mode - /// @param[in] i_mode mss::ON to enable - /// @warn Address counter modes must be 0 for this to work. - /// @note When enabled subtest complement bits become 3-bit port-dimm selector field - /// (Note: when turning this off, make sure you clear or reprogram complement bits) - /// @return void - /// - inline void change_maint_address_mode( const bool i_mode ) - { - iv_addr_gen.writeBit<TT::MAINT_ADDR_MODE_EN>(i_mode); - return; - } - - /// - /// @brief Enable or disable broadcast mode - /// @param[in] i_program the program in question - /// @param[in] i_mode mss::ON to enable - /// @warn Maint address mode must be enabled for this to work - /// @return void - /// - inline void change_maint_broadcast_mode( const bool i_mode ) - { - iv_addr_gen.writeBit<TT::MAINT_BROADCAST_MODE_EN>(i_mode); - return; - } - - - /// - /// @brief Enable or disable slave rank boundary detect - /// @param[in] i_program the program in question - /// @param[in] i_mode mss::ON to enable - /// @return void - /// - inline void change_srank_boundaries( const bool i_mode ) - { - iv_addr_gen.writeBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>(i_mode); - return; - } - - /// - /// @brief Enable or disable async mode - /// @param[in] i_program the program in question - /// @param[in] i_mode mss::ON to enable, programs will run async - /// @return void - /// - inline void change_async( const bool i_mode ) - { - iv_async = i_mode; - return; - } - - /// - /// @brief Select the port(s) to be used by the MCBIST - /// @param[in] i_ports uint64_t representing the ports. Multiple bits set imply broadcast - /// i_ports is a right-aligned uint64_t, of which only the right-most 4 bits are used. The register - /// field is defined such that the left-most bit in the field represents port 0, the right most - /// bit in the field represents port 3. So, to run on port 0, i_ports should be 0b1000. 0b0001 - /// (or 0x1) is port 3 - not port 0 - /// @return void - /// - inline void select_ports( const uint64_t i_ports ) - { - iv_control.insertFromRight<TT::PORT_SEL, TT::PORT_SEL_LEN>(i_ports); - FAPI_INF("mcbist select ports: iv_control 0x%016lx (ports: 0x%x)", iv_control, i_ports); - return; - } - - /// - /// @brief Process mcbist errors - /// @tparam MCBIST target type - /// @tparam T fapi2::TargetType representing the fapi2 target which - /// contains the MCBIST engine (e.g., fapi2::TARGET_TYPE_MCBIST) - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok - /// This shouldn't be called in firmware? Check with PRD - /// - inline fapi2::ReturnCode process_errors( const fapi2::Target<T> i_target ) const - { - // Until reading the error array is documented, comparison errors 'just' result in - // a flag indicating there was a problem on port. - { - fapi2::buffer<uint64_t> l_data; - uint64_t l_port = 0; - uint64_t l_subtest = 0; - FAPI_TRY( mss::getScom(i_target, TT::MCBSTATQ_REG, l_data), "%s Failed getScom", mss::c_str(i_target) ); - l_data.extractToRight<TT::LOGGED_ERROR_ON_PORT_INDICATOR, TT::LOGGED_ERROR_ON_PORT_INDICATOR_LEN>(l_port); - l_data.extractToRight<TT::SUBTEST_NUM_INDICATOR, TT::SUBTEST_NUM_INDICATOR_LEN>(l_subtest); - - FAPI_ASSERT( l_port == 0, - fapi2::MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN() - .set_MCBIST_TARGET(i_target) - .set_PORT(mss::first_bit_set(l_port)) - .set_SUBTEST(l_subtest), - "%s MCBIST error on port %d subtest %d", mss::c_str(i_target), mss::first_bit_set(l_port), l_subtest ); - } - - // Check for UE errors - { - fapi2::buffer<uint64_t> l_read0; - fapi2::buffer<uint64_t> l_read1; - - FAPI_TRY( mss::getScom(i_target, TT::SRERR0_REG, l_read0), "%s Failed getScom", mss::c_str(i_target) ); - FAPI_TRY( mss::getScom(i_target, TT::SRERR1_REG, l_read1), "%s Failed getScom", mss::c_str(i_target) ); - - FAPI_ASSERT( ((l_read0 == 0) && (l_read1 == 0)), - fapi2::MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN() - .set_MCBIST_TARGET(i_target) - .set_STATUS0(l_read0) - .set_STATUS1(l_read1), - "%s MCBIST scrub/read error reg0: 0x%016lx reg1: 0x%016lx", mss::c_str(i_target), l_read0, l_read1 ); - } - - FAPI_INF("%s Execution success - no errors seen from MCBIST program", mss::c_str(i_target)); - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Store off the pattern index. We'll use this to write the patterns when we load the program - /// @param[in] i_index an index such as mss::mcbist::PATTERN_0 - /// @return fapi2::ReturnCode checks for bad pattern index - /// @warning if you give a pattern index which does not exist your pattern will not change. - /// @note patterns default to PATTERN_0 - /// - inline fapi2::ReturnCode change_pattern( const uint64_t i_pattern ) - { - FAPI_INF("change MCBIST pattern index %d", i_pattern); - - // Sanity check the pattern since they're just numbers. - FAPI_ASSERT( i_pattern <= mcbist::NO_PATTERN, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_pattern), - "Attempting to change a pattern which does not exist %d", i_pattern ); - - iv_pattern = i_pattern; - - return fapi2::FAPI2_RC_SUCCESS; - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Store off the random 24b data seed index. We'll use this to write the 24b random data seeds when we load the program - /// @param[in] i_index an index such as mss::mcbist::RANDOM24_SEEDS_0 - /// @return fapi2::ReturnCode checks for bad pattern index - /// @warning if you give a pattern index which does not exist your pattern will not change. - /// @note patterns default to PATTERN_0 - /// - inline fapi2::ReturnCode change_random_24b_seeds( const uint64_t i_random24_seed ) - { - FAPI_INF("change MCBIST 24b random data seeds index %d", i_random24_seed ); - - // TK Want a new RC for random 24 - // Sanity check the pattern since they're just numbers. - FAPI_ASSERT( i_random24_seed <= mcbist::NO_RANDOM24_SEEDS, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_random24_seed), - "Attempting to change to a 24b random data seed which does not exist %d", i_random24_seed ); - - iv_random24_data_seed = i_random24_seed; - - return fapi2::FAPI2_RC_SUCCESS; - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief Store off the random 24b data seed mapping index. We'll use this to write the 24b random data seed mappings when we load the program - /// @param[in] i_index an index such as mss::mcbist::RANDOM24_SEEDS_0 - /// @return fapi2::ReturnCode checks for bad pattern index - /// @warning if you give a pattern index which does not exist your pattern will not change. - /// @note patterns default to PATTERN_0 - /// - inline fapi2::ReturnCode change_random_24b_maps( const uint64_t i_random24_map ) - { - FAPI_INF("change MCBIST 24b random data seed mappings index %d", i_random24_map ); - - // TK Want a new RC for random 24 - // Sanity check the pattern since they're just numbers. - FAPI_ASSERT( i_random24_map <= mcbist::NO_RANDOM24_SEED_MAP, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_random24_map), - "Attempting to change to a random seed map which does not exist %d", i_random24_map ); - - iv_random24_seed_map = i_random24_map; - - return fapi2::FAPI2_RC_SUCCESS; - - fapi_try_exit: - return fapi2::current_err; - } - - /// - /// @brief checks if two programs are equal - /// @param[in] i_rhs program to compare - /// @return bool true if equal - /// - inline bool operator==( const program<T>& i_rhs ) const - { - //checks the vector first, to save time if they're not equal (no sense in checking everything else) - if(iv_subtests != i_rhs.iv_subtests) - { - return false; - } - - //checks everything else - bool l_equal = iv_parameters == i_rhs.iv_parameters; - l_equal &= iv_addr_gen == i_rhs.iv_addr_gen; - l_equal &= iv_test_type == i_rhs.iv_test_type; - l_equal &= iv_poll == i_rhs.iv_poll; - l_equal &= iv_addr_map0 == i_rhs.iv_addr_map0; - l_equal &= iv_addr_map1 == i_rhs.iv_addr_map1; - l_equal &= iv_addr_map2 == i_rhs.iv_addr_map2; - l_equal &= iv_addr_map3 == i_rhs.iv_addr_map3; - l_equal &= iv_config == i_rhs.iv_config; - l_equal &= iv_control == i_rhs.iv_control; - l_equal &= iv_async == i_rhs.iv_async; - l_equal &= iv_pattern == i_rhs.iv_pattern; - l_equal &= iv_thresholds == i_rhs.iv_thresholds; - l_equal &= iv_data_rotate_cnfg == i_rhs.iv_data_rotate_cnfg; - l_equal &= iv_data_rotate_seed == i_rhs.iv_data_rotate_seed; - l_equal &= iv_random24_data_seed == i_rhs.iv_random24_data_seed; - l_equal &= iv_random24_seed_map == i_rhs.iv_random24_seed_map; - l_equal &= iv_data_rotate_cnfg == i_rhs.iv_data_rotate_cnfg; - l_equal &= iv_data_rotate_seed == i_rhs.iv_data_rotate_seed; - l_equal &= iv_compare_mask == i_rhs.iv_compare_mask; - - //returns result - return l_equal; - } - - // Vector of subtests. Note the MCBIST subtests are spread across - // 8 registers - 4 subtests fit in one 64b register - // (16 bits/test, 4 x 16 == 64, 4x8 = 32 subtests) - // We keep a vector of 16 bit subtests here, and we program the - // MCBIST engine (i.e., spread the subtests over the 8 registers) - // when we're told to execute the program. - std::vector< subtest_t<T> > iv_subtests; - - // Place to hold the value of the MCBIST Memory Parameter Register. We'll scom - // it when we execute the program. - fapi2::buffer<uint64_t> iv_parameters; - - // Place to hold the value of the MCBIST Address Generation Config. We'll scom - // it when we execute the program. - fapi2::buffer<uint64_t> iv_addr_gen; - - test_type iv_test_type; - - poll_parameters iv_poll; - - // Address Map Registers - // We might want to refactor to a vector ... BRS - // uint64_t iv_addr_map0; - // uint64_t iv_addr_map1; - // uint64_t iv_addr_map2; - // uint64_t iv_addr_map3; - //Perhaps this isn't the right approach, we can discuss and change if needed, leaving the above comments for now - fapi2::buffer<uint64_t> iv_addr_map0; - fapi2::buffer<uint64_t> iv_addr_map1; - fapi2::buffer<uint64_t> iv_addr_map2; - fapi2::buffer<uint64_t> iv_addr_map3; - - // Data Rotate Seed and Config Registers - fapi2::buffer<uint64_t> iv_data_rotate_cnfg; - fapi2::buffer<uint64_t> iv_data_rotate_seed; - - // Config register - fapi2::buffer<uint64_t> iv_config; - - // Control register - fapi2::buffer<uint64_t> iv_control; - - // True iff we want to run in asynchronous mode - bool iv_async; - - // The pattern for the pattern generator - uint64_t iv_pattern; - - // The pattern for the random 24b seeds - uint64_t iv_random24_data_seed; - - // The pattern for the random 24b data seed mapping - uint64_t iv_random24_seed_map; - - // The pattern for the pattern generator - fapi2::buffer<uint64_t> iv_compare_mask; - - // The error stop conditions, thresholds for the program - stop_conditions iv_thresholds; -}; - -/// -/// @brief Load the mcbist config register -/// @tparam T fapi2::TargetType of the MCBIST engine -/// @tparam TT the mssTraits associtated with T -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_config( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - FAPI_INF("loading MCBIST Config 0x%016lx", i_program.iv_config); - - // Copy the program's config settings - we want to modify them if we're in sim. - fapi2::buffer<uint64_t> l_config = i_program.iv_config; - - // If we're running in Cronus, there is no interrupt so any attention bits will - // hang something somewhere. Make sure there's nothing in this config which can - // turn on attention bits unless we're running in hostboot -#ifndef __HOSTBOOT_MODULE - l_config.template clearBit<TT::CFG_ENABLE_HOST_ATTN>(); - l_config.template clearBit<TT::CFG_ENABLE_SPEC_ATTN>(); -#endif - - FAPI_TRY( mss::putScom(i_target, TT::CFGQ_REG, l_config) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Load the mcbist control register -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_control( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - FAPI_INF("loading MCBIST Control 0x%016lx", i_program.iv_control); - return mss::putScom(i_target, TT::CNTLQ_REG, i_program.iv_control); -} - - -/// -/// @brief Load the address generator config -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_addr_gen( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - FAPI_INF("loading MCBIST Address Generation 0x%016lx", i_program.iv_addr_gen); - return mss::putScom(i_target, TT::MCBAGRAQ_REG, i_program.iv_addr_gen); -} - -/// -/// @brief Configure address range based on index -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start 64b right-aligned address -/// @param[in] i_end 64b right-aligned address -/// @param[in] i_index which start/end pair to effect -/// @return FAPI2_RC_SUCCSS iff ok -/// @note Only the right-most 37 bits of the start/end are used. -/// @warn if address counting mode is enabled in the MCBIST program, these bits are start, len -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode config_address_range( const fapi2::Target<T>& i_target, const uint64_t i_start, - const uint64_t i_end, const uint64_t i_index ) -{ - FAPI_INF("config MCBIST address range %d start: 0x%016lx (0x%016lx), end/len 0x%016lx (0x%016lx)", - i_index, i_start, (i_start << 26), i_end, (i_end << 26)); - FAPI_TRY( mss::putScom(i_target, TT::address_pairs[i_index].first, i_start << 26) ); - FAPI_TRY( mss::putScom(i_target, TT::address_pairs[i_index].second, i_end << 26) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Configure address range 0 -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start 64b right-aligned address -/// @param[in] i_end 64b right-aligned address -/// @return FAPI2_RC_SUCCSS iff ok -/// @note Only the right-most 37 bits of the start/end are used. -/// @warn if address counting mode is enabled in the MCBIST program, these bits are start, len -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode config_address_range0( const fapi2::Target<T>& i_target, const uint64_t i_start, - const uint64_t i_end ) -{ - return config_address_range(i_target, i_start, i_end, 0); -} - - -/// -/// @brief Configure address range 1 -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start 64b right-aligned address -/// @param[in] i_end 64b right-aligned address -/// @return FAPI2_RC_SUCCSS iff ok -/// @note Only the right-most 37 bits of the start/end are used. -/// @warn if address counting mode is enabled in the MCBIST program, these bits are start, len -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode config_address_range1( const fapi2::Target<T>& i_target, const uint64_t i_start, - const uint64_t i_end ) -{ - return config_address_range(i_target, i_start, i_end, 1); -} - - -/// -/// @brief Configure address range 2 -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start 64b right-aligned address -/// @param[in] i_end 64b right-aligned address -/// @return FAPI2_RC_SUCCSS iff ok -/// @note Only the right-most 37 bits of the start/end are used. -/// @warn if address counting mode is enabled in the MCBIST program, these bits are start, len -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode config_address_range2( const fapi2::Target<T>& i_target, const uint64_t i_start, - const uint64_t i_end ) -{ - return config_address_range(i_target, i_start, i_end, 2); -} - - -/// -/// @brief Configure address range 3 -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start 64b right-aligned address -/// @param[in] i_end 64b right-aligned address -/// @return FAPI2_RC_SUCCSS iff ok -/// @note Only the right-most 37 bits of the start/end are used. -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode config_address_range3( const fapi2::Target<T>& i_target, const uint64_t i_start, - const uint64_t i_end ) -{ - return config_address_range(i_target, i_start, i_end, 3); -} - -/// -/// @brief Start or stop the MCBIST engine -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start_stop bool START for starting, STOP otherwise -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode start_stop( const fapi2::Target<T>& i_target, bool i_start_stop ) -{ - // This is the same as the CCS start_stop ... perhaps we need one template for all - // 'engine' control functions? BRS - fapi2::buffer<uint64_t> l_buf; - FAPI_TRY(mss::getScom(i_target, TT::CNTLQ_REG, l_buf)); - - FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, - i_start_stop ? l_buf.setBit<TT::MCBIST_START>() : l_buf.setBit<TT::MCBIST_STOP>()) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Resume the MCBIST engine -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode resume( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_buf; - - FAPI_TRY( mss::getScom(i_target, TT::CNTLQ_REG, l_buf) ); - FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, l_buf.setBit<TT::MCBIST_RESUME>()) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Reset the MCBIST error logs -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode reset_errors( const fapi2::Target<T>& i_target ) -{ - fapi2::buffer<uint64_t> l_buf; - - FAPI_TRY( mss::getScom(i_target, TT::CNTLQ_REG, l_buf) ); - FAPI_TRY( mss::putScom(i_target, TT::CNTLQ_REG, l_buf.setBit<TT::MCBIST_RESET_ERRORS>()) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Return whether or not the MCBIST engine has an operation in progress -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the target to effect -/// @param[out] i_in_progress - false if no operation is in progress -/// @return FAPI2_RC_SUCCESS if getScom succeeded -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode in_progress( const fapi2::Target<T>& i_target, bool o_in_progress ) -{ - fapi2::buffer<uint64_t> l_buf; - - FAPI_TRY(mss::getScom(i_target, TT::STATQ_REG, l_buf)); - o_in_progress = l_buf.getBit<TT::MCBIST_IN_PROGRESS>(); - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Execute the mcbist program -/// @tparam T the fapi2::TargetType - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist program to execute -/// @return fapi2::ReturnCode, FAPI2_RC_SUCCESS iff OK -/// -template< fapi2::TargetType T > -fapi2::ReturnCode execute( const fapi2::Target<T>& i_target, const program<T>& i_program ); - -/// -/// @brief Load a set of MCBIST subtests in to the MCBIST registers -/// @tparam T the fapi2::TargetType - derived -/// @tparam TT the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode load_mcbmr( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ); - - -/// -/// @brief Load a set of MCBIST address map registers -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] the target to effect -/// @param[in] the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode load_mcbamr( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - // Vector? Can decide when we fully understand the methods to twiddle the maps themselves. BRS - FAPI_INF("load MCBIST address map register 0: 0x%016lx", i_program.iv_addr_map0); - FAPI_TRY( mss::putScom(i_target, TT::MCBAMR0A0Q_REG, i_program.iv_addr_map0) ); - - FAPI_INF("load MCBIST address map register 1: 0x%016lx", i_program.iv_addr_map1); - FAPI_TRY( mss::putScom(i_target, TT::MCBAMR1A0Q_REG, i_program.iv_addr_map1) ); - - FAPI_INF("load MCBIST address map register 2: 0x%016lx", i_program.iv_addr_map2); - FAPI_TRY( mss::putScom(i_target, TT::MCBAMR2A0Q_REG, i_program.iv_addr_map2) ); - - FAPI_INF("load MCBIST address map register 3: 0x%016lx", i_program.iv_addr_map3); - FAPI_TRY( mss::putScom(i_target, TT::MCBAMR3A0Q_REG, i_program.iv_addr_map3) ); - -fapi_try_exit: - return fapi2::current_err; -} - - -/// -/// @brief Load MCBIST Memory Parameter Register -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] the target to effect -/// @param[in] the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_mcbparm( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - FAPI_INF("load MCBIST parameter register: 0x%016lx", i_program.iv_parameters); - return mss::putScom(i_target, TT::MCBPARMQ_REG, i_program.iv_parameters); -} - -/// -/// @brief Clear mcbist errors -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target fapi2::Target<T> of the MCBIST -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode clear_errors( const fapi2::Target<T> i_target ) -{ - // TK: Clear the more detailed errors checked above - FAPI_INF("Clear MCBIST error state"); - FAPI_TRY( mss::putScom(i_target, TT::MCBSTATQ_REG, 0) ); - FAPI_TRY( mss::putScom(i_target, TT::SRERR0_REG, 0) ); - FAPI_TRY( mss::putScom(i_target, TT::SRERR1_REG, 0) ); - FAPI_TRY( mss::putScom(i_target, TT::FIRQ_REG, 0) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST pattern given a pattern -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_pattern an mcbist::patterns -/// @param[in] i_invert whether to invert the pattern or not -/// @note this overload disappears when we have real patterns. -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_pattern( const fapi2::Target<T>& i_target, const pattern& i_pattern, const bool i_invert ) -{ - uint64_t l_address = TT::PATTERN0_REG; - - // TODO RTC:155561 Add random pattern support. - - // TK: algorithm for patterns which include ECC bits in them - // Loop over the cache lines in the pattern. We write one half of the cache line - // to the even register and half to the odd. - for (const auto& l_cache_line : i_pattern) - { - fapi2::buffer<uint64_t> l_value_first = i_invert ? ~l_cache_line.first : l_cache_line.first; - fapi2::buffer<uint64_t> l_value_second = i_invert ? ~l_cache_line.second : l_cache_line.second; - FAPI_INF("Loading cache line pattern 0x%016lx 0x%016lx", l_value_first, l_value_second); - FAPI_TRY( mss::putScom(i_target, l_address, l_value_first) ); - FAPI_TRY( mss::putScom(i_target, ++l_address, l_value_second) ); - ++l_address; - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST pattern given an index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_index the pattern index -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_pattern( const fapi2::Target<T>& i_target, uint64_t i_pattern ) -{ - if (NO_PATTERN != i_pattern) - { - bool l_invert = false; - - // Sanity check the pattern since they're just numbers. - // Belt-and-suspenders FAPI_ASSERT as the sim-only uses this API directly. - FAPI_ASSERT( i_pattern <= mcbist::LAST_PATTERN, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_pattern), - "Attempting to load a pattern which does not exist %d", i_pattern ); - - // The indexes are split in to even and odd where the odd indexes don't really exist. - // They're just indicating that we want to grab the even index and invert it. So calculate - // the proper vector index and acknowledge the inversion if necessary. - if (mss::is_odd(i_pattern)) - { - l_invert = true; - i_pattern -= 1; - } - - return load_pattern(i_target, patterns[i_pattern / 2], l_invert); - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST pattern given an index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_pattern( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - return load_pattern(i_target, i_program.iv_pattern); -} - -/// -/// @brief Load MCBIST maint pattern given a pattern -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_pattern an mcbist::patterns -/// @param[in] i_invert whether to invert the pattern or not -/// @note this overload disappears when we have real patterns. -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, const pattern& i_pattern, const bool i_invert ); - - -/// -/// @brief Load MCBIST maint pattern given an index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_index the pattern index -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, uint64_t i_pattern ) -{ - if (NO_PATTERN != i_pattern) - { - bool l_invert = false; - - // Sanity check the pattern since they're just numbers. - // Belt-and-suspenders FAPI_ASSERT as the sim-only uses this API directly. - FAPI_ASSERT( i_pattern <= mcbist::LAST_PATTERN, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_pattern), - "Attempting to load a pattern which does not exist %d", i_pattern ); - - // The indexes are split in to even and odd where the odd indexes don't really exist. - // They're just indicating that we want to grab the even index and invert it. So calculate - // the proper vector index and acknowledge the inversion if necessary. - if ((i_pattern % 2) != 0) - { - l_invert = true; - i_pattern -= 1; - } - - return load_maint_pattern(i_target, patterns[i_pattern / 2], l_invert); - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST Maint mode pattern given an index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_maint_pattern( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - return load_maint_pattern(i_target, i_program.iv_pattern); -} - - -/// -/// @brief Load MCBIST 24b random data seeds given a pattern index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_random24_data_seed mcbist::random24_data_seed -/// @param[in] i_random24_map mcbist::random24_seed_map -/// @param[in] i_invert whether to invert the pattern or not -/// @note this overload disappears when we have real patterns. -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<T>& i_target, - const random24_data_seed& i_random24_data_seed, - const random24_seed_map& i_random24_map, - const bool i_invert ); - -/// -/// @brief Load MCBIST 24b Random data seeds given a pattern index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_data_seed the 24b random data seed index -/// @param[in] i_seed_map the 24b random data map index -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<T>& i_target, uint64_t i_data_seed, - uint64_t i_seed_map ) -{ - if ((NO_RANDOM24_SEEDS != i_data_seed) && (NO_RANDOM24_SEED_MAP != i_seed_map)) - { - bool l_invert = false; - - // TK Want a new RC for random 24 - // Sanity check the pattern since they're just numbers. - // Belt-and-suspenders FAPI_ASSERT as the sim-only uses this API directly. - FAPI_ASSERT( i_data_seed <= mcbist::LAST_RANDOM24_SEEDS, - fapi2::MSS_MEMDIAGS_INVALID_PATTERN_INDEX().set_INDEX(i_data_seed), - "Attempting to load a 24b random data seed set which does not exist %d", i_data_seed ); - - // The indexes are split in to even and odd where the odd indexes don't really exist. - // They're just indicating that we want to grab the even index and invert it. So calculate - // the proper vector index and acknowledge the inversion if necessary. - if ((i_data_seed % 2) != 0) - { - l_invert = true; - i_data_seed -= 1; - } - - return load_random24b_seeds(i_target, random24_data_seeds[i_data_seed / 2], random24_seed_maps[i_seed_map], l_invert); - } - - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST 24b Random data seeds given a program conatining a pattern index -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_random24b_seeds( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - return load_random24b_seeds(i_target, i_program.iv_random24_data_seed, i_program.iv_random24_seed_map); -} - -/// -/// @brief Loads the FIFO value if needed -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_fifo_mode( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - - // Checks if FIFO mode is required by checking all subtests - const auto l_subtest_it = std::find_if(i_program.iv_subtests.begin(), - i_program.iv_subtests.end(), []( const mss::mcbist::subtest_t<T>& i_rhs) -> bool - { - return i_rhs.fifo_mode_required(); - }); - - // if the FIFO load is not needed (no subtest requiring it was found), just exit out - if(l_subtest_it == i_program.iv_subtests.end()) - { - return fapi2::FAPI2_RC_SUCCESS; - } - - // Turns on FIFO mode - constexpr mss::states FIFO_ON = mss::states::ON; - - FAPI_TRY(mss::configure_wrq(i_target, FIFO_ON)); - FAPI_TRY(mss::configure_rrq(i_target, FIFO_ON)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Load MCBIST data patterns and configuration -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_data_config( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - uint64_t l_data_rotate_cnfg_addr = TT::DATA_ROTATE_CNFG_REG; - uint64_t l_data_rotate_seed_addr = TT::DATA_ROTATE_SEED_REG; - - // First load the data pattern registers - FAPI_INF("Loading the data pattern seeds!"); - FAPI_TRY( mss::mcbist::load_pattern(i_target, i_program.iv_pattern) ); - - // Load the 24b random data pattern seeds registers - FAPI_INF("Loading the 24b Random data pattern seeds!"); - FAPI_TRY( mss::mcbist::load_random24b_seeds(i_target, i_program.iv_random24_data_seed, - i_program.iv_random24_seed_map) ); - - // Load the maint data pattern into the Maint entry in the RMW buffer - // TK Might want to only load the RMW buffer if maint commands are present in the program - // The load takes 33 Putscoms to load 16 64B registers, might slow down mcbist programs that - // don't need the RMW buffer maint entry loaded - FAPI_INF("Loading the maint data pattern into the RMW buffer!"); - FAPI_TRY( mss::mcbist::load_maint_pattern(i_target, i_program.iv_pattern) ); - - FAPI_INF("Loading the data rotate config and seeds!"); - FAPI_TRY( mss::putScom(i_target, l_data_rotate_cnfg_addr, i_program.iv_data_rotate_cnfg) ); - FAPI_TRY( mss::putScom(i_target, l_data_rotate_seed_addr, i_program.iv_data_rotate_seed) ); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// -/// @brief Load MCBIST data compare mask registers -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the mcbist::program -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode load_data_compare_mask( const fapi2::Target<T>& i_target, - const mcbist::program<T>& i_program ); - -/// -/// @brief Load MCBIST Thresholds -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_thresholds the thresholds -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_thresholds( const fapi2::Target<T>& i_target, const uint64_t i_thresholds ) -{ - FAPI_INF("load MCBIST threshold register: 0x%016lx", i_thresholds ); - return mss::putScom(i_target, TT::THRESHOLD_REG, i_thresholds); -} - -/// -/// @brief Load MCBIST Threshold Register -/// @tparam T, the fapi2::TargetType - derived -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_program the program containing the thresholds -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode load_thresholds( const fapi2::Target<T>& i_target, const mcbist::program<T>& i_program ) -{ - return load_thresholds(i_target, i_program.iv_thresholds); -} - -/// -/// @brief Read entries from MCBIST Read Modify Write (RMW) array -/// @tparam T, the fapi2::TargetType -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start_addr the array address to read first -/// @param[in] i_num_entries the number of array entries to read -/// @param[in] i_roll_over_for_compare_mode set to true if only using first -/// NUM_COMPARE_INFO_ENTRIES of array, so array address rolls over at correct value -/// @param[out] o_data vector of output data -/// @param[out] o_ecc_data vector of ecc data -/// @return FAPI2_RC_SUCCSS iff ok -/// @note The number of entries in the array depends on i_roll_over_for_compare_mode parameter: -/// (NUM_COMPARE_LOG_ENTRIES for false, NUM_COMPARE_INFO_ENTRIES for true) but user may read more than -/// that since reads work in a circular buffer fashion -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode read_rmw_array(const fapi2::Target<T>& i_target, - const uint64_t i_start_addr, - const uint64_t i_num_entries, - const bool i_roll_over_for_compare_mode, - std::vector< fapi2::buffer<uint64_t> >& o_data, - std::vector< fapi2::buffer<uint64_t> >& o_ecc_data); - -/// -/// @brief Read entries from MCBIST Read Modify Write (RMW) array -/// Overload for the case where o_ecc_data is not needed -/// @tparam T, the fapi2::TargetType -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start_addr the array address to read first -/// @param[in] i_num_entries the number of array entries to read -/// @param[in] i_roll_over_for_compare_mode set to true if only using first -/// NUM_COMPARE_INFO_ENTRIES of array, so array address rolls over at correct value -/// @param[out] o_data vector of output data -/// @return FAPI2_RC_SUCCSS iff ok -/// @note The number of entries in the array depends on i_roll_over_for_compare_mode parameter: -/// (NUM_COMPARE_LOG_ENTRIES for false, NUM_COMPARE_INFO_ENTRIES for true) but user may read more than -/// that since reads work in a circular buffer fashion -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode read_rmw_array(const fapi2::Target<T>& i_target, - const uint64_t i_start_addr, - const uint64_t i_num_entries, - const bool i_roll_over_for_compare_mode, - std::vector< fapi2::buffer<uint64_t> >& o_data) -{ - std::vector< fapi2::buffer<uint64_t> > l_temp; - return read_rmw_array(i_target, i_start_addr, i_num_entries, i_roll_over_for_compare_mode, o_data, l_temp); -} - -/// -/// @brief Read entries from MCBIST Read Buffer (RB) array -/// @tparam T, the fapi2::TargetType -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start_addr the array address to read first -/// @param[in] i_num_entries the number of array entries to read -/// @param[out] o_data vector of output data -/// @param[out] o_ecc_data vector of ecc data -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode read_rb_array(const fapi2::Target<T>& i_target, - const uint64_t i_start_addr, - const uint64_t i_num_entries, - std::vector< fapi2::buffer<uint64_t> >& o_data, - std::vector< fapi2::buffer<uint64_t> >& o_ecc_data); - -/// -/// @brief Read entries from MCBIST Read Buffer (RB) array -/// Overload for the case where o_ecc_data is not needed -/// @tparam T, the fapi2::TargetType -/// @tparam TT, the mcbistTraits associated with T - derived -/// @param[in] i_target the target to effect -/// @param[in] i_start_addr the array address to read first -/// @param[in] i_num_entries the number of array entries to read -/// @param[out] o_data vector of output data -/// @return FAPI2_RC_SUCCSS iff ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -fapi2::ReturnCode read_rb_array(const fapi2::Target<T>& i_target, - const uint64_t i_start_addr, - const uint64_t i_num_entries, - std::vector< fapi2::buffer<uint64_t> >& o_data) -{ - std::vector< fapi2::buffer<uint64_t> > l_temp; - return read_rb_array(i_target, i_start_addr, i_num_entries, o_data, l_temp); -} - -/// +//// /// @brief Checks if broadcast mode is capable of being enabled on this target /// @param[in] i_target the target to effect /// @param[in] i_bc_force attribute's value to force off broadcast mode @@ -3206,20 +77,23 @@ const mss::states is_broadcast_capable_helper(const fapi2::Target<fapi2::TARGET_ /// /// @brief Checks if broadcast mode is capable of being enabled on this target +/// @tparam MC the mc type of the T /// @tparam T, the fapi2::TargetType /// @param[in] i_target the target to effect /// @return o_capable - yes iff these vector of targets are broadcast capable /// -template< fapi2::TargetType T > +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > const mss::states is_broadcast_capable(const fapi2::Target<T>& i_target); + /// /// @brief Checks if broadcast mode is capable of being enabled on this vector of targets +/// @tparam MC the mc type of the T /// @tparam T, the fapi2::TargetType /// @param[in] i_targets the vector of targets to analyze /// @return o_capable - yes iff these vector of targets are broadcast capable /// -template< fapi2::TargetType T > +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > const mss::states is_broadcast_capable(const std::vector<fapi2::Target<T>>& i_targets); /// @@ -3227,191 +101,55 @@ const mss::states is_broadcast_capable(const std::vector<fapi2::Target<T>>& i_ta /// @param[in] i_target the target to effect /// @return o_capable - yes iff these vector of targets are broadcast capable /// -const mss::states is_broadcast_capable(const std::vector<mss::dimm::kind>& i_kinds); +const mss::states is_broadcast_capable(const std::vector<mss::dimm::kind<>>& i_kinds); + /// /// @brief Configures all of the ports for broadcast mode +/// @tparam MC the mc type of the T /// @tparam T, the fapi2::TargetType /// @param[in] i_target the target to effect /// @param[out] o_port_select - the configuration of the selected ports /// @return FAPI2_RC_SUCCSS iff ok /// -template< fapi2::TargetType T > +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > fapi2::ReturnCode setup_broadcast_port_select(const fapi2::Target<T>& i_target, uint64_t& o_port_select); /// /// @brief Enables broadcast mode +/// @tparam MC the mc type of the T /// @tparam T, the fapi2::TargetType /// @param[in] i_target the target to effect /// @param[in,out] io_program the mcbist::program /// @return FAPI2_RC_SUCCSS iff ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode enable_broadcast_mode(const fapi2::Target<T>& i_target, mcbist::program<T>& io_program); +template< mss::mc_type MC = DEFAULT_MC_TYPE, fapi2::TargetType T > +fapi2::ReturnCode enable_broadcast_mode(const fapi2::Target<T>& i_target, mcbist::program<>& io_program); /// -/// @brief Configures broadcast mode, if it is needed -/// @tparam T, the fapi2::TargetType +/// @brief Load MCBIST ECC (and?) spare data pattern given a pattern - explorer specialization /// @param[in] i_target the target to effect -/// @param[in,out] io_program the mcbist::program +/// @param[in] i_pattern an mcbist::patterns +/// @param[in] i_invert whether to invert the pattern or not +/// @note this overload disappears when we have real patterns. /// @return FAPI2_RC_SUCCSS iff ok /// -template< fapi2::TargetType T > -fapi2::ReturnCode configure_broadcast_mode(const fapi2::Target<T>& i_target, mcbist::program<T>& io_program) -{ - // If we're not capable to do broadcast mode on this target, exit out - const auto l_broadcast_capable = is_broadcast_capable(i_target); - - if(l_broadcast_capable == mss::states::NO) - { - FAPI_INF("%s is not broadcast capable, skipping enablement of broadcast mode", mss::c_str(i_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - - // Enable broadcast mode - FAPI_INF("%s is broadcast capable, enabling broadcast mode", mss::c_str(i_target)); - return enable_broadcast_mode(i_target, io_program); -} - -} // mcbist namespace - -/// -/// @brief Reads the contents of the MCBISTFIRMASK -/// @tparam T fapi2 Target Type - derived -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in] i_target the target on which to operate -/// @param[out] o_data the register data -/// @return fapi2::fapi2_rc_success if ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode read_mcbfirmask( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) +template< > +inline fapi2::ReturnCode load_eccspare_pattern<mss::mc_type::NIMBUS>( + const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const pattern& i_pattern, + const bool i_invert ) { - o_data = 0; + // First up assemble the pattern + const auto l_pattern = generate_eccspare_pattern(i_pattern, i_invert); - FAPI_TRY( mss::getScom(i_target, TT::MCBFIRMASK_REG, o_data ), "%s failed to read MCBISTFIRMASK regiser", - mss::c_str(i_target)); - FAPI_DBG("%s MCBISTFIRMASK has data 0x%016lx", mss::c_str(i_target), o_data); + FAPI_TRY(fapi2::putScom(i_target, MCBIST_MCBFDQ, l_pattern)); fapi_try_exit: return fapi2::current_err; } +} // namespace MCBIST -/// -/// @brief Writes the contents of the MCBISTFIRMASK -/// @tparam T fapi2 Target Type - derived -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in] i_target the target on which to operate -/// @param[in] i_data the register data -/// @return fapi2::fapi2_rc_success if ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode write_mcbfirmask( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::MCBFIRMASK_REG, i_data ), "%s failed to write MCBISTFIRMASK regiser", - mss::c_str(i_target)); - FAPI_DBG("%s MCBISTFIRMASK has data 0x%016lx", mss::c_str(i_target), i_data); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Reads the contents of the MCBISTFIRQ -/// @tparam T fapi2 Target Type - derived -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in] i_target the target on which to operate -/// @param[out] o_data the register data -/// @return fapi2::fapi2_rc_success if ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode read_mcbfirq( const fapi2::Target<T>& i_target, fapi2::buffer<uint64_t>& o_data ) -{ - o_data = 0; - - FAPI_TRY( mss::getScom(i_target, TT::MCBFIRQ_REG, o_data ), "%s failed to read MCBISTFIRQ regiser", - mss::c_str(i_target)); - FAPI_DBG("%s MCBISTFIRQ has data 0x%016lx", mss::c_str(i_target), o_data); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Writes the contents of the MCBISTFIRQ -/// @tparam T fapi2 Target Type - derived -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in] i_target the target on which to operate -/// @param[in] i_data the register data -/// @return fapi2::fapi2_rc_success if ok -/// -template< fapi2::TargetType T, typename TT = mcbistTraits<T> > -inline fapi2::ReturnCode write_mcbfirq( const fapi2::Target<T>& i_target, const fapi2::buffer<uint64_t>& i_data ) -{ - FAPI_TRY( mss::putScom(i_target, TT::MCBFIRQ_REG, i_data ), "%s failed to write MCBISTFIRQ regiser", - mss::c_str(i_target)); - FAPI_DBG("%s MCBISTFIRQ has data 0x%016lx", mss::c_str(i_target), i_data); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Sets the mask for program complete -/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in,out] io_data the value of the register -/// @param[in] i_state the state to write into the enable -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = mcbistTraits<T> > -inline void set_mcbist_program_complete_mask( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::MCB_PROGRAM_COMPLETE_MASK>(i_state == mss::states::ON); - FAPI_DBG("set_mcbist_program_complete_mask to %d 0x%016lx", i_state, io_data); -} - -/// -/// @brief Sets the mask for WAT debug ATTN -/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in,out] io_data the value of the register -/// @param[in] i_state the state to write into the enable -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = mcbistTraits<T> > -inline void set_mcbist_wat_debug_attn_mask( fapi2::buffer<uint64_t>& io_data, const mss::states i_state ) -{ - io_data.writeBit<TT::MCB_WAT_DEBUG_ATTN_MASK>(i_state == mss::states::ON); - FAPI_DBG("set_mcbist_wat_debug_attn_mask to %d 0x%016lx", i_state, io_data); -} - -/// -/// @brief Clears the program complete and WAT debug ATTN -/// @tparam T fapi2 Target Type - defaults to TARGET_TYPE_MCBIST -/// @tparam TT traits type defaults to mcbistTraits<T> -/// @param[in,out] io_data the value of the register -/// @param[in] i_state the state to write into the enable -/// -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = mcbistTraits<T> > -inline void clear_mcbist_program_complete( fapi2::buffer<uint64_t>& io_data ) -{ - io_data.writeBit<TT::MCB_PROGRAM_COMPLETE>(mss::states::OFF); - io_data.writeBit<TT::MCB_WAT_DEBUG_ATTN>(mss::states::OFF); - FAPI_DBG("clear_mcbist_program_complete to %d 0x%016lx", mss::states::OFF, io_data); -} - -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = mcbistTraits<T> > -inline void get_mcbist_program_complete_mask( const fapi2::buffer<uint64_t> i_data, mss::states& o_state ) -{ - o_state = i_data.getBit<TT::MCB_PROGRAM_COMPLETE>() ? mss::states::HIGH : mss::states::LOW; - FAPI_DBG("get_mcbist_program_complete_mask %d", o_state); -} - -template< fapi2::TargetType T = fapi2::TARGET_TYPE_MCBIST, typename TT = mcbistTraits<T> > -inline void get_mcbist_wat_debug_attn_mask( const fapi2::buffer<uint64_t> i_data, mss::states& o_state ) -{ - o_state = i_data.getBit<TT::MCB_WAT_DEBUG_ATTN>() ? mss::states::HIGH : mss::states::LOW; - FAPI_DBG("mcbist_wat_debug_attn_mask %d", o_state); -} - -} // mss namespace +} // namespace mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H index 6936f7aff..7d9d3ab2c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/mcbist_traits.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -22,3 +22,645 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + +/// +/// @file mcbist_traits.H +/// @brief Run and manage the MCBIST engine +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_MCBIST_TRAITS_H_ +#define _MSS_MCBIST_TRAITS_H_ + +#include <fapi2.H> + +#include <lib/shared/mss_const.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_address.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_traits.H> +#include <p9_mc_scom_addresses.H> +#include <p9_mc_scom_addresses_fld.H> + +namespace mss +{ + +/// +/// @class mcbistMCTraits +/// @brief A MC to MC_TARGET_TYPE mapping +/// +template<> +class mcbistMCTraits<mss::mc_type::NIMBUS> +{ + public: + static constexpr fapi2::TargetType MC_TARGET_TYPE = fapi2::TARGET_TYPE_MCBIST; + static constexpr fapi2::TargetType FWMS_ADDR_TARGET_TYPE = fapi2::TARGET_TYPE_MCA; + + /// + /// @brief Returns an error for memdiags compare error in last pattern + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN memdiags_compare_error_in_last_pattern() + { + return fapi2::MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN(); + } + + /// + /// @brief Returns an error for memdiags error in last pattern + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN memdiags_error_in_last_pattern() + { + return fapi2::MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN(); + } + + /// + /// @brief Returns an error if memdiags failed to start + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_START memdiags_failed_to_start() + { + return fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_START(); + } + + /// + /// @brief Returns an error if memdiags failed to stop + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_STOP memdiags_failed_to_stop() + { + return fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_STOP(); + } + + /// + /// @brief Returns an error if memdiags has a non-functional port + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_PORT_NOT_FUNCTIONAL memdiags_port_not_functional() + { + return fapi2::MSS_MEMDIAGS_PORT_NOT_FUNCTIONAL(); + } + + /// + /// @brief Returns an error if memdiags super fast init failed to init + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT memdiags_sf_init_failed_init() + { + return fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags super fast read failed to init + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT memdiags_sf_read_failed_init() + { + return fapi2::MSS_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags continuous scrub failed to init + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT memdiags_continuous_scrub_failed_init() + { + return fapi2::MSS_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags targeted scrub failed to init + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT memdiags_targeted_scrub_failed_init() + { + return fapi2::MSS_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT(); + } + + /// + /// @brief Returns an error if memdiags is already at a boundary + /// @return memdiags error + /// + static fapi2::MSS_MEMDIAGS_ALREADY_AT_BOUNDARY memdiags_already_at_boundary() + { + return fapi2::MSS_MEMDIAGS_ALREADY_AT_BOUNDARY(); + } + + /// + /// @brief Returns an error if MCBIST timesout + /// @return MCBIST error + /// + static fapi2::MSS_MCBIST_TIMEOUT mcbist_timeout() + { + return fapi2::MSS_MCBIST_TIMEOUT(); + } + + /// + /// @brief Returns an error if MCBIST has an unknown failure + /// @return MCBIST error + /// + static fapi2::MSS_MCBIST_UNKNOWN_FAILURE mcbist_unknown_failure() + { + return fapi2::MSS_MCBIST_UNKNOWN_FAILURE(); + } + + /// + /// @brief Returns an error if MCBIST has a data miscompare + /// @return MCBIST error + /// + static fapi2::MSS_MCBIST_DATA_FAIL mcbist_data_fail() + { + return fapi2::MSS_MCBIST_DATA_FAIL(); + } +}; + +/// +/// @class mcbistTraits +/// @brief a collection of traits associated with the Nimbus MCBIST engine or hardware +/// +template<> +class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCBIST> +{ + public: + + // PORT_TYPE used in continuous_scrub_operation + static constexpr enum fapi2::TargetType PORT_TYPE = fapi2::TARGET_TYPE_MCA; + + // ATTN support + static constexpr mss::states CFG_ENABLE_ATTN_SUPPORT = mss::states::YES; + static constexpr mss::states BROADCAST_CAPABLE = mss::states::YES; + + // Multi-ports, dimms + static constexpr mss::states MULTI_PORTS = mss::states::YES; + + // Subtest + static constexpr size_t SUBTEST_PER_REG = 4; + static constexpr size_t SUBTEST_PER_PROGRAM = 32; + static constexpr size_t BITS_IN_SUBTEST = 16; // 2 Bytes + static constexpr size_t LEFT_SHIFT = (sizeof(uint64_t) * 8) - BITS_IN_SUBTEST; + + // LARGEST_ADDRESS + static constexpr uint64_t LARGEST_ADDRESS = ~0 >> mss::mcbist::address::MAGIC_PAD; + + // Length of expected patterns + static constexpr uint64_t EXPECTED_PATTERN_SIZE = 4; + + // Size + static constexpr size_t PORTS_PER_MCBIST = mss::PORTS_PER_MCBIST; + static constexpr size_t MAX_DIMM_PER_PORT = mss::MAX_DIMM_PER_PORT; + static constexpr size_t MAX_PRIMARY_RANKS_PER_PORT = mss::MAX_PRIMARY_RANKS_PER_PORT; + static constexpr size_t MAX_DQ_BITS = 72; + static constexpr size_t MAX_DQ_NIBBLES = MAX_DQ_BITS / + BITS_PER_NIBBLE; ///< For ISDIMMs are 18 DQ nibbles for DQ 72 bits + static constexpr size_t MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_BYTE; ///< For x8's there are 9 DRAM for 72 bits + static constexpr size_t MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE; ///< For x4's there are 18 DRAM for 72 bits + + /// MCBIST "memory registers" - config for subtests. + static constexpr uint64_t MCBMR0_REG = MCBIST_MCBMR0Q; + static constexpr uint64_t MCBMR1_REG = MCBIST_MCBMR1Q; + static constexpr uint64_t MCBMR2_REG = MCBIST_MCBMR2Q; + static constexpr uint64_t MCBMR3_REG = MCBIST_MCBMR3Q; + static constexpr uint64_t MCBMR4_REG = MCBIST_MCBMR4Q; + static constexpr uint64_t MCBMR5_REG = MCBIST_MCBMR5Q; + static constexpr uint64_t MCBMR6_REG = MCBIST_MCBMR6Q; + static constexpr uint64_t MCBMR7_REG = MCBIST_MCBMR7Q; + static constexpr uint64_t CFGQ_REG = MCBIST_MCBCFGQ; + static constexpr uint64_t CNTLQ_REG = MCBIST_MCB_CNTLQ; + static constexpr uint64_t STATQ_REG = MCBIST_MCB_CNTLSTATQ; + static constexpr uint64_t MCBSTATQ_REG = MCBIST_MCBSTATQ; + static constexpr uint64_t MCBPARMQ_REG = MCBIST_MCBPARMQ; + static constexpr uint64_t MCBAGRAQ_REG = MCBIST_MCBAGRAQ; + static constexpr uint64_t SRERR0_REG = MCBIST_MBSEC0Q; + static constexpr uint64_t SRERR1_REG = MCBIST_MBSEC1Q; + static constexpr uint64_t THRESHOLD_REG = MCBIST_MBSTRQ; + static constexpr uint64_t FIRQ_REG = MCBIST_MCBISTFIRQ; + static constexpr uint64_t LAST_ADDR_REG = MCBIST_MCBMCATQ; + + static constexpr uint64_t MCBAMR0A0Q_REG = MCBIST_MCBAMR0A0Q; + static constexpr uint64_t MCBAMR1A0Q_REG = MCBIST_MCBAMR1A0Q; + static constexpr uint64_t MCBAMR2A0Q_REG = MCBIST_MCBAMR2A0Q; + static constexpr uint64_t MCBAMR3A0Q_REG = MCBIST_MCBAMR3A0Q; + static constexpr uint64_t LFSR_REG = MCBIST_MCBLFSRA0Q; + static const std::vector<uint64_t> LFSR_MASK_VALUES; + + // MCBIST FIR registers + static constexpr uint64_t MCBFIRMASK_REG = MCBIST_MCBISTFIRMASK; + static constexpr uint64_t MCBFIRQ_REG = MCBIST_MCBISTFIRQ; + + // All of the pattern registers are calculated off of this base + static constexpr uint64_t PATTERN0_REG = MCBIST_MCBFD0Q; + static constexpr uint64_t PATTERN1_REG = MCBIST_MCBFD1Q; + static constexpr uint64_t PATTERN2_REG = MCBIST_MCBFD2Q; + static constexpr uint64_t PATTERN3_REG = MCBIST_MCBFD3Q; + static constexpr uint64_t PATTERN4_REG = MCBIST_MCBFD4Q; + static constexpr uint64_t PATTERN5_REG = MCBIST_MCBFD5Q; + static constexpr uint64_t PATTERN6_REG = MCBIST_MCBFD6Q; + static constexpr uint64_t PATTERN7_REG = MCBIST_MCBFD7Q; + + static constexpr uint64_t DATA_ROTATE_CNFG_REG = MCBIST_MCBDRCRQ; + static constexpr uint64_t DATA_ROTATE_SEED_REG = MCBIST_MCBDRSRQ; + + static constexpr uint16_t MAX_ADDRESS_START_END_REGISTERS = 4; + static constexpr uint64_t START_ADDRESS_0 = MCBIST_MCBSA0Q; + static constexpr uint64_t START_ADDRESS_1 = MCBIST_MCBSA1Q; + static constexpr uint64_t START_ADDRESS_2 = MCBIST_MCBSA2Q; + static constexpr uint64_t START_ADDRESS_3 = MCBIST_MCBSA3Q; + + static constexpr uint64_t END_ADDRESS_0 = MCBIST_MCBEA0Q; + static constexpr uint64_t END_ADDRESS_1 = MCBIST_MCBEA1Q; + static constexpr uint64_t END_ADDRESS_2 = MCBIST_MCBEA2Q; + static constexpr uint64_t END_ADDRESS_3 = MCBIST_MCBEA3Q; + + static constexpr uint64_t RANDOM_DATA_SEED0 = MCBIST_MCBRDS0Q; + static constexpr uint64_t RANDOM_DATA_SEED1 = MCBIST_MCBRDS1Q; + + + static constexpr uint64_t MBSTRQ_CFG_PAUSE_ON_MPE = MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE; + + + // MCBIST Compare Masks, used to setup the ECC traps + // TK there is one reg per port, does writing to this one write to all? + static constexpr uint64_t COMPARE_MASK = MCA_MCBCM; + + static constexpr uint64_t PATTERN_COUNT = 4; + + // Sometimes we want to access the start/end address registers based off + // of an index, like master rank. This allows us to do that. + static const std::pair<uint64_t, uint64_t> address_pairs[]; + static constexpr uint64_t ADDRESS_PAIRS = 4; + + // Subtest types that need to be run in FIFO mode + static const std::vector< mss::mcbist::op_type > FIFO_MODE_REQUIRED_OP_TYPES; + + // Which bit in the end boundary which siginifies this is a slave rank detect situation + static constexpr uint64_t SLAVE_RANK_INDICATED_BIT = 61; + + enum + { + // The start/end address config registers have common lengths and bits, just including 1 below + MCB_ADDR_CONFIG = MCBIST_MCBEA0Q_CFG_END_ADDR_0, + MCB_ADDR_CONFIG_LEN = MCBIST_MCBEA0Q_CFG_END_ADDR_0_LEN, + + // Subtest control bits. These are the same in all '16 bit subtest' field + COMPL_1ST_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, + COMPL_2ND_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_2ND_CMD, + COMPL_3RD_CMD = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_3RD_CMD, + ADDR_REV_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_REV_MODE, + ADDR_RAND_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_RAND_MODE, + + // Goto subtests use the compl_1st - rand_mode to define the subtest to jump to + GOTO_SUBTEST = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_COMPL_1ST_CMD, + GOTO_SUBTEST_LEN = 5, + + ECC_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ECC_MODE, + DATA_MODE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE, + DATA_MODE_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DATA_MODE_LEN, + ADDR_SEL = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL, + ADDR_SEL_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_ADDR_SEL_LEN, + OP_TYPE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE, + OP_TYPE_LEN = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_OP_TYPE_LEN, + DONE = MCBIST_MCBMR0Q_MCBIST_CFG_TEST00_DONE, + + SYNC_EN = MCBIST_MCBCFGQ_BROADCAST_SYNC_EN, + SYNC_WAIT = MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT, + SYNC_WAIT_LEN = MCBIST_MCBCFGQ_BROADCAST_SYNC_WAIT_LEN, + + PORT_SEL = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL, + PORT_SEL_LEN = MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN, + + MCBIST_START = MCBIST_MCB_CNTLQ_START, + MCBIST_STOP = MCBIST_MCB_CNTLQ_STOP, + MCBIST_RESUME = MCBIST_MCB_CNTLQ_RESUME_FROM_PAUSE, + MCBIST_RESET_ERRORS = MCBIST_MCB_CNTLQ_RESET_ERROR_LOGS, + + MCBIST_IN_PROGRESS = MCBIST_MCB_CNTLSTATQ_IP, + MCBIST_DONE = MCBIST_MCB_CNTLSTATQ_DONE, + MCBIST_FAIL = MCBIST_MCB_CNTLSTATQ_FAIL, + + MIN_CMD_GAP = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP, + MIN_CMD_GAP_LEN = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_LEN, + MIN_GAP_TIMEBASE = MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE, + MIN_CMD_GAP_BLIND_STEER = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER, + MIN_CMD_GAP_BLIND_STEER_LEN = MCBIST_MCBPARMQ_CFG_MIN_CMD_GAP_BLIND_STEER_LEN, + MIN_GAP_TIMEBASE_BLIND_STEER = MCBIST_MCBPARMQ_CFG_MIN_GAP_TIMEBASE_BLIND_STEER, + RANDCMD_WGT = MCBIST_MCBPARMQ_CFG_RANDCMD_WGT, + RANDCMD_WGT_LEN = MCBIST_MCBPARMQ_CFG_RANDCMD_WGT_LEN, + CLOCK_MONITOR_EN = MCBIST_MCBPARMQ_CFG_CLOCK_MONITOR_EN, + EN_RANDCMD_GAP = MCBIST_MCBPARMQ_CFG_EN_RANDCMD_GAP, + RANDGAP_WGT = MCBIST_MCBPARMQ_CFG_RANDGAP_WGT, + RANDGAP_WGT_LEN = MCBIST_MCBPARMQ_CFG_RANDGAP_WGT_LEN, + BC4_EN = MCBIST_MCBPARMQ_CFG_BC4_EN, + + FIXED_WIDTH = MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH, + FIXED_WIDTH_LEN = MCBIST_MCBAGRAQ_CFG_FIXED_WIDTH_LEN, + ADDR_COUNTER_MODE = MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE, + ADDR_COUNTER_MODE_LEN = MCBIST_MCBAGRAQ_CFG_ADDR_COUNTER_MODE_LEN, + MAINT_ADDR_MODE_EN = MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN, + MAINT_BROADCAST_MODE_EN = MCBIST_MCBAGRAQ_CFG_MAINT_BROADCAST_MODE_EN, + MAINT_DETECT_SRANK_BOUNDARIES = MCBIST_MCBAGRAQ_CFG_MAINT_DETECT_SRANK_BOUNDARIES, + + CFG_CMD_TIMEOUT_MODE = MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE, + CFG_CMD_TIMEOUT_MODE_LEN = MCBIST_MCBCFGQ_CFG_CMD_TIMEOUT_MODE_LEN, + RESET_KEEPER = MCBIST_MCBCFGQ_RESET_KEEPER, + CFG_CURRENT_ADDR_TRAP_UPDATE_DIS = MCBIST_MCBCFGQ_CFG_CURRENT_ADDR_TRAP_UPDATE_DIS, + CFG_CCS_RETRY_DIS = MCBIST_MCBCFGQ_CFG_CCS_RETRY_DIS, + CFG_RESET_CNTS_START_OF_RANK = MCBIST_MCBCFGQ_CFG_RESET_CNTS_START_OF_RANK, + CFG_LOG_COUNTS_IN_TRACE = MCBIST_MCBCFGQ_CFG_LOG_COUNTS_IN_TRACE, + SKIP_INVALID_ADDR_DIMM_DIS = MCBIST_MCBCFGQ_SKIP_INVALID_ADDR_DIMM_DIS, + REFRESH_ONLY_SUBTEST_EN = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_EN, + REFRESH_ONLY_SUBTEST_TIMEBASE_SEL = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL, + REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN = MCBIST_MCBCFGQ_REFRESH_ONLY_SUBTEST_TIMEBASE_SEL_LEN, + RAND_ADDR_ALL_ADDR_MODE_EN = MCBIST_MCBCFGQ_RAND_ADDR_ALL_ADDR_MODE_EN, + MCBIST_CFG_REF_WAIT_TIME = MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME, + MCBIST_CFG_REF_WAIT_TIME_LEN = MCBIST_MCBCFGQ_MCBIST_CFG_REF_WAIT_TIME_LEN, + CFG_MCB_LEN64 = MCBIST_MCBCFGQ_CFG_MCB_LEN64, + CFG_PAUSE_ON_ERROR_MODE = MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE, + CFG_PAUSE_ON_ERROR_MODE_LEN = MCBIST_MCBCFGQ_CFG_PAUSE_ON_ERROR_MODE_LEN, + MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST = MCBIST_MCBCFGQ_MCBIST_CFG_PAUSE_AFTER_CCS_SUBTEST, + MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR = MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR, + MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST = MCBIST_MCBCFGQ_MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST, + CFG_ENABLE_SPEC_ATTN = MCBIST_MCBCFGQ_CFG_ENABLE_SPEC_ATTN, + CFG_ENABLE_HOST_ATTN = MCBIST_MCBCFGQ_CFG_ENABLE_HOST_ATTN, + MCBIST_CFG_PAUSE_AFTER_RANK = MCBIST_MCBCFGQ_CFG_MCBIST_CFG_FORCE_PAUSE_AFTER_RANK, + + LOGGED_ERROR_ON_PORT_INDICATOR = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR, + LOGGED_ERROR_ON_PORT_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_LOGGED_ERROR_ON_PORT_INDICATOR_LEN, + SUBTEST_NUM_INDICATOR = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR, + SUBTEST_NUM_INDICATOR_LEN = MCBIST_MCBSTATQ_MCBIST_SUBTEST_NUM_INDICATOR_LEN, + + UE_COUNT = MCBIST_MBSEC1Q_UE_COUNT, + UE_COUNT_LEN = MCBIST_MBSEC1Q_UE_COUNT_LEN, + + MBSTRQ_CFG_MAINT_RCE_WITH_CE = MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE, + + CFG_AMAP_DIMM_SELECT = MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT, + CFG_AMAP_DIMM_SELECT_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_DIMM_SELECT_LEN, + CFG_AMAP_MRANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0, + CFG_AMAP_MRANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK0_LEN, + CFG_AMAP_MRANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1, + CFG_AMAP_MRANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_MRANK1_LEN, + CFG_AMAP_SRANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0, + CFG_AMAP_SRANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK0_LEN, + CFG_AMAP_SRANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1, + CFG_AMAP_SRANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK1_LEN, + CFG_AMAP_SRANK2 = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2, + CFG_AMAP_SRANK2_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_SRANK2_LEN, + CFG_AMAP_BANK2 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2, + CFG_AMAP_BANK2_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK2_LEN , + CFG_AMAP_BANK1 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1, + CFG_AMAP_BANK1_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK1_LEN , + CFG_AMAP_BANK0 = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0, + CFG_AMAP_BANK0_LEN = MCBIST_MCBAMR0A0Q_CFG_AMAP_BANK0_LEN , + + CFG_AMAP_BANK_GROUP1 = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1, + CFG_AMAP_BANK_GROUP1_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP1_LEN , + CFG_AMAP_BANK_GROUP0 = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0, + CFG_AMAP_BANK_GROUP0_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_BANK_GROUP0_LEN , + CFG_AMAP_ROW17 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17, + CFG_AMAP_ROW17_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW17_LEN, + CFG_AMAP_ROW16 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16, + CFG_AMAP_ROW16_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW16_LEN, + CFG_AMAP_ROW15 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15, + CFG_AMAP_ROW15_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW15_LEN, + CFG_AMAP_ROW14 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14, + CFG_AMAP_ROW14_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW14_LEN, + CFG_AMAP_ROW13 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13, + CFG_AMAP_ROW13_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW13_LEN, + CFG_AMAP_ROW12 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12, + CFG_AMAP_ROW12_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW12_LEN, + CFG_AMAP_ROW11 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11, + CFG_AMAP_ROW11_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW11_LEN, + CFG_AMAP_ROW10 = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10, + CFG_AMAP_ROW10_LEN = MCBIST_MCBAMR1A0Q_CFG_AMAP_ROW10_LEN, + + CFG_AMAP_ROW9 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9, + CFG_AMAP_ROW9_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW9_LEN, + CFG_AMAP_ROW8 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8, + CFG_AMAP_ROW8_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW8_LEN, + CFG_AMAP_ROW7 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7, + CFG_AMAP_ROW7_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW7_LEN, + CFG_AMAP_ROW6 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6, + CFG_AMAP_ROW6_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW6_LEN, + CFG_AMAP_ROW5 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5, + CFG_AMAP_ROW5_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW5_LEN, + CFG_AMAP_ROW4 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4, + CFG_AMAP_ROW4_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW4_LEN, + CFG_AMAP_ROW3 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3, + CFG_AMAP_ROW3_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW3_LEN, + CFG_AMAP_ROW2 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2, + CFG_AMAP_ROW2_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW2_LEN, + CFG_AMAP_ROW1 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1, + CFG_AMAP_ROW1_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW1_LEN, + CFG_AMAP_ROW0 = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0, + CFG_AMAP_ROW0_LEN = MCBIST_MCBAMR2A0Q_CFG_AMAP_ROW0_LEN, + + CFG_AMAP_COL9 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9, + CFG_AMAP_COL9_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL9_LEN, + CFG_AMAP_COL8 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8, + CFG_AMAP_COL8_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL8_LEN, + CFG_AMAP_COL7 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7, + CFG_AMAP_COL7_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL7_LEN, + CFG_AMAP_COL6 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6, + CFG_AMAP_COL6_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL6_LEN, + CFG_AMAP_COL5 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5, + CFG_AMAP_COL5_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL5_LEN, + CFG_AMAP_COL4 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4, + CFG_AMAP_COL4_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL4_LEN, + CFG_AMAP_COL3 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3, + CFG_AMAP_COL3_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL3_LEN, + CFG_AMAP_COL2 = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2, + CFG_AMAP_COL2_LEN = MCBIST_MCBAMR3A0Q_CFG_AMAP_COL2_LEN, + + LFSR_MASK = MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0, + LFSR_MASK_LEN = MCBIST_MCBLFSRA0Q_CFG_LFSR_MASK_A0_LEN, + + CFG_DATA_ROT_SEED1 = MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED, + CFG_DATA_ROT_SEED1_LEN = MCBIST_MCBDRSRQ_CFG_DATA_ROT_SEED_LEN, + CFG_DATA_ROT = MCBIST_MCBDRCRQ_CFG_DATA_ROT, + CFG_DATA_ROT_LEN = MCBIST_MCBDRCRQ_CFG_DATA_ROT_LEN, + CFG_DATA_ROT_SEED2 = MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED, + CFG_DATA_ROT_SEED2_LEN = MCBIST_MCBDRCRQ_CFG_DATA_ROT_SEED_LEN, + CFG_DATA_SEED_MODE = MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE, + CFG_DATA_SEED_MODE_LEN = MCBIST_MCBDRCRQ_CFG_DATA_SEED_MODE_LEN, + + CFG_TRAP_CE_ENABLE = MCA_MCBCM_MCBIST_TRAP_CE_ENABLE, + CFG_TRAP_UE_ENABLE = MCA_MCBCM_MCBIST_TRAP_UE_ENABLE, + CFG_TRAP_MPE_ENABLE = MCA_MCBCM_MCBIST_TRAP_MPE_ENABLE, + + CFG_DGEN_RNDD_SEED0 = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0, + CFG_DGEN_RNDD_SEED0_LEN = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED0_LEN, + CFG_DGEN_RNDD_SEED1 = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1, + CFG_DGEN_RNDD_SEED1_LEN = MCBIST_MCBRDS0Q_DGEN_RNDD_SEED1_LEN, + CFG_DGEN_RNDD_SEED2 = MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2, + CFG_DGEN_RNDD_SEED2_LEN = MCBIST_MCBRDS1Q_DGEN_RNDD_SEED2_LEN, + CFG_DGEN_RNDD_DATA_MAPPING = MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING, + CFG_DGEN_RNDD_DATA_MAPPING_LEN = MCBIST_MCBRDS1Q_DGEN_RNDD_DATA_MAPPING_LEN, + + // THRESHOLD control bits + MBSTRQ_CFG_THRESH_MAG_NCE_INT = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT, + MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN, + MBSTRQ_CFG_THRESH_MAG_NCE_SOFT = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT, + MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN, + MBSTRQ_CFG_THRESH_MAG_NCE_HARD = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD, + MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN, + MBSTRQ_CFG_THRESH_MAG_RCE = MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE, + MBSTRQ_CFG_THRESH_MAG_RCE_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN, + MBSTRQ_CFG_THRESH_MAG_ICE = MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE, + MBSTRQ_CFG_THRESH_MAG_ICE_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_INT = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT, + MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_SOFT = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT, + MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN, + MBSTRQ_CFG_THRESH_MAG_MCE_HARD = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD, + MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN = MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN, + MBSTRQ_CFG_PAUSE_ON_SCE = MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE, + MBSTRQ_CFG_PAUSE_ON_MCE = MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE, + MBSTRQ_CFG_PAUSE_ON_UE = MCBIST_MBSTRQ_CFG_PAUSE_ON_UE, + MBSTRQ_CFG_PAUSE_ON_SUE = MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE, + MBSTRQ_CFG_PAUSE_ON_AUE = MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE, + MBSTRQ_CFG_PAUSE_ON_RCD = MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD, + MBSTRQ_CFG_SYMBOL_COUNTER_MODE = MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE, + MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN = MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN, + MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_PAUSE_MCB_ERROR = MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR, + MBSTRQ_CFG_PAUSE_MCB_LOG_FULL = MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL, + MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE, + MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE = MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE, + + // Bit mapping for MCBIST error log control data (address+ in Nimbus doc) + ERROR_LOG_SUBTEST = 0, + ERROR_LOG_SUBTEST_LEN = 5, + ERROR_LOG_SUBCMD = 5, + ERROR_LOG_SUBCMD_LEN = 2, + ERROR_LOG_ADDR_DIMM = 7, + ERROR_LOG_ADDR_MRANK = 8, + ERROR_LOG_ADDR_MRANK_LEN = 2, + ERROR_LOG_ADDR_SRANK = 10, + ERROR_LOG_ADDR_SRANK_LEN = 3, + ERROR_LOG_ADDR_BANK_GROUP = 13, + ERROR_LOG_ADDR_BANK_GROUP_LEN = 2, + ERROR_LOG_ADDR_BANK = 15, + ERROR_LOG_ADDR_BANK_LEN = 3, + ERROR_LOG_ADDR_ROW = 18, + ERROR_LOG_ADDR_ROW_LEN = 18, + ERROR_LOG_ADDR_COLUMN = 36, + ERROR_LOG_ADDR_COLUMN_LEN = 8, + ERROR_LOG_BEAT = 44, + ERROR_LOG_BEAT_LEN = 2, + ERROR_LOG_TYPE = 46, + ERROR_LOG_TYPE_LEN = 2, + + //MCBIST FIR mask + MCB_PROGRAM_COMPLETE = MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE, + MCB_WAT_DEBUG_ATTN = MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN, + MCB_PROGRAM_COMPLETE_MASK = MCB_PROGRAM_COMPLETE, + MCB_WAT_DEBUG_ATTN_MASK = MCB_WAT_DEBUG_ATTN, + MCB_DATA_ERROR = MCBIST_MCBISTFIRQ_MCBIST_DATA_ERROR, + + //XLT address valid offset + XLT0_SLOT1_D_VALID = MCS_PORT13_MCP0XLT0_SLOT1_VALID, + XLT0_SLOT0_M1_VALID = MCS_PORT13_MCP0XLT0_SLOT0_M1_VALID, + XLT0_SLOT0_M0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_M0_VALID, + XLT0_SLOT0_S2_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S2_VALID, + XLT0_SLOT0_S1_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S1_VALID, + XLT0_SLOT0_S0_VALID = MCS_PORT13_MCP0XLT0_SLOT0_S0_VALID, + XLT0_SLOT0_ROW17_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW17_VALID, + XLT0_SLOT0_ROW16_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW16_VALID, + XLT0_SLOT0_ROW15_VALID = MCS_PORT02_MCP0XLT0_SLOT0_ROW15_VALID, + + }; + + +}; + + +/// +/// @class mcbistTraits +/// @brief a collection of traits associated with the Nimbus MCA +/// +template<> +class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCA> +{ + public: + // MCBIST error log related registers + static constexpr uint64_t ERROR_LOG_PTR_REG = MCA_ELPR; + static constexpr uint64_t RMW_WRT_BUF_CTL_REG = MCA_WREITE_AACR; + static constexpr uint64_t RMW_WRT_BUF_DATA_REG = MCA_AADR; + static constexpr uint64_t RMW_WRT_BUF_ECC_REG = MCA_AAER; + + // XLT registers + static constexpr uint64_t XLTATE0 = MCA_MBA_MCP0XLT0; + static constexpr uint64_t XLTATE1 = MCA_MBA_MCP0XLT1; + static constexpr uint64_t XLTATE2 = MCA_MBA_MCP0XLT2; + + // Maintenance data location within the array + static constexpr uint64_t MAINT_DATA_INDEX_START = 0b111110000; + static constexpr uint64_t MAINT_DATA_INDEX_END = 0b111111000; + + enum + { + // Register field constants + ERROR_LOG_PTR = MCA_ELPR_LOG_POINTER, + ERROR_LOG_PTR_LEN = MCA_ELPR_LOG_POINTER_LEN, + ERROR_LOG_FULL = MCA_ELPR_LOG_FULL, + RMW_WRT_BUFFER_SEL = MCA_WREITE_AACR_BUFFER, + RMW_WRT_ADDRESS = MCA_WREITE_AACR_ADDRESS, + RMW_WRT_ADDRESS_LEN = MCA_WREITE_AACR_ADDRESS_LEN, + RMW_WRT_AUTOINC = MCA_WREITE_AACR_AUTOINC, + RMW_WRT_ECCGEN = MCA_WREITE_AACR_ECCGEN, + + XLTATE_SLOT0_VALID = MCS_PORT02_MCP0XLT0_SLOT0_VALID, + XLTATE_SLOT1_VALID = MCS_PORT02_MCP0XLT0_SLOT1_VALID, + + // Constants used for field settings + SELECT_RMW_BUFFER = 0, + SELECT_WRT_BUFFER = 1, + + // Other constants + NUM_COMPARE_LOG_ENTRIES = 64, + // In compare mode, there is one "info" entry per 4 data (log) entries + // so compare mode only uses 16 info entries total in the rmw array + NUM_COMPARE_DATA_PER_INFO_LOG = 4, + NUM_COMPARE_INFO_ENTRIES = 16, + }; + +}; + + +/// +/// @class mcbistTraits +/// @brief a collection of traits associated with the Nimbus MCS +/// +template<> +class mcbistTraits<mss::mc_type::NIMBUS, fapi2::TARGET_TYPE_MCS> +{ + public: + // MCBIST error log related registers + static constexpr uint64_t RD_BUF_CTL_REG = MCS_PORT02_AACR; + static constexpr uint64_t RD_BUF_DATA_REG = MCS_PORT02_AADR; + static constexpr uint64_t RD_BUF_ECC_REG = MCS_PORT02_AAER; + + enum + { + // Register field constants + RB_BUFFER_SEL = MCS_PORT02_AACR_BUFFER, + RB_ADDRESS = MCS_PORT02_AACR_ADDRESS, + RB_ADDRESS_LEN = MCS_PORT02_AACR_ADDRESS_LEN, + RB_AUTOINC = MCS_PORT02_AACR_AUTOINC, + + // Other constants + NUM_COMPARE_LOG_ENTRIES = 64, + }; + +}; + + +} // namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C index b235637b5..1d4a4940c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ +/* Contributors Listed Below - COPYRIGHT 2016,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,26 +33,16 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> -#include <generic/memory/lib/utils/find_magic.H> #include <lib/mcbist/memdiags.H> #include <lib/mcbist/mcbist.H> -#include <lib/mcbist/address.H> -#include <lib/mcbist/settings.H> -#include <lib/mcbist/sim.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/poll.H> -using fapi2::TARGET_TYPE_MCBIST; -using fapi2::TARGET_TYPE_MCA; -using fapi2::TARGET_TYPE_DIMM; -using fapi2::TARGET_TYPE_SYSTEM; -using fapi2::FAPI2_RC_SUCCESS; -using fapi2::FAPI2_RC_INVALID_PARAMETER; namespace mss { @@ -61,153 +51,28 @@ namespace memdiags { /// -/// @brief Stop the current command -/// @param[in] i_target the target +/// @brief Set up memory controller specific settings for pre-maint mode read +/// @param[in] i_target the memory controller target /// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::NIMBUS specialization /// template<> -fapi2::ReturnCode stop( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) -{ - // Too long, make shorter - using TT = mss::mcbistTraits<TARGET_TYPE_MCBIST>; - - // Poll parameters are defined as TK so that we wait a nice time for operations - // For now use the defaults - mss::poll_parameters l_poll_parameters; - fapi2::buffer<uint64_t> l_status; - fapi2::buffer<uint64_t> l_last_address; - bool l_poll_result = false; - - FAPI_INF("Stopping any mcbist operations which are in progress for %s", mss::c_str(i_target)); - - // TODO RTC:153951 Add masking of FIR when stopping - FAPI_TRY( mss::mcbist::start_stop(i_target, mss::STOP) ); - - // Poll waiting for the engine to stop - l_poll_result = mss::poll(i_target, TT::STATQ_REG, l_poll_parameters, - [&l_status](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_DBG("looking for mcbist not in-progress, mcbist statq 0x%llx, remaining: %d", stat_reg, poll_remaining); - l_status = stat_reg; - // We're done polling when either we see we're in progress or we see we're done. - return l_status.getBit<TT::MCBIST_IN_PROGRESS>() == false; - }); - - // Pass or fail output the current address. This is useful for debugging when we can get it. - // It's in the register FFDC for memdiags so we don't need it below - FAPI_TRY( mss::getScom(i_target, TT::LAST_ADDR_REG, l_last_address) ); - FAPI_INF("MCBIST last address (during stop): 0x%016lx for %s", - l_last_address, mss::c_str(i_target)); - - // So we've either stopped or we timed out - FAPI_ASSERT( l_poll_result == true, - fapi2::MSS_MEMDIAGS_MCBIST_FAILED_TO_STOP() - .set_MCBIST_TARGET(i_target) - .set_POLL_COUNT(l_poll_parameters.iv_poll_count), - "%s The MCBIST engine failed to stop its program", - mss::c_str(i_target) ); - -fapi_try_exit: - return fapi2::current_err; - -} - -/// -/// @brief memdiags init helper -/// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes -/// in subclassed constructors more easily. -/// @return FAPI2_RC_SUCCESS iff everything ok -/// -template<> -fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::base_init() +fapi2::ReturnCode pre_maint_read_settings<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& + i_target ) { - FAPI_INF("memdiags base init for %s", mss::c_str(iv_target)); - - // Check the state of the MCBIST engine to make sure its OK that we proceed. - // Force stop the engine (per spec, as opposed to waiting our turn) - FAPI_TRY( memdiags::stop(iv_target) ); - - // Zero out cmd timebase - mcbist::program constructor does that for us. - // Load pattern - FAPI_TRY( iv_program.change_pattern(iv_const.iv_pattern) ); - - // Load end boundaries - iv_program.change_end_boundary(iv_const.iv_end_boundary); - - // Load thresholds - iv_program.change_thresholds(iv_const.iv_stop); - - // Setup the requested speed - FAPI_TRY( iv_program.change_speed(iv_target, iv_const.iv_speed) ); - - // Enable maint addressing mode - enabled by default in the mcbist::program ctor - - // Apparently the MCBIST engine needs the ports selected even though the ports are specified - // in the subtest. We can just select them all, and it adjusts when it executes the subtest - iv_program.select_ports(0b1111); - - // Kick it off, don't wait for a result - iv_program.change_async(mss::ON); - -fapi_try_exit: - return fapi2::current_err; + return fapi2::FAPI2_RC_SUCCESS; } /// -/// @brief Single port initializer -/// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes -/// in subclassed constructors more easily. -/// @return FAPI2_RC_SUCCESS iff everything ok +/// @brief Set up memory controller specific settings for pre-scrub +/// @param[in] i_target the memory controller target +/// @return FAPI2_RC_SUCCESS iff ok +/// @note mc_type::NIMBUS specialization /// template<> -fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::single_port_init() +fapi2::ReturnCode pre_scrub_settings<mss::mc_type::NIMBUS>( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) { - FAPI_INF("single port init for %s", mss::c_str(iv_target)); - - const uint64_t l_relative_port_number = iv_const.iv_start_address.get_port(); - const uint64_t l_dimm_number = iv_const.iv_start_address.get_dimm(); - - // Make sure the specificed port is functional - FAPI_ASSERT( mss::is_functional<TARGET_TYPE_MCA>(iv_target, l_relative_port_number), - fapi2::MSS_MEMDIAGS_PORT_NOT_FUNCTIONAL() - .set_RELATIVE_PORT_POSITION(l_relative_port_number) - .set_ADDRESS( uint64_t(iv_const.iv_start_address) ) - .set_MCBIST_TARGET(iv_target), - "Port with relative postion %d is not functional for %s", - l_relative_port_number, mss::c_str(iv_target)); - - // No broadcast mode for this one - // Push on a read subtest - { - mss::mcbist::subtest_t<TARGET_TYPE_MCBIST> l_subtest = iv_subtest; - - l_subtest.enable_port(l_relative_port_number); - l_subtest.enable_dimm(l_dimm_number); - iv_program.iv_subtests.push_back(l_subtest); - FAPI_INF("%s adding subtest 0x%04x for port %d, DIMM %d", - mss::c_str(iv_target), l_subtest, l_relative_port_number, l_dimm_number); - } - - // The address should have the port and DIMM noted in it. All we need to do is calculate the - // remainder of the address - if (iv_sim) - { - iv_const.iv_start_address.get_sim_end_address(iv_const.iv_end_address); - } - else if (iv_const.iv_end_address == mss::mcbist::address::LARGEST_ADDRESS) - { - // Only the DIMM range as we don't want to cross ports. - iv_const.iv_start_address.get_range<mss::mcbist::address::DIMM>(iv_const.iv_end_address); - } - - // Configure the address range - FAPI_TRY( mss::mcbist::config_address_range0(iv_target, iv_const.iv_start_address, iv_const.iv_end_address) ); - - // Initialize the common sections - FAPI_TRY( base_init() ); - -fapi_try_exit: - return fapi2::current_err; + return fapi2::FAPI2_RC_SUCCESS; } /// @@ -215,10 +80,12 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template<> -fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::multi_port_addr() +fapi2::ReturnCode operation<DEFAULT_MC_TYPE>::multi_port_addr() { + using TT = mcbistTraits<>; + mss::mcbist::address l_end_of_start_port; - mss::mcbist::address l_end_of_complete_port(mss::mcbist::address::LARGEST_ADDRESS); + mss::mcbist::address l_end_of_complete_port(TT::LARGEST_ADDRESS); mss::mcbist::address l_start_of_end_port; // The last address in the start port is the start address thru the "DIMM range" (all addresses left on this DIMM) @@ -255,8 +122,8 @@ fapi_try_exit: /// @param[in] i_dimms a vector of DIMM targets /// template<> -void operation<TARGET_TYPE_MCBIST>::configure_multiport_subtests(const - std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimms) +void operation<DEFAULT_MC_TYPE>::configure_multiport_subtests( + const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimms) { // Constexpr's to beautify the code constexpr uint64_t FIRST_ADDRESS = 0; @@ -424,37 +291,21 @@ fapi_try_exit: } /// -/// @brief memdiags multi-port init helper +/// @brief memdiags multi-port init /// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes /// in subclassed constructors more easily. /// @return FAPI2_RC_SUCCESS iff everything ok /// template<> -fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::multi_port_init() +fapi2::ReturnCode operation<DEFAULT_MC_TYPE>::multi_port_init_internal() { - FAPI_INF("multi-port init for %s", mss::c_str(iv_target)); - - const auto l_mcas = mss::find_targets<fapi2::TARGET_TYPE_MCA>(iv_target); + FAPI_INF("multi-port init internal for %s", mss::c_str(iv_target)); - // Make sure we have ports, if we don't then exit out - if(l_mcas.size() == 0) - { - // Cronus can have no ports under an MCBIST, FW deconfigures by association - FAPI_INF("%s has no attached MCAs skipping setup", mss::c_str(iv_target)); - return fapi2::FAPI2_RC_SUCCESS; - } // Let's assume we are going to send out all subtest unless we are in broadcast mode, // where we only send up to 2 subtests under an MCA ( 1 for each DIMM) which is why no const auto l_dimms = mss::find_targets<fapi2::TARGET_TYPE_DIMM>(iv_target); - if( l_dimms.size() == 0) - { - // Cronus can have no DIMMS under an MCBIST, FW deconfigures by association - FAPI_INF("%s has no attached DIMMs skipping setup", mss::c_str(iv_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - // Get the port/DIMM information for the addresses. This is an integral value which allows us to index // all the DIMM across a controller. const uint64_t l_portdimm_start_address = iv_const.iv_start_address.get_port_dimm(); @@ -478,7 +329,7 @@ fapi2::ReturnCode operation<TARGET_TYPE_MCBIST>::multi_port_init() "Start address %d larger than end address %d for %s", l_portdimm_start_address, l_portdimm_end_address, mss::c_str(iv_target)); - // Determine which ports are functional and whether we can broadcast to them +// Determine which ports are functional and whether we can broadcast to them // If we're in broadcast mode, PRD sends DIMM 0/1 of the first functional and configured port, // and we then run all ports in parallel (ports set in subtest config) if( mss::mcbist::is_broadcast_capable(iv_target) == mss::YES ) @@ -532,407 +383,7 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief memdiags::continuous_scrub_operation constructor -/// @param[in] i_target the target of the mcbist engine -/// @param[in] i_const the contraints of the operation -/// @param[out] o_rc the fapi2::ReturnCode of the intialization process -/// -template<> -continuous_scrub_operation<TARGET_TYPE_MCBIST>::continuous_scrub_operation( - const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc ): - operation<TARGET_TYPE_MCBIST>(i_target, mss::mcbist::scrub_subtest<TARGET_TYPE_MCBIST>(), i_const) -{ - mss::mcbist::address l_generic_start_address; - mss::mcbist::address l_generic_end_address; - - FAPI_INF("setting up for continuous scrub for %s", mss::c_str(i_target)); - - // Scrub operations run 128B - iv_program.change_len64(mss::OFF); - - // We build a little program here which allows us to restart the loop in the event of a pause. - // So we need to craft some of the address ranges and some of the subtests by hand. - - // Setup address config 0 to cover all the addresses for a port/dimm. - // We leverage the MCBIST's ability to skip invalid addresses, and just setup - // If we're running in the simulator, we want to only touch the addresses which training touched - // *INDENT-OFF* - iv_sim ? - l_generic_start_address.get_sim_end_address(l_generic_end_address) : - l_generic_start_address.get_range<mss::mcbist::address::DIMM>(l_generic_end_address); - // *INDENT-ON* - - FAPI_TRY( mss::mcbist::config_address_range0(i_target, l_generic_start_address, l_generic_end_address) ); - - // We push on a fake subtest 0 and subtest 1. We fix them up after we fill in the - // rest of the subtests. - iv_program.iv_subtests.push_back(iv_subtest); - iv_program.iv_subtests.push_back(iv_subtest); - - // a generic 0 - DIMM address range. - // - // Subtests 2-9: One subtest per port/dimm each covering the whole range of that - // port/dimm. scrub_subtests by default are using address config 0, so each of - // these get their full address complement. - for (const auto& p : iv_target.template getChildren<TARGET_TYPE_MCA>()) - { - for (const auto& d : p.template getChildren<TARGET_TYPE_DIMM>()) - { - // Don't destroy the subtest passed in, copy it - auto l_subtest = iv_subtest; - - l_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); - l_subtest.enable_dimm(mss::index(d)); - iv_program.iv_subtests.push_back(l_subtest); - FAPI_INF("adding scrub subtest for %s (dimm %d) ( 0x%04x)", mss::c_str(d), mss::index(d), l_subtest); - } - } - - // - // Subtest 10: goto subtest 2. This causes us to loop back to the first port/dimm and go thru them all - // This subtest will be marked the last when the MCBMR registers are filled in. - // - iv_program.iv_subtests.push_back(mss::mcbist::goto_subtest<TARGET_TYPE_MCBIST>(2)); - FAPI_INF("last goto subtest (10) is going to subtest 2 ( 0x%04x) for %s", iv_program.iv_subtests[2], - mss::c_str(iv_target)); - - // Ok, now we can go back in to fill in the first two subtests. - - { - auto l_subtest = iv_subtest; - auto l_port = iv_const.iv_start_address.get_port(); - auto l_dimm = iv_const.iv_start_address.get_dimm(); - size_t l_index = 2; - - // By default if we don't find our port/dimm in the subtests, we just go back to the beginning. - uint64_t l_goto_subtest = 2; - - // - // subtest 0 - // - - // load the start address given and calculate the end address. Stick this into address config 1 - // We don't need to account for the simulator here as the caller can do that when they setup the - // start address. - // *INDENT-OFF* - iv_sim ? - iv_const.iv_start_address.get_sim_end_address(iv_const.iv_end_address) : - iv_const.iv_start_address.get_range<mss::mcbist::address::DIMM>(iv_const.iv_end_address); - // *INDENT-ON* - - FAPI_TRY( mss::mcbist::config_address_range1(i_target, iv_const.iv_start_address, iv_const.iv_end_address) ); - - // We need to use this address range. We know it's ok to write to element 0 as we pushed it on above - l_subtest.change_addr_sel(1); - l_subtest.enable_port(l_port); - l_subtest.enable_dimm(l_dimm); - - iv_program.iv_subtests[0] = l_subtest; - FAPI_INF("adding scrub subtest 0 for port %d dimm %d (0x%04x) for %s", l_port, l_dimm, l_subtest, mss::c_str(i_target)); - - // - // subtest 1 - // - - // From the port/dimm specified in the start address, we know what subtest should execute next. The idea - // being that this 0'th subtest is a mechanism to allow the caller to start a scrub 'in the middle' and - // jump to the next port/dimm which would have been scrubbed. The hard part is that we don't know where - // in the subtest vector the 'next' port/dimm are placed. So we look for our port/dimm (skipping subtest 0 - // since we know that's us and skipping subtest 1 since it isn't there yet.) - for (; l_index < iv_program.iv_subtests.size(); ++l_index) - { - auto l_my_dimm = iv_program.iv_subtests[l_index].get_dimm(); - auto l_my_port = iv_program.iv_subtests[l_index].get_port(); - - if ((l_dimm == l_my_dimm) && (l_port == l_my_port)) - { - l_goto_subtest = l_index + 1; - break; - } - } - - // Since we set l_goto_subtest up with a meaningful default, we can just make a subtest with the - // l_goto_subtest subtest specified and pop that in to index 1. - FAPI_INF("adding scrub subtest 1 to goto subtest %d (port %d, dimm %d, test 0x%04x) for %s", l_goto_subtest, - iv_program.iv_subtests[l_goto_subtest].get_port(), - iv_program.iv_subtests[l_goto_subtest].get_dimm(), - iv_program.iv_subtests[l_goto_subtest], mss::c_str(i_target) ); - - iv_program.iv_subtests[1] = mss::mcbist::goto_subtest<TARGET_TYPE_MCBIST>(l_goto_subtest); - } - - // Initialize the common sections - FAPI_TRY( base_init() ); - -fapi_try_exit: - o_rc = fapi2::current_err; - return; -} - -/// -/// @brief Super Fast Read Init - used to init all memory behind a target with a given pattern -/// @note Uses broadcast mode if possible -/// @param[in] i_target the target behind which all memory should be initialized -/// @param[in] i_pattern an index representing a pattern to use to initize memory (defaults to 0) -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// -template<> -fapi2::ReturnCode sf_init( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const uint64_t i_pattern ) -{ - FAPI_INF("superfast init start for %s", mss::c_str(i_target)); - - uint8_t l_sim = false; - FAPI_TRY( mss::is_simulation( l_sim) ); - - if (l_sim) - { - // Use some sort of pattern in sim in case the verification folks need to look for something - // TK. Need a verification pattern. This is a not-good pattern for verification ... We don't really - // have a good pattern for verification defined. - FAPI_INF("running mss sim init in place of sf_init for %s", mss::c_str(i_target)); - return mss::mcbist::sim::sf_init(i_target, i_pattern); - } - else - { - fapi2::ReturnCode l_rc; - constraints l_const(i_pattern); - sf_init_operation<TARGET_TYPE_MCBIST> l_init_op(i_target, l_const, l_rc); - - FAPI_ASSERT( l_rc == FAPI2_RC_SUCCESS, - fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), - "Unable to initialize the MCBIST engine for a sf read %s", mss::c_str(i_target) ); - - return l_init_op.execute(); - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Super Fast Read to End of MCBIST - used to run superfast read on all memory behind the target -/// @tparam T the fapi2::TargetType of the target -/// @param[in] i_target the target behind which all memory should be read -/// @param[in] i_stop stop conditions -/// @param[in] i_address mcbist::address representing the address from which to start. -// Defaults to the first address behind the target -/// @param[in] i_end whether to end, and where -/// Defaults to stop after slave rank -/// @param[in] i_end_address mcbist::address representing the address to end. -// Defaults to mcbist::address::LARGEST_ADDRESS -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// @note The address is often the port, dimm, rank but this is not enforced in the API. -/// -template<> -fapi2::ReturnCode sf_read( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const stop_conditions& i_stop, - const mss::mcbist::address& i_address, - const end_boundary i_end, - const mss::mcbist::address& i_end_address ) -{ - FAPI_INF("superfast read - start for %s", mss::c_str(i_target)); - - fapi2::ReturnCode l_rc; - constraints l_const(i_stop, speed::LUDICROUS, i_end, i_address, i_end_address); - sf_read_operation<TARGET_TYPE_MCBIST> l_read_op(i_target, l_const, l_rc); - - FAPI_ASSERT( l_rc == FAPI2_RC_SUCCESS, - fapi2::MSS_MEMDIAGS_SUPERFAST_READ_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), - "Unable to initialize the MCBIST engine for a sf read %s", mss::c_str(i_target) ); - - return l_read_op.execute(); - -fapi_try_exit: - return fapi2::current_err; -} -/// -/// @brief Scrub - continuous scrub all memory behind the target -/// @param[in] i_target the target behind which all memory should be scrubbed -/// @param[in] i_stop stop conditions -/// @param[in] i_speed the speed to scrub -/// @param[in] i_address mcbist::address representing the port, dimm, rank -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @warning The function is asynchronous, and the caller should be looking for a done attention -/// @note The operation will fail immediately when a stop condition is encountered -/// -template<> -fapi2::ReturnCode background_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const stop_conditions& i_stop, - const speed i_speed, - const mss::mcbist::address& i_address ) -{ - FAPI_INF("continuous (background) scrub for %s", mss::c_str(i_target)); - - fapi2::ReturnCode l_rc; - constraints l_const(i_stop, i_speed, end_boundary::STOP_AFTER_ADDRESS, i_address); - continuous_scrub_operation<TARGET_TYPE_MCBIST> l_op(i_target, l_const, l_rc); +} // namespace memdiags - FAPI_ASSERT( l_rc == FAPI2_RC_SUCCESS, - fapi2::MSS_MEMDIAGS_CONTINUOUS_SCRUB_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), - "Unable to initialize the MCBIST engine for a continuous scrub %s", mss::c_str(i_target) ); - - return l_op.execute(); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Scrub - targeted scrub all memory behind the target -/// @param[in] i_target the target behind which all memory should be scrubbed -/// @param[in] i_stop stop conditions -/// @param[in] i_start_address mcbist::address representing the address from which to start. -/// @param[in] i_end_address mcbist::address representing the address at which to end. -/// @param[in] i_end whether to end, and where (defaults to not stop on error) -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// @note The caller can use the address range functions to calculate the end address as needed -/// -template<> -fapi2::ReturnCode targeted_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const stop_conditions& i_stop, - const mss::mcbist::address& i_start_address, - const mss::mcbist::address& i_end_address, - const end_boundary i_end ) -{ - FAPI_INF("targeted scrub for %s", mss::c_str(i_target)); - - fapi2::ReturnCode l_rc; - constraints l_const(i_stop, speed::LUDICROUS, i_end, i_start_address, i_end_address); - targeted_scrub_operation<TARGET_TYPE_MCBIST> l_op(i_target, l_const, l_rc); - - FAPI_ASSERT( l_rc == FAPI2_RC_SUCCESS, - fapi2::MSS_MEMDIAGS_TARGETED_SCRUB_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), - "Unable to initialize the MCBIST engine for a targeted scrub %s", mss::c_str(i_target) ); - - return l_op.execute(); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Continue current command on next address -/// The current commaand has paused on an error, so we can record the address of the error -/// and finish the current master or slave rank. -/// @param[in] i_target the target -/// @param[in] i_end whether to end, and where (default = don't stop at end of rank) -/// @param[in] i_stop stop conditions (default - 0 meaning 'don't change conditions') -/// @param[in] i_speed the speed to scrub (default - SAME_SPEED meaning leave speed untouched) -/// @return FAPI2_RC_SUCCESS iff ok -/// @note overloaded as there's no 'invalid' state for thresholds. -/// -template<> -fapi2::ReturnCode continue_cmd( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const end_boundary i_end, - const stop_conditions& i_stop, - const speed i_speed ) -{ - // Too long, make shorter - using TT = mss::mcbistTraits<TARGET_TYPE_MCBIST>; - - // We can use a local mcbist::program to help with the bit processing, and then write just the registers we touch. - mss::mcbist::program<TARGET_TYPE_MCBIST> l_program; - fapi2::buffer<uint64_t> l_status; - - FAPI_INF("continue_cmd for %s", mss::c_str(i_target)); - - // TODO RTC:155518 Check for stop or in progress before allowing continue. Not critical - // as the caller should know and can check the in-progress bit in the event they don't - - if (i_end != end_boundary::DONT_CHANGE) - { - // Before we go too far, check to see if we're already stopped at the boundary we are asking to stop at - bool l_stopped_at_boundary = false; - uint64_t l_error_mode = 0; - bool l_detect_slave = false; - - FAPI_TRY( mss::getScom(i_target, TT::CFGQ_REG, l_program.iv_config) ); - FAPI_TRY( mss::getScom(i_target, TT::MCBAGRAQ_REG, l_program.iv_addr_gen) ); - l_program.iv_config.extractToRight<TT::CFG_PAUSE_ON_ERROR_MODE, TT::CFG_PAUSE_ON_ERROR_MODE_LEN>(l_error_mode); - l_detect_slave = l_program.iv_addr_gen.getBit<TT::MAINT_DETECT_SRANK_BOUNDARIES>(); - - switch (i_end) - { - case end_boundary::STOP_AFTER_ADDRESS: - l_stopped_at_boundary = - l_program.iv_config.getBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_ADDR>() || - l_error_mode == end_boundary::STOP_AFTER_ADDRESS; - break; - - case end_boundary::STOP_AFTER_SLAVE_RANK: - // Note: we really want STOP_AFTER_MASTER_RANK here even though we're in the slave - // case because MASTER_RANK has the a 0 so that l_error_mode will check correctly - l_stopped_at_boundary = - l_program.iv_config.getBit<TT::MCBIST_CFG_PAUSE_AFTER_RANK>() || - ((l_error_mode == end_boundary::STOP_AFTER_MASTER_RANK) && (l_detect_slave == false)); - break; - - case end_boundary::STOP_AFTER_MASTER_RANK: - l_stopped_at_boundary = - l_program.iv_config.getBit<TT::MCBIST_CFG_PAUSE_AFTER_RANK>() || - ((l_error_mode == end_boundary::STOP_AFTER_MASTER_RANK) && (l_detect_slave == true)); - break; - - case end_boundary::STOP_AFTER_SUBTEST: - l_stopped_at_boundary = - l_program.iv_config.getBit<TT::MCBIST_CFG_FORCE_PAUSE_AFTER_SUBTEST>() || - l_error_mode == end_boundary::STOP_AFTER_SUBTEST; - break; - - // By default we're not stopped at a boundary we're going to continue from - default: - break; - }; - - FAPI_ASSERT( l_stopped_at_boundary == false, - fapi2::MSS_MEMDIAGS_ALREADY_AT_BOUNDARY().set_MCBIST_TARGET(i_target).set_BOUNDARY(i_stop), - "Asked to stop at a boundary, but we're already there" ); - - // Ok, if we're here either we need to change the stop and boundary conditions. - // Read-modify-write the fields in the program. - FAPI_TRY( mss::getScom(i_target, TT::MCBAGRAQ_REG, l_program.iv_addr_gen) ); - - // Configure broadcast mode if needed - FAPI_TRY(mss::mcbist::configure_broadcast_mode(i_target, l_program)); - - l_program.change_end_boundary(i_end); - - FAPI_TRY( mss::mcbist::load_addr_gen(i_target, l_program) ); - - FAPI_TRY( mss::mcbist::load_config(i_target, l_program) ); - } - - // Thresholds - // According to API definition, 0 means don't change conditions - if( i_stop != stop_conditions::DONT_CHANGE) - { - FAPI_TRY( mss::mcbist::load_thresholds(i_target, i_stop) ); - } - - // Setup speed - FAPI_TRY( l_program.change_speed(i_target, i_speed) ); - - // Load new speed unless we aren't changing it - if( i_speed != speed::SAME_SPEED ) - { - FAPI_TRY( load_mcbparm(i_target, l_program) ); - } - - // Tickle the resume from pause - FAPI_TRY( mss::mcbist::resume(i_target) ); - -fapi_try_exit: - return fapi2::current_err; -} - -} - -} +} // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H index 918342c6c..38ea0a8aa 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/memdiags.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,10 +39,17 @@ #include <fapi2.H> #include <lib/shared/mss_const.H> +#include <lib/shared/mss_const.H> +#include <lib/ecc/ecc_traits_nimbus.H> #include <lib/mcbist/mcbist.H> -#include <lib/mcbist/address.H> -#include <lib/mcbist/patterns.H> -#include <lib/mcbist/settings.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_memdiags.H> + +using fapi2::TARGET_TYPE_MCBIST; +using fapi2::TARGET_TYPE_MCA; +using fapi2::TARGET_TYPE_DIMM; +using fapi2::TARGET_TYPE_SYSTEM; +using fapi2::FAPI2_RC_SUCCESS; +using fapi2::FAPI2_RC_INVALID_PARAMETER; namespace mss { @@ -50,309 +57,10 @@ namespace mss namespace memdiags { -// Map some of the mcbist namespace here to make it easier for users of memdiags -// This is an intentional using statement in a header which is typically -// disallowed - I am intentionally pulling these into this namespace for all callers. -using mss::mcbist::constraints; -using mss::mcbist::speed; -using mss::mcbist::end_boundary; -using mss::mcbist::stop_conditions; -using mss::mcbist::cache_line; -using mss::mcbist::pattern; -using mss::mcbist::patterns; - -// Why not mss::mcbist::address? Because the fields can't be pulled in via using, -// and it seems even more confusing to have a memdiags address but have to use -// mcbist fields. So, we all use mcbist address until such time that its promoted -// to some other general namespace. - -using mss::mcbist::PATTERN_ZEROS; -using mss::mcbist::PATTERN_0; -using mss::mcbist::PATTERN_ONES; -using mss::mcbist::PATTERN_1; -using mss::mcbist::PATTERN_2; -using mss::mcbist::PATTERN_3; -using mss::mcbist::PATTERN_4; -using mss::mcbist::PATTERN_5; -using mss::mcbist::PATTERN_6; -using mss::mcbist::PATTERN_7; -using mss::mcbist::PATTERN_8; -using mss::mcbist::PATTERN_RANDOM; -using mss::mcbist::LAST_PATTERN; -using mss::mcbist::NO_PATTERN; - -/// -/// @brief Stop the current command -/// @tparam T the fapi2::TargetType of the target -/// @param[in] i_target the target -/// @return FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode stop( const fapi2::Target<T>& i_target ); - -/// -/// @class Base class for memdiags operations -/// @tparam T fapi2::TargetType of the MCBIST engine -/// -template< fapi2::TargetType T > -class operation -{ - public: - /// - /// @brief memdiags::operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_subtest the proper subtest for this operation - /// @param[in] i_const mss::constraint structure - /// - operation( const fapi2::Target<T>& i_target, - const mss::mcbist::subtest_t<T> i_subtest, - const constraints i_const ): - iv_target(i_target), - iv_subtest(i_subtest), - iv_const(i_const) - { - FAPI_TRY( mss::is_simulation (iv_sim) ); - return; - - fapi_try_exit: - // Seems like a safe risk to take ... - FAPI_ERR("Unable to get the attribute ATTR_IS_SIMULATION"); - return; - } - - operation() = delete; - - /// - /// @brief Execute the memdiags operation - /// @return FAPI2_RC_SUCCESS iff ok - /// - inline fapi2::ReturnCode execute() - { - return mss::mcbist::execute(iv_target, iv_program); - } - - /// - /// @brief memdiags::operation destructor - /// - virtual ~operation() = default; - - /// - /// @brief memdiags init helper - /// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes - /// in subclassed constructores more easily. - /// @return FAPI2_RC_SUCCESS iff everything ok - /// - fapi2::ReturnCode base_init(); - - /// - /// @brief Configures all subtests for a multiport init - /// @param[in] i_dimms a vector of DIMM targets - /// - void configure_multiport_subtests(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_DIMM>>& i_dimms); - - /// - /// @brief memdiags multi-port init helper - /// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes - /// in subclassed constructores more easily. - /// @return FAPI2_RC_SUCCESS iff everything ok - /// - fapi2::ReturnCode multi_port_init(); - - /// - /// @brief memdiags multi-port address config helper - /// Initializes the address configs needed for a multi port operation - /// @return FAPI2_RC_SUCCESS iff everything ok - /// - fapi2::ReturnCode multi_port_addr(); - - /// - /// @brief Single port initializer - /// Initializes common sections. Broken out rather than the base class ctor to enable checking return codes - /// in subclassed constructores more easily. - /// @return FAPI2_RC_SUCCESS iff everything ok - /// - fapi2::ReturnCode single_port_init(); - - /// - /// @brief get the protected mcbist program - useful for testing - /// @return a reference to the iv_program member - /// @note Intentionally not const ref; allows getter to set. - /// - mss::mcbist::program<T>& get_program() - { - return iv_program; - } - - /// - /// @brief get the protected mcbist subtest_t - useful for testing - /// @return a reference to the iv_subtest member - /// - const mss::mcbist::subtest_t<T>& get_subtest() const - { - return iv_subtest; - } - - protected: - fapi2::Target<T> iv_target; - mss::mcbist::subtest_t<T> iv_subtest; - constraints iv_const; - mss::mcbist::program<T> iv_program; - uint8_t iv_sim; -}; - -/// -/// @class Class for memdiags' super-fast init -/// @tparam T fapi2::TargetType of the MCBIST engine -/// -template< fapi2::TargetType T > -struct sf_init_operation : public operation<T> -{ - - /// - /// @brief memdiags::sf_init_operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_const mss::constraint structure - /// @param[out] o_rc the fapi2::ReturnCode of the intialization process - /// - sf_init_operation( const fapi2::Target<T>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc): - operation<T>(i_target, mss::mcbist::init_subtest<T>(), i_const) - { - // If sf_init was passed the random data pattern, then modify the subtest to use the true random data - if(i_const.iv_pattern == PATTERN_RANDOM) - { - this->iv_subtest.change_data_mode(mss::mcbist::data_mode::RAND_FWD_MAINT); - } - - // We're a multi-port operation - o_rc = this->multi_port_init(); - } - - sf_init_operation() = delete; -}; - -/// -/// @class Class for memdiags' super-fast read -/// @tparam T fapi2::TargetType of the MCBIST engine /// -template< fapi2::TargetType T > -struct sf_read_operation : public operation<T> -{ - - /// - /// @brief memdiags::sf_read_operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_const mss::constraint structure - /// @param[out] o_rc the fapi2::ReturnCode of the intialization process - /// - sf_read_operation( const fapi2::Target<T>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc): - operation<T>(i_target, mss::mcbist::read_subtest<T>(), i_const) - { - // We're a multi-port operation - o_rc = this->multi_port_init(); - } - - sf_read_operation() = delete; -}; - -/// -/// @class Class for memdiags' super-fast read to end of port -/// @tparam T fapi2::TargetType of the MCBIST engine -/// -template< fapi2::TargetType T > -struct sf_read_eop_operation : public operation<T> -{ - /// - /// @brief memdiags::sf_read_operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_const mss::constraint structure - /// @param[out] o_rc the fapi2::ReturnCode of the intialization process - /// - sf_read_eop_operation( const fapi2::Target<T>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc ): - operation<T>(i_target, mss::mcbist::read_subtest<T>(), i_const) - { - // We're a single-port operation - o_rc = this->single_port_init(); - } - - sf_read_eop_operation() = delete; -}; - -/// -/// @class Class for memdiags' continuous scrub -/// @tparam T fapi2::TargetType of the MCBIST engine -/// -template< fapi2::TargetType T > -struct continuous_scrub_operation : public operation<T> -{ - - /// - /// @brief memdiags::continuous_scrub_operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_const the contraints of the operation - /// @param[out] o_rc the fapi2::ReturnCode of the intialization process - /// - continuous_scrub_operation( const fapi2::Target<T>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc ); - - continuous_scrub_operation() = delete; -}; - -/// -/// @class Class for memdiags' targeted scrub -/// @tparam T fapi2::TargetType of the MCBIST engine -/// -template< fapi2::TargetType T > -struct targeted_scrub_operation : public operation<T> -{ - - /// - /// @brief memdiags::targeted_scrub_operation constructor - /// @param[in] i_target the target of the mcbist engine - /// @param[in] i_const the contraints of the operation - /// @param[out] o_rc the fapi2::ReturnCode of the intialization process - /// - targeted_scrub_operation( const fapi2::Target<T>& i_target, - const constraints i_const, - fapi2::ReturnCode& o_rc ): - operation<T>(i_target, mss::mcbist::scrub_subtest<T>(), i_const) - { - // Scrub operations run 128B - this->iv_program.change_len64(mss::OFF); - - // We're a single-port operation - o_rc = this->single_port_init(); - - // Targeted scrub needs to force a pause and the end boundary. So we make sure that happens here. - this->iv_program.change_forced_pause( i_const.iv_end_boundary ); - } - - targeted_scrub_operation() = delete; -}; - -/// -/// @brief Super Fast Init - used to init all memory behind a target with a given pattern -/// @note Uses broadcast mode if possible -/// @tparam T the fapi2::TargetType of the target -/// @param[in] i_target the target behind which all memory should be initialized -/// @param[in] i_pattern an index representing a pattern to use to init memory (defaults to 0) -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// -template< fapi2::TargetType T > -fapi2::ReturnCode sf_init( const fapi2::Target<T>& i_target, - const uint64_t i_pattern = PATTERN_0 ); - -/// -/// @brief Start address port dimm check - helper for testing +/// @brief Checks that the starting port/dimm address is in range for broadcast mode - helper for testing /// @param[in] i_targets a vector of MCA targets -/// @param[in] i_start_addr the starting port_dimm seelct address +/// @param[in] i_start_addr the starting port_dimm select address /// @return FAPI2_RC_SUCCESS iff okay /// fapi2::ReturnCode broadcast_mode_start_address_check_helper( @@ -370,82 +78,7 @@ fapi2::ReturnCode broadcast_mode_start_address_check(const fapi2::Target<fapi2:: const uint64_t i_start_addr, std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> >& o_dimms); -/// -/// @brief Super Fast Read - used to run superfast read on all memory behind the target -/// Determines ability to braodcast to all ports behind a target, does so if possible. -/// @tparam T the fapi2::TargetType of the target -/// @param[in] i_target the target behind which all memory should be read -/// @param[in] i_stop stop conditions -/// @param[in] i_address mcbist::address representing the address from which to start. -// Defaults to the first address behind the target -/// @param[in] i_end whether to end, and where -/// Defaults to stop after slave rank -/// @param[in] i_end_address mcbist::address representing the address to end. -// Defaults to mcbist::address::LARGEST_ADDRESS -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// @note The address is often the port, dimm, rank but this is not enforced in the API. -/// -template< fapi2::TargetType T > -fapi2::ReturnCode sf_read( const fapi2::Target<T>& i_target, - const stop_conditions& i_stop, - const mss::mcbist::address& i_address = mss::mcbist::address(), - const end_boundary i_end = end_boundary::STOP_AFTER_SLAVE_RANK, - const mss::mcbist::address& i_end_address = mss::mcbist::address(mcbist::address::LARGEST_ADDRESS) ); - -/// -/// @brief Scrub - continuous scrub all memory behind the target -/// @param[in] i_target the target behind which all memory should be scrubbed -/// @param[in] i_stop stop conditions -/// @param[in] i_speed the speed to scrub -/// @param[in] i_address mcbist::address representing the address from which to start. -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// @note The address is often the port, dimm, rank but this is not enforced in the API. -/// -template< fapi2::TargetType T > -fapi2::ReturnCode background_scrub( const fapi2::Target<T>& i_target, - const stop_conditions& i_stop, - const speed i_speed, - const mss::mcbist::address& i_address ); - -/// -/// @brief Scrub - targeted scrub all memory described by the input address (rank, slave, etc.) -/// @param[in] i_target the target behind which all memory should be scrubbed -/// @param[in] i_stop stop conditions -/// @param[in] i_speed the speed to scrub -/// @param[in] i_start_address mcbist::address representing the address from which to start. -/// @param[in] i_end_address mcbist::address representing the address at which to end. -/// @param[in] i_end whether to end, and where -/// @return FAPI2_RC_SUCCESS iff everything ok -/// @note The function is asynchronous, and the caller should be looking for a done attention -/// @note The address is often the port, dimm, rank but this is not enforced in the API. -/// -template< fapi2::TargetType T > -fapi2::ReturnCode targeted_scrub( const fapi2::Target<T>& i_target, - const stop_conditions& i_stop, - const mss::mcbist::address& i_start_address, - const mss::mcbist::address& i_end_address, - const end_boundary i_end ); - -/// -/// @brief Continue current command on next address -/// The current commaand has paused on an error, so we can record the address of the error -/// and finish the current master or slave rank. -/// @tparam T the fapi2::TargetType of the target -/// @param[in] i_target the target -/// @param[in] i_end whether to end, and where (default - don't stop at end of rank) -/// @param[in] i_stop stop conditions (default - 0 meaning 'don't change conditions') -/// @param[in] i_speed the speed to scrub (default - SAME_SPEED meaning leave speed untouched) -/// @return FAPI2_RC_SUCCESS iff ok -/// -template< fapi2::TargetType T > -fapi2::ReturnCode continue_cmd( const fapi2::Target<T>& i_target, - const end_boundary i_end = end_boundary::DONT_CHANGE, - const stop_conditions& i_stop = stop_conditions(stop_conditions::DONT_CHANGE), - const speed i_speed = speed::SAME_SPEED ); - -} // namespace +} // ns memdiags -} // namespace +} // ns mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C deleted file mode 100644 index ef65e381a..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C +++ /dev/null @@ -1,146 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file patterns.C -/// @brief Static definition of MCBIST patterns -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#include <fapi2.H> -#include <vector> -#include <lib/mcbist/patterns.H> - -namespace mss -{ - -namespace mcbist -{ - -/// Vector of cache lines, seaprated in to two 64B chunks -// TK Real patterns from Marc representing the proper bits for ECC checking -const std::vector< pattern > patterns = -{ - // Pattern index 0 (Pattern 1 is this inverted) - { {0x0000000000000000, 0x0000000000000000}, - {0x0000000000000000, 0x0000000000000000}, - {0x0000000000000000, 0x0000000000000000}, - {0x0000000000000000, 0x0000000000000000}, - }, - - // Pattern index 2 (Pattern 3 is this inverted) - { {0x5555555555555555, 0x5555555555555555}, - {0xAAAAAAAAAAAAAAAA, 0xAAAAAAAAAAAAAAAA}, - {0x5555555555555555, 0x5555555555555555}, - {0xAAAAAAAAAAAAAAAA, 0xAAAAAAAAAAAAAAAA}, - }, - - // Pattern index 4 (Pattern 5 is this inverted) - { {0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}, - {0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0x0000000000000000}, - {0x0000000000000000, 0x0000000000000000}, - }, - - // Pattern index 6 (Pattern 7 is this inverted) - { {0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0x0000000000000000}, - {0xFFFFFFFFFFFFFFFF, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0x0000000000000000}, - }, - - // Pattern index 8 Random Seed - { {0x1234567887654321, 0x8765432112345678}, - {0x1234567887654321, 0x8765432112345678}, - {0x1234567887654321, 0x8765432112345678}, - {0x1234567887654321, 0x8765432112345678}, - }, - - // Pattern index 10 (Pattern 11 is this inverted), MPR pattern - { {0x0000000000000000, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0xFFFFFFFFFFFFFFFF}, - {0x0000000000000000, 0xFFFFFFFFFFFFFFFF}, - }, -}; - -// TK Want a new RC for random 24 -/// Vector of 24b random data seeds -const std::vector< random24_data_seed > random24_data_seeds = -{ - // 24 Bit Pattern index 0 (Pattern 1 is this inverted) - { {0x010203}, - {0x040506}, - {0x070809}, - }, - - // 24 Bit Pattern index 2 (Pattern 3 is this inverted) - { {0x112233}, - {0x445566}, - {0x778899}, - }, - -}; - -/// Vector of 24b random data seed mappings -// Not sure how many mapping we will want, for now it should be sufficient to -// have all bytes point to a different LFSR or all bytes point to the same LFSR -const std::vector< random24_seed_map > random24_seed_maps = -{ - // 8 Bit Pattern index 0 - // This selection maps every data byte to a different random LFSR - { {0x0}, - {0x1}, - {0x2}, - {0x3}, - {0x4}, - {0x5}, - {0x6}, - {0x7}, - {0x8}, - }, - - // 8 Bit Pattern index 1 - // This selection maps every data byte to random LFSR 0 - { {0x0}, - {0x0}, - {0x0}, - {0x0}, - {0x0}, - {0x0}, - {0x0}, - {0x0}, - {0x0}, - }, - -}; - -} - -} diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H deleted file mode 100644 index b5faeeffd..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H +++ /dev/null @@ -1,104 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/mcbist/patterns.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file patterns.H -/// @brief Static definition of MCBIST patterns -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#ifndef _MSS_MCBIST_PATTERNS_ -#define _MSS_MCBIST_PATTERNS_ - -#include <vector> - -namespace mss -{ -namespace mcbist -{ - -/// Memory diagnostic Pattern indexes. -// Why not an enum? I want to do math on them to generate a proper index in to a vector of -// patterns and enums really don't like that. -// Couple of extra symbols in here to keep things easy if desired -constexpr uint64_t PATTERN_ZEROS = 0; -constexpr uint64_t PATTERN_0 = PATTERN_ZEROS; -constexpr uint64_t PATTERN_ONES = 1; -constexpr uint64_t PATTERN_1 = PATTERN_ONES; -constexpr uint64_t PATTERN_2 = 2; -constexpr uint64_t PATTERN_3 = 3; -constexpr uint64_t PATTERN_4 = 4; -constexpr uint64_t PATTERN_5 = 5; -constexpr uint64_t PATTERN_6 = 6; -constexpr uint64_t PATTERN_7 = 7; -constexpr uint64_t PATTERN_8 = 8; -constexpr uint64_t PATTERN_9 = 9; -constexpr uint64_t PATTERN_10 = 10; -constexpr uint64_t PATTERN_RANDOM = PATTERN_8; -constexpr uint64_t LAST_PATTERN = PATTERN_10; - -// Don't mess with the patterns -constexpr uint64_t NO_PATTERN = LAST_PATTERN + 1; - -//Pattern references for the 24b random data pattern seeds -constexpr uint64_t MAX_NUM_RANDOM24_SEEDS = 3; -constexpr uint64_t RANDOM24_SEEDS_0 = 0; -constexpr uint64_t RANDOM24_SEEDS_1 = 1; -constexpr uint64_t RANDOM24_SEEDS_2 = 2; -constexpr uint64_t RANDOM24_SEEDS_3 = 3; -constexpr uint64_t LAST_RANDOM24_SEEDS = RANDOM24_SEEDS_3; -constexpr uint64_t NO_RANDOM24_SEEDS = LAST_RANDOM24_SEEDS + 1; - -//Pattern references for the 24b random data pattern seeds -constexpr uint64_t MAX_NUM_RANDOM24_MAPS = 9; -constexpr uint64_t RANDOM24_SEED_MAP_0 = 0; -constexpr uint64_t RANDOM24_SEED_MAP_1 = 1; -constexpr uint64_t LAST_RANDOM24_SEED_MAP = RANDOM24_SEED_MAP_1; -constexpr uint64_t NO_RANDOM24_SEED_MAP = LAST_RANDOM24_SEED_MAP + 1; -constexpr uint64_t RANDOM24_SEED_MAP_FIELD_LEN = 4; - - -/// Vector of cache lines, separated in to two 64B chunks -typedef std::pair<uint64_t, uint64_t> cache_line; -typedef std::vector< cache_line > pattern; -extern const std::vector< pattern > patterns; - -// Vector of 24b random data seeds -typedef std::vector< uint64_t > random24_data_seed; -extern const std::vector< random24_data_seed > random24_data_seeds; - -// Vector of 24b random data seed maps -typedef std::vector< uint64_t > random24_seed_map; -extern const std::vector< random24_seed_map > random24_seed_maps; - -}// mcbist - -}// mss -#endif - diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H index 3e89ee647..f4d822105 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/settings.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,759 +38,11 @@ #include <fapi2.H> -#include <p9_mc_scom_addresses.H> -#include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> +#include <lib/ecc/ecc_traits_nimbus.H> +#include <lib/mcbist/mcbist_traits.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_settings.H> -#include <lib/mcbist/address.H> -#include <lib/utils/bit_count.H> +// This file is still necessary to put traits and generic code together -namespace mss -{ - -namespace mcbist -{ - -/// End boundaries for MCBIST programs - where to stop when stopping or pausing -enum end_boundary : uint64_t -{ - // We're gonna get a little hacky here. The pause on error mode field - // is two bits, with another bit representing slave/master. So we craft - // the enum so that we can insertFromRight and get the proper vaules, and - // leave one bit out of that two-bit range to represent master or slave - NONE = 0b000, - STOP_AFTER_ADDRESS = 0b001, - STOP_AFTER_MASTER_RANK = 0b010, - STOP_AFTER_SLAVE_RANK = 0b110, - STOP_AFTER_SUBTEST = 0b011, - - DONT_CHANGE = 0xFF, -}; - -/// Speeds for performing MCBIST operations -enum speed -{ - /// As fast as possible, often the default - LUDICROUS = 0, - - /// Background scrubbing speed. - BG_SCRUB = 1, - - /// Used to indicate to the continue current command to not change the speed of the commands - SAME_SPEED = 4, -}; - -/// -/// @class Memory diagnostic subsystem stop-on-error settings and thresholds -/// @note Matches Nimbus MBSTRQ, but might be changed later for Centaur, or mapped. -/// -class stop_conditions -{ - public: - - // Many of the config fields share a disable bit pattern, so we define it here - static constexpr uint64_t DISABLE = 0b1111; - static constexpr uint64_t MAX_THRESHOLD = 0b1110; - static constexpr uint64_t DONT_CHANGE = 0; - - private: - - /// - /// @brief Little helper to convert threshold inputs to exponents - /// @param[in] i_value, the value of the threshold (presumably) - /// @return a value n such that 2^n <= i_value && n < 15 - /// - uint64_t make_threshold_setting( const uint64_t i_value ) - { - // If the user passes in DISABLE, let it past. This prevents callers from having to - // do the conditional. Zero is none which is disable - if ((i_value == DISABLE) || (i_value == 0)) - { - return DISABLE; - } - - // Find the first bit set. This represents the largest power of 2 this input can represent - // The subtraction from 63 switches from a left-count to a right-count (e.g., 0 (left most - // bit) is really bit 63 if you start on the right.) - const uint64_t l_largest = 63 - first_bit_set(i_value); - - // If the first bit set is off in space and greater than 2^14, we just return 0b1110 - // Otherwise, l_largest is the droid we're looking for - return l_largest >= MAX_THRESHOLD ? MAX_THRESHOLD : l_largest; - } - - /// - /// @brief Generic pause on threshold - /// @tparam F, the bit field to manipulate - /// @tparam L, the length of F - /// @param[in] the state of the error - mss::ON or mss::OFF - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - template< uint64_t F, uint64_t L > - inline stop_conditions& set_pause_on_threshold( const states i_on_or_off ) - { - if (i_on_or_off == mss::OFF) - { - iv_value.insertFromRight<F, L>(DISABLE); - return *this; - } - - uint64_t l_thresh = 0; - iv_value.extractToRight<F, L>(l_thresh); - - if (l_thresh == DISABLE) - { - // Note the threshold field is an exponent, so this is 2^0, or 1 count - iv_value.insertFromRight<F, L>(0); - } - - return *this; - } - - public: - /// - /// @brief Stop/Thresholds class ctor - /// - stop_conditions(): - iv_value(0) - { - // By default we want to start everything in 'don't stop' mode. This means disabling - // the errors which contain thresholds - set_thresh_nce_int(DISABLE) - .set_thresh_nce_soft(DISABLE) - .set_thresh_nce_hard(DISABLE) - .set_thresh_rce(DISABLE) - .set_thresh_ice(DISABLE) - .set_thresh_mce_int(DISABLE) - .set_thresh_mce_soft(DISABLE) - .set_thresh_mce_hard(DISABLE); - } - - /// - /// @brief Stop/Thresholds class ctor - /// @param[in] uint64_t representing the threshold register contents - /// - stop_conditions(const uint64_t i_value): - iv_value(i_value) - { - } - - /// - /// @brief Stop/Thresholds class dtor - /// - ~stop_conditions() = default; - - /// - /// @brief uint64_t conversion - /// - inline operator uint64_t() const - { - return uint64_t(iv_value); - } - - /// - /// @brief set_thresh_nce_int - /// @param[in] i_value the value of the field - /// NCE intermittent error threshold magnitude to trigger for triggering pause. If - /// 1111, then pause will never be triggered (disabled). Else, then MCBIST will - /// pause if it takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_nce_int( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_nce_int - enable NCE intermittent error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_nce_int( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_INT_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_nce_soft - /// @param[in] i_value the value of the field - /// NCE soft error threshold magnitude to trigger for triggering pause. If 1111, - /// then pause will never be triggered (disabled). Else, then MCBIST will pause if it - /// takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_nce_soft( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_nce_int - enable NCE soft error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_nce_soft( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_SOFT_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_nce_hard - /// @param[in] i_value the value of the field - /// NCE hard error threshold magnitude to trigger for triggering pause. If 1111, - /// then pause will never be triggered (disabled). Else, then MCBIST will pause if it - /// takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_nce_hard( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_nce_hard - enable NCE hard error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_nce_hard( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD, - MCBIST_MBSTRQ_CFG_THRESH_MAG_NCE_HARD_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_rce - /// @param[in] i_value the value of the field - /// RCE error threshold magnitude to trigger for triggering pause. If 1111, then - /// pause will never be triggered (disabled). Else, then MCBIST will pause if it takes - /// sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_rce( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE, - MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_rce - enable RCE error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_rce( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE, - MCBIST_MBSTRQ_CFG_THRESH_MAG_RCE_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_ice - /// @param[in] i_value the value of the field - /// ICE (IMPE) error threshold magnitude to trigger for triggering pause. If 1111, - /// then pause will never be triggered (disabled). Else, then MCBIST will pause if - /// it takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_ice( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE, - MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_ice - enable ICE (IMPE) error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_ice( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE, - MCBIST_MBSTRQ_CFG_THRESH_MAG_ICE_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_mce_int - /// @param[in] i_value the value of the field - /// MCE intermittent error threshold magnitude to trigger for triggering pause. If - /// 1111, then pause will never be triggered (disabled). Else, then MCBIST will - /// pause if it takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_mce_int( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_mce_int - enable MCE intermittent error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_mce_int( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_INT_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_mce_soft - /// @param[in] i_value the value of the field - /// MCE soft error threshold magnitude to trigger for triggering pause. If 1111, - /// then pause will never be triggered (disabled). Else, then MCBIST will pause if it - /// takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_mce_soft( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_mce_soft - enable MCE soft error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_mce_soft( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_SOFT_LEN>(i_on_or_off); - } - - /// - /// @brief set_thresh_mce_hard - /// @param[in] i_value the value of the field - /// MCE hard error threshold magnitude to trigger for triggering pause. If 1111, - /// then pause will never be triggered (disabled). Else, then MCBIST will pause if it - /// takes sees 2^[this value] number of errors of this type. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note The register field is actually an exponent. The hardware will count 2^n for the - /// threshold. However, the input represents a count - how many. Thus we need to convert - /// the input to a power of 2 to get a proper exponent. Your input will be rounded down - /// to the nearest power of 2 which is less than 2^15 before being set in the register. - /// - inline stop_conditions& set_thresh_mce_hard( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN>(make_threshold_setting(i_value)); - return *this; - } - - /// - /// @brief set_pause_on_mce_hard - enable MCE hard error - /// @param[in] i_on_or_off - the desired state. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// @note If the input is mss::ON, this method enables the error, it's corresponding - /// threshold defines the threshold at which the engine will stop. If no threshold is - /// defined (the error is disabled) this method will set the threshold to 1. A previously - /// defined threshold (i.e., not disabled) will be left intact. If the input - /// is mss::OFF, this method will disable the error by setting the threshold to disabled. - /// - inline stop_conditions& set_pause_on_mce_hard( const states i_on_or_off ) - { - return set_pause_on_threshold<MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD, - MCBIST_MBSTRQ_CFG_THRESH_MAG_MCE_HARD_LEN>(i_on_or_off); - } - - /// - /// @brief set_pause_on_sce - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on SCE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_sce( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_SCE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_mce - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on MCE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_mce( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_MCE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_mpe - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on MPE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_mpe( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_MPE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_ue - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on UE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_ue( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_UE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_sue - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on SUE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_sue( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_SUE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_aue - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on AUE error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_aue( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_AUE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_on_rcd - /// @param[in] i_on_or_off - the desired state. - /// Enable pause on RCD error. When enabled, MCBIST will pause at the boundary - /// configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_on_rcd( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_ON_RCD>(i_on_or_off); - return *this; - } - - /// - /// @brief set_symbol_counter_mode - /// @param[in] i_value the value of the field - /// Selects which mode to use symbol counter latches: Mode 0) MAINT 8-bit error - /// counters for of 72 symbols Mode 1) MCBIST 4-bit error counters for 18 nibbles x 8 - /// ranks (port agnostic) Mode 2) MCBIST 4-bit error counters for 18 nibbles x 4 - /// ports (rank agnostic) and 1-bit error rank map for 18 nibbles x 4 ports - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_symbol_counter_mode( const uint64_t i_value ) - { - iv_value.insertFromRight<MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE, - MCBIST_MBSTRQ_CFG_SYMBOL_COUNTER_MODE_LEN>(i_value); - return *this; - } - - /// - /// @brief set_nce_soft_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables soft NCEs to trigger per symbol NCE error counting Only applies to - /// scrub where we have different types of NCE. Non scrub counts all NCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_nce_soft_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_NCE_SOFT_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_nce_inter_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables intermittent NCEs to trigger per symbol NCE error counting Only applies - /// to scrub where we have different types of NCE. Non scrub counts all NCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_nce_inter_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_NCE_INTER_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_nce_hard_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables hard NCEs to trigger per symbol NCE error counting Only applies to - /// scrub where we have different types of NCE. Non scrub counts all NCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_nce_hard_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_NCE_HARD_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_mcb_error - /// @param[in] i_on_or_off - the desired state. - /// Enable pause when MCBIST error is logged. When enabled, MCBIST will pause at - /// the boundary configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_mcb_error( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_MCB_ERROR>(i_on_or_off); - return *this; - } - - /// - /// @brief set_pause_mcb_log_full - /// @param[in] i_on_or_off - the desired state. - /// Enable pause when MCBIST log is full. When enabled, MCBIST will pause at the - /// boundary configured if this error is seen. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_pause_mcb_log_full( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_PAUSE_MCB_LOG_FULL>(i_on_or_off); - return *this; - } - - /// - /// @brief set_maint_rce_with_ce - /// @param[in] i_on_or_off - the desired state. - /// cfg_maint_rce_with_ce - not implemented. Need to investigate if needed for nimbus. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_maint_rce_with_ce( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_MAINT_RCE_WITH_CE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_mce_soft_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables soft MCEs to trigger per symbol MCE error counting Only applies to - /// scrub where we have different types of MCE. Non scrub counts all MCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_mce_soft_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_MCE_SOFT_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_mce_inter_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables intermittent MCEs to trigger per symbol MCE error counting Only applies - /// to scrub where we have different types of MCE. Non scrub counts all MCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_mce_inter_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_MCE_INTER_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - /// - /// @brief set_mce_hard_symbol_count_enable - /// @param[in] i_on_or_off - the desired state. - /// Enables hard MCEs to trigger per symbol MCE error counting Only applies to - /// scrub where we have different types of MCE. Non scrub counts all MCE. - /// @return fapi2::buffer<uint64_t>& this->iv_value useful for method chaining - /// - inline stop_conditions& set_mce_hard_symbol_count_enable( const states i_on_or_off ) - { - iv_value.writeBit<MCBIST_MBSTRQ_CFG_MCE_HARD_SYMBOL_COUNT_ENABLE>(i_on_or_off); - return *this; - } - - private: - - fapi2::buffer<uint64_t> iv_value; -}; - -/// -/// @class memdiags operational constraints -/// -struct constraints -{ - /// - /// @brief constraints default constructor - /// - constraints(): - iv_stop(), - iv_pattern(NO_PATTERN), - iv_end_boundary(NONE), - iv_speed(LUDICROUS), - iv_start_address(0), - iv_end_address(mcbist::address::LARGEST_ADDRESS) - { - } - - /// - /// @brief constraints constructor - /// @param[in] i_pattern a pattern to set - /// - constraints( const uint64_t i_pattern ): - constraints() - { - iv_pattern = i_pattern; - FAPI_INF("setting up constraints with pattern %d", i_pattern); - } - - /// - /// @brief constraints constructor - /// @param[in] i_stop stop conditions - /// - constraints( const stop_conditions& i_stop ): - constraints() - { - iv_stop = i_stop; - FAPI_INF("setting up constraints with stop 0x%016lx", uint64_t(i_stop)); - } - - /// - /// @brief constraints constructor - /// @param[in] i_stop stop conditions - /// @param[in] i_start_address address to start from - /// - constraints( const stop_conditions& i_stop, - const address& i_start_address ): - constraints(i_stop) - { - iv_start_address = i_start_address; - FAPI_INF("setting up constraints with start address 0x%016lx", uint64_t(i_start_address)); - } - - /// - /// @brief constraints constructor - /// @param[in] i_stop stop conditions - /// @param[in] i_speed the speed at which to run - /// @param[in] i_end_boundary the place to stop on error - /// @param[in] i_start_address address to start from - /// @param[in] i_end_address address to end at (optional, run to end) - /// - constraints( const stop_conditions& i_stop, - const speed i_speed, - const end_boundary i_end_boundary, - const address& i_start_address, - const address& i_end_address = mcbist::address(mcbist::address::LARGEST_ADDRESS) ): - constraints(i_stop, i_start_address) - { - iv_end_boundary = i_end_boundary; - iv_speed = i_speed; - iv_end_address = i_end_address; - - FAPI_INF("setting up constraints with end boundary %d and speed 0x%x", i_end_boundary, i_speed); - - // If our end address is 'before' our start address, make the end address the same as the start. - if (iv_start_address > iv_end_address) - { - iv_end_address = iv_start_address; - } - } - - // Member variable declaration - stop_conditions iv_stop; - uint64_t iv_pattern; - end_boundary iv_end_boundary; - speed iv_speed; - mcbist::address iv_start_address; - mcbist::address iv_end_address; -}; - - -} // namespace -} // namespace #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C b/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C deleted file mode 100644 index 2fa88eb98..000000000 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C +++ /dev/null @@ -1,175 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/mcbist/sim.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2016,2019 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ - -/// -/// @file mcbist/sim.C -/// @brief MCBIST/memdiags functions for when we're in simulation mode -/// -// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> -// *HWP Team: Memory -// *HWP Level: 3 -// *HWP Consumed by: FSP:HB - -#include <lib/shared/nimbus_defaults.H> -#include <fapi2.H> - -#include <lib/dimm/rank.H> -#include <lib/mcbist/address.H> -#include <lib/mcbist/mcbist.H> -#include <lib/mcbist/patterns.H> -#include <lib/mcbist/sim.H> -#include <generic/memory/lib/utils/count_dimm.H> -#include <generic/memory/lib/utils/pos.H> - -using fapi2::TARGET_TYPE_MCBIST; -using fapi2::TARGET_TYPE_MCA; -using fapi2::TARGET_TYPE_SYSTEM; -using fapi2::FAPI2_RC_SUCCESS; - -namespace mss -{ - -namespace mcbist -{ - -namespace sim -{ - -/// -/// @brief Perform a sim version of initializing memory -/// @param[in] i_target MCBIST -/// @param[in] i_pattern an index representing a pattern to use to initize memory (defaults to 0) -/// @return FAPI2_RC_SUCCESS iff ok -/// -template<> -fapi2::ReturnCode sf_init( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - const uint64_t i_pattern ) -{ - FAPI_INF("Start sim init"); - - // If we're running in the simulator, we want to only touch the addresses which training touched - - for (const auto& p : i_target.getChildren<TARGET_TYPE_MCA>()) - { - std::vector<uint64_t> l_pr; - mss::mcbist::program<TARGET_TYPE_MCBIST> l_program; - - mss::mcbist::address l_start; - mss::mcbist::address l_end; - - size_t l_rank_address_pair = 0; - - // No point in bothering if we don't have any DIMM - if (mss::count_dimm(p) == 0) - { - FAPI_INF("No DIMM on %s, not running sf_init", mss::c_str(p)); - continue; - } - - // In sim we know a few things ... - // Get the primary ranks for this port. We know there can only be 4, and we know we only trained the primary - // ranks. Therefore, we only need to clean up the primary ranks. And because there's 4 max, we can do it - // all using the 4 address range registers of tne MCBIST (broadcast currently not considered.) - // So we can write 0's to those to get their ECC fixed up. - FAPI_TRY( mss::rank::primary_ranks(p, l_pr) ); - fapi2::Assert( l_pr.size() <= mss::MAX_RANK_PER_DIMM ); - - for (auto r = l_pr.begin(); r != l_pr.end(); ++l_rank_address_pair, ++r) - { - FAPI_INF("sim init %s, rank %d", mss::c_str(p), *r); - - // Setup l_start to represent this rank, and then make the end address from that. - l_start.set_master_rank(*r); - - // Set C3 bit to get an entire cache line - l_start.get_sim_end_address(l_end); - - // By default we're in maint address mode, not address counting mode. So we give it a start and end, and ignore - // anything invalid - that's what maint address mode is all about - mss::mcbist::config_address_range(i_target, l_start, l_end, l_rank_address_pair); - - // Write - { - // Run in ECC mode, 64B writes (superfast mode) - - mss::mcbist::subtest_t<TARGET_TYPE_MCBIST> l_fw_subtest = - mss::mcbist::write_subtest<TARGET_TYPE_MCBIST>(); - - l_fw_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); - l_fw_subtest.change_addr_sel(l_rank_address_pair); - l_fw_subtest.enable_dimm(mss::rank::get_dimm_from_rank(*r)); - l_program.iv_subtests.push_back(l_fw_subtest); - FAPI_DBG("adding superfast write for %s rank %d (dimm %d)", mss::c_str(p), *r, mss::rank::get_dimm_from_rank(*r)); - } - - // Read - we do a read here as verification can use this as a tool as we do the write and then the read. - // If we failed to write properly the read would thow ECC errors. Just a write (which the real hardware would - // do) doesn't catch that. This takes longer, but it's not terribly long in any event. - { - // Run in ECC mode, 64B writes (superfast mode) - mss::mcbist::subtest_t<TARGET_TYPE_MCBIST> l_fr_subtest = - mss::mcbist::read_subtest<TARGET_TYPE_MCBIST>(); - - l_fr_subtest.enable_port(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); - l_fr_subtest.change_addr_sel(l_rank_address_pair); - l_fr_subtest.enable_dimm(mss::rank::get_dimm_from_rank(*r)); - l_program.iv_subtests.push_back(l_fr_subtest); - FAPI_DBG("adding superfast read for %s rank %d (dimm %d)", mss::c_str(p), *r, mss::rank::get_dimm_from_rank(*r)); - } - } - - // Write pattern - FAPI_TRY( mss::mcbist::load_pattern(i_target, i_pattern) ); - - // Setup the sim polling based on a heuristic <cough>guess</cough> - // Looks like ~400ck per address for a write/read program on the sim-dimm, and add a long number of polls - // On real hardware wait 100ms and then start polling for another 5s - l_program.iv_poll.iv_initial_sim_delay = mss::cycles_to_simcycles(((l_end - l_start) * l_pr.size()) * 800); - l_program.iv_poll.iv_initial_delay = 100 * mss::DELAY_1MS; - l_program.iv_poll.iv_sim_delay = 100000; - l_program.iv_poll.iv_delay = 10 * mss::DELAY_1MS; - l_program.iv_poll.iv_poll_count = 500; - - // Just one port for now. Per Shelton we need to set this in maint address mode - // even tho we specify the port/dimm in the subtest. - fapi2::buffer<uint8_t> l_port; - l_port.setBit(mss::relative_pos<TARGET_TYPE_MCBIST>(p)); - l_program.select_ports(l_port >> 4); - - // Kick it off, wait for a result - FAPI_TRY( mss::mcbist::execute(i_target, l_program) ); - } - -fapi_try_exit: - FAPI_INF("End sim init"); - return fapi2::current_err; -} - -} // namespace sim - -} // namespace mcbist - -} // namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss.mk b/src/import/chips/p9/procedures/hwp/memory/lib/mss.mk index 2b07ee18c..878c51e37 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss.mk +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2015,2017 +# Contributors Listed Below - COPYRIGHT 2015,2019 # [+] International Business Machines Corp. # # @@ -44,6 +44,7 @@ $(call ADD_MODULE_INCDIR,$(1),$(FAPI2_PATH)/include) $(call ADD_MODULE_INCDIR,$(1),$(GENPATH)) $(call ADD_MODULE_INCDIR,$(1),$(FAPI2_PLAT_INCLUDE)) $(call ADD_MODULE_INCDIR,$(1),$(ROOTPATH)) +$(call ADD_MODULE_INCDIR,$(1),$(ROOTPATH)/generic/memory/lib) endef MODULE = mss OBJS += $(MSS_MODULE_OBJS) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index c482989dd..709d3af1b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14142,6 +14142,31 @@ fapi_try_exit: /// +/// @brief ATTR_MSS_MRW_NVDIMM_SLOT_POSITION getter +/// @param[in] const ref to the TARGET_TYPE_DIMM +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note The position of a dimm is based on which mca it is associated with and which +/// drop behind that mca, with 16 dimms possible per processor socket. The formula +/// is: [processor position with no gaps, i.e. 0,1,2,3]*16 + [mca position on this +/// processor * 2] + [dimm location behind this +/// mca] +/// +inline fapi2::ReturnCode mrw_nvdimm_slot_position(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_NVDIMM_SLOT_POSITION, i_target, o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_NVDIMM_SLOT_POSITION: 0x%lx", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// /// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter /// @param[in] const ref to the fapi2::Target<fapi2::TARGET_TYPE_MCA> /// @param[out] ref to the value uint64_t @@ -21501,6 +21526,172 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook Thermal Memory Power Limit Used to calculate throttles +/// to meet the thermal power per DIMM limit Per DIMM basis, uses first matching KEY +/// entry KEY (0-21): In order DIMM_SIZE = bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = +/// 6-8, DIMM_WIDTH = 9-11, DIMM_DENSITY = 12-14, DIMM_STACK_TYPE = 15-16, +/// DRAM_MFGID = 17-19, DIMM_HEIGHT = 20-21, Bits 22-32: Not used VALUE (bits 32-47) +/// in cW: thermal power limit DDIMM: Total OCMB+DRAM power limit per DDIMM +/// non-DDIMM: VMEM+VPP power limit per +/// DIMM +/// +inline fapi2::ReturnCode mrw_ocmb_thermal_memory_power_limit(uint64_t* o_array) +{ + uint64_t l_value[25]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_value) ); + memcpy(o_array, &l_value, 200); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_OCMB_THERMAL_MEMORY_POWER_LIMIT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_OCMB_PWR_SLOPE getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook Power Curve Slope for DIMM Used to calculate thermal +/// throttles and port power Per DIMM basis, uses first matching KEY entry KEY +/// (0-21): In order DIMM_SIZE = bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-8, +/// DIMM_WIDTH = 9-11, DIMM_DENSITY = 12-14, DIMM_STACK_TYPE = 15-16, DRAM_MFGID = +/// 17-19, DIMM_HEIGHT = 20-21, Bits 22-32: Not used VALUE (bits 32-47) in +/// cW/utilization: DIMM power slope DDIMM: Total OCMB+DRAM power slope per DDIMM +/// non-DDIMM: VMEM+VPP power slope per +/// DIMM +/// +inline fapi2::ReturnCode mrw_ocmb_pwr_slope(uint64_t* o_array) +{ + uint64_t l_value[50]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OCMB_PWR_SLOPE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_value) ); + memcpy(o_array, &l_value, 400); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_OCMB_PWR_SLOPE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_OCMB_PWR_INTERCEPT getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook Power Curve Intercept for DIMM Used to calculate +/// thermal throttles and port power Per DIMM basis, uses first matching KEY entry +/// KEY (0-21): In order DIMM_SIZE = bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-8, +/// DIMM_WIDTH = 9-11, DIMM_DENSITY = 12-14, DIMM_STACK_TYPE = 15-16, DRAM_MFGID = +/// 17-19, DIMM_HEIGHT = 20-21, Bits 22-32: Not used VALUE (bits 32-47) in +/// cW/utilization: DIMM power intercept DDIMM: Total OCMB+DRAM power intercept per +/// DDIMM non-DDIMM: VMEM+VPP power intercept per +/// DIMM +/// +inline fapi2::ReturnCode mrw_ocmb_pwr_intercept(uint64_t* o_array) +{ + uint64_t l_value[50]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OCMB_PWR_INTERCEPT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_value) ); + memcpy(o_array, &l_value, 400); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_OCMB_PWR_INTERCEPT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook Current Curve Intercept and limit for DIMM Used to +/// calculate throttles to meet regulator current per DIMM limit Per DIMM basis, +/// uses first matching KEY entry For DDIMM, use PMIC SW output that provides worst +/// case throttling KEY (0-21): In order DIMM_SIZE = bits 0-3, DIMM_GEN = 4-5, +/// DIMM_TYPE = 6-8, DIMM_WIDTH = 9-11, DIMM_DENSITY = 12-14, DIMM_STACK_TYPE = +/// 15-16, DRAM_MFGID = 17-19, DIMM_HEIGHT = 20-21, Bits 22-32: Not used VALUE (bits +/// 32-39): Current limit (dA) DDIMM: PMIC output current limit per DDIMM non-DDIMM: +/// VMEM regulator current limit per DIMM VALUE (bits 40-51): Current slope +/// (cA/utilization) DDIMM: PMIC output current slope per DDIMM non-DDIMM: VMEM +/// regulator current slope per DIMM VALUE (bits 52-63): Current intercept (cA) +/// DDIMM: PMIC output current intercept per DDIMM non-DDIMM: VMEM regulator current +/// intercept per +/// DIMM +/// +inline fapi2::ReturnCode mrw_ocmb_current_curve_with_limit(uint64_t* o_array) +{ + uint64_t l_value[25]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + l_value) ); + memcpy(o_array, &l_value, 200); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_OCMB_CURRENT_CURVE_WITH_LIMIT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_SAFEMODE_DRAM_DATABUS_UTIL getter +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook value for safe mode dram data bus utilization in centi +/// percent (c%). Set to below optimum value/ rate. On a per port basis Also used +/// for emergency mode throttle Used to thermally protect the system in all +/// supported environmental conditions when OCC is not functional Consumer: +/// thermal_init, initfile Default to 2500 +/// c%% +/// +inline fapi2::ReturnCode mrw_safemode_dram_databus_util(uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SAFEMODE_DRAM_DATABUS_UTIL, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_SAFEMODE_DRAM_DATABUS_UTIL: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MEM_PORT_POS_OF_FAIL_THROTTLE getter +/// @param[out] uint64_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note This is the fapi position of the port that failed to calculate memory throttles +/// given the passed in watt target and or +/// utilization +/// +inline fapi2::ReturnCode port_pos_of_fail_throttle(uint64_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_PORT_POS_OF_FAIL_THROTTLE, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MEM_PORT_POS_OF_FAIL_THROTTLE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H index 201b1ee39..cf0884182 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors_manual.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,7 +40,7 @@ #define MSS_ATTR_ACCESS_MANUAL_H_ #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/mss_attribute_accessors.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H index d33f69a26..fd6485d83 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_vpd_decoder.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,7 @@ #include <lib/shared/mss_const.H> #include <lib/mss_utils.H> #include <lib/mss_attribute_accessors.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/index.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C index f68b7dab9..c12adbab8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,7 @@ #include <lib/phy/adr32s.H> #include <lib/phy/dcd.H> #include <lib/workarounds/adr32s_workarounds.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/mss_attribute_accessors_manual.H> using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H index 0de3f350e..ee8e54121 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/adr32s.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,7 +42,7 @@ #include <lib/mss_attribute_accessors.H> #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> namespace mss { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C index 88337c26c..82769de0f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C @@ -48,6 +48,7 @@ #include <lib/phy/adr.H> #include <lib/phy/seq.H> #include <lib/fir/check.H> +#include <lib/ccs/ccs_nimbus.H> #include <lib/workarounds/dp16_workarounds.H> #include <lib/workarounds/wr_vref_workarounds.H> #include <lib/dimm/ddr4/latch_wr_vref.H> @@ -55,10 +56,10 @@ #include <lib/workarounds/dll_workarounds.H> #include <lib/workarounds/dqs_align_workarounds.H> #include <lib/phy/mss_training.H> -#include <generic/memory/lib/utils/find_magic.H> +#include <lib/utils/find_magic.H> #include <generic/memory/lib/utils/bit_count.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/utils/dump_regs.H> +#include <lib/utils/nimbus_find.H> +#include <generic/memory/lib/utils/dump_regs.H> #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/dimm/rank.H> @@ -1038,9 +1039,9 @@ fapi2::ReturnCode execute_cal_steps_helper( const fapi2::Target<TARGET_TYPE_MCA> const uint64_t i_total_cycles) { const auto& l_mcbist = mss::find_target<TARGET_TYPE_MCBIST>(i_target); - auto l_cal_inst = mss::ccs::initial_cal_command<TARGET_TYPE_MCBIST>(i_rp); + auto l_cal_inst = mss::ccs::initial_cal_command(i_rp); - mss::ccs::program<TARGET_TYPE_MCBIST, TARGET_TYPE_MCA> l_program; + ccs::program l_program; FAPI_DBG("%s executing training CCS instruction: 0x%016llx, 0x%016llx for cal config 0x%16x", mss::c_str(i_target), @@ -1303,7 +1304,7 @@ fapi2::ReturnCode override_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE FAPI_ASSERT( i_rank < MAX_MRANK_PER_PORT, fapi2::MSS_INVALID_RANK() .set_RANK(i_rank) - .set_MCA_TARGET(i_target) + .set_PORT_TARGET(i_target) .set_FUNCTION(OVERRIDE_ODT_WR_CONFIG), "%s had invalid rank (0x%016lx) passed into override_odt_wr_config", mss::c_str(i_target), @@ -1337,7 +1338,7 @@ fapi_try_exit: template<> fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Danger: Make sure this DIMM target doesn't get used/accessed until it is populated // by get_dimm_target_from_rank below! @@ -1396,7 +1397,7 @@ fapi_try_exit: template<> fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Danger: Make sure this DIMM target doesn't get used/accessed until it is populated // by get_dimm_target_from_rank below! diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H index 9195725ae..06a115d85 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,7 +37,10 @@ #define _MSS_DDR_PHY_H_ #include <fapi2.H> -#include <lib/ccs/ccs.H> +#include <lib/shared/mss_const.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> + namespace mss { @@ -295,16 +298,15 @@ fapi2::ReturnCode override_odt_wr_config( const fapi2::Target<fapi2::TARGET_TYPE /// /// @brief Setup terminations for WR_LEVEL cal for a given RP /// @tparam T the target type of the MCA/MBA -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target the target associated with this cal setup /// @param[in] i_rp selected rank pair /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<T>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Setup terminations for WR_LEVEL cal for a given RP @@ -313,24 +315,23 @@ fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<T>& i_target, /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template<> +template< > fapi2::ReturnCode setup_wr_level_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Restore terminations after WR_LEVEL cal for a given RP /// @tparam T the target type of the MCA/MBA -/// @tparam CT TargetType of the CCS instruction /// @param[in] i_target the target associated with this cal setup /// @param[in] i_rp selected rank pair /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template< fapi2::TargetType T, fapi2::TargetType CT > +template< fapi2::TargetType T > fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<T>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<CT> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Restore terminations after WR_LEVEL cal for a given RP @@ -339,10 +340,10 @@ fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<T>& i_targe /// @param[in,out] io_inst a vector of CCS instructions we should add to /// @return FAPI2_RC_SUCCESS iff setup was successful /// -template<> +template< > fapi2::ReturnCode restore_mainline_terminations( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); /// /// @brief Perform the DLL calibration diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 507f95f86..81b8114ff 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -51,7 +51,7 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/pos.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find_magic.H> +#include <lib/utils/find_magic.H> #include <lib/workarounds/dp16_workarounds.H> #include <lib/fir/check.H> #include <generic/memory/lib/utils/mss_math.H> @@ -4626,7 +4626,7 @@ fapi2::ReturnCode check_rp_and_dram( const fapi2::Target<fapi2::TARGET_TYPE_MCA> // Checks for i_rp in bounds FAPI_ASSERT(i_rp < MAX_RANK_PAIRS, fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(i_rp). set_FUNCTION(i_function), "%s rank pair is out of bounds %lu", mss::c_str(i_target), i_rp); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index 73e011b94..1f9f9714d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -42,7 +42,7 @@ #include <p9_mc_scom_addresses_fld.H> #include <generic/memory/lib/utils/scom.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/mss_bad_bits.H> #include <lib/mss_attribute_accessors.H> #include <lib/shared/mss_const.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C index 8994a75d0..b57aa7070 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.C @@ -38,6 +38,7 @@ #include <lib/shared/nimbus_defaults.H> #include <p9_mc_scom_addresses.H> #include <p9_mc_scom_addresses_fld.H> +#include <lib/shared/mss_const.H> #include <lib/phy/mss_lrdimm_training.H> #include <lib/phy/mss_training.H> #include <lib/dimm/rank.H> @@ -45,13 +46,15 @@ #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> #include <lib/workarounds/ccs_workarounds.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/mc/port.H> #include <lib/rosetta_map/rosetta_map.H> #include <lib/dimm/ddr4/pba.H> #include <lib/eff_config/timing.H> #include <generic/memory/lib/utils/pos.H> + #ifdef LRDIMM_CAPABLE #include <lib/phy/mss_lrdimm_training_helper.H> #endif @@ -190,7 +193,7 @@ fapi2::ReturnCode mpr_pattern_wr_rank(const fapi2::Target<fapi2::TARGET_TYPE_MCA return fapi2::FAPI2_RC_SUCCESS; } - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Gets the DIMM target @@ -250,16 +253,17 @@ fapi_try_exit: /// fapi2::ReturnCode execute_nttm_mode_read(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) { - using TT = ccsTraits<fapi2::TARGET_TYPE_MCBIST>; + + using TT = ccsTraits<mss::mc_type::NIMBUS>; // A hardware bug requires us to increase our delay significanlty for NTTM mode reads constexpr uint64_t SAFE_NTTM_READ_DELAY = 0x40; - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); // Note: CKE are enabled by default in the NTTM mode read command, so we should be good to go // set the NTTM read mode - auto l_nttm_read = mss::ccs::nttm_read_command<fapi2::TARGET_TYPE_MCBIST>(); + auto l_nttm_read = mss::ccs::nttm_read_command(); l_nttm_read.arr1.template insertFromRight<TT::ARR1_IDLES, TT::ARR1_IDLES_LEN>(SAFE_NTTM_READ_DELAY); l_program.iv_instructions.push_back(l_nttm_read); @@ -439,21 +443,21 @@ fapi2::ReturnCode mrep::set_delay(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& const uint8_t i_rank, const uint8_t i_delay ) const { - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); std::vector<cw_info> l_bcws = { - {i_rank, NIBBLE0_BCW_NUMBER, i_delay, mss::tmrc(), mss::CW8_DATA_LEN, cw_info::BCW}, - {i_rank, NIBBLE1_BCW_NUMBER, i_delay, mss::tmrc(), mss::CW8_DATA_LEN, cw_info::BCW}, + {i_rank, NIBBLE0_BCW_NUMBER, i_delay, mss::tmrd_l2(), mss::CW8_DATA_LEN, cw_info::BCW}, + {i_rank, NIBBLE1_BCW_NUMBER, i_delay, mss::tmrd_l2(), mss::CW8_DATA_LEN, cw_info::BCW}, }; uint8_t l_sim = 0; FAPI_TRY(mss::is_simulation(l_sim)); // Ensure our CKE's are powered on - l_program.iv_instructions.push_back(mss::ccs::des_command<fapi2::TARGET_TYPE_MCBIST>()); + l_program.iv_instructions.push_back(mss::ccs::des_command()); // Inserts the function space selects FAPI_TRY(mss::ddr4::insert_function_space_select(l_bcws)); @@ -807,9 +811,11 @@ void deconfigure_steps(const uint8_t i_dimm_type, // If the DIMM type is an LRDIMM, configure for LRDIMM if(i_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) { - FAPI_INF("LRDIMM: deconfigure WR VREF 2D"); + FAPI_INF("LRDIMM: deconfigure WR VREF 2D and RD VREF 2D"); // We clear WRITE_CTR_2D_VREF as the HW calibration algorithm will not work with LRDIMM - io_cal_steps.clearBit<WRITE_CTR_2D_VREF>(); + // Same for RD VREF + io_cal_steps.clearBit<WRITE_CTR_2D_VREF>() + .clearBit<READ_CTR_2D_VREF>(); return; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H index c7d92d98a..eef2c09d4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_lrdimm_training.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,8 +39,10 @@ #define MSS_LRDIMM_TRAINING_H #include <generic/memory/lib/utils/shared/mss_generic_consts.H> +#include <lib/shared/mss_const.H> #include <lib/phy/mss_training.H> -#include <lib/ccs/ccs.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> #include <lib/dimm/ddr4/control_word_ddr4.H> #include <lib/dimm/ddr4/data_buffer_ddr4.H> @@ -52,6 +54,7 @@ #include <lib/rosetta_map/rosetta_map.H> #include <lib/phy/ddr_phy.H> + // Disables LRDIMM support for HB #ifndef __HOSTBOOT_MODULE #define CONFIG_LRDIMM_CAPABLE 1 @@ -86,18 +89,16 @@ fapi2::ReturnCode mpr_pattern_wr_all_ranks(const fapi2::Target<fapi2::TARGET_TYP /// /// @brief Adds all write commands for the passed in pattern -/// @tparam fapi2::TargetType T target type for the CCS instruction /// @param[in] i_target DIMM target on which to operate /// @param[in] i_rank the DIMM rank to set the MPR on /// @param[in] i_pattern the pattern to write into the MPRS /// @param[in,out] io_insts CCS instructions /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok /// -template<fapi2::TargetType T> inline fapi2::ReturnCode add_mpr_pattern_writes(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, const uint64_t i_pattern, - std::vector<mss::ccs::instruction_t<T>>& io_insts) + std::vector<mss::ccs::instruction_t>& io_insts) { constexpr uint64_t NUM_MPR_PATTERNS = 4; @@ -122,10 +123,10 @@ inline fapi2::ReturnCode add_mpr_pattern_writes(const fapi2::Target<fapi2::TARGE FAPI_TRY(l_swizzled_pattern.extract(l_pattern, l_ba * PATTERN_LEN, PATTERN_LEN, ADDR_START), "%s ba%u", mss::c_str(i_target), l_ba); { - auto l_wr = mss::ccs::wr_command<fapi2::TARGET_TYPE_MCBIST>( i_rank, - l_ba, - MPR_WR_BG, - l_pattern); + auto l_wr = mss::ccs::wr_command( i_rank, + l_ba, + MPR_WR_BG, + l_pattern); // Swaps the bank addresses so they're a true to the BA we tried to pass in above swap<BA0, BA1>(l_wr.arr0); @@ -142,14 +143,12 @@ fapi_try_exit: /// /// @brief Helper function to disable address inversion -/// @tparam fapi2::TargetType T target type for the CCS instruction /// @param[in] i_target DIMM target on which to operate /// @param[in,out] io_insts CCS instructions /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok /// -template<fapi2::TargetType T> inline fapi2::ReturnCode disable_address_inversion(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector<mss::ccs::instruction_t<T>>& io_insts) + std::vector<mss::ccs::instruction_t>& io_insts) { // Declares the default control word that handles address inversion // Data of 0 as we're going to override it below @@ -177,14 +176,12 @@ fapi_try_exit: /// /// @brief Helper function to restore default address inversion -/// @tparam fapi2::TargetType T target type for the CCS instruction /// @param[in] i_target DIMM target on which to operate /// @param[in,out] io_insts CCS instructions /// @return fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ok /// -template<fapi2::TargetType T> inline fapi2::ReturnCode restore_address_inversion(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - std::vector<mss::ccs::instruction_t<T>>& io_insts) + std::vector<mss::ccs::instruction_t>& io_insts) { // Declares the default control word that handles address inversion // Data of 0 as we're going to override it below @@ -590,7 +587,7 @@ inline fapi2::ReturnCode set_buffer_training(const fapi2::Target<fapi2::TARGET_T const mss::ddr4::training i_mode ) { - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -615,7 +612,7 @@ inline fapi2::ReturnCode mpr_load(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& const uint8_t i_mode, const uint64_t i_rank) { - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); @@ -647,7 +644,7 @@ inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& constexpr uint64_t SAFETY_CYCLES = 2; constexpr uint64_t ODT_CYCLE_LEN = 5 + SAFETY_CYCLES * 2; - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST> l_program; + mss::ccs::program l_program; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); uint8_t l_cl = 0; @@ -661,16 +658,16 @@ inline fapi2::ReturnCode mpr_read( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& FAPI_TRY(mss::eff_odt_rd(i_target, &l_rd_odt[0])); - FAPI_TRY( ddr4::mpr_read<fapi2::TARGET_TYPE_MCBIST>(i_target, i_mpr_loc, i_rank, l_program.iv_instructions)); + FAPI_TRY( ddr4::mpr_read(i_target, i_mpr_loc, i_rank, l_program.iv_instructions)); l_program.iv_instructions[0].arr1.template insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(l_delay); // Holds the RD ODT's for 5 cycles { - const auto l_ccs_value = mss::ccs::convert_odt_attr_to_ccs<fapi2::TARGET_TYPE_MCBIST>(fapi2::buffer<uint8_t> + const auto l_ccs_value = mss::ccs::convert_odt_attr_to_ccs(fapi2::buffer<uint8_t> (l_rd_odt[l_dimm_rank])); - auto l_odt = mss::ccs::odt_command<fapi2::TARGET_TYPE_MCBIST>(l_ccs_value, ODT_CYCLE_LEN); + auto l_odt = mss::ccs::odt_command(l_ccs_value, ODT_CYCLE_LEN); l_program.iv_instructions.push_back(l_odt); } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C index 50574d764..d48202d17 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/mss_training.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2019 */ +/* Contributors Listed Below - COPYRIGHT 2017,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,6 +55,7 @@ #include <lib/dimm/ddr4/pda.H> #include <lib/phy/seq.H> #include <lib/phy/read_cntrl.H> +#include <lib/mss_attribute_accessors.H> #ifdef LRDIMM_CAPABLE #include <lib/phy/mss_dwl.H> @@ -67,6 +68,19 @@ namespace mss { +/// +/// @brief Bad bit getter - Nimbus specialization +/// @param[in] i_target the fapi2 target oon which training was conducted +/// @param[out] o_array the bad bits +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +template <> +fapi2::ReturnCode get_bad_dq_bitmap<mss::mc_type::NIMBUS>(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint8_t (&o_array)[BAD_BITS_RANKS][BAD_DQ_BYTE_COUNT]) +{ + return mss::bad_dq_bitmap(i_target, &(o_array[0][0])); +} + namespace training { // Below definitions are used to avoid linker errors @@ -198,7 +212,7 @@ fapi2::ReturnCode wr_lvl::pre_workaround( const fapi2::Target<fapi2::TARGET_TYPE const uint64_t i_rp, const uint8_t i_abort_on_error ) const { - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> > l_rtt_inst; + std::vector< ccs::instruction_t > l_rtt_inst; FAPI_DBG("%s Running Pre-WR_LEVEL workaround steps on RP%d", mss::c_str(i_target), i_rp); // Setup WR_LEVEL specific terminations @@ -208,7 +222,7 @@ fapi2::ReturnCode wr_lvl::pre_workaround( const fapi2::Target<fapi2::TARGET_TYPE if (!l_rtt_inst.empty()) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; l_program.iv_instructions.insert(l_program.iv_instructions.end(), l_rtt_inst.begin(), l_rtt_inst.end() ); FAPI_TRY( mss::ccs::execute(l_mcbist, l_program, i_target) ); l_program.iv_instructions.clear(); @@ -261,7 +275,7 @@ fapi2::ReturnCode wr_lvl::post_workaround( const fapi2::Target<fapi2::TARGET_TYP const uint64_t i_rp, const uint8_t i_abort_on_error ) const { - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> > l_rtt_inst; + std::vector< ccs::instruction_t > l_rtt_inst; FAPI_DBG("%s Running Post-WR_LEVEL workaround steps on RP%d", mss::c_str(i_target), i_rp); @@ -270,7 +284,7 @@ fapi2::ReturnCode wr_lvl::post_workaround( const fapi2::Target<fapi2::TARGET_TYP if (!l_rtt_inst.empty()) { const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; l_program.iv_instructions.insert(l_program.iv_instructions.end(), l_rtt_inst.begin(), l_rtt_inst.end() ); @@ -660,14 +674,14 @@ fapi2::ReturnCode write_ctr::post_workaround( const fapi2::Target<fapi2::TARGET_ // If the rank vector is empty log an error FAPI_ASSERT(!l_ranks.empty(), fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(i_rp). set_FUNCTION(mss::ffdc_function_codes::WR_VREF_TRAINING_WORKAROUND), "%s rank pair is empty! %lu", mss::c_str(i_target), i_rp); FAPI_ASSERT(l_ranks[0] != NO_RANK, fapi2::MSS_INVALID_RANK(). - set_MCA_TARGET(i_target). + set_PORT_TARGET(i_target). set_RANK(NO_RANK). set_FUNCTION(mss::ffdc_function_codes::WR_VREF_TRAINING_WORKAROUND), "%s rank pair has no ranks %lu", mss::c_str(i_target), i_rp); @@ -767,7 +781,7 @@ fapi2::ReturnCode write_ctr::post_workaround( const fapi2::Target<fapi2::TARGET_ // As such, let's run the nvdimm with rank median vref value so later on we can just load // the vref in 1 ccs sequence. if ((l_hybrid[0] == fapi2::ENUM_ATTR_EFF_HYBRID_IS_HYBRID) && - (l_hybrid_type[0] == fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NVDIMM) && !iv_wr_vref) + (l_hybrid_type[0] == fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NVDIMM) && iv_wr_vref) { FAPI_TRY(mss::workarounds::wr_vref::nvdimm_workaround(i_target, i_rp, i_abort_on_error)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/accessor_wrapper.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/accessor_wrapper.H index a9cebab3a..fd0991a7a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/accessor_wrapper.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/accessor_wrapper.H @@ -22,3 +22,260 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file accessor_wrapper.H +/// @brief The wrapper of new accessor API(get_/set_) to old accessor API +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_ACCESSOR_WRAPPER_ +#define _MSS_ACCESSOR_WRAPPER_ + +#include <fapi2.H> +#include <lib/shared/mss_const.H> +#include <lib/mss_attribute_accessors.H> + + +namespace mss +{ +namespace attr +{ +/// +/// @brief ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Runtime throttle numerator setting for cfg_nm_n_per_slot +/// +inline fapi2::ReturnCode get_runtime_mem_throttled_n_commands_per_slot(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& + i_target, uint16_t& o_value) +{ + return mss::runtime_mem_throttled_n_commands_per_slot(i_target, o_value); +} + +/// +/// @brief ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT setter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[in] uint16_t the value to set +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Runtime throttle numerator setting for cfg_nm_n_per_slot +/// +inline fapi2::ReturnCode set_runtime_mem_throttled_n_commands_per_slot(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& + i_target, uint16_t i_value) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT, + i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + l_value[mss::index(i_target)] = i_value; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT, + i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed setting ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + + +/// +/// @brief ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Runtime throttled N commands per M DRAM clocks setting for cfg_nm_n_per_port. +/// +inline fapi2::ReturnCode get_runtime_mem_throttled_n_commands_per_port(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& + i_target, uint16_t& o_value) +{ + return mss::runtime_mem_throttled_n_commands_per_port(i_target, o_value); +} + +/// +/// @brief ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT setter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[in] uint16_t the value to set +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Runtime throttled N commands per M DRAM clocks setting for cfg_nm_n_per_port. +/// +inline fapi2::ReturnCode set_runtime_mem_throttled_n_commands_per_port(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& + i_target, uint16_t i_value) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT, + i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + l_value[mss::index(i_target)] = i_value; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT, + i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed setting ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note This is the throttle numerator setting for cfg_nm_n_per_slot +/// +inline fapi2::ReturnCode get_mem_throttled_n_commands_per_slot(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t& o_value) +{ + return mss::mem_throttled_n_commands_per_slot(i_target, o_value); +} + +/// +/// @brief ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT setter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[in] uint16_t the value to set +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note This is the throttled N commands per window of M DRAM clocks setting for cfg_nm_n_per_port. +/// +inline fapi2::ReturnCode set_mem_throttled_n_commands_per_port(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t i_value) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + l_value[mss::index(i_target)] = i_value; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed setting ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t& reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note This is the throttled N commands per window of M DRAM clocks setting for cfg_nm_n_per_port. +/// +inline fapi2::ReturnCode get_mem_throttled_n_commands_per_port(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t& o_value) +{ + return mss::mem_throttled_n_commands_per_port(i_target, o_value); +} + +/// +/// @brief ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT setter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[in] uint16_t the value to set +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note This is the throttle numerator setting for cfg_nm_n_per_slot +/// +inline fapi2::ReturnCode set_mem_throttled_n_commands_per_slot(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t i_value) +{ + uint16_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + l_value[mss::index(i_target)] = i_value; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), + l_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed setting ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_PORT_MAXPOWER setter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[in] uint32_t the value to set +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff set is OK +/// @note Channel Pair Max Power output from thermal procedures +/// +inline fapi2::ReturnCode set_port_maxpower(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, uint32_t i_value) +{ + uint32_t l_value[2] = {}; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_PORT_MAXPOWER, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + l_value[mss::index(i_target)] = i_value; + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_MSS_PORT_MAXPOWER, i_target.getParent<fapi2::TARGET_TYPE_MCS>(), l_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed setting ATTR_MSS_PORT_MAXPOWER: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + + +/// +/// @brief ATTR_MSS_DIMM_THERMAL_LIMIT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint32_t&[] array reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note DIMM Max Power based on a thermal limit Decoded from ATTR_MSS_MRW_THERMAL_POWER_LIMIT +/// +inline fapi2::ReturnCode get_dimm_thermal_limit(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint32_t (&o_array)[2]) +{ + return mss::dimm_thermal_limit(i_target, o_array); +} + +/// +/// @brief ATTR_MSS_TOTAL_PWR_INTERCEPT getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t&[] array reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note VDDR+VPP Power intercept value for dimm creator: mss_eff_config consumer: mss_bulk_pwr_throttles +/// +inline fapi2::ReturnCode get_total_pwr_intercept(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t (&o_array)[2]) +{ + return total_pwr_intercept(i_target, o_array); +} + +/// +/// @brief ATTR_MSS_TOTAL_PWR_SLOPE getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint16_t&[] array reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note VDDR+VPP Power slope value for dimm creator: mss_eff_config consumer: mss_bulk_pwr_throttles +/// +inline fapi2::ReturnCode get_total_pwr_slope(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + uint16_t (&o_array)[2]) +{ + return mss::total_pwr_slope(i_target, o_array); +} + +/// +/// @brief ATTR_MSS_MEM_WATT_TARGET getter +/// @param[in] const ref to the TARGET_TYPE_MCA +/// @param[out] uint32_t&[] array reference to store the value +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Total memory power used to throttle for each dimm Used to compute the throttles +/// on the channel and/or dimms for OCC OCC sets after IPL creator: mss_eff_config consumer: +/// mss_bulk_pwr_throttle, mss_utils_to_throttle firmware notes: none. +/// +inline fapi2::ReturnCode get_mem_watt_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + uint32_t& o_value) +{ + return mss::mem_watt_target(i_target, o_value); +} + +}// namespace attr +}// namespace mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C index b381042a2..8855a30f7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,6 +32,7 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> // fapi2 #include <fapi2.H> #include <vector> @@ -41,103 +42,24 @@ #include <mss.H> #include <lib/power_thermal/throttle.H> #include <lib/power_thermal/decoder.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/count_dimm.H> -#include <lib/dimm/kind.H> -#include <lib/shared/mss_const.H> +#include <generic/memory/lib/utils/power_thermal/gen_decoder.H> +#include <lib/dimm/nimbus_kind.H> -using fapi2::TARGET_TYPE_MCA; -using fapi2::TARGET_TYPE_MCS; -using fapi2::TARGET_TYPE_DIMM; -using fapi2::TARGET_TYPE_MCBIST; namespace mss { namespace power_thermal { -/// -/// @brief generates the 32 bit encoding for the power curve attributes -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful -/// @note populates iv_gen_keys -/// -fapi2::ReturnCode decoder::generate_encoding() +const std::vector< std::pair<uint8_t , uint8_t> > throttle_traits<mss::mc_type::NIMBUS>::DIMM_TYPE_MAP = { - //DIMM_SIZE - FAPI_TRY(( encode<DIMM_SIZE_START, DIMM_SIZE_LEN> - (iv_kind.iv_target, iv_kind.iv_size, DIMM_SIZE_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DIMM_SIZE", iv_kind.iv_size, c_str(iv_kind.iv_target) ); - - //DRAM_GEN - FAPI_TRY(( encode<DRAM_GEN_START, DRAM_GEN_LEN> - (iv_kind.iv_target, iv_kind.iv_dram_generation, DRAM_GEN_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DRAM_GEN", iv_kind.iv_dram_generation, c_str(iv_kind.iv_target) ); - - //DIMM_TYPE - FAPI_TRY(( encode<DIMM_TYPE_START, DIMM_TYPE_LEN> - (iv_kind.iv_target, iv_kind.iv_dimm_type, DIMM_TYPE_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DIMM_TYPE", iv_kind.iv_dimm_type, c_str(iv_kind.iv_target) ); - - //DRAM WIDTH - FAPI_TRY(( encode<DRAM_WIDTH_START, DRAM_WIDTH_LEN> - (iv_kind.iv_target, iv_kind.iv_dram_width, DRAM_WIDTH_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DRAM_WIDTH", iv_kind.iv_dram_width, c_str(iv_kind.iv_target) ); - - //DRAM DENSITY - FAPI_TRY(( encode<DRAM_DENSITY_START, DRAM_DENSITY_LEN> - (iv_kind.iv_target, iv_kind.iv_dram_density, DRAM_DENSITY_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DRAM_DENSITY", iv_kind.iv_dram_density, c_str(iv_kind.iv_target) ); - - //DRAM STACK TYPE - FAPI_TRY(( encode<DRAM_STACK_TYPE_START, DRAM_STACK_TYPE_LEN> - (iv_kind.iv_target, iv_kind.iv_stack_type, DRAM_STACK_TYPE_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DRAM_STACK_TYPE", iv_kind.iv_stack_type, c_str(iv_kind.iv_target) ); - - //DRAM MFG ID - FAPI_TRY(( encode<DRAM_MFGID_START, DRAM_MFGID_LEN> - (iv_kind.iv_target, iv_kind.iv_mfgid, DRAM_MFGID_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DRAM_MFG_ID", iv_kind.iv_mfgid, c_str(iv_kind.iv_target) ); - - //NUM DROPS PER PORT - FAPI_TRY(( encode<DIMMS_PER_PORT_START, DIMMS_PER_PORT_LEN> - (iv_kind.iv_target, iv_dimms_per_port, DIMMS_PORT_MAP, iv_gen_key)), - "Failed to generate power thermal encoding for %s val %d on target: %s", - "DIMMS_PER_PORT", iv_dimms_per_port, c_str(iv_kind.iv_target) ); - -fapi_try_exit: - return fapi2::current_err; -} -/// -///@brief a compare functor for the decoder::find_attr functions below -///@note AND's the input hash with the generated hash from the DIMM to see if they match -///@note Using an AND instead of == because not all DIMM configs have power slopes, so defaults are needed -/// -struct is_match -{ - /// - ///@brief functor constructor - ///@param[in] i_gen_key the class object's constructed hash for the installed dimm, to be compared with the attr array - /// - is_match(const uint32_t i_gen_key) : iv_gen_key(i_gen_key) {} - const fapi2::buffer<uint32_t> iv_gen_key; - - /// - ///@brief Boolean compare used for find_if function - /// - bool operator()(const uint64_t i_hash) - { - // l_this_hash is the first half of the i_hash's bits - uint32_t l_this_hash = i_hash >> 32; - return ((l_this_hash & iv_gen_key) == iv_gen_key); - } + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM, 0b00}, + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM, 0b01}, + {fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM, 0b10}, + {ANY_TYPE, 0b11} }; /// @@ -146,16 +68,21 @@ struct is_match /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful /// @note populates iv_vddr_slope, iv_total_slop /// -fapi2::ReturnCode decoder::find_slope (const std::vector<uint64_t>& i_slope) +template<> +fapi2::ReturnCode decoder<mss::mc_type::NIMBUS>::find_slope ( + const std::vector< const std::vector<uint64_t>* >& i_slope) { + using TT = throttle_traits<mss::mc_type::NIMBUS>; + + // For nimbus only one attribute is used to get slope (i_slope[0]) // Find iterator to matching key (if it exists) - const auto l_value_iterator = std::find_if(i_slope.begin(), - i_slope.end(), - is_match(iv_gen_key)); + const auto l_value_iterator = std::find_if((*i_slope[0]).begin(), + (*i_slope[0]).end(), + is_match<>(iv_gen_key)); //Should have matched with the default ATTR value at least //The last value should always be the default value - FAPI_ASSERT(l_value_iterator != i_slope.end(), + FAPI_ASSERT(l_value_iterator != (*i_slope[0]).end(), fapi2::MSS_NO_POWER_THERMAL_ATTR_FOUND() .set_GENERATED_KEY(iv_gen_key) .set_FUNCTION(SLOPE) @@ -184,8 +111,8 @@ fapi2::ReturnCode decoder::find_slope (const std::vector<uint64_t>& i_slope) { const fapi2::buffer<uint64_t> l_temp(*l_value_iterator); - l_temp.extractToRight<VDDR_START, VDDR_LENGTH>( iv_vddr_slope); - l_temp.extractToRight<TOTAL_START, TOTAL_LENGTH>(iv_total_slope); + l_temp.extractToRight<TT::VDDR_START, TT::VDDR_LENGTH>( iv_vddr_slope); + l_temp.extractToRight<TT::TOTAL_START, TT::TOTAL_LENGTH>(iv_total_slope); } fapi_try_exit: return fapi2::current_err; @@ -197,15 +124,19 @@ fapi_try_exit: /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful /// @note populates iv_vddr_intercept, iv_total_intercept /// -fapi2::ReturnCode decoder::find_intercept (const std::vector<uint64_t>& i_intercept) +template<> +fapi2::ReturnCode decoder<mss::mc_type::NIMBUS>::find_intercept ( + const std::vector< const std::vector<uint64_t>* >& i_intercept) { + using TT = throttle_traits<mss::mc_type::NIMBUS>; + // Find iterator to matching key (if it exists) - const auto l_value_iterator = std::find_if(i_intercept.begin(), - i_intercept.end(), - is_match(iv_gen_key)); + const auto l_value_iterator = std::find_if((*i_intercept[0]).begin(), + (*i_intercept[0]).end(), + is_match<>(iv_gen_key)); //Should have matched with the all default ATTR at least //The last value should always be the default value - FAPI_ASSERT(l_value_iterator != i_intercept.end(), + FAPI_ASSERT(l_value_iterator != (*i_intercept[0]).end(), fapi2::MSS_NO_POWER_THERMAL_ATTR_FOUND() .set_GENERATED_KEY(iv_gen_key) .set_FUNCTION(INTERCEPT) @@ -234,31 +165,36 @@ fapi2::ReturnCode decoder::find_intercept (const std::vector<uint64_t>& i_interc { const fapi2::buffer<uint64_t> l_temp(*l_value_iterator); - l_temp.extractToRight<VDDR_START, VDDR_LENGTH>( iv_vddr_intercept); - l_temp.extractToRight<TOTAL_START, TOTAL_LENGTH>(iv_total_intercept); + l_temp.extractToRight<TT::VDDR_START, TT::VDDR_LENGTH>( iv_vddr_intercept); + l_temp.extractToRight<TT::TOTAL_START, TT::TOTAL_LENGTH>(iv_total_intercept); } fapi_try_exit: return fapi2::current_err; } + /// /// @brief Finds a value from ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT and stores in iv variable /// @param[in] i_thermal_limits is a vector of the generated values from ATTR_MSS_MRW_THERMAL_POWER_LIMIT /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful -/// @note populates thermal_power_limit +/// @note populates thermal_power_limit. /// -fapi2::ReturnCode decoder::find_thermal_power_limit (const std::vector<uint64_t>& i_thermal_limits) +template<> +fapi2::ReturnCode decoder<mss::mc_type::NIMBUS>::find_thermal_power_limit ( + const std::vector< const std::vector<uint64_t>* >& i_thermal_limits) { + using TT = throttle_traits<mss::mc_type::NIMBUS>; + // Find iterator to matching key (if it exists) - const auto l_value_iterator = std::find_if(i_thermal_limits.begin(), - i_thermal_limits.end(), - is_match(iv_gen_key)); + const auto l_value_iterator = std::find_if((*i_thermal_limits[0]).begin(), + (*i_thermal_limits[0]).end(), + is_match<>(iv_gen_key)); fapi2::buffer<uint64_t> l_temp; //Should have matched with the all default ATTR at least //The last value should always be the default value - FAPI_ASSERT(l_value_iterator != i_thermal_limits.end(), + FAPI_ASSERT(l_value_iterator != (*i_thermal_limits[0]).end(), fapi2::MSS_NO_POWER_THERMAL_ATTR_FOUND() .set_GENERATED_KEY(iv_gen_key) .set_FUNCTION(POWER_LIMIT) @@ -287,11 +223,13 @@ fapi2::ReturnCode decoder::find_thermal_power_limit (const std::vector<uint64_t> { const fapi2::buffer<uint64_t> l_temp(*l_value_iterator); - l_temp.extractToRight<THERMAL_POWER_START, THERMAL_POWER_LENGTH>( iv_thermal_power_limit); + l_temp.extractToRight<TT::THERMAL_POWER_START, TT::THERMAL_POWER_LENGTH>( iv_thermal_power_limit); } fapi_try_exit: return fapi2::current_err; } + + /// /// @brief find the power curve attributes for each dimm on an MCS target /// @param[in] i_targets vector of MCS targets on which dimm attrs will be set @@ -317,13 +255,15 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& uint16_t o_total_int [PORTS_PER_MCS][MAX_DIMM_PER_PORT], uint32_t o_thermal_power [PORTS_PER_MCS][MAX_DIMM_PER_PORT]) { + using TT = throttle_traits<mss::mc_type::NIMBUS>; + for (const auto& l_dimm : find_targets <fapi2::TARGET_TYPE_DIMM> (i_mcs)) { - const auto l_mca_pos = mss::index (find_target<TARGET_TYPE_MCA>(l_dimm)); + const auto l_mca_pos = mss::index (find_target<fapi2::TARGET_TYPE_MCA>(l_dimm)); const auto l_dimm_pos = mss::index (l_dimm); - mss::dimm::kind l_kind (l_dimm); - mss::power_thermal::decoder l_decoder(l_kind); + mss::dimm::kind<> l_kind (l_dimm); + mss::power_thermal::decoder<> l_decoder(l_kind); FAPI_TRY( l_decoder.generate_encoding(), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); // The first entry into these arrays must be valid @@ -331,12 +271,13 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& if (i_slope.empty() || i_slope[0] == 0) { FAPI_INF("%s ATTR_MSS_MRW_PWR_SLOPE not found!!", mss::c_str(i_mcs)); - o_vddr_slope [l_mca_pos][l_dimm_pos] = default_power::VDDR_SLOPE; - o_total_slope [l_mca_pos][l_dimm_pos] = default_power::TOTAL_SLOPE; + o_vddr_slope [l_mca_pos][l_dimm_pos] = TT::VDDR_SLOPE; + o_total_slope [l_mca_pos][l_dimm_pos] = TT::TOTAL_SLOPE; } else { - FAPI_TRY( l_decoder.find_slope(i_slope), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); + const std::vector< const std::vector<uint64_t>* > l_slope {&i_slope}; + FAPI_TRY( l_decoder.find_slope(l_slope), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_slope; o_total_slope [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_slope; } @@ -344,12 +285,13 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& if (i_intercept.empty() || i_intercept[0] == 0) { FAPI_INF("%s ATTR_MSS_MRW_PWR_INTERCEPT not found!!", mss::c_str(i_mcs)); - o_total_int [l_mca_pos][l_dimm_pos] = default_power::TOTAL_INT; - o_vddr_int [l_mca_pos][l_dimm_pos] = default_power::VDDR_INT; + o_total_int [l_mca_pos][l_dimm_pos] = TT::TOTAL_INT; + o_vddr_int [l_mca_pos][l_dimm_pos] = TT::VDDR_INT; } else { - FAPI_TRY( l_decoder.find_intercept(i_intercept), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); + std::vector< const std::vector<uint64_t>* > l_intercept {&i_intercept}; + FAPI_TRY( l_decoder.find_intercept(l_intercept), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_vddr_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_vddr_intercept; o_total_int [l_mca_pos][l_dimm_pos] = l_decoder.iv_total_intercept; } @@ -357,11 +299,12 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& if (i_thermal_power_limit.empty() || i_thermal_power_limit[0] == 0) { FAPI_INF("%s ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT not found!!", mss::c_str(i_mcs)); - o_thermal_power [l_mca_pos][l_dimm_pos] = default_power::THERMAL_LIMIT; + o_thermal_power [l_mca_pos][l_dimm_pos] = TT::THERMAL_LIMIT; } else { - FAPI_TRY( l_decoder.find_thermal_power_limit(i_thermal_power_limit), + std::vector< const std::vector<uint64_t>* > l_thermal_power_limit {&i_thermal_power_limit}; + FAPI_TRY( l_decoder.find_thermal_power_limit(l_thermal_power_limit), "%s Error in get_power_attrs", mss::c_str(i_mcs) ); o_thermal_power [l_mca_pos][l_dimm_pos] = l_decoder.iv_thermal_power_limit; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H index ac1efcdbe..f6f9bf5ea 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/decoder.H @@ -36,222 +36,17 @@ #define _MSS_POWER_DECODER__ #include <fapi2.H> -#include <lib/dimm/kind.H> +#include <lib/shared/mss_const.H> +#include <lib/dimm/nimbus_kind.H> #include <generic/memory/lib/utils/count_dimm.H> +#include <generic/memory/lib/utils/power_thermal/gen_decoder.H> + namespace mss { namespace power_thermal { -enum size_of_attrs : size_t -{ - SIZE_OF_POWER_CURVES_ATTRS = 100, - SIZE_OF_THERMAL_ATTR = 10, -}; - -enum default_power -{ - //Values are the worst case defaults for power curves - //They are the default/ catch-all values from the power curve attributes - //Shouldn't be used if system is set up correctly and attributes are available - //This will throttle the DIMMs to ~76% dram data bus utilization - //(using the mrw regulator power limit of 1700 cW and thermal power limit here of 1940 cW). - VDDR_SLOPE = 0x41A, - VDDR_INT = 0x384, - TOTAL_SLOPE = 0x44C, - TOTAL_INT = 0x44C, - THERMAL_LIMIT = 0x794, -}; - -//Currently needs to be in sorted order for lookup to work -static const std::vector< std::pair<uint32_t , uint8_t> > DIMM_SIZE_MAP = -{ - {4, 0b0000}, - {8, 0b0001}, - {16, 0b0010}, - {32, 0b0011}, - {64, 0b0100}, - {128, 0b0101}, - {256, 0b0110}, - {512, 0b0111}, -}; - -static const std::vector< std::pair<uint8_t , uint8_t> > DIMM_TYPE_MAP = -{ - {fapi2::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, 0b00}, - {fapi2::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM, 0b01}, - {fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, 0b10}, -}; - -static const std::vector< std::pair<uint8_t , uint8_t> > DRAM_GEN_MAP = -{ - {fapi2::ENUM_ATTR_EFF_DRAM_GEN_EMPTY, 0b00}, - {fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR3, 0b01}, - {fapi2::ENUM_ATTR_EFF_DRAM_GEN_DDR4, 0b10} -}; - -static const std::vector <std::pair<uint8_t, uint8_t> > DRAM_WIDTH_MAP = -{ - {fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X4, 0b000}, - {fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8, 0b001}, - {fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X16, 0b010}, - {fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X32, 0b011} -}; - -static const std::vector< std::pair<uint8_t , uint8_t> > DRAM_DENSITY_MAP = -{ - {4, 0b000}, - {8, 0b001}, - {16, 0b010}, - {32, 0b011}, - {64, 0b100}, -}; - -static const std::vector <std::pair<uint8_t, uint8_t> > DRAM_STACK_TYPE_MAP = -{ - {fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_SDP, 0b00}, - {fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_DDP_QDP, 0b01}, - {fapi2::ENUM_ATTR_EFF_PRIM_STACK_TYPE_3DS, 0b10} -}; - -//Note, the first entries of the pairs need to be in sorted order!! -static const std::vector <std::pair<uint16_t, uint8_t> > DRAM_MFGID_MAP = -{ - //Kingston - {0x0198, 0b011}, - //A-data - {0x04CB, 0b101}, - //Micron - {0x802C, 0b000}, - //HYNIX - {0x80AD, 0b001}, - //SAMSUNG - {0x80CE, 0b010}, - //Innodisk - {0x86F1, 0b100}, -}; - -static const std::vector < std::pair< uint8_t, uint8_t> > DIMMS_PORT_MAP = -{ - //Num dimms per MCA, only 1 or 2 possible options. 0 is no-op - {1, 0b00}, - {2, 0b01} -}; - -//Bit positions for different section of the attribute -//first 32 bits are the encoding, second are for values -enum DECODE_BUFFER_POS -{ - ENCODING_START = 0, - ENCODING_LENGTH = 32, - VDDR_START = 32, - VDDR_LENGTH = 16, - TOTAL_START = 48, - TOTAL_LENGTH = 16, - THERMAL_POWER_START = 32, - THERMAL_POWER_LENGTH = 32, -}; - -//Positions and lengths of the encodings -enum ATTR_DECODE_INFO -{ - DIMM_SIZE_START = 0, - DIMM_SIZE_LEN = 4, - - DRAM_GEN_START = 4, - DRAM_GEN_LEN = 2, - - DIMM_TYPE_START = 6, - DIMM_TYPE_LEN = 2, - - DRAM_WIDTH_START = 8, - DRAM_WIDTH_LEN = 3, - - DRAM_DENSITY_START = 11, - DRAM_DENSITY_LEN = 3, - - DRAM_STACK_TYPE_START = 14, - DRAM_STACK_TYPE_LEN = 2, - - DRAM_MFGID_START = 16, - DRAM_MFGID_LEN = 3, - - DIMMS_PER_PORT_START = 19, - DIMMS_PER_PORT_LEN = 2, -}; - -/// -/// @class decoder -/// @brief Decodes the power curve and thermal power limit attributes for eff_config_thermal -/// -class decoder -{ - public: - - //IVs for all of the attributes per MCS - const mss::dimm::kind iv_kind; - - //Left in here rather than calculating during encode for testing - uint8_t iv_dimms_per_port; - - //Power thermal attributes, both total and vddr versions will be used in eff_config_thermal - uint16_t iv_vddr_slope; - uint16_t iv_vddr_intercept; - uint16_t iv_total_slope; - uint16_t iv_total_intercept; - - uint32_t iv_thermal_power_limit; - //Generated key, used to decode all three power curve attributes - fapi2::buffer<uint32_t> iv_gen_key; - - /// - /// @brief Constructor - /// @param[in] dimm::kind to call power thermal stuff on - /// - decoder( mss::dimm::kind& i_kind): - iv_kind(i_kind) - { - iv_dimms_per_port = mss::count_dimm (find_target<fapi2::TARGET_TYPE_MCA>(iv_kind.iv_target)); - }; - - // - // @brief Default destructor - // - ~decoder() = default; - - /// - /// @brief generates the 32 bit encoding for the power curve attributes - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful - /// @note populates iv_gen_key - /// - fapi2::ReturnCode generate_encoding (); - - /// - /// @brief Finds a value for the power curve slope attributes by matching the generated hashes - /// @param[in] i_array is a vector of the attribute values - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful - /// @note populates iv_vddr_slope, iv_total_slope - /// - fapi2::ReturnCode find_slope (const std::vector<uint64_t>& i_slope); - - /// - /// @brief Finds a value for power curve intercept attributes by matching the generated hashes - /// @param[in] i_array is a vector of the attribute values - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful - /// @note populates iv_vddr_intercept, iv_total_intercept - /// - fapi2::ReturnCode find_intercept (const std::vector<uint64_t>& i_intercept); - - /// - /// @brief Finds a value from ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT and stores in iv variable - /// @param[in] i_array is a vector of the attribute values - /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff the encoding was successful - /// @note populates iv_thermal_power_limit - /// - fapi2::ReturnCode find_thermal_power_limit (const std::vector<uint64_t>& i_thermal_limits); - -}; /// /// @brief find the power curve attributes for each dimm on an MCS target @@ -277,70 +72,6 @@ fapi2::ReturnCode get_power_attrs (const fapi2::Target<fapi2::TARGET_TYPE_MCS>& uint16_t o_total_slope [PORTS_PER_MCS][MAX_DIMM_PER_PORT], uint16_t o_total_int [PORTS_PER_MCS][MAX_DIMM_PER_PORT], uint32_t o_thermal_power [PORTS_PER_MCS][MAX_DIMM_PER_PORT]); -/// -/// @brief Encode the attribute into a bit encoding -/// @tparam[in] S *ATTR*_SIZE enum used for fapi2::buffer position -/// @tparam[in] L *ATTR*_LEN enum used for fapi2::buffer position -/// @tparam[in] OT fapi2::buffer of some integral type -/// @tparam[in] T integral type of key -/// @param[in] i_target the DIMM the encoding is for -/// @param[in] i_attr the attribute key being used for the encoding -/// @param[in] i_map a vector of pairs of the ATTR values and encodings for each value, sorted -/// @param[out] o_buf the fapi2::buffer where the encoding is going into -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff attribute is found in map lookup -/// -template<size_t S, size_t L, typename T, typename OT> -inline fapi2::ReturnCode encode ( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const T& i_attr, - const std::vector<std::pair<T, OT> >& i_map, - fapi2::buffer<uint32_t>& o_buf) -{ - //used to hold result from vector pair lookup - OT l_encoding = 0; - - //Failing out if we don't find an encoding. All suported types should be encoded above - FAPI_ASSERT( mss::find_value_from_key (i_map, i_attr, l_encoding), - fapi2::MSS_POWER_THERMAL_ENCODE_ERROR() - .set_ATTR(i_attr) - .set_DIMM_TARGET(i_target), - "Couldn't find encoding for power thermal encode for value: %x target: %s", i_attr, mss::c_str(i_target)); - o_buf.insertFromRight<S, L>(l_encoding); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Decode the attribute into a bit encoding -/// @tparam[in] S DRAM_GEN_SIZE enum used for fapi2::buffer position -/// @tparam[in] L DRAM_GEN_LEN enum used for fapi2::buffer position -/// @tparam[in] OT fapi2::buffer of some integral type -/// @tparam[in] T integral type of key -/// @param[in] i_target the DIMM the encoding is for -/// @param[in] i_map a vector of pairs of the ATTR values and encodings for each value -/// @param[in] i_buf the fapi2::buffer that has the encoding to parse -/// @param[out] o_attr the attribute value from the encoding is going -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff attribute is found in map lookup -/// -template<size_t S, size_t L, typename T, typename OT> -inline fapi2::ReturnCode decode ( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, - const std::vector<std::pair<T, OT> >& i_map, - fapi2::buffer<uint32_t>& i_buf, - T& o_attr ) -{ - //used to hold result from vector pair lookup - OT l_encoding = 0; - i_buf.extractToRight<S, L>(l_encoding); - - //Failing out if we don't find an decoding. All suported types should be encoded above - FAPI_ASSERT( mss::find_key_from_value (i_map, l_encoding, o_attr), - fapi2::MSS_POWER_THERMAL_DECODE_ERROR() - .set_ATTR(l_encoding) - .set_DIMM_TARGET(i_target), - "Couldn't find encoding for power thermal decode for target: %s", mss::c_str(i_target)); -fapi_try_exit: - return fapi2::current_err; -} } // power_thermal } // mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C index 82a5e2c6e..0ef22bddd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.C @@ -31,6 +31,8 @@ // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB + +#include <lib/shared/nimbus_defaults.H> //std lib #include<algorithm> // fapi2 @@ -41,687 +43,12 @@ #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/pos.H> -using fapi2::TARGET_TYPE_MCA; -using fapi2::TARGET_TYPE_MCS; -using fapi2::TARGET_TYPE_DIMM; -using fapi2::TARGET_TYPE_MCBIST; - namespace mss { namespace power_thermal { /// -/// @brief Constructor -/// @param[in] i_target MCS target to call power thermal stuff on -/// @param[out] o_rc, a return code which determines the success of the constructor -/// -throttle::throttle( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_mca, fapi2::ReturnCode& o_rc) : - iv_target(i_mca), - iv_databus_port_max(0), - iv_runtime_n_slot(0), - iv_runtime_n_port(0), - iv_n_slot(0), - iv_n_port(0), - iv_port_power_limit(0), - iv_calc_port_maxpower(0) -{ - //holder for watt_target to add up for port - uint32_t l_dimm_power_limits [MAX_DIMM_PER_PORT] = {}; - - FAPI_TRY( mrw_max_dram_databus_util(iv_databus_port_max), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift(iv_power_uplift), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( mrw_dimm_power_curve_percent_uplift_idle(iv_power_uplift_idle), "%s Error in throttle ctor", - mss::c_str(i_mca) ); - FAPI_TRY( dimm_thermal_limit( iv_target, iv_dimm_thermal_limit), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( total_pwr_intercept( iv_target, iv_pwr_int), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( total_pwr_slope( iv_target, iv_pwr_slope), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( runtime_mem_throttled_n_commands_per_slot(iv_target, iv_runtime_n_slot ), "%s Error in throttle ctor", - mss::c_str(i_mca) ); - FAPI_TRY( runtime_mem_throttled_n_commands_per_port(iv_target, iv_runtime_n_port ), "%s Error in throttle ctor", - mss::c_str(i_mca) ); - FAPI_TRY( mem_watt_target( iv_target, l_dimm_power_limits), "%s Error in throttle ctor", mss::c_str(i_mca) ); - FAPI_TRY( mrw_mem_m_dram_clocks(iv_m_clocks), "%s Error in throttle ctor", mss::c_str(i_mca) ); - - //Port power limit = sum of dimm power limits - for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) - { - iv_port_power_limit += l_dimm_power_limits[mss::index(l_dimm)]; - } - - FAPI_INF("Setting up throttle for target %s, Values are: max databus is %d, uplifts are %d %d, runtime throttles are %d %d", - mss::c_str(iv_target), - iv_databus_port_max, - iv_power_uplift, - iv_power_uplift_idle, - iv_runtime_n_slot, - iv_runtime_n_port); - - FAPI_INF("The dimm power limit for dimm0 is %d, dimm1 is %d, port power limit is %d, dram clocks are %d, dimm power curve slopes are %d %d,", - l_dimm_power_limits[0], - l_dimm_power_limits[1], - iv_port_power_limit, - iv_m_clocks, - iv_pwr_slope[0], - iv_pwr_slope[1]); - - FAPI_INF("DIMM power curve intercepts are %d %d, DIMM power thermal limits are %d %d", - iv_pwr_int[0], - iv_pwr_int[1], - iv_dimm_thermal_limit[0], - iv_dimm_thermal_limit[1]); - - FAPI_ASSERT( (iv_databus_port_max != 0), - fapi2::MSS_NO_DATABUS_UTILIZATION() - .set_PORT_DATABUS_UTIL(iv_databus_port_max) - .set_DIMM_COUNT(mss::count_dimm(iv_target)), - "Failed to get max databus utilization for target %s", - mss::c_str(iv_target)); - - FAPI_ASSERT( (iv_port_power_limit != 0), - fapi2::MSS_NO_PORT_POWER_LIMIT() - .set_COUNT_DIMMS( mss::count_dimm(iv_target)) - .set_PORT_POWER_LIMIT( iv_port_power_limit), - "Error calculating port_power_limit on target %s with %d DIMMs installed", - mss::c_str(iv_target), - iv_port_power_limit); - - //Checking to make sure all of the attributes are valid - for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) - { - const auto l_pos = mss::index(l_dimm); - FAPI_ASSERT( (iv_pwr_int[l_pos] != 0), - fapi2::MSS_POWER_INTERCEPT_NOT_SET(), - "The attribute ATTR_MSS_TOTAL_PWR_INTERCEPT equals 0 for %s", - mss::c_str(l_dimm)); - - FAPI_ASSERT( (iv_pwr_slope[l_pos] != 0), - fapi2::MSS_POWER_SLOPE_NOT_SET(), - "The attribute ATTR_MSS_TOTAL_PWR_SLOPE equals 0 for %s", - mss::c_str(l_dimm)); - } - -fapi_try_exit: - o_rc = fapi2::current_err; - return; -} - -/// -/// @brief Set ATTR_MSS_CHANNEL_PAIR_MAXPOWER, ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT and _PER_PORT -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Called in p9_mss_bulk_pwr_throttles -/// @note determines the throttle levels based off of the port's power curve, -/// @note the _per_slot throttles are set to the _per_port values -/// @note throttles are all equalized and set to the worst case value -/// -fapi2::ReturnCode throttle::power_regulator_throttles () -{ - double l_port_power_calc_idle = 0; - double l_port_power_calc_max = 0; - uint32_t l_port_power_slope = 0; - uint32_t l_port_power_int = 0; - double l_calc_util_port = 0; - double l_databus_dimm_max[MAX_DIMM_PER_PORT] = {}; - double l_calc_databus_port_idle[MAX_DIMM_PER_PORT] = {IDLE_UTIL, IDLE_UTIL}; - - FAPI_INF("Starting power regulator throttles"); - - //Decide utilization for each dimm based off of dimm count and power slopes - FAPI_TRY( calc_databus(iv_databus_port_max, l_databus_dimm_max), - "Failed to calculate each DIMMs' percentage of dram databus utilization for target %s, max port databus is %d", - mss::c_str(iv_target), - iv_databus_port_max); - - //Use the dimm utilizations and dimm power slopes to calculate port min and max power - FAPI_TRY( calc_port_power(l_calc_databus_port_idle, - l_databus_dimm_max, - l_port_power_calc_idle, - l_port_power_calc_max), - "Failed to calculate the max and idle power for port %s", - mss::c_str(iv_target)); - - FAPI_INF("POWER throttles: %s max port power is %f", mss::c_str(iv_target), l_port_power_calc_max); - - //Calculate the power curve slope and intercept using the port's min and max power values - FAPI_TRY(calc_power_curve(l_port_power_calc_idle, - l_port_power_calc_max, - l_port_power_slope, - l_port_power_int), - "Failed to calculate the power curve for port %s, calculated port power max is %d, idle is %d", - mss::c_str(iv_target), - l_port_power_calc_max, - l_port_power_calc_idle); - - FAPI_INF("%s POWER Port power limit is %d", mss::c_str(iv_target), iv_port_power_limit); - //Calculate the port's utilization to get under watt target using the port's calculated slopes - calc_util_usage(l_port_power_slope, - l_port_power_int, - iv_port_power_limit, - l_calc_util_port); - - FAPI_INF("%s POWER calc util port is %f", mss::c_str(iv_target), l_calc_util_port); - - //Calculate the new slot values and the max power value for the port - FAPI_TRY( calc_slots_and_power( l_calc_util_port), - "%s Error calculating the final throttles and power values for target with passed in port utilization %d", - mss::c_str(iv_target), - l_calc_util_port); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief set iv_n_port, iv_n_slot, iv_calc_port_maxpower -/// @param[in] i_util_port pass in the calculated port databus utilization -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// -fapi2::ReturnCode throttle::calc_slots_and_power (const double i_util_port) -{ - //Calculate the Port N throttles - iv_n_port = power_thermal::throttled_cmds(i_util_port, iv_m_clocks); - - //Set iv_n_slot to the lower value between the slot runtime and iv_n_port - iv_n_slot = (iv_runtime_n_slot != 0) ? std::min (iv_n_port, iv_runtime_n_slot) : iv_n_port; - - //Choose the lowest value of the runtime and the calculated - iv_n_port = (iv_runtime_n_port != 0) ? std::min (iv_n_port, iv_runtime_n_port) : iv_n_port; - - //Use the throttle value to calculate the power that gets to exactly that value - FAPI_TRY( calc_power_from_n(iv_n_slot, iv_n_port, iv_calc_port_maxpower)); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Set ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT and PER_PORT -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Called in p9_mss_bulk_pwr_throttles -/// @note Sets the throttle levels based off of the dimm's thermal limits -/// @note both DIMM's on a port are set to the same throttle level -/// -fapi2::ReturnCode throttle::thermal_throttles () -{ - double l_dimm_power_idle [MAX_DIMM_PER_PORT] = {}; - double l_dimm_power_max [MAX_DIMM_PER_PORT] = {}; - uint32_t l_dimm_power_slope [MAX_DIMM_PER_PORT] = {}; - uint32_t l_dimm_power_int [MAX_DIMM_PER_PORT] = {}; - double l_calc_util [MAX_DIMM_PER_PORT] = {}; - const auto l_count = count_dimm (iv_target); - - //Calculate the dimm power range for each dimm at max utilization for each - calc_dimm_power(power_thermal::IDLE_UTIL, - iv_databus_port_max, - l_dimm_power_idle, - l_dimm_power_max); - - //Let's calculate the N throttle for each DIMM - for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) - { - uint16_t l_temp_n_slot = 0; - uint8_t l_pos = mss::index(l_dimm); - //Calculate the power curve taking the thermal limit into account - FAPI_TRY( calc_power_curve(l_dimm_power_idle[l_pos], - l_dimm_power_max[l_pos], - l_dimm_power_slope[l_pos], - l_dimm_power_int[l_pos]), - "Failed to calculate the power curve for dimm %s, calculated dimm power curve slope is %d, intercept %d", - mss::c_str(l_dimm), - l_dimm_power_slope[l_pos], - l_dimm_power_int[l_pos]); - - //Calculate the databus utilization at the calculated power curve - calc_util_usage(l_dimm_power_slope[l_pos], - l_dimm_power_int[l_pos], - iv_dimm_thermal_limit[l_pos], - l_calc_util[l_pos]); - - FAPI_INF("THERMAL throttles: %s dram databus utilization is %f", mss::c_str(l_dimm), l_calc_util[l_pos]); - - l_temp_n_slot = power_thermal::throttled_cmds (l_calc_util[l_pos], iv_m_clocks); - - //Set to the min between the two value - //If iv_n_slot == 0 (so uninitialized), set it to the calculated slot value - //The l_n_slot value can't be equal to 0 because there's a dimm installed - if ((l_temp_n_slot < iv_n_slot) || (iv_n_slot == 0)) - { - iv_n_slot = l_temp_n_slot; - } - } - - //Set to lowest value between calculated and runtime - FAPI_INF("THERMAL throttles: runtime slot is %d, calc n slot is %d", iv_runtime_n_slot, iv_n_slot); - //Taking the min of the SLOT * (# of dimms on the port) and the iv_runtime_port throttle value - //Thermal throttling happens after the POWER calculations. the iv_runtime_n_port value shouldn't be set to 0 - iv_n_port = std::min(iv_runtime_n_port, static_cast<uint16_t>(iv_n_slot * l_count)); - iv_n_port = (iv_n_port == 0) ? MIN_THROTTLE : iv_n_port; - - iv_n_slot = std::min(iv_n_slot, iv_runtime_n_slot); - iv_n_slot = (iv_n_slot == 0) ? MIN_THROTTLE : iv_n_slot; - - //Now time to get and set iv_calc_port_max from the calculated N throttle - FAPI_TRY( calc_power_from_n(iv_n_slot, iv_n_port, iv_calc_port_maxpower), - "Failed to calculate the final max port maxpower. Slot throttle value is %d, port value is %d", - iv_n_slot, - iv_n_port); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - FAPI_ERR("Error calculating mss::power_thermal::thermal_throttles()"); - return fapi2::current_err; -} - -/// -/// @brief Calculates the min and max power usage for a port based off of power curves and utilizations -/// @param[in] i_idle_util the utilization of the databus in idle mode (0% most likely) -/// @param[in] i_max_util the utilization of the dimm at maximum possible percentage (mrw or calculated) -/// @param[out] o_port_power_idle max value of port power in cW -/// @param[out] o_port_power_max max value of port power in cW -/// @return fapi2::FAPI2_RC_SUCCESS iff the method was a success -/// @note Called twice in p9_mss_bulk_pwr_throttles -/// @note uses dimm power curves from class variables -/// -fapi2::ReturnCode throttle::calc_port_power(const double i_idle_util [MAX_DIMM_PER_PORT], - const double i_max_util [MAX_DIMM_PER_PORT], - double& o_port_power_idle, - double& o_port_power_max) const -{ - //Playing it safe - o_port_power_idle = 0; - o_port_power_max = 0; - - //Calculate the port power curve info by summing the dimms on the port - for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) - { - const auto l_pos = mss::index(l_dimm); - //Printing as decimals because HB messes up floats - FAPI_INF("%s max dram databus for DIMM in pos %d is %d, databus for idle is %d", - mss::c_str(iv_target), - l_pos, - static_cast<uint64_t>( i_max_util[l_pos]), - static_cast<uint64_t>( i_idle_util[l_pos]) ); - //Sum up the dim's power to calculate the port power curve - o_port_power_idle += calc_power(i_idle_util[l_pos], l_pos); - o_port_power_max += calc_power(i_max_util[l_pos], l_pos); - } - - //Raise the powers by the uplift percent - calc_power_uplift(iv_power_uplift_idle, o_port_power_idle); - calc_power_uplift(iv_power_uplift, o_port_power_max); - - FAPI_ASSERT( (o_port_power_max > 0), - fapi2::MSS_NO_PORT_POWER() - .set_COUNT_DIMMS(mss::count_dimm(iv_target)) - .set_MAX_UTILIZATION_DIMM_0(i_max_util[0]) - .set_MAX_UTILIZATION_DIMM_1(i_max_util[1]), - "No Port Power limit was calculated for %s, %d DIMMs installed, utilizations: DIMM 0 %d, DIMM 1 %d", - mss::c_str(iv_target), - mss::count_dimm(iv_target), - i_max_util[0], - i_max_util[1]); - - //FAPI_ASSERTs don't set the current err to good - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Calculates max and min power usages based off of DIMM power curves -/// @param[in] i_databus_idle idle databus utilization (either calculated or mrw) -/// @param[in] i_databus_max max databus utilization (either calculated or mrw) -/// @param[out] o_dimm_power_idle array of dimm power in cW -/// @param[out] o_dimm_power_max array of dimm power in cW -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK -/// @note Called in p9_mss_bulk_pwr_throttles -/// @note used for the thermal throttles -/// -void throttle::calc_dimm_power(const double i_databus_idle, - const double i_databus_max, - double o_dimm_power_idle [MAX_DIMM_PER_PORT], - double o_dimm_power_max [MAX_DIMM_PER_PORT]) const -{ - for ( const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target) ) - { - const uint8_t l_pos = mss::index(l_dimm); - o_dimm_power_idle[l_pos] = calc_power(i_databus_idle, l_pos); - o_dimm_power_max[l_pos] = calc_power(i_databus_max, l_pos); - - //Raise the powers by the uplift percent - - calc_power_uplift(iv_power_uplift_idle, o_dimm_power_idle[l_pos]); - calc_power_uplift(iv_power_uplift, o_dimm_power_max[l_pos]); - - FAPI_INF("Calc_dimm_power: dimm (%d) power max is %f, %f for dimm slope of %d, intercept of %d", - l_pos, - o_dimm_power_max[l_pos], - o_dimm_power_max[l_pos], - iv_pwr_slope[l_pos], - iv_pwr_int[l_pos]); - } -} - -/// -/// @brief Calculate the port power curve in order to calculate the port utilization -/// @param[in] i_power_idle double of the port's power consumption at idle -/// @param[in] i_power_max double of the port's power consumption at max utilization -/// @param[out] o_slope -/// @param[out] o_int -/// @note Called in p9_mss_bulk_pwr_throttles -/// @note Port power curve needed to calculate the port utilization -/// -fapi2::ReturnCode throttle::calc_power_curve(const double i_power_idle, - const double i_power_max, - uint32_t& o_slope, - uint32_t& o_int) const -{ - const double l_divisor = ((static_cast<double>(iv_databus_port_max) / UTIL_CONVERSION) - IDLE_UTIL); - FAPI_ASSERT ((l_divisor > 0), - fapi2::MSS_CALC_POWER_CURVE_DIVIDE_BY_ZERO() - .set_PORT_DATABUS_UTIL(iv_databus_port_max) - .set_UTIL_CONVERSION(UTIL_CONVERSION) - .set_IDLE_UTIL(IDLE_UTIL) - .set_RESULT(l_divisor), - "Calculated zero for the divisor in calc_power_curve on target %s", - mss::c_str(iv_target) ); - - o_slope = (i_power_max - i_power_idle) / l_divisor; - o_int = i_power_idle - (o_slope * IDLE_UTIL); - FAPI_INF("Calc_power_curve: power idle is %f, max is %f, slope is %d, int is %d", - i_power_idle, - i_power_max, - o_slope, - o_int); - return fapi2::FAPI2_RC_SUCCESS; - -fapi_try_exit: - FAPI_INF("Error calculating mss::power_thermal::calc_power_curve"); - return fapi2::current_err; - -} - -/// -/// @brief Calculate the databus utilization given the power curve -/// @param[in] i_slope -/// @param[in] i_int -/// @param[in] i_power_limit either the port_power_limit or the dimm thermal power limit -/// @param[out] o_port_util the port's databus utilization -/// @note Called in p9_mss_bulk_pwr_throttles -/// @note Chooses worst case between the maximum allowed databus utilization and the calculated value -/// -void throttle::calc_util_usage(const uint32_t i_slope, - const uint32_t i_int, - const uint32_t i_power_limit, - double& o_util) const -{ - o_util = ((static_cast<double>(i_power_limit) - i_int) / i_slope ) * UTIL_CONVERSION; - - //Cast to uint32 for edge case where it has decimals - o_util = (static_cast<uint32_t>(o_util) < iv_databus_port_max) ? static_cast<uint32_t>(o_util) : iv_databus_port_max; - - // Check for the minimum threshnold and update if need be - if(o_util < MIN_UTIL) - { - FAPI_INF("Calculated utilization (%lu) is less than the minimum utilization: %lu. Setting to minimum value", o_util, - MIN_UTIL); - o_util = MIN_UTIL; - } -} - -/// -/// @brief calculated the output power estimate from the calculated N throttle -/// @param[in] i_n_slot the throttle per slot in terms of N commands -/// @param[in] i_n_port the throttle per port in terms of N commands -/// @param[out] o_power the calculated power -/// @return fapi2::ReturnCode iff it was a success -/// -fapi2::ReturnCode throttle::calc_power_from_n (const uint16_t i_n_slot, - const uint16_t i_n_port, - uint32_t& o_power) const -{ - double l_calc_util_port = 0; - double l_calc_util_slot = 0; - double l_calc_databus_port_max[MAX_DIMM_PER_PORT] = {}; - double l_calc_databus_port_idle[MAX_DIMM_PER_PORT] = {}; - double l_port_power_max = 0; - double l_port_power_idle = 0; - - FAPI_TRY( calc_util_from_throttles(i_n_slot, iv_m_clocks, l_calc_util_slot), - "%s Error calculating utilization from slot throttle %d and mem clocks %d", - mss::c_str(iv_target), - i_n_slot, - iv_m_clocks); - FAPI_TRY( calc_util_from_throttles(i_n_port, iv_m_clocks, l_calc_util_port), - "%s Error calculating utilization from port throttle %d and mem clocks %d", - mss::c_str(iv_target), - i_n_port, - iv_m_clocks); - - //Determine the utilization for each DIMM that will maximize the port power - FAPI_TRY( calc_split_util(l_calc_util_slot, l_calc_util_port, l_calc_databus_port_max), - "Error splitting the utilization for target %s with slot utilizatio %d and port util %d", - mss::c_str(iv_target), - l_calc_util_slot, - l_calc_util_port); - - FAPI_TRY( calc_port_power(l_calc_databus_port_idle, - l_calc_databus_port_max, - l_port_power_idle, - l_port_power_max), - "Error calculating the port power value for %s. Slot value is %d, port value is %d", - mss::c_str(iv_target), - i_n_slot, - i_n_port); - - o_power = power_thermal::round_up (l_port_power_max); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Converts the port maximum databus to a dimm level based on powerslopes and dimms installed -/// @param[in] i_databus_port_max max databus utilization for the port (either calculated or mrw) -/// @param[out] o_databus_dimm_max array of dimm utilization values -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK -/// @note Called in p9_mss_bulk_pwr_throttles -/// @used to calculate the port power based off of DIMM power curves -/// -fapi2::ReturnCode throttle::calc_databus (const double i_databus_port_max, - double o_databus_dimm_max [MAX_DIMM_PER_PORT]) -{ - uint8_t l_count_dimms = count_dimm(iv_target); - - //No work for no dimms - if (l_count_dimms == 0) - { - return fapi2::FAPI2_RC_SUCCESS; - } - - for (const auto& l_dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(iv_target)) - { - //Left early if count_dimms == 0 - o_databus_dimm_max[mss::index(l_dimm)] = i_databus_port_max / l_count_dimms; - } - - //If the power slopes aren't equal, set the dimm with the highest power slope - //Should be correct even if only one DIMM is installed - if (iv_pwr_slope[0] != iv_pwr_slope[1]) - { - o_databus_dimm_max[0] = (iv_pwr_slope[0] > iv_pwr_slope[1]) ? i_databus_port_max : 0; - o_databus_dimm_max[1] = (iv_pwr_slope[1] > iv_pwr_slope[0]) ? i_databus_port_max : 0; - } - - //Make sure both are not 0 - FAPI_ASSERT ( (o_databus_dimm_max[0] != 0) || (o_databus_dimm_max[1] != 0), - fapi2::MSS_NO_DATABUS_UTILIZATION() - .set_PORT_DATABUS_UTIL(i_databus_port_max) - .set_DIMM_COUNT(l_count_dimms), - "Failed to calculated databus utilization for target %s", - mss::c_str(iv_target)); - - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Converts the port and slot util to a dimm level based on powerslopes and number of dimms installed -/// @param[in] i_util_slot databus utilization for the slot -/// @param[in] i_util_port databus utilization for the port -/// @param[out] o_util_dimm_max array of dimm utilization values -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK -/// @note determines worst case utilization per dimms, takes into account port and combine slot throttles -/// @note used in calculating the port power, not for calculating the slot and port utilization -/// -fapi2::ReturnCode throttle::calc_split_util( - const double i_util_slot, - const double i_util_port, - double o_util_dimm_max [MAX_DIMM_PER_PORT]) const -{ - uint8_t l_count_dimms = count_dimm (iv_target); - //The total utilization to be used is limited by either what the port can allow or what the dimms can use - FAPI_ASSERT( (i_util_slot <= i_util_port), - fapi2::MSS_SLOT_UTIL_EXCEEDS_PORT() - .set_SLOT_UTIL(i_util_slot) - .set_PORT_UTIL(i_util_port), - "The slot utilization (%f) exceeds the port's utilization (%f)", - i_util_slot, - i_util_port); - - if (l_count_dimms == 0) - { - return fapi2::FAPI2_RC_SUCCESS; - } - - //assumptions slot <= port, l_count_dimms <=2 - else if (i_util_slot * l_count_dimms > i_util_port) - { - FAPI_INF("In mss::power_thermal::calc_split i_util_slot is %f, i_util_port is %f, l_count_dimms is %d", - i_util_slot, - i_util_port, - l_count_dimms); - const uint8_t l_high_pos = (iv_pwr_slope[0] >= iv_pwr_slope[1]) ? 0 : 1; - - //Highest power_slope gets the higher utilization - o_util_dimm_max[l_high_pos] = std::min(i_util_slot, i_util_port); - //Set the other dimm to the left over utilization (i_util_port - i_util_slot) - o_util_dimm_max[(!l_high_pos)] = (l_count_dimms == 2) ? (i_util_port - o_util_dimm_max[l_high_pos]) : 0; - - FAPI_INF("Split utilization for target %s, DIMM in %d gets %f, DIMM in %d gets %f", - mss::c_str(iv_target), - l_high_pos, - o_util_dimm_max[l_high_pos], - !l_high_pos, - o_util_dimm_max[!l_high_pos]); - } - - else - { - //If only 1 dimm, i_util_port == i_util_slot - //If 2 dimms, 2*i_util_slot <= i_util_pot - //Either way, limit utilization by the slot value - for (const auto& l_dimm : mss::find_targets<TARGET_TYPE_DIMM>(iv_target)) - { - const size_t l_pos = mss::index(l_dimm); - o_util_dimm_max[l_pos] = i_util_slot; - } - } - - //make sure both are not 0 - FAPI_ASSERT ( (o_util_dimm_max[0] != 0) || (o_util_dimm_max[1] != 0), - fapi2::MSS_NO_DATABUS_UTILIZATION() - .set_PORT_DATABUS_UTIL(i_util_port) - .set_DIMM_COUNT(mss::count_dimm(iv_target)), - "Failed to calculated util utilization for target %s", - mss::c_str(iv_target)); -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Perform thermal calculations as part of the effective configuration -/// @param[in] i_target the MCS target in which the runtime throttles will be reset -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode restore_runtime_throttles( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ) -{ - uint16_t l_run_throttles [MAX_DIMM_PER_PORT] = {}; - uint32_t l_max_databus = 0; - uint32_t l_throttle_m_clocks = {}; - - FAPI_TRY( mrw_mem_m_dram_clocks(l_throttle_m_clocks) ); - FAPI_TRY( mrw_max_dram_databus_util(l_max_databus) ); - - //Set runtime throttles to unthrottled value, using max dram utilization and M throttle - //Do I need to check to see if any DIMMS configured on the port? - for (const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(i_target)) - { - const auto l_pos = mss::index(l_mca); - - if (mss::count_dimm (l_mca) != 0) - { - l_run_throttles[l_pos] = mss::power_thermal::throttled_cmds (l_max_databus, l_throttle_m_clocks); - } - } - - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT, i_target, l_run_throttles) ); - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT, i_target, l_run_throttles) ); - -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Update the runtime throttles to the worst case of the general throttle values and the runtime values -/// @param[in] i_target the MCS target in which the runtime throttles will be set -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode update_runtime_throttles( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets ) -{ - for (const auto& l_mcs : i_targets) - { - if (mss::count_dimm(l_mcs) == 0) - { - continue; - } - - uint16_t l_run_slot [PORTS_PER_MCS] = {}; - uint16_t l_run_port [PORTS_PER_MCS] = {}; - uint16_t l_calc_slot [PORTS_PER_MCS] = {}; - uint16_t l_calc_port [PORTS_PER_MCS] = {}; - - FAPI_TRY(runtime_mem_throttled_n_commands_per_slot(l_mcs, l_run_slot)); - FAPI_TRY(runtime_mem_throttled_n_commands_per_port(l_mcs, l_run_port)); - FAPI_TRY(mem_throttled_n_commands_per_slot(l_mcs, l_calc_slot)); - FAPI_TRY(mem_throttled_n_commands_per_port(l_mcs, l_calc_port)); - - for (const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(l_mcs)) - { - const auto l_pos = mss::index(l_mca); - //Choose the worst case between runtime and calculated throttles - //Have to make sure the calc_slot isn't equal to 0 though - l_run_slot[l_pos] = (l_calc_slot[l_pos] != 0) ? - std::min(l_run_slot[l_pos], l_calc_slot[l_pos]) : l_run_slot[l_pos]; - l_run_port[l_pos] = (l_calc_port[l_pos] != 0) ? - std::min(l_run_port[l_pos], l_calc_port[l_pos]) : l_run_port[l_pos]; - - FAPI_INF("New runtime throttles for %s for slot are %d, port are %d", - mss::c_str(l_mca), - l_run_slot[l_pos], - l_run_port[l_pos]); - } - - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT, l_mcs, l_run_port) ); - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_SLOT, l_mcs, l_run_slot) ); - } - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief set ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS and ATTR_MSS_MEM_WATT_TARGET /// @param[in] i_targets vector of mcs targets all on the same vddr domain /// @return FAPI2_RC_SUCCESS iff it was a success @@ -785,149 +112,5 @@ fapi_try_exit: return fapi2::current_err; } -/// -/// @brief Equalize the throttles and estimated power at those throttle levels -/// @param[in] i_targets vector of MCS targets all on the same VDDR domain -/// @param[in] i_throttle_type denotes if this was done for POWER (VMEM) or THERMAL (VMEM+VPP) throttles -/// @param[out] o_exceeded_power vector of MCA targets where the estimated power exceeded the maximum allowed -/// @return FAPI2_RC_SUCCESS iff ok -/// @note sets the throttles and power to the worst case -/// Called by p9_mss_bulk_pwr_throttles and by p9_mss_utils_to_throttle (so by IPL or by OCC) -/// -fapi2::ReturnCode equalize_throttles (const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets, - const throttle_type i_throttle_type, - std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> >& o_exceeded_power) -{ - o_exceeded_power.clear(); - - //Set to max values so every compare will change to min value - uint16_t l_min_slot = ~(0); - uint16_t l_min_port = ~(0); - - //Loop through all of the MCS targets to find the worst case throttle value (lowest) for the slot and port - for (const auto& l_mcs : i_targets) - { - uint16_t l_calc_slot [mss::PORTS_PER_MCS] = {}; - uint16_t l_calc_port [mss::PORTS_PER_MCS] = {}; - uint16_t l_run_slot [mss::PORTS_PER_MCS] = {}; - uint16_t l_run_port [mss::PORTS_PER_MCS] = {}; - - FAPI_TRY(mem_throttled_n_commands_per_slot(l_mcs, l_calc_slot)); - FAPI_TRY(mem_throttled_n_commands_per_port(l_mcs, l_calc_port)); - FAPI_TRY(runtime_mem_throttled_n_commands_per_slot(l_mcs, l_run_slot)); - FAPI_TRY(runtime_mem_throttled_n_commands_per_port(l_mcs, l_run_port)); - - for (const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(l_mcs)) - { - if (mss::count_dimm(l_mca) == 0) - { - continue; - } - - const auto l_pos = mss::index(l_mca); - //Find the smaller of the three values (calculated slot, runtime slot, and min slot) - l_min_slot = (l_calc_slot[l_pos] != 0) ? std::min( std::min (l_calc_slot[l_pos], l_run_slot[l_pos]), - l_min_slot) : l_min_slot; - l_min_port = (l_calc_port[l_pos] != 0) ? std::min( std::min( l_calc_port[l_pos], l_run_port[l_pos]), - l_min_port) : l_min_port; - } - } - - FAPI_INF("Calculated min slot is %d, min port is %d for the system", l_min_slot, l_min_port); - - //Now set every port to have those values - { - for (const auto& l_mcs : i_targets) - { - uint16_t l_fin_slot [mss::PORTS_PER_MCS] = {}; - uint16_t l_fin_port [mss::PORTS_PER_MCS] = {}; - uint32_t l_fin_power [mss::PORTS_PER_MCS] = {}; - - for (const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(l_mcs)) - { - if (mss::count_dimm(l_mca) == 0) - { - continue; - } - - const auto l_pos = mss::index(l_mca); - // Declaring above to avoid fapi2 jump - uint64_t l_power_limit = 0; - - l_fin_slot[l_pos] = (mss::count_dimm(l_mca)) ? l_min_slot : 0; - l_fin_port[l_pos] = (mss::count_dimm(l_mca)) ? l_min_port : 0; - - //Need to create throttle object for each mca in order to get dimm configuration and power curves - //To calculate the slot/port utilization and total port power consumption - fapi2::ReturnCode l_rc; - - const auto l_dummy = mss::power_thermal::throttle(l_mca, l_rc); - FAPI_TRY(l_rc, "Failed creating a throttle object in equalize_throttles"); - - FAPI_TRY( l_dummy.calc_power_from_n(l_fin_slot[l_pos], l_fin_port[l_pos], l_fin_power[l_pos]), - "Failed calculating the power value for throttles: slot %d, port %d for target %s", - l_fin_slot[l_pos], - l_fin_port[l_pos], - mss::c_str(l_mca)); - - //Only calculate the power for ports that have dimms - l_fin_power[l_pos] = (mss::count_dimm(l_mca) != 0 ) ? l_fin_power[l_pos] : 0; - - // You may ask why this is not a variable within the throttle struct - // It's because POWER throttling is on a per port basis while the THERMAL throttle is per dimm - // Didn't feel like adding a variable just for this check - l_power_limit = (i_throttle_type == throttle_type::POWER) ? - l_dummy.iv_port_power_limit : (l_dummy.iv_dimm_thermal_limit[0] + l_dummy.iv_dimm_thermal_limit[1]); - - FAPI_INF("Calculated power is %d, limit is %d", l_fin_power[l_pos], l_power_limit); - - //If there's an error with calculating port power, the wrong watt target was passed in - //Returns an error but doesn't deconfigure anything. Calling function can log if it wants to - //Called by OCC and by p9_mss_eff_config_thermal, thus different ways for error handling - //Continue setting throttles to prevent a possible throttle == 0 - //The error will be the last bad port found - if (l_fin_power[l_pos] > l_power_limit) - { - //Need this because of pos traits and templating stuff - uint64_t l_fail = mss::fapi_pos(l_mca); - //Set the failing port. OCC just needs one failing port, doesn't need all of them - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_MEM_PORT_POS_OF_FAIL_THROTTLE, - fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), - l_fail) ); - - FAPI_ASSERT_NOEXIT( false, - fapi2::MSS_CALC_PORT_POWER_EXCEEDS_MAX() - .set_CALCULATED_PORT_POWER(l_fin_power[l_pos]) - .set_MAX_POWER_ALLOWED(l_power_limit) - .set_PORT_POS(mss::pos(l_mca)) - .set_MCA_TARGET(l_mca), - "Error calculating the final port power value for target %s, calculated power is %d, max value can be %d", - mss::c_str(l_mca), - l_fin_power[l_pos], - l_power_limit); - - o_exceeded_power.push_back(l_mca); - } - - FAPI_INF("%s Final throttles values for slot %d, for port %d, power value %d", - mss::c_str(l_mca), - l_fin_port[l_pos], - l_fin_slot[l_pos], - l_fin_power[l_pos]); - } - - //Even if there's an error, still calculate and set the throttles. - //OCC will set to safemode if there's an error - //Better to set the throttles than leave them 0, and potentially brick the memory - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT, l_mcs, l_fin_port) ); - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, l_mcs, l_fin_slot) ); - FAPI_TRY( FAPI_ATTR_SET( fapi2::ATTR_MSS_PORT_MAXPOWER, l_mcs, l_fin_power) ); - } - } - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - FAPI_ERR("Error equalizing memory throttles"); - return fapi2::current_err; -} }//namespace power_thermal }//namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H index 189583cfa..bfc978492 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,332 +39,24 @@ #include <fapi2.H> #include <lib/shared/mss_const.H> #include <lib/mss_attribute_accessors.H> +#include <lib/power_thermal/accessor_wrapper.H> +#include <lib/power_thermal/throttle_traits.H> +#include <lib/dimm/nimbus_kind.H> +#include <generic/memory/lib/utils/power_thermal/gen_throttle.H> namespace mss { namespace power_thermal { /// -/// @brief throttle constants used in the power_thermal functions -/// -enum throttle_const : size_t -{ - /// Dram data bus utilization is bus utilization / 4 - DRAM_BUS_UTILS = 4, - - /// 10000 to convert to and from c% - UTIL_CONVERSION = 10000, - - /// Conversion to percentage - PERCENT_CONVERSION = 100, - - /// MIN_UTIL is in c% - MIN_UTIL = 2500, - - /// IDLE_UTIL is in c% - IDLE_UTIL = 0, - - /// Minimum throttle allowed for the port and or slot. If we set to 0, we brick the port - MIN_THROTTLE = 1, -}; - -/// -/// @class throttle -/// @brief Determine power_thermal throttles for memory -/// -class throttle -{ - private: - /// - /// @brief Calculate the power (cW) of inputs and the power curve - /// @tparam T - /// @param[in] i_util the databus utilization that the power will be based on - /// @param[in] l_pos the dimm position for the power value being calculated. - /// @return Integral type T - /// - template<typename T> - inline T calc_power (const T i_util, const size_t i_pos) const - { - return ((i_util / UTIL_CONVERSION) * iv_pwr_slope[i_pos]) + iv_pwr_int[i_pos]; - } - - /// - /// @brief Raise the o_value by the percent passed in - /// @param[in] i_uplift the percent the o_Value should be raised by - /// @param[out] o_value the value that will be modified - /// - inline void calc_power_uplift (const uint8_t i_uplift, double& o_value) const - { - o_value *= (1 + (static_cast<double>(i_uplift) / PERCENT_CONVERSION)); - } - - public: - const fapi2::Target<fapi2::TARGET_TYPE_MCA>& iv_target; - - uint32_t iv_databus_port_max; - - uint8_t iv_power_uplift_idle; - uint8_t iv_power_uplift; - - uint16_t iv_runtime_n_slot; - uint16_t iv_runtime_n_port; - uint32_t iv_m_clocks; - uint32_t iv_dimm_thermal_limit[MAX_DIMM_PER_PORT] = {}; - uint16_t iv_pwr_slope[MAX_DIMM_PER_PORT] = {}; - uint16_t iv_pwr_int[MAX_DIMM_PER_PORT] = {}; - uint16_t iv_n_slot; - uint16_t iv_n_port; - uint32_t iv_port_power_limit; - uint32_t iv_calc_port_maxpower; - - //default ctor deleted - throttle() = delete; - - /// - /// @brief Constructor - /// @param[in] i_target MCA target to call power thermal stuff on - /// @param[out] o_rc fapi2::ReturnCode fapi2::FAPI2_RC_SUCCESS iff ctor was successful - /// - throttle( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_mca, fapi2::ReturnCode& o_rc); - - // - // @brief Destructor - // - ~throttle() = default; - - /// - /// @brief Calculates the min and max power usage for a port - /// @param[in] i_idle_util the utilization of the databus in idle mode - /// @param[in] i_max_util the utilization of the port at maximum possible (mrw or calculated) - /// @param[out] o_port_power_idle max value of port power in cW - /// @param[out] o_port_power_max max value of port power in cW - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK - /// @note Called twice in p9_mss_bulk_pwr_throttles - /// - fapi2::ReturnCode calc_port_power( const double i_idle_util [MAX_DIMM_PER_PORT], - const double i_max_util [MAX_DIMM_PER_PORT], - double& o_port_power_idle, - double& o_port_power_max) const; - /// - /// @brief Calculates max and min power usages based off of DIMM power curves - /// @param[in] i_databus_port_max max databus utilization for the port (either calculated or mrw) - /// @param[in] i_port_power_calc_idle double of the port's power consumption at idle - /// @param[out] o_dimm_power_idle array of dimm power in cW - /// @param[out] o_dimm_power_max array of dimm power in cW - /// @note Called in p9_mss_bulk_pwr_throttles - /// @note used for the thermal throttles - /// - void calc_dimm_power(const double i_databus_idle, - const double i_databus_max, - double o_dimm_power_idle [MAX_DIMM_PER_PORT], - double o_dimm_power_max [MAX_DIMM_PER_PORT]) const; - - /// - /// @brief Calculate the power curve in order to calculate databus utilization - /// @param[in] i_power_idle double of the port's power consumption at idle - /// @param[in] i_power_max double of the port's power consumption at max utilization - /// @param[out] o_power_slope - /// @param[out] o_power_int - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK - /// @note Called in p9_mss_bulk_pwr_throttles - /// @note Power curve needed to calculate the utilization - /// - fapi2::ReturnCode calc_power_curve(const double i_power_idle, - const double i_power_max, - uint32_t& o_power_slope, - uint32_t& o_power_int) const; - /// - /// @brief Calculate the databus utilization given the power curve - /// @param[in] i_slope - /// @param[in] i_int - /// @param[in] i_power_limit either iv_port_power_limit or thermal_power_limit depending on throttle type - /// @param[out] o_port_util the port's databus utilization - /// @note Called in p9_mss_bulk_pwr_throttles - /// @note Chooses worst case between the maximum allowed databus utilization and the calculated value - /// - void calc_util_usage(const uint32_t i_slope, - const uint32_t i_int, - const uint32_t i_power_limit, - double& o_util) const; - /// - /// @brief set iv_n_port, iv_n_slot, iv_calc_port_maxpower - /// @param[in] i_util_port pass in the calculated port databus utilization - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK - /// - fapi2::ReturnCode calc_slots_and_power (const double i_util_port); - - /// - /// @brief calculated the output power estimate from the calculated N throttle - /// @param[in] i_n_slot the N throttle per slot - /// @param[in] i_n_port the N throttle per port - /// @param[out] o_power the calculated power - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK - /// - fapi2::ReturnCode calc_power_from_n (const uint16_t i_n_slot, const uint16_t i_n_port, uint32_t& o_power) const; - - /// - /// @brief Converts the port maximum databus util to a dimm level based on powerslopes and dimms installed - /// @param[in] i_databus_port_max max databus utilization for the port (either calculated or mrw) - /// @param[out] o_databus_dimm_max array of dimm utilization values - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK - /// @note Called in p9_mss_bulk_pwr_throttles - /// @used to calculate the port power based off of DIMM power curves - /// - fapi2::ReturnCode calc_databus( const double i_databus_port_max, - double o_databus_dimm_max [MAX_DIMM_PER_PORT]); - /// - /// @brief Converts the port and slot util to a dimm level based on powerslopes and number of dimms installed - /// @param[in] i_util_slot databus utilization for the slot - /// @param[in] i_util_port databus utilization for the port - /// @param[out] o_util_dimm_max array of dimm utilization values - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff the split is OK - /// @note determines worst case utilization per dimms, takes into account port and combine slot throttles - /// - fapi2::ReturnCode calc_split_util( - const double i_util_slot, - const double i_util_port, - double o_util_dimm_max [MAX_DIMM_PER_PORT]) const; - - - /// - /// @brief Calculate ATTR_MSS_CHANNEL_PAIR_MAXPOWER and ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK - /// @note Called in p9_mss_bulk_pwr_throttles - /// @note determines the throttle levels based off of the port's power curve, max databus utilization, - /// and memwat target. - /// @note currently sets the slot and port throttles to the same value - /// - fapi2::ReturnCode power_regulator_throttles (); - - /// - /// @brief Set ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, - /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK - /// @note Called in p9_mss_bulk_pwr_throttles - /// @note Sets the throttle levels based off of the dimm's thermal limits - /// @note both DIMM's on a port are set to the same throttle level - /// - fapi2::ReturnCode thermal_throttles (); -}; - -/// -/// @brief Calculate N (address operations) allowed within a window of M DRAM clocks -/// @param[in] i_databus_util databus utilization percentage (e.g. 5% = 5) -/// @param[in] i_num_dram_clocks window of M DRAM clocks -/// @return number of throttled commands allowed -/// @note Uses N/M Throttling. -/// Equation: N = (DRAM data bus utilization * M) / (4 * 10000) -/// -inline uint32_t throttled_cmds(const uint32_t i_databus_util, const uint32_t i_num_dram_clocks) -{ - constexpr uint64_t l_divisor = DRAM_BUS_UTILS * UTIL_CONVERSION; - const uint64_t l_dividend = i_databus_util * i_num_dram_clocks; - const uint64_t l_result = l_dividend / l_divisor; - - //Make sure N is not equal to 0, or we brick the dram until reboot - return ((l_result == 0) ? 1 : l_result); -} - -/// -/// @brief Calculate the port databus utilization based off of N throttles and M dram clocks -/// @tparam T output type -/// @param[in] i_n_throttles N (address operations) allowed within a window of M DRAM clocks -/// @param[in] i_num_dram_clocks window of M DRAM clocks -/// @param[out] o_calc_util -/// @return FAPI2_RC_SUCCESS iff method was a success -/// @note Uses N/M Throttling. -/// @note DRAM databus utilization = N * 4 * 10000 / M -/// -template<typename T> -fapi2::ReturnCode calc_util_from_throttles(const uint16_t i_n_throttles, - const uint32_t i_num_dram_clocks, - T& o_calc_util) -{ - constexpr uint32_t l_multiplier = DRAM_BUS_UTILS * UTIL_CONVERSION; - FAPI_ASSERT( (i_num_dram_clocks != 0), - fapi2::MSS_M_DRAM_CLOCKS_EQUALS_ZERO(), - "ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS was not set and equals zero"); - - o_calc_util = (static_cast<double>(i_n_throttles) * l_multiplier) / i_num_dram_clocks; - - // Best way to check for overflow if o_calc_util can be a double? - // If o_calc_util overflows, the value inside will be below the expected outcome - // So compare o_calc_util with the calculated value, but store calculated value in largest storage - // Compare ">=" because o_calc_util can be a double, and so we can't compare just equality due to truncation - FAPI_ASSERT( o_calc_util >= static_cast<uint64_t>((static_cast<double>(i_n_throttles) * l_multiplier) / - i_num_dram_clocks), - fapi2::MSS_OUTPUT_OVERFLOW_CALC_UTIL() - .set_RESULT((static_cast<double>(i_n_throttles) * l_multiplier) / i_num_dram_clocks), - "Overflow of output variable in calc_util_from_throttles throttles: %d, multiplier %d, dram_clocks %d", - i_n_throttles, - l_multiplier, - i_num_dram_clocks); - - // Check for the minimum - if(o_calc_util < MIN_UTIL) - { - FAPI_INF("Calculated utilization (%f) is less than the minimum utilization: %lu. Setting to minimum value", - o_calc_util, MIN_UTIL); - o_calc_util = MIN_UTIL; - } - - FAPI_INF("In calc_util_from_throttles, calculated %f for output utilization", o_calc_util); - return fapi2::FAPI2_RC_SUCCESS; -fapi_try_exit: - return fapi2::current_err; -} - -/// -/// @brief Determines if the double has decimal digits and adds 1 and rounds if true -/// @param[in] i_val the double to be rounded up if trialing digits -/// @return the input value rounded up to the next whole digit -/// @note Called in p9_mss_bulk_pwr_throttles -/// -inline uint32_t round_up(double i_val) -{ - //convert to uint to truncate decimals and convert back to double for comparison - uint32_t temp = uint32_t (i_val); - - //if not equal, lost something from truncating, so add 1 - temp += (temp == i_val) ? 0 : 1; - - //Truncate final value - return temp; -} - -/// -/// @brief Perform thermal calculations as part of the effective configuration -/// @param[in] i_target the MCS target in which the runtime throttles will be reset -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode restore_runtime_throttles( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target ); - -/// -/// @brief Update the runtime throttles to the worst case of the general throttle values and the runtime values -/// @param[in] i_target the MCS target in which the runtime throttles will be set -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode update_runtime_throttles(const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets); - -/// /// @brief set ATTR_MSS_RUNTIME_MEM_M_DRAM_CLOCKS and ATTR_MSS_MEM_WATT_TARGET /// @param[in] i_targets vector of mcs targets all on the same vddr domain /// @return FAPI2_RC_SUCCESS iff it was a success /// fapi2::ReturnCode set_runtime_m_and_watt_limit( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets ); -/// -/// @brief Equalize the throttles and estimated power at those throttle levels -/// @param[in] i_targets vector of MCS targets all on the same VDDR domain -/// @param[in] i_throttle_type denotes if this was done for POWER (VMEM) or THERMAL (VMEM+VPP) throttles -/// @param[out] o_exceeded_power vector of MCA targets where the estimated power exceeded the maximum allowed -/// @return FAPI2_RC_SUCCESS iff ok -/// @note sets the throttles and power to the worst case -/// -fapi2::ReturnCode equalize_throttles (const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets, - const throttle_type i_throttle_type, - std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> >& o_exceeded_power); - }//power_thermal + }// mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle_traits.H b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle_traits.H index da277d6fb..15407e3a4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle_traits.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/power_thermal/throttle_traits.H @@ -22,3 +22,125 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ +/// +/// @file p9_mss_utils_to_throttle.H +/// @brief throttle API +/// + +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB + +#ifndef _MSS_POWER_THROTTLE_TRAITS_ +#define _MSS_POWER_THROTTLE_TRAITS_ + +#include <fapi2.H> +#include <generic/memory/lib/utils/power_thermal/gen_throttle_traits.H> + +namespace mss +{ +namespace power_thermal +{ + +/// +/// @class Traits and policy class for throttle code - specialization for the NIMBUS mc type +/// +template<> +class throttle_traits<mss::mc_type::NIMBUS> +{ + public: + ////////////////////////////////////////////////////////////// + // Target types + ////////////////////////////////////////////////////////////// + static constexpr fapi2::TargetType MC_TARGET_TYPE = fapi2::TARGET_TYPE_MCS; + static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MCA; + + // MIN_UTIL is in c% + static const uint64_t MIN_UTIL = 2500; + // IDLE_UTIL is in c% + static const uint64_t IDLE_UTIL = 0; + // Minimum throttle allowed for the port and or slot. If we set to 0, we brick the port + static const uint64_t MIN_THROTTLE = 1; + + enum size_of_attrs : size_t + { + SIZE_OF_POWER_CURVES_ATTRS = 100, + SIZE_OF_THERMAL_ATTR = 10, + }; + + enum default_power + { + //Values are the worst case defaults for power curves + //They are the default/ catch-all values from the power curve attributes + //Shouldn't be used if system is set up correctly and attributes are available + //This will throttle the DIMMs to ~76% dram data bus utilization + //(using the mrw regulator power limit of 1700 cW and thermal power limit here of 1940 cW). + VDDR_SLOPE = 0x41A, + VDDR_INT = 0x384, + TOTAL_SLOPE = 0x44C, + TOTAL_INT = 0x44C, + THERMAL_LIMIT = 0x794, + }; + + enum + { + PORTS_PER_MC = 2, + DIMMS_PER_PORT = 2, + }; + + //Bit positions for different section of the attribute + //first 32 bits are the encoding, second are for values + enum DECODE_BUFFER_POS + { + ENCODING_START = 0, + ENCODING_LENGTH = 32, + VDDR_START = 32, + VDDR_LENGTH = 16, + TOTAL_START = 48, + TOTAL_LENGTH = 16, + THERMAL_POWER_START = 32, + THERMAL_POWER_LENGTH = 32, + }; + + //Positions and lengths of the encodings + enum ATTR_DECODE_INFO + { + DIMM_SIZE_START = 0, + DIMM_SIZE_LEN = 4, + + DRAM_GEN_START = 4, + DRAM_GEN_LEN = 2, + + DIMM_TYPE_START = 6, + DIMM_TYPE_LEN = 2, + + DRAM_WIDTH_START = 8, + DRAM_WIDTH_LEN = 3, + + DRAM_DENSITY_START = 11, + DRAM_DENSITY_LEN = 3, + + DRAM_STACK_TYPE_START = 14, + DRAM_STACK_TYPE_LEN = 2, + + DRAM_MFGID_START = 16, + DRAM_MFGID_LEN = 3, + + DIMMS_PER_PORT_START = 19, + DIMMS_PER_PORT_LEN = 2, + + // Invalid for Nimbus but compile will fail without them + DIMM_MODULE_HEIGHT_START = 0, + DIMM_MODULE_HEIGHT_LEN = 1, + }; + + + // Definition is in chip folder + static const std::vector< std::pair<uint8_t , uint8_t> > DIMM_TYPE_MAP; +}; +}//power_thermal +}// mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H index bf84c1662..679459d74 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/mss_const.H @@ -51,7 +51,6 @@ enum sizes MC_PER_MODULE = 2, MCBIST_PER_MC = 1, MAX_DIMM_PER_PORT = 2, - MAX_RANK_PER_DIMM = 4, PORTS_PER_MODULE = MC_PER_MODULE * MCS_PER_MC * PORTS_PER_MCS, BITS_PER_DP = 16, NIBBLES_PER_DP = BITS_PER_DP / BITS_PER_NIBBLE, @@ -64,7 +63,7 @@ enum sizes RANK_MID_POINT = 4, ///< Which rank number indicates the switch to the other DIMM MAX_NUM_IMP = 4, ///< number of impedances valid per slew type MAX_NUM_CAL_SLEW_RATES = 4, ///< 3V/ns, 4V/ns, 5V/ns, 6V/n - MAX_DQ_BITS = 72, /// TODO RTC:157753 This is Nimbus specific. Should be attribute/trait of processor. + MAX_DQ_BITS = 72, MAX_DQ_NIBBLES = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For ISDIMMs are 18 DQ nibbles for DQ 72 bits MAX_DRAMS_X8 = MAX_DQ_BITS / BITS_PER_BYTE, ///< For x8's there are 9 DRAM for 72 bits MAX_DRAMS_X4 = MAX_DQ_BITS / BITS_PER_NIBBLE, ///< For x4's there are 18 DRAM for 72 bits @@ -75,10 +74,6 @@ enum sizes ROW_REPAIR_BYTE_COUNT = 4, ///< Elements in a ROW_REPAIR_DATA attribute array. - BYTES_PER_GB = 1000000000, ///< Multiplier to go from GB to B - T_PER_MT = 1000000, ///< Multiplier to go from MT/s to T/s - CYCLES_PER_CMD = 4, ///< Best case cycles per MCBIST command - // All need to be attributes? - BRS WR_LVL_BIG_STEP = 0b0111, WR_LVL_SMALL_STEP = 0b000, @@ -99,27 +94,11 @@ enum sizes // Largest size a VPD keyword can be VPD_KEYWORD_MAX = 255, - - // Number of double words in... - NUM_DW_IN_128B = 16, - NUM_DW_IN_64B = 8, - - // MCBIST polling constant for actual HW - // The specific value here is not important, only that it is very large to avoid polling timeouts, - // but not to avoid any actual hardware timeouts - // Note: ~0 is not used as that would cause MCBIST to never timeout even if the hardware is in an infinite loop - // You can't get greater than ~0, so you'd never timeout - // TODO RTC:166340 - Clean up MCBIST polling - OVERLY_LARGE_NUMBER_OF_POLLS = 5000000000000, }; enum times { // Not *exactly* a time but go with i - BG_SCRUB_IN_HOURS = 12, - - CMD_TIMEBASE = 8192, ///< Represents the timebase multiplier for the MCBIST inter cmd gap - MAX_CMD_GAP = 4095, ///< Represents the maximum (non-multplied) time for MCBIST inter cmd gap FULL_DLL_CAL_DELAY = 37382, ///< Full DLL calibration (in ddphy_nck cycles) }; @@ -154,26 +133,9 @@ enum ffdc_function_codes SOFT_POST_PACKAGE_REPAIR = 27, EFF_BC07 = 28, - // Used in fw_mark_store.H for MSS_INVALID_RANK_PASSED - FWMS_READ = 30, - FWMS_WRITE = 31, - - // Used in hw_mark_store.H for MSS_INVALID_RANK_PASSED - HWMS_READ = 40, - HWMS_WRITE = 41, - - // MSS_INVALID_INDEX_PASSED - SYMBOL_COUNT_READ = 50, - SYMBOL_COUNT_WRITE = 51, - // Used in rank.H MAP_RP_PRIMARY_TO_INIT_CAL = 60, - // Power thermal functions - SLOPE = 70, - INTERCEPT = 71, - POWER_LIMIT = 72, - // PDA function codes PDA_WR_VREF_LATCH_CONTAINER = 80, PDA_WR_VREF_LATCH_VECTOR = 81, @@ -198,6 +160,7 @@ enum ffdc_function_codes DRAM_TO_RP_REG = 101, // eff_dimm.C + RAW_CARD_FACTORY = 115, PRIMARY_STACK_TYPE = 116, // CW engine information @@ -212,9 +175,6 @@ enum ffdc_function_codes // LR training function DWL_CALL_OUT = 130, MREP_CALL_OUT = 131, - - - CCS_INST_CONFIGURE_RANK = 132, }; // Static consts describing the bits used in the cal_step_enable attribute @@ -276,44 +236,6 @@ enum voltages : uint64_t }; -enum port_select -{ - // Port selects for MCBIST and CCS - // Select for 1 port - PORT0 = 0b1000, - PORT1 = 0b0100, - PORT2 = 0b0010, - PORT3 = 0b0001, - // Selects for 2 port combinations - PORT01 = PORT0 | PORT1, - PORT02 = PORT0 | PORT2, - PORT03 = PORT0 | PORT3, - PORT12 = PORT1 | PORT2, - PORT13 = PORT1 | PORT3, - PORT23 = PORT2 | PORT3, - // Selects for 3 port combinations - PORT012 = PORT0 | PORT1 | PORT2, - PORT013 = PORT0 | PORT1 | PORT3, - PORT023 = PORT0 | PORT2 | PORT3, - PORT123 = PORT1 | PORT2 | PORT3, - // Select all - PORT0123 = PORT0 | PORT1 | PORT2 | PORT3, - // Maybe a better name for disabling all - PORT_NONE = 0b0000, -}; - -enum dimm_select -{ - // Dimm selects for MCBIST and CCS - // Select for 1 dimm - DIMM0 = 0b10, - DIMM1 = 0b01, - // Selects for 2 dimm combinations - DIMM01 = DIMM0 | DIMM1, - // Maybe a better name for disabling all - DIMM_NONE = 0b00, -}; - // Possible values for power domains in MBARPC0Q enum min_max_domains : uint64_t { @@ -324,179 +246,5 @@ enum min_max_domains : uint64_t MAX1_MIN0 = 0b100, }; -namespace mcbist -{ - -enum broadcast_timebase -{ - // Number of 1024 2:1 cycle timebases to wait starting MCBIST - // for SRQs to get synced for broadcast mode - TB_COUNT_2 = 0b0000001, - TB_COUNT_4 = 0b0000011, - TB_COUNT_8 = 0b0000111, - TB_COUNT_16 = 0b0001111, - TB_COUNT_32 = 0b0011111, - TB_COUNT_64 = 0b0111111, - TB_COUNT_128 = 0b1111111, -}; - -enum rmw_address -{ - // 32B block addresses into the maint portion of the rmw buffer - DW0 = 0b111110000, - DW1 = 0b111110001, - DW2 = 0b111110010, - DW3 = 0b111110011, - DW4 = 0b111110100, - DW5 = 0b111110101, - DW6 = 0b111110110, - DW7 = 0b111110111, - DW8 = 0b111111000, - DW9 = 0b111111001, - DWA = 0b111111010, - DWB = 0b111111011, - DWC = 0b111111100, - DWD = 0b111111101, - DWE = 0b111111110, - DWF = 0b111111111, -}; - -enum data_rotate_mode -{ - // MCBIST data rotate modes refer to register MCBDRCR bits 0:3 - ROTATE_0_BITS = 0b0000, - ROTATE_1_BITS = 0b0001, - ROTATE_2_BITS = 0b0010, - ROTATE_3_BITS = 0b0011, - ROTATE_4_BITS = 0b0100, - ROTATE_5_BITS = 0b0101, - ROTATE_6_BITS = 0b0110, - ROTATE_7_BITS = 0b0111, - ROTATE_8_BITS = 0b1000, - ROTATE_9_BITS = 0b1001, - ROTATE_10_BITS = 0b1010, - ROTATE_11_BITS = 0b1011, - ROTATE_12_BITS = 0b1100, - ROTATE_13_BITS = 0b1101, - ROTATE_14_BITS = 0b1110, - ROTATE_15_BITS = 0b1111, -}; - -enum data_seed_mode -{ - // MCBIST data seed modes refer to register MCBDRCR bits 21:22 - ALL_UNIQUE = 0b00, - REPEAT_SEED_0 = 0b01, - REPEAT_SEED_1 = 0b10, - REPEAT_SEED_2 = 0b11, -}; - -enum data_mode -{ - // MCBIST test data modes - FIXED_DATA_MODE = 0b000, - RAND_FWD_MODE = 0b001, - RAND_REV_MODE = 0b010, - RAND_FWD_MAINT = 0b011, - RAND_REV_MAINT = 0b100, - DATA_EQ_ADDR = 0b101, - ROTATE_LEFT_MODE = 0b110, - ROTATE_RIGHT_MODE = 0b111, -}; - -// 0:3 Operation Type -enum op_type -{ - WRITE = 0b0000, // fast, with no concurrent traffic - READ = 0b0001, // fast, with no concurrent traffic - READ_WRITE = 0b0010, - WRITE_READ = 0b0011, - READ_WRITE_READ = 0b0100, - READ_WRITE_WRITE = 0b0101, - RAND_SEQ = 0b0110, - READ_READ_WRITE = 0b1000, - SCRUB_RRWR = 0b1001, - STEER_RW = 0b1010, - ALTER = 0b1011, // (W) - DISPLAY = 0b1100, // (R, slow) - CCS_EXECUTE = 0b1111, - - // if bits 9:11 (Data Mode bits) = 000 (bits 4:8 used to specify which subtest to go to) - // Refresh only cmd if bits 9:11 (Data Mode bits) /= 000 - GOTO_SUBTEST_N = 0b0111, -}; - - -enum test_type -{ - USER_MODE = 0, - CENSHMOO = 1, - SUREFAIL = 2, - MEMWRITE = 3, - MEMREAD = 4, - CBR_REFRESH = 5, - MCBIST_SHORT = 6, - SHORT_SEQ = 7, - DELTA_I = 8, - DELTA_I_LOOP = 9, - SHORT_RAND = 10, - LONG1 = 11, - BUS_TAT = 12, - SIMPLE_FIX = 13, - SIMPLE_RAND = 14, - SIMPLE_RAND_2W = 15, - SIMPLE_RAND_FIXD = 16, - SIMPLE_RA_RD_WR = 17, - SIMPLE_RA_RD_R = 18, - SIMPLE_RA_FD_R = 19, - SIMPLE_RA_FD_R_INF = 20, - SIMPLE_SA_FD_R = 21, - SIMPLE_RA_FD_W = 22, - INFINITE = 23, - WR_ONLY = 24, - W_ONLY = 25, - R_ONLY = 26, - W_ONLY_RAND = 27, - R_ONLY_RAND = 28, - R_ONLY_MULTI = 29, - SHORT = 30, - SIMPLE_RAND_BARI = 31, - W_R_INFINITE = 32, - W_R_RAND_INFINITE = 33, - R_INFINITE1 = 34, - R_INFINITE_RF = 35, - MARCH = 36, - SIMPLE_FIX_RF = 37, - SHMOO_STRESS = 38, - SIMPLE_RAND_RA = 39, - SIMPLE_FIX_RA = 40, - SIMPLE_FIX_RF_RA = 41, - TEST_RR = 42, - TEST_RF = 43, - W_ONLY_INFINITE_RAND = 44, - MCB_2D_CUP_SEQ = 45, - MCB_2D_CUP_RAND = 46, - SHMOO_STRESS_INFINITE = 47, - HYNIX_1_COL = 48, - RMWFIX = 49, - RMWFIX_I = 50, - W_INFINITE = 51, - R_INFINITE = 52, -}; - - -} // namespace mcbist - -enum class shmoo_edge : std::size_t -{ - LEFT, - RIGHT -}; - -enum visual_max : uint64_t -{ - MAX_VISUAL_VALUE = 9999 -}; - } // namespace mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/shared/nimbus_defaults.H b/src/import/chips/p9/procedures/hwp/memory/lib/shared/nimbus_defaults.H index 5863d063f..0a10d2522 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/shared/nimbus_defaults.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/shared/nimbus_defaults.H @@ -36,12 +36,15 @@ #ifndef _MSS_NIMBUS_DEFAULTS_H_ #define _MSS_NIMBUS_DEFAULTS_H_ +#include <fapi2.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> namespace mss { constexpr mss::mc_type DEFAULT_MC_TYPE = mss::mc_type::NIMBUS; +constexpr fapi2::TargetType DEFAULT_MC_TARGET = fapi2::TARGET_TYPE_MCBIST; +constexpr fapi2::TargetType DEFAULT_MEM_PORT_TARGET = fapi2::TARGET_TYPE_MCA; } // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C index be8343c71..2d6aef4c8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/spd/spd_factory.C @@ -53,7 +53,7 @@ #include <generic/memory/lib/spd/spd_checker.H> #include <generic/memory/lib/spd/spd_utils.H> #include <lib/utils/mss_nimbus_conversions.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/eff_config/timing.H> #include <lib/shared/mss_const.H> @@ -131,7 +131,8 @@ fapi2::ReturnCode raw_card_factory(const fapi2::Target<TARGET_TYPE_DIMM>& i_targ FAPI_ASSERT( false, fapi2::MSS_INVALID_DIMM_TYPE() .set_DIMM_TYPE(l_dimm_type) - .set_DIMM_TARGET(i_target), + .set_DIMM_TARGET(i_target) + .set_FUNCTION(mss::ffdc_function_codes::RAW_CARD_FACTORY), "Recieved invalid dimm type: %d for %s", l_dimm_type, mss::spd::c_str(i_target) ); break; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/find_magic.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find_magic.H new file mode 100644 index 000000000..3c8a385c4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/find_magic.H @@ -0,0 +1,140 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/utils/find_magic.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef _MSS_FIND_WITH_MAGIC_H +#define _MSS_FIND_WITH_MAGIC_H + +#include <fapi2.H> +#include <vector> +#include <generic/memory/lib/utils/pos.H> +#include <generic/memory/lib/utils/c_str.H> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ + +/// +/// @brief find the union of functionl targets and any magic targets +/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. +/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. +/// This function returns all functional targets and includes the magic target whether or not +/// it is truly functional. +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return a vector of M targets. +/// +template< fapi2::TargetType M, fapi2::TargetType T > +inline std::vector< fapi2::Target<M> > find_targets_with_magic( const fapi2::Target<T>& i_target); + +/// +/// @brief find a set of magic elements based on a fapi2 target +/// @note The PHY has a logic block which is only contained in the 0th PHY in the controller. +/// This makes the 0th PHY 'magic' in that it needs to always be present if not functional. +/// This function returns all magic targets whether or not it is truly functional. +/// It does not include other functional or present targets. +/// @tparam M the target type to be returned +/// @tparam T the fapi2 target type of the argument +/// @param[in] i_target the fapi2 target T +/// @return a vector of M targets. +/// +template< fapi2::TargetType M, fapi2::TargetType T > +inline std::vector< fapi2::Target<M> > find_magic_targets( const fapi2::Target<T>& i_target); + +/// +/// @brief find the magic MCA connected to an MCBIST +/// @param[in] i_target the fapi2::Target MCBIST +/// @return a vector of fapi2::TARGET_TYPE_MCA +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > +find_magic_targets(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) +{ + // The magic port is in position 0, relative to the MCBIST + constexpr uint64_t RELATIVE_MAGIC_POS = 0; + + // This is only one magic MCA on every MCBIST, so we only return a vector of one + std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>> l_magic_ports; + + // Get all the present MCA children and find the target with the relative position of 0 + for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(fapi2::TARGET_STATE_PRESENT)) + { + if (mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(p) == RELATIVE_MAGIC_POS) + { + l_magic_ports.push_back(p); + } + } + + // We don't care if the vector is empty. We don't know what the caller will do with this + // and they might not care if there is no magic port either ... + return l_magic_ports; +} + +/// +/// @brief find the union of functionl targets and any magic targets +/// @param[in] i_target the fapi2::Target MCBIST +/// @return a vector of i2::Target<fapi2::TARGET_TYPE_MCA> +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > +find_targets_with_magic( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) +{ + // We need the union of the functional target list and the magic target list. We can + // get a little tricky with the MCA's - we know there's only one magic port. + // So if the one magic port isn't in the list of functional ports, add it + auto l_magic_ports = find_magic_targets<fapi2::TARGET_TYPE_MCA>(i_target); + + if (l_magic_ports.size() != 1) + { + FAPI_ERR("Found wrong number of magic ports on %s (%d)", mss::c_str(i_target), l_magic_ports.size()); + fapi2::Assert(false); + } + + auto l_ports = mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target); + const auto l_magic_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(l_magic_ports[0]); + const auto l_magic_port = std::find_if(l_ports.begin(), l_ports.end(), + [&l_magic_pos](const fapi2::Target<fapi2::TARGET_TYPE_MCA>& t) + { + // Check ports by relative position. + const auto l_pos = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(t); + FAPI_DBG("checking for magic port at %d candidate is %d", l_magic_pos, l_pos); + return l_magic_pos == l_pos; + }); + + if (l_magic_port == l_ports.end()) + { + // Add the magic port to the front of the port vector. + FAPI_DBG("inserting magic port %d", l_magic_pos); + l_ports.insert(l_ports.begin(), l_magic_ports[0]); + } + + // In either case, l_ports is the proper thing to return. Either the magic port was in + // l_ports or it is now because we inserted it. + return l_ports; +} + +}// mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/hwp_wrappers_nim.C b/src/import/chips/p9/procedures/hwp/memory/lib/utils/hwp_wrappers_nim.C new file mode 100644 index 000000000..7f5dd54e7 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/hwp_wrappers_nim.C @@ -0,0 +1,169 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/utils/hwp_wrappers_nim.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file hwp_wrappers_nim.C +/// @brief Main wrapper file for PRD calling Nimbus memory procedure code +/// +// *HWP HWP Owner: Matthew Hickman <Matthew.Hickman@ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> +#include <lib/mcbist/mcbist_traits.H> +#include <generic/memory/lib/utils/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> +#include <lib/dimm/rank.H> +#include <mss.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_memdiags.H> + +/// +/// @brief Memdiags stop command wrapper for Nimbus +/// @param[in] i_target the target +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode nim_stop( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) +{ + return mss::memdiags::stop<mss::mc_type::NIMBUS>(i_target); +} + +/// +/// @brief Memdiags Super Fast Init command wrapper for Nimbus +/// @param[in] i_target the target behind which all memory should be initialized +/// @param[in] i_pattern an index representing a pattern to use to init memory (defaults to 0) +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode nim_sf_init( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const uint64_t i_pattern ) +{ + return mss::memdiags::sf_init<mss::mc_type::NIMBUS>(i_target, i_pattern); +} + +/// +/// @brief Memdiags Super Fast Read command wrapper for Nimbus +/// @param[in] i_target the target behind which all memory should be read +/// @param[in] i_stop stop conditions +/// @param[in] i_address mcbist::address representing the address from which to start. +// Defaults to the first address behind the target +/// @param[in] i_end whether to end, and where +/// Defaults to stop after slave rank +/// @param[in] i_end_address mcbist::address representing the address to end. +// Defaults to TT::LARGEST_ADDRESS +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode nim_sf_read( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::NIMBUS>& i_stop, + const mss::mcbist::address& i_address, + const mss::mcbist::end_boundary i_end, + const mss::mcbist::address& i_end_address ) +{ + return mss::memdiags::sf_read<mss::mc_type::NIMBUS>(i_target, i_stop, i_address, i_end, i_end_address); +} + +/// +/// @brief Continuous background scrub command wrapper for Nimbus +/// @param[in] i_target the target behind which all memory should be scrubbed +/// @param[in] i_stop stop conditions +/// @param[in] i_speed the speed to scrub +/// @param[in] i_address mcbist::address representing the address from which to start. +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode nim_background_scrub( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::NIMBUS>& i_stop, + const mss::mcbist::speed i_speed, + const mss::mcbist::address& i_address ) +{ + return mss::memdiags::background_scrub<mss::mc_type::NIMBUS>(i_target, i_stop, i_speed, i_address); +} + +/// +/// @brief Targeted scrub command wrapper for Nimbus +/// @param[in] i_target the target behind which all memory should be scrubbed +/// @param[in] i_stop stop conditions +/// @param[in] i_speed the speed to scrub +/// @param[in] i_start_address mcbist::address representing the address from which to start. +/// @param[in] i_end_address mcbist::address representing the address at which to end. +/// @param[in] i_end whether to end, and where +/// @return FAPI2_RC_SUCCESS iff everything ok +/// +fapi2::ReturnCode nim_targeted_scrub( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const mss::mcbist::stop_conditions<mss::mc_type::NIMBUS>& i_stop, + const mss::mcbist::address& i_start_address, + const mss::mcbist::address& i_end_address, + const mss::mcbist::end_boundary i_end ) +{ + return mss::memdiags::targeted_scrub<mss::mc_type::NIMBUS>(i_target, i_stop, i_start_address, i_end_address, i_end); +} + +/// +/// @brief Continue current command wrapper for Nimbus +/// @param[in] i_target the target +/// @param[in] i_end whether to end, and where (default - don't stop at end of rank) +/// @param[in] i_stop stop conditions (default - 0 meaning 'don't change conditions') +/// @param[in] i_speed the speed to scrub (default - SAME_SPEED meaning leave speed untouched) +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode nim_continue_cmd( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + const mss::mcbist::end_boundary i_end, + const mss::mcbist::stop_conditions<mss::mc_type::NIMBUS>& i_stop, + const mss::mcbist::speed i_speed ) +{ + return mss::memdiags::continue_cmd<mss::mc_type::NIMBUS>(i_target, i_end, i_stop, i_speed); +} + +/// +/// @brief Broadcast mode check wrapper for Nimbus +/// @param[in] i_target the target to effect +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states nim_is_broadcast_capable(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target) +{ + return mss::mcbist::is_broadcast_capable<mss::mc_type::NIMBUS>(i_target); +} + + +/// +/// @brief Broadcast mode check wrapper for Nimbus +/// @param[in] i_targets the vector of targets to analyze +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states nim_is_broadcast_capable(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_MCA>>& i_targets) +{ + return mss::mcbist::is_broadcast_capable<mss::mc_type::NIMBUS>(i_targets); +} + +/// +/// @brief Broadcast mode check wrapper for Nimbus +/// @param[in] i_kinds the dimms to effect +/// @return o_capable - yes iff these vector of targets are broadcast capable +/// +const mss::states nim_is_broadcast_capable(const std::vector<mss::dimm::kind<mss::mc_type::NIMBUS>>& i_kinds) +{ + return mss::mcbist::is_broadcast_capable(i_kinds); +} diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_nimbus_conversions.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_nimbus_conversions.H index 1b7f749fd..9a560f72a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_nimbus_conversions.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_nimbus_conversions.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -36,7 +36,7 @@ #define _MSS_NIMBUS_CONVERSIONS_H_ #include <generic/memory/lib/utils/conversions.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/mss_attribute_accessors.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H index 9b2a7a1af..ddea7c7fd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/mss_pair.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #define _MSS_PAIR_CONST_H_ #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/c_str.H> namespace mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_find.H b/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_find.H new file mode 100644 index 000000000..b922938d4 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_find.H @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/utils/nimbus_find.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file nimbus_find.H +/// @brief Nimbus templates specialization for finding things +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: HB:FSP + +#ifndef _MSS_NIMBUS_FIND_H +#define _MSS_NIMBUS_FIND_H + +#include <fapi2.H> +#include <vector> +#include <generic/memory/lib/utils/find.H> + +namespace mss +{ + +/// +/// @brief find the McBIST given a DIMM +/// @param[in] i_target the fapi2 target DIMM +/// @return a McBIST target. +/// +template<> +inline fapi2::Target<fapi2::TARGET_TYPE_MCBIST> find_target(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_MCBIST>(); +} + +/// +/// @brief find all the dimm connected to an MCS +/// @param[in] i_target a fapi2::Target MCS +/// @return a vector of fapi2::TARGET_TYPE_DIMM +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > +find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MCS>& i_target, + fapi2::TargetState i_state ) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > l_dimms; + + for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state)) + { + auto l_these_dimms( p.getChildren<fapi2::TARGET_TYPE_DIMM>(i_state) ); + l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); + } + + return l_dimms; +} + +/// +/// @brief find all the dimms connected to an MCBIST +/// @param[in] i_target a fapi2::Target MCBIST +/// @return a vector of fapi2::TARGET_TYPE_DIMM +/// +template<> +inline std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > +find_targets( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, + fapi2::TargetState i_state ) +{ + std::vector< fapi2::Target<fapi2::TARGET_TYPE_DIMM> > l_dimms; + + for (const auto& p : i_target.getChildren<fapi2::TARGET_TYPE_MCA>(i_state)) + { + auto l_these_dimms( p.getChildren<fapi2::TARGET_TYPE_DIMM>(i_state) ); + l_dimms.insert(l_dimms.end(), l_these_dimms.begin(), l_these_dimms.end()); + } + + return l_dimms; +} + +/// +/// @brief find the MCS given a DIMM +/// @param[in] i_target the fapi2 target DIMM +/// @return a MCS target. +/// +template<> +inline fapi2::Target<fapi2::TARGET_TYPE_MCS> find_target( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target) +{ + return i_target.getParent<fapi2::TARGET_TYPE_MCA>().getParent<fapi2::TARGET_TYPE_MCS>(); +} + +}// mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C index cb9e22594..107cca50c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/adr32s_workarounds.C @@ -48,7 +48,7 @@ #include <lib/workarounds/adr32s_workarounds.H> #include <lib/phy/ddr_phy.H> #include <lib/phy/dcd.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_SYSTEM; diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C index f6a8b3467..de136357f 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.C @@ -34,13 +34,16 @@ // *HWP Consumed by: FSP:HB Memory Lab #include <lib/shared/nimbus_defaults.H> +#include <lib/shared/mss_const.H> #include <lib/workarounds/ccs_workarounds.H> #include <lib/dimm/rank.H> #include <p9_mc_scom_addresses.H> #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/pos.H> #include <lib/eff_config/timing.H> -#include <lib/ccs/ccs.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/mc/port.H> +#include <lib/mc/mc.H> namespace mss { @@ -105,7 +108,7 @@ fapi_try_exit: /// fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ) + ccs::program& io_program ) { const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); // Issues A-side MRS @@ -150,9 +153,9 @@ fapi_try_exit: /// ccs program execution will be handled by OCC /// fapi2::ReturnCode preload_ccs_for_epow( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program) + ccs::program& i_program) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; // Subtract one for the idle we insert at the end constexpr size_t CCS_INSTRUCTION_DEPTH = 32 - 1; @@ -219,6 +222,66 @@ namespace nvdimm { /// +/// @brief add_refreshes() helper +/// @param[in] i_target The MCA target where the program will be executed on +/// @param[in,out] i_program the MCBIST ccs program to append the refreshes +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode add_refreshes_helper(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + mss::ccs::program& io_program) +{ + typedef ccsTraits<mss::mc_type::NIMBUS> TT; + + uint16_t l_trefi = 0; + + // 3 refreshes because the maximum number of instructions we can have is 28 for + // dual-rank NVDIMM (MRS) + constexpr size_t l_num_refreshes = 3; + constexpr uint64_t CS_N_ACTIVE = 0b00; + + //get tREFI + FAPI_TRY(mss::eff_dram_trefi(i_target, l_trefi)); + + //load the refreshes into the program + for (size_t i = 0; i < l_num_refreshes; i++) + { + // We want to make sure the refresh hit all the ranks, so let's get the refresh command and change the chip select manually later + mss::ccs::instruction_t l_inst = mss::ccs::refresh_command(0, l_trefi); + l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_0_1, TT::ARR0_DDR_CSN_0_1_LEN>(CS_N_ACTIVE); + l_inst.arr0.insertFromRight<TT::ARR0_DDR_CSN_2_3, TT::ARR0_DDR_CSN_2_3_LEN>(CS_N_ACTIVE); + l_inst.iv_update_rank = false; + io_program.iv_instructions.push_back(l_inst); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Adds refreshes at the beginning and end of the program +/// @param[in] i_target The MCA target where the program will be executed on +/// @param[in,out] io_program the MCBIST ccs program to add the refreshes +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode add_refreshes(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + mss::ccs::program& io_program) +{ + mss::ccs::program l_program; + + // Add the refreshes at the beginning + FAPI_TRY(add_refreshes_helper(i_target, l_program)); + + // Append the instructions from io_program + l_program.iv_instructions.insert(l_program.iv_instructions.end(), io_program.iv_instructions.begin(), + io_program.iv_instructions.end()); + + io_program = l_program; + +fapi_try_exit: + return fapi2::current_err; +} + +/// /// @brief Execute the contents of the CCS array with ccs_addr_mux_sel control /// @param[in] i_target The MCBIST containing the array /// @param[in] i_program the MCBIST ccs program - to get the polling parameters @@ -229,10 +292,10 @@ namespace nvdimm /// CCS can properly drive the bus during the nvdimm post-restore sequence. /// fapi2::ReturnCode execute_inst_array(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program, + mss::ccs::program& i_program, const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_port) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; fapi2::buffer<uint64_t> status; @@ -256,7 +319,7 @@ fapi2::ReturnCode execute_inst_array(const fapi2::Target<fapi2::TARGET_TYPE_MCBI i_program.iv_probes); // Check for done and success. DONE being the only bit set. - if (status == STAT_QUERY_SUCCESS) + if (status == TT::STAT_QUERY_SUCCESS) { FAPI_INF("%s CCS Executed Successfully.", mss::c_str(i_port) ); goto fapi_try_exit; @@ -280,105 +343,130 @@ fapi_try_exit: /// @note This is a copy of execute() with minor tweaks to the namespace and single port only /// fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program, + mss::ccs::program& i_program, const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_port) { - typedef ccsTraits<fapi2::TARGET_TYPE_MCBIST> TT; + typedef ccsTraits<mss::mc_type::NIMBUS> TT; // Subtract one for the idle we insert at the end constexpr size_t CCS_INSTRUCTION_DEPTH = 32 - 1; constexpr uint64_t CCS_ARR0_ZERO = MCBIST_CCS_INST_ARR0_00; constexpr uint64_t CCS_ARR1_ZERO = MCBIST_CCS_INST_ARR1_00; + mss::states l_str_state = mss::states::OFF; + fapi2::buffer<uint64_t> l_farb6q; - mss::ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> l_des = ccs::des_command<fapi2::TARGET_TYPE_MCBIST>(); + mss::ccs::instruction_t l_des = ccs::des_command(); FAPI_INF("loading ccs instructions (%d) for %s", i_program.iv_instructions.size(), mss::c_str(i_target)); - auto l_inst_iter = i_program.iv_instructions.begin(); + //Check if we are in str. If we are not, throw some refreshes into the program + FAPI_TRY(mss::mc::read_farb6q(i_port, l_farb6q)); + mss::mc::get_self_time_refresh_state(l_farb6q, l_str_state); - // Stop the CCS engine just for giggles - it might be running ... - FAPI_TRY( mss::ccs::start_stop(i_target, mss::states::STOP), "Error in ccs::execute" ); - - FAPI_ASSERT( mss::poll(i_target, TT::STATQ_REG, poll_parameters(), - [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool + if (l_str_state == mss::states::OFF) { - FAPI_INF("ccs statq (stop) 0x%llx, remaining: %d", stat_reg, poll_remaining); - return stat_reg.getBit<TT::CCS_IN_PROGRESS>() != 1; - }), - fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target) ); + // Since we are executing the CCS program with data in the DRAMs, we need to be congnizant + // about the refreshes. Refresh from mc is fenced off when CCS has the bus, and by the time + // the control is given back to the mc, we would have violated 8*trefi refresh window. + // As such, let's start off each program with couple of refreshes so we don't violate the + // rolling 8*trefi window (verified on logic analyzer) + FAPI_TRY(add_refreshes(i_port, i_program)); + } - while (l_inst_iter != i_program.iv_instructions.end()) { - size_t l_inst_count = 0; + auto l_inst_iter = i_program.iv_instructions.begin(); - uint64_t l_total_delay = 0; - uint64_t l_delay = 0; - uint64_t l_repeat = 0; - uint8_t l_current_cke = 0; + std::vector<rank_configuration> l_rank_configs; + FAPI_TRY(get_rank_config(i_target, l_rank_configs)); - // Shove the instructions into the CCS engine, in 32 instruction chunks, and execute them - for (; l_inst_iter != i_program.iv_instructions.end() - && l_inst_count < CCS_INSTRUCTION_DEPTH; ++l_inst_count, ++l_inst_iter) + // Stop the CCS engine just for giggles - it might be running ... + FAPI_TRY( mss::ccs::start_stop(i_target, mss::states::STOP), "Error in ccs::execute" ); + + FAPI_ASSERT( mss::poll(i_target, TT::STATQ_REG, poll_parameters(), + [](const size_t poll_remaining, const fapi2::buffer<uint64_t>& stat_reg) -> bool { - l_inst_iter->arr0.extractToRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); + FAPI_INF("ccs statq (stop) 0x%llx, remaining: %d", stat_reg, poll_remaining); + return stat_reg.getBit<TT::CCS_IN_PROGRESS>() != 1; + }), + fapi2::MSS_CCS_HUNG_TRYING_TO_STOP().set_MCBIST_TARGET(i_target) ); - // Make sure this instruction leads to the next. Notice this limits this mechanism to pretty - // simple (straight line) CCS programs. Anything with a loop or such will need another mechanism. - l_inst_iter->arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_GOTO_CMD, - MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN>(l_inst_count + 1); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0), "Error in ccs::execute" ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1), "Error in ccs::execute" ); + while (l_inst_iter != i_program.iv_instructions.end()) + { + size_t l_inst_count = 0; - // arr1 contains a specification of the delay and repeat after this instruction, as well - // as a repeat. Total up the delays as we go so we know how long to wait before polling - // the CCS engine for completion - l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(l_delay); - l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, - MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT>(l_repeat); + uint64_t l_total_delay = 0; + uint64_t l_delay = 0; + uint64_t l_repeat = 0; + uint8_t l_current_cke = 0; + const auto l_port_index = mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port); - l_total_delay += l_delay * (l_repeat + 1); + // Shove the instructions into the CCS engine, in 32 instruction chunks, and execute them + for (; l_inst_iter != i_program.iv_instructions.end() + && l_inst_count < CCS_INSTRUCTION_DEPTH; ++l_inst_count, ++l_inst_iter) + { + // First, update the current instruction's chip selects for the current port + FAPI_TRY(l_inst_iter->configure_rank(i_port, l_rank_configs[l_port_index]), "Error in rank config"); - FAPI_INF("css inst %d: 0x%016lX 0x%016lX (0x%lx, 0x%lx) delay: 0x%x (0x%x) %s", - l_inst_count, l_inst_iter->arr0, l_inst_iter->arr1, - CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, - l_delay, l_total_delay, mss::c_str(i_target)); - } + l_inst_iter->arr0.extractToRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); - // Check our program for any delays. If there isn't a iv_initial_delay configured, then - // we use the delay we just summed from the instructions. - if (i_program.iv_poll.iv_initial_delay == 0) - { - i_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, l_total_delay); - } + // Make sure this instruction leads to the next. Notice this limits this mechanism to pretty + // simple (straight line) CCS programs. Anything with a loop or such will need another mechanism. + l_inst_iter->arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_GOTO_CMD, + MCBIST_CCS_INST_ARR1_00_GOTO_CMD_LEN>(l_inst_count + 1); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_inst_iter->arr0), "Error in ccs::execute" ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_inst_iter->arr1), "Error in ccs::execute" ); + + // arr1 contains a specification of the delay and repeat after this instruction, as well + // as a repeat. Total up the delays as we go so we know how long to wait before polling + // the CCS engine for completion + l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(l_delay); + l_inst_iter->arr1.extractToRight<MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT, + MCBIST_CCS_INST_ARR1_00_REPEAT_CMD_CNT>(l_repeat); + + l_total_delay += l_delay * (l_repeat + 1); + + FAPI_INF("css inst %d: 0x%016lX 0x%016lX (0x%lx, 0x%lx) delay: 0x%x (0x%x) %s", + l_inst_count, l_inst_iter->arr0, l_inst_iter->arr1, + CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, + l_delay, l_total_delay, mss::c_str(i_target)); + } - if (i_program.iv_poll.iv_initial_sim_delay == 0) - { - i_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(l_total_delay); - } + // Check our program for any delays. If there isn't a iv_initial_delay configured, then + // we use the delay we just summed from the instructions. + if (i_program.iv_poll.iv_initial_delay == 0) + { + i_program.iv_poll.iv_initial_delay = cycles_to_ns(i_target, l_total_delay); + } - FAPI_INF("executing ccs instructions (%d:%d, %d) for %s", - i_program.iv_instructions.size(), l_inst_count, i_program.iv_poll.iv_initial_delay, mss::c_str(i_target)); - - // Deselect - l_des.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); - - // Insert a DES as our last instruction. DES is idle state anyway and having this - // here as an instruction forces the CCS engine to wait the delay specified in - // the last instruction in this array (which it otherwise doesn't do.) - l_des.arr1.setBit<MCBIST_CCS_INST_ARR1_00_END>(); - FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0), "Error in ccs::execute" ); - FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1), "Error in ccs::execute" ); - - FAPI_INF("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s", - l_inst_count, l_des.arr0, l_des.arr1, - CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, mss::c_str(i_target)); - - // Kick off the CCS engine - per port. No broadcast mode for CCS (per Shelton 9/23/15) - FAPI_INF("executing CCS array for port %d (%s)", mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port), - mss::c_str(i_port)); - FAPI_TRY( mss::ccs::select_ports( i_target, mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port)), - "Error in ccs execute" ); - FAPI_TRY( execute_inst_array(i_target, i_program, i_port), "Error in ccs execute" ); + if (i_program.iv_poll.iv_initial_sim_delay == 0) + { + i_program.iv_poll.iv_initial_sim_delay = cycles_to_simcycles(l_total_delay); + } + + FAPI_INF("executing ccs instructions (%d:%d, %d) for %s", + i_program.iv_instructions.size(), l_inst_count, i_program.iv_poll.iv_initial_delay, mss::c_str(i_target)); + + // Deselect + l_des.arr0.insertFromRight<TT::ARR0_DDR_CKE, TT::ARR0_DDR_CKE_LEN>(l_current_cke); + + // Insert a DES as our last instruction. DES is idle state anyway and having this + // here as an instruction forces the CCS engine to wait the delay specified in + // the last instruction in this array (which it otherwise doesn't do.) + l_des.arr1.setBit<MCBIST_CCS_INST_ARR1_00_END>(); + FAPI_TRY( mss::putScom(i_target, CCS_ARR0_ZERO + l_inst_count, l_des.arr0), "Error in ccs::execute" ); + FAPI_TRY( mss::putScom(i_target, CCS_ARR1_ZERO + l_inst_count, l_des.arr1), "Error in ccs::execute" ); + + FAPI_INF("css inst %d fixup: 0x%016lX 0x%016lX (0x%lx, 0x%lx) %s", + l_inst_count, l_des.arr0, l_des.arr1, + CCS_ARR0_ZERO + l_inst_count, CCS_ARR1_ZERO + l_inst_count, mss::c_str(i_target)); + + // Kick off the CCS engine - per port. No broadcast mode for CCS (per Shelton 9/23/15) + FAPI_INF("executing CCS array for port %d (%s)", mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port), + mss::c_str(i_port)); + FAPI_TRY( mss::ccs::select_ports<mss::mc_type::NIMBUS>( i_target, mss::relative_pos<fapi2::TARGET_TYPE_MCBIST>(i_port)), + "Error in ccs execute" ); + FAPI_TRY( execute_inst_array(i_target, i_program, i_port), "Error in ccs execute" ); + } } fapi_try_exit: @@ -413,7 +501,7 @@ void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state) fapi2::ReturnCode add_mrs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rank, const mss::states& i_state, - std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>>& io_inst) + std::vector<ccs::instruction_t>& io_inst) { // First, get the DIMM target // Note: the target is setup below based upon the rank @@ -555,7 +643,7 @@ fapi2::ReturnCode configure_non_calibrating_ranks(const fapi2::Target<fapi2::TAR const mss::states& i_state) { // Declares variables - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST, fapi2::TARGET_TYPE_MCA> l_program; + ccs::program l_program; std::vector<uint64_t> l_ranks; const auto& l_mcbist = mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H index 067f8481f..5cb57295b 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/ccs_workarounds.H @@ -38,12 +38,15 @@ #include <fapi2.H> #include <p9_mc_scom_addresses.H> +#include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/c_str.H> -#include <generic/memory/lib/utils/find.H> -#include <lib/ccs/ccs.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> #include <lib/dimm/ddr4/mrs_load_ddr4.H> + namespace mss { @@ -66,7 +69,7 @@ namespace workarounds /// fapi2::ReturnCode exit( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const uint64_t i_rank, - ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ); + ccs::program& io_program ); /// /// @brief Re-enables PDA mode on a given rank in the shadow registers @@ -83,7 +86,7 @@ fapi2::ReturnCode enable_pda_shadow_reg( const fapi2::Target<fapi2::TARGET_TYPE_ /// @param[in,out] io_inst - the CCS instruction /// inline void hold_cke_low_helper( fapi2::buffer<uint8_t>& io_cke, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst ) + ccs::instruction_t& io_inst ) { fapi2::buffer<uint8_t> l_cur_cke; io_inst.arr0.extractToRight<MCBIST_CCS_INST_ARR0_00_DDR_CKE, MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN>(l_cur_cke); @@ -95,7 +98,7 @@ inline void hold_cke_low_helper( fapi2::buffer<uint8_t>& io_cke, /// @brief Holds the lower order rank cke low in higher order rank instruction /// @param[in,out] io_program - CCS program with instructions on multi-rank DIMM /// -inline void hold_cke_low( ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ) +inline void hold_cke_low( ccs::program& io_program ) { fapi2::buffer<uint8_t> l_cke(CKE_HIGH); @@ -111,7 +114,7 @@ inline void hold_cke_low( ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ) /// @param[in,out] io_inst - the CCS instruction /// inline void hold_cke_high_helper( fapi2::buffer<uint8_t>& io_cke, - ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>& io_inst ) + ccs::instruction_t& io_inst ) { fapi2::buffer<uint8_t> l_cur_cke; io_inst.arr0.extractToRight<MCBIST_CCS_INST_ARR0_00_DDR_CKE, MCBIST_CCS_INST_ARR0_00_DDR_CKE_LEN>(l_cur_cke); @@ -123,7 +126,7 @@ inline void hold_cke_high_helper( fapi2::buffer<uint8_t>& io_cke, /// @brief Holds the lower order rank cke high in higher order rank instruction /// @param[in,out] io_inst - CCS program with instructions on multi-rank DIMM /// -inline void hold_cke_high( std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>>& io_inst ) +inline void hold_cke_high( std::vector<ccs::instruction_t>& io_inst ) { fapi2::buffer<uint8_t> l_cke(CKE_LOW); @@ -137,7 +140,7 @@ inline void hold_cke_high( std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCB /// @brief Holds the lower order rank cke high in higher order rank instruction /// @param[in,out] io_program - CCS program with instructions on multi-rank DIMM /// -inline void hold_cke_high( ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ) +inline void hold_cke_high( ccs::program& io_program ) { fapi2::buffer<uint8_t> l_cke(CKE_LOW); @@ -155,12 +158,30 @@ inline void hold_cke_high( ccs::program<fapi2::TARGET_TYPE_MCBIST>& io_program ) /// @note This is written specifically to support EPOW on NVDIMM /// fapi2::ReturnCode preload_ccs_for_epow( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program); + ccs::program& i_program); namespace nvdimm { /// +/// @brief add_refreshes() helper +/// @param[in] i_target The MCA target where the program will be executed on +/// @param[in,out] i_program the MCBIST ccs program to append the refreshes +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode add_refreshes_helper(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + mss::ccs::program& io_program); + +/// +/// @brief Adds refreshes at the beginning and end of the program +/// @param[in] i_target The MCA target where the program will be executed on +/// @param[in,out] io_program the MCBIST ccs program to add the refreshes +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode add_refreshes(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + mss::ccs::program& io_program); + +/// /// @brief Execute a set of CCS instructions /// @param[in] i_target the target to effect /// @param[in] i_program the vector of instructions @@ -169,7 +190,7 @@ namespace nvdimm /// @note This is a copy of execute() with minor tweaks to the namespace and single port only /// fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program, + mss::ccs::program& i_program, const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_port); /// @@ -183,7 +204,7 @@ fapi2::ReturnCode execute( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_tar /// CCS can properly drive the bus during the nvdimm post-restore sequence. /// fapi2::ReturnCode execute_inst_array(const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mss::ccs::program<fapi2::TARGET_TYPE_MCBIST>& i_program, + mss::ccs::program& i_program, fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_port); } @@ -208,7 +229,7 @@ void update_mrs(mss::ddr4::mrs01_data& io_mrs, const mss::states i_state); fapi2::ReturnCode add_mrs(const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rank, const mss::states& i_state, - std::vector<ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST>>& io_inst); + std::vector<ccs::instruction_t>& io_inst); /// /// @brief Gets a vector of ranks that are not going to be calibrated in the given rank pair diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C index 4e73323f2..584dc36c8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dll_workarounds.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,7 +33,7 @@ #include <fapi2.H> #include <lib/workarounds/dll_workarounds.H> #include <lib/fir/check.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/scom.H> #include <lib/phy/dp16.H> #include <lib/fir/fir.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C index 798447c83..f9e3b08d7 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.C @@ -59,6 +59,79 @@ namespace mss namespace workarounds { +// Putting the NVDIMM workarounds here as it's a bit of a hybrid case +// Also there are issues as the nvdimm_workarounds.* files are picked up externally +namespace nvdimm +{ + +/// +/// @brief Checks if the NVDIMM RD DQ delay adjust is needed +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_is_needed true if the workaround is needed +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode is_adjust_rd_dq_delay_needed( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + bool& o_is_needed ) +{ + uint8_t l_hybrid_type[mss::MAX_DIMM_PER_PORT] = {}; + uint8_t l_is_hybrid[mss::MAX_DIMM_PER_PORT] = {}; + o_is_needed = false; + + FAPI_TRY(mss::eff_hybrid_memory_type(i_target, l_hybrid_type)); + FAPI_TRY(mss::eff_hybrid(i_target, l_is_hybrid)); + + // This workaround is only needed if we're dealing with NVDIMM + // We only need DIMM0 as NVDIMM will only ever be single drop + o_is_needed = (l_hybrid_type[0] == fapi2::ENUM_ATTR_EFF_HYBRID_IS_HYBRID) && + (l_is_hybrid[0] == fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NVDIMM); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Adjusts NVDIMM RD DQ delays +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_rp the rank pair on which to adjust delays +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode adjust_rd_dq_delay( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp ) +{ + // Constexpr's for some general beautification + constexpr uint64_t VALUE0_START = MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD; + constexpr uint64_t VALUE1_START = MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_DELAY1; + typedef mss::dp16Traits<fapi2::TARGET_TYPE_MCA> TT; + + bool l_is_needed = false; + std::vector<fapi2::buffer<uint64_t>> l_data; + FAPI_TRY(is_adjust_rd_dq_delay_needed(i_target, l_is_needed)); + + // If the adjust is not needed, exit out + if(!l_is_needed) + { + FAPI_INF("%s RD DQ delay adjust isn't needed. Skipping the workaround", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Read + FAPI_TRY(mss::scom_suckah(i_target, TT::READ_DELAY_REG[i_rp], l_data)); + + // Modify + for(auto& l_info : l_data) + { + update_rd_dq_delay<VALUE0_START>(l_info); + update_rd_dq_delay<VALUE1_START>(l_info); + } + + // Write + FAPI_TRY(mss::scom_blastah(i_target, TT::READ_DELAY_REG[i_rp], l_data)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // close namespace nvdimm + namespace dp16 { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H index daf9780d6..ddee4f42a 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/dp16_workarounds.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -52,6 +52,48 @@ namespace mss namespace workarounds { +// Putting the NVDIMM workarounds here as it's a bit of a hybrid case +// Also there are issues as the nvdimm_workarounds.* files are picked up externally +namespace nvdimm +{ + +/// +/// @brief Updates a single RD DQ value for the NVDIMM workaround +/// @tparam P the bit position to update +/// @param[in,out] io_data the data bufffer to update +/// +template<uint64_t P> +void update_rd_dq_delay(fapi2::buffer<uint64_t>& io_data) +{ + constexpr uint64_t MAX_VALUE = 0x7f; + constexpr uint64_t OFFSET = 2; + constexpr uint64_t LEN = MCA_DDRPHY_DP16_READ_DELAY0_RANK_PAIR0_P0_0_01_RD_LEN; + uint64_t l_value = 0; + io_data.extractToRight<P, LEN>(l_value); + l_value += OFFSET; + l_value = std::min(l_value, MAX_VALUE); + io_data.insertFromRight<P, LEN>(l_value); +} + +/// +/// @brief Checks if the NVDIMM RD DQ delay adjust is needed +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_is_needed true if the workaround is needed +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode is_adjust_rd_dq_delay_needed( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + bool& o_is_needed ); + +/// +/// @brief Adjusts NVDIMM RD DQ delays +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_rp the rank pair on which to adjust delays +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +fapi2::ReturnCode adjust_rd_dq_delay( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, const uint64_t i_rp ); + +} // close namespace nvdimm + namespace dp16 { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C index a0a375f2b..dd5275288 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,7 @@ namespace workarounds /// fapi2::ReturnCode rcw_reset_dram( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst) + std::vector< ccs::instruction_t >& io_inst) { // Note: we're always going to run this guy FAPI_INF("%s running the DRAM RCW DRAM reset workaround", mss::c_str(i_target)); diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H index 1b43c1416..437065578 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/draminit_workarounds.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -53,7 +53,7 @@ namespace workarounds /// fapi2::ReturnCode rcw_reset_dram( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, const bool i_sim, - std::vector< ccs::instruction_t<fapi2::TARGET_TYPE_MCBIST> >& io_inst); + std::vector< ccs::instruction_t >& io_inst); } // namespace workarounds diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.C new file mode 100644 index 000000000..dae18167b --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.C @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + + +#include <fapi2.H> +#include <lib/mss_attribute_accessors.H> +#include <lib/workarounds/eff_config_workarounds.H> + +namespace mss +{ + +namespace workarounds +{ + +namespace eff_config +{ + +/// +/// @brief Checks if the NVDIMM RC drive strength workaround is needed +/// @param[in] i_target DIMM target on which to operate +/// @param[out] o_is_needed true if the workaround is needed +/// @return SUCCESS if the code executes successfully +/// +fapi2::ReturnCode is_nvdimm_rc_drive_strength_needed(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + bool& o_is_needed) +{ + o_is_needed = false; + + uint8_t l_hybrid = 0; + uint8_t l_hybrid_type = 0; + uint32_t l_size = 0; + + FAPI_TRY(mss::eff_hybrid(i_target, l_hybrid)); + FAPI_TRY(mss::eff_hybrid_memory_type(i_target, l_hybrid_type)); + FAPI_TRY(mss::eff_dimm_size(i_target, l_size)); + + if(l_hybrid == fapi2::ENUM_ATTR_EFF_HYBRID_IS_HYBRID && + l_hybrid_type == fapi2::ENUM_ATTR_EFF_HYBRID_MEMORY_TYPE_NVDIMM && + l_size == fapi2::ENUM_ATTR_EFF_DIMM_SIZE_32GB) + { + o_is_needed = true; + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Updates the RC drive strength if the workaround is needed +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_override_value the value to override if the workaround needs to be applied +/// @param[in,out] io_rc_value Register Control word value to update +/// @return SUCCESS if the code executes successfully +/// +fapi2::ReturnCode nvdimm_rc_drive_strength(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_override_value, + fapi2::buffer<uint8_t>& io_rc_value) +{ + bool l_is_needed = false; + FAPI_TRY(is_nvdimm_rc_drive_strength_needed(i_target, l_is_needed)); + + // If the workaround is needed, overwrite it to be ALL_MODERATE values + // Otherwise keep it as it is + io_rc_value = l_is_needed ? fapi2::buffer<uint8_t>(i_override_value) : io_rc_value; + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns eff_config +} // ns workarounds +} // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.H index c3a8e6c8c..f41d9b89c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/fir/memdiags_fir.H $ */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/workarounds/eff_config_workarounds.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -24,45 +24,52 @@ /* IBM_PROLOG_END_TAG */ /// -/// @file memdiags_fir.H -/// @brief Subroutines for memdiags/prd FIR +/// @file eff_config_workarounds.H +/// @brief Workarounds for effective config +/// Workarounds are very device specific, so there is no attempt to generalize +/// this code in any way. /// // *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> -// *HWP HWP Backup: Marc Gollub <gollub@us.ibm.com> +// *HWP HWP Backup: Andre Marin <aamarin@us.ibm.com> // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB -#ifndef _MSS_MEMDIAGS_FIR_H_ -#define _MSS_MEMDIAGS_FIR_H_ +#ifndef _EFF_CONFIG_WORKAROUNDS_H_ +#define _EFF_CONFIG_WORKAROUNDS_H_ #include <fapi2.H> -#include <lib/fir/fir.H> namespace mss { -namespace unmask +namespace workarounds +{ + +namespace eff_config { /// -/// @brief Unmask and setup actions for memdiags related FIR -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// @brief Checks if the NVDIMM RC drive strength workaround is needed +/// @param[in] i_target DIMM target on which to operate +/// @param[out] o_is_needed true if the workaround is needed +/// @return SUCCESS if the code executes successfully /// -template< fapi2::TargetType T > -fapi2::ReturnCode after_memdiags( const fapi2::Target<T>& i_target ); +fapi2::ReturnCode is_nvdimm_rc_drive_strength_needed(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + bool& o_is_needed); /// -/// @brief Unmask and setup actions for scrub related FIR -/// @tparam T the fapi2::TargetType which hold the FIR bits -/// @param[in] i_target the fapi2::Target -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff ok +/// @brief Updates the RC drive strength if the workaround is needed +/// @param[in] i_target DIMM target on which to operate +/// @param[in] i_override_value the value to override if the workaround needs to be applied +/// @param[in,out] io_rc_value Register Control word value to update +/// @return SUCCESS if the code executes successfully /// -template< fapi2::TargetType T > -fapi2::ReturnCode after_background_scrub( const fapi2::Target<T>& i_target ); +fapi2::ReturnCode nvdimm_rc_drive_strength(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint8_t i_override_value, + fapi2::buffer<uint8_t>& io_rc_value); -} -} +} // ns eff_config +} // ns workarounds +} // ns mss #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C index d9e8f6416..164fbe580 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mca_workarounds.C @@ -66,6 +66,17 @@ bool check_str_non_tsv_parity_workaround(const fapi2::Target<fapi2::TARGET_TYPE_ bool l_tsv = false; bool l_str_enabled = false; bool l_is_nvdimm = false; + bool l_has_4r_dimm = false; + uint8_t l_master_ranks[MAX_DIMM_PER_PORT] = {}; + + FAPI_TRY(eff_num_master_ranks_per_dimm(i_target, l_master_ranks)); + + // If we have either DIMM having four ranks, we need to disable parity mode + if((l_master_ranks[0] == fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R) || + (l_master_ranks[1] == fapi2::ENUM_ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM_4R)) + { + l_has_4r_dimm = true; + } // Figure out if any hybrid memory is plugged FAPI_TRY(mss::eff_hybrid(i_target, l_hybrid)); @@ -101,11 +112,13 @@ bool check_str_non_tsv_parity_workaround(const fapi2::Target<fapi2::TARGET_TYPE_ // 1) greater than or equal to DD2 // 2) self time refresh is enabled // 3) the DIMM's are not TSV - FAPI_INF("%s %s DD2 STR: %s DIMM %s TSV", mss::c_str(i_target), + // 4) a 4R DIMM is present + FAPI_INF("%s %s DD2 STR: %s DIMM %s TSV %s DIMM", mss::c_str(i_target), l_less_than_dd2 ? "less than" : "greater than or equal to", l_str_enabled ? "enabled" : "disabled", - l_tsv ? "is" : "isn't"); - return (!l_less_than_dd2) && l_str_enabled && (!l_tsv); + l_tsv ? "is" : "isn't", + l_has_4r_dimm ? "4R" : "not 4R"); + return ((!l_less_than_dd2) && l_str_enabled && (!l_tsv)) || (l_has_4r_dimm); fapi_try_exit: FAPI_ERR("failed calling check_str_non_tsv_parity_workaround: 0x%lx (target: %s)", diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C index 9316abaa5..f87d01078 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.C @@ -43,7 +43,7 @@ #include <lib/mss_attribute_accessors.H> #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/pos.H> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> #include <lib/workarounds/mcbist_workarounds.H> #include <lib/mcbist/mcbist.H> #include <lib/fir/fir.H> @@ -66,9 +66,9 @@ namespace mcbist /// @param[in,out] the MCBIST program to check for read/display replacement /// @note Useful for testing /// -void replace_read_helper(mss::mcbist::program<TARGET_TYPE_MCBIST>& io_program) +void replace_read_helper(mss::mcbist::program<>& io_program) { - using TT = mss::mcbistTraits<TARGET_TYPE_MCBIST>; + using TT = mss::mcbistTraits<>; io_program.change_maint_broadcast_mode(mss::OFF); io_program.change_end_boundary(mss::mcbist::end_boundary::STOP_AFTER_ADDRESS); @@ -99,9 +99,9 @@ void replace_read_helper(mss::mcbist::program<TARGET_TYPE_MCBIST>& io_program) /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// fapi2::ReturnCode end_of_rank( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target, - mss::mcbist::program<TARGET_TYPE_MCBIST>& io_program ) + mss::mcbist::program<>& io_program ) { - using TT = mss::mcbistTraits<TARGET_TYPE_MCBIST>; + using TT = mss::mcbistTraits<>; // If we don't need the mcbist work-around, we're done. if (! mss::chip_ec_feature_mcbist_end_of_rank(i_target) ) @@ -110,8 +110,9 @@ fapi2::ReturnCode end_of_rank( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target } // First things first - lets find out if we have an 1R DIMM on our side of the chip. - const auto l_dimm_kinds = dimm::kind::vector( mss::find_targets<TARGET_TYPE_DIMM>(i_target) ); - const auto l_kind = std::find_if(l_dimm_kinds.begin(), l_dimm_kinds.end(), [](const dimm::kind & k) -> bool + const auto l_dimm_kinds = dimm::kind<>::vector( mss::find_targets<TARGET_TYPE_DIMM>(i_target) ); + const auto l_kind = std::find_if(l_dimm_kinds.begin(), + l_dimm_kinds.end(), [](const dimm::kind<>& k) -> bool { // If total ranks are 1, we have a 1R DIMM, SDP. This is the fellow of concern return k.iv_total_ranks == 1; @@ -146,26 +147,6 @@ fapi2::ReturnCode end_of_rank( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target } /// -/// @brief WAT debug attention -/// For Nimbus DD1 the MCBIST engine uses the WAT debug bit as a workaround -/// For Nimbus DD2 the WAT debug bit is used for a different workaround -/// @param[in] i_target the fapi2 target of the mcbist -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode wat_debug_attention( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ) -{ - // MCBIST attentions are already special attention - fapi2::ReturnCode l_rc; - fir::reg<MCBIST_MCBISTFIRQ> mcbist_fir_register(i_target, l_rc); - FAPI_TRY(l_rc, "unable to create fir::reg for %d", MCBIST_MCBISTFIRQ); - - FAPI_TRY(mcbist_fir_register.attention<MCBIST_MCBISTFIRQ_WAT_DEBUG_ATTN>().write()); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief BROADCAST OUT OF SYNC workaround /// A UE noise window is triggered by UE/AUEs causing an out of sync error /// @param[in] i_target the fapi2 target of the mcbist diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H index 1e5d9662a..7a4533c6d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/mcbist_workarounds.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,7 +55,7 @@ namespace mcbist /// @param[in] the MCBIST program to check for read/display replacement /// @note Useful for testing /// -void replace_read_helper(mss::mcbist::program<fapi2::TARGET_TYPE_MCBIST>& i_program); +void replace_read_helper(mss::mcbist::program<>& i_program); /// /// @brief End of rank work around @@ -69,15 +69,7 @@ void replace_read_helper(mss::mcbist::program<fapi2::TARGET_TYPE_MCBIST>& i_prog /// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok /// fapi2::ReturnCode end_of_rank( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target, - mss::mcbist::program<fapi2::TARGET_TYPE_MCBIST>& i_program ); - -/// -/// @brief WAT debug attention -/// For Nimbus DD1 the MCBIST engine uses the WAT debug bit as a workaround -/// @param[in] i_target the fapi2 target of the mcbist -/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok -/// -fapi2::ReturnCode wat_debug_attention( const fapi2::Target<fapi2::TARGET_TYPE_MCBIST>& i_target ); + mss::mcbist::program<>& i_program ); /// /// @brief BROADCAST OUT OF SYNC workaround diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C index 86e2cce75..f5942b528 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.C @@ -48,33 +48,8 @@ namespace workarounds namespace nvdimm { -// MBASTR0Q for each MCA // Note: Since the scoms are executed at the chip, it needs the dedicated // address for each MCA -constexpr const uint64_t MBASTR0Q_REG[] = -{ - MCA_0_MBASTR0Q, - MCA_1_MBASTR0Q, - MCA_2_MBASTR0Q, - MCA_3_MBASTR0Q, - MCA_4_MBASTR0Q, - MCA_5_MBASTR0Q, - MCA_6_MBASTR0Q, - MCA_7_MBASTR0Q, -}; - -// MBARPC0Q for each MCA -constexpr const uint64_t MBARPC0Q_REG[] = -{ - MCA_0_MBARPC0Q, - MCA_1_MBARPC0Q, - MCA_2_MBARPC0Q, - MCA_3_MBARPC0Q, - MCA_4_MBARPC0Q, - MCA_5_MBARPC0Q, - MCA_6_MBARPC0Q, - MCA_7_MBARPC0Q, -}; // FARB5Q for each MCA constexpr const uint64_t FARB5Q_REG[] = @@ -89,6 +64,15 @@ constexpr const uint64_t FARB5Q_REG[] = MCA_7_MBA_FARB5Q, }; +// MCFGP for each MCS +constexpr const uint64_t MCFGP[] = +{ + MCS_0_MCFGP, + MCS_1_MCFGP, + MCS_2_MCFGP, + MCS_3_MCFGP, +}; + // MCB_CNTLQ constexpr const uint64_t MCB_CNTLQ_REG[] = { @@ -96,89 +80,159 @@ constexpr const uint64_t MCB_CNTLQ_REG[] = MCBIST_1_MCB_CNTLQ, }; +// MCB_MCBAGRAQ +constexpr const uint64_t MCB_MCBAGRAQ_REG[] = +{ + MCBIST_0_MCBAGRAQ, + MCBIST_1_MCBAGRAQ, +}; + +// CCS_MODEQ +constexpr const uint64_t CCS_MODEQ_REG[] = +{ + MCBIST_0_CCS_MODEQ, + MCBIST_1_CCS_MODEQ, +}; + +// CCS_CNTLQ +constexpr const uint64_t CCS_CNTLQ_REG[] = +{ + MCBIST_0_CCS_CNTLQ, + MCBIST_1_CCS_CNTLQ, +}; + constexpr uint8_t PORTS_PER_MODULE = 8; +constexpr uint8_t PORTS_PER_MCBIST = 4; +constexpr uint8_t MCBISTS_PER_PROC = 2; /// -/// @brief Helper for trigger_csave. This subroutine puts the MCA into STR -/// This is the same thing as mss::nvdimm::self_refresh_entry() but rewritten -/// to support SBE +/// @brief Program the necessary scom regs to prepare for CSAVE /// @param[in] i_target - PROC_CHIP target -/// @param[in] l_mca_pos - The MCA position relative to the PROC +/// @param[in] i_mcbist - mcbist position relative to the proc +/// @param[out] o_addresses - list of addresses that require restore +/// @param[out] o_data - data to restore to o_addresses /// @return FAPI2_RC_SUCCESS iff setup was successful /// -fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - const uint8_t l_mca_pos) +fapi2::ReturnCode prep_for_csave( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mcbist, + std::vector<uint64_t>& o_addresses, + std::vector<fapi2::buffer<uint64_t>>& o_data) { - FAPI_ASSERT((l_mca_pos < PORTS_PER_MODULE), - fapi2::MSS_SRE_MCA_OUT_OF_RANGE(). - set_PROC_TARGET(i_target). - set_MCA_POS(l_mca_pos), - "Invalid port number %u provided", l_mca_pos); + fapi2::buffer<uint64_t> l_mcbcntlq_data; + fapi2::buffer<uint64_t> l_mcbagraq_data; + fapi2::buffer<uint64_t> l_ccs_modeq_data; - FAPI_DBG("Entering STR on port %u.", l_mca_pos); + // Stop mcbist first otherwise it can kick the DIMM out of STR + FAPI_TRY(fapi2::getScom(i_target, MCB_CNTLQ_REG[i_mcbist], l_mcbcntlq_data)); + l_mcbcntlq_data.setBit<MCBIST_CCS_CNTLQ_STOP>(); + FAPI_TRY(fapi2::putScom(i_target, MCB_CNTLQ_REG[i_mcbist], l_mcbcntlq_data)); - { - fapi2::buffer<uint64_t> l_mbarpc0_data, l_mbastr0_data, l_mcbcntlq_data; - constexpr uint64_t ENABLE = 1; - constexpr uint64_t DISABLE = 0; - constexpr uint64_t MAXALL_MIN0 = 0b010; - constexpr uint64_t STOP = 1; - constexpr uint64_t PORTS_PER_MCBIST = 4; - constexpr uint64_t TIME_0 = 0; - const uint8_t l_mcbist = l_mca_pos < PORTS_PER_MCBIST ? 0 : 1; - - // Stop mcbist first otherwise it can kick the DIMM out of STR - FAPI_TRY(fapi2::getScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data)); - l_mcbcntlq_data.writeBit<MCBIST_CCS_CNTLQ_STOP>(STOP); - FAPI_TRY(fapi2::putScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_mcbcntlq_data)); - - // Step 1 - In MBARPC0Q, disable power domain control, set domain to MAXALL_MIN0, - // and disable minimum domain reduction (allow immediate entry of STR) - FAPI_TRY(fapi2::getScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data)); - l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE>(DISABLE); - l_mbarpc0_data.insertFromRight<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS, MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_LEN>(MAXALL_MIN0); - l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_DOMAIN_REDUCTION_ENABLE>(DISABLE); - FAPI_TRY(fapi2::putScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data)); - - // Step 2 - In MBASTR0Q, enable STR entry - FAPI_TRY(fapi2::getScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data)); - l_mbastr0_data.writeBit<MCA_MBASTR0Q_CFG_STR_ENABLE>(ENABLE); - l_mbastr0_data.insertFromRight<MCA_MBASTR0Q_CFG_ENTER_STR_TIME, MCA_MBASTR0Q_CFG_ENTER_STR_TIME_LEN>(TIME_0); - FAPI_TRY(fapi2::putScom(i_target, MBASTR0Q_REG[l_mca_pos], l_mbastr0_data)); - - // Step 3 - In MBARPC0Q, enable power domain control. - l_mbarpc0_data.writeBit<MCA_MBARPC0Q_CFG_MIN_MAX_DOMAINS_ENABLE>(ENABLE); - FAPI_TRY(fapi2::putScom(i_target, MBARPC0Q_REG[l_mca_pos], l_mbarpc0_data)); - } + // Backup the address and data for the following scoms to restore later + + // Disable maint. address mode + FAPI_TRY(fapi2::getScom(i_target, MCB_MCBAGRAQ_REG[i_mcbist], l_mcbagraq_data)); + o_addresses.push_back(MCB_MCBAGRAQ_REG[i_mcbist]); + o_data.push_back(l_mcbagraq_data); + l_mcbagraq_data.clearBit<MCBIST_MCBAGRAQ_CFG_MAINT_ADDR_MODE_EN>(); + FAPI_TRY(fapi2::putScom(i_target, MCB_MCBAGRAQ_REG[i_mcbist], l_mcbagraq_data)); + + // Required for CCS to drive RESETn + FAPI_TRY(fapi2::getScom(i_target, CCS_MODEQ_REG[i_mcbist], l_ccs_modeq_data)); + o_addresses.push_back(CCS_MODEQ_REG[i_mcbist]); + o_data.push_back(l_ccs_modeq_data); + l_ccs_modeq_data.setBit<MCBIST_CCS_MODEQ_IDLE_PAT_BANK_2>(); + FAPI_TRY(fapi2::putScom(i_target, CCS_MODEQ_REG[i_mcbist], l_ccs_modeq_data)); fapi_try_exit: return fapi2::current_err; } /// -/// @brief Helper for trigger_csave. This subroutine assert RESET_n to trigger -/// the backup on nvdimm -/// @param[in] i_target - PROC_CHIP targetdefine -/// @param[in] l_mca_pos - The MCA position relative to the PROC +/// @brief Start or stop CCS +/// @param[in] i_target - PROC_CHIP target +/// @param[in] i_mcbist - mcbist position relative to the proc +/// @param[in] i_start_stop - start or stop CCS /// @return FAPI2_RC_SUCCESS iff setup was successful /// -fapi2::ReturnCode assert_resetn( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint8_t l_mca_pos) +fapi2::ReturnCode start_stop_ccs( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mcbist, + const uint8_t i_start_stop) { - FAPI_ASSERT((l_mca_pos < PORTS_PER_MODULE), - fapi2::MSS_RESETN_MCA_OUT_OF_RANGE(). + fapi2::buffer<uint64_t> l_data; + constexpr uint8_t START = 1; + + FAPI_TRY(fapi2::getScom(i_target, CCS_CNTLQ_REG[i_mcbist], l_data)); + FAPI_TRY(fapi2::putScom(i_target, CCS_CNTLQ_REG[i_mcbist], + i_start_stop == START ? l_data.setBit<MCBIST_CCS_CNTLQ_START>() : l_data.setBit<MCBIST_CCS_CNTLQ_STOP>())); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Select which port to run CCS on +/// @param[in] i_target - PROC_CHIP target +/// @param[in] i_mca - mca position relative to the proc +/// @param[out] o_addresses - list of addresses that require restore +/// @param[out] o_data - data to restore to o_addresses +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode select_port(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mca, + std::vector<uint64_t>& o_addresses, + std::vector<fapi2::buffer<uint64_t>>& o_data) +{ + FAPI_ASSERT((i_mca < PORTS_PER_MODULE), + fapi2::MSS_SELECT_PORT_MCA_OUT_OF_RANGE(). set_PROC_TARGET(i_target). - set_MCA_POS(l_mca_pos), - "Invalid port number %u provided", l_mca_pos); + set_MCA_POS(i_mca), + "Invalid port number %u provided", i_mca); + { + // MCB_CNTLQ[2:5]. Default to port 0 then shift right as needed + constexpr uint8_t PORT_0 = 0b1000; + const uint64_t l_port_sel = PORT_0 >> (i_mca % PORTS_PER_MCBIST); + const uint8_t l_mcbist = i_mca < PORTS_PER_MCBIST ? 0 : 1; + fapi2::buffer<uint64_t> l_data; - FAPI_DBG("Asserting RESETn on port %d.", l_mca_pos); + FAPI_TRY(fapi2::getScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_data)); + l_data.insertFromRight<MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL, MCBIST_MCB_CNTLQ_MCBCNTL_PORT_SEL_LEN>(l_port_sel); + FAPI_TRY(fapi2::putScom(i_target, MCB_CNTLQ_REG[l_mcbist], l_data)); + // For each port, set the address mux to CCS and enable CCS to drive RESETn + FAPI_TRY(fapi2::getScom(i_target, FARB5Q_REG[i_mca], l_data)); + o_addresses.push_back(FARB5Q_REG[i_mca]); + o_data.push_back(l_data); + l_data.setBit<MCA_MBA_FARB5Q_CFG_CCS_ADDR_MUX_SEL>(); + l_data.setBit<MCA_MBA_FARB5Q_CFG_CCS_INST_RESET_ENABLE>(); + FAPI_TRY(fapi2::putScom(i_target, FARB5Q_REG[i_mca], l_data)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief change the BAR valid state on MCS with NVDIMM installed +/// @param[in] i_target - PROC_CHIP target +/// @param[in] i_port_bitmap - port bitmap that indicates port with nvdimm +/// @param[in] i_state - BAR state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::buffer<uint8_t> i_port_bitmap, + const uint64_t i_state) +{ + for (uint8_t l_mca_pos = 0; l_mca_pos < PORTS_PER_MODULE; l_mca_pos++) { - fapi2::buffer<uint64_t> l_farb5q_data; - constexpr uint64_t LOW = 0; + if (i_port_bitmap.getBit(l_mca_pos) == fapi2::ENUM_ATTR_SBE_NVDIMM_IN_PORT_YES) + { + const uint8_t l_mcs = l_mca_pos / 2; + fapi2::buffer<uint64_t> l_data; - FAPI_TRY(fapi2::getScom(i_target, FARB5Q_REG[l_mca_pos], l_farb5q_data)); - l_farb5q_data.writeBit<MCA_MBA_FARB5Q_CFG_DDR_RESETN>(LOW); - FAPI_TRY(fapi2::putScom(i_target, FARB5Q_REG[l_mca_pos], l_farb5q_data)); + FAPI_TRY(fapi2::getScom(i_target, MCFGP[l_mcs], l_data)); + l_data.writeBit<MCS_MCFGP_VALID>(i_state); + FAPI_TRY(fapi2::putScom(i_target, MCFGP[l_mcs], l_data)); + } } fapi_try_exit: @@ -195,23 +249,70 @@ fapi_try_exit: fapi2::ReturnCode trigger_csave( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ) { fapi2::buffer<uint8_t> l_nvdimm_port_bitmap = 0; + constexpr uint64_t INVALID = 0; + constexpr uint64_t VALID = 1; + constexpr uint8_t START = 1; + constexpr uint8_t STOP = 0; + constexpr uint64_t MS_IN_NS = 1000000; + const uint64_t DELAY_20MS_IN_NS = 20 * MS_IN_NS; FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_SBE_NVDIMM_IN_PORT, i_target, l_nvdimm_port_bitmap) ); - for (uint8_t l_mca_pos = 0; l_mca_pos < PORTS_PER_MODULE; l_mca_pos++) + // Invalidate the BAR temporarily. This prevents any memory access (proc, IO, etc.) from + // remove the port out of STR + FAPI_TRY( change_bar_valid_state(i_target, l_nvdimm_port_bitmap, INVALID)); + + // Get all the mcbists/mcas with NVDIMM + for (uint8_t l_mcbist = 0; l_mcbist < MCBISTS_PER_PROC; l_mcbist++) { - if (l_nvdimm_port_bitmap.getBit(l_mca_pos) == fapi2::ENUM_ATTR_SBE_NVDIMM_IN_PORT_YES) + std::vector<uint8_t> l_mcas; + std::vector<uint64_t> l_addresses; + std::vector<fapi2::buffer<uint64_t>> l_data; + const uint8_t MCA_STARTING_POS = (PORTS_PER_MCBIST * l_mcbist); + + // For each mcbist, gather a list of mcas with nvdimm installed + for (uint8_t l_mca_pos = 0 + MCA_STARTING_POS; + l_mca_pos < PORTS_PER_MCBIST + MCA_STARTING_POS; + l_mca_pos++) { - FAPI_DBG("NVDIMM found in port %d ", l_mca_pos); + if (l_nvdimm_port_bitmap.getBit(l_mca_pos) == fapi2::ENUM_ATTR_SBE_NVDIMM_IN_PORT_YES) + { + l_mcas.push_back(l_mca_pos); + } + } - // Enter STR - FAPI_TRY(self_refresh_entry(i_target, l_mca_pos)); + // Nothing to do + if (l_mcas.empty()) + { + FAPI_DBG("No mca with nvdimm detect. l_mcbist = 0x%x, l_mcas.size = %u", + l_mcbist, l_mcas.size()); + continue; + } + + // Prep mcbist/ccs for csave + FAPI_TRY( prep_for_csave(i_target, l_mcbist, l_addresses, l_data)); - // Assert ddr_resetn - FAPI_TRY(assert_resetn(i_target, l_mca_pos)); + // Start and stop CCS, one port at a time. + for (const auto l_mca : l_mcas) + { + FAPI_TRY( select_port(i_target, l_mca, l_addresses, l_data), "Error returned from select_port(). l_mca = %u", l_mca); + FAPI_TRY( start_stop_ccs(i_target, l_mcbist, START), "Error to START from start_stop_ccs()"); + FAPI_TRY( fapi2::delay(DELAY_20MS_IN_NS, 0), "Error returned from fapi2::delay call"); + FAPI_TRY( start_stop_ccs(i_target, l_mcbist, STOP), "Error to STOP from start_stop_ccs()"); + } + + // Restore the original value. This is a don't care for poweroff/warm reboot, + // needed for MPIPL + for (size_t index = 0; index < l_addresses.size(); index++) + { + FAPI_TRY(fapi2::putScom(i_target, l_addresses[index], l_data[index])); } } + // Set the BAR back to valid. This is a don't care for the power down but required + // for MPIPL. + FAPI_TRY( change_bar_valid_state(i_target, l_nvdimm_port_bitmap, VALID)); + fapi_try_exit: return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.H index a5d1b4a07..39952ddf8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/nvdimm_workarounds.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -58,27 +58,55 @@ typedef fapi2::ReturnCode (*p9_flush_nvdimm_FP_t) (const fapi2::Target<fapi2::TA /// @param[in] i_target - PROC_CHIP target /// @return FAPI2_RC_SUCCESS iff setup was successful /// - fapi2::ReturnCode trigger_csave( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ); /// -/// @brief Helper for trigger_csave. This subroutine assert RESET_n to trigger -/// the backup on nvdimm +/// @brief Program the necessary scom regs to prepare for CSAVE /// @param[in] i_target - PROC_CHIP target -/// @param[in] l_mca_pos - The MCA position relative to the PROC +/// @param[in] i_mcbist - mcbist position relative to the proc +/// @param[out] o_addresses - list of addresses that require restore +/// @param[out] o_data - data to restore to o_addresses /// @return FAPI2_RC_SUCCESS iff setup was successful /// +fapi2::ReturnCode prep_for_csave( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mcbist, + std::vector<uint64_t>& o_addresses, + std::vector<fapi2::buffer<uint64_t>>& o_data); -fapi2::ReturnCode assert_resetn( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, uint8_t l_mca_pos); +/// +/// @brief Select which port to run CCS on +/// @param[in] i_target - PROC_CHIP target +/// @param[in] i_mca - mca position relative to the proc +/// @param[out] o_addresses - list of addresses that require restore +/// @param[out] o_data - data to restore to o_addresses +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode select_port(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mca, + std::vector<uint64_t>& o_addresses, + std::vector<fapi2::buffer<uint64_t>>& o_data); /// -/// @brief Helper for trigger_csave. This subroutine puts the MCA into STR +/// @brief Start or stop CCS /// @param[in] i_target - PROC_CHIP target -/// @param[in] l_mca_pos - The MCA position relative to the PROC +/// @param[in] i_mcbist - mcbist position relative to the proc +/// @param[in] i_start_stop - start or stop CCS /// @return FAPI2_RC_SUCCESS iff setup was successful /// +fapi2::ReturnCode start_stop_ccs( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t i_mcbist, + const bool i_start_stop); -fapi2::ReturnCode self_refresh_entry( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, uint8_t l_mca_pos); +/// +/// @brief change the BAR valid state on MCS with NVDIMM installed +/// @param[in] i_target - PROC_CHIP target +/// @param[in] i_port_bitmap - port bitmap that indicates port with nvdimm +/// @param[in] i_state - BAR state to change to +/// @return FAPI2_RC_SUCCESS iff setup was successful +/// +fapi2::ReturnCode change_bar_valid_state( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::buffer<uint8_t> i_port_bitmap, + const uint64_t i_state); }//ns nvdimm }//ns workarounds diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C new file mode 100644 index 000000000..cf13e917a --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C @@ -0,0 +1,256 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file quad_encode_workarounds.C +/// @brief Contains workarounds having to do with quad-encode CS +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB Memory Lab + +#include <lib/shared/nimbus_defaults.H> +#include <fapi2.H> +#include <p9n2_mc_scom_addresses.H> + +#include <generic/memory/lib/utils/c_str.H> +#include <lib/utils/nimbus_find.H> +#include <lib/ccs/ccs_traits_nimbus.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/mss_attribute_accessors.H> +#include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <lib/workarounds/quad_encode_workarounds.H> + +namespace mss +{ + +namespace workarounds +{ + +const std::vector< uint64_t> shadow_regs_traits<0>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR0_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR0_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR0_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR0_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<1>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR1_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR1_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR1_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR1_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<2>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR2_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR2_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR2_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR2_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<3>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR3_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR3_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR3_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR3_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<4>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR4_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR4_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR4_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR4_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<5>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR5_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR5_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR5_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR5_RP3_P0, +}; +const std::vector< uint64_t> shadow_regs_traits<6>::REGS = +{ + P9N2_MCA_DDRPHY_PC_MR6_RP0_P0, + P9N2_MCA_DDRPHY_PC_MR6_RP1_P0, + P9N2_MCA_DDRPHY_PC_MR6_RP2_P0, + P9N2_MCA_DDRPHY_PC_MR6_RP3_P0, +}; + +/// +/// @brief Returns true if an MRS command was run +/// @param[in] i_inst instruction to check for an MRS command +/// @return true iff the command contains an MRS command +/// +bool is_command_mrs(const ccs::instruction_t& i_inst) +{ + // An MRS command is + // 1) at least one chip select active + // 2) at ACT HI, RAS/CAS/WEN low + // 3) not BA7 + + const auto l_cs_low = !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1>() || + !i_inst.arr0.getBit < MCBIST_CCS_INST_ARR0_00_DDR_CSN_0_1 + 1 > () || + !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3>() || + !i_inst.arr0.getBit < MCBIST_CCS_INST_ARR0_00_DDR_CSN_2_3 + 1 > (); + + const auto l_mrs_cmd = i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_ACTN>() && + !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_16>() && + !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_15>() && + !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_ADDRESS_14>(); + + const auto l_mrs_ba = !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1>() || + !i_inst.arr0.getBit < MCBIST_CCS_INST_ARR0_00_DDR_BANK_0_1 + 1 > () || + !i_inst.arr0.getBit<MCBIST_CCS_INST_ARR0_00_DDR_BANK_GROUP_0>(); + return l_cs_low && l_mrs_cmd && l_mrs_ba; +} +/// +/// @brief Returns true if a vector of commands contains an MRS command +/// @param[in] i_inst instruction to check for an MRS command +/// @return true iff the command contains an MRS command +/// +bool contains_command_mrs(const std::vector<ccs::instruction_t>& i_inst) +{ + bool l_contains_mrs = false; + + for(const auto& l_inst : i_inst) + { + l_contains_mrs = is_command_mrs(l_inst); + + if(l_contains_mrs) + { + FAPI_DBG("0x%016lx is an MRS command. Exiting", uint64_t(l_inst.arr0)); + break; + } + } + + return l_contains_mrs; +} + +/// +/// @brief Fixes shadow register corruption over all ranks if needed +/// @param[in] i_target - the DIMM target on which to operate +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// +fapi2::ReturnCode fix_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target) +{ + std::vector< uint64_t > l_ranks; + FAPI_TRY(mss::rank::primary_ranks( i_target, l_ranks )); + + for(const auto l_rank : l_ranks) + { + FAPI_TRY(fix_shadow_register_corruption(i_target, l_rank)); + } + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Fixes shadow register corruption if needed +/// @param[in] i_target - the DIMM target on which to operate +/// @param[in] i_rank - the rank on which to operate +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// +fapi2::ReturnCode fix_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint64_t i_rank) +{ + fapi2::Target<fapi2::TARGET_TYPE_DIMM> l_dimm; + const auto l_dimm_rank = mss::index(i_rank); + uint64_t l_rp = 0; + bool l_fix_needed = false; + + // In this case, the rank is really to get the DIMM in question + FAPI_TRY(mss::rank::get_dimm_target_from_rank(i_target, i_rank, l_dimm), + "%s failed to get DIMM from rank%u", mss::c_str(i_target), i_rank); + + FAPI_TRY(check_shadow_register_corruption(l_dimm, i_rank, l_fix_needed), + "%s failed to check if the fix is needed", mss::c_str(i_target)); + + // If the fix isn't needed, exit out + if(!l_fix_needed) + { + FAPI_INF("%s workaround not needed. Skipping", mss::c_str(i_target)); + return fapi2::FAPI2_RC_SUCCESS; + } + + // Shadow registers are on a per-rank pair basis + FAPI_TRY(mss::rank::get_pair_from_rank(i_target, i_rank, l_rp), + "%s rank%u failed to get RP nominal values", mss::c_str(i_target), i_rank); + + FAPI_TRY(fix_shadow_register_corruption_mr<0>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR0", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<1>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR1", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<2>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR2", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<3>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR3", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<4>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR4", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<5>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR5", mss::c_str(i_target)); + FAPI_TRY(fix_shadow_register_corruption_mr<6>(l_dimm, l_rp, l_dimm_rank), + "%s failed to fix shadow regs on MR6", mss::c_str(i_target)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @param[in] i_target - the DIMM target on which to operate +/// @param[in] i_rank - the rank on which to operate +/// @param[out] o_fix_needed - true iff the shadow register's could be corrupted (aka are we a 4R DIMM?) +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// + +fapi2::ReturnCode check_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + bool& o_fix_needed) +{ + // Number of master ranks for this DIMM - if we have 4, we need the workaround + // Also, always run the workaround if we have an LRDIMM + constexpr uint8_t RANKS_FOR_FIX_NEEDED = 4; + uint8_t l_master_ranks = 0; + uint8_t l_dimm_type = 0; + o_fix_needed = false; + + FAPI_TRY(mss::eff_num_master_ranks_per_dimm(i_target, l_master_ranks), "%s failed to get master ranks", + mss::c_str(i_target)); + FAPI_TRY(mss::eff_dimm_type(i_target, l_dimm_type), "%s failed to get dimm_type", + mss::c_str(i_target)); + o_fix_needed = (l_master_ranks == RANKS_FOR_FIX_NEEDED) || + (l_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM); + FAPI_INF("%s workaround %s needed. num master ranks %u dimm type %u", mss::c_str(i_target), o_fix_needed ? "is" : "not", + l_master_ranks, l_dimm_type); + +fapi_try_exit: + return fapi2::current_err; +} + +} // ns workarounds +} // ns mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H new file mode 100644 index 000000000..1d7ea180f --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H @@ -0,0 +1,373 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/workarounds/quad_encode_workarounds.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file quad_encode_workaround.H +/// @brief Contains workarounds having to do with quad-encode CS +/// +// *HWP HWP Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 3 +// *HWP Consumed by: FSP:HB Memory Lab + +#ifndef _QUAD_ENCODE_WORKAROUND_H_ +#define _QUAD_ENCODE_WORKAROUND_H_ + +#include <fapi2.H> +#include <p9_mc_scom_addresses.H> + +#include <lib/shared/mss_const.H> +#include <generic/memory/lib/utils/c_str.H> +#include <lib/utils/nimbus_find.H> +#include <generic/memory/lib/ccs/ccs.H> +#include <lib/dimm/rank.H> +#include <lib/dimm/ddr4/mrs_load_ddr4.H> +#include <p9_mc_scom_addresses_fld.H> + +namespace mss +{ + +namespace workarounds +{ + +static constexpr uint64_t MAX_MR = 6; + +/// +/// @brief Fixes shadow register corruption over all ranks if needed +/// @param[in] i_target - the DIMM target on which to operate +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// +fapi2::ReturnCode fix_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target); + +/// +/// @brief Fixes shadow register corruption if needed +/// @param[in] i_target - the DIMM target on which to operate +/// @param[in] i_rank - the rank on which to operate +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// +fapi2::ReturnCode fix_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target, + const uint64_t i_rank); + +/// +/// @param[in] i_target - the DIMM target on which to operate +/// @param[in] i_rank - the rank on which to operate +/// @param[out] o_fix_needed - true iff the shadow register's could be corrupted (aka are we a 4R DIMM?) +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// + +fapi2::ReturnCode check_shadow_register_corruption( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rank, + bool& o_fix_needed); + +/// +/// @brief Returns true if an MRS command was run +/// @param[in] i_inst instruction to check for an MRS command +/// @return true iff the command contains an MRS command +/// +bool is_command_mrs(const ccs::instruction_t& i_inst); + +/// +/// @brief Returns true if a vector of commands contains an MRS command +/// @param[in] i_inst instruction to check for an MRS command +/// @return true iff the command contains an MRS command +/// +bool contains_command_mrs(const std::vector<ccs::instruction_t>& i_inst); + +/// +/// @brief Converts the CCS instructions to the shadow register configuration +/// @param[in] i_inst CCS instruction to convert +/// @return the register value for the shadow register +/// +inline fapi2::buffer<uint64_t> convert_to_shadow_reg(const ccs::instruction_t& i_inst) +{ + fapi2::buffer<uint64_t> l_arr0(i_inst.arr0); + mss::reverse(l_arr0); + constexpr uint64_t SHADOW_REG_START = 50; + l_arr0.clearBit<0, SHADOW_REG_START>(); + return l_arr0; +} + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register +/// @tparam MR the MR number for which to fix the shadow regs +/// +template< uint64_t MR > +class shadow_regs_traits; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR0 +/// +template<> +class shadow_regs_traits<0> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + constexpr uint8_t LR_2666_MARGIN_ADJUST = 2; + + // So, why is MRS0 being reset differently compared to the other mode register sets? + // For LRDIMM, at 2666, we're running at the edge of the PHY's capabilities to account for the read delay + // This means, we've started taking some fails related to not being able to wait long enough for the data to come back + // A handy workaround for this is to increase our CAS latency within the PHY itself by changing the value of the mode register + // This tricks the PHY's snooping capabilities to think that the data is coming back a bit later + // This allows the gate delay and RLO to account for the increased delay correctly + // Note: we need the DRAM to send the data back at the same time, but fake the PHY into thinking that it's coming later + + uint8_t l_dimm_type = 0; + uint64_t l_freq = 0; + + // Check to make sure our ctor worked ok + mss::ddr4::mrs00_data l_data( i_target, fapi2::current_err ); + FAPI_TRY( fapi2::current_err, "%s Unable to construct MRS00 data from attributes", mss::c_str(i_target) ); + FAPI_TRY( mss::eff_dimm_type(i_target, l_dimm_type)); + FAPI_TRY( mss::freq(mss::find_target<fapi2::TARGET_TYPE_MCBIST>(i_target), l_freq)); + + // Apply the CAS latency offset if we have an LRDIMM at 2666 + l_data.iv_cas_latency += ((l_dimm_type == fapi2::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && + (l_freq == fapi2::ENUM_ATTR_MSS_FREQ_MT2666)) ? + LR_2666_MARGIN_ADJUST : 0; + FAPI_TRY( mss::ddr4::mrs00(i_target, l_data, io_inst, i_rank) ); + fapi_try_exit: + return fapi2::current_err; + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR1 +/// +template<> +class shadow_regs_traits<1> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs01(i_target, io_inst, i_rank); + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR2 +/// +template<> +class shadow_regs_traits<2> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs02(i_target, io_inst, i_rank); + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR3 +/// +template<> +class shadow_regs_traits<3> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs03(i_target, io_inst, i_rank); + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR4 +/// +template<> +class shadow_regs_traits<4> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs04(i_target, io_inst, i_rank); + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR5 +/// +template<> +class shadow_regs_traits<5> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs05(i_target, io_inst, i_rank); + }; +}; + +/// +/// @class shadow_regs_traits +/// @brief a collection of traits associated with each shadow register - specialization for MR6 +/// +template<> +class shadow_regs_traits<6> +{ + public: + + static const std::vector<uint64_t> REGS; + + /// + /// @brief Configure the ARR0 of the CCS isntruction for mrs00 + /// @param[in] i_target a fapi2::Target<fapi2::TARGET_TYPE_DIMM> + /// @param[in,out] io_inst the instruction to fixup + /// @param[in] i_rank ths rank in question + /// @return FAPI2_RC_SUCCESS iff OK + /// + static inline fapi2::ReturnCode mrs_gen(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + ccs::instruction_t& io_inst, + const uint64_t i_rank) + { + return mss::ddr4::mrs06(i_target, io_inst, i_rank); + }; +}; + + +/// +/// @brief Fixes shadow register corruption on the associated MR +/// @tparam MR the MR number for which to fix the shadow regs +/// @tparam traits associated with this shadow register +/// @param[in] i_target - the DIMM target on which to operate +/// @param[in] i_rp - the rank pair on which to operate +/// @param[in] i_rank - the rank on which to operate +/// @return fapi2::ReturnCode - SUCCESS iff everything executes successfully +/// +template< uint64_t MR, typename TT = shadow_regs_traits<MR> > +fapi2::ReturnCode fix_shadow_register_corruption_mr( const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, + const uint64_t i_rp, + const uint64_t i_rank) +{ + static_assert( MR <= MAX_MR, "MR instance out of range"); + + ccs::instruction_t l_inst; + const auto& l_mca = mss::find_target<fapi2::TARGET_TYPE_MCA>(i_target); + + // Converts this to DIMM rank. just. in. case. + const auto l_dimm_rank = mss::index(i_rank); + + FAPI_ASSERT( i_rp < MAX_RANK_PAIRS, + fapi2::MSS_INVALID_RANK_PAIR() + .set_RANK_PAIR(i_rp) + .set_FUNCTION(mss::ffdc_function_codes::FIX_SHADOW_REGISTER) + .set_MCA_TARGET(l_mca), + "%s invalid RP %u. Max is %u", + mss::c_str(l_mca), i_rp, MAX_RANK_PAIRS); + + FAPI_TRY(TT::mrs_gen(i_target, l_inst, l_dimm_rank), "%s failed to get MRS%u nominal values", mss::c_str(i_target), MR); + + // Issues the scom to the shadow regiser + FAPI_TRY(mss::putScom(l_mca, TT::REGS[i_rp], convert_to_shadow_reg(l_inst)), + "%s rank%u failed to set the shadow register", mss::c_str(i_target), l_dimm_rank); + + return fapi2::FAPI2_RC_SUCCESS; +fapi_try_exit: + return fapi2::current_err; +} + +} // ns workarounds +} // ns mss + +#endif diff --git a/src/import/chips/p9/procedures/hwp/memory/mss.H b/src/import/chips/p9/procedures/hwp/memory/mss.H index f8c5dabf9..47200a2eb 100644 --- a/src/import/chips/p9/procedures/hwp/memory/mss.H +++ b/src/import/chips/p9/procedures/hwp/memory/mss.H @@ -49,26 +49,26 @@ #include <lib/shared/mss_const.H> #include <lib/shared/mss_kind.H> +#include <lib/ccs/ccs_nimbus.H> #include <generic/memory/lib/utils/index.H> #include <generic/memory/lib/utils/c_str.H> -#include <lib/utils/num.H> +#include <generic/memory/lib/utils/num.H> #include <generic/memory/lib/utils/pos.H> #include <generic/memory/lib/utils/buffer_ops.H> #include <lib/utils/mss_nimbus_conversions.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/poll.H> #include <lib/utils/checker.H> -#include <lib/utils/dump_regs.H> +#include <generic/memory/lib/utils/dump_regs.H> -#include <lib/ccs/ccs.H> #include <lib/mcbist/mcbist.H> #include <lib/dimm/rcd_load.H> #include <lib/dimm/mrs_load.H> #include <lib/dimm/rank.H> -#include <lib/dimm/kind.H> +#include <lib/dimm/nimbus_kind.H> #include <lib/phy/ddr_phy.H> #include <lib/phy/dp16.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_background_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_background_scrub.C index aaf7b6195..e9e4fd0d1 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_background_scrub.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_background_scrub.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,52 +40,32 @@ #include <lib/dimm/rank.H> #include <lib/mcbist/address.H> #include <lib/mcbist/mcbist.H> -#include <lib/mcbist/patterns.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_patterns.H> #include <lib/mcbist/memdiags.H> -#include <lib/mcbist/sim.H> #include <generic/memory/lib/utils/count_dimm.H> -#include <lib/fir/memdiags_fir.H> +#include <lib/fir/unmask.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_SYSTEM; using fapi2::FAPI2_RC_SUCCESS; -/// -/// @brief Begin background scrub -/// @param[in] i_target MCBIST -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode p9_mss_background_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) -{ - FAPI_INF("Start mss background scrub on: %s", mss::c_str( i_target )); - // If there are no DIMM we don't need to bother. In fact, we can't as we didn't setup - // attributes for the PHY, etc. - if (mss::count_dimm(i_target) == 0) - { - FAPI_INF("... skipping background scrub for %s - no DIMM ...", mss::c_str(i_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - - // If we're running in the simulator, we want to only touch the addresses which training touched - uint8_t l_sim = 0; - FAPI_TRY( mss::is_simulation(l_sim) ); +extern "C" +{ - // Kick off background scrub if we are not running in sim - if (!(l_sim)) + /// + /// @brief Begin background scrub + /// @param[in] i_target MCBIST + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode p9_mss_background_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { - // Start background scrub - FAPI_TRY ( mss::memdiags::background_scrub( i_target, - mss::mcbist::stop_conditions(), - mss::mcbist::speed::BG_SCRUB, - mss::mcbist::address() ) ); + FAPI_INF("Start mss background scrub on: %s", mss::c_str( i_target )); + FAPI_TRY(mss::memdiags::mss_background_scrub_helper(i_target)); + fapi_try_exit: + return fapi2::current_err; } - // Unmask firs after background scrub is started - FAPI_TRY ( mss::unmask::after_background_scrub( i_target ) ); - -fapi_try_exit: - return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_bulk_pwr_throttles.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_bulk_pwr_throttles.C index 84cc1c73e..e88962861 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_bulk_pwr_throttles.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_bulk_pwr_throttles.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -32,11 +32,13 @@ // *HWP Team: Memory // *HWP Level: 3 // *HWP Consumed by: FSP:HB + +#include <lib/shared/nimbus_defaults.H> #include <vector> #include <fapi2.H> #include <p9_mss_bulk_pwr_throttles.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/power_thermal/throttle.H> @@ -88,7 +90,7 @@ extern "C" const uint8_t l_pos = mss::index(l_mca); - mss::power_thermal::throttle l_pwr_struct(l_mca, l_rc); + mss::power_thermal::throttle<> l_pwr_struct(l_mca, l_rc); FAPI_TRY(l_rc, "Error constructing mss:power_thermal::throttle object for target %s", mss::c_str(l_mca)); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C index 27b616a72..8d439b9d8 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_ddr_phy_reset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,6 +33,7 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> #include <stdint.h> #include <string.h> @@ -198,7 +199,7 @@ extern "C" // The algorithm is 'good path do after_phy_reset, all paths (error or not) perform the checks // which are defined in during_phy_reset'. We won't run after_phy_reset (unmask of FIR) unless // we're done with a success. - FAPI_TRY( mss::unmask::after_phy_reset<mss::mc_type::NIMBUS>(i_target), "%s Error in p9_mss_ddr_phy_reset.C", + FAPI_TRY( mss::unmask::after_phy_reset(i_target), "%s Error in p9_mss_ddr_phy_reset.C", mss::c_str(i_target) ); // Leave as we're all good and checked the FIR already ... diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C index 559593111..62a9e3114 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit.C @@ -60,10 +60,6 @@ extern "C" { fapi2::buffer<uint64_t> l_data; - mss::ccs::instruction_t<TARGET_TYPE_MCBIST> l_des = mss::ccs::des_command<TARGET_TYPE_MCBIST>(); - - mss::ccs::program<TARGET_TYPE_MCBIST> l_program; - // Up, down P down, up N. Somewhat magic numbers - came from Centaur and proven to be the // same on Nimbus. Why these are what they are might be lost to time ... constexpr uint64_t PCLK_INITIAL_VALUE = 0b10; @@ -158,16 +154,10 @@ extern "C" mss::c_str(i_target) ); } - // Also a Deselect command must be registered as required from the Spec. - // Register DES instruction, which pulls CKE high. Idle 400 cycles, and then begin RCD loading - // Note: This only is sent to one of the MCA as we still have the mux_addr_sel bit set, meaning - // we'll PDE/DES all DIMM at the same time. - l_des.arr1.insertFromRight<MCBIST_CCS_INST_ARR1_00_IDLES, MCBIST_CCS_INST_ARR1_00_IDLES_LEN>(400); - l_program.iv_instructions.push_back(l_des); - - FAPI_TRY( mss::ccs::execute(i_target, l_program, l_mcas[0]), - "%s Failed execute in p9_mss_draminit", - mss::c_str(i_target) ); + // Holds our CKE high for 400 cycles - required by the JEDEC spec + FAPI_TRY( mss::draminit_cke_helper(l_mcas[0]), + "%s Failed to hold CKE high in p9_mss_draminit", + mss::c_str(i_target)); // Per conversation with Shelton and Steve 10/9/15, turn off addr_mux_sel after the CKE CCS but // before the RCD/MRS CCSs diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C index 66892c8bd..22a6bacb4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_mc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,13 +33,14 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <mss.H> #include <p9_mc_scom_addresses_fld.H> #include <p9_mss_draminit_mc.H> #include <lib/fir/unmask.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/workarounds/mca_workarounds.H> @@ -87,7 +88,6 @@ extern "C" for(const auto& l_mca : mss::find_targets<fapi2::TARGET_TYPE_MCA>(i_target)) { FAPI_TRY(mss::workarounds::str_non_tsv_parity(l_mca)); - FAPI_TRY(mss::configure_cid_parity(l_mca)); } // TODO:RTC179508 - Cleanup draminit_mc @@ -140,14 +140,14 @@ extern "C" FAPI_TRY( mss::enable_periodic_cal(p), "%s Failed enable_periodic_cal", mss::c_str(i_target) ); // Step Six: Setup Control Bit ECC - FAPI_TRY( mss::enable_read_ecc(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::enable_read_ecc<mss::mc_type::NIMBUS>(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); // apply marks from MVPD - FAPI_TRY( mss::apply_mark_store(p), "%s Failed enable_read_ecc", mss::c_str(i_target) ); + FAPI_TRY( mss::apply_mark_store(p), "%s Failed apply_mark_store", mss::c_str(i_target) ); } // At this point the DDR interface must be monitored for memory errors. Memory related FIRs should be unmasked. - FAPI_TRY( mss::unmask::after_draminit_mc<mss::mc_type::NIMBUS>(i_target), "%s Failed after_draminit_mc", + FAPI_TRY( mss::unmask::after_draminit_mc(i_target), "%s Failed after_draminit_mc", mss::c_str(i_target) ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C index e4084b461..0a13ac90c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training.C @@ -33,6 +33,7 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <mss.H> #include <vector> @@ -212,7 +213,7 @@ extern "C" // We do it here in order to train every port FAPI_TRY( mss::draminit_training_error_handler(l_fails) ); // Unmask FIR - FAPI_TRY( mss::unmask::after_draminit_training<mss::mc_type::NIMBUS>(i_target), "Error in p9_mss_draminit" ); + FAPI_TRY( mss::unmask::after_draminit_training(i_target), "Error in p9_mss_draminit" ); fapi_try_exit: FAPI_INF("End draminit training"); diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C index 95a662883..67c3074a2 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_draminit_training_adv.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,6 +43,7 @@ #include <lib/phy/seq.H> #include <lib/phy/ddr_phy.H> #include <lib/phy/mss_training.H> +#include <lib/workarounds/dp16_workarounds.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; @@ -125,6 +126,9 @@ extern "C" { FAPI_TRY( l_step->execute(p, rp, l_cal_abort_on_error) ); } + + // Adjusts values for NVDIMM's + FAPI_TRY(mss::workarounds::nvdimm::adjust_rd_dq_delay(p, rp)); }// rank pairs // Resetting current_err. diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C index 7ce96a63d..9a8217e52 100755 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config.C @@ -42,10 +42,11 @@ #include <fapi2.H> // mss lib +#include <lib/shared/nimbus_defaults.H> #include <generic/memory/lib/spd/common/ddr4/spd_decoder_ddr4.H> #include <generic/memory/lib/utils/pos.H> #include <lib/utils/checker.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/shared/mss_kind.H> #include <lib/dimm/eff_dimm.H> #include <lib/eff_config/plug_rules.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C index bd5819fd2..b9d63f3fc 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_eff_config_thermal.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -33,13 +33,13 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> #include <fapi2.H> #include <vector> #include <p9_mss_eff_config_thermal.H> #include <p9_mss_bulk_pwr_throttles.H> #include <lib/power_thermal/throttle.H> #include <lib/power_thermal/decoder.H> -#include <lib/dimm/kind.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/shared/mss_const.H> #include <mss.H> @@ -52,12 +52,14 @@ extern "C" /// @note sets ATTR_MSS_MEM_WATT_TARGET, ATTR_MSS_RUNTIME_MEM_THROTTLED_N_COMMANDS_PER_PORT and _PER_SLOT, and ATTR_MSS_PORT_MAXPOWER fapi2::ReturnCode p9_mss_eff_config_thermal( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCS> >& i_targets ) { + using TT = mss::power_thermal::throttle_traits<mss::mc_type::NIMBUS>; + FAPI_INF("Start effective config thermal"); fapi2::ReturnCode l_rc; - std::vector< uint64_t > l_slope (mss::power_thermal::SIZE_OF_POWER_CURVES_ATTRS, 0); - std::vector< uint64_t > l_intercept (mss::power_thermal::SIZE_OF_POWER_CURVES_ATTRS, 0); - std::vector< uint64_t > l_thermal_power_limit (mss::power_thermal::SIZE_OF_THERMAL_ATTR, 0); + std::vector< uint64_t > l_slope (TT::SIZE_OF_POWER_CURVES_ATTRS, 0); + std::vector< uint64_t > l_intercept (TT::SIZE_OF_POWER_CURVES_ATTRS, 0); + std::vector< uint64_t > l_thermal_power_limit (TT::SIZE_OF_THERMAL_ATTR, 0); uint16_t l_vddr_slope [mss::PORTS_PER_MCS][mss::MAX_DIMM_PER_PORT] = {}; uint16_t l_vddr_int [mss::PORTS_PER_MCS][mss::MAX_DIMM_PER_PORT] = {}; @@ -75,19 +77,21 @@ extern "C" // Return error if safemode throttle utilization is less than MIN_UTIL // This section needs to be in braces otherwise the compile will fail { + using TT = mss::power_thermal::throttle_traits<>; + const uint64_t l_min_util = TT::MIN_UTIL; uint16_t l_throttle_per_port = 0; uint32_t l_throttle_denominator = 0; FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_throttle_denominator), "Error in p9_mss_eff_config_thermal" ); FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_throttle_per_port), "Error in p9_mss_eff_config_thermal" ); - FAPI_ASSERT( (l_throttle_per_port >= (mss::power_thermal::MIN_UTIL * l_throttle_denominator / + FAPI_ASSERT( (l_throttle_per_port >= (TT::MIN_UTIL * l_throttle_denominator / mss::power_thermal::DRAM_BUS_UTILS / mss::power_thermal::UTIL_CONVERSION)), fapi2::MSS_MRW_SAFEMODE_THROTTLE_NOT_SUPPORTED() .set_MRW_SAFEMODE_N_VALUE(l_throttle_per_port) .set_MRW_DRAM_CLOCK_THROTTLE_M(l_throttle_denominator) - .set_MIN_UTIL_VALUE(mss::power_thermal::MIN_UTIL), + .set_MIN_UTIL_VALUE(l_min_util), "MRW safemode attribute (N=%d, M=%d) has less util than the min util allowed (%d centi percent)", - l_throttle_per_port, l_throttle_denominator, mss::power_thermal::MIN_UTIL); + l_throttle_per_port, l_throttle_denominator, l_min_util); } //Restore runtime_throttles from safemode setting diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C index 7d770fc13..6c24fd182 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq.C @@ -48,7 +48,7 @@ #include <lib/freq/nimbus_freq_traits.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/freq/gen_mss_freq.H> -#include <generic/memory/lib/data_engine/pre_data_init.H> +#include <lib/eff_config/pre_data_init.H> using fapi2::TARGET_TYPE_MCS; using fapi2::TARGET_TYPE_MCA; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C index cba559c16..7721c724d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_freq_system.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,7 +39,7 @@ #include <mss.H> #include <p9_mss_freq_system.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/freq/sync.H> diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C index 150f725a3..80b54d1ff 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_memdiag.C @@ -39,16 +39,15 @@ #include <lib/dimm/rank.H> #include <generic/memory/lib/utils/poll.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <generic/memory/lib/utils/count_dimm.H> #include <lib/mcbist/address.H> -#include <lib/mcbist/patterns.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_patterns.H> #include <lib/mcbist/memdiags.H> #include <lib/mcbist/mcbist.H> #include <lib/mc/port.H> -#include <lib/mcbist/sim.H> -#include <lib/ecc/ecc.H> -#include <lib/fir/memdiags_fir.H> +#include <lib/fir/unmask.H> +#include <generic/memory/lib/ecc/ecc.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_SYSTEM; @@ -181,7 +180,7 @@ extern "C" l_probes); FAPI_ASSERT( l_poll_results == true, - fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), + fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT().set_MC_TARGET(i_target), "p9_mss_memdiag (init) timedout %s", mss::c_str(i_target) ); // Unmask firs after memdiags and turn off FIFO mode diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C index 3ee15dc3b..9dc8d134c 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scominit.C @@ -40,11 +40,11 @@ #include <p9n_mcbist_scom.H> #include <p9n_ddrphy_scom.H> #include <generic/memory/lib/utils/count_dimm.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/phy/ddr_phy.H> #include <lib/mc/mc.H> #include <lib/fir/unmask.H> -#include <generic/memory/lib/utils/find_magic.H> +#include <lib/utils/find_magic.H> using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_MCBIST; @@ -119,7 +119,7 @@ fapi2::ReturnCode p9_mss_scominit( const fapi2::Target<TARGET_TYPE_MCBIST>& i_ta FAPI_TRY( mss::phy_scominit(i_target), "%s failed phy_scominit", mss::c_str(i_target) ); // Do FIRry things - FAPI_TRY( mss::unmask::after_scominit<mss::mc_type::NIMBUS>(i_target), "%s failed after_scominit", + FAPI_TRY( mss::unmask::after_scominit(i_target), "%s failed after_scominit", mss::c_str(i_target) ); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C index b6845295e..caba47caf 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_scrub.C @@ -40,106 +40,34 @@ #include <lib/dimm/rank.H> #include <lib/mcbist/address.H> #include <lib/mcbist/mcbist.H> -#include <lib/mcbist/patterns.H> +#include <generic/memory/lib/utils/mcbist/gen_mss_mcbist_patterns.H> #include <lib/mcbist/memdiags.H> -#include <lib/mcbist/sim.H> #include <generic/memory/lib/utils/count_dimm.H> -#include <lib/fir/memdiags_fir.H> +#include <lib/fir/unmask.H> using fapi2::TARGET_TYPE_MCBIST; using fapi2::TARGET_TYPE_MCA; using fapi2::TARGET_TYPE_SYSTEM; using fapi2::FAPI2_RC_SUCCESS; -/// -/// @brief Begin background scrub -/// @param[in] i_target MCBIST -/// @return FAPI2_RC_SUCCESS iff ok -/// -fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) +extern "C" { - FAPI_INF("Start mss scrub"); - - // If there are no DIMM we don't need to bother. In fact, we can't as we didn't setup - // attributes for the PHY, etc. - if (mss::count_dimm(i_target) == 0) - { - FAPI_INF("... skipping scrub for %s - no DIMM ...", mss::c_str(i_target)); - return fapi2::FAPI2_RC_SUCCESS; - } - - // If we're running in the simulator, we want to only touch the addresses which training touched - uint8_t l_sim = 0; - bool l_poll_results = false; - fapi2::buffer<uint64_t> l_status; - - // A small vector of addresses to poll during the polling loop - const std::vector<mss::poll_probe<fapi2::TARGET_TYPE_MCBIST>> l_probes = - { - {i_target, "mcbist current address", MCBIST_MCBMCATQ}, - }; - - // We'll fill in the initial delay below - mss::poll_parameters l_poll_parameters(0, 200, 100 * mss::DELAY_1MS, 200, 10000); - uint64_t l_memory_size = 0; - - FAPI_TRY( mss::eff_memory_size<mss::mc_type::NIMBUS>(i_target, l_memory_size) ); - l_poll_parameters.iv_initial_delay = mss::calculate_initial_delay(i_target, (l_memory_size * mss::BYTES_PER_GB)); - FAPI_TRY( mss::is_simulation( l_sim) ); - - if (l_sim) + /// + /// @brief Begin background scrub + /// @param[in] i_target MCBIST + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode p9_mss_scrub( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target ) { - fapi2::ReturnCode l_rc; - - // Use some sort of pattern in sim in case the verification folks need to look for something - // TK. Need a verification pattern. This is a not-good pattern for verification ... We don't really - // have a good pattern for verification defined. - FAPI_INF("running mss sim init in place of scrub"); - l_rc = mss::mcbist::sim::sf_init(i_target, mss::mcbist::PATTERN_0); - - // Unmask firs and turn off FIFO mode before returning - FAPI_TRY ( mss::unmask::after_memdiags( i_target ) ); - FAPI_TRY ( mss::unmask::after_background_scrub( i_target ) ); - FAPI_TRY ( mss::reset_reorder_queue_settings(i_target) ); - - return l_rc; + FAPI_INF("Start mss scrub for %s", mss::c_str(i_target)); + // Initialize memory and set firs accordingly + FAPI_TRY(mss::memdiags::mss_initialize_memory(i_target)); + // Kickoff background scrub and unmask firs + FAPI_TRY(mss::memdiags::mss_background_scrub_helper(i_target)); + + fapi_try_exit: + return fapi2::current_err; } - // In Cronus on hardware (which is how we got here - f/w doesn't call this) we want - // to call sf_init (0's) - // TK we need to check FIR given the way this is right now, we should adjust with better stop - // conditions when we learn more about what we want to find in the lab - FAPI_TRY( mss::memdiags::sf_init(i_target, mss::mcbist::PATTERN_0) ); - - // Poll for completion. - l_poll_results = mss::poll(i_target, MCBIST_MCBISTFIRQ, l_poll_parameters, - [&l_status](const size_t poll_remaining, - const fapi2::buffer<uint64_t>& stat_reg) -> bool - { - FAPI_DBG("mcbist firq 0x%llx, remaining: %d", stat_reg, poll_remaining); - l_status = stat_reg; - return l_status.getBit<MCBIST_MCBISTFIRQ_MCBIST_PROGRAM_COMPLETE>() == true; - }, - l_probes); - - FAPI_ASSERT( l_poll_results == true, - fapi2::MSS_MEMDIAGS_SUPERFAST_INIT_FAILED_TO_INIT().set_MCBIST_TARGET(i_target), - "p9_mss_scrub (init) timedout %s", mss::c_str(i_target) ); - - // Unmask firs after memdiags and turn off FIFO mode - FAPI_TRY ( mss::unmask::after_memdiags( i_target ) ); - FAPI_TRY ( mss::reset_reorder_queue_settings(i_target) ); - - // Start background scrub - FAPI_TRY ( mss::memdiags::background_scrub( i_target, - mss::mcbist::stop_conditions(), - mss::mcbist::speed::BG_SCRUB, - mss::mcbist::address() ) ); - - // Unmask firs after background scrub is started - FAPI_TRY ( mss::unmask::after_background_scrub( i_target ) ); - -fapi_try_exit: - return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C index 2523989fa..45ea4392d 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_thermal_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,8 +34,9 @@ // *HWP Consumed by: FSP:HB #include <fapi2.H> +#include <lib/shared/nimbus_defaults.H> #include <lib/mc/mc.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <p9_mss_thermal_init.H> using fapi2::TARGET_TYPE_MCS; diff --git a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C index 076cd911c..01bd44749 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9_mss_utils_to_throttle.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,7 @@ // *HWP Level: 3 // *HWP Consumed by: FSP:HB +#include <lib/shared/nimbus_defaults.H> #include <p9_mss_utils_to_throttle.H> // fapi2 @@ -45,7 +46,7 @@ // mss lib #include <lib/power_thermal/throttle.H> #include <generic/memory/lib/utils/index.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <lib/utils/mss_nimbus_conversions.H> #include <lib/power_thermal/throttle.H> #include <lib/mss_attribute_accessors.H> @@ -71,6 +72,8 @@ extern "C" /// fapi2::ReturnCode p9_mss_utils_to_throttle( const std::vector< fapi2::Target<TARGET_TYPE_MCS> >& i_targets ) { + constexpr uint64_t l_min_util = mss::power_thermal::throttle_traits<mss::mc_type::NIMBUS>::MIN_UTIL; + FAPI_INF("Entering p9_mss_utils_to_throttle"); std::vector< fapi2::Target<fapi2::TARGET_TYPE_MCA> > l_exceeded_power; @@ -87,20 +90,24 @@ extern "C" uint32_t l_max_databus_util = {}; uint32_t l_dram_clocks = 0; uint16_t l_safemode_throttle_per_port = 0; - double l_calc_util_safemode = 0; + uint32_t l_calc_util = 0; uint16_t l_n_port[mss::PORTS_PER_MCS] = {}; uint16_t l_n_slot[mss::PORTS_PER_MCS] = {}; uint32_t l_max_power[mss::PORTS_PER_MCS] = {}; - FAPI_TRY( mss::mrw_mem_m_dram_clocks(l_dram_clocks) ); + FAPI_TRY(mss::mrw_mem_m_dram_clocks(l_dram_clocks) ); //Util attribute set by OCC - FAPI_TRY( mss::databus_util(l_mcs, l_input_databus_util) ); - FAPI_TRY( mss::mrw_max_dram_databus_util(l_max_databus_util)); + FAPI_TRY(mss::databus_util(l_mcs, l_input_databus_util) ); + FAPI_TRY(mss::mrw_max_dram_databus_util(l_max_databus_util)); + FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_safemode_throttle_per_port)); for( const auto& l_mca : mss::find_targets<TARGET_TYPE_MCA>(l_mcs) ) { + fapi2::ReturnCode l_rc; + bool l_safemode = false; + FAPI_INF("Input databus utilization for %s is %d", mss::c_str(l_mca), l_input_databus_util[mss::index(l_mca)]); @@ -113,56 +120,31 @@ extern "C" } // If input utilization is zero, use mrw safemode throttle values for utilization - bool l_safemode = false; - - if (l_input_databus_util[l_port_num] == 0) - { - FAPI_TRY(mss::mrw_safemode_mem_throttled_n_commands_per_port(l_safemode_throttle_per_port), - "Error in getting safemode throttles" ); - FAPI_TRY( mss::power_thermal::calc_util_from_throttles(l_safemode_throttle_per_port, l_dram_clocks, - l_calc_util_safemode), - "%s Error calculating utilization from safemode throttle %d and mem clocks %d", - mss::c_str(l_mca), - l_safemode_throttle_per_port, - l_dram_clocks); - FAPI_INF( "%s Safemode throttles being used since input util is zero: Using N=%d, Utilization %f", - mss::c_str(l_mca), - l_safemode_throttle_per_port, - l_calc_util_safemode); - l_safemode = true; - l_input_databus_util[l_port_num] = l_calc_util_safemode; - } - - //Make sure MIN_UTIL <= input_utilization <= max_utilization - const uint32_t l_databus_util = ( l_input_databus_util[l_port_num] >= mss::power_thermal::MIN_UTIL) ? - std::min(l_input_databus_util[l_port_num], l_max_databus_util) - : mss::power_thermal::MIN_UTIL; + // else make sure we're within our maximum utilization limit + FAPI_TRY(mss::power_thermal::calc_utilization<mss::mc_type::NIMBUS>(l_mca, + l_input_databus_util[l_port_num], + l_dram_clocks, + l_safemode_throttle_per_port, + l_max_databus_util, + l_calc_util, + l_util_error, + l_safemode)); // Error if utilization is less than MIN_UTIL // Don't exit, let HWP finish and return error at end - if (l_input_databus_util[l_port_num] < mss::power_thermal::MIN_UTIL) - { - FAPI_ASSERT_NOEXIT( false, - fapi2::MSS_MIN_UTILIZATION_ERROR() - .set_INPUT_UTIL_VALUE(l_input_databus_util[l_port_num]) - .set_MIN_UTIL_VALUE(mss::power_thermal::MIN_UTIL), - "%s Input utilization (%d) less than minimum utilization allowed (%d)", - mss::c_str(l_mca), l_input_databus_util[l_port_num], mss::power_thermal::MIN_UTIL); - l_util_error = true; - } - - //Make a throttle object in order to calculate the port power - fapi2::ReturnCode l_rc; - - mss::power_thermal::throttle l_throttle (l_mca, l_rc); - FAPI_TRY(l_rc, "Error calculating mss::power_thermal::throttle constructor in p9_mss_utils_to_throttles"); + FAPI_ASSERT_NOEXIT(!l_util_error, + fapi2::MSS_MIN_UTILIZATION_ERROR() + .set_INPUT_UTIL_VALUE(l_input_databus_util[l_port_num]) + .set_MIN_UTIL_VALUE(l_min_util), + "%s Input utilization (%d) less than minimum utilization allowed (%d)", + mss::c_str(l_mca), l_input_databus_util[l_port_num], l_min_util); - FAPI_INF( "%s MRW dram clock window: %d, databus utilization: %d", - mss::c_str(l_mca), - l_dram_clocks, - l_databus_util); + // Make a throttle object in order to calculate the port power + mss::power_thermal::throttle<mss::mc_type::NIMBUS> l_throttle (l_mca, l_rc); + FAPI_TRY(l_rc, "%s Error calculating mss::power_thermal::throttle constructor in p9_mss_utils_to_throttles", + mss::c_str(l_mca)); - FAPI_TRY( l_throttle.calc_slots_and_power(l_databus_util)); + FAPI_TRY( l_throttle.calc_slots_and_power(l_calc_util)); FAPI_INF( "%s Calculated N commands per port %d, per slot %d, commands per dram clock window %d, maxpower is %d", mss::c_str(l_mca), @@ -194,7 +176,7 @@ extern "C" // Return a failing RC code if we had any input utilization values less than MIN_UTIL if (l_util_error) { - fapi2::current_err = fapi2::FAPI2_RC_FALSE; + fapi2::current_err = fapi2::RC_MSS_MIN_UTILIZATION_ERROR; } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C b/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C index b11696597..60d52d748 100644 --- a/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C +++ b/src/import/chips/p9/procedures/hwp/memory/p9a_omi_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -90,20 +90,13 @@ fapi2::ReturnCode p9a_omi_init_enable_templates(const fapi2::Target<fapi2::TARGE l_enable_tmpl_7), "Error from FAPI_ATTR_GET (ATTR_PROC_ENABLE_DL_TMPL_7)"); - FAPI_ASSERT(l_enable_tmpl_1 != 0, - fapi2::PROC_DOWNSTREAM_TMPL1_REQUIRED_ERR() - .set_TARGET(i_target), - "Downstream template 1 is required."); - - FAPI_ASSERT(l_enable_tmpl_4 != 0 || l_enable_tmpl_7 != 0, - fapi2::PROC_DOWNSTREAM_TMPL4OR7_REQUIRED_ERR() - .set_TARGET(i_target), - "Downstream template 4 and/or 7 is required."); - - //Turn off temp0_only - FAPI_TRY(getScom(i_target, P9A_MCC_DSTLCFG, l_data)); - l_data.clearBit<P9A_MCC_DSTLCFG_TMPL0_ONLY>(); - FAPI_TRY(putScom(i_target, P9A_MCC_DSTLCFG, l_data)); + if (l_enable_tmpl_1 || l_enable_tmpl_4 || l_enable_tmpl_7) + { + //Turn off temp0_only + FAPI_TRY(getScom(i_target, P9A_MCC_DSTLCFG, l_data)); + l_data.clearBit<P9A_MCC_DSTLCFG_TMPL0_ONLY>(); + FAPI_TRY(putScom(i_target, P9A_MCC_DSTLCFG, l_data)); + } fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C b/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C index 9f1a45f6b..58e2393cc 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fab_iovalid.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -998,7 +998,7 @@ fapi2::ReturnCode p9_fab_iovalid_get_link_delay( { FAPI_DBG("Start"); fapi2::buffer<uint64_t> l_link_delay_reg; - uint32_t l_sublink_delay[2]; + uint32_t l_sublink_delay[2] = {}; // read link delay register, extract hi/lo delay values & return their average FAPI_TRY(fapi2::getScom(i_target, i_link_ctl.tl_link_delay_addr, l_link_delay_reg), diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C index 342e32247..0feeff44e 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_eff_grouping.C @@ -745,7 +745,7 @@ fapi2::ReturnCode EffGroupingMccAttrs::getAttrs( iv_dimmSize = (iv_ocmbs.size() * l_min_size); // Display this OMI's attribute info - FAPI_INF("EffGroupingMccAttrs::getAttrs: MCC %d, OCMBs attached %d, " + FAPI_INF("EffGroupingMccAttrs::getAttrs: MCC %d, OCMBs w/ memory attached %d, " "iv_dimmSize %d GB ", iv_unitPos, iv_ocmbs.size(), iv_dimmSize); @@ -1553,7 +1553,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr( } // Setting NHTM & OCC base addresses - if ( (l_nhtmSize + l_chtmSize) < i_procAttrs.iv_occSandboxSize) + // Set larger allocations on top (at higher addresses) + if ( (l_nhtmSize + l_chtmSize) >= i_procAttrs.iv_occSandboxSize) { iv_occ_sandbox_base = l_mem_bases[l_index] + l_mem_sizes[l_index]; iv_nhtm_bar_base = iv_occ_sandbox_base + i_procAttrs.iv_occSandboxSize; @@ -1564,6 +1565,23 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr( iv_occ_sandbox_base = iv_nhtm_bar_base + l_nhtmSize + l_chtmSize; } + // Verify NHTM base addresses aligned with allocated size. + // The OCC sandbox base is just a FW scratch area and no HW + // functions mapped to it so we don't need to check its base alignment. + if ( ((l_nhtmSize + l_chtmSize) > 0) && + (iv_nhtm_bar_base & ((l_nhtmSize + l_chtmSize) - 1)) ) + { + FAPI_ASSERT(false, + fapi2::MSS_EFF_GROUPING_ADDRESS_NOT_ALIGNED() + .set_NHTM_BAR_BASE(iv_nhtm_bar_base) + .set_NHTM_SIZE(l_nhtmSize) + .set_CHTM_SIZE(l_chtmSize), + "EffGroupingBaseSizeData::set_HTM_OCC_base_addr: " + "NHTM BAR base address is not aligned with its size " + "NHTM_BAR_BASE 0x%.16llX, NHTM_SIZE 0x%.16llX, CTHM_SIZE 0x%.16llX", + iv_nhtm_bar_base, l_nhtmSize, l_chtmSize); + } + // Setting CHTM base addresses for (uint8_t ii = 0; ii < NUM_OF_CHTM_REGIONS; ii++) { @@ -1608,7 +1626,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::set_HTM_OCC_base_addr( } // Update mem sizes with working array values - if (l_numRegions == NUM_NON_MIRROR_REGIONS) + if (i_sysAttrs.iv_selectiveMode == + fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) { memcpy(iv_memory_sizes, l_mem_sizes, sizeof(iv_memory_sizes)); } @@ -1809,7 +1828,8 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData( } // Update mem sizes with working array values - if (l_numRegions == NUM_NON_MIRROR_REGIONS) + if (i_sysAttrs.iv_selectiveMode == + fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) { memcpy(iv_memory_sizes, l_mem_sizes, sizeof(iv_memory_sizes)); } @@ -1839,7 +1859,7 @@ fapi2::ReturnCode EffGroupingBaseSizeData::setSMFBaseSizeData( ii, l_mem_bases[ii], l_mem_sizes[ii]); } - FAPI_INF("SMF_BASE %.16lld (%d GB)", iv_smf_bar_base, iv_smf_bar_base >> 30); + FAPI_INF("SMF_BASE 0x%.16llX", iv_smf_bar_base); for (uint8_t ii = 0; ii < l_numRegions; ii++) { @@ -2147,7 +2167,6 @@ void grouping_group8PortsPerGroup(const EffGroupingMemInfo& i_memInfo, o_groupData.iv_data[g][MEMBER_IDX(5)] = MCPORTID_5; o_groupData.iv_data[g][MEMBER_IDX(6)] = MCPORTID_3; o_groupData.iv_data[g][MEMBER_IDX(7)] = MCPORTID_7; - g++; // increase o_groupData.iv_numGroups // Record which MC ports were grouped // Check if OMI mirrorable @@ -2163,6 +2182,8 @@ void grouping_group8PortsPerGroup(const EffGroupingMemInfo& i_memInfo, } } + g++; // increase o_groupData.iv_numGroups + FAPI_INF("grouping_group8PortsPerGroup: Successfully grouped 8 " "MC ports."); } diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C index 90e62859e..46a87c966 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_mss_setup_bars.C @@ -6,6 +6,7 @@ /* OpenPOWER HostBoot Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2015,2019 */ +/* [+] Inspur Power Systems Corp. */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,17 +45,20 @@ #include <p9_mc_scom_addresses_fld.H> #include <p9n2_mc_scom_addresses.H> #include <p9n2_mc_scom_addresses_fld.H> +#include <p9a_mc_scom_addresses.H> +#include <p9a_mc_scom_addresses_fld.H> #include <p9a_misc_scom_addresses.H> #include <p9a_misc_scom_addresses_fld.H> #include <p9a_addr_ext.H> #include <map> #include <lib/shared/mss_const.H> #include <generic/memory/lib/utils/memory_size.H> -#include <exp_inband.H> +#include <lib/inband/exp_inband.H> ///---------------------------------------------------------------------------- /// Constant definitions ///---------------------------------------------------------------------------- +const uint8_t USTL_MDI_EQUAL_ONE = 1; const uint8_t MAX_MC_PORTS_PER_MCS = 2; // 2 MC ports per MCS const uint8_t NO_CHANNEL_PER_GROUP = 0xFF; // Init value of channel per group @@ -300,12 +304,12 @@ fapi2::ReturnCode getMcMemSize( uint8_t l_mcaPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mca, l_mcaPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Get the amount of memory behind this MCA target FAPI_TRY(mss::eff_memory_size<mss::mc_type::NIMBUS>(l_mca, l_mcaSize), "Error returned from eff_memory_size - MCA, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); FAPI_INF("MCA %u: Total DIMM size %lu GB", l_mcaPos, l_mcaSize); o_mcSize += l_mcaSize; @@ -334,12 +338,12 @@ fapi2::ReturnCode getMcMemSize( uint8_t l_dmiPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_dmi, l_dmiPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Get the amount of memory behind this DMI target FAPI_TRY(mss::eff_memory_size<mss::mc_type::CENTAUR>(l_dmi, l_chSize), "Error returned from eff_memory_size - DMI, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); FAPI_INF("DMI %u: Total DIMM size %lu GB", l_dmiPos, l_chSize); o_mcSize += l_chSize; @@ -370,19 +374,19 @@ fapi2::ReturnCode getMcMemSize( for (auto l_omi : l_omiChiplets) { - const auto& l_ocmb_chiplets = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>(); + const auto& l_ocmb_chips = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>(); - if (!l_ocmb_chiplets.empty()) + if (!l_ocmb_chips.empty()) { uint8_t l_omiPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_omi, l_omiPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Get the amount of memory behind this OMI - FAPI_TRY(mss::eff_memory_size<mss::mc_type::EXPLORER>(l_ocmb_chiplets[0], l_chSize), + FAPI_TRY(mss::eff_memory_size<mss::mc_type::EXPLORER>(l_ocmb_chips[0], l_chSize), "Error returned from eff_memory_size - ocmb, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); FAPI_INF("OMI %u: Total DIMM size %lu GB", l_omiPos, l_chSize); @@ -506,14 +510,14 @@ fapi2::ReturnCode validateGroupData( uint8_t l_mcPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc, l_mcPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); FAPI_INF("validateGroupData: MC unit pos %d", l_mcPos); // Get the memory size behind this MC FAPI_TRY(getMcMemSize(l_mc, l_mcSize), "Error returned from getMcMemSize, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Get this MC memsize reported in Group data getGroupDataMcMemSize(l_mcPos, i_omi, i_groupData, l_portFound, @@ -536,6 +540,8 @@ fapi2::ReturnCode validateGroupData( } // MC loop + FAPI_INF("Total memory size= %lu GB", l_mcSize); + // Assert if a PORT_ID is found more than once in any group for (uint8_t ii = 0; ii < NUM_MC_PORTS_PER_PROC; ii++) { @@ -590,7 +596,7 @@ fapi2::ReturnCode getGroupSizeEncodedValue( uint8_t l_mcPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_mcTarget, l_mcPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Assert if can't find Group size in the table FAPI_ASSERT( false, fapi2::MSS_SETUP_BARS_INVALID_GROUP_SIZE() @@ -761,7 +767,7 @@ fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<T>& i_mcTarget, FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo[0].groupSize, o_mcBarData.MCFGP_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address o_mcBarData.MCFGP_groupBaseAddr = i_portInfo[0].groupBaseAddr; @@ -774,7 +780,7 @@ fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<T>& i_mcTarget, FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo[1].groupSize, o_mcBarData.MCFGPM_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address o_mcBarData.MCFGPM_groupBaseAddr = i_portInfo[1].groupBaseAddr; @@ -873,7 +879,7 @@ fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<fapi2::TARGET_TYPE_M FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo.groupSize, o_mcBarData.MCFGP_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address o_mcBarData.MCFGP_groupBaseAddr = i_portInfo.groupBaseAddr; @@ -886,7 +892,7 @@ fapi2::ReturnCode getNonMirrorBarIdSize(const fapi2::Target<fapi2::TARGET_TYPE_M FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo.groupSize, o_mcBarData.MCFGPM_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address o_mcBarData.MCFGPM_groupBaseAddr = i_portInfo.groupBaseAddr; @@ -1040,7 +1046,7 @@ fapi2::ReturnCode getMirrorBarData(const fapi2::Target<T>& i_mcTarget, FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo[1].groupSize, io_mcBarData.MCFGPM_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address io_mcBarData.MCFGPM_groupBaseAddr = i_portInfo[1].groupBaseAddr; @@ -1106,7 +1112,7 @@ fapi2::ReturnCode getMirrorBarData(const fapi2::Target<fapi2::TARGET_TYPE_MCC>& FAPI_TRY(getGroupSizeEncodedValue(i_mcTarget, i_portInfo.groupSize, io_mcBarData.MCFGPM_group_size), "getGroupSizeEncodedValue() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Group base address io_mcBarData.MCFGPM_groupBaseAddr = i_portInfo.groupBaseAddr; @@ -1462,7 +1468,7 @@ fapi2::ReturnCode buildMCBarData( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE, FAPI_SYSTEM, l_mirror_ctl), "Error getting ATTR_MRW_HW_MIRRORING_ENABLE, " - "l_rc 0x%.8X", (uint64_t)fapi2::current_err); + "l_rc 0x%.8X", uint64_t(fapi2::current_err)); for (auto l_mc : i_mcTargets) { @@ -1473,7 +1479,7 @@ fapi2::ReturnCode buildMCBarData( uint8_t l_unitPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc, l_unitPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); fapi2::toString(l_mc, l_targetStr, sizeof(l_targetStr)); FAPI_INF("Build BAR data for MC target: %s", l_targetStr); @@ -1493,7 +1499,7 @@ fapi2::ReturnCode buildMCBarData( // ---- Build MCFGP/MCFGM data based on port group info ---- FAPI_TRY(getNonMirrorBarData(l_mc, l_portInfo, l_mcBarData), "getNonMirrorBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // --------------------------------------------------------------- // Set MC register values for mirror groups @@ -1514,7 +1520,7 @@ fapi2::ReturnCode buildMCBarData( // ---- Build MCFGM data based on port group info ---- FAPI_TRY(getMirrorBarData(l_mc, l_portInfoMirrored, l_mcBarData), "getMirrorBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); } } @@ -1563,7 +1569,7 @@ fapi2::ReturnCode buildMCBarData( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MRW_HW_MIRRORING_ENABLE, FAPI_SYSTEM, l_mirror_ctl), "Error getting ATTR_MRW_HW_MIRRORING_ENABLE, " - "l_rc 0x%.8X", (uint64_t)fapi2::current_err); + "l_rc 0x%.8X", uint64_t(fapi2::current_err)); for (auto l_mcc : i_mccTargets) { @@ -1574,7 +1580,7 @@ fapi2::ReturnCode buildMCBarData( uint8_t l_unitPos = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mcc, l_unitPos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); fapi2::toString(l_mcc, l_targetStr, sizeof(l_targetStr)); FAPI_INF("Build BAR data for MC target: %s", l_targetStr); @@ -1593,7 +1599,7 @@ fapi2::ReturnCode buildMCBarData( // ---- Build MCFGP/MCFGM data based on port group info ---- FAPI_TRY(getNonMirrorBarData(l_mcc, l_portInfo, l_mcBarData), "getNonMirrorBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // --------------------------------------------------------------- // Set MC register values for mirror groups @@ -1610,7 +1616,7 @@ fapi2::ReturnCode buildMCBarData( // ---- Build MCFGM data based on port group info ---- FAPI_TRY(getMirrorBarData(l_mcc, l_portInfoMirrored, l_mcBarData), "getMirrorBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); } // Add to output pair @@ -1675,13 +1681,12 @@ fapi2::ReturnCode writeMCBarData( FAPI_DBG("Entering"); fapi2::buffer<uint64_t> l_scomData(0); - fapi2::ATTR_MSS_INTERLEAVE_GRANULARITY_Type l_interleave_granule_size; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_INTERLEAVE_GRANULARITY, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_interleave_granule_size), "Error getting ATTR_MSS_INTERLEAVE_GRANULARITY, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); for (auto l_pair : i_mcBarDataPair) { @@ -1718,11 +1723,13 @@ fapi2::ReturnCode writeMCBarData( MCS_MCFGP_GROUP_BASE_ADDRESS_LEN>( (l_data.MCFGP_groupBaseAddr >> 2)); + // configure interleave granularity if 2/4/8 MC per group only - if ((l_data.MCFGP_chan_per_group == 0b0100) || // 2 MC/group - (l_data.MCFGP_chan_per_group == 0b0101) || - (l_data.MCFGP_chan_per_group == 0b0110) || // 4 MC/group - (l_data.MCFGP_chan_per_group == 0b1000)) // 8 MC/group + if ( (l_data.MCFGP_chan_per_group == 0b0100) || // 2 MC/group + (l_data.MCFGP_chan_per_group == 0b0101) || + (l_data.MCFGP_chan_per_group == 0b0110) || // 4 MC/group + (l_data.MCFGP_chan_per_group == 0b1000) // 8 MC/group + ) { fapi2::buffer<uint64_t> l_mcmode0_scom_data; FAPI_TRY(fapi2::getScom(l_target, MCS_MCMODE0, l_mcmode0_scom_data), @@ -1971,7 +1978,7 @@ fapi2::ReturnCode writeMCCInterleaveGranularity( fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_interleave_granule_size), "Error getting ATTR_MSS_INTERLEAVE_GRANULARITY, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); for (auto l_pair : i_mcBarDataPair) { @@ -1982,33 +1989,6 @@ fapi2::ReturnCode writeMCCInterleaveGranularity( if (l_data.MCFGP_valid == true) { fapi2::Target<fapi2::TARGET_TYPE_MI> l_mi_target = l_target.getParent<fapi2::TARGET_TYPE_MI>(); - - // configure interleave granularity if 1/2/4/8 MC per group only - if ((l_data.MCFGP_chan_per_group == 0) || // 8 MC/group - (l_data.MCFGP_chan_per_group == 1) || // 1 MC/group - (l_data.MCFGP_chan_per_group == 2) || // 2 MC/group - (l_data.MCFGP_chan_per_group == 4)) // 4 MC/group - { - //Only set to true if the value for the target is not set yet - if (l_granule_supported.find(l_mi_target) == l_granule_supported.end()) - { - l_granule_supported[l_mi_target] = true; - } - } - else - { - //Always set to false if we find one channel that cannot support it. - l_granule_supported[l_mi_target] = false; - } - } - } - - for ( auto l_it = l_granule_supported.begin(); l_it != l_granule_supported.end(); l_it++ ) - { - if (l_it->second) - { - auto l_mi_target = l_it->first; - fapi2::buffer<uint64_t> l_mcmode0_scom_data; FAPI_TRY(fapi2::getScom(l_mi_target, P9A_MI_MCMODE0, l_mcmode0_scom_data), "Error reading from MCS_MCMODE0 reg"); @@ -2065,10 +2045,19 @@ fapi2::ReturnCode writeMCBarData( uint8_t l_pos; fapi2::buffer<uint64_t> l_scomData(0); + fapi2::buffer<uint64_t> l_scomData_mirror(0); + fapi2::buffer<uint64_t> l_scomData_mcmode(0); fapi2::buffer<uint64_t> l_extAddr(0); fapi2::buffer<uint64_t> l_norAddr; uint64_t l_ext_mask; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + uint8_t mirror_policy; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MEM_MIRROR_PLACEMENT_POLICY, FAPI_SYSTEM, mirror_policy), + "Error reading ATTR_MEM_MIRROR_PLACEMENT_POLICY, l_rc 0x%.8X", + (uint64_t)fapi2::current_err); + FAPI_TRY(p9a_get_ext_mask(l_ext_mask)); FAPI_TRY(writeMCCInterleaveGranularity(i_mcBarDataPair)); @@ -2084,7 +2073,7 @@ fapi2::ReturnCode writeMCBarData( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_target, l_pos), "Error getting ATTR_CHIP_UNIT_POS, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // 1. ---- Set MCFGP reg ----- l_scomData = 0; @@ -2174,55 +2163,176 @@ fapi2::ReturnCode writeMCBarData( "Error writing to P9A_MI_MCFGPM1 reg"); } - // 3. ---- Set MCFGPA reg ----- + // 3. ---- Set MCFGPA/MCFGPMA regs ----- l_scomData = 0; - - // Assert if both HOLE1 and SMF are valid, settings will overlap - FAPI_ASSERT((l_data.MCFGPA_HOLE_valid[1] && l_data.MCFGPA_SMF_valid) == 0, - fapi2::MSS_SETUP_BARS_HOLE1_SMF_CONFLICT() - .set_TARGET(l_target) - .set_HOLE1_VALID(l_data.MCFGPA_HOLE_valid[1]) - .set_SMF_VALID(l_data.MCFGPA_SMF_valid), - "Error: MCFGPA HOLE1 and SMF are both valid, settings will overlap"); + l_scomData_mirror = 0; // Hole 0 if (l_data.MCFGPA_HOLE_valid[0] == true) { - // MCFGPA HOLE0 valid (bit 0) - l_scomData.setBit<P9A_MI_MCFGP0A_HOLE_VALID>(); + if(mirror_policy == + fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) //Non-mirrored mode, but still set up mirrored equiv addressses + { + // Non-mirrored + // MCFGP0A HOLE valid (bit 0) + l_scomData.setBit<P9A_MI_MCFGP0A_HOLE_VALID>(); + + // Hole lower addr + // Hole always extends to end of range + FAPI_DBG("l_data.MCFGPA_HOLE_LOWER_addr[0]: %016llx", l_data.MCFGPA_HOLE_LOWER_addr[0]); + FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPA_HOLE_LOWER_addr[0], l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS, + P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:31 extendedBarAddress shifts left 8 (17-8) = 9 + + // Mirrored Address = Non-mirrored >> 1 since bit 56 is not part of the dsaddr + // MCFGPM0A HOLE0 valid (bit 0) + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_HOLE_VALID>(); + + // Hole lower addr + // Hole always extends to end of range + FAPI_DBG("l_data.MCFGPA_HOLE_LOWER_addr[0]: %016llx", (l_data.MCFGPA_HOLE_LOWER_addr[0] >> 1)); + FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPA_HOLE_LOWER_addr[0], l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS, + P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS_LEN>( + (l_extAddr << 8)); //matches 17:31 extendedBarAddress shifts left 8 (17- (8 + 1)) = 8 + } + else + { + // Mirrored Address + // MCFGPM0A HOLE0 valid (bit 0) + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_HOLE_VALID>(); + + // Hole 0 lower addr + // Hole 0 always extends to end of range + FAPI_DBG("l_data.MCFGPA_HOLE_LOWER_addr[0]: %016llx", l_data.MCFGPA_HOLE_LOWER_addr[0]); + FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPA_HOLE_LOWER_addr[0], l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS, + P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:31 extendedBarAddress shifts left 8 (17- 8) = 9 + + // Non-mirrored Address = Mirrored Address << 1 since bit 56 is part of the dsaddr + // MCFGPA HOLE0 valid (bit 0) + l_scomData.setBit<P9A_MI_MCFGP0A_HOLE_VALID>(); + + // Hole 0 lower addr + // Hole 0 always extends to end of range + FAPI_DBG("l_data.MCFGPA_HOLE_LOWER_addr[0]: %016llx", (l_data.MCFGPA_HOLE_LOWER_addr[0] << 1)); + FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPA_HOLE_LOWER_addr[0], l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS, + P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS_LEN>( + (l_extAddr << 10)); //matches 17:31 extendedBarAddress shifts left 8 (17- (8 - 1)) = 10 - // Hole 0 lower addr - // Hole 0 always extends to end of range - FAPI_DBG("l_data.MCFGPA_HOLE_LOWER_addr[0]: %016llx", l_data.MCFGPA_HOLE_LOWER_addr[0]); - FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPA_HOLE_LOWER_addr[0], l_extAddr)); - l_scomData.insert<P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS, - P9A_MI_MCFGP0A_HOLE_LOWER_ADDRESS_LEN>( - (l_extAddr << 9)); //matches 17:31 extendedBarAddress shifts left 8 (17-8) = 9 + } } // SMF if (l_data.MCFGPA_SMF_valid == true) { - // MCFGPA SMF valid (bit 0) - l_scomData.setBit<P9A_MI_MCFGP0A_SMF_VALID>(); + FAPI_DBG("Writing SMF bit into address extension now"); + // Set up Extension Address for SMF + FAPI_TRY(fapi2::getScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCMODE2, l_scomData_mcmode), + "Error reading to P9A_MI_MCMODE2 reg"); + l_scomData_mcmode.setBit<P9A_MI_MCMODE2_CHIP_ADDRESS_EXTENSION_MASK_ENABLE>(); + FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCMODE2, l_scomData_mcmode), + "Error writing to P9A_MI_MCMODE2 reg"); + + if(mirror_policy == + fapi2::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) //Non-mirrored mode, but still set up mirrored equiv addressses + { + //Non-mirrored + // MCFGPA SMF valid (bit 0) + l_scomData.setBit<P9A_MI_MCFGP0A_SMF_VALID>(); + + // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE + l_scomData.setBit<P9A_MI_MCFGP0A_SMF_EXTEND_TO_END_OF_RANGE>(); + + // SMF lower addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_LOWER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS, + P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:35 extendBarAddress shifts left 8 (17-8) = 9 + // SMF upper addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_UPPER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS, + P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:35 extendBarAddress shifts left 8 (17-8) = 9 + + + //Mirrored BAR = Non-mirrored BAR >> 1 since bit 56 is not a dsaddr bit + // MCFGPA SMF valid (bit 0) + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_SMF_VALID>(); + + // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_SMF_EXTEND_TO_END_OF_RANGE>(); + + // SMF lower addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_LOWER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS, + P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS_LEN>( + (l_extAddr << 8)); //matches 17:35 extendBarAddress shifts left 8 (17- (8 + 1)) = 8 + // SMF upper addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_UPPER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS, + P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS_LEN>( + (l_extAddr << 8)); //matches 17:35 extendBarAddress shifts left 8 (17- (8 + 1)) = 8 + } + else + { + //Mirrored + // MCFGPA SMF valid (bit 0) + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_SMF_VALID>(); + + // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE + l_scomData_mirror.setBit<P9A_MI_MCFGPM0A_SMF_EXTEND_TO_END_OF_RANGE>(); + + // SMF lower addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_LOWER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS, + P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:35 extendBarAddress shifts left 8 (17- 8) = 9 + // SMF upper addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_UPPER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData_mirror.insert<P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS, + P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS_LEN>( + (l_extAddr << 9)); //matches 17:35 extendBarAddress shifts left 8 (17- 8) = 9 + + //Non-Mirrored BAR = Mirrored BAR << 1 since bit 56 is now a dsaddr bit + // MCFGPA SMF valid (bit 0) + l_scomData.setBit<P9A_MI_MCFGP0A_SMF_VALID>(); + + // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE + l_scomData.setBit<P9A_MI_MCFGP0A_SMF_EXTEND_TO_END_OF_RANGE>(); + + // SMF lower addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_LOWER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS, + P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS_LEN>( + (l_extAddr << 10)); //matches 17:35 extendBarAddress shifts left 8 (17- (8 - 1)) = 10 + // SMF upper addr + l_norAddr = 0; + l_norAddr.insertFromRight<17, 19>(l_data.MCFGPA_SMF_UPPER_addr); + FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); + l_scomData.insert<P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS, + P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS_LEN>( + (l_extAddr << 10)); //matches 17:35 extendBarAddress shifts left 8 (17- (8 - 1)) = 10 - // MCFGPA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE - l_scomData.setBit<P9A_MI_MCFGP0A_SMF_EXTEND_TO_END_OF_RANGE>(); - // SMF lower addr - l_norAddr = 0; - l_norAddr.insertFromRight<22, 14>(l_data.MCFGPA_SMF_LOWER_addr); - FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); - l_scomData.insert<P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS, - P9A_MI_MCFGP0A_SMF_LOWER_ADDRESS_LEN>( - (l_extAddr << 14)); //matches 22:35 extendBarAddress shifts left 8 (22-8) = 14 - // SMF upper addr - l_norAddr = 0; - l_norAddr.insertFromRight<22, 14>(l_data.MCFGPA_SMF_UPPER_addr); - FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); - l_scomData.insert<P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS, - P9A_MI_MCFGP0A_SMF_UPPER_ADDRESS_LEN>( - (l_extAddr << 14)); //matches 22:35 extendBarAddress shifts left 8 (22-8) = 14 + } } // Write to reg @@ -2232,6 +2342,11 @@ fapi2::ReturnCode writeMCBarData( P9A_MI_MCFGP0A, l_scomData); FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGP0A, l_scomData), "Error writing to P9A_MI_MCFGP0A reg"); + + FAPI_INF("Write MCFGPM0A reg 0x%.16llX, Value 0x%.16llX", + P9A_MI_MCFGPM0A, l_scomData_mirror); + FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGPM0A, l_scomData_mirror), + "Error writing to P9A_MI_MCFGPM0A reg"); } else { @@ -2239,83 +2354,76 @@ fapi2::ReturnCode writeMCBarData( P9A_MI_MCFGP1A, l_scomData); FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGP1A, l_scomData), "Error writing to P9A_MI_MCFGP1A reg"); - } - - // 4. ---- Set MCFGPMA reg ----- - l_scomData = 0; - // Assert if both HOLE1 and SMF are valid, settings will overlap - FAPI_ASSERT((l_data.MCFGPMA_HOLE_valid[1] && l_data.MCFGPMA_SMF_valid) == 0, - fapi2::MSS_SETUP_BARS_HOLE1_SMF_CONFLICT() - .set_TARGET(l_target) - .set_HOLE1_VALID(l_data.MCFGPMA_HOLE_valid[1]) - .set_SMF_VALID(l_data.MCFGPMA_SMF_valid), - "Error: MCFGPMA HOLE1 and SMF are both valid, settings will overlap"); - - // Hole 0 - if (l_data.MCFGPMA_HOLE_valid[0] == true) - { - // MCFGPMA HOLE0 valid (bit 0) - l_scomData.setBit<P9A_MI_MCFGPM0A_HOLE_VALID>(); - - // Hole 0 lower addr - // 0b0000000001 = 4GB - FAPI_TRY(extBar(l_ext_mask, l_data.MCFGPMA_HOLE_LOWER_addr[0], l_extAddr)); - l_scomData.insert<P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS, - P9A_MI_MCFGPM0A_HOLE_LOWER_ADDRESS_LEN>( - (l_extAddr << 9)); //matches 17:31 extendedBarAddress shifts left 8 (17-8) = 9 + FAPI_INF("Write MCFGPM1A reg 0x%.16llX, Value 0x%.16llX", + P9A_MI_MCFGPM1A, l_scomData_mirror); + FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGPM1A, l_scomData_mirror), + "Error writing to P9A_MI_MCFGP1A reg"); } + } // Data pair loop - // SMF - if (l_data.MCFGPMA_SMF_valid == true) - { - // MCFGPMA SMF valid (bit 0) - l_scomData.setBit<P9A_MI_MCFGPM0A_SMF_VALID>(); +fapi_try_exit: + FAPI_DBG("Exit"); + return fapi2::current_err; +} - // MCFGPMA_SMF_UPPER_ADDRESS_AT_END_OF_RANGE - l_scomData.setBit<P9A_MI_MCFGPM0A_SMF_EXTEND_TO_END_OF_RANGE>(); +/// +/// @brief Apply Gemini MDI bit workaround and mask Channel Timeout +/// +/// @param[in] i_target target to set actions/mask +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode applyGeminiFixes(const fapi2::Target<fapi2::TARGET_TYPE_MCC> i_target) +{ + FAPI_DBG("Entering fixGeminiMDI on %s", mss::c_str(i_target)); - // SMF lower addr - l_norAddr = 0; - l_norAddr.insertFromRight<22, 14>(l_data.MCFGPMA_SMF_LOWER_addr); - FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); - l_scomData.insert<P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS, - P9A_MI_MCFGPM0A_SMF_LOWER_ADDRESS_LEN>( - (l_extAddr << 14 )); //matches 22:35 extendBarAddress shifts left 8 (22-8) = 14 - // SMF upper addr - l_norAddr = 0; - l_norAddr.insertFromRight<22, 14>(l_data.MCFGPMA_SMF_UPPER_addr); - FAPI_TRY(extendBarAddress(l_ext_mask, l_norAddr, l_extAddr)); - l_scomData.insert<P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS, - P9A_MI_MCFGPM0A_SMF_UPPER_ADDRESS_LEN>( - (l_extAddr << 14)); //matches 22:35 extendBarAddress shifts left 8 (22-8) = 14 - } + fapi2::buffer<uint64_t> l_scom_data; + uint8_t l_any_gemini = 0; + const auto l_omiChiplets = i_target.getChildren<fapi2::TARGET_TYPE_OMI>(); - // Write to reg - if (l_pos % 2 == 0) - { - FAPI_INF("Write P9A_MI_MCFGPM0A reg 0x%.16llX, Value 0x%.16llX", - P9A_MI_MCFGPM0A, l_scomData); + for (const auto& l_omi : l_omiChiplets) + { + const auto& l_ocmb_chips = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>(); - FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGPM0A, l_scomData), - "Error writing to P9A_MI_MCFGPM0A reg"); - } - else + if (!l_ocmb_chips.empty()) { - FAPI_INF("Write P9A_MI_MCFGPM1A reg 0x%.16llX, Value 0x%.16llX", - P9A_MI_MCFGPM1A, l_scomData); - - FAPI_TRY(fapi2::putScom(l_target.getParent<fapi2::TARGET_TYPE_MI>(), P9A_MI_MCFGPM1A, l_scomData), - "Error writing to P9A_MI_MCFGPM1A reg"); + uint8_t l_workaround = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_AXONE_GEMINI_MDI_ERROR, + l_ocmb_chips[0], + l_workaround), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_AXONE_GEMINI_MDI_ERROR)"); + l_any_gemini |= l_workaround; } + } - } // Data pair loop + if(l_any_gemini) + { + // MDI Workaround + FAPI_TRY(fapi2::getScom(i_target, P9A_MCC_USTLCFG, l_scom_data), + "Error reading from MCC_USTLCFG reg"); + l_scom_data.setBit<P9A_MCC_USTLCFG_DEFAULT_META_DATA_ENABLE>(); + l_scom_data.insertFromRight<P9A_MC_USTLCFG_DEFAULT_META_DATA, + P9A_MC_USTLCFG_DEFAULT_META_DATA_LEN>(USTL_MDI_EQUAL_ONE); + FAPI_TRY(fapi2::putScom(i_target, P9A_MCC_USTLCFG, l_scom_data), + "Error writing to MCC_USTLCFG reg"); + + + fapi2::Target<fapi2::TARGET_TYPE_MI> l_mi_target = i_target.getParent<fapi2::TARGET_TYPE_MI>(); + // Channel Timeout + FAPI_TRY(fapi2::getScom(l_mi_target, P9A_MI_MCTO, l_scom_data), + "Error reading from MCC_USTLCFG reg"); + l_scom_data.clearBit<P9A_MI_MCTO_ENABLE_CHANNEL_HANG>(); + FAPI_TRY(fapi2::putScom(l_mi_target, P9A_MI_MCTO, l_scom_data), + "Error writing to MCC_USTLCFG reg"); + } + + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: - FAPI_DBG("Exit"); + FAPI_DBG("Exiting fixGeminiMDI on %s", mss::c_str(i_target)); return fapi2::current_err; } - /// /// @brief Unmask FIR before opening BARs /// @@ -2462,7 +2570,7 @@ fapi2::ReturnCode p9_mss_setup_bars( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MSS_MCS_GROUP_32, i_target, l_groupData), "Error getting ATTR_MSS_MCS_GROUP_32, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Setup BAR for Nimbus if (l_mcsChiplets.size() > 0) @@ -2470,22 +2578,22 @@ fapi2::ReturnCode p9_mss_setup_bars( // Validate group data from attributes FAPI_TRY(validateGroupData(l_mcsChiplets, false, l_groupData), "validateGroupData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Build MC BAR data based on Group data info FAPI_TRY(buildMCBarData(l_mcsChiplets, l_groupData, l_mcsBarDataPair), "buildMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Unmask MC FIRs FAPI_TRY(unmaskMCFIR(l_mcsBarDataPair), "unmaskMCFIR() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Write data to MCS FAPI_TRY(writeMCBarData(l_mcsBarDataPair), "writeMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); } // Setup BAR for Axone @@ -2494,25 +2602,33 @@ fapi2::ReturnCode p9_mss_setup_bars( // Validate group data from attributes FAPI_TRY(validateGroupData(l_mccChiplets, true, l_groupData), "validateGroupData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Build MC BAR data based on Group data info FAPI_TRY(buildMCBarData(l_mccChiplets, l_groupData, l_mccBarDataPair), "buildMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Unmask MC FIRs for (auto l_target : l_miChiplets) { FAPI_TRY(unmaskMCFIR(l_target), "unmaskMCFIR() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); + } + + // Apply Gemini MDI bit workaround + for (fapi2::Target<fapi2::TARGET_TYPE_MCC> l_target : l_mccChiplets) + { + FAPI_TRY(applyGeminiFixes(l_target), + "fixGeminiMDI() returns error, l_rc 0x%.8X", + uint64_t(fapi2::current_err)); } // Write data to MI FAPI_TRY(writeMCBarData(l_mccBarDataPair), "writeMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); } // Setup BAR for Cumulus @@ -2521,22 +2637,22 @@ fapi2::ReturnCode p9_mss_setup_bars( // Validate group data from attributes FAPI_TRY(validateGroupData(l_miChiplets, false, l_groupData), "validateGroupData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Build MC BAR data based on Group data info FAPI_TRY(buildMCBarData(l_miChiplets, l_groupData, l_miBarDataPair), "buildMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Unmask MC FIRs FAPI_TRY(unmaskMCFIR(l_miBarDataPair), "unmaskMCFIR() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); // Write data to MI FAPI_TRY(writeMCBarData(l_miBarDataPair), "writeMCBarData() returns error, l_rc 0x%.8X", - (uint64_t)fapi2::current_err); + uint64_t(fapi2::current_err)); } diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C index cf3edc4f4..cb2e6f175 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_npu_scominit.C @@ -42,6 +42,7 @@ #include <p9_misc_scom_addresses_fld.H> #include <p9a_misc_scom_addresses.H> #include <p9a_misc_scom_addresses_fld.H> +#include <p9_fbc_ioo_dl_npu_scom.H> //------------------------------------------------------------------------------ // Constant definitions @@ -99,6 +100,30 @@ fapi2::ReturnCode p9_npu_scominit( goto fapi_try_exit; } + // Enable obus for NPU for Axone + if (l_axone) + { + auto l_obus_targets = i_target.getChildren<fapi2::TARGET_TYPE_OBUS>(); + + for (auto l_obus_target : l_obus_targets) + { + FAPI_DBG("Invoking p9.fbc.ioo_dl.npu.scom.initfile..."); + FAPI_EXEC_HWP(l_rc, + p9_fbc_ioo_dl_npu_scom, + l_obus_target, + i_target, + fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>()); + + if (l_rc) + { + FAPI_ERR("Error from p9.fbc.ioo_dl.npu.scom.initfile"); + fapi2::current_err = l_rc; + goto fapi_try_exit; + } + + } + } + // apply additional SCOM inits l_atrmiss.setBit<PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP>() .setBit<PU_NPU_SM2_XTS_ATRMISS_ENA>(); diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C index 844899466..31a20244d 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -743,6 +743,160 @@ fapi_try_exit: } +/// @brief Configure an NPU instance +/// +/// @param[in] i_target Processor chip target +/// @param[in] i_attr_bar_enable Enable the NPU MMIO bar +/// @param[in] i_attr_bar The BAR for the NPU instance +/// @param[in] i_mmio_offset The MMIO offset for the chip +/// @param[in] i_attr_pri The private reg interface settings for each NDL +/// @param[in] i_npu_regs The registers for this NPU +/// @param[in] i_chip_info Structure describing chip properties/base addresses +/// +/// @return FAPI_RC_SUCCESS if all calls are successful, else error +fapi2::ReturnCode +p9a_setup_bars_npuX(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const uint8_t& i_attr_bar_enable, + fapi2::buffer<uint64_t> i_attr_bar, + const uint64_t& i_mmio_offset, + const uint8_t i_attr_pri[], + p9_setup_bars_p9a_npu_regs& i_npu_regs, + p9_setup_bars_chip_info& i_chip_info) +{ + FAPI_DBG("Start"); + + if (i_attr_bar_enable) + { + p9_setup_bars_addr_range l_mmio_range; + FAPI_ASSERT((i_attr_bar & P9_SETUP_BARS_OFFSET_MASK_16_MB) == 0, + fapi2::P9_SETUP_BARS_NPU_MMIO_BAR_ATTR_ERR() + .set_TARGET(i_target) + .set_BAR_OFFSET(i_attr_bar) + .set_BAR_OFFSET_MASK(P9_SETUP_BARS_OFFSET_MASK_16_MB) + .set_BAR_OVERLAP(i_attr_bar & P9_SETUP_BARS_OFFSET_MASK_2_MB), + "NPU MMIO BAR offset attribute is not aligned to HW implementation"); + + i_attr_bar &= NPU_BAR_BASE_ADDR_MASK; + i_attr_bar += i_mmio_offset; + i_attr_bar = i_attr_bar << NPU_BAR_ADDR_SHIFT; + i_attr_bar = NPU_BAR_REG_MASK & i_attr_bar; + i_attr_bar.setBit<PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE>(); + + for (uint8_t ll = 0; ll < NPU_NUM_BAR_SHADOWS; ll++) + { + FAPI_TRY(fapi2::putScom(i_target, i_npu_regs.bar_regs[ll], i_attr_bar), + "Error from putScom (0x08X)", i_npu_regs.bar_regs[ll]); + } + + l_mmio_range.base_addr = i_attr_bar; + l_mmio_range.size = P9_SETUP_BARS_SIZE_16_MB; + l_mmio_range.enabled = true; + i_chip_info.ranges.push_back(l_mmio_range); + i_chip_info.ranges.back().print(); + } + + for (uint8_t ll = 0; ll < NPU_NUM_BAR_SHADOWS; ll++) + { + uint64_t l_pri_val = static_cast<uint64_t>(i_attr_pri[ll]) << (64 - 8); + FAPI_TRY(fapi2::putScom(i_target, i_npu_regs.pri_regs[ll], l_pri_val), + "Error from putScom (0x08X)", i_npu_regs.pri_regs[ll]); + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + +/// @brief Configure p9a NPU MMIO access +/// +/// @param[in] i_target Processor chip target +/// @param[in] i_target_sys System target +/// @param[in] i_chip_info Structure describing chip properties/base addresses +/// +/// @return FAPI_RC_SUCCESS if all calls are successful, else error +fapi2::ReturnCode +p9a_setup_bars_npu(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>& i_target_sys, + p9_setup_bars_chip_info& i_chip_info) + +{ + FAPI_DBG("Start"); + + fapi2::buffer<uint64_t> l_mmio_bar = i_chip_info.base_address_mmio; + + //NPU0 + { + fapi2::ATTR_PROC_NPU0_MMIO_BAR_ENABLE_Type l_mmio_enable; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_MMIO_BAR_ENABLE, i_target, l_mmio_enable), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_MMIO_BAR_ENABLE)"); + + fapi2::ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET)"); + + fapi2::ATTR_PROC_NPU0_PRI_CONFIG_Type l_pri_config; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU0_PRI_CONFIG, i_target, l_pri_config), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU0_PRI_CONFIG)"); + + FAPI_TRY(p9a_setup_bars_npuX(i_target, + l_mmio_enable, + l_mmio_offset, + l_mmio_bar, + l_pri_config, + p9_setup_bars_p9a_npu0_regs, + i_chip_info)); + } + //NPU1 + { + fapi2::ATTR_PROC_NPU1_MMIO_BAR_ENABLE_Type l_mmio_enable; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_MMIO_BAR_ENABLE, i_target, l_mmio_enable), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_MMIO_BAR_ENABLE)"); + + fapi2::ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET)"); + + fapi2::ATTR_PROC_NPU1_PRI_CONFIG_Type l_pri_config; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU1_PRI_CONFIG, i_target, l_pri_config), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU1_PRI_CONFIG)"); + + FAPI_TRY(p9a_setup_bars_npuX(i_target, + l_mmio_enable, + l_mmio_offset, + l_mmio_bar, + l_pri_config, + p9_setup_bars_p9a_npu1_regs, + i_chip_info)); + } + //NPU2 + { + fapi2::ATTR_PROC_NPU2_MMIO_BAR_ENABLE_Type l_mmio_enable; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_MMIO_BAR_ENABLE, i_target, l_mmio_enable), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_MMIO_BAR_ENABLE)"); + + fapi2::ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET_Type l_mmio_offset; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET, i_target_sys, l_mmio_offset), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET)"); + + fapi2::ATTR_PROC_NPU2_PRI_CONFIG_Type l_pri_config; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_NPU2_PRI_CONFIG, i_target, l_pri_config), + "Error from FAPI_ATTR_GET (ATTR_PROC_NPU2_PRI_CONFIG)"); + + FAPI_TRY(p9a_setup_bars_npuX(i_target, + l_mmio_enable, + l_mmio_offset, + l_mmio_bar, + l_pri_config, + p9_setup_bars_p9a_npu2_regs, + i_chip_info)); + } + +fapi_try_exit: + FAPI_DBG("End"); + return fapi2::current_err; +} + + /// @brief Configure NPU MMIO access /// /// @param[in] i_target Processor chip target @@ -1237,7 +1391,12 @@ p9_setup_bars_check_overlap(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i .set_BASE_ADDR2(i_chip_info.ranges[jj].base_addr) .set_END_ADDR2(i_chip_info.ranges[jj].end_addr()) .set_ENABLED2(i_chip_info.ranges[jj].enabled), - "Overlapping address regions detected!"); + "Overlapping address regions detected %llx->%llx %llx->%llx!", + i_chip_info.ranges[ii].base_addr, + i_chip_info.ranges[ii].end_addr(), + i_chip_info.ranges[jj].base_addr, + i_chip_info.ranges[jj].end_addr() + ); } } } @@ -1255,6 +1414,10 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) FAPI_INF("Start"); fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; p9_setup_bars_chip_info l_chip_info; + fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP_Type l_one_npu; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP, i_target, l_one_npu), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP)"); // process chip information FAPI_TRY(p9_setup_bars_build_chip_info(i_target, @@ -1268,9 +1431,18 @@ p9_setup_bars(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) // PSI FAPI_TRY(p9_setup_bars_psi(i_target, FAPI_SYSTEM, l_chip_info), "Error from p9_setup_bars_psi"); + // NPU - FAPI_TRY(p9_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info), - "Error from p9_setup_bars_npu"); + if (l_one_npu) + { + FAPI_TRY(p9_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info), + "Error from p9_setup_bars_npu"); + } + else + { + FAPI_TRY(p9a_setup_bars_npu(i_target, FAPI_SYSTEM, l_chip_info), + "Error from p9a_setup_bars_npu"); + } // MCD if (!l_chip_info.hw423589_option1) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H index ebf4682af..19a04873e 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_setup_bars_defs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -344,6 +344,13 @@ const uint8_t NPU_NUM_BAR_SHADOWS = 4; const uint64_t NPU_BAR_BASE_ADDR_MASK = 0x0001FFFFFFFFFFFFULL; const uint64_t NPU_BAR_ADDR_SHIFT = 12; +// The NPU BAR does not include the Memory Select bits. +// This mask ensures after shifting the attribute bar value +// we only set the relivant BAR bits. +// 0001122233444556 +// 0482604826048260 +const uint64_t NPU_BAR_REG_MASK = 0x1FFFFFF000000000ULL; + const uint64_t NPU_PHY0_BAR_REGS_NDD1[NPU_NUM_BAR_SHADOWS] = { PU_NPU0_SM0_PHY_BAR, @@ -360,6 +367,14 @@ const uint64_t NPU_PHY0_BAR_REGS[NPU_NUM_BAR_SHADOWS] = 0x05011496 }; +const uint64_t NPU_PHY0_BAR_REGS_ADD1[NPU_NUM_BAR_SHADOWS] = +{ + 0x05011406, + 0x05011436, + 0x05011466, + 0x05011496 +}; + const uint64_t NPU_PHY1_BAR_REGS_NDD1[NPU_NUM_BAR_SHADOWS] = { PU_NPU1_SM0_PHY_BAR, @@ -392,4 +407,29 @@ const uint64_t NPU_MMIO_BAR_REGS[NPU_NUM_BAR_SHADOWS] = 0x05011096 }; +// P9A Npu instances +struct p9_setup_bars_p9a_npu_regs +{ + uint64_t bar_regs[NPU_NUM_BAR_SHADOWS]; + uint64_t pri_regs[NPU_NUM_BAR_SHADOWS]; +}; + +p9_setup_bars_p9a_npu_regs p9_setup_bars_p9a_npu0_regs = +{ + { 0x501103C, 0x501109C, 0x50110FC, 0x501115C }, + { 0x50111F6, 0x5011216, 0x50113D6, 0x50113F6 } +}; + +p9_setup_bars_p9a_npu_regs p9_setup_bars_p9a_npu1_regs = +{ + { 0x501143C, 0x501149C, 0x50114FC, 0x501155C }, + { 0x50115F6, 0x5011616, 0x50117D6, 0x50117F6 } +}; + +p9_setup_bars_p9a_npu_regs p9_setup_bars_p9a_npu2_regs = +{ + { 0x3011C3C, 0x3011C9C, 0x3011CFC, 0x3011D5C }, + { 0x3011DF6, 0x3011E16, 0x3011FD6, 0x3011FF6 } +}; + #endif //_P9_SETUP_BARS_DEFS_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C index e62ff6ab1..3ed9cc44c 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_throttle_sync.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,7 +43,7 @@ //------------------------------------------------------------------------------ #include <p9_throttle_sync.H> #include <fapi2.H> -#include <generic/memory/lib/utils/find.H> +#include <lib/utils/nimbus_find.H> #include <p9_perv_scom_addresses.H> ///---------------------------------------------------------------------------- @@ -79,13 +79,30 @@ template<> uint8_t findNumDimms(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_miTarget) { FAPI_DBG("Entering findNumDimms"); - auto l_dmiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_DMI>(); uint8_t l_num_dimms = 0; - for (auto l_dmi : l_dmiChiplets) + // Cumulus code + const auto& l_dmiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_DMI>(); + + for (const auto& l_dmi : l_dmiChiplets) + { + const auto& l_memBufs = l_dmi.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>(); + + if (l_memBufs.size() > 0) + { + l_num_dimms++; + } + } + + FAPI_DBG("After number of DIMM's after cumulus targets %u", l_num_dimms); + + // Axone code + const auto& l_omiChiplets = i_miTarget.getChildren<fapi2::TARGET_TYPE_OMI>(); + + for (const auto& l_omi : l_omiChiplets) { - auto l_memBufs = l_dmi.getChildren<fapi2::TARGET_TYPE_MEMBUF_CHIP>(); + const auto& l_memBufs = l_omi.getChildren<fapi2::TARGET_TYPE_OCMB_CHIP>(); if (l_memBufs.size() > 0) { @@ -93,6 +110,8 @@ uint8_t findNumDimms(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_miTarget) } } + FAPI_DBG("After number of DIMM's after axone targets %u", l_num_dimms); + FAPI_DBG("Exiting findNumDimms"); return l_num_dimms; } @@ -374,7 +393,7 @@ fapi2::ReturnCode throttleSync( } // Program the MCMODE0 if HW397255 is not enabled which means we - // should have a chip with Nimbus DD2+ or Cumulus. + // should have a chip with Nimbus DD2+ or Cumulus/Axone. if (i_HW397255_enabled == 0) { progMCMODE0(l_mc, i_mcTargets); @@ -442,7 +461,7 @@ extern "C" // HW397255 requires to also program a master MCS on MC23 if // it has DIMMs. // This should only be enabled for Nimbus DD1, disabled for Nimbus DD2 - // and Cumulus. + // and Cumulus/Axone. fapi2::ATTR_CHIP_EC_FEATURE_HW397255_Type l_HW397255_enabled; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_HW397255, i_target, l_HW397255_enabled), @@ -456,7 +475,7 @@ extern "C" (uint64_t)fapi2::current_err); } - // Cumulus + // Cumulus/Axone if (l_miChiplets.size() > 0) { FAPI_TRY(throttleSync(l_miChiplets, l_HW397255_enabled), diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C index 04ce62cd9..18c0079b0 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C @@ -44,6 +44,7 @@ const uint64_t M_PATH_CTRL_REG_CLEAR_VALUE = 0x0000000000000000; const uint64_t S_PATH_CTRL_REG_CLEAR_VALUE = 0x0000003F00000000; +static const uint8_t P9A_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL9_DC = 21; /// @brief MPIPL specific steps to clear the previous topology, this should be // called only during MPIPL @@ -778,6 +779,18 @@ fapi2::ReturnCode configure_m_path_ctrl_reg( const p9_tod_setup_osc_sel i_osc_sel) { fapi2::buffer<uint64_t> l_m_path_ctrl_reg = 0; + fapi2::buffer<uint64_t> l_root_ctrl8_reg = 0; + bool l_tod_on_lpc_clock = false; + + const bool is_mdmt = (i_tod_node->i_tod_master && i_tod_node->i_drawer_master); + + // Read ROOT_CTRL8 to determine TOD input clock selection + FAPI_TRY(fapi2::getScom(*(i_tod_node->i_target), + PERV_ROOT_CTRL8_SCOM, + l_root_ctrl8_reg), + "Error from getScom (PERV_ROOT_CTRL8_SCOM)!"); + + l_tod_on_lpc_clock = l_root_ctrl8_reg.getBit<P9A_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL9_DC>(); // Read PERV_TOD_M_PATH_CTRL_REG to preserve any prior configuration FAPI_TRY(fapi2::getScom(*(i_tod_node->i_target), @@ -785,85 +798,91 @@ fapi2::ReturnCode configure_m_path_ctrl_reg( l_m_path_ctrl_reg), "Error from getScom (PERV_TOD_M_PATH_CTRL_REG)!"); - // Configure Master OSC0/OSC1 path - FAPI_DBG("Configuring Master OSC path in PERV_TOD_M_PATH_CTRL_REG"); + // Configure single or dual edge detect based on tod clock select + l_m_path_ctrl_reg.writeBit<PERV_TOD_M_PATH_CTRL_REG_STEP_CREATE_DUAL_EDGE_DISABLE>(l_tod_on_lpc_clock); - if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) + if (is_mdmt) { - FAPI_DBG("OSC0 is valid; master path-0 will be configured."); + // Configure Master OSC0/OSC1 path + FAPI_DBG("Configuring Master OSC path in PERV_TOD_M_PATH_CTRL_REG"); - // OSC0 is connected - l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID>(); + if (i_osc_sel == TOD_OSC_0 || + i_osc_sel == TOD_OSC_0_AND_1 || + i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || + i_osc_sel == TOD_OSC_0_AND_1_SEL_1) + { + FAPI_DBG("OSC0 is valid; master path-0 will be configured."); - // OSC0 step alignment enabled - l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_DISABLE>(); + // OSC0 is connected + l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID>(); - // Set 512 steps per sync for path 0 - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT, - PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN>( - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_CREATE_SPS_512); + // OSC0 step alignment enabled + l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_0_STEP_ALIGN_DISABLE>(); - // Set step check CPS deviation to 50% - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION, - PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN>( - STEP_CHECK_CPS_DEVIATION_50_00_PCENT); + // Set 512 steps per sync for path 0 + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT, + PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN>( + TOD_M_PATH_CTRL_REG_M_PATH_SYNC_CREATE_SPS_512); - // 8 valid steps are required before step check is enabled - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT, - PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN>( - STEP_CHECK_VALIDITY_COUNT_8); - } - else - { - FAPI_DBG("OSC0 is not connected."); + // Set step check CPS deviation to 50% + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION, + PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_CPS_DEVIATION_LEN>( + STEP_CHECK_CPS_DEVIATION_50_00_PCENT); - // OSC0 is not connected; any previous path-0 settings will be ignored - l_m_path_ctrl_reg.setBit<PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID>(); - } + // 8 valid steps are required before step check is enabled + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT, + PERV_TOD_M_PATH_CTRL_REG_0_STEP_CHECK_VALIDITY_COUNT_LEN>( + STEP_CHECK_VALIDITY_COUNT_8); + } + else + { + FAPI_DBG("OSC0 is not connected."); - if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - FAPI_DBG("OSC1 is valid; master path-1 will be configured."); + // OSC0 is not connected; any previous path-0 settings will be ignored + l_m_path_ctrl_reg.setBit<PERV_TOD_M_PATH_CTRL_REG_0_OSC_NOT_VALID>(); + } - // OSC1 is connected - l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID>(); + if (i_osc_sel == TOD_OSC_1 || + i_osc_sel == TOD_OSC_0_AND_1 || + i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || + i_osc_sel == TOD_OSC_0_AND_1_SEL_1) + { + FAPI_DBG("OSC1 is valid; master path-1 will be configured."); - // OSC1 step alignment enabled - l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_DISABLE>(); + // OSC1 is connected + l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID>(); - // Set 512 steps per sync for path 1 - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT, - PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN>( - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_CREATE_SPS_512); + // OSC1 step alignment enabled + l_m_path_ctrl_reg.clearBit<PERV_TOD_M_PATH_CTRL_REG_1_STEP_ALIGN_DISABLE>(); - // Set step check CPS deviation to 50% - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION, - PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN>( - STEP_CHECK_CPS_DEVIATION_50_00_PCENT); + // Set 512 steps per sync for path 1 + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT, + PERV_TOD_M_PATH_CTRL_REG_SYNC_CREATE_SPS_SELECT_LEN>( + TOD_M_PATH_CTRL_REG_M_PATH_SYNC_CREATE_SPS_512); - // 8 valid steps are required before step check is enabled - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT, - PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN>( - STEP_CHECK_VALIDITY_COUNT_8); - } - else - { - FAPI_DBG("OSC1 is not connected."); + // Set step check CPS deviation to 50% + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION, + PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_CPS_DEVIATION_LEN>( + STEP_CHECK_CPS_DEVIATION_50_00_PCENT); - // OSC1 is not connected; any previous path-1 settings will be ignored - l_m_path_ctrl_reg.setBit<PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID>(); - } + // 8 valid steps are required before step check is enabled + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT, + PERV_TOD_M_PATH_CTRL_REG_1_STEP_CHECK_VALIDITY_COUNT_LEN>( + STEP_CHECK_VALIDITY_COUNT_8); + } + else + { + FAPI_DBG("OSC1 is not connected."); - // CPS deviation factor configures both path-0 and path-1 - l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR, - PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN>( - STEP_CHECK_CPS_DEVIATION_FACTOR_1); + // OSC1 is not connected; any previous path-1 settings will be ignored + l_m_path_ctrl_reg.setBit<PERV_TOD_M_PATH_CTRL_REG_1_OSC_NOT_VALID>(); + } + + // CPS deviation factor configures both path-0 and path-1 + l_m_path_ctrl_reg.insertFromRight<PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR, + PERV_TOD_M_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR_LEN>( + STEP_CHECK_CPS_DEVIATION_FACTOR_1); + } FAPI_TRY(fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_M_PATH_CTRL_REG, @@ -1058,13 +1077,10 @@ fapi2::ReturnCode configure_tod_node( i_osc_sel), "Error from configure_port_ctrl_regs!"); - if (is_mdmt) - { - FAPI_TRY(configure_m_path_ctrl_reg(i_tod_node, - i_tod_sel, - i_osc_sel), - "Error from configure_m_path_ctrl_reg!"); - } + FAPI_TRY(configure_m_path_ctrl_reg(i_tod_node, + i_tod_sel, + i_osc_sel), + "Error from configure_m_path_ctrl_reg!"); FAPI_TRY(configure_i_path_ctrl_reg(i_tod_node, i_tod_sel, diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_addr_ext.C b/src/import/chips/p9/procedures/hwp/nest/p9a_addr_ext.C index 4f6aeeb07..31f826501 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9a_addr_ext.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_addr_ext.C @@ -69,7 +69,8 @@ fapi_try_exit: /* - * As documented + * As documented (TYPO in BAR Bits) + * They should be naturally ordered. * BAR Bits 6 8 9 7 10 11 12 13 * 0x00 15 16 17 18 21 20 19 14 * 0x04 15 16 17 18 21 20 14 19 @@ -92,29 +93,6 @@ fapi_try_exit: * 0xF6 15 21 14 20 19 18 17 16 * 0xF7 15 14 21 20 19 18 17 16 * - * Ordered bar bits - * BAR Bits 5 6 7 8 9 10 11 12 13 14 ... - * 0x00 13 15 18 16 17 21 20 19 14 22 ... - * 0x04 13 15 18 16 17 21 20 14 19 22 ... - * 0x06 13 15 18 16 17 21 14 20 19 22 ... - * 0x07 13 15 18 16 17 14 21 20 19 22 ... - * 0x80 13 15 18 16 17 21 20 19 14 22 ... - * 0x84 13 15 18 16 17 21 20 14 19 22 ... - * 0x86 13 15 18 16 17 21 14 20 19 22 ... - * 0x87 13 15 18 16 17 14 21 20 19 22 ... - * 0xC0 13 15 21 17 18 20 19 14 16 22 ... - * 0xC4 13 15 21 17 18 20 14 19 16 22 ... - * 0xC6 13 15 21 17 18 14 20 19 16 22 ... - * 0xC7 13 15 14 17 18 21 20 19 16 22 ... - * 0xE0 13 15 20 18 21 19 14 17 16 22 ... - * 0xE4 13 15 20 18 21 14 19 17 16 22 ... - * 0xE6 13 15 14 18 21 20 19 17 16 22 ... - * 0xE7 13 15 21 18 14 20 19 17 16 22 ... - * 0xF0 13 15 19 21 20 14 18 17 16 22 ... - * 0xF4 13 15 14 21 20 19 18 17 16 22 ... - * 0xF6 13 15 20 21 14 19 18 17 16 22 ... - * 0xF7 13 15 20 14 21 19 18 17 16 22 ... - * * */ fapi2::ReturnCode extendBarAddress(const uint64_t& i_ext_mask, const fapi2::buffer<uint64_t>& i_bar_addr, @@ -127,27 +105,27 @@ fapi2::ReturnCode extendBarAddress(const uint64_t& i_ext_mask, const fapi2::buff static const int NUM_EXT_MASKS = 20; // 20 different extension masks are supported static const uint64_t EXT_MASK_REORDER[][9] = // Workbook table 7 { - // B 6 7 8 9 10 11 12 13 - { 0x00, 15, 18, 16, 17, 21, 20, 19, 14 }, - { 0x04, 15, 18, 16, 17, 21, 20, 14, 19 }, - { 0x06, 15, 18, 16, 17, 21, 14, 20, 19 }, - { 0x07, 15, 18, 16, 17, 14, 21, 20, 19 }, - { 0x80, 15, 18, 16, 17, 21, 20, 19, 14 }, - { 0x84, 15, 18, 16, 17, 21, 20, 14, 19 }, - { 0x86, 15, 18, 16, 17, 21, 14, 20, 19 }, - { 0x87, 15, 18, 16, 17, 14, 21, 20, 19 }, - { 0xC0, 15, 21, 17, 18, 20, 19, 14, 16 }, - { 0xC4, 15, 21, 17, 18, 20, 14, 19, 16 }, - { 0xC6, 15, 21, 17, 18, 14, 20, 19, 16 }, - { 0xC7, 15, 14, 17, 18, 21, 20, 19, 16 }, - { 0xE0, 15, 20, 18, 21, 19, 14, 17, 16 }, - { 0xE4, 15, 20, 18, 21, 14, 19, 17, 16 }, - { 0xE6, 15, 14, 18, 21, 20, 19, 17, 16 }, - { 0xE7, 15, 21, 18, 14, 20, 19, 17, 16 }, - { 0xF0, 15, 19, 21, 20, 14, 18, 17, 16 }, - { 0xF4, 15, 14, 21, 20, 19, 18, 17, 16 }, - { 0xF6, 15, 20, 21, 14, 19, 18, 17, 16 }, - { 0xF7, 15, 20, 14, 21, 19, 18, 17, 16 } + // B 6 7 8 9 10 11 12 13 + { 0x00, 15, 16, 17, 18, 21, 20, 19, 14 }, + { 0x04, 15, 16, 17, 18, 21, 20, 14, 19 }, + { 0x06, 15, 16, 17, 18, 21, 14, 20, 19 }, + { 0x07, 15, 16, 17, 18, 14, 21, 20, 19 }, + { 0x80, 15, 16, 17, 18, 21, 20, 19, 14 }, + { 0x84, 15, 16, 17, 18, 21, 20, 14, 19 }, + { 0x86, 15, 16, 17, 18, 21, 14, 20, 19 }, + { 0x87, 15, 16, 17, 18, 14, 21, 20, 19 }, + { 0xC0, 15, 17, 18, 21, 20, 19, 14, 16 }, + { 0xC4, 15, 17, 18, 21, 20, 14, 19, 16 }, + { 0xC6, 15, 17, 18, 21, 14, 20, 19, 16 }, + { 0xC7, 15, 17, 18, 14, 21, 20, 19, 16 }, + { 0xE0, 15, 18, 21, 20, 19, 14, 17, 16 }, + { 0xE4, 15, 18, 21, 20, 14, 19, 17, 16 }, + { 0xE6, 15, 18, 21, 14, 20, 19, 17, 16 }, + { 0xE7, 15, 18, 14, 21, 20, 19, 17, 16 }, + { 0xF0, 15, 21, 20, 19, 14, 18, 17, 16 }, + { 0xF4, 15, 21, 20, 14, 19, 18, 17, 16 }, + { 0xF6, 15, 21, 14, 20, 19, 18, 17, 16 }, + { 0xF7, 15, 14, 21, 20, 19, 18, 17, 16 } }; uint64_t l_bar = i_bar_addr; diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C index c2cb8d8ef..836d63057 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_get_mmio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,8 +55,8 @@ fapi2::ReturnCode p9a_get_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> std::vector<uint8_t>& o_data) { uint8_t data[8]; - uint8_t l_idx; - uint8_t l_data_idx; + uint32_t l_idx; + uint32_t l_data_idx; uint32_t l_max_grans; uint32_t l_grans; p9_ADU_oper_flag l_myAduFlag; @@ -82,7 +82,7 @@ fapi2::ReturnCode p9a_get_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> } FAPI_TRY(addOMIBase(i_target, l_addr)); - FAPI_INF("Read address: 0x%lX transaction size: %d", l_addr, l_tsize); + FAPI_DBG("Read address: 0x%lX transaction size: %d", l_addr, l_tsize); l_proc_target = i_target.getParent<fapi2::TARGET_TYPE_OMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); @@ -120,7 +120,7 @@ fapi2::ReturnCode p9a_get_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> sprintf(&l_hexdata[l_i * 2], "%02X", o_data[l_i]); } - FAPI_INF("Read data: 0x%s", l_hexdata); + FAPI_DBG("Read data: 0x%s", l_hexdata); fapi_try_exit: diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.C b/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.C index e5efc07c5..9801e8f30 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.C @@ -45,7 +45,7 @@ #include <p9_mc_scom_addresses.H> #include <p9a_misc_scom_addresses.H> #include <p9a_misc_scom_addresses_fld.H> -#include <chips/ocmb/explorer/procedures/hwp/memory/exp_inband.H> +#include <lib/inband/exp_inband.H> //----------------------------------------------------------------------------------- // Function definitions diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.mk b/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.mk index d24e4e5f0..b7428fc57 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.mk +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_omi_setup_bars.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2017,2019 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -25,5 +25,6 @@ PROCEDURE=p9a_omi_setup_bars OBJS+=p9_fbc_utils.o OBJS+=p9a_addr_ext.o +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/ocmb/explorer/procedures/hwp/memory/) $(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C index adebd16da..fb1a2c13b 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_put_mmio.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,8 +55,8 @@ fapi2::ReturnCode p9a_put_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> const std::vector<uint8_t>& i_data) { uint8_t data[8]; - uint8_t l_idx; - uint8_t l_data_idx; + uint32_t l_idx; + uint32_t l_data_idx; uint32_t l_max_grans; uint32_t l_grans; p9_ADU_oper_flag l_myAduFlag; @@ -87,8 +87,8 @@ fapi2::ReturnCode p9a_put_mmio(const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> } FAPI_TRY(addOMIBase(i_target, l_addr)); - FAPI_INF("Write address: %lX", l_addr); - FAPI_INF("Write data: %s", l_hexdata); + FAPI_DBG("Write address: %lX", l_addr); + FAPI_DBG("Write data: %s", l_hexdata); l_proc_target = i_target.getParent<fapi2::TARGET_TYPE_OMI>().getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.C b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.C new file mode 100644 index 000000000..c288c1fb2 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.C @@ -0,0 +1,346 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// ---------------------------------------------------------------------------- +/// @file p9_throttle_sync.C +/// +/// @brief Perform p9_throttle_sync HWP +/// +/// The purpose of this procedure is to triggers sync command from a 'master' +/// MC to other MCs that have attached memory in a processor. +/// +/// ---------------------------------------------------------------------------- +/// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com> +/// *HWP HWP Backup : Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +/// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +/// *HWP Team : Nest +/// *HWP Level : 3 +/// *HWP Consumed by : HB +/// ---------------------------------------------------------------------------- + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <p9a_throttle_sync.H> +#include <fapi2.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/c_str.H> +#include <lib/shared/axone_consts.H> + +/// +/// @brief Program MCMODE0 based on the functional targets +/// +/// @param[in] i_mi_target The MC target to be programmed +/// @param[in] i_mi_targets Other MC targets. +/// +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode prog_MCMODE0( + const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_mc_target, + const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MI> >& i_mc_targets) +{ + FAPI_DBG("Entering prog_MCMODE0 on target %s", mss::c_str(i_mc_target)); + // -------------------------------------------------------------- + // Setup MCMODE0 for disabling MC SYNC to other-side and same-side + // partner unit. + // BIT27: set if other-side MC is non-functional, 0<->2, 1<->3 + // BIT28: set if same-side MC is non-functional, 0<->1, 2<->3 + // -------------------------------------------------------------- + fapi2::buffer<uint64_t> l_scomData(0); + fapi2::buffer<uint64_t> l_scomMask(0); + bool l_other_side_functional = false; + bool l_same_side_functional = false; + uint8_t l_current_pos = 0; + uint8_t l_other_side_pos = 0; + uint8_t l_same_side_pos = 0; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_mc_target, l_current_pos), + "Error getting ATTR_CHIP_UNIT_POS on %s", mss::c_str(i_mc_target)); + + // Calculate the peer MC in the other side and in the same side. + l_other_side_pos = (l_current_pos + MAX_MC_PER_SIDE) % MAX_MC_PER_PROC; + l_same_side_pos = ((l_current_pos / MAX_MC_SIDES_PER_PROC) * MAX_MC_PER_SIDE) + + ((l_current_pos % MAX_MC_PER_SIDE) + 1) % MAX_MC_PER_SIDE; + + FAPI_DBG("Current pos: %i, other side pos: %i, same side pos: %i", + l_current_pos, l_other_side_pos, l_same_side_pos); + + // Determine side functionality + for (const auto& l_mc : i_mc_targets) + { + uint8_t l_tmp_pos = 0; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc, l_tmp_pos), + "Error getting ATTR_CHIP_UNIT_POS on %s", mss::c_str(l_mc)); + + // The other side + if (l_tmp_pos == l_other_side_pos) + { + l_other_side_functional = true; + } + + // The same side + if (l_tmp_pos == l_same_side_pos) + { + l_same_side_functional = true; + } + } + + l_scomData.flush<0>(); + l_scomMask.flush<0>(); + + if (!l_other_side_functional) + { + l_scomData.setBit<P9A_MI_MCMODE0_DISABLE_MC_SYNC>(); + l_scomMask.setBit<P9A_MI_MCMODE0_DISABLE_MC_SYNC>(); + } + else + { + l_scomData.clearBit<P9A_MI_MCMODE0_DISABLE_MC_SYNC>(); + l_scomMask.setBit<P9A_MI_MCMODE0_DISABLE_MC_SYNC>(); + } + + if (!l_same_side_functional) + { + l_scomData.setBit<P9A_MI_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + l_scomMask.setBit<P9A_MI_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + } + else + { + l_scomData.clearBit<P9A_MI_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + l_scomMask.setBit<P9A_MI_MCMODE0_DISABLE_MC_PAIR_SYNC>(); + } + + FAPI_DBG("Writing MCS_MCMODE0 reg 0x%016llX: Mask 0x%016llX , Data 0x%016llX", + P9A_MI_MCMODE0, l_scomMask, l_scomData); + + FAPI_TRY(fapi2::putScomUnderMask(i_mc_target, P9A_MI_MCMODE0, l_scomData, l_scomMask), + "putScomUnderMask() returns an error, P9A_MI_MCMODE0 reg 0x%016llX", P9A_MI_MCMODE0); + +fapi_try_exit: + FAPI_DBG("Exiting prog_MCMODE0"); + return fapi2::current_err; +} + +/// +/// @brief Programming master MCS +/// Writes P9A_MI_MCSYNC reg to set the input MCS as the master. +/// +/// @param[in] i_mcsTarget The MCS target to be programmed as master. +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode prog_master(const fapi2::Target<fapi2::TARGET_TYPE_MI>& i_mc_target) +{ + FAPI_DBG("Entering progMaster with target %s", mss::c_str(i_mc_target)); + fapi2::buffer<uint64_t> l_scomData(0); + fapi2::buffer<uint64_t> l_scomMask(0); + + // ------------------------------------------------------------------- + // 1. Reset sync command + // ------------------------------------------------------------------- + + // Clear GO bit + l_scomMask.flush<0>().setBit<P9A_MI_MCSYNC_SYNC_GO>(); + l_scomData.flush<0>(); + FAPI_TRY(fapi2::putScomUnderMask(i_mc_target, P9A_MI_MCSYNC, l_scomData, l_scomMask), + "putScomUnderMask() returns an error (Reset), P9A_MI_MCSYNC reg 0x%016llX", P9A_MI_MCSYNC); + + // -------------------------------------------------------------- + // 2. Setup MC Sync Command Register data for master MCS or MI + // -------------------------------------------------------------- + + // Clear buffers + l_scomData.flush<0>(); + l_scomMask.flush<0>(); + + // Force bit set in case cleared from last procedure run + l_scomData.setBit<EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN>(); + l_scomMask.setBit<EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN>(); + + // Iterate through OCMBs to make sure refresh SYNC bit is set + for (const auto& l_ocmb : mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_mc_target)) + { + FAPI_DBG("Writing EXPLR_SRQ_MBA_SYNCCNTLQ reg 0x%016llX: Data 0x%016llX Mask 0x%016llX", + EXPLR_SRQ_MBA_SYNCCNTLQ, l_scomData, l_scomMask); + + FAPI_TRY(fapi2::putScomUnderMask(l_ocmb, EXPLR_SRQ_MBA_SYNCCNTLQ, l_scomData, l_scomMask), + "Error writing to REG 0x%016llX of %s", EXPLR_SRQ_MBA_SYNCCNTLQ, mss::c_str(l_ocmb)); + } + + // Clear buffers + l_scomData.flush<0>(); + l_scomMask.flush<0>(); + + // Setup MCSYNC_CHANNEL_SELECT + // Set ALL channels with or without DIMMs (bits 0:7) + l_scomData.setBit<P9A_MI_MCSYNC_CHANNEL_SELECT, + P9A_MI_MCSYNC_CHANNEL_SELECT_LEN>(); + l_scomMask.setBit<P9A_MI_MCSYNC_CHANNEL_SELECT, + P9A_MI_MCSYNC_CHANNEL_SELECT_LEN>(); + + // Setup MCSYNC_SYNC_TYPE for SYNC ALL + l_scomData.setBit<P9A_MI_MCSYNC_SYNC_TYPE>(); + l_scomMask.setBit<P9A_MI_MCSYNC_SYNC_TYPE>(); + + // Setup SYNC_GO (bit 16 is now used for both channels) + l_scomMask.setBit<P9A_MI_MCSYNC_SYNC_GO>(); + l_scomData.setBit<P9A_MI_MCSYNC_SYNC_GO>(); + + // -------------------------------------------------------------- + // 3. Write to MC Sync Command Register of master MCS or MI + // -------------------------------------------------------------- + // Write to MCSYNC reg + FAPI_DBG("Writing P9A_MI_MCSYNC reg 0x%016llX: Mask 0x%016llX , Data 0x%016llX", + P9A_MI_MCSYNC, l_scomMask, l_scomData); + + FAPI_TRY(fapi2::putScomUnderMask(i_mc_target, P9A_MI_MCSYNC, l_scomData, l_scomMask), + "putScomUnderMask() returns an error (Sync), P9A_MI_MCSYNC reg 0x%016llX", P9A_MI_MCSYNC); + + // Note: No need to read Sync replay count and retry in P9. + + // -------------------------------------------------------------- + // 4. Clear refresh sync bit + // -------------------------------------------------------------- + l_scomData.flush<0>(); + l_scomMask.flush<0>().setBit<EXPLR_SRQ_MBA_SYNCCNTLQ_SYNC_REF_EN>(); + + // Iterate through OCMBs to clear refresh sync bit + for (const auto& l_ocmb : mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_mc_target)) + { + FAPI_DBG("Writing EXPLR_SRQ_MBA_SYNCCNTLQ reg 0x%016llX: Mask 0x%016llX , Data 0x%016llX on %s", + EXPLR_SRQ_MBA_SYNCCNTLQ, l_scomMask, l_scomData, mss::c_str(l_ocmb)); + + FAPI_TRY(fapi2::putScomUnderMask(l_ocmb, EXPLR_SRQ_MBA_SYNCCNTLQ, l_scomData, l_scomMask), + "putScomUnderMask() returns an error (Sync), EXPLR_SRQ_MBA_SYNCCNTLQ reg 0x%016llX", + EXPLR_SRQ_MBA_SYNCCNTLQ); + } + +fapi_try_exit: + FAPI_DBG("Exiting progMaster"); + return fapi2::current_err; +} + +/// +/// @brief Perform throttle sync on the Memory Controllers +/// +/// @param[in] i_mc_targets vector of reference of MC targets (MCS or MI) +/// @return FAPI2_RC_SUCCESS if success, else error code. +/// +fapi2::ReturnCode throttle_sync( + const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MI> >& i_mc_targets) +{ + mc_side_info_t l_mcSide[MAX_MC_SIDES_PER_PROC]; + uint8_t l_sideNum = 0; + uint8_t l_pos = 0; + uint8_t l_numMasterProgrammed = 0; + + // Initialization + for (l_sideNum = 0; l_sideNum < MAX_MC_SIDES_PER_PROC; l_sideNum++) + { + l_mcSide[l_sideNum].master_mc_found = false; + } + + // --------------------------------------------------------------------- + // 1. Pick the first MCS/MI with DIMMS as potential master + // for both MC sides (MC01/MC23) + // --------------------------------------------------------------------- + for (const auto& l_mc : i_mc_targets) + { + uint8_t l_num_dimms = mss::find_targets<fapi2::TARGET_TYPE_DIMM>(l_mc).size(); + + if (l_num_dimms > 0) + { + // This MCS or MI has DIMMs attached, find out which MC side it + // belongs to: + // l_sideNum = 0 --> MC01 + // 1 --> MC23 + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_mc, l_pos), + "Error getting ATTR_CHIP_UNIT_POS on %s", mss::c_str(l_mc)); + l_sideNum = l_pos / MAX_MC_SIDES_PER_PROC; + + FAPI_INF("MCS %u has DIMMs", l_pos); + + // If there's no master MCS or MI marked for this side yet, mark + // this MCS as master + if (l_mcSide[l_sideNum].master_mc_found == false) + { + FAPI_INF("Mark MCS %u as master for MC side %u", + l_pos, l_sideNum); + l_mcSide[l_sideNum].master_mc_found = true; + l_mcSide[l_sideNum].master_mc = l_mc; + } + } + + prog_MCMODE0(l_mc, i_mc_targets); + } + + // -------------------------------------------------------------- + // 2. Program the master MI + // -------------------------------------------------------------- + for (l_sideNum = 0; l_sideNum < MAX_MC_SIDES_PER_PROC; l_sideNum++) + { + // If there is a potential master MI found for this side + if (l_mcSide[l_sideNum].master_mc_found == true) + { + // No master MI programmed for either side yet, + // go ahead and program this MI as master. + if (l_numMasterProgrammed == 0) + { + FAPI_TRY(prog_master(l_mcSide[l_sideNum].master_mc), + "programMaster() returns error on %s", mss::c_str(l_mcSide[l_sideNum].master_mc)); + l_numMasterProgrammed++; + } + } + } + +fapi_try_exit: + FAPI_DBG("Exiting"); + return fapi2::current_err; +} + +extern "C" +{ + /// + /// @brief p9a_throttle_sync procedure + /// + /// @param[in] i_target TARGET_TYPE_PROC_CHIP target + /// @return FAPI2_RC_SUCCESS if success, else error code. + /// + fapi2::ReturnCode p9a_throttle_sync( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) + { + FAPI_DBG("Executing p9a_throttle_sync on %s", mss::c_str(i_target)); + + const auto l_miChiplets = i_target.getChildren<fapi2::TARGET_TYPE_MI>(); + + if (l_miChiplets.size() > 0) + { + FAPI_TRY(throttle_sync(l_miChiplets), "Error calling throttle_sync() with vector of MI Chiplets"); + } + + fapi_try_exit: + FAPI_DBG("Exiting"); + return fapi2::current_err; + } + +} // extern "C" diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.H b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.H new file mode 100644 index 000000000..c87312b23 --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.H @@ -0,0 +1,78 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// ---------------------------------------------------------------------------- +/// @file p9a_throttle_sync.H +/// +/// @brief p9a_throttle_sync HWP +/// +/// The purpose of this procedure is to triggers sync command from a 'master' +/// MC to other MCs that have attached memory in a processor. +/// +/// ---------------------------------------------------------------------------- +/// *HWP HWP Owner : Joe McGill <jmcgill@us.ibm.com> +/// *HWP HWP Backup : Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +/// *HWP FW Owner : Thi Tran <thi@us.ibm.com> +/// *HWP Team : Nest +/// *HWP Level : 3 +/// *HWP Consumed by : HB +/// ---------------------------------------------------------------------------- +#ifndef _P9A_THROTTLE_SYNC_H_ +#define _P9A_THROTTLE_SYNC_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +#include <p9a_mc_scom_addresses_fld.H> +#include <p9a_misc_scom_addresses_fld.H> +#include <p9a_misc_scom_addresses.H> +#include <explorer_scom_addresses.H> +#include <explorer_scom_addresses_fld.H> + +// Function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9a_throttle_sync_FP_t)(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + +/// +/// @brief Structure that holds the potential master MI for a MC side (MC01/MC23) +/// +struct mc_side_info_t +{ + bool master_mc_found = false; + fapi2::Target<fapi2::TARGET_TYPE_MI> master_mc; // Master MC for this MC side +}; + +extern "C" +{ + /// + /// @brief p9a_throttle_sync procedure + /// + /// @param[in] i_target TARGET_TYPE_PROC_CHIP target + /// @return FAPI2_RC_SUCCESS if success, else error code. + /// + fapi2::ReturnCode p9a_throttle_sync(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + +} // extern "C" + +#endif // _P9A_THROTTLE_SYNC_H_ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.mk b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.mk new file mode 100644 index 000000000..cf235b53d --- /dev/null +++ b/src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.mk @@ -0,0 +1,30 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/import/chips/p9/procedures/hwp/nest/p9a_throttle_sync.mk $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2019 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +PROCEDURE=p9a_throttle_sync +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)/chips/p9a/procedures/hwp/memory/) + +$(call ADD_MODULE_INCDIR,$(PROCEDURE),$(ROOTPATH)) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_nv_ref_clk_enable.C b/src/import/chips/p9/procedures/hwp/perv/p9_nv_ref_clk_enable.C index 43e396486..8c64aa78a 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_nv_ref_clk_enable.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_nv_ref_clk_enable.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -43,12 +43,16 @@ #include <p9_nv_ref_clk_enable.H> #include <p9_perv_scom_addresses.H> #include <p9_perv_scom_addresses_fld.H> +#include <p9a_perv_scom_addresses.H> +#include <p9a_perv_scom_addresses_fld.H> //------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ const uint16_t TPFSI_OFFCHIP_REFCLK_EN_NV = 0xF; +// P9A_PERV_ROOT_CTRL7_TP_TPIO_NV_REFCLK_EN_DC_LEN == 6 +const uint16_t P9A_NV_REFCLK_BIT_LEN = 4; //------------------------------------------------------------------------------ // Function definitions @@ -58,13 +62,27 @@ fapi2::ReturnCode p9_nv_ref_clk_enable(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { FAPI_INF("Start"); - fapi2::buffer<uint64_t> l_root_ctrl6; - FAPI_TRY(fapi2::getScom(i_target, PERV_ROOT_CTRL6_SCOM, l_root_ctrl6), - "Error from getScom (PERV_ROOT_CTRL6_SCOM)"); - l_root_ctrl6.insertFromRight<PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC, - PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC_LEN>(TPFSI_OFFCHIP_REFCLK_EN_NV); - FAPI_TRY(fapi2::putScom(i_target, PERV_ROOT_CTRL6_SCOM, l_root_ctrl6), - "Error from putScom (PERV_ROOT_CTRL6_SCOM)"); + fapi2::buffer<uint64_t> l_root_ctrl; + fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP_Type l_one_npu; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_ONE_NPU_TOP, i_target, l_one_npu)); + + if (l_one_npu) + { + FAPI_TRY(fapi2::getScom(i_target, PERV_ROOT_CTRL6_SCOM, l_root_ctrl), + "Error from getScom (PERV_ROOT_CTRL6_SCOM)"); + l_root_ctrl.insertFromRight<PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC, + PERV_ROOT_CTRL6_TSFSI_NV_REFCLK_EN_DC_LEN>(TPFSI_OFFCHIP_REFCLK_EN_NV); + FAPI_TRY(fapi2::putScom(i_target, PERV_ROOT_CTRL6_SCOM, l_root_ctrl), + "Error from putScom (PERV_ROOT_CTRL6_SCOM)"); + } + else + { + FAPI_TRY(fapi2::getScom(i_target, P9A_PERV_ROOT_CTRL7_SCOM, l_root_ctrl), + "Error from getScom (P9A_PERV_ROOT_CTRL7_SCOM)"); + l_root_ctrl.setBit<P9A_PERV_ROOT_CTRL7_TP_TPIO_NV_REFCLK_EN_DC, P9A_NV_REFCLK_BIT_LEN>(); + FAPI_TRY(fapi2::putScom(i_target, P9A_PERV_ROOT_CTRL7_SCOM, l_root_ctrl), + "Error from putScom (P9A_PERV_ROOT_CTRL7_SCOM)"); + } fapi_try_exit: FAPI_INF("End"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H index 9390108ed..5b39fc2a9 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_proc_gettracearray.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -63,6 +63,7 @@ static const fapi2::TargetType PROC_GETTRACEARRAY_TARGET_TYPES = fapi2::TARGET_TYPE_PROC_CHIP | fapi2::TARGET_TYPE_OBUS | fapi2::TARGET_TYPE_MCBIST | + fapi2::TARGET_TYPE_MC | fapi2::TARGET_TYPE_EX | fapi2::TARGET_TYPE_CORE; @@ -98,10 +99,22 @@ extern "C" { return fapi2::TARGET_TYPE_EX; } - else + else if (i_trace_bus <= _PROC_TB_LAST_CORE_TARGET) { return fapi2::TARGET_TYPE_CORE; } + else if (i_trace_bus <= _PROC_TB_LAST_AXONE_CHIP_TARGET) + { + return fapi2::TARGET_TYPE_PROC_CHIP; + } + else if (i_trace_bus <= _PROC_TB_LAST_AXONE_MC_TARGET) + { + return fapi2::TARGET_TYPE_MC; + } + else + { + return fapi2::TARGET_TYPE_EX; + } } /** diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C index 24d789f02..87e1d5b70 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_ram_core.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -49,6 +49,8 @@ const uint32_t RAM_REG_MSR = 2001; const uint32_t RAM_REG_CR = 2002; const uint32_t RAM_REG_FPSCR = 2003; const uint32_t RAM_REG_VSCR = 2004; +const uint32_t RAM_REG_SLBE = 2005; +const uint32_t RAM_REG_SLBV = 2006; // opcode for ramming const uint32_t OPCODE_MTSPR_FROM_GPR0_TO_SPRD = 0x7C1543A6; @@ -602,6 +604,16 @@ fapi2::ReturnCode RamCore::get_reg(const Enum_RegType i_type, opcodes[8] = {&l_backup_vr0_dw0, OPCODE_MFSPR_FROM_SPRD_TO_GPR0 + (1 << 21), NULL}; opcodes[9] = {NULL, OPCODE_MTVSRDD_FROM_GPR1_0_TO_VSR32, NULL}; } + else if(i_reg_num == RAM_REG_SLBE) + { + opcodes[0] = {NULL, OPCODE_SLBMFEE, NULL}; + opcodes[1] = {NULL, OPCODE_MTSPR_FROM_GPR0_TO_SPRD, &o_buffer[0]}; + } + else if(i_reg_num == RAM_REG_SLBV) + { + opcodes[0] = {NULL, OPCODE_SLBMFEV, NULL}; + opcodes[1] = {NULL, OPCODE_MTSPR_FROM_GPR0_TO_SPRD, &o_buffer[0]}; + } else { //1.create mfspr<gpr0, i_reg_num> opcode, ram into thread diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C index 64153812f..fa51f80f9 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_hreset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017,2018 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -55,6 +55,7 @@ fapi2::ReturnCode p9_sbe_i2c_bit_rate_divisor_setting( { uint8_t l_attr_nest_pll_bucket = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2_Type l_i2cm_internal_clk_div2 = 0; fapi2::buffer<uint16_t> l_mb_bit_rate_divisor; fapi2::buffer<uint64_t> l_data64; fapi2::buffer<uint32_t> l_data32; @@ -63,7 +64,12 @@ fapi2::ReturnCode p9_sbe_i2c_bit_rate_divisor_setting( FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_attr_nest_pll_bucket)); FAPI_INF("ATTR_NEST_PLL_BUCKET value: %d", l_attr_nest_pll_bucket); - l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1]; + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2, i_target_chip, l_i2cm_internal_clk_div2)); + + l_mb_bit_rate_divisor = NEST_PLL_FREQ_I2CDIV_LIST[l_attr_nest_pll_bucket - 1] * + ((l_i2cm_internal_clk_div2) ? (2) : (1)); + FAPI_INF("Bit_rate_divisor value: %d", l_mb_bit_rate_divisor); FAPI_DBG("Adjust I2C bit rate divisor setting in I2CM B Mode Reg"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C index fdb602e74..640347186 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -103,14 +103,15 @@ enum chip_type_and_ec { NIMBUS = 1, CUMULUS = 2, - OTHER = 4, + AXONE = 4, + OTHER = 128, ANY_CHIP = 0xFF, }; struct ta_def { /* One entry per mux setting; value of 0 means N/A */ - p9_tracearray_bus_id bus_ids[TRACE_MUX_POSITIONS]; + uint8_t bus_ids[TRACE_MUX_POSITIONS]; const uint8_t ex_odd_scom_offset: 2; const uint8_t chiplet: 6; const uint8_t base_multiplier; @@ -133,12 +134,15 @@ struct ta_def { { PROC_TB_PB9 }, 0x00, 0x03, 0x03, ANY_CHIP }, { { PROC_TB_PB10 }, 0x00, 0x03, 0x04, ANY_CHIP }, { { PROC_TB_PB11 }, 0x00, 0x03, 0x05, ANY_CHIP }, - { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, 0x00, 0x03, 0x06, ANY_CHIP }, - { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, 0x00, 0x03, 0x07, ANY_CHIP }, + { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS }, 0x00, 0x03, 0x06, NIMBUS | CUMULUS }, + { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13 }, 0x00, 0x03, 0x07, NIMBUS | CUMULUS }, + { { PROC_TB_MCD0, PROC_TB_MCD1, PROC_TB_VAS, PROC_TB_NPU20 }, 0x00, 0x03, 0x06, AXONE }, + { { PROC_TB_MCS2, PROC_TB_MCS3, PROC_TB_PB13, PROC_TB_NPU21 }, 0x00, 0x03, 0x07, AXONE }, { { PROC_TB_PBIO0 }, 0x00, 0x03, 0x08, ANY_CHIP }, { { PROC_TB_PBIO1 }, 0x00, 0x03, 0x09, ANY_CHIP }, /* N2 */ - { { PROC_TB_CXA1, PROC_TB_IOPSI }, 0x00, 0x04, 0x00, ANY_CHIP }, + { { PROC_TB_CXA1, PROC_TB_IOPSI }, 0x00, 0x04, 0x00, NIMBUS | CUMULUS }, + { { NO_TB, PROC_TB_IOPSI }, 0x00, 0x04, 0x00, AXONE }, { { PROC_TB_PCIS0, PROC_TB_PCIS1, PROC_TB_PCIS2 }, 0x00, 0x04, 0x01, ANY_CHIP }, /* N3 */ { { PROC_TB_PB0 }, 0x00, 0x05, 0x00, ANY_CHIP }, @@ -147,10 +151,13 @@ struct ta_def { { PROC_TB_PB3 }, 0x00, 0x05, 0x03, ANY_CHIP }, { { PROC_TB_PB4 }, 0x00, 0x05, 0x04, ANY_CHIP }, { { PROC_TB_PB5 }, 0x00, 0x05, 0x05, ANY_CHIP }, - { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, 0x00, 0x05, 0x06, ANY_CHIP }, - { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, 0x00, 0x05, 0x07, ANY_CHIP }, + { { PROC_TB_INT, PROC_TB_NPU1, PROC_TB_NMMU1 }, 0x00, 0x05, 0x06, NIMBUS | CUMULUS }, + { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12 }, 0x00, 0x05, 0x07, NIMBUS | CUMULUS }, + { { PROC_TB_NPU10, PROC_TB_INT, PROC_TB_NMMU1, PROC_TB_NPU01 }, 0x00, 0x05, 0x06, AXONE }, + { { PROC_TB_MCS0, PROC_TB_MCS1, PROC_TB_PB12, PROC_TB_NPU11 }, 0x00, 0x05, 0x07, AXONE }, { { PROC_TB_BRIDGE }, 0x00, 0x05, 0x08, ANY_CHIP }, - { { PROC_TB_NPU0 }, 0x00, 0x05, 0x0A, ANY_CHIP }, + { { PROC_TB_NPU0 }, 0x00, 0x05, 0x0A, NIMBUS | CUMULUS }, + { { PROC_TB_NPU00 }, 0x00, 0x05, 0x0A, AXONE }, { { PROC_TB_NMMU0 }, 0x00, 0x05, 0x0B, ANY_CHIP }, /* XBUS */ { { PROC_TB_PBIOX0, PROC_TB_IOX0 }, 0x00, 0x06, 0x00, ANY_CHIP }, @@ -166,12 +173,13 @@ struct ta_def { { PROC_TB_MCA0 }, 0x00, 0x07, 0x20, NIMBUS }, { { PROC_TB_MCA1 }, 0x00, 0x07, 0x21, NIMBUS }, { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, 0x00, 0x07, 0x00, NIMBUS }, - { { PROC_TB_MCA0 }, 0x00, 0x07, 0x00, (uint8_t)~NIMBUS }, - { { PROC_TB_MCA1 }, 0x00, 0x07, 0x01, (uint8_t)~NIMBUS }, - { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, 0x00, 0x07, 0x02, (uint8_t)~NIMBUS }, + { { PROC_TB_MCA0 }, 0x00, 0x07, 0x00, CUMULUS | AXONE }, + { { PROC_TB_MCA1 }, 0x00, 0x07, 0x01, CUMULUS | AXONE }, + { { PROC_TB_IOMC0, PROC_TB_IOMC1, PROC_TB_IOMC2, PROC_TB_IOMC3 }, 0x00, 0x07, 0x02, CUMULUS }, + { { PROC_TB_OMI0, PROC_TB_OMI1, PROC_TB_OMI2 }, 0x00, 0x07, 0x02, AXONE }, /* EX */ - { { PROC_TB_L20, NO_TB, NO_TB, PROC_TB_SKIT10 }, 0x01, 0x10, 0x94, ANY_CHIP }, - { { PROC_TB_L21, NO_TB, NO_TB, PROC_TB_SKIT11 }, 0x01, 0x10, 0x95, ANY_CHIP }, + { { PROC_TB_L20, NO_TB, PROC_TB_SKIT00, PROC_TB_SKIT10 }, 0x01, 0x10, 0x94, ANY_CHIP }, + { { PROC_TB_L21, NO_TB, PROC_TB_SKIT01, PROC_TB_SKIT11 }, 0x01, 0x10, 0x95, ANY_CHIP }, { { PROC_TB_L30, PROC_TB_NCU0, PROC_TB_CME, PROC_TB_EQPB }, 0x02, 0x10, 0x00, ANY_CHIP }, { { PROC_TB_L31, PROC_TB_NCU1, PROC_TB_IVRM, PROC_TB_SKEWADJ }, 0x02, 0x10, 0x01, ANY_CHIP }, /* CORE */ @@ -349,6 +357,9 @@ static chip_type_and_ec map_chip_type_and_ec(fapi2::ATTR_NAME_Type i_name, fapi2 case fapi2::ENUM_ATTR_NAME_CUMULUS: return CUMULUS; + case fapi2::ENUM_ATTR_NAME_AXONE: + return AXONE; + default: return OTHER; } @@ -412,24 +423,11 @@ fapi2::ReturnCode p9_sbe_tracearray( } } - /* check that core trace arrays can be logged out, based on EC feature attribute */ - if (ta_type == fapi2::TARGET_TYPE_CORE) - { - uint8_t l_core_trace_not_scomable = 0; - - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> proc_target = - i_target.getParent<fapi2::TARGET_TYPE_PROC_CHIP>(); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE, - proc_target, l_core_trace_not_scomable), - "Failed to query chip EC feature " - "ATTR_CHIP_EC_FEATURE_CORE_TRACE_NOT_SCOMABLE"); - - FAPI_ASSERT(!l_core_trace_not_scomable || - !i_args.collect_dump, - fapi2::PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE() - .set_TARGET(i_target).set_TRACE_BUS(i_args.trace_bus), - "Core arrays cannot be dumped in this chip EC; please use fastarray instead."); - } + /* we cannot dump core trace arrays on any chip - permanent erratum. */ + FAPI_ASSERT(!(i_args.collect_dump && ta_type == fapi2::TARGET_TYPE_CORE), + fapi2::PROC_GETTRACEARRAY_CORE_NOT_DUMPABLE() + .set_TARGET(i_target).set_TRACE_BUS(i_args.trace_bus), + "Core arrays cannot be dumped; please use fastarray instead."); /* For convenience, we link Cache trace arrays to the virtual EX chiplets. * Transform back to EQ chiplet. */ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H index c587924b9..ecaf785f7 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tracearray.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -120,10 +120,22 @@ extern "C" { { return fapi2::TARGET_TYPE_EX; } - else + else if (i_trace_bus <= _PROC_TB_LAST_CORE_TARGET) { return fapi2::TARGET_TYPE_CORE; } + else if (i_trace_bus <= _PROC_TB_LAST_AXONE_CHIP_TARGET) + { + return fapi2::TARGET_TYPE_PROC_CHIP; + } + else if (i_trace_bus <= _PROC_TB_LAST_AXONE_MC_TARGET) + { + return fapi2::TARGET_TYPE_PERV; + } + else + { + return fapi2::TARGET_TYPE_EX; + } } /* TODO via RTC:164528 - Look at optimization to improve performance diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H index 6bf4ac961..abfc2effe 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_spr_name_map.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -234,7 +234,9 @@ typedef std::map<std::string, SPRMapEntry>::iterator SPR_MAP_IT; _op_(MSR ,2001, ECP.SD.T<??T>_MSR ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ _op_(CR ,2002, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ _op_(FPSCR ,2003, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,64)\ - _op_(VSCR ,2004, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32) + _op_(VSCR ,2004, N/A ,FLAG_READ_WRITE ,SPR_PER_PT ,32)\ + _op_(SLBE ,2005, N/A ,FLAG_READ_ONLY ,SPR_PER_PT ,64)\ + _op_(SLBV ,2006, N/A ,FLAG_READ_ONLY ,SPR_PER_PT ,64) #define DO_SPR_MAP(in_name, in_number, in_spy_name, in_flag, in_share_type, in_bit_length)\ SPRMapEntry entry##in_name; \ diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C index 914a78072..13990c15e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -71,7 +71,6 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> fapi2::buffer<uint8_t> l_read_attr; fapi2::buffer<uint8_t> l_fifo_reset_skip; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; - fapi2::buffer<uint8_t> l_is_axone; FAPI_INF("p9_start_cbs: Entering ..."); @@ -81,8 +80,6 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_START_CBS_FIFO_RESET_SKIP, FAPI_SYSTEM, l_fifo_reset_skip)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9A_SBE_REGION, i_target_chip, l_is_axone)); - FAPI_DBG("Clearing Selfboot message register before every boot "); // buffer is init value is 0 FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_SB_MSG_FSI, l_data32)); @@ -203,70 +200,9 @@ fapi2::ReturnCode p9_start_cbs(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> .set_FSI2PIB_STATUS_READ(l_data32), "ERROR:VDD OFF, FSI2PIB BIT 16 NOT SET"); - if (l_is_axone) - { - FAPI_DBG("Switching to PIB2PCB mux sel to 1 [till pcbnet clocks are started]"); - FAPI_TRY(p9_start_cbs_switch_to_pib2pcb_path_cfam(i_target_chip)); - } - FAPI_INF("p9_start_cbs: Exiting ..."); fapi_try_exit: return fapi2::current_err; } - -/// @brief Switching to PIB2PCB Path via cfam -/// -/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP -/// @return FAPI2_RC_SUCCESS if success, else error code. -fapi2::ReturnCode p9_start_cbs_switch_to_pib2pcb_path_cfam(const - fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip) -{ - fapi2::buffer<uint32_t> l_read_reg; - FAPI_INF("p9_start_cbs_switch_to_pib2pcb_path_cfam: Entering ..."); - - FAPI_DBG("Reading ROOT_CTRL0_REG"); - FAPI_TRY(fapi2::getCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - - if (!l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>()) - { - FAPI_DBG("Setting PCB RESET bit in ROOT_CTRL0_REG"); - l_read_reg.setBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - } - - if (!l_read_reg.getBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>()) - { - FAPI_DBG("Setting PIB2PCB bit in ROOT_CTRL0_REG"); - l_read_reg.setBit<PERV_ROOT_CTRL0_18_SPARE_MUX_CONTROL>(); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - } - - if (l_read_reg.getBit<PERV_ROOT_CTRL0_PIB2PCB_DC>()) - { - FAPI_DBG("Clearing FSI2PCB bit in ROOT_CTRL0_REG"); - l_read_reg.clearBit<PERV_ROOT_CTRL0_PIB2PCB_DC>(); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - } - - if (l_read_reg.getBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>()) - { - FAPI_DBG("Clearing PCB2PCB bit in ROOT_CTRL0_REG"); - l_read_reg.clearBit<PERV_ROOT_CTRL0_19_SPARE_MUX_CONTROL>(); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - } - - if (l_read_reg.getBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>()) - { - FAPI_DBG("Clearing PCB RESET bit in ROOT_CTRL0_REG"); - l_read_reg.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); - FAPI_TRY(fapi2::putCfamRegister(i_target_chip, PERV_ROOT_CTRL0_FSI, l_read_reg)); - } - - FAPI_INF("p9_start_cbs_switch_to_pib2pcb_path_cfam: Exiting ..."); - -fapi_try_exit: - return fapi2::current_err; - -} diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_tracearray_defs.H b/src/import/chips/p9/procedures/hwp/perv/p9_tracearray_defs.H index 7cf13bdf9..c0f8d8e32 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_tracearray_defs.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_tracearray_defs.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -166,6 +166,27 @@ enum p9_tracearray_bus_id /* Core chiplets - TARGET_TYPE_CORE */ PROC_TB_CORE0, PROC_TB_CORE1, + + _PROC_TB_LAST_CORE_TARGET = PROC_TB_CORE1, + + /* New Axone trace buses */ + PROC_TB_NPU00, + PROC_TB_NPU01, + PROC_TB_NPU10, + PROC_TB_NPU11, + PROC_TB_NPU20, + PROC_TB_NPU21, + + _PROC_TB_LAST_AXONE_CHIP_TARGET = PROC_TB_NPU21, + + PROC_TB_OMI0, + PROC_TB_OMI1, + PROC_TB_OMI2, + + _PROC_TB_LAST_AXONE_MC_TARGET = PROC_TB_OMI2, + + PROC_TB_SKIT00, + PROC_TB_SKIT01, }; #endif //_P9_TRACEARRAY_DEFS_H diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C index 347bd3545..c40cf595c 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_hcode_image_build.C @@ -97,10 +97,10 @@ extern "C" */ #define ROUND_OFF_32B( ROUND_SIZE) \ { \ - uint32_t tempSize = ROUND_SIZE; \ - if( tempSize ) \ + uint32_t temp = ROUND_SIZE; \ + if( temp ) \ { \ - ROUND_SIZE = (( ( tempSize + 31 )/32 ) * 32 ); \ + ROUND_SIZE = (( ( temp + 31 )/32 ) * 32 ); \ } \ } namespace p9_hcodeImageBuild @@ -146,6 +146,7 @@ enum SMF_BIT_CHECK = 0x0001000000000000ull, INST_VALUE_SC2 = 0x44000042, SRESET_WORD_POS = 0x40, + CPMR_VDM_PER_QUAD = 0x43504d525f322e30ull, //supports VDM per quad }; /** @@ -894,6 +895,8 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO uint16_t qmFlags = 0; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; sgpeHeader_t* pSgpeHdr = (sgpeHeader_t*)& i_pChipHomer->qpmrRegion.sgpeRegion.sgpeSramImage[SGPE_INT_VECTOR_SIZE]; PgpeHeader_t* pPgpeHdr = (PgpeHeader_t*)& i_pChipHomer->ppmrRegion.pgpeSramImage[PGPE_INT_VECTOR_SIZE]; @@ -1295,7 +1298,12 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO FAPI_DBG("WOF Enabled : %s", attrVal ? "TRUE" : "FALSE" ); + if( SWIZZLE_8_BYTE(pCpmrHdr->magic_number) >= CPMR_VDM_PER_QUAD ) + { + qmFlags |= CME_QM_FLAG_PER_QUAD_VDM_ENABLE; + } + FAPI_DBG("Quad VDM Enable : Yes" ); // Updating flag fields in the headers pCmeHdr->g_cme_mode_flags = SWIZZLE_4_BYTE(cmeFlag); @@ -1304,7 +1312,7 @@ fapi2::ReturnCode updateImageFlags( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PRO pPgpeHdr->g_pgpe_flags = SWIZZLE_2_BYTE(pgpeFlag); FAPI_INF("CME Flag Value : 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_mode_flags)); - FAPI_INF("CME QM Flag Value : 0x%08x", SWIZZLE_2_BYTE(pCmeHdr->g_cme_qm_mode_flags)); + FAPI_INF("CME QM Flag Value : 0x%04x", SWIZZLE_2_BYTE(pCmeHdr->g_cme_qm_mode_flags)); FAPI_INF("SGPE Flag Value : 0x%08x", SWIZZLE_4_BYTE(pSgpeHdr->g_sgpe_reserve_flags)); FAPI_INF("SGPE Chtm Config : 0x%016llx", SWIZZLE_8_BYTE(pSgpeHdr->g_sgpe_chtm_mem_cfg)); FAPI_INF("PGPE Flag Value : 0x%08x", SWIZZLE_2_BYTE(pPgpeHdr->g_pgpe_flags)); @@ -1321,12 +1329,18 @@ fapi_try_exit: * @brief updates various CPMR fields which are associated with scan rings. * @param[in] i_pChipHomer points to start of P9 HOMER. */ -void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) +fapi2::ReturnCode updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer, CONST_FAPI2_PROC& i_procTgt ) { FAPI_INF(">> updateCpmrCmeRegion"); - cpmrHeader_t* pCpmrHdr = + cpmrHeader_t* pCpmrHdr = (cpmrHeader_t*) & (i_pChipHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); - cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + uint32_t l_pstateSize = sizeof(LocalPstateParmBlock); + ROUND_OFF_32B(l_pstateSize); + uint8_t l_cmePos = 0; + auto cmeList = i_procTgt.getChildren<fapi2::TARGET_TYPE_EX>(fapi2::TARGET_STATE_FUNCTIONAL); + uint32_t l_cmeCustSize = SWIZZLE_4_BYTE(pCmeHdr->g_cme_custom_length); + uint64_t l_cpmrMagic = SWIZZLE_8_BYTE(pCpmrHdr->magic_number); //Updating CPMR Header using info from CME Header pCpmrHdr->cmeImgOffset = SWIZZLE_4_BYTE((CME_IMAGE_CPMR_OFFSET >> CME_BLK_SIZE_SHIFT)); @@ -1338,6 +1352,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) pCpmrHdr->coreScomLength = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_TOTAL); pCpmrHdr->coreMaxScomEntry = SWIZZLE_4_BYTE(MAX_CORE_SCOM_ENTRIES); + if( pCmeHdr->g_cme_common_ring_length ) { pCpmrHdr->cmeCommonRingOffset = CME_IMAGE_CPMR_OFFSET + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); @@ -1356,21 +1371,54 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) pCpmrHdr->coreSpecRingLength = pCmeHdr->g_cme_max_spec_ring_length; // already swizzled } + FAPI_INF( "Custom Len 0x%08x", l_cmeCustSize ); + for( auto cme : cmeList ) + { + uint32_t *pPstateOffset = (uint32_t *)&pCpmrHdr->quad0PstateOffset; + FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, cme, l_cmePos), + "fapiGetAttribute of ATTR_CHIP_UNIT_POS"); + + //Populating CPMR fields for CME PState field + + pPstateOffset = pPstateOffset + (l_cmePos >> 1); + + if( l_cpmrMagic >= CPMR_VDM_PER_QUAD ) + { + *pPstateOffset = SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingOffset) + + SWIZZLE_4_BYTE(pCpmrHdr->coreSpecRingLength) + ( (l_cmePos) * l_cmeCustSize ); + *pPstateOffset = SWIZZLE_4_BYTE(*pPstateOffset); + } + else + { + *pPstateOffset = 0; //ensures compatibility with quad common LPSPB + } + } + //Updating CME Image header - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + - SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); - pCmeHdr->g_cme_scom_offset = - ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); + if( l_cpmrMagic >= CPMR_VDM_PER_QUAD ) + { + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_offset) + + (l_pstateSize >> CME_BLK_SIZE_SHIFT); + } + else //ensures compatibility with quad common LPSPB + { + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length); + pCmeHdr->g_cme_scom_offset = + ((pCmeHdr->g_cme_scom_offset + CME_BLOCK_READ_LEN - 1 ) >> CME_BLK_SIZE_SHIFT); + //Adding to it instance ring length which is already a multiple of 32B + pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); + } + + pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); //Adding to it instance ring length which is already a multiple of 32B - pCmeHdr->g_cme_scom_offset += SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length); - pCmeHdr->g_cme_scom_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset); - pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME); + pCmeHdr->g_cme_scom_length = SWIZZLE_4_BYTE(CORE_SCOM_RESTORE_SIZE_PER_CME); // Timebase frequency uint32_t l_ppe_timebase_hz; calcPPETimebase(&l_ppe_timebase_hz); - pCmeHdr->g_cme_timebase_hz = SWIZZLE_4_BYTE(l_ppe_timebase_hz); + pCmeHdr->g_cme_timebase_hz = SWIZZLE_4_BYTE(l_ppe_timebase_hz); FAPI_INF("========================= CME Header Start =================================="); FAPI_INF(" HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset)); @@ -1382,6 +1430,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) FAPI_INF(" CR Size : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_length)); FAPI_INF(" CSR Offset : 0x%08X (Real offset / 32) ", SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset)); FAPI_INF(" CSR Length : 0x%08X (Real length / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) ); + FAPI_INF(" CME PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_offset)); FAPI_INF(" SCOM Offset : 0x%08X (Real offset / 32)", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_offset)); FAPI_INF(" SCOM Area Len : 0x%08X", SWIZZLE_4_BYTE(pCmeHdr->g_cme_scom_length)); FAPI_INF(" CPMR Phy Add : 0x%016lx", SWIZZLE_8_BYTE(pCmeHdr->g_cme_cpmr_PhyAddr)); @@ -1391,6 +1440,7 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) FAPI_INF("========================= CME Header End =================================="); FAPI_INF("==========================CPMR Header==========================================="); + FAPI_INF(" CPMR Ver : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cpmrVersion)); FAPI_INF(" CME HC Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgOffset)); FAPI_INF(" CME HC Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmeImgLength)); FAPI_INF(" PS Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->cmePstateOffset)); @@ -1402,9 +1452,18 @@ void updateCpmrCmeRegion( Homerlayout_t* i_pChipHomer ) FAPI_INF(" Core SCOM Offset : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomOffset)); FAPI_INF(" Core SCOM Length : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreScomLength )); FAPI_INF(" Max SCOM Entries : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->coreMaxScomEntry)); + FAPI_INF(" Quad0 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad0PstateOffset)); + FAPI_INF(" Quad1 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad1PstateOffset)); + FAPI_INF(" Quad2 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad2PstateOffset)); + FAPI_INF(" Quad3 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad3PstateOffset)); + FAPI_INF(" Quad4 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad4PstateOffset)); + FAPI_INF(" Quad5 P-State : 0x%08X", SWIZZLE_4_BYTE(pCpmrHdr->quad5PstateOffset)); + FAPI_INF("==================================CPMR Ends====================================="); FAPI_INF("<< updateCpmrCmeRegion"); +fapi_try_exit: + return fapi2::current_err; } //------------------------------------------------------------------------------ @@ -1432,8 +1491,8 @@ void updateCpmrHeaderSR( Homerlayout_t* i_pChipHomer, uint8_t i_fusedState, uint if( SMF_SELF_SIGNATURE == i_smfSign ) { - pCpmrHdr->selfRestoreVer = 0x01; - pCpmrHdr->stopApiVer = 0x01; + pCpmrHdr->selfRestoreVer = SELF_SAVE_RESTORE_VER; + pCpmrHdr->stopApiVer = STOP_API_CPU_SAVE_VER; } else { @@ -1839,6 +1898,7 @@ fapi2::ReturnCode buildCoreRestoreImage( void* const i_pImageIn, FAPI_TRY( initSmfDisabledSelfRestore( i_pChipHomer ), "Failed To Initialize Self-Restore Region In Non SMF Mode" ); } + } updateCpmrHeaderSR( i_pChipHomer, i_fusedState, i_procFuncModel.isSmfEnabled(), l_pSmfSignature ); @@ -1915,14 +1975,18 @@ fapi2::ReturnCode buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipH // Names have g_ prefix as these global variables for CME Hcode // Note: Only the *memory* addresses are updated cmeHeader_t* pImgHdr = (cmeHeader_t*) & i_pChipHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; - pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; - pImgHdr->g_cme_hcode_length = ppeSection.iv_size; + pImgHdr->g_cme_hcode_offset = CME_SRAM_HCODE_OFFSET; + pImgHdr->g_cme_hcode_length = ppeSection.iv_size; //Populating common ring offset here. So, that other scan ring related field can be updated. - pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_HOMER_OFFSET); - pImgHdr->g_cme_pstate_region_offset = pImgHdr->g_cme_hcode_offset + pImgHdr->g_cme_hcode_length; pImgHdr->g_cme_pstate_region_length = 0; - pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_pstate_region_offset + pImgHdr->g_cme_pstate_region_length; + pImgHdr->g_cme_pstate_region_offset = 0; + pImgHdr->g_cme_cpmr_PhyAddr = (i_cpmrPhyAdd | CPMR_HOMER_OFFSET); + + + pImgHdr->g_cme_common_ring_offset = pImgHdr->g_cme_hcode_offset + + pImgHdr->g_cme_hcode_length; + pImgHdr->g_cme_common_ring_length = 0; pImgHdr->g_cme_scom_offset = 0; pImgHdr->g_cme_scom_length = CORE_SCOM_RESTORE_SIZE_PER_CME; @@ -1931,7 +1995,6 @@ fapi2::ReturnCode buildCmeImage( void* const i_pImageIn, Homerlayout_t* i_pChipH //Let us handle the endianess at the end pImgHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_pstate_region_offset); - pImgHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_common_ring_offset); pImgHdr->g_cme_hcode_offset = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_offset); pImgHdr->g_cme_hcode_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_hcode_length); pImgHdr->g_cme_scom_length = SWIZZLE_4_BYTE(pImgHdr->g_cme_scom_length); @@ -2419,6 +2482,7 @@ fapi2::ReturnCode updatePgpeHeader( void* const i_pHomer, CONST_FAPI2_PROC& i_pr pPgpeHdr->g_pgpe_beacon_addr = 0; pPgpeHdr->g_quad_status_addr = 0; pPgpeHdr->g_pgpe_wof_state_address = 0; + pPgpeHdr->g_pgpe_wof_values_address = 0; pPgpeHdr->g_pgpe_req_active_quad_address = 0; pPgpeHdr->g_wof_table_addr = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_wof_table_offset); pPgpeHdr->g_wof_table_length = SWIZZLE_4_BYTE(pPpmrHdr->g_ppmr_wof_table_length); @@ -2526,6 +2590,46 @@ fapi_try_exit: //--------------------------------------------------------------------------- +fapi2::ReturnCode buildCmePstateInfo( Homerlayout_t * i_pHomer, CONST_FAPI2_PROC& i_procTgt, + ImageType_t i_imgType, PstateSuperStructure * i_pSuperStruct ) +{ + FAPI_DBG(">> buildCmePstateInfo"); + uint8_t l_cmePos = 0; + cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + auto cmeList = i_procTgt.getChildren<fapi2::TARGET_TYPE_EX>(fapi2::TARGET_STATE_FUNCTIONAL); + uint8_t * l_pCmePstate = NULL; + uint32_t l_pstateSize = sizeof(LocalPstateParmBlock); + ROUND_OFF_32B(l_pstateSize); + uint32_t l_ringSize = (SWIZZLE_4_BYTE(pCmeHdr->g_cme_max_spec_ring_length) << CME_BLK_SIZE_SHIFT ); + uint32_t l_cmeCustSize = l_ringSize + l_pstateSize; + + uint32_t l_cmeCurIndex = ( SWIZZLE_4_BYTE(pCmeHdr->g_cme_core_spec_ring_offset) << CME_BLK_SIZE_SHIFT ); + l_cmeCurIndex += l_ringSize; + + for( auto cme : cmeList ) + { + FAPI_TRY(FAPI_ATTR_GET( fapi2::ATTR_CHIP_UNIT_POS, cme, l_cmePos), + "fapiGetAttribute of ATTR_CHIP_UNIT_POS"); + //copying CME specific LPSPB info into HOMER + l_pCmePstate = + (uint8_t *) &i_pHomer->cpmrRegion.cmeSramRegion[ (l_cmeCustSize * l_cmePos ) + l_cmeCurIndex ]; + memcpy( l_pCmePstate, &i_pSuperStruct->localppb[(l_cmePos >> 1)], sizeof(LocalPstateParmBlock) ); + + //Populating CPMR fields for CME PState field + } + + pCmeHdr->g_cme_pstate_offset = ( l_cmeCurIndex >> CME_BLK_SIZE_SHIFT ); + pCmeHdr->g_cme_pstate_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_offset); + pCmeHdr->g_cme_custom_length = SWIZZLE_4_BYTE(l_cmeCustSize >> CME_BLK_SIZE_SHIFT); + + FAPI_INF( "CME PS Offset 0x%08x x32= 0x%08x", SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_offset), l_cmeCurIndex ); + +fapi_try_exit: + FAPI_DBG("<< buildCmePstateInfo"); + return fapi2::current_err; +} +//--------------------------------------------------------------------------- + /** * @brief updates the PState parameter block info in CPMR and PPMR region * @param[in] i_pHomer points to start of of chip's HOMER @@ -2542,32 +2646,31 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i { FAPI_INF(">> buildParameterBlock"); - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + PstateSuperStructure stateSupStruct; + + FAPI_IMP("Size of sup-struct 0x%08x", sizeof(PstateSuperStructure)); + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + uint32_t pgpeRunningOffset = 0; + uint32_t sizePStateBlock = 0; + uint32_t wofTableSize = i_sizeBuf1; + uint32_t localPStateBlock = 0; + uint32_t sizeAligned = 0; + fapi2::ReturnCode retCode; if( i_imgType.pgpePstateParmBlockBuild ) { - - fapi2::ReturnCode retCode; Homerlayout_t* pHomerLayout = (Homerlayout_t*)i_pHomer; PPMRLayout_t* pPpmr = (PPMRLayout_t*) &pHomerLayout->ppmrRegion; cmeHeader_t* pCmeHdr = (cmeHeader_t*) &pHomerLayout->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (pHomerLayout->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); + uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); + fapi2::ATTR_WOF_ENABLED_Type l_wof_enabled; uint32_t ppmrRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_offset) + SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - FAPI_DBG("Hcode ppmrRunningOffset 0x%08x", ppmrRunningOffset ); - - uint32_t pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); - - FAPI_DBG(" PGPE Hcode End 0x%08x", pgpeRunningOffset ); - - uint32_t sizeAligned = 0; - uint32_t sizePStateBlock = 0; - uint32_t wofTableSize = i_sizeBuf1; - - // Allocate struct onto stack - PstateSuperStructure stateSupStruct; // Clearing i_pBuf1 memset(i_pBuf1,0x00,i_sizeBuf1); @@ -2580,39 +2683,45 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i //Check if WOF Table is copied properly even if WOF is disabled. //As this is memory range check, we don't want memory corruption //issues to go unnoticed as this should not EVER happen. + FAPI_ASSERT( ( wofTableSize <= OCC_WOF_TABLES_SIZE ), fapi2::PARAM_WOF_TABLE_SIZE_ERR() .set_ACTUAL_WOF_TABLE_SIZE(wofTableSize) .set_MAX_SIZE_ALLOCATED(OCC_WOF_TABLES_SIZE), "Size of WOF Table Exceeds Max Size Allowed" ); - //-------------------------- Local P-State Parameter Block ------------------------------ - uint32_t localPspbStartIndex = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); - uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; - - sizePStateBlock = sizeof(LocalPstateParmBlock); - - //Note: Not checking size here. Once entire CME Image layout is complete, there is a - //size check at last. WE are safe as long as everthing put together doesn't exceed - //maximum SRAM image size allowed(32KB). No need to check size of Local P-State - //parameter block individually. - - FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); - memcpy( pLocalPState, &(stateSupStruct.localppb), sizePStateBlock ); - - ALIGN_DBWORD( sizeAligned, sizePStateBlock ) - uint32_t localPStateBlock = sizeAligned; - FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); - - pCmeHdr->g_cme_pstate_region_length = localPStateBlock; - pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset) + localPStateBlock; + FAPI_INF( "Magic Word 0x%016lx Copy Start Index 0x%08x", SWIZZLE_8_BYTE(pCpmrHdr->magic_number), localPspbStartIndex ); + if( SWIZZLE_8_BYTE(pCpmrHdr->magic_number) >= CPMR_VDM_PER_QUAD ) + { + FAPI_TRY( buildCmePstateInfo( pHomerLayout, i_procTgt, i_imgType, &stateSupStruct ), + "Failed to copy quad P-State info in CME SRAM image region" ); + } + else + { + uint8_t* pLocalPState = &pHomerLayout->cpmrRegion.cmeSramRegion[localPspbStartIndex]; + sizePStateBlock = sizeof(LocalPstateParmBlock); + //Note: Not checking size here. Once entire CME Image layout is complete, there is a + //size check at last. WE are safe as long as everthing put together doesn't exceed + //maximum SRAM image size allowed(32KB). No need to check size of Local P-State + //parameter block individually. + + FAPI_DBG("Copying Local P-State Parameter Block into CPMR" ); + memcpy( pLocalPState, &(stateSupStruct.localppb), sizePStateBlock ); + ALIGN_DBWORD( sizeAligned, sizePStateBlock ) + localPStateBlock = sizeAligned; + FAPI_DBG("LPSPB Actual size 0x%08x After Alignment 0x%08x", sizePStateBlock, sizeAligned ); + pCmeHdr->g_cme_pstate_region_length = localPStateBlock; + pCmeHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset) + + SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_length); + pCmeHdr->g_cme_common_ring_offset = pCmeHdr->g_cme_pstate_region_offset + localPStateBlock; + } //-------------------------- Local P-State Parameter Block Ends -------------------------- //-------------------------- Global P-State Parameter Block ------------------------------ - FAPI_DBG("Copying Global P-State Parameter Block" ); + pgpeRunningOffset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_hcode_length); sizePStateBlock = sizeof(GlobalPstateParmBlock); FAPI_ASSERT( ( sizePStateBlock <= PGPE_GLOBAL_PSTATE_PARAM_BLOCK_SIZE), @@ -2622,7 +2731,7 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i .set_ACTUAL_SIZE( sizePStateBlock ), "Size of Global Parameter Block Exceeds Max Size Allowed" ); - FAPI_DBG("GPPBB pgpeRunningOffset 0x%08x", pgpeRunningOffset ); + FAPI_DBG("Copying Global P-State Parameter Block" ); memcpy( &pPpmr->pgpeSramImage[pgpeRunningOffset], &(stateSupStruct.globalppb), sizePStateBlock ); @@ -2666,10 +2775,18 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i sizePStateBlock ); //-------------------------- OCC P-State Parameter Block Ends ------------------------------ + //Not relevant any longer. Kept for legacy reason. Now we have field per quad. - io_ppmrHdr.g_ppmr_lppb_offset = CPMR_HOMER_OFFSET + CME_IMAGE_CPMR_OFFSET + localPspbStartIndex; - io_ppmrHdr.g_ppmr_lppb_length = localPStateBlock; - + if( SWIZZLE_8_BYTE(pCpmrHdr->magic_number) >= CPMR_VDM_PER_QUAD ) + { + io_ppmrHdr.g_ppmr_lppb_offset = 0; + io_ppmrHdr.g_ppmr_lppb_length = 0; + } + else + { + io_ppmrHdr.g_ppmr_lppb_offset = CPMR_HOMER_OFFSET + CME_IMAGE_CPMR_OFFSET + localPspbStartIndex; + io_ppmrHdr.g_ppmr_lppb_length = localPStateBlock; + } //------------------------------ OCC P-State Table Allocation ------------------------------ // The PPMR offset is from the begining --- which is the ppmrHeader @@ -2683,6 +2800,7 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i io_ppmrHdr.g_ppmr_wof_table_length = OCC_WOF_TABLES_SIZE; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_WOF_ENABLED, i_procTgt, l_wof_enabled)); + if (l_wof_enabled) { memcpy( &pPpmr->wofTableSize, i_pBuf1, wofTableSize ); @@ -2697,10 +2815,11 @@ fapi2::ReturnCode buildParameterBlock( void* const i_pHomer, CONST_FAPI2_PROC& i FAPI_DBG("OPPB pgpeRunningOffset 0x%08x io_ppmrHdr.g_ppmr_pgpe_sram_img_size 0x%08x", pgpeRunningOffset, io_ppmrHdr.g_ppmr_pgpe_sram_img_size ); - //Finally let us handle endianess + //let us handle endianess //CME Header pCmeHdr->g_cme_pstate_region_length = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_length); pCmeHdr->g_cme_common_ring_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_common_ring_offset); + pCmeHdr->g_cme_pstate_region_offset = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset); //PPMR Header io_ppmrHdr.g_ppmr_gppb_offset = SWIZZLE_4_BYTE(io_ppmrHdr.g_ppmr_gppb_offset); @@ -2860,13 +2979,22 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer, { FAPI_DBG( ">> layoutInstRingsForCme"); uint32_t rc = IMG_BUILD_SUCCESS; - fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + fapi2::current_err = fapi2::FAPI2_RC_SUCCESS; + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); // Let us find out ring-pair which is biggest in list of 12 ring pairs - uint32_t maxCoreSpecRingLength = 0; - uint32_t ringLength = 0; - uint32_t tempSize = 0; - uint32_t tempRepairLength = 0; - uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + uint32_t maxCoreSpecRingLength = 0; + uint32_t ringLength = 0; + uint32_t tempSize = 0; + uint32_t tempRepairLength = 0; + uint32_t ringStartToHdrOffset = ( TOR_VER_ONE == tor_version() ) ? RING_START_TO_RS4_OFFSET : 0; + uint32_t cmePstateSize = 0; + + if( SWIZZLE_8_BYTE(pCpmrHdr->magic_number) >= CPMR_VDM_PER_QUAD ) + { + cmePstateSize = sizeof(LocalPstateParmBlock); + ROUND_OFF_32B(cmePstateSize); + } if( i_imgType.cmeHcodeBuild ) { @@ -2926,7 +3054,7 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer, ROUND_OFF_32B(maxCoreSpecRingLength); } - FAPI_DBG("Max Instance Spec Ring 0x%08X", maxCoreSpecRingLength); + FAPI_DBG("Max Instance Spec Ring 0x%08X Pstate Size Considered 0x%08x", maxCoreSpecRingLength, cmePstateSize ); // Let us copy the rings now. uint8_t* pRingStart = NULL; @@ -2935,7 +3063,8 @@ fapi2::ReturnCode layoutInstRingsForCme( Homerlayout_t* i_pHomer, for( uint32_t exId = 0; exId < MAX_CMES_PER_CHIP; exId++ ) { - pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + ( exId * maxCoreSpecRingLength ) ]; + pRingStart = (uint8_t*)&i_pHomer->cpmrRegion.cmeSramRegion[io_ringLength + + ( exId * ( maxCoreSpecRingLength + cmePstateSize ) ) ]; pRingPayload = pRingStart + sizeof(CoreSpecRingList_t); pScanRingIndex = (uint16_t*)pRingStart; @@ -3151,6 +3280,8 @@ fapi2::ReturnCode layoutRingsForCME( Homerlayout_t* i_pHomer, uint32_t ringLength = 0; uint32_t tempLength = 0; RingVariant_t l_ringVariant = RV_BASE; + cpmrHeader_t* pCpmrHdr = + (cpmrHeader_t*) & (i_pHomer->cpmrRegion.selfRestoreRegion.CPMR_SR.elements.CPMRHeader); cmeHeader_t* pCmeHdr = (cmeHeader_t*) &i_pHomer->cpmrRegion.cmeSramRegion[CME_INT_VECTOR_SIZE]; RingBucket cmeRings( PLAT_CME, (uint8_t*)&i_pHomer->cpmrRegion, @@ -3179,10 +3310,16 @@ fapi2::ReturnCode layoutRingsForCME( Homerlayout_t* i_pHomer, break; } - ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_pstate_region_offset) + SWIZZLE_4_BYTE( - pCmeHdr->g_cme_pstate_region_length); + ringLength = SWIZZLE_4_BYTE(pCmeHdr->g_cme_hcode_offset) + SWIZZLE_4_BYTE( + pCmeHdr->g_cme_hcode_length); + + if( SWIZZLE_8_BYTE(pCpmrHdr->magic_number) < CPMR_VDM_PER_QUAD ) + { + ringLength += sizeof(LocalPstateParmBlock); + } + //save the length where hcode ends - tempLength = ringLength; + tempLength = ringLength; FAPI_TRY( layoutCmnRingsForCme( i_pHomer, i_chipState, i_ringData, i_debugMode, l_ringVariant, @@ -3383,7 +3520,6 @@ fapi2::ReturnCode layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, RingBucket& io_sgpeRings ) { FAPI_INF(">> layoutCmnRingsForSgpe"); - uint32_t rc = IMG_BUILD_SUCCESS; uint32_t sgpeHcodeSize = SWIZZLE_4_BYTE(io_qpmrHdr.sgpeImgLength); uint8_t* pCmnRingPayload = &i_pHomer->qpmrRegion.sgpeRegion.sgpeSramImage[sgpeHcodeSize + @@ -3462,7 +3598,7 @@ fapi2::ReturnCode layoutCmnRingsForSgpe( Homerlayout_t* i_pHomer, .set_RING_ID( torRingId ) .set_EC_LEVEL( i_chipState.getChipLevel() ) .set_CHIP_TYPE( i_chipState.getChipName() ), - "Failed To Complete Quad Common Ring Layout" ); + "Failed To Complete Quad Common Ring Layout 0x%08x ring id 0x%08x variant %d", rc, torRingId, l_ringVariant ); memcpy( pCmnRingPayload, i_ringData.iv_pWorkBuf1, tempBufSize); io_sgpeRings.setRingOffset( pCmnRingPayload, io_sgpeRings.getCommonRingId( ringIndex ) ); @@ -3663,12 +3799,10 @@ fapi2::ReturnCode layoutRingsForSGPE( Homerlayout_t* i_pHomer, } //Manage the Quad Common rings in HOMER - FAPI_TRY( layoutCmnRingsForSgpe( i_pHomer, i_chipState, i_ringData, i_debugMode, l_ringVariant, io_qpmrHdr, i_imgType, sgpeRings), "Quad Common Ring Layout Failed"); - //Manage the Quad Override rings in HOMER FAPI_TRY( layoutSgpeScanOverride( i_pHomer, i_pOverride, i_chipState, @@ -4822,12 +4956,10 @@ fapi2::ReturnCode populateUnsecureHomerAddress( CONST_FAPI2_PROC& i_procTgt, Hom pCmeHdr->g_cme_unsec_cpmr_PhyAddr = pCmeHdr->g_cme_cpmr_PhyAddr; goto fapi_try_exit; } - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_UNSECURE_HOMER_ADDRESS, i_procTgt, l_unsecureHomerAdd), "Error from FAPI_ATTR_GET for attribute ATTR_UNSECURE_HOMER_ADDRESS"); - FAPI_INF( "Atrribute ATTR_UNSECURE_HOMER_ADDRESS 0x%016lx", l_unsecureHomerAdd ); if( l_unsecureHomerAdd & 0x1fffff ) @@ -4902,7 +5034,6 @@ fapi2::ReturnCode initUnsecureHomer( void* const i_pBuf2, const uint32_t i_s } //-------------------------------------------------------------------------------------------------------- - fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, void* const i_pImageIn, void* i_pHomerImage, @@ -5018,10 +5149,6 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, FAPI_TRY( buildPgpeAux( pChipHomer ), "Failed to build auxiliary function in PPMR" ); - //Update P State parameter block info in HOMER - FAPI_TRY( buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType, i_pBuf1, i_sizeBuf1 ), - "Failed to Add Parameter Block" ); - FAPI_INF("PGPE built"); //Let us add Scan Rings to the image. FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYSTEM_RING_DBG_MODE, @@ -5082,8 +5209,13 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, FAPI_TRY( populateUnsecureHomerAddress( i_procTgt, pChipHomer, l_chipFuncModel.isSmfEnabled() ), "Failed To Populate Unsecure HOMER Region with sc2 instruction" ); + //Update P State parameter block info in HOMER + FAPI_TRY( buildParameterBlock( pChipHomer, i_procTgt, l_ppmrHdr, i_imgType, i_pBuf1, i_sizeBuf1 ), + "Failed to Add Parameter Block" ); + //Update CPMR Header with Scan Ring details - updateCpmrCmeRegion( pChipHomer ); + FAPI_TRY( updateCpmrCmeRegion( pChipHomer, i_procTgt ), + "Failed to update CPMR CME region" ); //Update QPMR Header area in HOMER @@ -5139,7 +5271,6 @@ fapi2::ReturnCode p9_hcode_image_build( CONST_FAPI2_PROC& i_procTgt, FAPI_TRY( initUnsecureHomer( i_pBuf2, i_sizeBuf2 ), "Failed to initialize unsecure HOMER" ); - fapi_try_exit: FAPI_IMP("<< p9_hcode_image_build" ); return fapi2::current_err; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C index 77cd232e8..db22f670e 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_corequad_init.C @@ -684,14 +684,14 @@ fapi2::ReturnCode pm_disable_resclk( uint16_t l_quad_table_value; uint8_t l_caccr_bit_13_14_value = 0; - uint32_t attr_freq_proc_refclock_khz = 0; + uint32_t attr_freq_dpll_refclock_khz = 0; uint32_t attr_proc_dpll_divider = 8; const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; auto l_exChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EX> (fapi2::TARGET_STATE_FUNCTIONAL); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_proc_refclock_khz) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_dpll_refclock_khz) , "Attribute read failed"); //Read the frequency of the quad l_address = EQ_QPPM_DPLL_FREQ; @@ -701,10 +701,10 @@ fapi2::ReturnCode pm_disable_resclk( l_data64.extractToRight<EQ_QPPM_DPLL_FREQ_FMULT, EQ_QPPM_DPLL_FREQ_FMULT_LEN>(l_fmult); - FAPI_INF("EQ_QPPM_DPLL_FREQ_FMULT %04x, attr_freq_proc_refclock_khz %08x, attr_proc_dpll_divider %x", - l_fmult, attr_freq_proc_refclock_khz, attr_proc_dpll_divider); + FAPI_INF("EQ_QPPM_DPLL_FREQ_FMULT %04x, attr_freq_dpll_refclock_khz %08x, attr_proc_dpll_divider %x", + l_fmult, attr_freq_dpll_refclock_khz, attr_proc_dpll_divider); - l_fmult = ((l_fmult * attr_freq_proc_refclock_khz ) / attr_proc_dpll_divider) / 1000; + l_fmult = ((l_fmult * attr_freq_dpll_refclock_khz ) / attr_proc_dpll_divider) / 1000; FAPI_INF("EQ_QPPM_DPLL_FREQ FMULT value %08x", l_fmult); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.C index 9a13c51a2..7e31dbf78 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,6 +44,34 @@ #include <p9_pm_get_poundw_bucket.H> #include <attribute_ids.H> +#ifdef __VDM_TEST + +uint8_t dummy_attr[] = +{ + 0x30, 0x05, + 0x2F, 0x6A, 0x04, 0x68, 0x05, 0xC0, 0x23, 0x12, 0x41, 0x42, + 0x42, 0x42, 0x42, 0x43, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, + 0x02, 0x53, 0xA1, 0x04, 0x6A, 0x00, 0x00, + + 0x1B, 0xF0, 0x07, 0x95, 0x07, 0x40, 0x23, 0x12, 0x23, 0x24, + 0x24, 0x24, 0x24, 0x25, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, + 0x02, 0x53, 0xA1, 0x04, 0x6A, 0x00, 0x00, + + 0x40, 0x42, 0x04, 0x2C, 0x04, 0xD0, 0x23, 0x12, 0x5A, 0x5A, + 0x5A, 0x5B, 0x5B, 0x5B, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, + 0x02, 0x53, 0xA1, 0x04, 0x6A, 0x00, 0x00, + + 0x60, 0x85, 0x0E, 0xD1, 0x0C, 0xF0, 0x23, 0x12, 0x80, 0x80, + 0x80, 0x80, 0x81, 0x81, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, + 0x02, 0x53, 0xA1, 0x04, 0x6A, 0x00, 0x00, + + 0x9C, 0x40, 0x14, 0xEE, 0x09, 0x98, 0x4E, 0x20, 0x27, 0x10, + 0x01, 0x02, 0x03, 0xFF, 0x03, 0x7F, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +#endif + // See doxygen in header file fapi2::ReturnCode p9_pm_get_poundw_bucket( const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target, @@ -59,7 +87,15 @@ fapi2::ReturnCode p9_pm_get_poundw_bucket( i_target, l_bucketAttr)); - memcpy(&o_data, l_bucketAttr, sizeof(o_data)); + memcpy(&o_data, l_bucketAttr, sizeof(o_data)); + +#ifdef __VDM_TEST + + memcpy( &o_data, dummy_attr, sizeof(o_data) ); + +#endif + + FAPI_INF( "COPYING from ATTR_POUNDW_BUCKET_DATA" ); fapi_try_exit: FAPI_DBG("Exiting p9_pm_get_poundw_bucket ...."); diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.H index 47f72c091..1ca6b36f9 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -59,7 +59,7 @@ typedef struct __attribute__((__packed__)) vdmData // bucket Id uint8_t bucketId; // VDM data - uint8_t vdmData[PW_VER_2_VDMDATA_SIZE]; + uint8_t vdmData[PW_VER_30_VDMDATA_SIZE]; } vdmData_t; } diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.C index 40a2b03de..331c4c22f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -51,7 +51,7 @@ fapi2::ReturnCode p9_pm_get_poundw_bucket_attr( uint8_t* l_fullVpdData = nullptr; uint32_t l_vpdSize = 0; uint8_t l_bucketId; - uint8_t l_bucketSize = 0; + uint8_t l_bucketSize = PW_VER_30_VDMDATA_SIZE; //To read MVPD we will need the proc parent of the inputted EQ target fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_procParent = @@ -116,6 +116,10 @@ fapi2::ReturnCode p9_pm_get_poundw_bucket_attr( //Set the size of the bucket l_bucketSize = POUNDW_BUCKETID_SIZE + PW_VER_2_VDMDATA_SIZE; } + else if ( ( *l_fullVpdData ) >= POUNDW_VERSION_30 ) + { + l_bucketSize = POUNDW_BUCKETID_SIZE + PW_VER_30_VDMDATA_SIZE; + } else { FAPI_ASSERT( false, diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.H b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.H index 6e425ba3b..edf2eb011 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_get_poundw_bucket_attr.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2017 */ +/* Contributors Listed Below - COPYRIGHT 2017,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,13 +44,15 @@ enum poundwBucketParms { - POUNDW_VERSION_1 = 0x01, - POUNDW_VERSION_2 = 0x02, - POUNDW_VERSION_F = 0x0F, - POUNDW_VERSION_SIZE = 0x01, // version is uint8_t - POUNDW_BUCKETID_SIZE = 0x01, // bucket ID is uint8_t - PW_VER_1_VDMDATA_SIZE = 0x28, - PW_VER_2_VDMDATA_SIZE = 0x3C, + POUNDW_VERSION_1 = 0x01, + POUNDW_VERSION_2 = 0x02, + POUNDW_VERSION_F = 0x0F, + POUNDW_VERSION_30 = 0x30, + POUNDW_VERSION_SIZE = 0x01, // version is uint8_t + POUNDW_BUCKETID_SIZE = 0x01, // bucket ID is uint8_t + PW_VER_1_VDMDATA_SIZE = 0x28, + PW_VER_2_VDMDATA_SIZE = 0x3C, + PW_VER_30_VDMDATA_SIZE = 0x87, }; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C index 8483b9308..01e27f604 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_pstate_gpe_init.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -263,10 +263,10 @@ fapi2::ReturnCode pstate_gpe_init( auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ> (fapi2::TARGET_STATE_FUNCTIONAL); fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ_Type l_attr_safe_mode_freq_mhz; - fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ_Type l_ref_clock_freq_khz; + fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ_Type l_ref_clock_freq_khz; fapi2::ATTR_PROC_DPLL_DIVIDER_Type l_proc_dpll_divider; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ, i_target, l_attr_safe_mode_freq_mhz)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, l_ref_clock_freq_khz)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, l_ref_clock_freq_khz)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_DPLL_DIVIDER, i_target, l_proc_dpll_divider)); // Convert frequency value to a format that needs to be written to the // register diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C index f3b28a9b4..04c14d2a1 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pm_reset.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -500,7 +500,7 @@ p9_pm_reset_psafe_update(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ta fapi2::ATTR_VDD_AVSBUS_BUSNUM_Type l_vdd_bus_num; fapi2::ATTR_VDD_AVSBUS_RAIL_Type l_vdd_bus_rail; fapi2::ATTR_VDD_BOOT_VOLTAGE_Type l_vdd_voltage_mv; - fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ_Type l_freq_proc_refclock_khz; + fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ_Type l_freq_proc_refclock_khz; fapi2::ATTR_PROC_DPLL_DIVIDER_Type l_proc_dpll_divider; fapi2::ATTR_SAFE_MODE_NOVDM_UPLIFT_MV_Type l_uplift_mv; fapi2::ATTR_EXTERNAL_VRM_STEPSIZE_Type l_ext_vrm_step_size_mv; @@ -511,7 +511,7 @@ p9_pm_reset_psafe_update(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ta FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_AVSBUS_RAIL, i_target, l_vdd_bus_rail)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_BOOT_VOLTAGE, i_target, l_vdd_voltage_mv)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_DPLL_DIVIDER, i_target, l_proc_dpll_divider)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, l_freq_proc_refclock_khz)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, l_freq_proc_refclock_khz)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_NOVDM_UPLIFT_MV, i_target, l_uplift_mv)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_EXTERNAL_VRM_STEPSIZE, FAPI_SYSTEM, l_ext_vrm_step_size_mv)); l_attr_safe_mode_mv += l_uplift_mv; diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C index cedb6d1eb..413c340b0 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.C @@ -198,19 +198,19 @@ const uint8_t g_sysvfrtData[] = VDN_PERCENT_KEY, // vdn percentage(1B), 0x05, // vdd percentage(1B) QID_KEY, // quad id(1B) - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA5, 0xA5, - 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA5, 0xA5, + 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, - 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA5, 0xA5, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, + 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA5, 0xA5, 0xA1, 0x9D, 0x9A }; @@ -223,6 +223,8 @@ char const* region_names[] = { "REGION_POWERSAVE_NOMINAL", }; char const* prt_region_names[] = VPD_OP_SLOPES_REGION_ORDER_STR; +const uint32_t LEGACY_RESISTANCE_ENTRY_SIZE = 10; + //the value in this table are in Index format uint8_t g_GreyCodeIndexMapping [] = { @@ -254,7 +256,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ uint8_t* o_buf, uint32_t& io_size) { - FAPI_DBG("> p9_pstate_parameter_block"); + FAPI_IMP("> p9_pstate_parameter_block"); const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; fapi2::ReturnCode l_rc = 0; io_size = 0; @@ -278,8 +280,8 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ memset (&l_globalppb, 0, sizeof(GlobalPstateParmBlock)); // CME content - LocalPstateParmBlock l_localppb; - memset (&l_localppb, 0, sizeof(LocalPstateParmBlock)); + LocalPstateParmBlock l_localppb[MAX_QUADS_PER_CHIP]; + memset ( &l_localppb, 0, ( MAX_QUADS_PER_CHIP * sizeof(LocalPstateParmBlock) ) ); // OCC content OCCPstateParmBlock l_occppb; @@ -333,7 +335,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ // ---------------- // Initialize VDM data // ---------------- - l_pmPPB.vdm_init(); + FAPI_TRY(l_pmPPB.vdm_init()); // ---------------- // get Resonant clocking attributes @@ -348,7 +350,7 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ // ---------------- // Initialize LPPB structure // ---------------- - FAPI_TRY(l_pmPPB.lppb_init(&l_localppb)); + FAPI_TRY(l_pmPPB.lppb_init(&l_localppb[0])); // ---------------- // WOF initialization @@ -371,25 +373,26 @@ p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_ // Put out the Parmater Blocks to the trace - gppb_print(&(l_globalppb)); + FAPI_TRY(gppb_print(&(l_globalppb), i_target)); oppb_print(&(l_occppb)); // Populate Global,local and OCC parameter blocks into Pstate super structure - (*io_pss).globalppb = l_globalppb; - (*io_pss).localppb = l_localppb; - (*io_pss).occppb = l_occppb; + (*io_pss).globalppb = l_globalppb; + (*io_pss).occppb = l_occppb; + + memcpy( &((*io_pss).localppb), &l_localppb, ( MAX_QUADS_PER_CHIP * sizeof(LocalPstateParmBlock) ) ); } while(0); fapi_try_exit: - FAPI_DBG("< p9_pstate_parameter_block"); + FAPI_IMP("< p9_pstate_parameter_block"); return fapi2::current_err; } // END OF PSTATE PARAMETER BLOCK function /////////////////////////////////////////////////////////// -//////// freq2pState +//////// freq2pState /////////////////////////////////////////////////////////// int PlatPmPPB::freq2pState (const uint32_t i_freq_khz, Pstate* o_pstate, @@ -477,22 +480,22 @@ fapi2::ReturnCode PlatPmPPB::set_global_feature_attributes() (fapi2::ATTR_WOV_OVERV_ENABLED_Type)fapi2::ENUM_ATTR_WOV_OVERV_ENABLED_FALSE; - iv_wov_underv_enabled = false; - iv_wov_overv_enabled = false; //Check whether to enable WOV Undervolting. WOV can //only be enabled if VDMs are enabled - if (is_wov_underv_enabled() && - is_vdm_enabled()) + if (!is_wov_underv_enabled() || + !is_vdm_enabled()) { - iv_wov_underv_enabled = true; + FAPI_DBG("UNDERV_DISABLED") + iv_wov_underv_enabled = false; } //Check whether to enable WOV Overvolting. WOV can //only be enabled if VDMs are enabled - if (is_wov_overv_enabled() && - is_vdm_enabled()) + if (!is_wov_overv_enabled() || + !is_vdm_enabled()) { - iv_wov_overv_enabled = true; + FAPI_DBG("OVERV_DISABLED") + iv_wov_overv_enabled = false; } if (iv_pstates_enabled) @@ -546,7 +549,7 @@ fapi_try_exit: } //end of set_global_feature_attributes /////////////////////////////////////////////////////////// -//////// oppb_init +//////// oppb_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::oppb_init( OCCPstateParmBlock *i_occppb ) @@ -620,7 +623,7 @@ fapi2::ReturnCode PlatPmPPB::oppb_init( revle16(iv_poundW_data.poundw[TURBO].ivdd_tdp_ac_current_10ma); i_occppb->lac_tdp_vdd_nominal_10ma = revle16(iv_poundW_data.poundw[NOMINAL].ivdd_tdp_ac_current_10ma); - FAPI_INF("l_occppb.lac_tdp_vdd_turbo_10ma 0x%x (%d)", + FAPI_INF("l_occppb.lac_tdp_vdd_turbo_10ma 0x%x (%d)", i_occppb->lac_tdp_vdd_turbo_10ma, i_occppb->lac_tdp_vdd_turbo_10ma); FAPI_INF("l_occppb.lac_tdp_vdd_nominal_10ma 0x%x (%d)", i_occppb->lac_tdp_vdd_nominal_10ma, i_occppb->lac_tdp_vdd_nominal_10ma); @@ -676,7 +679,7 @@ fapi2::ReturnCode PlatPmPPB::oppb_init( /////////////////////////////////////////////////////////// -//////// lppb_init +//////// lppb_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::lppb_init( LocalPstateParmBlock *i_localppb) @@ -684,79 +687,91 @@ fapi2::ReturnCode PlatPmPPB::lppb_init( FAPI_INF(">>>>>>>> lppb_init"); do { - // ----------------------------------------------- - // Local parameter block - // ----------------------------------------------- - i_localppb->magic = revle64(LOCAL_PARMSBLOCK_MAGIC); + uint8_t l_eqPos = 0; + auto l_eqChiplets = iv_procChip.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); + LocalPstateParmBlock *l_pLocalPspbTemp = NULL; - // VpdBias External and Internal Biases for Global and Local parameter - // block - for (uint8_t i = 0; i < NUM_OP_POINTS; i++) + for( auto eq : l_eqChiplets ) { - i_localppb->ext_biases[i] = iv_bias[i]; - i_localppb->int_biases[i] = iv_bias[i]; - } + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, eq, l_eqPos )); + l_pLocalPspbTemp = i_localppb + l_eqPos; - //load vpd operating points - for (uint32_t i = 0; i < NUM_OP_POINTS; i++) - { - i_localppb->operating_points[i].frequency_mhz = revle32(iv_biased_vpd_pts[i].frequency_mhz); - i_localppb->operating_points[i].vdd_mv = revle32(iv_biased_vpd_pts[i].vdd_mv); - i_localppb->operating_points[i].idd_100ma = revle32(iv_biased_vpd_pts[i].idd_100ma); - i_localppb->operating_points[i].vcs_mv = revle32(iv_biased_vpd_pts[i].vcs_mv); - i_localppb->operating_points[i].ics_100ma = revle32(iv_biased_vpd_pts[i].ics_100ma); - i_localppb->operating_points[i].pstate = iv_biased_vpd_pts[i].pstate; - } + // ----------------------------------------------- + // Local parameter block + // ----------------------------------------------- + l_pLocalPspbTemp->magic = revle64(LOCAL_PARMSBLOCK_MAGIC); + + // VpdBias External and Internal Biases for Global and Local parameter + // block + for (uint8_t i = 0; i < NUM_OP_POINTS; i++) + { + l_pLocalPspbTemp->ext_biases[i] = iv_bias[i]; + l_pLocalPspbTemp->int_biases[i] = iv_bias[i]; + } - i_localppb->vdd_sysparm = iv_vdd_sysparam; + //load vpd operating points + for (uint32_t i = 0; i < NUM_OP_POINTS; i++) + { + l_pLocalPspbTemp->operating_points[i].frequency_mhz = revle32(iv_biased_vpd_pts[i].frequency_mhz); + l_pLocalPspbTemp->operating_points[i].vdd_mv = revle32(iv_biased_vpd_pts[i].vdd_mv); + l_pLocalPspbTemp->operating_points[i].idd_100ma = revle32(iv_biased_vpd_pts[i].idd_100ma); + l_pLocalPspbTemp->operating_points[i].vcs_mv = revle32(iv_biased_vpd_pts[i].vcs_mv); + l_pLocalPspbTemp->operating_points[i].ics_100ma = revle32(iv_biased_vpd_pts[i].ics_100ma); + l_pLocalPspbTemp->operating_points[i].pstate = iv_biased_vpd_pts[i].pstate; + } - // IvrmParmBlock - i_localppb->ivrm = iv_ivrmpb; + l_pLocalPspbTemp->vdd_sysparm = iv_vdd_sysparam; - // VDMParmBlock - memset (&(i_localppb->vdm),0,sizeof(i_localppb->vdm)); + // IvrmParmBlock + l_pLocalPspbTemp->ivrm = iv_ivrmpb; - i_localppb->dpll_pstate0_value = - ((iv_reference_frequency_khz) / - (iv_frequency_step_khz)); - i_localppb->dpll_pstate0_value = revle32(i_localppb->dpll_pstate0_value); + // VDMParmBlock + memset (&(l_pLocalPspbTemp->vdm), 0, sizeof(l_pLocalPspbTemp->vdm)); - FAPI_INF("l_localppb.dpll_pstate0_value %X (%d)", - revle32(i_localppb->dpll_pstate0_value), - revle32(i_localppb->dpll_pstate0_value)); + l_pLocalPspbTemp->dpll_pstate0_value = + ((iv_reference_frequency_khz) / + (iv_frequency_step_khz)); + l_pLocalPspbTemp->dpll_pstate0_value = revle32(l_pLocalPspbTemp->dpll_pstate0_value); - i_localppb->resclk = iv_resclk_setup; + FAPI_INF("l_localppb.dpll_pstate0_value %X (%d)", + revle32(l_pLocalPspbTemp->dpll_pstate0_value), + revle32(l_pLocalPspbTemp->dpll_pstate0_value)); - if (iv_attrs.attr_system_vdm_disable == fapi2::ENUM_ATTR_SYSTEM_VDM_DISABLE_OFF) - { + l_pLocalPspbTemp->resclk = iv_resclk_setup; + + if (iv_attrs.attr_system_vdm_disable == fapi2::ENUM_ATTR_SYSTEM_VDM_DISABLE_OFF) + { - //Initializing threshold and jump values for LPPB - memcpy ( i_localppb->vid_point_set, - iv_vid_point_set, - sizeof(i_localppb->vid_point_set)); + //Initializing threshold and jump values for LPPB + memcpy ( l_pLocalPspbTemp->vid_point_set, + iv_vid_point_set, + sizeof(l_pLocalPspbTemp->vid_point_set)); - memcpy ( i_localppb->threshold_set, - iv_threshold_set, - sizeof(i_localppb->threshold_set)); + memcpy ( l_pLocalPspbTemp->threshold_set, + iv_threshold_set, + sizeof(l_pLocalPspbTemp->threshold_set)); - memcpy ( i_localppb->jump_value_set, - iv_jump_value_set, - sizeof(i_localppb->jump_value_set)); + memcpy ( l_pLocalPspbTemp->jump_value_set, + iv_jump_value_set, + sizeof(l_pLocalPspbTemp->jump_value_set)); - memcpy ( i_localppb->PsVIDCompSlopes, - iv_PsVIDCompSlopes, - sizeof(i_localppb->PsVIDCompSlopes)); + memcpy ( l_pLocalPspbTemp->PsVIDCompSlopes, + iv_PsVIDCompSlopes, + sizeof(l_pLocalPspbTemp->PsVIDCompSlopes)); - memcpy ( i_localppb->PsVDMThreshSlopes, - iv_PsVDMThreshSlopes, - sizeof(i_localppb->PsVDMThreshSlopes)); + memcpy ( l_pLocalPspbTemp->PsVDMThreshSlopes, + iv_PsVDMThreshSlopes, + sizeof(l_pLocalPspbTemp->PsVDMThreshSlopes)); - memcpy ( i_localppb->PsVDMJumpSlopes, - iv_PsVDMJumpSlopes, - sizeof(i_localppb->PsVDMJumpSlopes)); - } + memcpy ( l_pLocalPspbTemp->PsVDMJumpSlopes, + iv_PsVDMJumpSlopes, + sizeof(l_pLocalPspbTemp->PsVDMJumpSlopes)); + } + + }// for eq }while(0); +fapi_try_exit: FAPI_INF("<<<<<<<< lppb_init"); return fapi2::current_err; @@ -764,7 +779,7 @@ fapi2::ReturnCode PlatPmPPB::lppb_init( /////////////////////////////////////////////////////////// -//////// gppb_init +//////// gppb_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::gppb_init( GlobalPstateParmBlock *io_globalppb) @@ -878,9 +893,9 @@ fapi2::ReturnCode PlatPmPPB::gppb_init( if (iv_attrs.attr_system_vdm_disable == fapi2::ENUM_ATTR_SYSTEM_VDM_DISABLE_OFF) { //Initializing threshold and jump values for GPPB - memcpy ( io_globalppb->vid_point_set, - iv_vid_point_set, - sizeof(io_globalppb->vid_point_set)); + for (uint8_t p = 0; p < NUM_OP_POINTS; p++) { + io_globalppb->vid_point_set[p] = iv_vid_point_set[0][p]; + } memcpy ( io_globalppb->threshold_set, iv_threshold_set, @@ -890,9 +905,9 @@ fapi2::ReturnCode PlatPmPPB::gppb_init( iv_jump_value_set, sizeof(io_globalppb->jump_value_set)); - memcpy ( io_globalppb->PsVIDCompSlopes, - iv_PsVIDCompSlopes, - sizeof(io_globalppb->PsVIDCompSlopes)); + for (uint32_t r = 0; r < VPD_NUM_SLOPES_REGION; r++) { + io_globalppb->PsVIDCompSlopes[r] = iv_PsVIDCompSlopes[0][r]; + } memcpy ( io_globalppb->PsVDMThreshSlopes, iv_PsVDMThreshSlopes, @@ -937,6 +952,13 @@ fapi2::ReturnCode PlatPmPPB::gppb_init( FAPI_INF("SafeVoltage=%u",revle32(io_globalppb->safe_voltage_mv)); } + //Avs Bus topplogy + io_globalppb->avs_bus_topology.vdd_avsbus_num = iv_attrs.vdd_bus_num; + io_globalppb->avs_bus_topology.vdd_avsbus_rail = iv_attrs.vdd_rail_select; + io_globalppb->avs_bus_topology.vdn_avsbus_num = iv_attrs.vdn_bus_num; + io_globalppb->avs_bus_topology.vdn_avsbus_rail = iv_attrs.vdn_rail_select; + io_globalppb->avs_bus_topology.vcs_avsbus_num = iv_attrs.vcs_bus_num; + io_globalppb->avs_bus_topology.vcs_avsbus_rail = iv_attrs.vcs_rail_select; } while (0); @@ -960,7 +982,7 @@ fapi2::ReturnCode PlatPmPPB::gppb_init( // Inflection Point 0 is POWERSAVE // /////////////////////////////////////////////////////////// -//////// compute_PStateV_slope +//////// compute_PStateV_slope /////////////////////////////////////////////////////////// void PlatPmPPB::compute_PStateV_slope( GlobalPstateParmBlock* o_gppb) @@ -1018,7 +1040,7 @@ void PlatPmPPB::compute_PStateV_slope( /////////////////////////////////////////////////////////// -//////// wof_init +//////// wof_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::wof_init( uint8_t* o_buf, @@ -1220,7 +1242,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// update_vfrt +//////// update_vfrt /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::update_vfrt( uint8_t* i_pBuffer, @@ -1422,14 +1444,14 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// safe_mode_init +//////// safe_mode_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::safe_mode_init( void ) { FAPI_INF(">>>>>>>>>> safe_mode_init"); uint8_t l_ps_pstate = 0; Safe_mode_parameters l_safe_mode_values; - uint32_t l_ps_freq_khz = + uint32_t l_ps_freq_khz = iv_operating_points[VPD_PT_SET_BIASED][POWERSAVE].frequency_mhz * 1000; do @@ -1462,18 +1484,18 @@ fapi_try_exit: /////////////////////////////////////////////////////////// //////// vdm_init /////////////////////////////////////////////////////////// -void PlatPmPPB::vdm_init( void ) +fapi2::ReturnCode PlatPmPPB::vdm_init( void ) { FAPI_INF(">>>>>>>> vdm_init"); do { uint8_t l_biased_pstate[NUM_OP_POINTS]; - memset(&iv_vid_point_set,0, sizeof(iv_vid_point_set)); - memset(iv_threshold_set,0,sizeof(iv_threshold_set)); - memset(&iv_PsVIDCompSlopes,0,sizeof(iv_PsVIDCompSlopes)); - memset(iv_PsVDMThreshSlopes,0,sizeof(iv_PsVDMThreshSlopes)); - memset(iv_jump_value_set,0,sizeof(iv_jump_value_set)); - memset(iv_PsVDMJumpSlopes,0,sizeof(iv_PsVDMJumpSlopes)); + memset( &iv_vid_point_set[0], 0, sizeof(iv_vid_point_set) ); + memset(iv_threshold_set, 0, sizeof(iv_threshold_set)); + memset( &iv_PsVIDCompSlopes[0], 0, sizeof(iv_PsVIDCompSlopes) ); + memset(iv_PsVDMThreshSlopes, 0, sizeof(iv_PsVDMThreshSlopes)); + memset(iv_jump_value_set, 0, sizeof(iv_jump_value_set)); + memset(iv_PsVDMJumpSlopes, 0, sizeof(iv_PsVDMJumpSlopes)); for (uint8_t i = 0; i < NUM_OP_POINTS; ++i) { @@ -1483,27 +1505,29 @@ void PlatPmPPB::vdm_init( void ) if (iv_attrs.attr_system_vdm_disable == fapi2::ENUM_ATTR_SYSTEM_VDM_DISABLE_OFF) { - compute_vdm_threshold_pts(); + //loop thru the quad list + FAPI_TRY(compute_vdm_threshold_pts()); // VID slope calculation - compute_PsVIDCompSlopes_slopes(l_biased_pstate); + FAPI_TRY(compute_PsVIDCompSlopes_slopes(l_biased_pstate)); // VDM threshold slope calculation compute_PsVDMThreshSlopes(l_biased_pstate); // VDM Jump slope calculation compute_PsVDMJumpSlopes (l_biased_pstate); - } }while(0); FAPI_INF("<<<<<<<< vdm_init"); +fapi_try_exit: + return fapi2::current_err; } //end of vdm_init /////////////////////////////////////////////////////////// -//////// compute_PsVDMJumpSlopes +//////// compute_PsVDMJumpSlopes /////////////////////////////////////////////////////////// void PlatPmPPB::compute_PsVDMJumpSlopes( uint8_t* i_pstate) @@ -1528,10 +1552,10 @@ void PlatPmPPB::compute_PsVDMJumpSlopes( { iv_PsVDMJumpSlopes[region][i] = revle16( - compute_slope_thresh(iv_jump_value_set[region+1][i], + compute_slope_thresh(iv_jump_value_set[region + 1][i], iv_jump_value_set[region][i], i_pstate[region], - i_pstate[region+1]) + i_pstate[region + 1]) ); FAPI_INF("PsVDMJumpSlopes %s %x N_S %d N_L %d L_S %d S_N %d", @@ -1549,7 +1573,7 @@ void PlatPmPPB::compute_PsVDMJumpSlopes( /////////////////////////////////////////////////////////// -//////// compute_PsVDMThreshSlopes +//////// compute_PsVDMThreshSlopes /////////////////////////////////////////////////////////// void PlatPmPPB::compute_PsVDMThreshSlopes( uint8_t* i_pstate) @@ -1572,7 +1596,7 @@ void PlatPmPPB::compute_PsVDMThreshSlopes( { iv_PsVDMThreshSlopes[region][i] = revle16( - compute_slope_thresh(iv_threshold_set[region+1][i], + compute_slope_thresh(iv_threshold_set[region + 1][i], iv_threshold_set[region][i], i_pstate[region], i_pstate[region+1]) @@ -1593,9 +1617,9 @@ void PlatPmPPB::compute_PsVDMThreshSlopes( /////////////////////////////////////////////////////////// -//////// compute_PsVIDCompSlopes_slopes +//////// compute_PsVIDCompSlopes_slopes /////////////////////////////////////////////////////////// -void PlatPmPPB::compute_PsVIDCompSlopes_slopes( +fapi2::ReturnCode PlatPmPPB::compute_PsVIDCompSlopes_slopes( uint8_t* i_pstate) { do @@ -1604,6 +1628,8 @@ void PlatPmPPB::compute_PsVIDCompSlopes_slopes( "REGION_NOMINAL_TURBO", "REGION_TURBO_ULTRA" }; + uint8_t l_eqPos = 0; + auto l_eqChiplets = iv_procChip.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); // ULTRA TURBO pstate check is not required..because its pstate will be // 0 @@ -1615,37 +1641,53 @@ void PlatPmPPB::compute_PsVIDCompSlopes_slopes( break; } - for(auto region(REGION_POWERSAVE_NOMINAL); region <= REGION_TURBO_ULTRA; ++region) + for( auto eq : l_eqChiplets ) { - iv_PsVIDCompSlopes[region] = - revle16( - compute_slope_4_12( iv_vid_point_set[region + 1], - iv_vid_point_set[region], - i_pstate[region], - i_pstate[region + 1]) - ); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, eq, l_eqPos )); + + for(auto region(REGION_POWERSAVE_NOMINAL); region <= REGION_TURBO_ULTRA; ++region) + { + iv_PsVIDCompSlopes[l_eqPos][region] = + revle16( + compute_slope_4_12( iv_vid_point_set[l_eqPos][region + 1], + iv_vid_point_set[l_eqPos][region], + i_pstate[region], + i_pstate[region + 1]) + ); - FAPI_DBG("PsVIDCompSlopes[%s] 0x%04x %d", region_names[region], - revle16(iv_PsVIDCompSlopes[region]), - revle16(iv_PsVIDCompSlopes[region])); + FAPI_DBG( "PsVIDCompSlopes[%s] 0x%04x %d", region_names[region], + revle16(iv_PsVIDCompSlopes[l_eqPos][region]), + revle16(iv_PsVIDCompSlopes[l_eqPos][region]) ); + } } } while(0); -} // end of compute_PsVIDCompSlopes_slopes + +fapi_try_exit: +return fapi2::current_err; + +} // end of compute_PsVIDCompSlopes_slopes /////////////////////////////////////////////////////////// //////// compute_vdm_threshold_pts /////////////////////////////////////////////////////////// -void PlatPmPPB::compute_vdm_threshold_pts() +fapi2::ReturnCode PlatPmPPB::compute_vdm_threshold_pts() { int p = 0; + uint8_t l_eqPos = 0; + auto l_eqChiplets = iv_procChip.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); - //VID POINTS - for (p = 0; p < NUM_OP_POINTS; p++) + for( auto eq : l_eqChiplets ) { - iv_vid_point_set[p] = iv_poundW_data.poundw[p].vdm_vid_compare_ivid; - FAPI_INF("Bi:VID=%x", iv_vid_point_set[p]); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, eq, l_eqPos )); + + //VID POINTS + for (p = 0; p < NUM_OP_POINTS; p++) + { + iv_vid_point_set[l_eqPos][p] = iv_poundW_data.poundw[p].vdm_vid_compare_per_quad[l_eqPos]; + FAPI_INF("Bi:VID=%x", iv_vid_point_set[l_eqPos][p]); + } } // Threshold points @@ -1689,10 +1731,13 @@ void PlatPmPPB::compute_vdm_threshold_pts() FAPI_INF("Bi: S_L =%d", iv_jump_value_set[p][3]); } + +fapi_try_exit: +return fapi2::current_err; } //end of compute_vdm_threshold_pts /////////////////////////////////////////////////////////// -//////// ps2v_mv +//////// ps2v_mv /////////////////////////////////////////////////////////// uint32_t PlatPmPPB::ps2v_mv(const Pstate i_pstate) { @@ -1817,11 +1862,11 @@ fapi2::ReturnCode PlatPmPPB::safe_mode_computation( "Core floor freqency is greater than UltraTurbo frequency"); } - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_FREQUENCY_MHZ, iv_procChip, l_safe_mode_freq_mhz)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_VOLTAGE_MV, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SAFE_MODE_VOLTAGE_MV, iv_procChip, l_safe_mode_mv)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_BOOT_VOLTAGE, + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDD_BOOT_VOLTAGE, iv_procChip, l_boot_mv)); FAPI_DBG ("l_safe_mode_freq_mhz 0%08x (%d)", @@ -1866,7 +1911,7 @@ fapi2::ReturnCode PlatPmPPB::safe_mode_computation( (float)(l_safe_mode_values.safe_op_freq_mhz * 1000)) / (float)iv_frequency_step_khz; - l_safe_mode_op_ps2freq_mhz = (iv_reference_frequency_khz - + l_safe_mode_op_ps2freq_mhz = (iv_reference_frequency_khz - (l_safe_mode_values.safe_op_ps * iv_frequency_step_khz)) / 1000; while (l_safe_mode_op_ps2freq_mhz < l_safe_mode_values.safe_op_freq_mhz) @@ -1980,7 +2025,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// attr_init +//////// attr_init /////////////////////////////////////////////////////////// void PlatPmPPB::attr_init( void ) { @@ -2043,7 +2088,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as DATABLOCK_GET_ATTR(ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE, iv_procChip, attr_voltage_int_vdd_bias_powersave); // Frequency attributes - DATABLOCK_GET_ATTR(ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_proc_refclock_khz); + DATABLOCK_GET_ATTR(ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, attr_freq_dpll_refclock_khz); DATABLOCK_GET_ATTR(ATTR_FREQ_PB_MHZ, FAPI_SYSTEM, attr_nest_frequency_mhz); DATABLOCK_GET_ATTR(ATTR_FREQ_CORE_CEILING_MHZ, FAPI_SYSTEM, attr_freq_core_ceiling_mhz); DATABLOCK_GET_ATTR(ATTR_SAFE_MODE_FREQUENCY_MHZ,iv_procChip, attr_pm_safe_frequency_mhz); @@ -2074,13 +2119,13 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as DATABLOCK_GET_ATTR(ATTR_TDP_RDP_CURRENT_FACTOR, iv_procChip, attr_tdp_rdp_current_factor); - DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_START_NS, + DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_START_NS, FAPI_SYSTEM, attr_ext_vrm_transition_start_ns); - DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US, + DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_RATE_INC_UV_PER_US, FAPI_SYSTEM, attr_ext_vrm_transition_rate_inc_uv_per_us); - DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US, + DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_RATE_DEC_UV_PER_US, FAPI_SYSTEM, attr_ext_vrm_transition_rate_dec_uv_per_us); - DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS, + DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_TRANSITION_STABILIZATION_TIME_NS, FAPI_SYSTEM, attr_ext_vrm_stabilization_time_us); DATABLOCK_GET_ATTR(ATTR_EXTERNAL_VRM_STEPSIZE, FAPI_SYSTEM, attr_ext_vrm_step_size_mv); DATABLOCK_GET_ATTR(ATTR_NEST_LEAKAGE_PERCENT, FAPI_SYSTEM, attr_nest_leakage_percent); @@ -2105,12 +2150,12 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as DATABLOCK_GET_ATTR(ATTR_PROC_R_LOADLINE_VCS_UOHM, iv_procChip, r_loadline_vcs_uohm); DATABLOCK_GET_ATTR(ATTR_PROC_R_DISTLOSS_VCS_UOHM, iv_procChip, r_distloss_vcs_uohm); DATABLOCK_GET_ATTR(ATTR_PROC_VRM_VOFFSET_VCS_UV, iv_procChip, vrm_voffset_vcs_uv); - DATABLOCK_GET_ATTR(ATTR_FREQ_PROC_REFCLOCK_KHZ, FAPI_SYSTEM, freq_proc_refclock_khz); + DATABLOCK_GET_ATTR(ATTR_FREQ_DPLL_REFCLOCK_KHZ, FAPI_SYSTEM, freq_proc_refclock_khz); DATABLOCK_GET_ATTR(ATTR_PROC_DPLL_DIVIDER, iv_procChip, proc_dpll_divider); // AVSBus ... needed by p9_setup_evid //Get WOV attributes - DATABLOCK_GET_ATTR(ATTR_SYSTEM_WOV_OVERV_DISABLE, FAPI_SYSTEM,attr_wov_overv_enable); - DATABLOCK_GET_ATTR(ATTR_SYSTEM_WOV_UNDERV_DISABLE, FAPI_SYSTEM,attr_wov_underv_enable); + DATABLOCK_GET_ATTR(ATTR_SYSTEM_WOV_OVERV_DISABLE, FAPI_SYSTEM,attr_wov_overv_disable); + DATABLOCK_GET_ATTR(ATTR_SYSTEM_WOV_UNDERV_DISABLE, FAPI_SYSTEM,attr_wov_underv_disable); DATABLOCK_GET_ATTR(ATTR_WOV_UNDERV_FORCE, iv_procChip,attr_wov_underv_force); DATABLOCK_GET_ATTR(ATTR_WOV_SAMPLE_125US, iv_procChip,attr_wov_sample_125us); DATABLOCK_GET_ATTR(ATTR_WOV_MAX_DROOP_10THPCT, iv_procChip,attr_wov_max_droop_pct); @@ -2135,7 +2180,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as #_attr_name, iv_attrs._attr_name, iv_attrs._attr_name); \ } - SET_DEFAULT(attr_freq_proc_refclock_khz, 133333); + SET_DEFAULT(attr_freq_dpll_refclock_khz, 133333); SET_DEFAULT(freq_proc_refclock_khz, 133333); // Future: collapse this out SET_DEFAULT(attr_ext_vrm_transition_start_ns, EXT_VRM_TRANSITION_START_NS) SET_DEFAULT(attr_ext_vrm_transition_rate_inc_uv_per_us, EXT_VRM_TRANSITION_RATE_INC_UV_PER_US) @@ -2268,7 +2313,7 @@ FAPI_INF("%-60s = 0x%08x %d", #attr_name, iv_attrs.attr_assign, iv_attrs.attr_as iv_wov_overv_enabled = true; //Calculate nest & frequency_step_khz - iv_frequency_step_khz = (iv_attrs.attr_freq_proc_refclock_khz / + iv_frequency_step_khz = (iv_attrs.attr_freq_dpll_refclock_khz / iv_attrs.attr_proc_dpll_divider); iv_nest_freq_mhz = iv_attrs.attr_nest_frequency_mhz; @@ -2362,9 +2407,9 @@ void PlatPmPPB::compute_vpd_pts() //BIASED POINTS for (p = 0; p < NUM_OP_POINTS; p++) { - uint32_t l_frequency_mhz = (iv_biased_vpd_pts[p].frequency_mhz); - uint32_t l_vdd_mv = (iv_biased_vpd_pts[p].vdd_mv); - uint32_t l_vcs_mv = (iv_biased_vpd_pts[p].vcs_mv); + uint32_t l_frequency_mhz = (iv_raw_vpd_pts[p].frequency_mhz); + uint32_t l_vdd_mv = (iv_raw_vpd_pts[p].vdd_mv); + uint32_t l_vcs_mv = (iv_raw_vpd_pts[p].vcs_mv); iv_operating_points[VPD_PT_SET_BIASED][p].vdd_mv = bias_adjust_mv(l_vdd_mv, iv_bias[p].vdd_ext_hp); @@ -2457,7 +2502,7 @@ void PlatPmPPB::compute_vpd_pts() /////////////////////////////////////////////////////////// -//////// resclk_init +//////// resclk_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::resclk_init( void ) { @@ -2485,7 +2530,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// res_clock_setup +//////// res_clock_setup /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::res_clock_setup (void) { @@ -2696,7 +2741,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// get_ivrm_parms +//////// get_ivrm_parms /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::get_ivrm_parms () { @@ -2752,7 +2797,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// chk_valid_poundv +//////// chk_valid_poundv /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::chk_valid_poundv( const bool i_biased_state) @@ -2805,7 +2850,7 @@ fapi2::ReturnCode PlatPmPPB::chk_valid_poundv( (l_attr_mvpd_data[pv_op_order[i]].vcs_mv), (l_attr_mvpd_data[pv_op_order[i]].ics_100ma)); - if (is_wof_enabled() && + if (is_wof_enabled() && (strcmp(pv_op_str[pv_op_order[i]], "UltraTurbo") == 0)) { if (l_attr_mvpd_data[pv_op_order[i]].frequency_mhz == 0 || @@ -2979,25 +3024,25 @@ fapi2::ReturnCode PlatPmPPB::chk_valid_poundv( // Only skip checkinug for WOF not enabled and UltraTurbo. if ( is_wof_enabled() || - (!( !is_wof_enabled() && + (!( !is_wof_enabled() && (strcmp(pv_op_str[pv_op_order[i]], "UltraTurbo") == 0)))) { - if (l_attr_mvpd_data[pv_op_order[i - 1]].frequency_mhz > + if (l_attr_mvpd_data[pv_op_order[i - 1]].frequency_mhz > l_attr_mvpd_data[pv_op_order[i]].frequency_mhz || - l_attr_mvpd_data[pv_op_order[i - 1]].vdd_mv > + l_attr_mvpd_data[pv_op_order[i - 1]].vdd_mv > l_attr_mvpd_data[pv_op_order[i]].vdd_mv || - l_attr_mvpd_data[pv_op_order[i - 1]].idd_100ma > + l_attr_mvpd_data[pv_op_order[i - 1]].idd_100ma > l_attr_mvpd_data[pv_op_order[i]].idd_100ma || - l_attr_mvpd_data[pv_op_order[i - 1]].vcs_mv > + l_attr_mvpd_data[pv_op_order[i - 1]].vcs_mv > l_attr_mvpd_data[pv_op_order[i]].vcs_mv || - l_attr_mvpd_data[pv_op_order[i - 1]].ics_100ma > + l_attr_mvpd_data[pv_op_order[i - 1]].ics_100ma > l_attr_mvpd_data[pv_op_order[i]].ics_100ma ) { iv_pstates_enabled = false; if (attr_poundv_validity_halt_disable) { - FAPI_IMP("**** WARNING : halt on #V validity checking has been " + FAPI_IMP("**** WARNING : halt on #V validity checking has been " "disabled and relationship errors were found"); FAPI_IMP("**** WARNING : Relationship error between #V operating point " "(%s > %s)(power save <= nominal <= turbo <= ultraturbo) (chiplet = %u bucket id = %u op point = %u)", @@ -3014,7 +3059,7 @@ fapi2::ReturnCode PlatPmPPB::chk_valid_poundv( FAPI_INF("%s Frequency value %u is %s %s Frequency value %u", pv_op_str[pv_op_order[i - 1]], l_attr_mvpd_data[pv_op_order[i - 1]].frequency_mhz, - POUNDV_SLOPE_CHECK(l_attr_mvpd_data[pv_op_order[i - 1]].frequency_mhz, + POUNDV_SLOPE_CHECK(l_attr_mvpd_data[pv_op_order[i - 1]].frequency_mhz, l_attr_mvpd_data[pv_op_order[i]].frequency_mhz),pv_op_str[pv_op_order[i]], l_attr_mvpd_data[pv_op_order[i]].frequency_mhz); FAPI_INF("%s VDD voltage value %u is %s %s Frequency value %u", @@ -3143,7 +3188,7 @@ fapi_try_exit: /////////////////////////////////////////////////////////// -//////// get_mvpd_poundV +//////// get_mvpd_poundV /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::get_mvpd_poundV() { @@ -3153,7 +3198,7 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundV() uint8_t j = 0; uint8_t first_chplt = 1; uint8_t bucket_id = 0; - uint8_t* l_buffer = + uint8_t* l_buffer = reinterpret_cast<uint8_t*>(malloc(sizeof(voltageBucketData_t)) ); uint8_t* l_buffer_inc = NULL; @@ -3421,11 +3466,11 @@ fapi_try_exit: FAPI_INF("<<<<<<<<<<<< apply_biased_values"); return fapi2::current_err; -} // end of apply_biased_values +} // end of apply_biased_values /////////////////////////////////////////////////////////// -//////// large_jump_defaults +//////// large_jump_defaults /////////////////////////////////////////////////////////// void PlatPmPPB::large_jump_defaults() { @@ -3452,7 +3497,7 @@ void PlatPmPPB::large_jump_defaults() /////////////////////////////////////////////////////////// -//////// get_mvpd_poundW +//////// get_mvpd_poundW /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) { @@ -3461,11 +3506,6 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) uint8_t selected_eq = 0; uint8_t bucket_id = 0; uint8_t version_id = 0; - const uint16_t VDM_VOLTAGE_IN_MV = 512; - const uint16_t MIN_VDM_VOLTAGE_IN_MV = 576; - const uint16_t VDM_GRANULARITY = 4; - uint32_t l_vdm_compare_raw_mv[NUM_OP_POINTS]; - uint32_t l_vdm_compare_biased_mv[NUM_OP_POINTS]; const char* pv_op_str[NUM_OP_POINTS] = PV_OP_ORDER_STR; @@ -3512,10 +3552,41 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) FAPI_TRY(p9_pm_get_poundw_bucket(l_eqChiplets[selected_eq], l_vdmBuf)); - bucket_id = l_vdmBuf.bucketId; - version_id = l_vdmBuf.version; + bucket_id = l_vdmBuf.bucketId; + version_id = l_vdmBuf.version; - FAPI_INF("#W chiplet = %u bucket id = %u", l_chipletNum, bucket_id, version_id); + FAPI_INF( "#W chiplet = %u bucket id = %u", l_chipletNum, bucket_id ); + + if( version_id < POUNDW_VERSION_30 ) + { + PoundW_data_per_quad l_poundwPerQuad; + PoundW_data l_poundw; + memcpy( &l_poundw, l_vdmBuf.vdmData, sizeof( PoundW_data ) ); + memset( &l_poundwPerQuad, 0, sizeof(PoundW_data_per_quad) ); + + for( size_t op = 0; op <= ULTRA; op++ ) + { + //structure mapping + l_poundwPerQuad.poundw[op].ivdd_tdp_ac_current_10ma = l_poundw.poundw[op].ivdd_tdp_ac_current_10ma; + + l_poundwPerQuad.poundw[op].ivdd_tdp_dc_current_10ma = l_poundw.poundw[op].ivdd_tdp_dc_current_10ma; + l_poundwPerQuad.poundw[op].vdm_overvolt_small_thresholds = l_poundw.poundw[op].vdm_overvolt_small_thresholds; + l_poundwPerQuad.poundw[op].vdm_large_extreme_thresholds = l_poundw.poundw[op].vdm_large_extreme_thresholds; + l_poundwPerQuad.poundw[op].vdm_normal_freq_drop = l_poundw.poundw[op].vdm_normal_freq_drop; + l_poundwPerQuad.poundw[op].vdm_normal_freq_return = l_poundw.poundw[op].vdm_normal_freq_return; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[0] = l_poundw.poundw[op].vdm_vid_compare_ivid; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[1] = l_poundw.poundw[op].vdm_vid_compare_ivid; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[2] = l_poundw.poundw[op].vdm_vid_compare_ivid; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[3] = l_poundw.poundw[op].vdm_vid_compare_ivid; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[4] = l_poundw.poundw[op].vdm_vid_compare_ivid; + l_poundwPerQuad.poundw[op].vdm_vid_compare_per_quad[5] = l_poundw.poundw[op].vdm_vid_compare_ivid; + } + + memcpy( &l_poundwPerQuad.resistance_data, &l_poundw.resistance_data , LEGACY_RESISTANCE_ENTRY_SIZE ); + l_poundwPerQuad.resistance_data.r_undervolt_allowed = l_poundw.undervolt_tested; + memset(&l_vdmBuf.vdmData, 0, sizeof(l_vdmBuf)); + memcpy(&l_vdmBuf.vdmData, &l_poundwPerQuad, sizeof( PoundW_data_per_quad ) ); + } //if we match with the bucket id, then we don't need to continue if (iv_poundV_bucket_id == bucket_id) @@ -3548,18 +3619,19 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) // When we read the data from VPD image the order will be N,PS,T,UT. // But we need the order PS,N,T,UT.. hence we are swapping the data // between PS and Nominal. - poundw_entry_t l_tmp_data; + poundw_entry_per_quad_t l_tmp_data; + memset( &l_tmp_data ,0, sizeof(poundw_entry_per_quad_t)); memcpy (&l_tmp_data, &(iv_poundW_data.poundw[VPD_PV_NOMINAL]), - sizeof (poundw_entry_t)); + sizeof (poundw_entry_per_quad_t)); memcpy (&(iv_poundW_data.poundw[VPD_PV_NOMINAL]), &(iv_poundW_data.poundw[VPD_PV_POWERSAVE]), - sizeof(poundw_entry_t)); + sizeof(poundw_entry_per_quad_t)); memcpy (&(iv_poundW_data.poundw[VPD_PV_POWERSAVE]), &l_tmp_data, - sizeof(poundw_entry_t)); + sizeof(poundw_entry_per_quad_t)); // If the #W version is less than 3, validate Turbo VDM large threshold // not larger than -32mV. This filters out parts that have bad VPD. If @@ -3661,83 +3733,16 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) // within #W. If VDMs are not enabled (or supported), skip all of it if (!is_vdm_enabled()) { - FAPI_INF(" get_mvpd_poundW: VDM is disabled. Skipping remaining checks"); - iv_vdm_enabled = false; - break; - } - - for (int i = 0; i < NUM_OP_POINTS; ++i) - { - l_vdm_compare_raw_mv[i] = VDM_VOLTAGE_IN_MV + (iv_poundW_data.poundw[i].vdm_vid_compare_ivid << 2); - FAPI_INF("%10s vdm_vid_compare_ivid %3d => %d mv", - pv_op_str[i], - iv_poundW_data.poundw[i].vdm_vid_compare_ivid, - l_vdm_compare_raw_mv[i]); - } - - //Validation of VPD Data - //If all VID compares are zero then use #V VDD voltage to populate local - //data structure..So that we make progress in lab with early hardware - if ( !(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid) && - !(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid) && - !(iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid) && - !(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid)) - { - //vdm_vid_compare_ivid will be in ivid units (eg HEX((Compare - //Voltage (mv) - 512mV)/4mV). - iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid = - (iv_poundV_raw_data.VddNomVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; - iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid = - (iv_poundV_raw_data.VddPSVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; - iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid = - (iv_poundV_raw_data.VddTurboVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; - iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid = - (iv_poundV_raw_data.VddUTurboVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; - }//if any one of the VID compares are zero, then need to fail because of BAD VPD image. - else if ( !(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid) || - !(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid) || - !(iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid) || - !(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid)) - { - iv_vdm_enabled = false; - FAPI_ASSERT_NOEXIT(false, - fapi2::PSTATE_PB_POUND_W_INVALID_VID_VALUE(fapi2::FAPI2_ERRL_SEV_RECOVERED) - .set_CHIP_TARGET(iv_procChip) - .set_EQ_TARGET(l_eqChiplets[selected_eq]) - .set_NOMINAL_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid) - .set_POWERSAVE_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid) - .set_TURBO_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid) - .set_ULTRA_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid), - "Pstate Parameter Block #W : one of the VID compare value is zero"); - break; - } - - // validate vid values - bool l_compare_vid_value_state = 1; - VALIDATE_VID_VALUES (iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid, - iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid, - iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid, - iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid, - l_compare_vid_value_state); - - if (!l_compare_vid_value_state) - { + FAPI_INF( "get_mvpd_poundW: VDM is disabled. Skipping remaining checks" ); iv_vdm_enabled = false; - FAPI_ASSERT_NOEXIT(false, - fapi2::PSTATE_PB_POUND_W_INVALID_VID_ORDER(fapi2::FAPI2_ERRL_SEV_RECOVERED) - .set_CHIP_TARGET(iv_procChip) - .set_EQ_TARGET(l_eqChiplets[selected_eq]) - .set_NOMINAL_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_ivid) - .set_POWERSAVE_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_ivid) - .set_TURBO_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[TURBO].vdm_vid_compare_ivid) - .set_ULTRA_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_ivid), - "Pstate Parameter Block #W VID compare data are not in increasing order"); break; } // validate threshold values bool l_threshold_value_state = 1; + validate_quad_spec_data( ); + for (uint8_t p = 0; p < NUM_OP_POINTS; ++p) { FAPI_INF("iv_poundW_data.poundw[%d].vdm_overvolt_thresholds 0x%X", @@ -3749,9 +3754,9 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) FAPI_INF("iv_poundW_data.poundw[%d].vdm_extreme_thresholds 0x%X", p,(iv_poundW_data.poundw[p].vdm_large_extreme_thresholds) & 0x0F); VALIDATE_THRESHOLD_VALUES(((iv_poundW_data.poundw[p].vdm_overvolt_small_thresholds >> 4) & 0x0F), // overvolt - ((iv_poundW_data.poundw[p].vdm_overvolt_small_thresholds) & 0x0F), //small - ((iv_poundW_data.poundw[p].vdm_large_extreme_thresholds >> 4) & 0x0F), //large - ((iv_poundW_data.poundw[p].vdm_large_extreme_thresholds) & 0x0F), //extreme + ((iv_poundW_data.poundw[p].vdm_overvolt_small_thresholds) & 0x0F), // small + ((iv_poundW_data.poundw[p].vdm_large_extreme_thresholds >> 4) & 0x0F), // large + ((iv_poundW_data.poundw[p].vdm_large_extreme_thresholds) & 0x0F), // extreme l_threshold_value_state); if (!l_threshold_value_state) @@ -3777,7 +3782,7 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) { // These fields are 4 bits wide, and stored in a uint8, hence the shifting // N_S, N_L, L_S, S_N - FAPI_INF("iv_poundW_data.poundw[%d] VDM_FREQ_DROP N_S = %d", + FAPI_INF("iv_poundW_data.poundw[%d] VDM_FREQ_DROP N_S = %d", p, ((iv_poundW_data.poundw[p].vdm_normal_freq_drop >> 4) & 0x0F)); FAPI_INF("iv_poundW_data.poundw[%d] VDM_FREQ_DROP N_L = %d", p, ((iv_poundW_data.poundw[p].vdm_normal_freq_drop) & 0x0F)); @@ -3809,44 +3814,16 @@ fapi2::ReturnCode PlatPmPPB::get_mvpd_poundW (void) } } - //Biased compare vid data - fapi2::ATTR_VDM_VID_COMPARE_BIAS_0P5PCT_Type l_bias_value; - - - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_VID_COMPARE_BIAS_0P5PCT, - iv_procChip, - l_bias_value), - "Error from FAPI_ATTR_GET for attribute ATTR_VDM_VID_COMPARE_BIAS_0P5PCT"); - - float l_pound_w_points[NUM_OP_POINTS]; - - for (uint8_t i = 0; i < NUM_OP_POINTS; i++) - { - l_pound_w_points[i] = calc_bias(l_bias_value[i]); - l_vdm_compare_biased_mv[i] = internal_ceil( (l_vdm_compare_raw_mv[i] * l_pound_w_points[i])); - - if (l_vdm_compare_biased_mv[i] < MIN_VDM_VOLTAGE_IN_MV) - { - l_vdm_compare_biased_mv[i] = MIN_VDM_VOLTAGE_IN_MV; - } - - iv_poundW_data.poundw[i].vdm_vid_compare_ivid = - (l_vdm_compare_biased_mv[i] - VDM_VOLTAGE_IN_MV) >> 2; - - FAPI_INF("vdm_vid_compare_ivid %x %x, %x", - iv_poundW_data.poundw[i].vdm_vid_compare_ivid, - iv_poundW_data.poundw[i].vdm_vid_compare_ivid, - l_pound_w_points[i]); - } //If we have reached this point, that means VDM is ok to be enabled. Only then we try to //enable wov undervolting - if ( ((iv_poundW_data.undervolt_tested == 1) || (iv_attrs.attr_wov_underv_force == 1)) && - is_wov_underv_enabled() == 1) { + if ( ((iv_poundW_data.resistance_data.r_undervolt_allowed == 1) || (iv_attrs.attr_wov_underv_force == 1)) && + is_wov_underv_enabled() == 1 ) + { iv_wov_underv_enabled = true; - FAPI_INF("UNDERV_TESTED or UNDERV_FORCE set to 1"); - } else{ + FAPI_DBG("UNDERV_TESTED or UNDERV_FORCE set to 1"); + } else { iv_wov_underv_enabled = false; - FAPI_INF("UNDERV_TESTED and UNDERV_FORCE set to 0"); + FAPI_DBG("UNDERV_TESTED and UNDERV_FORCE set to 0"); } @@ -3879,10 +3856,129 @@ fapi_try_exit: } // end of get_mvpd_poundW +fapi2::ReturnCode PlatPmPPB::validate_quad_spec_data( ) +{ + auto l_eqChiplets = iv_procChip.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); + uint8_t eqNum = 0; + const uint16_t VDM_VOLTAGE_IN_MV = 512; + const uint16_t VDM_GRANULARITY = 4; + const uint16_t MIN_VDM_VOLTAGE_IN_MV = 576; + const char* pv_op_str[NUM_OP_POINTS] = VPD_PV_ORDER_STR; + uint32_t l_vdm_compare_raw_mv[NUM_OP_POINTS]; + uint32_t l_vdm_compare_biased_mv[NUM_OP_POINTS]; + + for( auto eq : l_eqChiplets ) + { + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, eq, eqNum )); + + for (int i = 0; i < NUM_OP_POINTS; ++i) + { + l_vdm_compare_raw_mv[i] = VDM_VOLTAGE_IN_MV + (iv_poundW_data.poundw[i].vdm_vid_compare_per_quad[eqNum] << 2); + + FAPI_INF( "%10s Op Point [%d] vdm_vid_compare_per_quad[%d] %3d => %d mv", + pv_op_str[i], i, eqNum, iv_poundW_data.poundw[i].vdm_vid_compare_per_quad[eqNum], + l_vdm_compare_raw_mv[i] ); + } + + //Validation of VPD Data + //If all VID compares are zero then use #V VDD voltage to populate local + //data structure..So that we make progress in lab with early hardware + if ( !(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum]) && + !(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum]) && + !(iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum]) && + !(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum])) + { + //vdm_vid_compare_per_quad[eqNum] will be in ivid units (eg HEX((Compare + //Voltage (mv) - 512mV)/4mV). + iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum] = + (iv_poundV_raw_data.VddNomVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; + iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum] = + (iv_poundV_raw_data.VddPSVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; + iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum] = + (iv_poundV_raw_data.VddTurboVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; + iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum] = + (iv_poundV_raw_data.VddUTurboVltg - VDM_VOLTAGE_IN_MV ) / VDM_GRANULARITY; + }//if any one of the VID compares are zero, then need to fail because of BAD VPD image. + else if ( !(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum]) || + !(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum]) || + !(iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum]) || + !(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum])) + { + iv_vdm_enabled = false; + FAPI_ASSERT_NOEXIT(false, + fapi2::PSTATE_PB_POUND_W_INVALID_VID_VALUE(fapi2::FAPI2_ERRL_SEV_RECOVERED) + .set_CHIP_TARGET(iv_procChip) + .set_EQ_TARGET(eq) + .set_NOMINAL_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum]) + .set_POWERSAVE_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum]) + .set_TURBO_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum]) + .set_ULTRA_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum]), + "Pstate Parameter Block #W : one of the VID compare value is zero"); + break; + } + + // validate vid values + bool l_compare_vid_value_state = 1; + VALIDATE_VID_VALUES (iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum], + iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum], + iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum], + iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum], + l_compare_vid_value_state); + + if (!l_compare_vid_value_state) + { + iv_vdm_enabled = false; + FAPI_ASSERT_NOEXIT(false, + fapi2::PSTATE_PB_POUND_W_INVALID_VID_ORDER(fapi2::FAPI2_ERRL_SEV_RECOVERED) + .set_CHIP_TARGET(iv_procChip) + .set_EQ_TARGET(eq) + .set_NOMINAL_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[NOMINAL].vdm_vid_compare_per_quad[eqNum]) + .set_POWERSAVE_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[POWERSAVE].vdm_vid_compare_per_quad[eqNum]) + .set_TURBO_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[TURBO].vdm_vid_compare_per_quad[eqNum]) + .set_ULTRA_VID_COMPARE_IVID_VALUE(iv_poundW_data.poundw[ULTRA].vdm_vid_compare_per_quad[eqNum]), + "Pstate Parameter Block #W VID compare data are not in increasing order"); + break; + } + + //Biased compare vid data + fapi2::ATTR_VDM_VID_COMPARE_BIAS_0P5PCT_Type l_bias_value; + + + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_VDM_VID_COMPARE_BIAS_0P5PCT, + iv_procChip, + l_bias_value), + "Error from FAPI_ATTR_GET for attribute ATTR_VDM_VID_COMPARE_BIAS_0P5PCT"); + + float l_pound_w_points[NUM_OP_POINTS]; + + for (uint8_t i = 0; i < NUM_OP_POINTS; i++) + { + l_pound_w_points[i] = calc_bias(l_bias_value[i]); + l_vdm_compare_biased_mv[i] = internal_ceil( (l_vdm_compare_raw_mv[i] * l_pound_w_points[i])); + + if (l_vdm_compare_biased_mv[i] < MIN_VDM_VOLTAGE_IN_MV) + { + l_vdm_compare_biased_mv[i] = MIN_VDM_VOLTAGE_IN_MV; + } + + iv_poundW_data.poundw[i].vdm_vid_compare_per_quad[eqNum] = + (l_vdm_compare_biased_mv[i] - VDM_VOLTAGE_IN_MV) >> 2; + + FAPI_INF("vdm_vid_compare_per_quad[eqNum] %x %x, %x", + iv_poundW_data.poundw[i].vdm_vid_compare_per_quad[eqNum], + iv_poundW_data.poundw[i].vdm_vid_compare_per_quad[eqNum], + l_pound_w_points[i]); + } + }//for eq + +fapi_try_exit: + return fapi2::current_err; + +} /////////////////////////////////////////////////////////// -//////// iddq_print +//////// iddq_print /////////////////////////////////////////////////////////// void iddq_print(IddqTable* i_iddqt) { @@ -4192,7 +4288,7 @@ void PlatPmPPB::load_mvpd_operating_point (vpd_type i_type) iv_raw_vpd_pts[i].idd_100ma = (iv_attr_mvpd_poundV_raw[pv_op_order[i]].idd_100ma); iv_raw_vpd_pts[i].vcs_mv = (iv_attr_mvpd_poundV_raw[pv_op_order[i]].vcs_mv); iv_raw_vpd_pts[i].ics_100ma = (iv_attr_mvpd_poundV_raw[pv_op_order[i]].ics_100ma); - iv_raw_vpd_pts[i].pstate = (iv_attr_mvpd_poundV_raw[ULTRA].frequency_mhz - + iv_raw_vpd_pts[i].pstate = (iv_attr_mvpd_poundV_raw[ULTRA].frequency_mhz - iv_attr_mvpd_poundV_raw[pv_op_order[i]].frequency_mhz) * 1000 / (iv_frequency_step_khz); FAPI_INF("PSTATE %x %x %d",iv_attr_mvpd_poundV_raw[ULTRA].frequency_mhz,iv_attr_mvpd_poundV_raw[pv_op_order[i]].frequency_mhz,iv_raw_vpd_pts[i].pstate); } @@ -4206,7 +4302,7 @@ void PlatPmPPB::load_mvpd_operating_point (vpd_type i_type) iv_biased_vpd_pts[i].idd_100ma = (iv_attr_mvpd_poundV_biased[pv_op_order[i]].idd_100ma); iv_biased_vpd_pts[i].vcs_mv = (iv_attr_mvpd_poundV_biased[pv_op_order[i]].vcs_mv); iv_biased_vpd_pts[i].ics_100ma = (iv_attr_mvpd_poundV_biased[pv_op_order[i]].ics_100ma); - iv_biased_vpd_pts[i].pstate = (iv_attr_mvpd_poundV_biased[ULTRA].frequency_mhz - + iv_biased_vpd_pts[i].pstate = (iv_attr_mvpd_poundV_biased[ULTRA].frequency_mhz - iv_attr_mvpd_poundV_biased[pv_op_order[i]].frequency_mhz) * 1000 / (iv_frequency_step_khz); } } @@ -4216,7 +4312,7 @@ void PlatPmPPB::load_mvpd_operating_point (vpd_type i_type) /////////////////////////////////////////////////////////// -//////// vpd_init +//////// vpd_init /////////////////////////////////////////////////////////// fapi2::ReturnCode PlatPmPPB::vpd_init( void ) { @@ -4308,22 +4404,22 @@ fapi_try_exit: } // end of vpd_init /////////////////////////////////////////////////////////// -//////// is_wov_underv_enabled +//////// is_wov_underv_enabled /////////////////////////////////////////////////////////// bool PlatPmPPB::is_wov_underv_enabled() { - return(!(iv_attrs.attr_wov_underv_enable) && + return(!(iv_attrs.attr_wov_underv_disable) && iv_wov_underv_enabled) ? true : false; } ///-------------------------------------- /////////////////////////////////////////////////////////// -//////// is_wov_overv_enabled +//////// is_wov_overv_enabled /////////////////////////////////////////////////////////// bool PlatPmPPB::is_wov_overv_enabled() { - return (!(iv_attrs.attr_wov_overv_enable) && + return (!(iv_attrs.attr_wov_overv_disable) && iv_wov_overv_enabled) ? true : false; } @@ -4367,7 +4463,7 @@ bool PlatPmPPB::is_vdm_enabled() /////////////////////////////////////////////////////////// -//////// isPstateModeEnabled +//////// isPstateModeEnabled /////////////////////////////////////////////////////////// bool PlatPmPPB::isPstateModeEnabled() { @@ -4377,7 +4473,7 @@ bool PlatPmPPB::isPstateModeEnabled() /////////////////////////////////////////////////////////// -//////// isEqChipletPresent +//////// isEqChipletPresent /////////////////////////////////////////////////////////// bool PlatPmPPB::isEqChipletPresent () { @@ -4386,7 +4482,7 @@ bool PlatPmPPB::isEqChipletPresent () /////////////////////////////////////////////////////////// -//////// large_jump_interpolate +//////// large_jump_interpolate /////////////////////////////////////////////////////////// uint32_t PlatPmPPB::large_jump_interpolate(const Pstate i_pstate, const Pstate i_ps_pstate) @@ -4607,15 +4703,18 @@ fapi_try_exit: /////////////////////////////////////////////////////////// //////// gppb_print /////////////////////////////////////////////////////////// -void gppb_print(GlobalPstateParmBlock* i_gppb) +fapi2::ReturnCode gppb_print(GlobalPstateParmBlock* i_gppb, const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ) { - static const uint32_t BUFFSIZE = 256; + static const uint32_t BUFFSIZE = 512; char l_buffer[BUFFSIZE]; char l_temp_buffer[BUFFSIZE]; char l_temp_buffer1[BUFFSIZE]; const char* pv_op_str[NUM_OP_POINTS] = PV_OP_ORDER_STR; const char* thresh_op_str[NUM_THRESHOLD_POINTS] = VPD_THRESHOLD_ORDER_STR; const char* slope_region_str[VPD_NUM_SLOPES_REGION] = VPD_OP_SLOPES_REGION_ORDER_STR; + auto l_eqChiplets = i_target.getChildren<fapi2::TARGET_TYPE_EQ>(fapi2::TARGET_STATE_FUNCTIONAL); + uint8_t eqPos = 0; + int l_len = strlen(l_buffer); // Put out the endian-corrected scalars FAPI_INF("---------------------------------------------------------------------------------------"); FAPI_INF("Global Pstate Parameter Block @ %p", i_gppb); @@ -4803,10 +4902,29 @@ void gppb_print(GlobalPstateParmBlock* i_gppb) } FAPI_INF ("VID Operating Points"); - for (auto i = 0; i < NUM_OP_POINTS; ++i) + for( auto eq : l_eqChiplets ) { - sprintf (l_buffer, " %-16s : %02X ",pv_op_str[i], i_gppb->vid_point_set[i]); - FAPI_INF("%s", l_buffer); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, eq, eqPos )); + strcpy(l_buffer,""); + strcpy(l_temp_buffer, ""); + + //FIXME avoiding changes in GPSPB to address compatibility issues between + //hardware image and HWP + for (auto i = 0; i < NUM_OP_POINTS; ++i) + { + //sprintf (l_buffer, "Q[%d] %-16s : %02X ", eqPos, pv_op_str[i], i_gppb->vid_point_set[eqPos][i]); + //FAPI_INF("%s", l_buffer); + } + + for (auto j = 0; j < VPD_NUM_SLOPES_REGION; ++j) + { + //sprintf(l_temp_buffer1, "%04X", + // revle16(i_gppb->PsVIDCompSlopes[eqPos][j])); + //CENTER_STR(l_temp_buffer, l_temp_buffer1, 8); + //strcat(l_buffer, l_temp_buffer); + } + + //FAPI_INF("%s", l_buffer); } sprintf(l_buffer, "%-25s", "Thrshod Op Points: "); @@ -4832,7 +4950,6 @@ void gppb_print(GlobalPstateParmBlock* i_gppb) } sprintf(l_buffer, "VID Compare Slopes:"); - int l_len = strlen(l_buffer); for (auto j = 0; j < VPD_NUM_SLOPES_REGION; ++j) { sprintf(l_temp_buffer1, "%s", prt_region_names[j]); @@ -4842,14 +4959,6 @@ void gppb_print(GlobalPstateParmBlock* i_gppb) FAPI_INF("%s", l_buffer); sprintf( l_buffer, "%*s", l_len+6," "); - for (auto j = 0; j < VPD_NUM_SLOPES_REGION; ++j) - { - sprintf(l_temp_buffer1, "%04X", - revle16(i_gppb->PsVIDCompSlopes[j])); - CENTER_STR(l_temp_buffer, l_temp_buffer1, 8); - strcat(l_buffer, l_temp_buffer); - } - FAPI_INF("%s", l_buffer); sprintf(l_buffer, "%-18s", "VDM Thrshld Slopes:"); for (auto j = 0; j < VPD_NUM_SLOPES_REGION; ++j) @@ -4936,6 +5045,8 @@ void gppb_print(GlobalPstateParmBlock* i_gppb) } FAPI_INF("---------------------------------------------------------------------------------------"); +fapi_try_exit: + return fapi2::current_err; } // end of gppb_print @@ -5095,5 +5206,4 @@ void oppb_print(OCCPstateParmBlock* i_oppb) FAPI_INF("---------------------------------------------------------------------------------------"); } // end of oppb_print - // *INDENT-ON* diff --git a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H index 971a7be99..3d140464f 100644 --- a/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H +++ b/src/import/chips/p9/procedures/hwp/pm/p9_pstate_parameter_block.H @@ -42,7 +42,7 @@ #include <p9_pstates_occ.h> #include "p9_pm_get_poundv_bucket.H" #include "p9_pm_get_poundw_bucket.H" - +#include <p9_hcd_memmap_base.H> //Pstate SuperStructure typedef struct @@ -54,7 +54,7 @@ typedef struct GlobalPstateParmBlock globalppb; // CME content - LocalPstateParmBlock localppb; + LocalPstateParmBlock localppb[MAX_QUADS_PER_CHIP]; // OCC content OCCPstateParmBlock occppb; @@ -119,7 +119,7 @@ typedef struct uint32_t attr_proc_r_distloss_vcs_uohm; uint32_t attr_proc_vrm_voffset_vcs_uv; - uint32_t attr_freq_proc_refclock_khz; + uint32_t attr_freq_dpll_refclock_khz; uint32_t attr_proc_dpll_divider; uint32_t attr_nest_frequency_mhz; @@ -205,8 +205,8 @@ typedef struct uint32_t proc_dpll_divider; ///Undervolt and Overvolt Attributes - uint8_t attr_wov_underv_enable; - uint8_t attr_wov_overv_enable; + uint8_t attr_wov_underv_disable; + uint8_t attr_wov_overv_disable; uint8_t attr_wov_underv_force; uint32_t attr_wov_sample_125us; uint32_t attr_wov_max_droop_pct; @@ -247,21 +247,21 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Initialize VPD data - // @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + // @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode vpd_init(); /// ----------------------------------------------------------------------- /// @brief Initialize resclk data - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode resclk_init(); /// ----------------------------------------------------------------------- /// @brief Initialize WOF data /// @param[out] o_buf points to WOF data - /// @param[inout] io_size size of the wof table - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @param[inout] io_size size of the wof table + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode wof_init( uint8_t* o_buf, @@ -269,19 +269,19 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Initialize global pstate parameter block - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode gppb_init( GlobalPstateParmBlock* i_globalppb); /// ----------------------------------------------------------------------- /// @brief Initialize local pstate parameter block - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode lppb_init(LocalPstateParmBlock* i_localppb); /// ----------------------------------------------------------------------- /// @brief Initialize occ pstate parameter block - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode oppb_init(OCCPstateParmBlock* i_occppb); @@ -289,11 +289,11 @@ class PlatPmPPB /// @brief VDM initializtion based on #W data /// @return none /// ----------------------------------------------------------------------- - void vdm_init( void ); + fapi2::ReturnCode vdm_init( void ); /// ----------------------------------------------------------------------- /// @brief Safe mode frquency and voltage init - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode safe_mode_init( void ); @@ -301,7 +301,7 @@ class PlatPmPPB /// @brief VFRT data initialization from WOF data /// @param[in] i_pBuffer WOF data buffer /// @param[inout] o_vfrt_data vfrt data - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode update_vfrt( uint8_t* i_pBuffer, @@ -309,43 +309,43 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Compute and apply biased values - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode get_extint_bias(); /// ----------------------------------------------------------------------- /// @brief apply biased values for #V data - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode apply_biased_values(); /// ----------------------------------------------------------------------- /// @brief Read IQ vpd data - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode get_mvpd_iddq( void ); /// ----------------------------------------------------------------------- /// @brief Read #W(VDM) vpd data - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode get_mvpd_poundW (void); /// ----------------------------------------------------------------------- /// @brief Read IVRM data from attributes - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode get_ivrm_parms (); /// ----------------------------------------------------------------------- /// @brief Set resclk attribute values - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode set_resclk_table_attrs(); /// ----------------------------------------------------------------------- /// @brief Compute and setup resclk values - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode res_clock_setup (void); @@ -358,7 +358,7 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Compute safe mode values /// @param[in] i_action voltage config action (Compute/set) - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode compute_boot_safe( const VoltageConfigActions_t i_action); @@ -373,7 +373,7 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief This will set the pstate feature attrbutes(VDM,RESCLK,VRM,WOF) - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode set_global_feature_attributes(); @@ -410,14 +410,14 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Read #V data form module vpd - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode get_mvpd_poundV(); /// ----------------------------------------------------------------------- /// @brief Validate #V data /// @param[in] i_biased_state present/nonpresent - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode chk_valid_poundv( const bool i_biased_state); @@ -431,8 +431,9 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Converts frequency value to pstate number /// @param[in] i_freq_khz input frequency - /// @param[out] o_pstate pstate output for a given inut frequency - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @param[out] pstate pstate output for a given inut frequency + /// @param[in] i_round p-state rounding strategy + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- int freq2pState (const uint32_t freq_khz, Pstate* pstate, @@ -440,9 +441,9 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Compute safe mode values - /// @param[in] i_pstate pstate value + /// @param[in] i_ps_state pstate value /// @param[out] o_safe_mode_values safe mode freq/voltage values - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- fapi2::ReturnCode safe_mode_computation( const Pstate i_ps_pstate, @@ -451,7 +452,7 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Convert pstate to voltage /// @param[in] i_pstate pstate value that needs to be converted - /// @return fapi::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- uint32_t ps2v_mv(const Pstate i_pstate); @@ -474,16 +475,16 @@ class PlatPmPPB /// ----------------------------------------------------------------------- /// @brief Compute VID compare slope values for a given pstate /// @param[in] i_pstate pstate value - /// @return none + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- - void compute_PsVIDCompSlopes_slopes( + fapi2::ReturnCode compute_PsVIDCompSlopes_slopes( uint8_t* i_pstate); /// ----------------------------------------------------------------------- /// @brief Compute VDM threshold points for different regions - /// @return none + /// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ----------------------------------------------------------------------- - void compute_vdm_threshold_pts(); + fapi2::ReturnCode compute_vdm_threshold_pts(); /// ----------------------------------------------------------------------- /// @brief Compute bias value for pre-defined percentage unit @@ -685,8 +686,10 @@ class PlatPmPPB } #endif + private: //function + fapi2::ReturnCode validate_quad_spec_data( ); - private: + private: //data fapi2::Target< fapi2::TARGET_TYPE_PROC_CHIP > iv_procChip; // processor chip target AttributeList iv_attrs; // Pstate attributes list VpdOperatingPoint iv_raw_vpd_pts[NUM_OP_POINTS]; // Raw vpd operating points @@ -718,14 +721,14 @@ class PlatPmPPB VpdPoint iv_attr_mvpd_poundV_raw[5]; VpdPoint iv_attr_mvpd_poundV_biased[5]; - PoundW_data iv_poundW_data; + PoundW_data_per_quad iv_poundW_data; IddqTable iv_iddqt; GP_VDMParmBlock iv_vdmpb; IvrmParmBlock iv_ivrmpb; ResonantClockingSetup iv_resclk_setup; - CompareVIDPoints iv_vid_point_set[NUM_OP_POINTS]; + CompareVIDPoints iv_vid_point_set[MAX_QUADS_PER_CHIP][NUM_OP_POINTS]; uint8_t iv_threshold_set[NUM_OP_POINTS][NUM_THRESHOLD_POINTS]; - int16_t iv_PsVIDCompSlopes[VPD_NUM_SLOPES_REGION]; + int16_t iv_PsVIDCompSlopes[MAX_QUADS_PER_CHIP][VPD_NUM_SLOPES_REGION]; int16_t iv_PsVDMThreshSlopes[VPD_NUM_SLOPES_REGION][NUM_THRESHOLD_POINTS]; uint8_t iv_jump_value_set[NUM_OP_POINTS][NUM_JUMP_VALUES]; int16_t iv_PsVDMJumpSlopes[VPD_NUM_SLOPES_REGION][NUM_JUMP_VALUES]; @@ -747,10 +750,10 @@ extern "C" /// ------------------------------------------------------------------- /// @brief Print a GlobalPstateParameterBlock structure on a given stream /// @param[in] i_gppb The Global Pstate Parameter Block to print -/// @return void +/// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ------------------------------------------------------------------- - void - gppb_print(GlobalPstateParmBlock* i_gppb); + fapi2::ReturnCode gppb_print(GlobalPstateParmBlock* i_gppb, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ); /// ------------------------------------------------------------------- @@ -778,7 +781,7 @@ extern "C" /// @param[inout] *io_pss => pointer to pstate superstructure /// @param[out] *o_buf => wof table data /// @param[inout] &io_size => wof table data size -/// @return FAPI2::SUCCESS +/// @return fapi2::ReturnCode: FAPI2_RC_SUCCESS if success, else error code. /// ------------------------------------------------------------------- fapi2::ReturnCode p9_pstate_parameter_block( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H index 27603b23f..b92d439bb 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_cpu_reg_restore_instruction.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -76,7 +76,8 @@ enum SKIP_SPR_REST_INST = 0x4800001c, //b . +0x01c MFLR_R30 = 0x7fc802a6, SKIP_SPR_SELF_SAVE = 0x3bff0020, //addi r31 r31, 0x20 - MTLR_INST = 0x7fc803a6 //mtlr r30 + MTLR_INST = 0x7fc803a6, //mtlr r30 + BRANCH_BE_INST = 0x48000020, }; #ifdef __cplusplus diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C index f41086b44..d3e11e8ab 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -80,7 +80,7 @@ const uint32_t LEGACY_QUAD_SCOM_SUPPORTED = 63; //----------------------------------------------------------------------------- /** - * @brief vaildated input arguments passed to p9_stop_save_cpureg_control. + * @brief validated input arguments passed to p9_stop_save_cpureg_control. * @param[in] i_pImage point to start of HOMER * @param[in] i_coreId id of the core * @param[in] i_threadId id of the thread @@ -651,138 +651,9 @@ StopReturnCode_t p9_stop_save_cpureg( void* const i_pImage, const uint64_t i_regData, const uint64_t i_pir ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; // procedure return code - HomerSection_t* chipHomer = NULL; - SmfHomerSection_t* smfChipHomer = NULL; - - do - { - uint32_t threadId = 0; - uint32_t coreId = 0; - uint32_t lookUpKey = 0; - void* pSprEntryLocation = NULL; // an offset w.r.t. to start of image - void* pThreadLocation = NULL; - bool threadScopeReg = false; - uint8_t l_urmorFix = false; - uint64_t l_sprValue = 0; - uint8_t l_selfRestVer = 0; - - MY_INF(">> p9_stop_save_cpureg" ); - - l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); - - if( l_rc ) - { - MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", - i_pir); - break; - } - - MY_INF( " PIR 0x%016llx coreId %d threadid %d " - " registerId %d", i_pir, coreId, - threadId, i_regId ); - - // First of all let us validate all input arguments. - l_rc = validateSprImageInputs( i_pImage, - i_regId, - coreId, - &threadId, - &threadScopeReg ); - - if( l_rc ) - { - // Error: bad argument traces out error code - MY_ERR("Bad input argument rc %d", l_rc ); - - break; - } - - l_urmorFix = *(uint8_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_URMOR_FIX_BYTE); - l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); - - if( l_selfRestVer ) - { - smfChipHomer = ( SmfHomerSection_t*)i_pImage; - - if( threadScopeReg ) - { - pThreadLocation = - &(smfChipHomer->iv_coreThreadRestore[coreId].iv_threadRestoreArea[threadId][0]); - } - else - { - pThreadLocation = - &(smfChipHomer->iv_coreThreadRestore[coreId].iv_coreRestoreArea[0]); - } - } - else //Old fips or OPAL release that doesn't support SMF - { - chipHomer = (HomerSection_t*)i_pImage; - - if( threadScopeReg ) - { - pThreadLocation = - &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_threadArea[0]); - } - else - { - pThreadLocation = - &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_coreArea[0]); - } - } - - if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) || - ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) ) - { - // table for given core id doesn't exit. It needs to be - // defined. - pSprEntryLocation = pThreadLocation; - } - else - { - // an SPR restore section for given core already exists - lookUpKey = genKeyForSprLookup( i_regId ); - l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, - lookUpKey, - threadScopeReg, - &pSprEntryLocation, - l_selfRestVer ); - } - - if( l_rc ) - { - MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId ", - "0x%08x regId 0x%08x lookUpKey 0x%08x pThreadLocation 0x%08x" - , coreId, threadId, i_regId, lookUpKey, pThreadLocation ); - break; - } - - if( ( P9_STOP_SPR_URMOR == i_regId ) && ( l_urmorFix ) ) - { - l_sprValue = i_regData - URMOR_CORRECTION; - } - else - { - l_sprValue = i_regData; - } - - l_rc = updateSprEntryInImage( (uint32_t*) pSprEntryLocation, - i_regId, - l_sprValue, - UPDATE_SPR_ENTRY ); - - if( l_rc ) - { - MY_ERR( " Failed to update the SPR entry of PIR 0x%08x reg" - "0x%08x", i_pir, i_regId ); - break; - } - - } - while(0); + MY_INF(">> p9_stop_save_cpureg" ); - MY_INF("<< p9_stop_save_cpureg" ); - return l_rc; + return proc_stop_save_cpureg( i_pImage, i_regId, i_regData, i_pir ); } //----------------------------------------------------------------------------- @@ -1008,6 +879,239 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, const ScomOperation_t i_operation, const ScomSection_t i_section ) { + MY_INF(">> p9_stop_save_scom"); + + return proc_stop_save_scom( i_pImage, i_scomAddress, + i_scomData, i_operation, i_section ); +} + +//----------------------------------------------------------------------------- + +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_sprBitPos bit position associated with SPR in save mask vector. + * @param[in] l_pSprSaveStart start location of SPR save segment + * @param[in] i_searchLength length of SPR save segment + * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, + uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) +{ + int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); + uint32_t l_oriInst = getOriInstruction( 0, 0, i_sprBitPos ); + StopReturnCode_t l_rc = STOP_SAVE_FAIL; + + while( l_saveWordLength > 0 ) + { + if( l_oriInst == *l_pSprSaveStart ) + { + *i_pSaveSprLoc = l_pSprSaveStart; + l_rc = STOP_SAVE_SUCCESS; + break; + } + + l_pSprSaveStart++; + l_saveWordLength--; + } + + return l_rc; +} + +//----------------------------------------------------------------------------- + +/** + * @brief searches a self save entry of an SPR in self-save segment. + * @param[in] i_pSaveReg start of editable location of a SPR save entry. + * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. + * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. + */ +STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + + do + { + if( !i_pSaveReg ) + { + l_rc = STOP_SAVE_FAIL; + MY_ERR( "Failed to update self save area for SPR 0x%04x", i_sprNum ); + break; + } + + if( P9_STOP_SPR_MSR == i_sprNum ) + { + *i_pSaveReg = getMfmsrInstruction( 1 ); + } + else + { + *i_pSaveReg = getMfsprInstruction( 1, i_sprNum ); + } + + i_pSaveReg++; + + *i_pSaveReg = getBranchLinkRegInstruction( ); + } + while(0); + + return l_rc; +} + +//----------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ) +{ + MY_INF( ">> p9_stop_save_cpureg_control" ); + + return proc_stop_save_cpureg_control( i_pImage, i_pir, i_saveRegVector ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +{ + MY_INF( ">> p9_stop_init_cpureg" ); + + return proc_stop_init_cpureg( i_pImage, i_corePos ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) +{ + MY_INF( ">> p9_stop_init_self_save" ); + + return proc_stop_init_self_save( i_pImage, i_corePos ); +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +{ + + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint32_t* l_pRestoreStart = NULL; + void* l_pTempLoc = NULL; + SmfHomerSection_t* l_pHomer = NULL; + uint32_t l_threadPos = 0; + uint32_t l_lookUpKey = 0; + uint32_t l_sprIndex = 0; + uint8_t l_selfRestVer = 0; + + MY_INF( ">> proc_stop_init_cpureg" ); + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + if( i_corePos > MAX_CORE_ID_SUPPORTED ) + { + l_rc = STOP_SAVE_ARG_INVALID_CORE; + break; + } + + l_pHomer = ( SmfHomerSection_t * ) i_pImage; + l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); + + for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED; l_sprIndex++ ) + { + //Check if a given SPR needs to be self-saved each time on STOP entry + + l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId ); + + if( g_sprRegister[l_sprIndex].iv_isThreadScope ) + { + for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) + { + l_pRestoreStart = + (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_threadRestoreArea[l_threadPos][0]; + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister[l_sprIndex].iv_isThreadScope, + &l_pTempLoc, + l_selfRestVer ); + + if( l_rc ) + { + MY_ERR( "Thread SPR lookup failed in p9_stop_init_cpureg SPR %d Core %d Thread %d Index %d", + g_sprRegister[l_sprIndex].iv_sprId, i_corePos, l_threadPos, l_sprIndex ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Thread SPR region init failed. Core %d SPR Id %d", + i_corePos, g_sprRegister[l_sprIndex].iv_sprId ); + break; + } + + }//end for thread + + if( l_rc ) + { + break; + } + + }//end if SPR threadscope + else + { + l_pRestoreStart = (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_coreRestoreArea[0]; + + l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, + g_sprRegister[l_sprIndex].iv_isThreadScope, + &l_pTempLoc, l_selfRestVer ); + + if( l_rc ) + { + MY_ERR( "Core SPR lookup failed in p9_stop_init_cpureg" ); + break; + } + + l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, + ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, + 0x00, + INIT_SPR_REGION ); + + if( l_rc ) + { + MY_ERR( "Core SPR region init failed. Core %d SPR Id %d SPR Index %d", + i_corePos, g_sprRegister[l_sprIndex].iv_sprId, l_sprIndex ); + break; + } + + }// end else + + }// end for l_sprIndex + + } + while(0); + + MY_INF( "<< proc_stop_init_cpureg" ); + + return l_rc; +} + +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ) +{ + MY_INF( ">> proc_stop_save_scom" ); + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t entryLimit = 0; uint8_t chipletId = 0; @@ -1028,7 +1132,6 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, uint32_t swizzleBlr = SWIZZLE_4_BYTE(BLR_INST); bool cacheEntry = true; - MY_INF(">> p9_stop_save_scom"); //Reads SGPE image version info from QPMR Header in HOMER //For backward compatibility, for base version of SGPE Hcode, @@ -1323,87 +1426,16 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, updateEntryHeader( pEditScomHeader, imageVer, l_maxScomRestoreEntry ); } - MY_INF("<< p9_stop_save_scom"); - return l_rc; -} - -//----------------------------------------------------------------------------- - -/** - * @brief searches a self save entry of an SPR in self-save segment. - * @param[in] i_sprBitPos bit position associated with SPR in save mask vector. - * @param[in] l_pSprSaveStart start location of SPR save segment - * @param[in] i_searchLength length of SPR save segment - * @param[in] i_pSaveSprLoc start location of save entry for a given SPR. - * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. - */ -STATIC StopReturnCode_t lookUpSelfSaveSpr( uint32_t i_sprBitPos, uint32_t* l_pSprSaveStart, - uint32_t i_searchLength, uint32_t** i_pSaveSprLoc ) -{ - int32_t l_saveWordLength = (int32_t)(i_searchLength >> 2); - uint32_t l_oriInst = getOriInstruction( 0, 0, i_sprBitPos ); - StopReturnCode_t l_rc = STOP_SAVE_FAIL; - - while( l_saveWordLength > 0 ) - { - if( l_oriInst == *l_pSprSaveStart ) - { - *i_pSaveSprLoc = l_pSprSaveStart; - l_rc = STOP_SAVE_SUCCESS; - break; - } - - l_pSprSaveStart++; - l_saveWordLength--; - } - - return l_rc; -} - -//----------------------------------------------------------------------------- - -/** - * @brief searches a self save entry of an SPR in self-save segment. - * @param[in] i_pSaveReg start of editable location of a SPR save entry. - * @param[in] i_sprNum Id of the SPR for which entry needs to be edited. - * @return STOP_SAVE_SUCCESS if look up succeeds, error code otherwise. - */ -STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sprNum ) -{ - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - - do - { - if( !i_pSaveReg ) - { - l_rc = STOP_SAVE_FAIL; - MY_ERR( "Failed to update self save area for SPR 0x%04x", i_sprNum ); - break; - } - - if( P9_STOP_SPR_MSR == i_sprNum ) - { - *i_pSaveReg = getMfmsrInstruction( 1 ); - } - else - { - *i_pSaveReg = getMfsprInstruction( 1, i_sprNum ); - } - - i_pSaveReg++; - - *i_pSaveReg = getBranchLinkRegInstruction( ); - } - while(0); + MY_INF( "<< proc_stop_save_scom" ); return l_rc; } -//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, - const uint64_t i_pir, - const uint32_t i_saveRegVector ) +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ) { StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t l_coreId = 0; @@ -1419,6 +1451,7 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, uint32_t * l_pTempWord = NULL; SmfHomerSection_t* l_pHomer = NULL; uint8_t l_selfRestVer = 0; + MY_INF(">> proc_stop_save_cpureg_control" ); do { @@ -1522,134 +1555,168 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, } while(0); + MY_INF("<< proc_stop_save_cpureg_control" ); + return l_rc; + } //----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ) +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ) { - StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; - uint32_t* l_pRestoreStart = NULL; - void* l_pTempLoc = NULL; - SmfHomerSection_t* l_pHomer = NULL; - uint32_t l_threadPos = 0; - uint32_t l_lookUpKey = 0; - uint32_t l_sprIndex = 0; - uint8_t l_selfRestVer = 0; + MY_INF(">> proc_stop_save_cpureg" ); - MY_INF( ">> p9_stop_init_cpureg" ); + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; // procedure return code + HomerSection_t* chipHomer = NULL; + SmfHomerSection_t* smfChipHomer = NULL; do { - if( !i_pImage ) + uint32_t threadId = 0; + uint32_t coreId = 0; + uint32_t lookUpKey = 0; + void* pSprEntryLocation = NULL; // an offset w.r.t. to start of image + void* pThreadLocation = NULL; + bool threadScopeReg = false; + uint8_t l_urmorFix = false; + uint64_t l_sprValue = 0; + uint8_t l_selfRestVer = 0; + + + l_rc = getCoreAndThread( i_pImage, i_pir, &coreId, &threadId ); + + if( l_rc ) { - l_rc = STOP_SAVE_ARG_INVALID_IMG; + MY_ERR("Failed to determine Core Id and Thread Id from PIR 0x%016llx", + i_pir); break; } - if( i_corePos > MAX_CORE_ID_SUPPORTED ) + MY_INF( " PIR 0x%016llx coreId %d threadid %d " + " registerId %d", i_pir, coreId, + threadId, i_regId ); + + // First of all let us validate all input arguments. + l_rc = validateSprImageInputs( i_pImage, + i_regId, + coreId, + &threadId, + &threadScopeReg ); + + if( l_rc ) { - l_rc = STOP_SAVE_ARG_INVALID_CORE; + // Error: bad argument traces out error code + MY_ERR("Bad input argument rc %d", l_rc ); + break; } - l_pHomer = ( SmfHomerSection_t * ) i_pImage; + l_urmorFix = *(uint8_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + CPMR_URMOR_FIX_BYTE); l_selfRestVer = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); - for( l_sprIndex = 0; l_sprIndex < MAX_SPR_SUPPORTED; l_sprIndex++ ) + if( l_selfRestVer ) { - //Check if a given SPR needs to be self-saved each time on STOP entry - - l_lookUpKey = genKeyForSprLookup( ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId ); + smfChipHomer = ( SmfHomerSection_t*)i_pImage; - if( g_sprRegister[l_sprIndex].iv_isThreadScope ) + if( threadScopeReg ) { - for( l_threadPos = 0; l_threadPos < MAX_THREADS_PER_CORE; l_threadPos++ ) - { - l_pRestoreStart = - (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_threadRestoreArea[l_threadPos][0]; - - l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, - g_sprRegister[l_sprIndex].iv_isThreadScope, - &l_pTempLoc, - l_selfRestVer ); - - if( l_rc ) - { - MY_ERR( "Thread SPR lookup failed in p9_stop_init_cpureg SPR %d Core %d Thread %d Index %d", - g_sprRegister[l_sprIndex].iv_sprId, i_corePos, l_threadPos, l_sprIndex ); - break; - } - - l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, - ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, - 0x00, - INIT_SPR_REGION ); - - if( l_rc ) - { - MY_ERR( "Thread SPR region init failed. Core %d SPR Id %d", - i_corePos, g_sprRegister[l_sprIndex].iv_sprId ); - break; - } - - }//end for thread - - if( l_rc ) - { - break; - } - - }//end if SPR threadscope + pThreadLocation = + &(smfChipHomer->iv_coreThreadRestore[coreId].iv_threadRestoreArea[threadId][0]); + } else { - l_pRestoreStart = (uint32_t*)&l_pHomer->iv_coreThreadRestore[i_corePos].iv_coreRestoreArea[0]; + pThreadLocation = + &(smfChipHomer->iv_coreThreadRestore[coreId].iv_coreRestoreArea[0]); + } + } + else //Old fips or OPAL release that doesn't support SMF + { + chipHomer = (HomerSection_t*)i_pImage; - l_rc = lookUpSprInImage( (uint32_t*)l_pRestoreStart, l_lookUpKey, - g_sprRegister[l_sprIndex].iv_isThreadScope, - &l_pTempLoc, l_selfRestVer ); + if( threadScopeReg ) + { + pThreadLocation = + &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_threadArea[0]); + } + else + { + pThreadLocation = + &(chipHomer->iv_coreThreadRestore[coreId][threadId].iv_coreArea[0]); + } + } - if( l_rc ) - { - MY_ERR( "Core SPR lookup failed in p9_stop_init_cpureg" ); - break; - } + if( ( SWIZZLE_4_BYTE(BLR_INST) == *(uint32_t*)pThreadLocation ) || + ( SWIZZLE_4_BYTE(ATTN_OPCODE) == *(uint32_t*) pThreadLocation ) ) + { + // table for given core id doesn't exit. It needs to be + // defined. + pSprEntryLocation = pThreadLocation; + } + else + { + // an SPR restore section for given core already exists + lookUpKey = genKeyForSprLookup( i_regId ); + l_rc = lookUpSprInImage( (uint32_t*)pThreadLocation, + lookUpKey, + threadScopeReg, + &pSprEntryLocation, + l_selfRestVer ); + } - l_rc = updateSprEntryInImage( (uint32_t*) l_pTempLoc, - ( CpuReg_t )g_sprRegister[l_sprIndex].iv_sprId, - 0x00, - INIT_SPR_REGION ); + if( l_rc ) + { + MY_ERR("Invalid or corrupt SPR entry. CoreId 0x%08x threadId ", + "0x%08x regId 0x%08x lookUpKey 0x%08x pThreadLocation 0x%08x" + , coreId, threadId, i_regId, lookUpKey, pThreadLocation ); + break; + } - if( l_rc ) - { - MY_ERR( "Core SPR region init failed. Core %d SPR Id %d SPR Index %d", - i_corePos, g_sprRegister[l_sprIndex].iv_sprId, l_sprIndex ); - break; - } + if( ( P9_STOP_SPR_URMOR == i_regId ) && ( l_urmorFix ) ) + { + l_sprValue = i_regData - URMOR_CORRECTION; + } + else + { + l_sprValue = i_regData; + } - }// end else + l_rc = updateSprEntryInImage( (uint32_t*) pSprEntryLocation, + i_regId, + l_sprValue, + UPDATE_SPR_ENTRY ); - }// end for l_sprIndex + if( l_rc ) + { + MY_ERR( " Failed to update the SPR entry of PIR 0x%08x reg" + "0x%08x", i_pir, i_regId ); + break; + } } while(0); - MY_INF( "<< p9_stop_init_cpureg" ); + MY_INF("<< proc_stop_save_cpureg" ); + return l_rc; } //----------------------------------------------------------------------------------------------------- -StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ) { + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; uint32_t* l_pSaveStart = NULL; SmfHomerSection_t * l_pHomer = NULL; uint32_t l_threadPos = 0; uint32_t l_sprBitPos = 0; uint32_t l_sprIndexAdj = 0; - MY_INF( ">> p9_stop_init_self_save" ); + + MY_INF(">> proc_stop_init_self_save" ); do { @@ -1756,12 +1823,74 @@ StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i } while(0); - MY_INF( "<< p9_stop_init_self_save" ); + MY_INF("<< proc_stop_init_self_save" ); + return l_rc; } +//----------------------------------------------------------------------------------------------------- + +StopReturnCode_t proc_stop_api_discover_capability( void* const i_pImage, uint64_t * o_inCompVector ) +{ + StopReturnCode_t l_rc = STOP_SAVE_SUCCESS; + uint64_t l_incompVector = 0; + uint32_t l_tempWord = 0; + *o_inCompVector = 0; + + do + { + if( !i_pImage ) + { + l_rc = STOP_SAVE_ARG_INVALID_IMG; + break; + } + + l_tempWord = + *(uint32_t*)((uint8_t*)i_pImage + CPMR_HOMER_OFFSET + SMF_SUPPORT_SIGNATURE_OFFSET); + + if( l_tempWord != SWIZZLE_4_BYTE(SMF_SELF_SIGNATURE) ) + { + l_incompVector |= SMF_SUPPORT_MISSING_IN_HOMER; + } + + l_tempWord = *(uint32_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_HEADER_SIZE ); + + if( l_tempWord != SWIZZLE_4_BYTE(BRANCH_BE_INST) ) + { + l_incompVector |= SELF_SUPPORT_MISSING_FOR_LE_HYP; + } + + l_tempWord = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_SELF_RESTORE_VER_BYTE ); + + if( l_tempWord < SELF_SAVE_RESTORE_VER ) + { + l_incompVector |= SELF_RESTORE_VER_MISMATCH; + } + + l_tempWord = *(uint8_t *)((uint8_t *)i_pImage + CPMR_HOMER_OFFSET + CPMR_STOP_API_VER_BYTE ); + + if( l_tempWord < STOP_API_CPU_SAVE_VER ) + { + l_incompVector |= IPL_RUNTIME_CPU_SAVE_VER_MISMATCH; + } + + *o_inCompVector = l_incompVector; + + if( l_incompVector ) + { + l_rc = STOP_SAVE_API_IMG_INCOMPATIBLE; + } + + }while(0); + + return l_rc; +} + +} //extern "C" + #ifdef __cplusplus } //namespace stopImageSection ends -} //extern "C" +//----------------------------------------------------------------------------------------------------- + #endif diff --git a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H index ef0d9d1ec..983a3845d 100755 --- a/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H +++ b/src/import/chips/p9/procedures/utils/stopreg/p9_stop_api.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -70,6 +70,26 @@ typedef enum P9_STOP_SPR_PMCR = 884, // core register P9_STOP_SPR_HID = 1008, // core register P9_STOP_SPR_MSR = 2000, // thread register + + //enum members which are project agnostic + PROC_STOP_SPR_DAWR = 180, // thread register + PROC_STOP_SPR_CIABR = 187, // thread register + PROC_STOP_SPR_DAWRX = 188, // thread register + PROC_STOP_SPR_HSPRG0 = 304, // thread register + PROC_STOP_SPR_HRMOR = 313, // core register + PROC_STOP_SPR_LPCR = 318, // thread register + PROC_STOP_SPR_HMEER = 337, // core register + PROC_STOP_SPR_PTCR = 464, // core register + PROC_STOP_SPR_USPRG0 = 496, // thread register + PROC_STOP_SPR_USPRG1 = 497, // thread register + PROC_STOP_SPR_URMOR = 505, // core register + PROC_STOP_SPR_SMFCTRL = 511, // thread register + PROC_STOP_SPR_LDBAR = 850, // thread register + PROC_STOP_SPR_PSSCR = 855, // thread register + PROC_STOP_SPR_PMCR = 884, // core register + PROC_STOP_SPR_HID = 1008, // core register + PROC_STOP_SPR_MSR = 2000, // thread register + } CpuReg_t; /** @@ -94,6 +114,7 @@ typedef enum STOP_SAVE_FAIL = 14, // for internal failure within firmware. STOP_SAVE_SPR_ENTRY_MISSING = 15, STOP_SAVE_SPR_BIT_POS_RESERVE = 16, + STOP_SAVE_API_IMG_INCOMPATIBLE = 18, } StopReturnCode_t; /** @@ -110,7 +131,20 @@ typedef enum P9_STOP_SCOM_RESET = 6, P9_STOP_SCOM_OR_APPEND = 7, P9_STOP_SCOM_AND_APPEND = 8, - P9_STOP_SCOM_OP_MAX = 9 + P9_STOP_SCOM_OP_MAX = 9, + + //enum members which are project agnostic + PROC_STOP_SCOM_OP_MIN = 0, + PROC_STOP_SCOM_APPEND = 1, + PROC_STOP_SCOM_REPLACE = 2, + PROC_STOP_SCOM_OR = 3, + PROC_STOP_SCOM_AND = 4, + PROC_STOP_SCOM_NOOP = 5, + PROC_STOP_SCOM_RESET = 6, + PROC_STOP_SCOM_OR_APPEND = 7, + PROC_STOP_SCOM_AND_APPEND = 8, + PROC_STOP_SCOM_OP_MAX = 9, + } ScomOperation_t; /** @@ -123,7 +157,15 @@ typedef enum P9_STOP_SECTION_EQ_SCOM = 2, P9_STOP_SECTION_L2 = 3, P9_STOP_SECTION_L3 = 4, - P9_STOP_SECTION_MAX = 5 + P9_STOP_SECTION_MAX = 5, + + //enum members which are project agnostic + PROC_STOP_SECTION_MIN = 0, + PROC_STOP_SECTION_CORE_SCOM = 1, + PROC_STOP_SECTION_EQ_SCOM = 2, + PROC_STOP_SECTION_L2 = 3, + PROC_STOP_SECTION_L3 = 4, + PROC_STOP_SECTION_MAX = 5, } ScomSection_t; /** @@ -157,6 +199,21 @@ typedef enum BIT_POS_USPRG1 = 30, } SprBitPositionList_t; +/** + * @brief List of major incompatibilities between API version. + * @note STOP APIs assumes a specific HOMER layout, certain + * level of CME-SGPE hcode and certain version of self-save restore + * binary. A mismatch can break STOP function. + */ + +typedef enum +{ + SMF_SUPPORT_MISSING_IN_HOMER = 0x01, + SELF_SUPPORT_MISSING_FOR_LE_HYP = 0x02, + IPL_RUNTIME_CPU_SAVE_VER_MISMATCH = 0x04, + SELF_RESTORE_VER_MISMATCH = 0x08, +} VersionIncompList_t; + #ifdef __cplusplus extern "C" { @@ -227,13 +284,87 @@ p9_stop_save_cpureg_control( void* i_pImage, const uint64_t i_pir, * @brief initializes self-save region with specific instruction. * @param[in] i_pImage start address of homer image of P9 chip. * @param[in] i_corePos physical core's relative position within processor chip. - * @return STOP_SAVE_SUCCESS SUCCESS if self-save is initialized successfully, + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, * error code otherwise. * @note API is intended only for use case of HOMER build. There is no explicit * effort to support any other use case. */ StopReturnCode_t p9_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); +/** + * @brief creates SCOM restore entry for a given scom adress in HOMER. + * @param i_pImage points to start address of HOMER image. + * @param i_scomAddress address associated with SCOM restore entry. + * @param i_scomData data associated with SCOM restore entry. + * @param i_operation operation type requested for API. + * @param i_section section of HOMER in which restore entry needs to be created. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for creating SCOM restore entry in HOMER. It is agnostic to + * generation of POWER processor. + */ + +StopReturnCode_t proc_stop_save_scom( void* const i_pImage, + const uint32_t i_scomAddress, + const uint64_t i_scomData, + const ScomOperation_t i_operation, + const ScomSection_t i_section ); + +/** + * @brief initializes self save restore region of HOMER. + * @param[in] i_pImage points to base of HOMER image. + * @param[in] i_corePos position of the physical core. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for initializing self restore region in HOMER. It is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_init_cpureg( void* const i_pImage, const uint32_t i_corePos ); + +/** + * @brief enables self save for a given set of SPRs + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg_control( void* i_pImage, + const uint64_t i_pir, + const uint32_t i_saveRegVector ); + +/** + * @brief creates an SPR restore entry in HOMER + * @param[in] i_pImage points to start address of HOMER image. + * @param[in] i_pir PIR value associated with core and thread. + * @param[in] i_saveRegVector bit vector representing the SPRs that needs to be self saved. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note It is an API for enabling self save of SPRs and it is agnostic to + * generation of POWER processor. + */ +StopReturnCode_t proc_stop_save_cpureg( void* const i_pImage, + const CpuReg_t i_regId, + const uint64_t i_regData, + const uint64_t i_pir ); + +/** + * @brief initializes self-save region with specific instruction. + * @param[in] i_pImage start address of homer image. + * @param[in] i_corePos physical core's relative position within processor chip. + * @return STOP_SAVE_SUCCESS if self-save is initialized successfully, + * error code otherwise. + * @note API is project agnostic and is intended only for use case of HOMER build. + * There is no explicit effort to support any other use case. + */ +StopReturnCode_t proc_stop_init_self_save( void* const i_pImage, const uint32_t i_corePos ); + +/** + * @brief verifies if API is compatible of current HOMER image. + * @param[in] i_pImage points to the start of HOMER image of P9 chip. + * @param[out] o_inCompVector list of incompatibilities found. + * @return STOP_SAVE_SUCCESS if if API succeeds, error code otherwise. + */ +StopReturnCode_t proc_stop_api_discover_capability( void* const i_pImage, uint64_t* o_inCompVector ); + #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 1c2df1354..1a9b27e47 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -116,6 +116,40 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_CP_FILTER_100MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True where CP refclock is expected to be 100 MHz + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_I2CM_INTERNAL_CLK_DIV2</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + I2CM internal clock divider is div2 , not div4 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NOT_DD1_FBC_AND_ALINK</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -149,6 +183,25 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_XBUS_COMPRESSION_WORKAROUND</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Modifies calibration gain targets and moves common mode to improve + DAC linearity and compression. + Enable only for Axone. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_NO_NPU2_FIR</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -1212,13 +1265,6 @@ <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> - <chip> - <name>ENUM_ATTR_NAME_AXONE</name> - <ec> - <value>0x10</value> - <test>GREATER_THAN_OR_EQUAL</test> - </ec> - </chip> </chipEcFeature> </attribute> <!-- ******************************************************************** --> @@ -3118,6 +3164,23 @@ </chip> </chipEcFeature> </attribute> + <!-- ********************************************************************* --> +<attribute> + <id>ATTR_CHIP_EC_FEATURE_NMMU_AX1_ISS768_FIX_DIS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + NMMU disables seg fault generation for radix access to DR=1, HV=1 with lpid !=0. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_NMMU_PWC_DIS_DD2</id> @@ -3311,10 +3374,11 @@ <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW438727</id> - <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP,TARGET_TYPE_PROC_CHIP</targetType> <description> - Anything NDD20+,CDD10+: Disable clockgating to allow correct - errors to be reported in ODL c_err_rpt and other error capture + Anything NDD20+,CDD10+,ADD10+: Disable clockgating to allow correct + errors to be reported in ODL c_err_rpt and other error capture. + Axone see: HW481539 </description> <chipEcFeature> <chip> @@ -3331,6 +3395,13 @@ <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> </chipEcFeature> </attribute> <!-- ******************************************************************** --> @@ -5055,6 +5126,37 @@ </attribute> <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW499047</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> + <description> + HW499047 - SMT2 prefetch issue + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x22</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x11</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW420860</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -5329,7 +5431,7 @@ <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_CORE_SMF_SETUP</id> - <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> <description> Core inits for enabling secure memory facility </description> @@ -6926,6 +7028,13 @@ <test>GREATER_THAN_OR_EQUAL</test> </ec> </chip> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> </chipEcFeature> </attribute> @@ -7749,7 +7858,24 @@ </chip> </chipEcFeature> </attribute> - + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_FBC_SETTINGS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Fabric settings that are in Axone only + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW412371</id> <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_PROC_CHIP</targetType> @@ -8011,6 +8137,7 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> <attribute> <id>ATTR_CHIP_EC_FEATURE_HW426816</id>> @@ -8042,6 +8169,30 @@ </chip> </chipEcFeature> </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW515286</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Mask Particular type of NPU OTL UE to prevent unwanted xstops and/or fences. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> <!-- ******************************************************************** --> <!-- NOTE: This attribute is used in an initfile to qualify the contents of a GPTR ring. There is special processing in place to move the @@ -8848,4 +8999,156 @@ </chipEcFeature> </attribute> <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW476692</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + HW476692 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_GEMINI_OVERRUN</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Setup Memory controller to hold back too many operations from being passed to Gemini + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_MMU</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Bumpy Toothpaste fix not enabled in Axone + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_HW441771</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Bumpy Toothpaste fix not enabled in Axone + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + The DL half width backoff enable bit in DL_CONFIG0_CFG (bit 47) + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_EXPLORER</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_GEMINI_MENTERP_WORKAROUND</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Bypass MENTERP register read/writes on gemini due to FW bug + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_GEMINI</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_GEMINI_MDI_ERROR</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Setup Memory controller to always deliver MDI=1 by default due to Gemini bug + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_GEMINI</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_GEMINI_OMI_SETUP_CONFIG_WORKAROUND</id> + <targetType>TARGET_TYPE_OCMB_CHIP</targetType> + <description> + Setup config registers for gemini in exp_omi_setup + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_GEMINI</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_AXONE_HW476620</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Sim fail defect number HW476620 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_AXONE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> </attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml index 6f8b366f1..a64167bb3 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/freq_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -39,6 +39,17 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_FREQ_DPLL_REFCLOCK_KHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of the processor DPLL refclock in kHz. + </description> + <valueType>uint32</valueType> + <platInit/> + <default>133333</default> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_FREQ_MEM_REFCLOCK</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 0a3c2e2b4..fd10554ce 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1178,18 +1178,6 @@ </attribute> <attribute> - <id>ATTR_MSS_MEM_PORT_POS_OF_FAIL_THROTTLE</id> - <targetType>TARGET_TYPE_SYSTEM</targetType> - <description> - This is the fapi position of the port that failed to calculate - memory throttles given the passed in watt target and or utilization - </description> - <initToZero></initToZero> - <valueType>uint64</valueType> - <writeable/> - </attribute> - - <attribute> <id>ATTR_MSS_MEM_M_DRAM_CLOCKS</id> <targetType>TARGET_TYPE_MCS</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index 078f79284..ae6bbb47e 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -24,6 +24,22 @@ <!-- IBM_PROLOG_END_TAG --> <attributes> + <attribute> + <id>ATTR_MSS_MRW_NVDIMM_SLOT_POSITION</id> + <targetType>TARGET_TYPE_DIMM</targetType> + <description> + The position of a dimm is based on which mca it is + associated with and which drop behind that mca, with + 16 dimms possible per processor socket. The formula is: + [processor position with no gaps, i.e. 0,1,2,3]*16 + + [mca position on this processor * 2] + [dimm location behind this mca] + </description> + <valueType>uint8</valueType> + <default>0xFF</default> + <platInit/> + <mrwHide/> + <mssAccessorName>mrw_nvdimm_slot_position</mssAccessorName> + </attribute> <attribute> <id>ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG</id> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index 2967e614a..7a2c4aa95 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -50,15 +50,20 @@ <id>ATTR_FREQ_MCA_MHZ</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> - The frequency of the memory controller channel. In synchronous mode, - this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set - per pair of memory channels if operating in asynchronous mode, - but this configuration is not anticipated. This clock drives the MCU queues, - and all the associated logic that drives the inputs to the DMI and reads - its outputs. + The frequency of the memory controller channel. + NIMBUS: In synchronous mode, this is equivalent to ATTR_FREQ_PB_MHZ. This + may be independently set per pair of memory channels if operating in + asynchronous mode, but this configuration is not anticipated. + CUMULUS: This clock drives the MCU queues, and all the associated logic + that drives the inputs to the DMI and reads its outputs. + AXONE: This is tied to the OMI frequency (MCAx16=OMI). </description> <valueType>uint32</valueType> <enum> + 1200 = 1200, + 1333 = 1333, + 1466 = 1466, + 1600 = 1600, 2000 = 2000, 2400 = 2400 </enum> @@ -66,6 +71,38 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_FREQ_OMI_MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + The frequency of the OMI channel. + </description> + <valueType>uint32</valueType> + <enum> + 19200 = 19200, + 21330 = 21330, + 23460 = 23460, + 25600 = 25600 + </enum> + <platInit/> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_OMI_PLL_VCO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Should the 20GHz or the 26GHz OMI PLL VCO be used. + </description> + <valueType>uint8</valueType> + <enum> + 20G = 0, + 26G = 1 + </enum> + <platInit/> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_FREQ_O_MHZ</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -312,6 +349,7 @@ 1 = CAPI 2.0 2 = NV 2.0 3 = OPENCAPI + 4 = Not Wired Provided by the MRW. </description> <valueType>uint8</valueType> @@ -319,7 +357,8 @@ SMP = 0x0, CAPI = 0x1, NV = 0x2, - OCAPI = 0x3 + OCAPI = 0x3, + NOT_WIRED=0x4 </enum> <platInit/> </attribute> @@ -349,12 +388,16 @@ 0 = default = SMP 1 = CAPI 2.0 2 = NV 2.0 + 3 = OPENCAPI + 4 = Not Wired </description> <valueType>uint8</valueType> <enum> SMP = 0x0, CAPI = 0x1, - NV = 0x2 + NV = 0x2, + OCAPI = 0x3, + NOT_WIRED=0x4 </enum> <array>4</array> <writeable/> @@ -1069,11 +1112,11 @@ An 8 bit vector that would be a designation of which MC (Nimbus MCA or Cumulus MI) are involved in the group. So the bits would represent - Nimbus Cumulus - Bit 0 MCA0 MI0 - Bit 1 MCA1 MI1 + Nimbus Cumulus Axone + Bit 0 MCA0 MI0 MCC0 + Bit 1 MCA1 MI1 MCC1 ..... - Bit 7 MCA7 MI7 + Bit 7 MCA7 MI7 MCC7 Set by p9_mss_eff_grouping </description> <valueType>uint8</valueType> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml index fc9efabf5..849270429 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_io_obus_attributes.xml @@ -93,6 +93,22 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_IO_OBUS_LINK_SPARE_MARK</id> + <targetType>TARGET_TYPE_OBUS</targetType> + <description> + Used to save indication that a spare lane has been deployed during + runtime link recovery retrain sequence. This sparing will be posted + into the DL FIR after all other FIR clearing/unmasking has been + performed in the link recovery sequence. Index 0 tracks the even half + link, index 1 the odd half link. + </description> + <array>2</array> + <valueType>uint8</valueType> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_IO_OBUS_LANE_PDWN</id> <targetType>TARGET_TYPE_OBUS</targetType> <description> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml index 920e0dcf1..88bd4192b 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_setup_bars_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -167,6 +167,20 @@ <mrwHide/> </attribute> <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NPU MMIO (stack2) BAR enable + creator: platform + consumer: p9_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************* --> <attribute> <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> <targetType>TARGET_TYPE_SYSTEM</targetType> @@ -185,9 +199,71 @@ </attribute> <!-- ********************************************************************* --> <attribute> - <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <id>ATTR_PROC_NPU0_MMIO_BAR_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> - <description>NPU MMIO (stack2) BAR enable + <description>NPU0 MMIO BAR enable + creator: platform + consumer: p9_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>NPU MMIO BAR + creator: platform + consumer: p9_setup_bars + firmware notes: + Defines 16MB range mapped to NPU0 registers + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- Bits 15:39 of the RA + (excludes system/memory select/group/chip fields) + </description> + <valueType>uint64</valueType> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NPU1 MMIO BAR enable + creator: platform + consumer: p9_setup_bars + firmware notes: none + </description> + <valueType>uint8</valueType> + <enum>DISABLE = 0x0, ENABLE = 0x1</enum> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>NPU1 MMIO BAR + creator: platform + consumer: p9_setup_bars + firmware notes: + Defines 16MB range mapped to NPU1 registers + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- Bits 15:39 of the RA + (excludes system/memory select/group/chip fields) + </description> + <valueType>uint64</valueType> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>NPU2 MMIO BAR enable creator: platform consumer: p9_setup_bars firmware notes: none @@ -199,6 +275,104 @@ </attribute> <!-- ********************************************************************* --> <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>NPU2 MMIO BAR + creator: platform + consumer: p9_setup_bars + firmware notes: + Defines 16MB range mapped to NPU2 registers + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- Bits 15:39 of the RA + (excludes system/memory select/group/chip fields) + </description> + <valueType>uint64</valueType> + <platInit/> + <mrwHide/> + </attribute> + <!-- ********************************************************************** --> + <attribute> + <id>ATTR_PROC_NPU0_PRI_CONFIG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + NPU0 NTL Private Register Interface (PRI) Configuration register settings + Array 0 = SM0 value + 1 = SM1 value + 2 = SM2 value + 3 = SM3 value + Bits of values: + 0 PRI_CONFIG_DISABLE: Disable + 1 Disable (this will disable NTL from decoding the NDL register space) + 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access + 00 = NDL 0 + 01 = NDL 1 + 10 = NDL 2 + 11 = NDL 3 + 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space + 00 = Decode PHY0 register space + 01 = Decode PHY1 register space + 1- = Do not decode any PHY register space + </description> + <valueType>uint8</valueType> + <array>4</array> + <platInit/> + </attribute> + <!-- ********************************************************************** --> + <attribute> + <id>ATTR_PROC_NPU1_PRI_CONFIG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + NPU1 NTL Private Register Interface (PRI) Configuration register settings + Array 0 = SM0 value + 1 = SM1 value + 2 = SM2 value + 3 = SM3 value + Bits of values: + 0 PRI_CONFIG_DISABLE: Disable + 1 Disable (this will disable NTL from decoding the NDL register space) + 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access + 00 = NDL 0 + 01 = NDL 1 + 10 = NDL 2 + 11 = NDL 3 + 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space + 00 = Decode PHY0 register space + 01 = Decode PHY1 register space + 1- = Do not decode any PHY register space + </description> + <valueType>uint8</valueType> + <array>4</array> + <platInit/> + </attribute> + <!-- ********************************************************************** --> + <attribute> + <id>ATTR_PROC_NPU2_PRI_CONFIG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + NPU2 NTL Private Register Interface (PRI) Configuration register settings + Array 0 = SM0 value + 1 = SM1 value + 2 = SM2 value + 3 = SM3 value + Bits of values: + 0 PRI_CONFIG_DISABLE: Disable + 1 Disable (this will disable NTL from decoding the NDL register space) + 1:2 PRI_CONFIG_NDL: NDL indication sent in the PRI Read/Write access + 00 = NDL 0 + 01 = NDL 1 + 10 = NDL 2 + 11 = NDL 3 + 3:4 PRI_CONFIG_PHY: Indicates if NTL should decode a PHY register space + 00 = Decode PHY0 register space + 01 = Decode PHY1 register space + 1- = Do not decode any PHY register space + </description> + <valueType>uint8</valueType> + <array>4</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> <id>ATTR_PROC_PSI_BRIDGE_BAR_ENABLE</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>PSI Bridge BAR enable diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9a_io_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9a_io_attributes.xml index 70ba79239..dd982c93f 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9a_io_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9a_io_attributes.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -31,7 +31,7 @@ </targetType> <description> An OMI target's relative logical postion to its OMIC parent target. - + pos | DL_GROUP_POS -----+-------------- 4 | 0 @@ -48,7 +48,7 @@ 15 | 0 10 | 1 11 | 2 - 8 | 0 + 8 | 0 9 | 1 </description> @@ -63,7 +63,7 @@ TARGET_TYPE_OMI </targetType> <description> - An OMI target's logical DL number + An OMI target's logical DL number pos | DL_NUM -----+-------------- @@ -90,4 +90,17 @@ <default>0xFF</default><!-- Ensures platform explicitly puts a valid number in here --> </attribute> <!-- ******************************************************************************** --> + <attribute> + <id>ATTR_OCMB_COUNTER</id> + <targetType> + TARGET_TYPE_OCMB_CHIP + </targetType> + <description> + Tracks the sequence id for OCMB command transactions. The platform is + expected to guarantee a unique value on each read. + </description> + <valueType>uint32</valueType> + <platInit/> + <default>0</default> + </attribute> </attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml new file mode 100644 index 000000000..b1eafcf0a --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml @@ -0,0 +1,55 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9a_omi_train.xml $ --> +<!-- --> +<!-- OpenPOWER HostBoot Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2019 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- --> +<!-- @file p9a_omi_train.xml --> +<!-- @brief Attribute xml for p9a_omi_train --> +<!-- --> +<!-- *HWP HWP Owner: Devon Baughen <devon.baughen1@ibm.com> --> +<!-- *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> --> +<!-- *HWP FW Owner: Daniel Crowell <dcrowell@us.ibm.com> --> +<!-- *HWP Team: Memory --> +<!-- *HWP Level: 2 --> +<!-- *HWP Consumed by: FSP:HB --> +<!-- --> + +<attributes> + + <attribute> + <id>ATTR_OMI_DL_LN_REV_ENABLE</id> + <targetType>TARGET_TYPE_OMI</targetType> + <description> + The DL lane reversible enable bit in DL_CONFIG0_CFG (bit 38) + </description> + <valueType>uint8</valueType> + <enum> + ENABLED = 0x01, + DISABLED = 0x00 + </enum> + <default>0x01</default> + <platInit/> + <mssAccessorName>omi_dl_ln_rev_enable</mssAccessorName> + </attribute> + +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 92286ce9a..c77fbcb99 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -753,7 +753,10 @@ <attribute> <id>ATTR_MC_PLL_BUCKET</id> <targetType>TARGET_TYPE_SYSTEM</targetType> - <description>MC pll bucket selection in async mode for Cumulus</description> + <description>MC pll bucket selection. + See MEM_PLL_FREQ_LIST for Cumulus. + See OMI_PLL_FREQ_LIST for Axone. + </description> <valueType>uint8</valueType> <platInit/> </attribute> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml index ef8672bf3..a8d4a08f6 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -1515,7 +1515,7 @@ </description> <valueType>uint8</valueType> <initToZero/> - <array>61</array> + <array>135</array> <platInit/> </attribute> <!-- ********************************************************************* --> @@ -2265,6 +2265,7 @@ </enum> <platInit/> <initToZero/> + <mrwHide/> </attribute> <!-- ********************************************************************* --> <attribute> @@ -2286,6 +2287,7 @@ </enum> <platInit/> <initToZero/> + <mrwHide/> </attribute> <!-- ********************************************************************* --> <attribute> @@ -2303,6 +2305,7 @@ <valueType>uint64</valueType> <platInit/> <initToZero/> + <mrwHide/> </attribute> <!-- ********************************************************************* --> <attribute> diff --git a/src/import/chips/p9/procedures/xml/error_info/ddimm_get_efd.xml b/src/import/chips/p9/procedures/xml/error_info/ddimm_get_efd.xml index f4c7862fb..cb2a65d7f 100644..100755 --- a/src/import/chips/p9/procedures/xml/error_info/ddimm_get_efd.xml +++ b/src/import/chips/p9/procedures/xml/error_info/ddimm_get_efd.xml @@ -159,7 +159,6 @@ <description>DMB manufacturer ID is not the expected ID and therefore not supported.</description> <ffdc>DMB_MFG_ID</ffdc> - <ffdc>EXPECTED</ffdc> <ffdc>OCMB_CHIP_TARGET</ffdc> <ffdc>VPD_TYPE</ffdc> <ffdc>DDR_TYPE</ffdc> @@ -192,7 +191,6 @@ <description>DMB revision is not the expected revision and therefore not supported.</description> <ffdc>DMB_REVISION</ffdc> - <ffdc>EXPECTED</ffdc> <ffdc>OCMB_CHIP_TARGET</ffdc> <ffdc>VPD_TYPE</ffdc> <ffdc>DDR_TYPE</ffdc> @@ -221,6 +219,29 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> + <rc>RC_DDIMM_UNSUPPORTED_FREQUENCY</rc> + <description>Chosen frequency not supported by this DDIMM</description> + <ffdc>UNSUPPORTED_FREQ</ffdc> + <ffdc>SUPPORTED_FREQS</ffdc> + <ffdc>OCMB_CHIP_TARGET</ffdc> + <ffdc>VPD_TYPE</ffdc> + <ffdc>DDR_TYPE</ffdc> + <!-- This is always a code bug. --> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> + <!-- It could also be bogus SPD content --> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>OCMB_CHIP_TARGET</refTarget> + </hw> + <priority>LOW</priority> + </callout> + </hwpError> + <!-- ********************************************************************* --> + <hwpError> <rc>RC_DDIMM_GET_EFD_UNSUPPORTED_FREQUENCY</rc> <description>Invalid Frequency. Valid values are 12800, 14930, 17060, 19200, 21330, 23460 and 25600.</description> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_get_mem_vpd_keyword.xml b/src/import/chips/p9/procedures/xml/error_info/p9_get_mem_vpd_keyword.xml index 48be558fe..a9372ceda 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_get_mem_vpd_keyword.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_get_mem_vpd_keyword.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2017 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -128,15 +128,22 @@ <ffdc>MAPROW8</ffdc> <ffdc>MAPROW9</ffdc> <!-- Should use a variable ffdc for the rows but that isn't supported --> + <!-- Most likely scenario is some bad configs --> <callout> - <hw> - <hwid>VPD_PART</hwid> - <refTarget>MCS_TARGET</refTarget> - </hw> + <procedure>MEMORY_PLUGGING_ERROR</procedure> <priority>HIGH</priority> </callout> + <!-- Next would be a code issue since we have a copy of MEMD in FW --> <callout> <procedure>CODE</procedure> + <priority>MEDIUM</priority> + </callout> + <!-- Finally it could be downlevel MEMD VPD in the backplane --> + <callout> + <hw> + <hwid>VPD_PART</hwid> + <refTarget>MCS_TARGET</refTarget> + </hw> <priority>LOW</priority> </callout> </hwpError> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml index d7bb833cd..b177f8d18 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_draminit_training.xml @@ -658,20 +658,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_RANK</rc> - <description> - Invalid rank passed into function - </description> - <ffdc>FUNCTION</ffdc> - <ffdc>RANK</ffdc> - <ffdc>MCA_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> -</hwpError> - -<hwpError> <rc>RC_MSS_INVALID_RANK_PAIR</rc> <description> Invalid rank pair passed into function diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml index 9d9aea174..8569812a9 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -37,18 +37,6 @@ <hwpErrors> <hwpError> - <rc>RC_MSS_INVALID_FINE_REFRESH_MODE</rc> - <description> - Invalid fine refresh mode received from the mrw - </description> - <ffdc>FINE_REF_MODE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_FINE_REFRESH_MODE_WITH_TEMP_REFRESH_MODE_ENABLED</rc> <description> Invalid fine refresh mode received due to temperature refresh mode being enabled @@ -109,18 +97,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_CAST_CALC_NCK</rc> - <description>Invalid cast or calculation for calc_nck</description> - <ffdc>TIMING_PS</ffdc> - <ffdc>NCK_NS</ffdc> - <ffdc>CORRECTION_FACTOR</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_SPD_SLAVE_RANKS</rc> <description> Seems logical ranks are not master ranks* slave ranks. @@ -270,20 +246,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_FREQ_PASSED_IN</rc> - <description> - An invalid Freq value has been set - </description> - <ffdc>FREQ</ffdc> - <ffdc>FUNCTION</ffdc> - <ffdc>DIMM_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_ERROR_CREATING_EFF_CONFIG_DIMM_OBJECT</rc> <description> Failed to create a dimm object, probably due to bad data from SPD (ie code doesn't support) @@ -395,19 +357,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_REFRESH_RATE_REQUEST</rc> - <description> - Invalid refresh request rate received. - Possibly due to bad MRW setting for ATTR_MSS_MRW_REFRESH_RATE_REQUEST. - </description> - <ffdc>REFRESH_RATE_REQUEST</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_FINE_REFRESH</rc> <description> Incorrect FINE Refresh Mode received @@ -420,72 +369,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_FAILED_TO_FIND_TRFC</rc> - <description> - Unable to find tRFC (ps) from map with SDRAM density key - </description> - <ffdc>SDRAM_DENSITY</ffdc> - <ffdc>REFRESH_MODE</ffdc> - <callout> - <target>DIMM_TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_PAGE_SIZE</rc> - <description> - Invalid page size - </description> - <ffdc>DRAM_WIDTH</ffdc> - <callout> - <procedure>MEMORY_PLUGGING_ERROR</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>DIMM_TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DRAM_WIDTH</rc> - <description> - Code only supports x4 and x8 drams at this time - </description> - <ffdc>DRAM_WIDTH</ffdc> - <callout> - <procedure>MEMORY_PLUGGING_ERROR</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>DIMM_TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_RTT_PARK_CALCULATIONS</rc> <description> Calculated the rtt_park_index into the VPD attribute incorrectly @@ -522,23 +405,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_VPD_KEYWORD_MAX</rc> - <description> - VPD keyword is too big for space allocated for it. - </description> - <ffdc>MAX</ffdc> - <ffdc>ACTUAL</ffdc> - <ffdc>KEYWORD</ffdc> - <callout> - <hw> - <hwid>VPD_PART</hwid> - <refTarget>MCS_TARGET</refTarget> - </hw> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_OFFSET_WR_VREF_OUT_OF_RANGE</rc> <description> The offset composite range is out of range diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config_thermal.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config_thermal.xml index 5de51418f..a156088c2 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config_thermal.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_eff_config_thermal.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -34,182 +34,6 @@ <!-- --> <hwpErrors> - <hwpError> - <rc>RC_MSS_NO_POWER_THERMAL_ATTR_FOUND</rc> - <description> - There was no match or value found in decoding the power thermal attributes - </description> - <ffdc>GENERATED_KEY</ffdc> - <ffdc>FUNCTION</ffdc> - <ffdc>DIMM_TARGET</ffdc> - <ffdc>SIZE</ffdc> - <ffdc>DRAM_GEN</ffdc> - <ffdc>DIMM_TYPE</ffdc> - <ffdc>DRAM_WIDTH</ffdc> - <ffdc>DRAM_DENSITY</ffdc> - <ffdc>STACK_TYPE</ffdc> - <ffdc>MFGID</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_POWER_THERMAL_ENCODE_ERROR</rc> - <description> - There was no match or value found in encoding the power thermal attributes - </description> - <ffdc>DIMM_TARGET</ffdc> - <ffdc>ATTR</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_POWER_THERMAL_DECODE_ERROR</rc> - <description> - There was no match or value found in decoding the power thermal attributes - </description> - <ffdc>DIMM_TARGET</ffdc> - <ffdc>ATTR</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_POWER_INTERCEPT_NOT_SET</rc> - <description> - The attribute ATTR_MSS_TOTAL_POWER_INTERCEPT was not set and equals 0 - </description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_POWER_SLOPE_NOT_SET</rc> - <description> - The attribute ATTR_MSS_TOTAL_POWER_INTERCEPT was not set and equals 0 - </description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_NO_DATABUS_UTILIZATION</rc> - <description> - There are 2 DIMMS on the port but both have 0 databus utilization - </description> - <ffdc>PORT_DATABUS_UTIL</ffdc> - <ffdc>DIMM_COUNT</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_CALC_POWER_CURVE_DIVIDE_BY_ZERO</rc> - <description> - Denominator equals 0 - </description> - <ffdc>PORT_DATABUS_UTIL</ffdc> - <ffdc>UTIL_CONVERSION</ffdc> - <ffdc>IDLE_UTIL</ffdc> - <ffdc>RESULT</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_NO_PORT_POWER_LIMIT</rc> - <description> - Got 0 when calculating port power limit. - Either no dimms or attribute MEM_WATT_TARGET wasn't set - </description> - <ffdc>COUNT_DIMMS</ffdc> - <ffdc>PORT_POWER_LIMIT</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_NO_PORT_POWER</rc> - <description> - Got 0 when calculating port power limits using the DIMMs databus utilization - </description> - <ffdc>COUNT_DIMMS</ffdc> - <ffdc>MAX_UTILIZATION_DIMM_0</ffdc> - <ffdc>MAX_UTILIZATION_DIMM_1</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_M_DRAM_CLOCKS_EQUALS_ZERO</rc> - <description> - ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS was not set and equals zero - </description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_CALC_PORT_POWER_EXCEEDS_MAX</rc> - <description> - The calculated port power from equalizing throttles exceeds the maximum allowed power - </description> - <ffdc>CALCULATED_PORT_POWER</ffdc> - <ffdc>MAX_POWER_ALLOWED</ffdc> - <ffdc>PORT_POS</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <childTargets> - <parent>MCA_TARGET</parent> - <childType>TARGET_TYPE_DIMM</childType> - </childTargets> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <childTargets> - <parent>MCA_TARGET</parent> - <childType>TARGET_TYPE_DIMM</childType> - </childTargets> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_SLOT_UTIL_EXCEEDS_PORT</rc> - <description> - The memory throttle per slot (DIMM) exceeds the allowed throttle for the port - </description> - <ffdc>SLOT_UTIL</ffdc> - <ffdc>PORT_UTIL</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> <rc>RC_MSS_SPLIT_UTIL_CALC_ERROR</rc> <description> @@ -225,17 +49,6 @@ </callout> </hwpError> - <hwpError> - <rc>RC_MSS_OUTPUT_OVERFLOW_CALC_UTIL</rc> - <description> - Type of output variable is not large enough for the calculations - </description> - <ffdc>RESULT</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> <hwpError> <rc>RC_MSS_DIMM_COUNT_EXCEEDS_VMEM_REGULATOR_LIMIT</rc> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml index 4a1b6f51f..e2a9bf1ab 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_freq.xml @@ -127,32 +127,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_INVALID_VPD_FREQ_LIST_PASSED</rc> - <description> - Wrong size vector passed into limit_freq_by_vpd function - </description> - <ffdc>SIZE</ffdc> - <ffdc>EXPECTED</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_FREQ_LIST_PASSED</rc> - <description> - Wrong size vector passed into frequency scoreboard function - </description> - <ffdc>SIZE</ffdc> - <ffdc>EXPECTED</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_ERROR_FINDING_DIMM_SPEED_MAP</rc> <description> Empty MCBIST target vector found when constructing dimm speed mapping @@ -204,22 +178,6 @@ </callout> </hwpError> - - <hwpError> - <rc>RC_MSS_MAX_FREQ_ATTR_SIZE_CHANGED</rc> - <description> - Number of entries for MSS_MRW_MAX_FREQ attribute from VPD has changed without updating the code - Asserted because direct accesses to array - </description> - <ffdc>ACTUAL_SIZE</ffdc> - <ffdc>SUPPOSED_SIZE</ffdc> - <ffdc>MCA_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> <rc>RC_MSS_MRW_FREQ_MAX_FREQ_EMPTY_SET</rc> <description> @@ -286,50 +244,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_TOO_MANY_DIMMS_ON_PORT</rc> - <description>There seem to be too many dimms on the port</description> - <ffdc>DIMM_COUNT</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <childTargets> - <parent>PORT_TARGET</parent> - <childType>TARGET_TYPE_DIMM</childType> - </childTargets> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_TOO_MANY_PRIMARY_RANKS_ON_DIMM</rc> - <description>There seem to be too many primary ranks seen on the dimm</description> - <ffdc>RANK_COUNT</ffdc> - <callout> - <target>DIMM_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <gard> - <target>DIMM_TARGET</target> - </gard> - </hwpError> - - <hwpError> - <rc>RC_MSS_FREQ_INDEX_TOO_LARGE</rc> - <description>Error calculating the index into max_freq array</description> - <ffdc>INDEX</ffdc> - <ffdc>NUM_MAX_FREQS</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_FREQ_TO_NEST_FREQ_RATIO_TOO_LARGE</rc> <description> Case when mss_freq to nest freq is above the maximum allowed. diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml index 0d7d6c791..1625e16f0 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_lib.xml @@ -163,7 +163,7 @@ </registerFfdc> <hwpError> - <rc>RC_MSS_CCS_READ_MISCOMPARE</rc> + <rc>RC_MSS_NIMBUS_CCS_READ_MISCOMPARE</rc> <description> CCS reports a read miscompare. </description> @@ -186,7 +186,7 @@ </hwpError> <hwpError> - <rc>RC_MSS_CCS_UE_SUE</rc> + <rc>RC_MSS_NIMBUS_CCS_UE_SUE</rc> <description> CCS reports a UE or SUE in the CCS program array Chould be an indicator of corruption in the CCS program @@ -210,7 +210,7 @@ </hwpError> <hwpError> - <rc>RC_MSS_CCS_CAL_TIMEOUT</rc> + <rc>RC_MSS_NIMBUS_CCS_CAL_TIMEOUT</rc> <description> CCS reports never getting a response back from the PHY on a calibration command </description> @@ -233,7 +233,7 @@ </hwpError> <hwpError> - <rc>RC_MSS_CCS_HUNG</rc> + <rc>RC_MSS_NIMBUS_CCS_HUNG</rc> <description> Software reported that the machine is not seeing the CCS finish in the alloted time </description> @@ -282,83 +282,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_MCBIST_TIMEOUT</rc> - <description> - MCBIST program failed to return in the time allowed - Software timer, MCBIST has not finished in the time allowed - </description> - <collectRegisterFfdc> - <id>REG_FFDC_MSS_CCS_FAILURE</id> - <target>MCBIST_TARGET</target> - <targetType>TARGET_TYPE_MCBIST</targetType> - </collectRegisterFfdc> - <callout> - <target>MCBIST_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>MCBIST_TARGET</target> - </deconfigure> - <gard> - <target>MCBIST_TARGET</target> - </gard> - </hwpError> - - <hwpError> - <rc>RC_MSS_MCBIST_DATA_FAIL</rc> - <description> - MCBIST program appeared to have failed, but set conflicting bits in the status register - </description> - <ffdc>STATUS_REGISTER</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_MSS_CCS_FAILURE</id> - <target>MCBIST_TARGET</target> - <targetType>TARGET_TYPE_MCBIST</targetType> - </collectRegisterFfdc> - <callout> - <target>MCBIST_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>MCBIST_TARGET</target> - </deconfigure> - <gard> - <target>MCBIST_TARGET</target> - </gard> - </hwpError> - - <hwpError> - <rc>RC_MSS_MCBIST_UNKNOWN_FAILURE</rc> - <description>MCBIST program reported a failure but no error status was found</description> - <ffdc>STATUS_REGISTER</ffdc> - <collectRegisterFfdc> - <id>REG_FFDC_MSS_CCS_FAILURE</id> - <target>MCBIST_TARGET</target> - <targetType>TARGET_TYPE_MCBIST</targetType> - </collectRegisterFfdc> - <callout> - <target>MCBIST_TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>MCBIST_TARGET</target> - </deconfigure> - <gard> - <target>MCBIST_TARGET</target> - </gard> - </hwpError> - - <hwpError> - <rc>RC_MSS_MCBIST_PROGRAM_TOO_BIG</rc> - <description>MCBIST program larger than currently supported size</description> - <ffdc>PROGRAM_LENGTH</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_APB_INVALID_ADDRESS</rc> <description>PHY APB interface is reporting an invalid address was read or written</description> <ffdc>PORT_POSITION</ffdc> @@ -566,19 +489,8 @@ </hwpError> <hwpError> - <rc>RC_MSS_SRE_MCA_OUT_OF_RANGE</rc> - <description>Indicates a MCA passed to the NVDIMM sre code is out of range</description> - <ffdc>PROC_TARGET</ffdc> - <ffdc>MCA_POS</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_RESETN_MCA_OUT_OF_RANGE</rc> - <description>Indicates a MCA passed to the NVDIMM resetn code is out of range</description> + <rc>RC_MSS_SELECT_PORT_MCA_OUT_OF_RANGE</rc> + <description>Indicates a MCA is out of range</description> <ffdc>PROC_TARGET</ffdc> <ffdc>MCA_POS</ffdc> <callout> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml index b18d42520..09c2bc180 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_memdiags.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2016,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2016,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -84,117 +84,112 @@ </registerFfdc> <hwpError> - <rc>RC_MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN</rc> - <description>An error was caused by the last MCBIST pattern</description> - <ffdc>STATUS0</ffdc> - <ffdc>STATUS1</ffdc> + <rc>RC_MSS_MCBIST_TIMEOUT</rc> + <description> + MCBIST program failed to return in the time allowed + Software timer, MCBIST has not finished in the time allowed + </description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> </hwpError> <hwpError> - <rc>RC_MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN</rc> - <description>A miscompare error was caused by the last MCBIST pattern</description> - <ffdc>PORT</ffdc> - <ffdc>SUBTEST</ffdc> + <rc>RC_MSS_MCBIST_DATA_FAIL</rc> + <description> + MCBIST program appeared to have failed, but set conflicting bits in the status register + </description> + <ffdc>STATUS_REGISTER</ffdc> <collectRegisterFfdc> - <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <id>REG_FFDC_MSS_CCS_FAILURE</id> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> </hwpError> <hwpError> - <rc>RC_MSS_MEMDIAGS_INVALID_PATTERN_INDEX</rc> - <description>An invalid pattern index was passed to the pattern loader</description> - <ffdc>INDEX</ffdc> + <rc>RC_MSS_MCBIST_UNKNOWN_FAILURE</rc> + <description>MCBIST program reported a failure but no error status was found</description> + <ffdc>STATUS_REGISTER</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_MCBIST</targetType> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> + <deconfigure> + <target>MC_TARGET</target> + </deconfigure> + <gard> + <target>MC_TARGET</target> + </gard> </hwpError> <hwpError> - <rc>RC_MSS_MEMDIAGS_ERROR_CHANGING_RANDOM_SEED</rc> - <description>Attempting to change to a 24b random data seed which does not exist</description> - <ffdc>RANDOM_SEED</ffdc> + <rc>RC_MSS_MEMDIAGS_ERROR_IN_LAST_PATTERN</rc> + <description>An error was caused by the last MCBIST pattern</description> + <ffdc>STATUS0</ffdc> + <ffdc>STATUS1</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_MCBIST</targetType> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> <hwpError> - <rc>RC_MSS_INVALID_GALOIS_TO_SYMBOL</rc> - <description> An invalid galois code was found</description> - <ffdc>GALOIS</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_SYMBOL_FOR_GALOIS</rc> - <description> An invalid symbol was passed to symbol_to_galois</description> - <ffdc>SYMBOL</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DQ_TO_SYMBOL</rc> - <description> An invalid DQ bit index received to map to Galois symbol</description> - <ffdc>DQ</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_SYMBOL_TO_DQ</rc> - <description> An invalid symbol received to map to DQ bit index</description> - <ffdc>SYMBOL</ffdc> + <rc>RC_MSS_MEMDIAGS_COMPARE_ERROR_IN_LAST_PATTERN</rc> + <description>A miscompare error was caused by the last MCBIST pattern</description> + <ffdc>PORT</ffdc> + <ffdc>SUBTEST</ffdc> + <collectRegisterFfdc> + <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> + <target>MC_TARGET</target> + <targetType>TARGET_TYPE_MCBIST</targetType> + </collectRegisterFfdc> <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> + <target>MC_TARGET</target> + <priority>HIGH</priority> </callout> </hwpError> - <hwpError> - <rc>RC_MSS_INVALID_RANK_PASSED</rc> - <description> An invalid rank was passed to ecc::read function</description> - <ffdc>RANK</ffdc> - <ffdc>FUNCTION</ffdc> - <ffdc>TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> <hwpError> - <rc>RC_MSS_INVALID_INDEX_PASSED</rc> - <description> An invalid index was passed to MODAL_SYMBOL_COUNT function</description> - <ffdc>INDEX</ffdc> - <ffdc>FUNCTION</ffdc> + <rc>RC_MSS_MEMDIAGS_ERROR_CHANGING_RANDOM_SEED</rc> + <description>Attempting to change to a 24b random data seed which does not exist</description> + <ffdc>RANDOM_SEED</ffdc> <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> + <procedure>CODE</procedure> + <priority>HIGH</priority> </callout> </hwpError> @@ -218,11 +213,11 @@ <description>The MCBIST engine failed to start its program</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -232,12 +227,12 @@ <description>The MCBIST engine failed to stop its program</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <ffdc>POLL_COUNT</ffdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -247,10 +242,10 @@ <description>The port used in an MCBIST program is not functional</description> <ffdc>RELATIVE_PORT_POSITION</ffdc> <ffdc>ADDRESS</ffdc> - <ffdc>MCBIST_TARGET</ffdc> + <ffdc>MC_TARGET</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> @@ -264,11 +259,11 @@ <description>A superfast read operation failed initialization</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -278,11 +273,11 @@ <description>A superfast init operation failed initialization</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -292,11 +287,11 @@ <description>A continuous scrub operation failed initialization</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -306,11 +301,11 @@ <description>A continuous scrub operation failed initialization</description> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <priority>HIGH</priority> </callout> </hwpError> @@ -318,11 +313,11 @@ <hwpError> <rc>RC_MSS_MEMDIAGS_ALREADY_AT_BOUNDARY</rc> <description>A continue request asked to stop at a boundary, but we are there already</description> - <ffdc>MCBIST_TARGET</ffdc> + <ffdc>MC_TARGET</ffdc> <ffdc>BOUNDARY</ffdc> <collectRegisterFfdc> <id>REG_FFDC_MSS_MEMDIAGS_FAILURE</id> - <target>MCBIST_TARGET</target> + <target>MC_TARGET</target> <targetType>TARGET_TYPE_MCBIST</targetType> </collectRegisterFfdc> <callout> @@ -332,16 +327,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_MEMDIAGS_NO_MCBIST_SUBTESTS</rc> - <description>Attempt to run an MCBIST program with no subtests</description> - <ffdc>MCBIST_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_MEMDIAGS_REPAIRS_EXCEEDED</rc> <description>A mark repair operation failed to repair enough bad bits</description> <collectRegisterFfdc> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml index a1310dec2..eec228380 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_spd_decode.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -37,140 +37,6 @@ <hwpErrors> <hwpError> - <rc>RC_MSS_INVALID_SPD_RESERVED_BITS</rc> - <description> - Invalid SPD reserved bits received. - This could be code problem (decoding) or bad SPD. - </description> - <ffdc>FUNCTION_CODE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DIMM_SPEED</rc> - <description> - Invalid DIMM speed received. Possibly a programming error. - </description> - <ffdc>DIMM_SPEED</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DB_MDQ_DRIVE_STRENGTH</rc> - <description> - Bad SPD data for bytes 145 - 147. - Reserved settings for data buffer MDQ drive strength received. - This could be code problem (decoding) or bad SPD. - </description> - <ffdc>DATA_RATE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DRAM_GEN</rc> - <description> - Received a DRAM gen unsupported by the SPD decoder factory - </description> - <ffdc>DRAM_GEN</ffdc> - <ffdc>FUNCTION</ffdc> - <callout> - <procedure>MEMORY_PLUGGING_ERROR</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>DIMM_TARGET</target> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_HYBRID_MODULE</rc> - <description> - Received an invalid or unsupported hybrid media (SPD byte 3, bits [6:4]) - for a specified hybrid modue (SPD byte 3, bit [7]) - </description> - <ffdc>HYBRID</ffdc> - <ffdc>HYBRID_MEDIA</ffdc> - <ffdc>FUNCTION</ffdc> - <callout> - <procedure>MEMORY_PLUGGING_ERROR</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DIMM_TYPE</rc> - <description> - Received a DIMM type unsupported by the SPD decoder factory - </description> - <ffdc>DIMM_TYPE</ffdc> - <ffdc>FUNCTION</ffdc> - <callout> - <procedure>MEMORY_PLUGGING_ERROR</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>DIMM_TARGET</target> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>DIMM_TARGET</target> - </deconfigure> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - </hwpError> - - <hwpError> <rc>RC_MSS_INVALID_RAW_CARD</rc> <description> Received a raw card that isn't currently supported in code @@ -194,89 +60,4 @@ </deconfigure> </hwpError> - <hwpError> - <rc>RC_MSS_FAILED_SPD_REVISION_FALLBACK</rc> - <description> - Unable to fall back SPD decoder to the highest decoded - revision. Most likely a programming error. - </description> - <ffdc>FAILED_REVISION</ffdc> - <ffdc>FUNCTION_CODE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_SPD_TIMING_FAIL</rc> - <description> - Timing SPD parameter failed to meet JEDEC SPD timing - bounds. FUNCTION_CODE ffdc field encodes which timing param. - </description> - <ffdc>FAILED_REVISION</ffdc> - <ffdc>FUNCTION_CODE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_SPD_PARAMETER_RECEIVED</rc> - <description> - Unable to fall back SPD decoder to the highest decoded - revision. Most likely a programming error. - </description> - <ffdc>SPD_PARAM</ffdc> - <ffdc>FUNCTION_CODE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - - <hwpError> - <rc>RC_MSS_SPD_REV_ENCODING_LEVEL_NOT_SUPPORTED</rc> - <description> - SPD revision on byte 1 (bits 7~4) has a unsupported encoding level - that is greater than the largest decoded SPD decoder. There is - no backward compatible revision to fallback to. This could be - bad SPD or a programming error. - </description> - <ffdc>ENCODING_LEVEL</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>MEDIUM</priority> - </callout> - <callout> - <target>TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>TARGET</target> - </deconfigure> - </hwpError> - </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml index 5147e960f..5a5764e97 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_mss_eff_grouping_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -239,4 +239,18 @@ </callout> </hwpError> +<hwpError> + <rc>RC_MSS_EFF_GROUPING_ADDRESS_NOT_ALIGNED</rc> + <description> + NHTM BAR address is not aligned with requested size. + </description> + <ffdc>NHTM_BAR_BASE</ffdc> + <ffdc>NHTM_SIZE</ffdc> + <ffdc>CHTM_SIZE</ffdc> + <callout> + <procedure>CODE</procedure> + <priority>HIGH</priority> + </callout> +</hwpError> + </hwpErrors> diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml index 4dee999b7..e2c010a53 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2015,2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -34,6 +34,8 @@ for a completed transition. </description> + <ffdc>EX</ffdc> + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> <collectRegisterFfdc> @@ -47,11 +49,6 @@ <targetType>TARGET_TYPE_EQ</targetType> </collectRegisterFfdc> <collectRegisterFfdc> - <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> - <target>EX</target> - <targetType>TARGET_TYPE_EX</targetType> - </collectRegisterFfdc> - <collectRegisterFfdc> <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> <target>EC</target> <targetType>TARGET_TYPE_CORE</targetType> @@ -77,6 +74,8 @@ but the achieved level is not appropriate. </description> + <ffdc>EX</ffdc> + <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc> <collectRegisterFfdc> @@ -90,11 +89,6 @@ <targetType>TARGET_TYPE_EQ</targetType> </collectRegisterFfdc> <collectRegisterFfdc> - <id>CHECK_MASTER_STOP15_FFDC_REGS_EX</id> - <target>EX</target> - <targetType>TARGET_TYPE_EX</targetType> - </collectRegisterFfdc> - <collectRegisterFfdc> <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id> <target>EC</target> <targetType>TARGET_TYPE_CORE</targetType> diff --git a/src/import/chips/p9/xip/p9_xip_image.h b/src/import/chips/p9/xip/p9_xip_image.h index 76bc2bad1..7821ca642 100644 --- a/src/import/chips/p9/xip/p9_xip_image.h +++ b/src/import/chips/p9/xip/p9_xip_image.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2018 */ +/* Contributors Listed Below - COPYRIGHT 2015,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -1619,6 +1619,7 @@ p9_xip_decode_toc_dump(void* i_image, void* i_dump, .macro .xip_toc, index:req, type:req, address:req, elements=1 .if (((\type) < 1) || ((\type) > P9_XIP_MAX_TYPE_INDEX)) + // cppcheck-suppress syntaxError .error ".xip_toc : Illegal type index" .endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/p9a_data_init_traits.H b/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/p9a_data_init_traits.H new file mode 100644 index 000000000..509795f47 --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/p9a_data_init_traits.H @@ -0,0 +1,555 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/eff_config/p9a_data_init_traits.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9a_data_init_traits.H +/// @brief Trait class definitions for Axone pre_data_init +/// +// *HWP HWP Owner: Andre Marin <aamarin@us.ibm.com> +// *HWP FW Owner: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: HB:CI + +#ifndef _MSS_P9A_PRE_DATA_INIT_TRAITS_H_ +#define _MSS_P9A_PRE_DATA_INIT_TRAITS_H_ + +#include <fapi2.H> +#include <generic/memory/lib/data_engine/data_engine_traits_def.H> +#include <generic/memory/lib/data_engine/data_engine_utils.H> +#include <generic/memory/lib/spd/spd_facade.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <generic/memory/lib/mss_generic_attribute_setters.H> + +namespace mss +{ + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, DIMM_TYPE specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::DIMM_TYPE> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DIMM_TYPE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_TYPE; + + /// + /// @brief attribute getter + /// @param[in] i_target the attr target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dimm_type(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attr target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dimm_type(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > BASE_MODULE_TYPE_MAP = + { + //{key byte, dimm type} + {1, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_RDIMM}, + {2, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_UDIMM}, + {10, fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_DDIMM}, + // All others reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_base_module_type = 0; + FAPI_TRY( i_spd_data.base_module(l_base_module_type), + "%s failed to get base module from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY( lookup_table_check(l_dimm, BASE_MODULE_TYPE_MAP, FFDC_CODE, l_base_module_type, o_setting), + "%s failed DIMM_TYPE lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, DRAM_GEN specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::DRAM_GEN> +{ + using attr_type = fapi2::ATTR_MEM_EFF_DRAM_GEN_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DRAM_GEN_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DRAM_GEN; + + /// + /// @brief attribute getter + /// @param[in] i_target the attr target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dram_gen(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attr target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dram_gen(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 2 (0x002): Key Byte / DRAM Device Type + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > DRAM_GEN_MAP = + { + //{key value, dram gen} + {0x0C, fapi2::ENUM_ATTR_MEM_EFF_DRAM_GEN_DDR4} + // Other key bytes reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_device_type = 0; + FAPI_TRY( i_spd_data.device_type(l_device_type), + "%s failed to get device type from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY( lookup_table_check(l_dimm, DRAM_GEN_MAP, FFDC_CODE, l_device_type, o_setting), + "%s failed DRAM_GEN lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, HOST_TO_DDR_SPEED_RATIO specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::HOST_TO_DDR_SPEED_RATIO> +{ + using attr_type = fapi2::ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HOST_TO_DDR_SPEED_RATIO; + + /// + /// @brief attribute getter + /// @param[in] i_target the attr target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_host_to_ddr_speed_ratio(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attr target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_host_to_ddr_speed_ratio(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 220 (0x0DC): Host Interface Speed to DDR Interface Speed Ratio + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > HOST_TO_DDR_SPEED_RATIO_MAP = + { + // {key byte, speed ratio} + {0, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_1_TO_1}, + {1, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_2_TO_1}, + {2, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_4_TO_1}, + {3, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_8_TO_1}, + {4, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_16_TO_1}, + {5, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_32_TO_1}, + {6, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_64_TO_1}, + {7, fapi2::ENUM_ATTR_MEM_EFF_HOST_TO_DDR_SPEED_RATIO_128_TO_1}, + // All others reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_value = 0; + FAPI_TRY( i_spd_data.host_to_ddr_speed_ratio(l_value), + "%s failed to get host to DDR speed ratio from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY( lookup_table_check(l_dimm, HOST_TO_DDR_SPEED_RATIO_MAP, FFDC_CODE, l_value, o_setting), + "%s failed HOST_TO_DDR_SPEED_RATIO lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, HYBRID specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::HYBRID> +{ + using attr_type = fapi2::ATTR_MEM_EFF_HYBRID_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_HYBRID_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID; + + /// + /// @brief attribute getter + /// @param[in] i_target the attr target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_hybrid(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attr target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_hybrid(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type - Hybrid + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > HYBRID_MAP = + { + //{key byte, dimm type} + {0, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_NOT_HYBRID}, + {1, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_IS_HYBRID}, + // All others reserved or not supported + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_spd_hybrid_type = 0; + FAPI_TRY(i_spd_data.hybrid(l_spd_hybrid_type), + "%s failed to get hybrid from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY(lookup_table_check(l_dimm, HYBRID_MAP, FFDC_CODE, l_spd_hybrid_type, o_setting), + "%s failed HYBRID lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, HYBRID_MEDIA specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::HYBRID_MEDIA> +{ + using attr_type = fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_HYBRID_MEDIA; + + /// + /// @brief attribute getter + /// @param[in] i_target the attr target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_hybrid_memory_type(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attr target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_hybrid_memory_type(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 3 (0x003): Key Byte / Module Type - Hybrid + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > HYBRID_MEMORY_TYPE_MAP = + { + + //{key byte, dimm type} + {0, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_NONE}, + {1, fapi2::ENUM_ATTR_MEM_EFF_HYBRID_MEMORY_TYPE_NVDIMM}, + // All others reserved or not supported + }; + const auto l_dimm = i_spd_data.get_dimm_target(); + attr_integral_type l_spd_hybrid_media = 0; + + FAPI_TRY( i_spd_data.hybrid_media(l_spd_hybrid_media), + "%s failed to get hybrid media from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY( lookup_table_check(l_dimm, HYBRID_MEMORY_TYPE_MAP, FFDC_CODE, l_spd_hybrid_media, o_setting), + "%s failed HYBRID_MEMORY_TYPE lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note pre_data_init_fields, MRANKS specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::MRANKS> +{ + using attr_type = fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static constexpr fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_MRANKS; + + /// + /// @brief attribute getter + /// @param[in] i_target the attribute associated target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_num_master_ranks_per_dimm(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the attribute associated target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_num_master_ranks_per_dimm(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + /// + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // ========================================================= + // DDR4 SPD Document Release 4 + // Byte 12 (0x00C): Module Organization + // ========================================================= + static const std::vector< std::pair<uint8_t, uint8_t> > NUM_PACKAGE_RANKS_MAP = + { + // {key byte, num of package ranks per DIMM (package ranks)} + {0, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_1R}, + {1, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_2R}, + {3, fapi2::ENUM_ATTR_MEM_EFF_NUM_MASTER_RANKS_PER_DIMM_4R}, + }; + + const auto l_dimm = i_spd_data.get_dimm_target(); + + attr_integral_type l_master_ranks_spd = 0; + FAPI_TRY( i_spd_data.num_package_ranks_per_dimm(l_master_ranks_spd), + "%s failed to get number of package ranks from SPD", spd::c_str(l_dimm) ); + + FAPI_TRY( lookup_table_check(l_dimm, NUM_PACKAGE_RANKS_MAP, FFDC_CODE, l_master_ranks_spd, o_setting), + "%s failed MASTER_RANKS lookup check", spd::c_str(l_dimm) ); + + fapi_try_exit: + return fapi2::current_err; + } +}; + +/// +/// @brief Traits for pre_data_engine +/// @class attrEngineTraits +/// @note DIMM_RANKS_CNFG specialization +/// +template<> +struct attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::DIMM_RANKS_CNFG> +{ + + using attr_type = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_Type; + using attr_integral_type = std::remove_all_extents<attr_type>::type; + static const fapi2::TargetType TARGET_TYPE = fapi2::ATTR_MEM_EFF_DIMM_RANKS_CONFIGED_TargetType; + static constexpr generic_ffdc_codes FFDC_CODE = SET_DIMM_RANKS_CNFG; + + /// + /// @brief attribute getter + /// @param[in] i_target the fapi2 target + /// @param[out] o_setting array to populate + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode get_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& o_setting) + { + return mss::attr::get_dimm_ranks_configed(i_target, o_setting); + } + + /// + /// @brief attribute setter + /// @param[in] i_target the fapi2 target + /// @param[in] i_setting array to set + /// @return FAPI2_RC_SUCCESS iff okay + /// + static inline fapi2::ReturnCode set_attr(const fapi2::Target<TARGET_TYPE>& i_target, + attr_type& i_setting) + { + return mss::attr::set_dimm_ranks_configed(i_target, i_setting); + } + + /// + /// @brief Computes setting for attribute + /// @param[in] i_spd_data SPD data + /// @param[out] o_setting value we want to set attr with + /// @return FAPI2_RC_SUCCESS iff okay + + static fapi2::ReturnCode get_value_to_set(const spd::facade& i_spd_data, + attr_integral_type& o_setting) + { + // Set configed ranks. Set the bit representing the master rank configured (0 being left most.) So, + // a 4R DIMM would be 0b11110000 (0xF0). This is used by PRD. + fapi2::buffer<uint8_t> l_ranks_configed; + + // Make sure the number of master ranks is setup + uint8_t l_master_ranks = 0; + FAPI_TRY( (attrEngineTraits<proc_type::AXONE, pre_data_init_fields, pre_data_init_fields::MRANKS>::get_value_to_set( + i_spd_data, + l_master_ranks)) ); + + FAPI_TRY( l_ranks_configed.setBit(0, l_master_ranks), + "%s. Failed to setBit", spd::c_str(i_spd_data.get_dimm_target()) ); + + o_setting = l_ranks_configed; + + fapi_try_exit: + return fapi2::current_err; + } +}; + +}//mss + +#endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.C b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H index 6e745ea5c..045c8b5f9 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.C $ */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir_traits.H b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir_traits.H new file mode 100644 index 000000000..19e7f4fa9 --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir_traits.H @@ -0,0 +1,24 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_fir_traits.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2020 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.H b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_unmask.C index a71466b4a..497d5c685 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_unmask.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_mss_scrub.H $ */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/fir/p9a_unmask.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H index 1b4f96d0c..3c21636fc 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_freq_traits.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -56,14 +56,15 @@ class frequency_traits<mss::proc_type::AXONE> ////////////////////////////////////////////////////////////// static constexpr fapi2::TargetType PORT_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; static constexpr fapi2::TargetType FREQ_TARGET_TYPE = fapi2::TARGET_TYPE_MEM_PORT; + static constexpr fapi2::TargetType FREQ_DOMAIN_TARGET_TYPE = fapi2::TARGET_TYPE_PROC_CHIP; static constexpr fapi2::TargetType VPD_TARGET_TYPE = fapi2::TARGET_TYPE_OCMB_CHIP; ////////////////////////////////////////////////////////////// // Traits values ////////////////////////////////////////////////////////////// static const std::vector<uint64_t> SUPPORTED_FREQS; - // MEM_PORT is our frequency domain. So 1 port per domain - static constexpr uint64_t PORTS_PER_FREQ_DOMAIN = 1; + // PROC_CHIP is our frequency domain + static constexpr uint64_t PORTS_PER_FREQ_DOMAIN = 16; // Max DIMM's per port static constexpr uint64_t MAX_DIMM_PER_PORT = 2; // Maxium number of primary ranks on a DIMM diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_mss_freq.C b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_mss_freq.C index 08317cb8a..db6556af3 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_mss_freq.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_mss_freq.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -37,6 +37,10 @@ #include <vpd_access.H> #include <vector> +// Explorer rank API +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> + // Memory libraries #include <lib/freq/axone_freq_traits.H> #include <lib/shared/axone_consts.H> @@ -100,10 +104,13 @@ fapi_try_exit: /// template<> fapi2::ReturnCode set_freq<mss::proc_type::AXONE>( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint64_t i_freq) { - FAPI_TRY( mss::attr::set_freq(i_target, i_freq) ); + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + FAPI_TRY( mss::attr::set_freq(l_port, i_freq) ); + } fapi_try_exit: return fapi2::current_err; @@ -130,7 +137,7 @@ fapi_try_exit: return fapi2::current_err; } /// -/// @brief Gets the DIMM type for a specific DIMM - specialization for the NIMBUS processor type +/// @brief Gets the DIMM type for a specific DIMM - specialization for the AXONE processor type /// @param[in] i_target DIMM target /// @param[out] o_dimm_type DIMM type on the DIMM target /// @return FAPI2_RC_SUCCESS iff ok @@ -187,7 +194,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode callout_bad_freq_calculated<mss::proc_type::AXONE>( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const uint64_t i_final_freq) { using TT = mss::frequency_traits<mss::proc_type::AXONE>; @@ -218,55 +225,18 @@ fapi_try_exit: } /// -/// @brief Return a list of configured ranks on a MEM_PORT -/// @param[in] i_target the port target -/// @param[out] o_ranks list of valid ranks on the port -/// @return FAPI2_RC_SUCCESS iff ok +/// @brief Determines if rank info object is that of an LR dimm /// -// TK this function should get replaced by our rank API when available -fapi2::ReturnCode get_ranks_for_vpd( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - std::vector<uint64_t>& o_ranks) +/// @param[in] i_rank_info rank info object +/// @param[out] l_lr_dimm true if LRDIMM, else false +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if success +/// +inline fapi2::ReturnCode rank_is_lr_dimm(const mss::rank::info<> i_rank_info, bool& o_lr_dimm) { - using TT = mss::frequency_traits<mss::proc_type::AXONE>; - - uint8_t l_rank_count_dimm[TT::MAX_DIMM_PER_PORT] = {}; - uint8_t l_dimm_type[TT::MAX_DIMM_PER_PORT] = {}; + uint8_t l_dimm_type = 0; + FAPI_TRY(mss::attr::get_dimm_type(i_rank_info.get_dimm_target(), l_dimm_type)); - o_ranks.clear(); - - FAPI_TRY( get_master_rank_per_dimm<mss::proc_type::AXONE>(i_target, &(l_rank_count_dimm[0])) ); - FAPI_TRY( get_dimm_type<mss::proc_type::AXONE>(i_target, &(l_dimm_type[0])) ); - - // So for LRDIMM, our SI works a bit differently than for non-LRDIMM - // LRDIMM's have buffers that operate on a per-DIMM basis across multiple ranks - // As such, they act as a single load, similar to a 1R DIMM would - // per the IBM signal integrity team, the 1R DIMM settings should be used for LRDIMM's - // So, if we are LRDIMM's and have ranks, we want to only note it as a 1R DIMM for purposes of querying the VPD - FAPI_DBG("%s for DIMM 0 rank count %u dimm type %u %s", - mss::c_str(i_target), l_rank_count_dimm[0], l_dimm_type[0], l_dimm_type[0] == TT::LRDIMM_TYPE ? "LRDIMM" : "RDIMM"); - FAPI_DBG("%s for DIMM 1 rank count %u dimm type %u %s", - mss::c_str(i_target), l_rank_count_dimm[1], l_dimm_type[1], l_dimm_type[1] == TT::LRDIMM_TYPE ? "LRDIMM" : "RDIMM"); - - l_rank_count_dimm[0] = ((l_dimm_type[0] == TT::LRDIMM_TYPE) && (l_rank_count_dimm[0] > 0)) ? 1 : l_rank_count_dimm[0]; - l_rank_count_dimm[1] = ((l_dimm_type[1] == TT::LRDIMM_TYPE) && (l_rank_count_dimm[1] > 0)) ? 1 : l_rank_count_dimm[1]; - - FAPI_DBG("after LR modification %s for DIMM 0 rank count %u dimm type %u %s", - mss::c_str(i_target), l_rank_count_dimm[0], l_dimm_type[0], l_dimm_type[0] == TT::LRDIMM_TYPE ? "LRDIMM" : "RDIMM"); - FAPI_DBG("after LR modification %s for DIMM 1 rank count %u dimm type %u %s", - mss::c_str(i_target), l_rank_count_dimm[1], l_dimm_type[1], l_dimm_type[1] == TT::LRDIMM_TYPE ? "LRDIMM" : "RDIMM"); - - // Add DIMM0's ranks - for (uint64_t l_rank = 0; l_rank < l_rank_count_dimm[0]; ++l_rank) - { - o_ranks.push_back(l_rank); - } - - // Add DIMM1's ranks - for (uint64_t l_rank = 0; l_rank < l_rank_count_dimm[1]; ++l_rank) - { - o_ranks.push_back(l_rank + TT::MAX_PRIMARY_RANK_PER_DIMM); - } + o_lr_dimm = (l_dimm_type == fapi2::ENUM_ATTR_MEM_EFF_DIMM_TYPE_LRDIMM); fapi_try_exit: return fapi2::current_err; @@ -288,37 +258,45 @@ fapi2::ReturnCode check_freq_support_vpd<mss::proc_type::AXONE>( const fapi2::Ta using TT = mss::frequency_traits<mss::proc_type::AXONE>; o_supported = false; - std::vector<uint64_t> l_ranks; + std::vector<mss::rank::info<>> l_ranks; fapi2::VPDInfo<TT::VPD_TARGET_TYPE> l_vpd_info(TT::VPD_BLOB); const auto& l_vpd_target = mss::find_target<TT::VPD_TARGET_TYPE>(i_target); + uint32_t l_omi_freq = 0; l_vpd_info.iv_is_config_ffdc_enabled = false; - FAPI_TRY(convert_ddr_freq_to_omi_freq(i_target, i_proposed_freq, l_vpd_info.iv_omi_freq_mhz)); - FAPI_INF("Setting VPD info OMI frequency: %d Gbps, for DDR frequency %d MT/s", - l_vpd_info.iv_omi_freq_mhz, i_proposed_freq); + FAPI_TRY(convert_ddr_freq_to_omi_freq(i_target, i_proposed_freq, l_omi_freq)); + l_vpd_info.iv_omi_freq_mhz = l_omi_freq; // DDIMM SPD can contain different SI settings for each master rank. // To determine which frequencies are supported, we have to check for each valid // master rank on the port's DIMMs - FAPI_TRY(get_ranks_for_vpd(i_target, l_ranks)); + FAPI_TRY(mss::rank::ranks_on_port(i_target, l_ranks)); - for (const auto l_rank : l_ranks) + for (const auto& l_rank : l_ranks) { - l_vpd_info.iv_rank = l_rank; - FAPI_INF("%s. VPD info - checking rank: %d", - mss::c_str(i_target), l_rank); + // We will skip LRDIMMs with ranks > 0 + bool l_is_lr_dimm = false; + FAPI_TRY(rank_is_lr_dimm(l_rank, l_is_lr_dimm)); + + if (rank_not_supported_in_vpd_config(l_is_lr_dimm, l_rank.get_dimm_rank())) + { + FAPI_DBG("LRDIMM ranks > 0 are not supported for check_freq_support_vpd. Skipping this rank. Target: %s", + mss::c_str(i_target)); + continue; + } + + l_vpd_info.iv_rank = l_rank.get_dimm_rank(); // Check if this VPD configuration is supported FAPI_TRY(is_vpd_config_supported<mss::proc_type::AXONE>(l_vpd_target, i_proposed_freq, l_vpd_info, o_supported), - "%s failed to determine if %u freq is supported", mss::c_str(i_target), i_proposed_freq); - + "%s failed to determine if %u freq is supported on rank %d", mss::c_str(i_target), i_proposed_freq, l_vpd_info.iv_rank); // If we fail any of the ranks, then this VPD configuration is not supported if(o_supported == false) { - FAPI_INF("%s is not supported on rank%u exiting...", mss::c_str(i_target), l_rank); + FAPI_INF("%s is not supported on rank %u exiting...", mss::c_str(i_target), l_rank.get_port_rank()); break; } } @@ -328,29 +306,34 @@ fapi_try_exit: } /// -/// @brief Update supported frequency scoreboard according to processor limits - specialization for Axone and MEM_PORT +/// @brief Update supported frequency scoreboard according to processor limits - specialization for Axone and PROC_CHIP /// @param[in] i_target processor frequency domain /// @param[in,out] io_scoreboard scoreboard of port targets supporting each frequency /// @return FAPI2_RC_SUCCESS iff ok /// template<> fapi2::ReturnCode limit_freq_by_processor<mss::proc_type::AXONE>( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, freq_scoreboard& io_scoreboard) { - std::vector<uint64_t> l_converted_omi_freqs; - // OCMB always needs to be in sync between OMI and DDR, by the given ratio // so we convert the supported OMI freqs and remove every other DDR freq // from the scoreboard - for (const auto l_omi_freq : AXONE_OMI_FREQS) + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) { - uint64_t l_ddr_freq = 0; - FAPI_TRY(convert_omi_freq_to_ddr_freq(i_target, l_omi_freq, l_ddr_freq)); - l_converted_omi_freqs.push_back(l_ddr_freq); - } + const auto l_port_pos = mss::relative_pos<fapi2::TARGET_TYPE_PROC_CHIP>(l_port); - FAPI_TRY(io_scoreboard.remove_freqs_not_on_list(0, l_converted_omi_freqs)); + std::vector<uint64_t> l_converted_omi_freqs; + + for (const auto l_omi_freq : AXONE_OMI_FREQS) + { + uint64_t l_ddr_freq = 0; + FAPI_TRY(convert_omi_freq_to_ddr_freq(l_port, l_omi_freq, l_ddr_freq)); + l_converted_omi_freqs.push_back(l_ddr_freq); + } + + FAPI_TRY(io_scoreboard.remove_freqs_not_on_list(l_port_pos, l_converted_omi_freqs)); + } fapi_try_exit: return fapi2::current_err; @@ -374,12 +357,12 @@ fapi2::ReturnCode num_master_ranks_per_dimm<mss::proc_type::AXONE>( /// @brief Calls out the target if no DIMM frequencies are supported - specialization for Axone and MEM_PORT /// @param[in] i_target target on which to operate /// @param[in] i_supported_freq true if any FREQ's are supported -/// @param[in,out] i_num_ports number of configured ports (always 1 for Axone) +/// @param[in,out] i_num_ports number of configured ports /// @return FAPI2_RC_SUCCESS iff ok /// template<> fapi2::ReturnCode callout_no_common_freq<mss::proc_type::AXONE>( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const bool i_supported_freq, const uint64_t i_num_ports) { @@ -408,7 +391,7 @@ fapi_try_exit: /// template<> fapi2::ReturnCode callout_max_freq_empty_set<mss::proc_type::AXONE>( - const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, const std::vector<std::vector<uint32_t>>& i_vpd_supported_freqs) { @@ -423,21 +406,26 @@ fapi2::ReturnCode callout_max_freq_empty_set<mss::proc_type::AXONE>( uint32_t l_max_mrw_freqs[NUM_MAX_FREQS] = {0}; FAPI_TRY( mss::attr::get_max_allowed_dimm_freq(l_max_mrw_freqs) ); - FAPI_ASSERT(false, - fapi2::P9A_MSS_MRW_FREQ_MAX_FREQ_EMPTY_SET() - .set_MSS_VPD_FREQ_0(l_port_vpd_max_freq[0]) - .set_MSS_VPD_FREQ_1(l_port_vpd_max_freq[1]) - .set_MSS_VPD_FREQ_2(l_port_vpd_max_freq[2]) - .set_MSS_MAX_FREQ_0(l_max_mrw_freqs[0]) - .set_MSS_MAX_FREQ_1(l_max_mrw_freqs[1]) - .set_MSS_MAX_FREQ_2(l_max_mrw_freqs[2]) - .set_MSS_MAX_FREQ_3(l_max_mrw_freqs[3]) - .set_MSS_MAX_FREQ_4(l_max_mrw_freqs[4]) - .set_OMI_FREQ_0(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_21_33GBPS) - .set_OMI_FREQ_1(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_23_46GBPS) - .set_OMI_FREQ_2(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_25_60GBPS) - .set_PORT_TARGET(i_target), - "%s didn't find a supported frequency for the port", mss::c_str(i_target)); + for (const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) + { + FAPI_ASSERT_NOEXIT(false, + fapi2::P9A_MSS_MRW_FREQ_MAX_FREQ_EMPTY_SET() + .set_MSS_VPD_FREQ_0(l_port_vpd_max_freq[0]) + .set_MSS_VPD_FREQ_1(l_port_vpd_max_freq[1]) + .set_MSS_VPD_FREQ_2(l_port_vpd_max_freq[2]) + .set_MSS_MAX_FREQ_0(l_max_mrw_freqs[0]) + .set_MSS_MAX_FREQ_1(l_max_mrw_freqs[1]) + .set_MSS_MAX_FREQ_2(l_max_mrw_freqs[2]) + .set_MSS_MAX_FREQ_3(l_max_mrw_freqs[3]) + .set_MSS_MAX_FREQ_4(l_max_mrw_freqs[4]) + .set_OMI_FREQ_0(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_21_33GBPS) + .set_OMI_FREQ_1(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_23_46GBPS) + .set_OMI_FREQ_2(fapi2::ENUM_ATTR_MSS_OCMB_EXP_BOOT_CONFIG_SERDES_FREQUENCY_SERDES_25_60GBPS) + .set_TARGET(l_port), + "%s didn't find a supported frequency for any ports in this domain", mss::c_str(l_port)); + } + + return fapi2::RC_P9A_MSS_MRW_FREQ_MAX_FREQ_EMPTY_SET; fapi_try_exit: return fapi2::current_err; @@ -446,14 +434,14 @@ namespace check { /// -/// @brief Checks the final frequency for the system type - Axone and MEM_PORT specialization +/// @brief Checks the final frequency for the system type - Axone and PROC_CHIP specialization /// @param[in] i_target the target on which to operate /// @return FAPI2_RC_SUCCESS iff okay /// @note This function was needed in Nimbus to enforce a frequency limit due to a hardware limitation /// and is not needed here. /// template<> -fapi2::ReturnCode final_freq<mss::proc_type::AXONE>(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target) +fapi2::ReturnCode final_freq<mss::proc_type::AXONE>(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { return fapi2::FAPI2_RC_SUCCESS; } diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.C b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.C index 8fd3c679b..1e3aea1a5 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -156,7 +156,7 @@ fapi_try_exit: /// bool deconfigure(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, const uint64_t i_dimm_speed, - const uint32_t i_max_freq) + const uint64_t i_max_freq) { bool l_is_hw_deconfigured = (i_dimm_speed != i_max_freq); @@ -174,44 +174,42 @@ bool deconfigure(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, } /// -/// @brief Selects synchronous mode and performs requirements enforced by selected port frequency +/// @brief Selects OMI frequency based on selected port frequencies /// @param[in] i_freq_map dimm speed mapping /// @param[in] i_equal_dimm_speed tracks whether map has equal dimm speeds /// @param[in] i_omi_freq OMI frequency -/// @param[out] o_selected_sync_mode final synchronous mode -/// @param[out] o_selected_omi_freq final freq selected, only valid if final sync mode is in-sync +/// @param[out] o_selected_omi_freq final freq selected /// @return FAPI2_RC_SUCCESS iff successful /// -fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t >& i_freq_map, - const speed_equality i_equal_dimm_speed, - const uint32_t i_omi_freq, - uint8_t& o_selected_sync_mode, - uint64_t& o_selected_omi_freq) +fapi2::ReturnCode select_omi_freq(const std::map< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t >& i_freq_map, + const speed_equality i_equal_dimm_speed, + const uint32_t i_omi_freq, + uint32_t& o_selected_omi_freq) { - FAPI_INF("---- In select_sync_mode ----"); - switch(i_equal_dimm_speed) { - // If we have a port which has resolved to equal speeds ... + // If we resolved to equal speeds ... case speed_equality::EQUAL_DIMM_SPEEDS: { // Return back the resulting speed. It doesn't matter which we select from the map as they're all equal // If we end up not in sync in the conditional below, thats ok - this parameter is ignored by the // caller if we're not in sync mode const auto l_ddr_freq = i_freq_map.begin()->second; - FAPI_TRY(convert_ddr_freq_to_omi_freq(i_freq_map.begin()->first, l_ddr_freq, o_selected_omi_freq)); + FAPI_TRY(convert_ddr_freq_to_omi_freq(i_freq_map.begin()->first, + l_ddr_freq, + o_selected_omi_freq)); // When we selected ATTR_MSS_FREQ, we made sure that we didn't // select a DIMM freq the OMI couldn't support. - o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC; + +#ifndef __HOSTBOOT_MODULE // On Cronus if the o_selected_omi_freq != i_omi_freq we've got a mismatch. Note that p9a_mss_freq ensures // we don't select an invalid freq, but doesn't ensure we select the current OMI freq. -#ifndef __HOSTBOOT_MODULE FAPI_ASSERT(o_selected_omi_freq == i_omi_freq, fapi2::P9A_MSS_FAILED_SYNC_MODE() .set_OMI_FREQ(i_omi_freq) .set_MEM_FREQ(o_selected_omi_freq), - "The DIMM freq (%d) and the OMI freq (%d) don't align", + "The OMI freq selected by DIMM speed (%d) and the currently selected OMI freq (%d) don't align", o_selected_omi_freq, i_omi_freq); #endif return fapi2::FAPI2_RC_SUCCESS; @@ -223,13 +221,14 @@ fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<fapi2::TARGET_T // When we selected ATTR_MSS_FREQ, we made sure that we didn't // select a DIMM freq the OMI couldn't support. That means that the fastest of the ports // is the one that rules the roost (the OMI can support it too.) So find that, and set it to - // the selected frequency. Then deconfigure the slower port (unless we're in Cronus in which + // the selected frequency. Then deconfigure the slower ports (unless we're in Cronus in which // case we just bomb out.) #ifdef __HOSTBOOT_MODULE uint64_t l_max_dimm_speed = 0; fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> l_fastest_port_target = i_freq_map.begin()->first; std::for_each(i_freq_map.begin(), i_freq_map.end(), - [&l_max_dimm_speed, &l_fastest_port_target](const std::pair<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t>& m) + [&l_max_dimm_speed, &l_fastest_port_target] + (const std::pair<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t>& m) { l_max_dimm_speed = std::max(l_max_dimm_speed, m.second); l_fastest_port_target = m.first; @@ -241,15 +240,16 @@ fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<fapi2::TARGET_T deconfigure(m.first, m.second, l_max_dimm_speed); }); - o_selected_sync_mode = fapi2::ENUM_ATTR_MC_SYNC_MODE_IN_SYNC; - FAPI_TRY(convert_ddr_freq_to_omi_freq(l_fastest_port_target, l_max_dimm_speed, o_selected_omi_freq)); + FAPI_TRY(convert_ddr_freq_to_omi_freq(l_fastest_port_target, + l_max_dimm_speed, + o_selected_omi_freq)); return fapi2::FAPI2_RC_SUCCESS; #else // Cronus only FAPI_ASSERT(false, fapi2::P9A_MSS_FAILED_SYNC_MODE() .set_OMI_FREQ(i_omi_freq), - "DIMM speeds differ from OMI speed %d", i_omi_freq); + "Some DIMM speeds are incompatible with OMI speed %d", i_omi_freq); #endif break; } diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.H b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.H index 06345713c..29436db00 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/freq/axone_sync.H @@ -43,6 +43,7 @@ #include <mss_generic_attribute_getters.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <lib/shared/axone_consts.H> +#include <lib/freq/axone_freq_traits.H> #include <generic/memory/lib/utils/freq/mss_freq_scoreboard.H> #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/mss_math.H> @@ -60,6 +61,18 @@ static const std::vector<uint64_t> AXONE_OMI_FREQS = }; /// +/// @brief determines if rank is not supported in VPD config, will be skipped in check_freq_support_vpd() +/// +/// @param[in] i_is_lr_dimm is LR +/// @param[in] i_dimm_rank DIMM rank +/// @return true if LR & rank > 0, else false +/// +inline bool rank_not_supported_in_vpd_config(const bool i_is_lr_dimm, const uint8_t i_dimm_rank) +{ + return (i_is_lr_dimm && i_dimm_rank > 0); +} + +/// /// @brief Converts an OMI frequency attribute enum to the corresponding OMI frequency /// @param[in] i_omi_enum a frequency enum value that is to be converted /// @return the corresponding OMI frequency @@ -99,18 +112,19 @@ fapi_try_exit: /// inline fapi2::ReturnCode convert_ddr_freq_to_omi_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, const uint64_t i_ddr_freq, - uint64_t& o_omi_freq) + uint32_t& o_omi_freq) { using TT = mss::frequency_traits<mss::proc_type::AXONE>; constexpr uint64_t ROUND_UNITS = 10; + uint64_t l_omi_freq = 0; // Get the OMI to DDR freq ratio uint8_t l_ratio[TT::MAX_DIMM_PER_PORT] = {0}; FAPI_TRY(mss::attr::get_host_to_ddr_speed_ratio(i_target, l_ratio)); // Multiply by the ratio and round to the nearest 10GBPS - FAPI_TRY(mss::divide_and_round((i_ddr_freq * l_ratio[0]), ROUND_UNITS, o_omi_freq)); - o_omi_freq *= ROUND_UNITS; + FAPI_TRY(mss::divide_and_round((i_ddr_freq * l_ratio[0]), ROUND_UNITS, l_omi_freq)); + o_omi_freq = ROUND_UNITS * l_omi_freq; FAPI_DBG("For ratio %d and DDR freq %d, corresponding OMI freq is %d", l_ratio[0], i_ddr_freq, o_omi_freq); fapi_try_exit: @@ -125,7 +139,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff successful /// inline fapi2::ReturnCode convert_omi_freq_to_ddr_freq(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - const uint64_t i_omi_freq, + const uint32_t i_omi_freq, uint64_t& o_ddr_freq) { using TT = mss::frequency_traits<mss::proc_type::AXONE>; @@ -134,7 +148,7 @@ inline fapi2::ReturnCode convert_omi_freq_to_ddr_freq(const fapi2::Target<fapi2: uint8_t l_ratio[TT::MAX_DIMM_PER_PORT] = {0}; FAPI_TRY(mss::attr::get_host_to_ddr_speed_ratio(i_target, l_ratio)); - FAPI_TRY(mss::divide_and_round(i_omi_freq, static_cast<uint64_t>(l_ratio[0]), o_ddr_freq), + FAPI_TRY(mss::divide_and_round(static_cast<uint64_t>(i_omi_freq), static_cast<uint64_t>(l_ratio[0]), o_ddr_freq), "%s freq system saw a zero Host (OMI) to DDR frequency ratio", mss::c_str(i_target)); FAPI_DBG( "For ratio %d and OMI freq %d, corresponding DDR freq is %d", l_ratio[0], i_omi_freq, o_ddr_freq); @@ -143,26 +157,6 @@ fapi_try_exit: } /// -/// @brief Checks to see if a passed in value could be a valid OMI frequency -/// @param[in] i_target the port target -/// @param[in] i_proposed_freq a frequency value that is to be checked -/// @param[out] o_valid boolean whether the value is a valid OMI frequency -/// @return FAPI2_RC_SUCCESS iff successful -/// -inline fapi2::ReturnCode is_omi_freq_valid (const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, - const uint64_t i_proposed_freq, - uint64_t& o_valid) -{ - uint64_t l_proposed_omi_freq = 0; - FAPI_TRY(convert_ddr_freq_to_omi_freq(i_target, i_proposed_freq, l_proposed_omi_freq)); - - o_valid = std::binary_search(AXONE_OMI_FREQS.begin(), AXONE_OMI_FREQS.end(), l_proposed_omi_freq); - -fapi_try_exit: - return fapi2::current_err; -} - -/// /// @brief Retrieves a mapping of MSS frequency values per port target /// @param[in] i_targets vector of port targets /// @param[out] o_freq_map dimm speed map <key, value> = (port target, frequency) @@ -182,22 +176,20 @@ fapi2::ReturnCode dimm_speed_map(const std::vector< fapi2::Target<fapi2::TARGET_ /// bool deconfigure(const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target, const uint64_t i_dimm_speed, - const uint32_t i_omi_freq); + const uint64_t i_omi_freq); /// -/// @brief Selects synchronous mode and performs requirements enforced by selected port frequency +/// @brief Selects OMI frequency based on selected port frequencies /// @param[in] i_freq_map dimm speed mapping /// @param[in] i_equal_dimm_speed tracks whether map has equal dimm speeds /// @param[in] i_omi_freq OMI frequency -/// @param[out] o_selected_sync_mode final synchronous mode -/// @param[out] o_selected_omi_freq final freq selected, only valid if final sync mode is in-sync +/// @param[out] o_selected_omi_freq final freq selected /// @return FAPI2_RC_SUCCESS iff successful /// -fapi2::ReturnCode select_sync_mode(const std::map< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t >& i_freq_map, - const speed_equality i_equal_dimm_speed, - const uint32_t i_omi_freq, - uint8_t& o_selected_sync_mode, - uint64_t& o_selected_omi_freq); +fapi2::ReturnCode select_omi_freq(const std::map< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t >& i_freq_map, + const speed_equality i_equal_dimm_speed, + const uint32_t i_omi_freq, + uint32_t& o_selected_omi_freq); }// mss diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/host_mc_traits.H index fa45be920..e849eafea 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/host_mc_traits.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/p9/procedures/hwp/memory/lib/dimm/nimbus_kind.C $ */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/mc/host_mc_traits.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H index 1298699b5..48f5cb222 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/mc/omi.H @@ -46,7 +46,10 @@ #include <generic/memory/lib/utils/scom.H> #include <generic/memory/lib/utils/buffer_ops.H> #include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <generic/memory/lib/mss_generic_system_attribute_getters.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <mss_p9a_attribute_getters.H> namespace mss { @@ -54,327 +57,8 @@ namespace mss namespace mc { - -/// -/// @brief These values are the number of clock cycles and the times specified assume a 625ps period. -/// This timer value must be greater than the di/dt timer -/// -enum rx_cdr_timer -{ - CDR_TIMER_DISABLED = 0b0001, - CDR_TIMER_60NS = 0b0001, - CDR_TIMER_125NS = 0b0010, - CDR_TIMER_185NS = 0b0011, - CDR_TIMER_250NS = 0b0100, - CDR_TIMER_375NS = 0b0101, - CDR_TIMER_500NS = 0b0110, - CDR_TIMER_750NS = 0b0111, - CDR_TIMER_1US = 0b1000, - CDR_TIMER_2US = 0b1001, - CDR_TIMER_4US = 0b1010, - CDR_TIMER_8US = 0b1011, - CDR_TIMER_16US = 0b1100, - CDR_TIMER_32US = 0b1101, - CDR_TIMER_64US = 0b1110, - CDR_TIMER_128US = 0b1111 -}; - -/// -/// @brief Amount of time to wait after lane is turned on/off before another lane can be turned on/off -/// -enum didt_timer -{ - DIDT_TIMER_DISABLED = 0b0000, - DIDT_TIMER_5NS = 0b0001, - DIDT_TIMER_10NS = 0b0010, - DIDT_TIMER_15NS = 0b0011, - DIDT_TIMER_20NS = 0b0100, - DIDT_TIMER_30NS = 0b0101, - DIDT_TIMER_45NS = 0b0110, - DIDT_TIMER_60NS = 0b0111, - DIDT_TIMER_90NS = 0b1000, - DIDT_TIMER_125NS = 0b1001, - DIDT_TIMER_185NS = 0b1010, - DIDT_TIMER_250NS = 0b1011, - DIDT_TIMER_375NS = 0b1100, - DIDT_TIMER_500NS = 0b1101, - DIDT_TIMER_768NS = 0b1110, - DIDT_TIMER_1US = 0b1111 -}; - -/// -/// @brief Calibration timer - amount of time betweem re-calibration for a given lane -/// -enum recal_timer -{ - RECAL_TIMER_DISABLED = 0b000, - RECAL_TIMER_25MS = 0b001, - RECAL_TIMER_50MS = 0b010, - RECAL_TIMER_100MS = 0b011, - RECAL_TIMER_200MS = 0b100, - RECAL_TIMER_400MS = 0b101, - RECAL_TIMER_800MS = 0b110, - RECAL_TIMER_1600MS = 0b111 -}; - -/// -/// @brief PMU prescalar value -/// -enum pmu_prescalar -{ - PRESCALAR_16BIT = 0b000, - PRESCALAR_8BIT = 0b001, - PRESCALAR_20BIT = 0b100, -}; - - -/// -/// @brief PMU cntrx pair selector -/// -enum cntrl_pair_selector -{ - SEL_ODD = 0b00, - SEL_EVEN = 0b01, - SEL_BOTH_AND = 0b10, - SEL_BOTH_XOR = 0b11 -}; - -/// -/// @brief PMU cntrx event selector /// -enum cntrl_event_selector -{ - SIG_7_6 = 0b00, - SIG_5_4 = 0b01, - SIG_3_2 = 0b10, - SIG_1_0 = 0b11 -}; - -/// -/// @brief dl0 no forward progress timer -/// -enum no_forward_progress_timer -{ - NO_FORWARD_TIMER_1US = 0b0000, - NO_FORWARD_TIMER_2US = 0b0001, - NO_FORWARD_TIMER_4US = 0b0010, - NO_FORWARD_TIMER_8US = 0b0011, - NO_FORWARD_TIMER_16US = 0b0100, - NO_FORWARD_TIMER_32US = 0b0101, - NO_FORWARD_TIMER_64US = 0b0110, - NO_FORWARD_TIMER_128US = 0b0111, - NO_FORWARD_TIMER_256US = 0b1000, - NO_FORWARD_TIMER_512US = 0b1001, - NO_FORWARD_TIMER_1MS = 0b1010, - NO_FORWARD_TIMER_2MS = 0b1011, - NO_FORWARD_TIMER_4MS = 0b1100, - NO_FORWARD_TIMER_8MS = 0b1101, - NO_FORWARD_TIMER_16MS = 0b1110, - NO_FORWARD_TIMER_DISABLED = 0b1111 -}; - -/// -/// @brief dl0 PHY control mode - determines the amount of time needed to receive pattern A or pattern B -/// -enum phy_ctr_mode -{ - PHY_CTR_MODE_1US = 0b0000, - PHY_CTR_MODE_50US = 0b0001, - PHY_CTR_MODE_100US = 0b0010, - PHY_CTR_MODE_200US = 0b0011, - PHY_CTR_MODE_500US = 0b0100, - PHY_CTR_MODE_1MS = 0b0101, - PHY_CTR_MODE_2MS = 0b0110, - PHY_CTR_MODE_3MS = 0b0111, - PHY_CTR_MODE_4MS = 0b1000, - PHY_CTR_MODE_5MS = 0b1001, - PHY_CTR_MODE_6MS = 0b1010, - PHY_CTR_MODE_8MS = 0b1011, - PHY_CTR_MODE_10MS = 0b1100, - PHY_CTR_MODE_15MS = 0b1101, - PHY_CTR_MODE_30MS = 0b1110, - PHY_CTR_MODE_60MS = 0b1111 -}; - -/// -/// @brief dl0 supported link widths -/// -enum link_widths -{ - LINK_WIDTHS_X4PLUS1 = 0b1000, - LINK_WIDTHS_X16 = 0b0100, - LINK_WIDTHS_X8 = 0b0010, - LINK_WIDTHS_X4 = 0b0001 -}; - -/// -/// @brief dl0 train mode -/// -enum train_mode -{ - TX_ZEROS = 0b0000, - TX_PATTERN_A = 0b0001, - TX_PATTERN_B = 0b0010, - TX_SYNC_PATTERN = 0b0011, - TX_TRAINING_STATE1 = 0b0100, - TX_TRAINING_STATE2 = 0b0101, - TX_TRAINING_STATE3 = 0b0110, - TX_TRAINING_STATE0 = 0b0111, - ENABLE_AUTO_TRAINING = 0b1000 -}; - -/// -/// @brief Configuration override to select lane width for dynamic lane power down modes. -/// -enum lan_width_override -{ - TL_CTR_BY_SIDEBAND = 0b00, - DL_OVERRIDE_X2 = 0b01, - DL_OVERRIDE_X4 = 0b10, - DL_OVERRIDE_X8 = 0b11 -}; - -/// -/// @brief Number of consecutive pattern B seen before indicating received pattern B -/// -enum b_hysteresis -{ - B_HYSTERESIS_16 = 0b0000, - B_HYSTERESIS_24 = 0b0001, - B_HYSTERESIS_32 = 0b0010, - B_HYSTERESIS_40 = 0b0011, - B_HYSTERESIS_48 = 0b0100, - B_HYSTERESIS_56 = 0b0101, - B_HYSTERESIS_64 = 0b0110, - B_HYSTERESIS_72 = 0b0111, - B_HYSTERESIS_80 = 0b1000, - B_HYSTERESIS_96 = 0b1001, - B_HYSTERESIS_128 = 0b1010, - B_HYSTERESIS_256 = 0b1011, - B_HYSTERESIS_512 = 0b1100, - B_HYSTERESIS_1K = 0b1101, - B_HYSTERESIS_2K = 0b1110, - B_HYSTERESIS_4K = 0b1111 -}; - -/// -/// @brief Number of consecutive pattern A seen before indicating received pattern A. -/// -enum a_hysteresis -{ - A_HYSTERESIS_16 = 0b0000, - A_HYSTERESIS_24 = 0b0001, - A_HYSTERESIS_32 = 0b0010, - A_HYSTERESIS_48 = 0b0011, - A_HYSTERESIS_64 = 0b0100, - A_HYSTERESIS_96 = 0b0101, - A_HYSTERESIS_128 = 0b0110, - A_HYSTERESIS_256 = 0b0111, - A_HYSTERESIS_512 = 0b1000, - A_HYSTERESIS_1024 = 0b1001, - A_HYSTERESIS_2K = 0b1010, - A_HYSTERESIS_4K = 0b1011, - A_HYSTERESIS_8K = 0b1100, - A_HYSTERESIS_16K = 0b1101, - A_HYSTERESIS_32K = 0b1110, - A_HYSTERESIS_64K = 0b1111 -}; - -/// -/// @brief Lanes disabled -/// -enum -{ - LANE_DISABLED_NONE = 0b00000000, - LANE_DISABLED_7 = 0b00000001, - LANE_DISABLED_6 = 0b00000010, - LANE_DISABLED_5 = 0b00000100, - LANE_DISABLED_4 = 0b00001000, - LANE_DISABLED_3 = 0b00010000, - LANE_DISABLED_2 = 0b00100000, - LANE_DISABLED_1 = 0b01000000, - LANE_DISABLED_0 = 0b10000000 -}; - -/// -/// @brief dl0 inject crc direction -/// -enum crc_inject_dir -{ - CRC_DIR_RX = 0, - CRC_DIR_TX = 1 -}; - -/// -/// @brief dl0 crc injection rate -/// -enum crc_inject_rate -{ - CRC_INJ_RATE_1US = 0b0000, - CRC_INJ_RATE_8US = 0b0001, - CRC_INJ_RATE_64US = 0b0010, - CRC_INJ_RATE_512US = 0b0011, - CRC_INJ_RATE_4MS = 0b0100, - CRC_INJ_RATE_32MS = 0b0101, - CRC_INJ_RATE_256MS = 0b0110, - CRC_INJ_RATE_2S = 0b0111 -}; - -/// -/// @brief CFG_DL0_EDPL_TIME: dl0 edpl time window -/// -enum edpl_time_win -{ - EDPL_TIME_WIN_NO = 0b0000, - EDPL_TIME_WIN_4US = 0b0001, - EDPL_TIME_WIN_32US = 0b0010, - EDPL_TIME_WIN_256US = 0b0011, - EDPL_TIME_WIN_2MS = 0b0100, - EDPL_TIME_WIN_16MS = 0b0101, - EDPL_TIME_WIN_128MS = 0b0110, - EDPL_TIME_WIN_1S = 0b0111, - EDPL_TIME_WIN_8S = 0b1000, - EDPL_TIME_WIN_64S = 0b1001, - EDPL_TIME_WIN_512S = 0b1010, - EDPL_TIME_WIN_4KS = 0b1011, - EDPL_TIME_WIN_32KS = 0b1100, - EDPL_TIME_WIN_256KS = 0b1101, - EDPL_TIME_WIN_2MILLIONS = 0b1110, - EDPL_TIME_WIN_16MILLIONS = 0b1111 -}; - -/// -/// @brief CFG_DL0_EDPL_THRESHOLD: dl0 edpl threshold -/// -enum edpl_err_thres -{ - EDPL_ERR_THRES_DISABLED = 0b000, - EDPL_ERR_THRES_2 = 0b001, - EDPL_ERR_THRES_4 = 0b010, - EDPL_ERR_THRES_8 = 0b011, - EDPL_ERR_THRES_16 = 0b100, - EDPL_ERR_THRES_32 = 0b101, - EDPL_ERR_THRES_64 = 0b110, - EDPL_ERR_THRES_128 = 0b111 -}; - -/// -/// @brief CONFIG1_CFG_PREIPL_PRBS_TIME: config1 pre-ipl prbs time -/// -enum preipl_prbs_time -{ - PREIPL_PRBS_256US = 0b000, - PREIPL_PRBS_1US = 0b001, - PREIPL_PRBS_4MS = 0b010, - PREIPL_PRBS_16MS = 0b011, - PREIPL_PRBS_64MS = 0b100, - PREIPL_PRBS_256MS = 0b101, - PREIPL_PRBS_1S = 0b110, - PREIPL_PRBS_4S = 0b111 -}; - -/// -/// @brief Helper function to setup the CMN_CONFIG +/// @brief Function to setup the CMN_CONFIG /// @tparam PROC the proc type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi @@ -382,31 +66,31 @@ enum preipl_prbs_time /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_mcn_config_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_mcn_config(const fapi2::Target<T>& i_target) { // The value is 0x042364008874630F fapi2::buffer<uint64_t> l_val; // CFG_CMN_SPARE: Spare - l_val.template insertFromRight< TT::MC_REG0_CMN_CONFIG_SPARE, TT::MC_REG0_CMN_CONFIG_SPARE_LEN>(0); + l_val.insertFromRight< TT::MC_REG0_CMN_CONFIG_SPARE, TT::MC_REG0_CMN_CONFIG_SPARE_LEN>(0); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_PM_CDR_TIMER, TT::MC_REG0_CMN_CONFIG_PM_CDR_TIMER_LEN> - (CDR_TIMER_250NS); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_PM_CDR_TIMER, TT::MC_REG0_CMN_CONFIG_PM_CDR_TIMER_LEN> + (mss::omi::rx_cdr_timer::CDR_TIMER_250NS); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_PM_DIDT_TIMER, TT::MC_REG0_CMN_CONFIG_PM_DIDT_TIMER_LEN> - (DIDT_TIMER_10NS); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_PM_DIDT_TIMER, TT::MC_REG0_CMN_CONFIG_PM_DIDT_TIMER_LEN> + (mss::omi::didt_timer::DIDT_TIMER_10NS); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_PSAV_STS_ENABLE>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_PSAV_STS_ENABLE>(0); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_RECAL_TIMER, TT::MC_REG0_CMN_CONFIG_RECAL_TIMER_LEN> - (RECAL_TIMER_100MS); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_RECAL_TIMER, TT::MC_REG0_CMN_CONFIG_RECAL_TIMER_LEN> + (mss::omi::recal_timer::RECAL_TIMER_100MS); // CFG_CMN_1US_TMR: Number of cycles in 1us. Needs to be changed based on clock frequency - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR, TT::MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR_LEN> + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR, TT::MC_REG0_CMN_CONFIG_CFG_CMN_1US_TMR_LEN> (1600); // CFG_CMN_DBG_EN: Enable the debug logic - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CFG_CMN_DBG_EN>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CFG_CMN_DBG_EN>(0); // CFG_CMN_DBG_SEL: Debug select // 000 - zeros @@ -419,40 +103,48 @@ fapi2::ReturnCode setup_mc_mcn_config_helper(const fapi2::Target<T>& i_target) // 11 bits from all 3 DLs plus // 33 bits from common macro 2 // 111 - zeros - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_DBG_SEL, TT::MC_REG0_CMN_CONFIG_DBG_SEL_LEN>(0); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_DBG_SEL, TT::MC_REG0_CMN_CONFIG_DBG_SEL_LEN>(0); // CFG_CMN_RD_RST: Reset the PMU counters when the PMU counters are read - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_RD_RST>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_RD_RST>(1); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_PRE_SCALAR, TT::MC_REG0_CMN_CONFIG_PRE_SCALAR_LEN> - (PRESCALAR_16BIT); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_PRE_SCALAR, TT::MC_REG0_CMN_CONFIG_PRE_SCALAR_LEN> + (mss::omi::pmu_prescalar::PRESCALAR_16BIT); // CFG_CMN_FREEZE: PMU freeze mode - when set, the PMU will stop all counters when 1 of the counters wraps. - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CFG_CMN_FREEZE>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CFG_CMN_FREEZE>(1); // CFG_CMN_PORT_SEL: PMU port select - select which of the 8 groups of inputs will be used by the PMU. - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_PORT_SEL, TT::MC_REG0_CMN_CONFIG_PORT_SEL_LEN>(0); - - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR3_PS, TT::MC_REG0_CMN_CONFIG_CNTR3_PS_LEN>(SEL_EVEN); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR3_ES, TT::MC_REG0_CMN_CONFIG_CNTR3_ES_LEN>(SIG_1_0); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR2_PS, TT::MC_REG0_CMN_CONFIG_CNTR2_PS_LEN>(SEL_EVEN); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR2_ES, TT::MC_REG0_CMN_CONFIG_CNTR2_ES_LEN>(SIG_7_6); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR1_PS, TT::MC_REG0_CMN_CONFIG_CNTR1_PS_LEN>(SEL_EVEN); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR1_ES, TT::MC_REG0_CMN_CONFIG_CNTR1_ES_LEN>(SIG_3_2); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR0_PS, TT::MC_REG0_CMN_CONFIG_CNTR0_PS_LEN>(SEL_ODD); - l_val.template insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR0_ES, TT::MC_REG0_CMN_CONFIG_CNTR0_ES_LEN>(SIG_1_0); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_PORT_SEL, TT::MC_REG0_CMN_CONFIG_PORT_SEL_LEN>(0); + + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR3_PS, TT::MC_REG0_CMN_CONFIG_CNTR3_PS_LEN>( + mss::omi::cntrl_pair_selector::SEL_EVEN); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR3_ES, TT::MC_REG0_CMN_CONFIG_CNTR3_ES_LEN>( + mss::omi::cntrl_event_selector::SIG_1_0); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR2_PS, TT::MC_REG0_CMN_CONFIG_CNTR2_PS_LEN>( + mss::omi::cntrl_pair_selector::SEL_EVEN); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR2_ES, TT::MC_REG0_CMN_CONFIG_CNTR2_ES_LEN>( + mss::omi::cntrl_event_selector::SIG_7_6); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR1_PS, TT::MC_REG0_CMN_CONFIG_CNTR1_PS_LEN>( + mss::omi::cntrl_pair_selector::SEL_EVEN); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR1_ES, TT::MC_REG0_CMN_CONFIG_CNTR1_ES_LEN>( + mss::omi::cntrl_event_selector::SIG_3_2); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR0_PS, TT::MC_REG0_CMN_CONFIG_CNTR0_PS_LEN>( + mss::omi::cntrl_pair_selector::SEL_ODD); + l_val.insertFromRight<TT::MC_REG0_CMN_CONFIG_CNTR0_ES, TT::MC_REG0_CMN_CONFIG_CNTR0_ES_LEN>( + mss::omi::cntrl_event_selector::SIG_1_0); // CFG_CMN_CNTRx_PE: PMU cntrx positive edge select - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR3_PE>(0); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR2_PE>(0); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR1_PE>(0); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR0_PE>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR3_PE>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR2_PE>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR1_PE>(0); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR0_PE>(0); // CFG_CMN_CNTRx_EN: PMU cntrx enable - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR3_EN>(1); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR2_EN>(1); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR1_EN>(1); - l_val.template writeBit<TT::MC_REG0_CMN_CONFIG_CNTR0_EN>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR3_EN>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR2_EN>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR1_EN>(1); + l_val.writeBit<TT::MC_REG0_CMN_CONFIG_CNTR0_EN>(1); FAPI_TRY( mss::putScom(i_target, TT::MC_REG0_CMN_CONFIG, l_val) ); FAPI_TRY( mss::putScom(i_target, TT::MC_REG1_CMN_CONFIG, l_val) ); @@ -463,24 +155,30 @@ fapi_try_exit: } /// -/// @brief Helper function to set the CONFIG0 +/// @brief Function to set the CONFIG0 for the given train mode and backoff_en bit /// @tparam PROC the proc type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi /// @param[in] i_target the OMI target to operate on +/// @param[in] i_train_mode training step to enable +/// @param[in] i_dl_x4_backoff_en backoff enable mode /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_config0( + const fapi2::Target<T>& i_target, + const uint8_t i_train_mode, + const uint8_t i_dl_x4_backoff_en) { // The value is 0x8200040000152824 fapi2::buffer<uint64_t> l_val; + uint8_t l_dl_tx_ln_rev_en = 1; // CFG_DL0_ENABLE: dl0 enabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ENABLE>(1); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ENABLE>(1); // CFG_DL0_CFG_SPARE: dl0 Spare - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE, TT::MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE_LEN>(0); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE, TT::MC_REG2_DL0_CONFIG0_CFG_CFG_SPARE_LEN>(0); // CFG_DL0_CFG_TL_CREDITS: dl0 TL credits - Maximum number of credits that can be sent to the TL l_val.template @@ -491,23 +189,25 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target) // Bit 1 = Freeze afu, leave TL and DL running // Bit 2 = Trigger Internal Logic Analyzers // Bit 3 = Bring down the link - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS, - TT::MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN>(0); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS, TT::MC_REG2_DL0_CONFIG0_CFG_TL_EVENT_ACTIONS_LEN>(0); // CFG_DL0_TL_ERROR_ACTIONS: dl0 TL error actions // Bit 0 = Freeze all // Bit 1 = Freeze afu, leave TL and DL running // Bit 2 = Trigger Internal Logic Analyzers // Bit 3 = Bring down the link - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS, - TT::MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN>(0); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS, TT::MC_REG2_DL0_CONFIG0_CFG_TL_ERROR_ACTIONS_LEN>(0); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER, - TT::MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN>(NO_FORWARD_TIMER_16US); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER, TT::MC_REG2_DL0_CONFIG0_CFG_FWD_PROGRESS_TIMER_LEN>( + mss::omi::no_forward_progress_timer::NO_FORWARD_TIMER_16US); // CFG_DL0_REPLAY_RSVD_ENTRIES: dl0 replay buffers reserved - times 16 is the number of replay buffers reserved - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES, - TT::MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN>(0); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES, TT::MC_REG2_DL0_CONFIG0_CFG_REPLAY_RSVD_ENTRIES_LEN> + (0); // CFG_DL0_DEBUG_SELECT: dl0 trace mux select // "000" = zeros @@ -518,66 +218,73 @@ fapi2::ReturnCode setup_mc_config0_helper(const fapi2::Target<T>& i_target) // "101" = 11 bits of TX flit information // "110" = 11 bits of Tx training information // "111" = zeros - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT, TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN> + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT, TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_SELECT_LEN> (0); // CFG_DL0_DEBUG_ENABLE: dl0 trace enable - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_ENABLE>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DEBUG_ENABLE>(0); // CFG_DL0_DL2TL_DATA_PARITY_INJECT: dl0 inject a data parity error - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DL2TL_DATA_PARITY_INJECT>(0); // CFG_DL0_DL2TL_CONTROL_PARITY_INJECT: dl0 inject a control parity error - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_DL2TL_CONTROL_PARITY_INJECT>(0); // CFG_DL0_ECC_UE_INJECTION: dl0 inject a ECC UE error - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ECC_UE_INJECTION>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ECC_UE_INJECTION>(0); // CFG_DL0_ECC_CE_INJECTION: dl0 inject a ECC CE error - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ECC_CE_INJECTION>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_ECC_CE_INJECTION>(0); // CFG_DL0_FP_DISABLE: dl0 fastpath disabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_FP_DISABLE>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_FP_DISABLE>(0); // CFG_DL0_UNUSED2: dl0 Spare - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_UNUSED2>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_UNUSED2>(0); // CFG_DL0_TX_LN_REV_ENA: When set will allow dl0 to perform tx lane reversals. - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA>(0); + FAPI_TRY(mss::attr::get_omi_dl_ln_rev_enable(i_target, l_dl_tx_ln_rev_en), + "Error from FAPI_ATTR_GET (ATTR_OMI_DL_LN_REV_ENABLE)"); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_LN_REV_ENA>(l_dl_tx_ln_rev_en); // CFG_DL0_128_130_ENCODING_ENABLED: dl0 128/130 encoding enabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_128_130_ENCODING_ENABLED>(0); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT, - TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN>(PHY_CTR_MODE_50US); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT, TT::MC_REG2_DL0_CONFIG0_CFG_PHY_CNTR_LIMIT_LEN>( + mss::omi::phy_ctr_mode::PHY_CTR_MODE_60MS); // CFG_DL0_RUNLANE_OVRD_ENABLE: When enabled, the dl0 will drive run lane to the PHY for all training states. - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_EP_MODE>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_TX_EP_MODE>(0); // CFG_DL0_PWRMGT_ENABLE: dl0 power management enabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE>(1); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_PWRMGT_ENABLE>(0); // CFG_DL0_QUARTER_WIDTH_BACKOFF_ENABLE: dl0 x1 backoff enabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X1_BACKOFF_ENABLE>(0); // CFG_DL0_HALF_WIDTH_BACKOFF_ENABLE: dl0 x4 backoff enabled - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE>(1); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_X4_BACKOFF_ENABLE>(i_dl_x4_backoff_en); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES, - TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN>(LINK_WIDTHS_X8); + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES, TT::MC_REG2_DL0_CONFIG0_CFG_SUPPORTED_MODES_LEN>( + mss::omi::link_widths::LINK_WIDTHS_X8); // CFG_DL0_TRAIN_MODE: dl0 train mode - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE, TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE_LEN> - (ENABLE_AUTO_TRAINING); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE, TT::MC_REG2_DL0_CONFIG0_CFG_TRAIN_MODE_LEN>( + i_train_mode); // CFG_DL0_VERSION: dl0 version number - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_VERSION, TT::MC_REG2_DL0_CONFIG0_CFG_VERSION_LEN>(9); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG0_CFG_VERSION, TT::MC_REG2_DL0_CONFIG0_CFG_VERSION_LEN>(9); // CFG_DL0_RETRAIN: dl0 retrain - Reset dl0 back to training state 4 - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_RETRAIN>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_RETRAIN>(0); // CFG_DL0_RESET: dl0 reset - Reset dl0 back to traning state 0 - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_RESET>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG0_CFG_RESET>(0); + + FAPI_DBG("Writing 0x%16llx to MC_REG2_DL0_CONFIG0 (0x%16llx) of %s", + l_val, TT::MC_REG2_DL0_CONFIG0, mss::c_str(i_target)); FAPI_TRY( mss::putScom(i_target, TT::MC_REG2_DL0_CONFIG0, l_val) ); @@ -586,7 +293,7 @@ fapi_try_exit: } /// -/// @brief Helper function to set the CONFIG1 +/// @brief Function to setup the CONFIG1 /// @tparam PROC the proc type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi @@ -594,28 +301,30 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_config1(const fapi2::Target<T>& i_target) { // The value is 0x0C00050000000059; fapi2::buffer<uint64_t> l_val; uint8_t l_sim = 0; + uint8_t l_edpl_disable = 0; FAPI_TRY( mss::attr::get_is_simulation( l_sim) ); // CFG_DL0_CFG1_PREIPL_PRBS - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME, - TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>(l_sim ? PREIPL_PRBS_1US : PREIPL_PRBS_64MS); - - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, 1>(1); // Enable + l_val.template + insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME, TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_TIME_LEN>( + l_sim ? mss::omi::preipl_prbs_time::PREIPL_PRBS_1US : mss::omi::preipl_prbs_time::PREIPL_PRBS_256MS); + // PRE-IPL PRBS Timing is not functional in Axone, so set to disable + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_PREIPL_PRBS_ENA, 1>(0); // Disable - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH, - TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN>(TL_CTR_BY_SIDEBAND); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH, TT::MC_REG2_DL0_CONFIG1_CFG_LANE_WIDTH_LEN>( + mss::omi::lan_width_override::TL_CTR_BY_SIDEBAND); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS, - TT::MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN>(B_HYSTERESIS_16); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS, TT::MC_REG2_DL0_CONFIG1_CFG_B_HYSTERESIS_LEN>( + mss::omi::b_hysteresis::B_HYSTERESIS_16); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS, - TT::MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN>(A_HYSTERESIS_16); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS, TT::MC_REG2_DL0_CONFIG1_CFG_A_HYSTERESIS_LEN>( + mss::omi::a_hysteresis::A_HYSTERESIS_16); // CFG_DL0_B_PATTERN_LENGTH: Number of consecutive 1s and 0s needed to represent training Pattern // B=> "11111111111111110000000000000000" @@ -623,8 +332,8 @@ fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target<T>& i_target) // "10" = four Xs => "111111111111XXXX000000000000XXXX" // "01" = one Xs => "111111111111111X000000000000000X" // "11" = same as "10" - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH, - TT::MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN>(0); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH, + TT::MC_REG2_DL0_CONFIG1_CFG_B_PATTERN_LENGTH_LEN>(0); // CFG_DL0_A_PATTERN_LENGTH: Number of consecutive 1s and 0s needed to represent training Pattern // A => "1111111100000000" @@ -632,62 +341,63 @@ fapi2::ReturnCode setup_mc_config1_helper(const fapi2::Target<T>& i_target) // "10" = four Xs => "1111XXXX0000XXXX" // "01" = one Xs => "1111111X0000000X" // "11" = same as "10" - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH, - TT::MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN>(0); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH, + TT::MC_REG2_DL0_CONFIG1_CFG_A_PATTERN_LENGTH_LEN>(0); // CFG_DL0_TX_PERF_DEGRADED: "00" = if tx perf is degraded by 1% set error bit 25 // "01" = if tx perf is degraded by 2% set error bit 25 // "10" = if tx perf is degraded by 3% set error bit 25 // "11" = if tx perf is degraded by 4% set error bit 25 - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED, - TT::MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN>(1); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED, + TT::MC_REG2_DL0_CONFIG1_CFG_TX_PERF_DEGRADED_LEN>(1); // CFG_DL0_RX_PERF_DEGRADED: "00" = if rx performance is degraded by 1% set error bit 26 // "01" = if rx perf is degraded by 2% set error bit 26 // "10" = if rx perf is degraded by 3% set error bit 26 // "11" = if rx perf is degraded by 4% set error bit 26 - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED, - TT::MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN>(1); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED, + TT::MC_REG2_DL0_CONFIG1_CFG_RX_PERF_DEGRADED_LEN>(1); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE, - TT::MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN>(LANE_DISABLED_NONE); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE, + TT::MC_REG2_DL0_CONFIG1_CFG_TX_LANES_DISABLE_LEN>(mss::omi::LANE_DISABLED_NONE); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE, - TT::MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN>(LANE_DISABLED_NONE); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE, + TT::MC_REG2_DL0_CONFIG1_CFG_RX_LANES_DISABLE_LEN>(mss::omi::LANE_DISABLED_NONE); // CFG_DL0_RESET_ERR_HLD: dl0 reset the error hold register when it is read - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_HLD>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_HLD>(0); // CFG_DL0_RESET_ERR_CAP: dl0 reset the error capture register when it is read - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_CAP>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_ERR_CAP>(0); // CFG_DL0_RESET_TSHD_REG: dl0 reset the edpl threshold register when it is read - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_TSHD_REG>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_TSHD_REG>(0); // CFG_DL0_RESET_RMT_MSG: dl0 reset the remote register when it is read - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_RMT_MSG>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_RESET_RMT_MSG>(0); // CFG_DL0_INJECT_CRC_DIRECTION: dl0 inject crc direction - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION>(CRC_DIR_RX); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_DIRECTION>(mss::omi::crc_inject_dir::CRC_DIR_RX); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE, - TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN>(CRC_INJ_RATE_1US); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE, + TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_RATE_LEN>(mss::omi::crc_inject_rate::CRC_INJ_RATE_1US); // CFG_DL0_INJECT_CRC_LANE: dl0 inject crc error on lane number l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE, TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_LANE_LEN>(0); // CFG_DL0_INJECT_CRC_ERROR: dl0 inject crc error enable - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_ERROR>(0); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_INJECT_CRC_ERROR>(0); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME, - TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME_LEN>(EDPL_TIME_WIN_16MS); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME, + TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_TIME_LEN>(mss::omi::edpl_time_win::EDPL_TIME_WIN_16MS); - l_val.template insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD, - TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN>(EDPL_ERR_THRES_16); + l_val.insertFromRight<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD, + TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_THRESHOLD_LEN>(mss::omi::edpl_err_thres::EDPL_ERR_THRES_16); // CFG_DL0_EDPL_ENA: dl0 error detection per lane "edpl" enable - l_val.template writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_ENA>(1); + FAPI_TRY(mss::attr::get_mss_omi_edpl_disable(l_edpl_disable)); + l_val.writeBit<TT::MC_REG2_DL0_CONFIG1_CFG_EDPL_ENA>(l_edpl_disable ? 0 : 1); FAPI_TRY( mss::putScom(i_target, TT::MC_REG2_DL0_CONFIG1, l_val) ); @@ -696,7 +406,7 @@ fapi_try_exit: } /// -/// @brief Helper function to set the DL0_CYA_BITS +/// @brief Function to set the DL0_CYA_BITS /// @tparam PROC the proc type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi @@ -704,7 +414,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_cya_bits_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_cya_bits(const fapi2::Target<T>& i_target) { fapi2::buffer<uint64_t> l_val; @@ -719,7 +429,7 @@ fapi_try_exit: } /// -/// @brief Helper function to set the DL0_ERROR_ACTION +/// @brief Function to set the DL0_ERROR_ACTION /// @tparam PROC the memory controller type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi @@ -727,7 +437,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_error_action_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_error_action(const fapi2::Target<T>& i_target) { fapi2::buffer<uint64_t> l_val; @@ -753,7 +463,7 @@ fapi_try_exit: /// -/// @brief Helper function to set the DL0_RMT_CONFIG +/// @brief Function to set the DL0_RMT_CONFIG /// @tparam PROC the proc type /// @tparam T the fapi2 target type of the target /// @tparam TT the class traits for the omi @@ -761,7 +471,7 @@ fapi_try_exit: /// @return FAPI2_RC_SUCCESS iff ok /// template< mss::proc_type PROC = DEFAULT_PROC_TYPE, fapi2::TargetType T, typename TT = omiTraits<T, PROC>> -fapi2::ReturnCode setup_mc_rmt_config_helper(const fapi2::Target<T>& i_target) +fapi2::ReturnCode setup_mc_rmt_config(const fapi2::Target<T>& i_target) { fapi2::buffer<uint64_t> l_val; diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.H b/src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.C index 76f5cd416..e27f6cef5 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.C @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/exp_config_thermal.H $ */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits.H b/src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.H index 86f274e54..8ccc4ab9c 100644 --- a/src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.H @@ -1,11 +1,11 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/import/chips/ocmb/explorer/procedures/hwp/memory/lib/ecc/ecc_traits.H $ */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/plug_rules/p9a_plug_rules.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/shared/axone_consts.H b/src/import/chips/p9a/procedures/hwp/memory/lib/shared/axone_consts.H index c2ef9aee8..dcca78fa0 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/lib/shared/axone_consts.H +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/shared/axone_consts.H @@ -39,4 +39,8 @@ #include <generic/memory/lib/utils/shared/mss_generic_consts.H> +const uint8_t MAX_MC_SIDES_PER_PROC = 2; // MC01, MC23 +const uint8_t MAX_MC_PER_PROC = 4; // MC0, MC1, MC2, MC3 +const uint8_t MAX_MC_PER_SIDE = 2; // MC0, MC1 or MC2, MC3 + #endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C new file mode 100644 index 000000000..783091c62 --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C @@ -0,0 +1,212 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_workarounds.C +/// @brief Workarounds for p9a_omi_* procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: Memory + +#include <fapi2.H> +#include <lib/shared/axone_defaults.H> +#include <p9a_mc_scom_addresses.H> +#include <p9a_mc_scom_addresses_fld.H> +#include <p9a_mc_scom_addresses_fixes.H> +#include <p9a_mc_scom_addresses_fld_fixes.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/mss_generic_system_attribute_getters.H> +#include <generic/memory/lib/mss_generic_attribute_getters.H> +#include <lib/mc/omi.H> +#include <lib/mc/omi_traits.H> +#include <lib/workarounds/p9a_omi_workarounds.H> + +namespace mss +{ +namespace workarounds +{ +namespace mc +{ +/// +/// @brief Helper function to determine whether PRBS OMI workaround will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +{ + // OMI Workaround Logic: + // Explorer+Axone: OMI/PROC-side workaround off + // Gemini+Axone: OMI/PROC-side workaround on + // Any+apollo: OMI/PROC-side workaround on + // P10: No workarounds required. Enums don't exist yet, so this must be revisited later + return ((i_proc_type != fapi2::ENUM_ATTR_NAME_AXONE) || (i_ocmb_type == fapi2::ENUM_ATTR_NAME_GEMINI)); // Gem && axone +} + +/// +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type) +{ + // OMI Workaround Logic: + // Explorer+Axone: Workaround on. + // Else: None + return ((i_proc_type == fapi2::ENUM_ATTR_NAME_AXONE) + && (i_ocmb_type == fapi2::ENUM_ATTR_NAME_EXPLORER)); // Explorer && axone +} + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi) +{ + uint8_t l_sim = 0; + uint32_t l_prbs_time = 0; + uint64_t l_prbs_time_scaled = 0; + + FAPI_TRY( mss::attr::get_is_simulation( l_sim) ); + + FAPI_TRY(mss::attr::get_omi_dl_preipl_prbs_time(i_omi, l_prbs_time), + "Error from FAPI_ATTR_GET (ATTR_OMI_DL_PREIPL_PRBS_TIME)"); + l_prbs_time_scaled = l_prbs_time * mss::common_timings::DELAY_1MS; + + FAPI_TRY(fapi2::delay(l_prbs_time_scaled, mss::common_timings::DELAY_1US)); + FAPI_DBG("OMI Training Pre-ipl PRBS Time = %dns", + (l_sim ? mss::common_timings::DELAY_1US : l_prbs_time_scaled)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Get PROC and OCMB types +/// +/// @param[in] i_ocmb_chip OCMB chip +/// @param[in] i_proc_chip PROC chip +/// @param[out] o_required workaround required +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode get_ocmb_proc_types( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> i_proc_chip, + uint8_t& o_ocmb_type, + uint8_t& o_proc_type) +{ + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_ocmb_chip, o_ocmb_type), + "Error getting ATTR_NAME of %s", mss::c_str(i_ocmb_chip)); + + FAPI_TRY(FAPI_ATTR_GET_PRIVILEGED(fapi2::ATTR_NAME, i_proc_chip, o_proc_type), + "Error getting ATTR_NAME of %s", mss::c_str(i_proc_chip)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform the PRBS OMI workaround for gemini configurations +/// +/// @param[in] i_omi OMI +/// @param[in] i_dl_x4_backoff_en backoff enable bit +/// @return fapi2::FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode omi_training_prbs_gem( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing PRBS OMI workaround on %s", mss::c_str(i_omi)); + + // *_CONFIG0 should be the last one written, since it starts the training. + // We are not using the pre-ipl PRBS auto training mode because it doesn't function properly in Axone + + // Enable training state 6 to send TS3 + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE3, i_dl_x4_backoff_en)); + + FAPI_TRY(prbs_delay(i_omi)); + + // Enable training state 1 to send Pattern A + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Train axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 1: send Pattern A + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_PATTERN_A, i_dl_x4_backoff_en)); + + FAPI_TRY(fapi2::delay(100 * mss::common_timings::DELAY_1MS, mss::common_timings::DELAY_1MS)); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en) +{ + FAPI_DBG("Performing OMI Setup axone workaround on %s", mss::c_str(i_omi)); + + // Training mode 4: send State 1 + FAPI_TRY(mss::mc::setup_mc_config0(i_omi, mss::omi::train_mode::TX_TRAINING_STATE1, i_dl_x4_backoff_en)); + + FAPI_TRY(prbs_delay(i_omi)); + +fapi_try_exit: + return fapi2::current_err; +} + +} // mc +} // workarounds +} // mss diff --git a/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H new file mode 100644 index 000000000..4491a91e3 --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H @@ -0,0 +1,124 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/lib/workarounds/p9a_omi_workarounds.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_workarounds.H +/// @brief Workarounds for p9a_omi_* procedures +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Stephen Glancy <sglancy@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: Memory + +#ifndef P9A_OMI_WORKAROUNDS_H_ +#define P9A_OMI_WORKAROUNDS_H_ + +#include <fapi2.H> + +namespace mss +{ +namespace workarounds +{ +namespace mc +{ +/// +/// @brief Helper function to determine whether PRBS OMI workaround will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); + +/// +/// @brief Helper function to determine whether PRBS axone OMI workarounds will be performed, that can be unit tested +/// +/// @param[in] i_ocmb_type OCMB type/name +/// @param[in] i_proc_type PROC type/name +/// @return true/false perform workaround +/// +bool is_prbs_omi_axone_required(const uint8_t i_ocmb_type, const uint8_t i_proc_type); + +/// +/// @brief Perform PRBS delay from prbs time and sim attributes +/// +/// @param[in] i_omi OMI target +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success, else error code +/// +fapi2::ReturnCode prbs_delay(const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_omi); + +/// +/// @brief Get PROC and OCMB types +/// +/// @param[in] i_ocmb_chip OCMB chip +/// @param[in] i_proc_chip PROC chip +/// @param[out] o_required workaround required +/// @return FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode get_ocmb_proc_types( + const fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> i_ocmb_chip, + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> i_proc_chip, + uint8_t& o_ocmb_type, + uint8_t& o_proc_type); + +/// +/// @brief Perform the PRBS OMI workaround for gemini configurations +/// +/// @param[in] i_omi OMI +/// @param[in] i_dl_x4_backoff_en backoff enable bit +/// @return fapi2::FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode omi_training_prbs_gem( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_train workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en); + +/// +/// @brief Perform p9a_omi_setup (pre-training) workaround for Axone+Explorer +/// +/// @param[in] i_omi OMI target +/// @param[in] i_dl_x4_backoff_en backoff enable field +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS iff success +/// +fapi2::ReturnCode pre_omi_training_prbs( + const fapi2::Target<fapi2::TARGET_TYPE_OMI> i_omi, + const uint8_t i_dl_x4_backoff_en); + +} // namespace mc +} // namespace workarounds +} // namespace mss + +#endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_bulk_pwr_throttles.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_bulk_pwr_throttles.mk index aff426ea7..8c936264d 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_bulk_pwr_throttles.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_bulk_pwr_throttles.mk @@ -25,5 +25,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_mss_bulk_pwr_throttles -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C index 75d23c6af..7a62e36a0 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.C @@ -33,17 +33,24 @@ // *HWP Level: 1 // *HWP Consumed by: FSP:HB -// fapi2 #include <fapi2.H> #include <p9a_mss_eff_config.H> +#include <lib/shared/exp_defaults.H> +#include <lib/dimm/exp_rank.H> +#include <generic/memory/lib/utils/mss_rank.H> #include <generic/memory/lib/data_engine/data_engine.H> #include <generic/memory/lib/utils/find.H> #include <generic/memory/lib/spd/ddimm/efd_factory.H> #include <vpd_access.H> #include <mss_generic_attribute_getters.H> +#include <generic/memory/lib/data_engine/attr_engine_traits.H> #include <lib/eff_config/explorer_attr_engine_traits.H> +#include <lib/eff_config/pmic_attr_engine_traits.H> +#include <lib/eff_config/explorer_efd_processing.H> +#include <lib/eff_config/pmic_efd_processing.H> #include <lib/freq/axone_freq_traits.H> #include <lib/freq/axone_sync.H> +#include <generic/memory/mss_git_data_helper.H> /// /// @brief Configure the attributes for each controller @@ -52,23 +59,22 @@ /// fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target ) { - // Workaround until DIMM level attrs work - uint8_t l_ranks[mss::exp::MAX_DIMM_PER_PORT] = {}; + using mss::DEFAULT_MC_TYPE; - FAPI_TRY( mss::attr::get_num_master_ranks_per_dimm(i_target, l_ranks) ); + mss::display_git_commit_info("p9a_mss_eff_config"); for(const auto& dimm : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) { - uint8_t l_dimm_index = 0; uint64_t l_freq = 0; - uint64_t l_omi_freq = 0; - FAPI_TRY( mss::attr::get_freq(mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(dimm), l_freq) ); - FAPI_TRY( mss::convert_ddr_freq_to_omi_freq(mss::find_target<fapi2::TARGET_TYPE_MEM_PORT>(dimm), l_freq, l_omi_freq)); + uint32_t l_omi_freq = 0; + FAPI_TRY( mss::attr::get_freq(i_target, l_freq) ); + FAPI_TRY( mss::convert_ddr_freq_to_omi_freq(i_target, l_freq, l_omi_freq)); - // Quick hack to get the index until DIMM level attrs work - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_REL_POS, dimm, l_dimm_index) ); + // Get ranks via rank API + std::vector<mss::rank::info<>> l_ranks; + mss::rank::ranks_on_dimm(dimm, l_ranks); - for( auto rank = 0; rank < l_ranks[l_dimm_index]; ++rank ) + for (const auto& l_rank : l_ranks) { std::shared_ptr<mss::efd::base_decoder> l_efd_data; @@ -76,7 +82,7 @@ fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM const auto l_ocmb = mss::find_target<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); fapi2::MemVpdData_t l_vpd_type(fapi2::MemVpdData::EFD); fapi2::VPDInfo<fapi2::TARGET_TYPE_OCMB_CHIP> l_vpd_info(l_vpd_type); - l_vpd_info.iv_rank = rank; + l_vpd_info.iv_rank = l_rank.get_dimm_rank(); l_vpd_info.iv_omi_freq_mhz = l_omi_freq; FAPI_TRY( fapi2::getVPD(l_ocmb, l_vpd_info, nullptr), "failed getting VPD size from getVPD" ); @@ -88,7 +94,13 @@ fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM FAPI_TRY( mss::efd::factory(l_ocmb, l_vpd_raw, l_vpd_info.iv_rank, l_efd_data) ); // Set up SI ATTRS - FAPI_TRY( mss::attr_si_engine<mss::attr_si_engine_fields>::set(l_efd_data) ); + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::attr_si_engine_fields>::set(l_efd_data)) ); + + // Explorer EFD + FAPI_TRY( mss::exp::efd::process(dimm, l_efd_data)); + + // PMIC EFD + FAPI_TRY(mss::pmic::efd::process(dimm, l_efd_data)); } { @@ -103,12 +115,19 @@ fapi2::ReturnCode p9a_mss_eff_config( const fapi2::Target<fapi2::TARGET_TYPE_MEM FAPI_TRY( l_rc, "Failed to initialize SPD facade for %s", mss::spd::c_str(dimm) ); // Set up generic SPD ATTRS - FAPI_TRY( mss::attr_eff_engine<mss::attr_eff_engine_fields>::set(l_spd_decoder) ); + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::attr_eff_engine_fields>::set(l_spd_decoder)) ); // Set up explorer SPD ATTRS - FAPI_TRY( mss::attr_eff_engine<mss::exp::attr_eff_engine_fields>::set(l_spd_decoder) ); + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::exp::attr_eff_engine_fields>::set(l_spd_decoder)) ); + + // Set up pmic SPD ATTRS + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::pmic::attr_eff_engine_fields>::set(l_spd_decoder)) ); } } + + // Set up derived ATTRS + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::attr_engine_derived_fields>::set(dimm)) ); + }// dimm fapi_try_exit: diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.mk index 65e376f98..a01aeb9ee 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_eff_config.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.C index 342523d5a..4e8db7142 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,43 +40,56 @@ #include <p9a_mss_freq.H> #include <lib/freq/axone_freq_traits.H> -#include <generic/memory/lib/data_engine/p9a/p9a_data_init_traits.H> +#include <lib/eff_config/p9a_data_init_traits.H> #include <lib/eff_config/explorer_attr_engine_traits.H> #include <generic/memory/lib/data_engine/data_engine.H> #include <generic/memory/lib/utils/find.H> #include <generic/memory/lib/spd/spd_facade.H> #include <generic/memory/lib/utils/count_dimm.H> #include <generic/memory/lib/utils/freq/gen_mss_freq.H> +#include <generic/memory/mss_git_data_helper.H> /// /// @brief Calculate and save off DIMM frequencies /// @param[in] i_target port target /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode p9a_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target ) +fapi2::ReturnCode p9a_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ) { + mss::display_git_commit_info("p9a_mss_freq"); + // If there are no DIMM, we can just get out. - if (mss::count_dimm(i_target) == 0) + if (mss::count_dimm(mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) == 0) { FAPI_INF("Seeing no DIMM on %s, no freq to set", mss::c_str(i_target)); return fapi2::FAPI2_RC_SUCCESS; } // We will first set pre-eff_config attribes - for(const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(i_target)) + // Note that we have to go through the MEM_PORT to get to the DIMM targets because of the + // target hierarchy in Axone + for(const auto& p : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target)) { - std::vector<uint8_t> l_raw_spd; - FAPI_TRY(mss::spd::get_raw_data(d, l_raw_spd)); + for(const auto& d : mss::find_targets<fapi2::TARGET_TYPE_DIMM>(p)) { - // Gets the SPD facade - fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS); - mss::spd::facade l_spd_decoder(d, l_raw_spd, l_rc); + std::vector<uint8_t> l_raw_spd; + FAPI_TRY(mss::spd::get_raw_data(d, l_raw_spd)); + { + // Gets the SPD facade + fapi2::ReturnCode l_rc(fapi2::FAPI2_RC_SUCCESS); + mss::spd::facade l_spd_decoder(d, l_raw_spd, l_rc); + + // Checks that the facade was setup correctly + FAPI_TRY( l_rc, "Failed to initialize SPD facade for %s", mss::spd::c_str(d) ); - // Checks that the facade was setup correctly - FAPI_TRY( l_rc, "Failed to initialize SPD facade for %s", mss::spd::c_str(d) ); + // Set pre-eff_config SPD driven attributes + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::pre_data_init_fields>::set(l_spd_decoder)), + "Failed gen::attr_engine<mss::proc_type::AXONE, mss::pre_data_init_fields>::set on %s", mss::spd::c_str(d) ); - FAPI_TRY( mss::attr_eff_engine<mss::pre_data_init_fields>::set(l_spd_decoder) ); - FAPI_TRY( mss::attr_derived_engine<mss::generic_metadata_fields>::set(d) ); + // Set pre_eff_config attributes derived from other attributes + FAPI_TRY( (mss::gen::attr_engine<mss::proc_type::AXONE, mss::generic_metadata_fields>::set(d)), + "Failed gen::attr_engine<mss::proc_type::AXONE, mss::generic_metadata_fields>::set on %s", mss::spd::c_str(d) ); + } } } diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.H index e4e20b050..ef3b57188 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.H +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018,2019 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,7 +38,7 @@ #include <fapi2.H> -typedef fapi2::ReturnCode (*p9a_mss_freq_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>&); +typedef fapi2::ReturnCode (*p9a_mss_freq_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); extern "C" { @@ -48,7 +48,7 @@ extern "C" /// @param[in] i_target port target /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9a_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>& i_target ); + fapi2::ReturnCode p9a_mss_freq( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ); } diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.C index cc23976d8..9088840f4 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -35,13 +35,57 @@ // fapi2 #include <p9a_mss_freq_system.H> +#include <lib/freq/axone_sync.H> +#include <generic/memory/lib/utils/find.H> +#include <generic/memory/lib/utils/count_dimm.H> +extern "C" +{ /// /// @brief Matches OMI freq with DDR freq -/// @param[in] i_target controller (e.g. MC) +/// @param[in] i_target PROC_CHIP target /// @return FAPI2_RC_SUCCESS iff ok /// -fapi2::ReturnCode p9a_mss_freq_system( const fapi2::Target<fapi2::TARGET_TYPE_MC>& i_target ) -{ - return fapi2::FAPI2_RC_SUCCESS; -} + fapi2::ReturnCode p9a_mss_freq_system( const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target ) + { + const auto& l_ports = mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(i_target); + + // If there are no DIMM we don't need to bother. In fact, we can't as we didn't setup + // attributes for the PHY, etc. If there is even one DIMM on this proc, + // we do the right thing. + if (mss::count_dimm(l_ports) == 0) + { + FAPI_INF("... skipping freq_system - no DIMM ..."); + return fapi2::FAPI2_RC_SUCCESS; + } + + std::map< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>, uint64_t > l_freq_map; + uint32_t l_omi_freq = 0; + uint32_t l_selected_omi_freq = 0; + mss::speed_equality l_equal_dimm_speed; + + // Get OMI freq + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_OMI_MHZ, i_target, l_omi_freq) ); + + // Populate dimm speed map + FAPI_TRY( mss::dimm_speed_map(l_ports, l_freq_map, l_equal_dimm_speed), + "Failed to get dimm speed mapping" ); + + FAPI_INF("Dimm speed for all OCMBs are the same : %s", + uint8_t(l_equal_dimm_speed) ? "true" : "false"); + + // Select OMI freq, or check in the case of Cronus + FAPI_TRY( mss::select_omi_freq(l_freq_map, + l_equal_dimm_speed, + l_omi_freq, + l_selected_omi_freq) ); + + // Set attributes. + FAPI_INF("%s: Setting recommended OMI frequency in ATTR_FREQ_OMI_MHZ to %d", mss::c_str(i_target), l_selected_omi_freq); + FAPI_TRY( FAPI_ATTR_SET(fapi2::ATTR_FREQ_OMI_MHZ, i_target, l_selected_omi_freq) ); + + fapi_try_exit: + return fapi2::current_err; + } + +} //extern "C" diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H index cbf2d718c..31389feff 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -39,17 +39,17 @@ #include <fapi2.H> #include <vector> -typedef fapi2::ReturnCode (*p9a_mss_freq_system_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_MC>&); +typedef fapi2::ReturnCode (*p9a_mss_freq_system_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); extern "C" { /// /// @brief Matches OMI freq with DDR freq - /// @param[in] i_target controller (e.g. MC) + /// @param[in] i_target PROC_CHIP target /// @return FAPI2_RC_SUCCESS iff ok /// - fapi2::ReturnCode p9a_mss_freq_system(const fapi2::Target<fapi2::TARGET_TYPE_MC>& i_target); + fapi2::ReturnCode p9a_mss_freq_system(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); } #endif diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.mk index 2e399418e..baacd38d6 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_freq_system.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -27,5 +27,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_mss_freq_system -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.C index 0666a8772..7d8afb81f 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,10 +38,16 @@ // *HWP Consumed by: FSP:HB #include <p9a_mss_utils_to_throttle.H> +#include <lib/shared/exp_defaults.H> +#include <lib/shared/exp_consts.H> +#include <mss_explorer_attribute_getters.H> +#include <lib/power_thermal/exp_throttle.H> // fapi2 #include <fapi2.H> +extern "C" +{ /// /// @brief Determines throttle and power values for a given port databus utilization. /// @param[in] i_targets vector of OCMB_CHIPs to set throttle and power attributes on @@ -49,11 +55,106 @@ /// @note ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT will be set to worst case of all slots passed in /// @note input ATTR_MSS_DATABUS_UTIL and ATTR_MSS_MEM_WATT_TARGET /// @note output ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_SLOT, ATTR_MSS_MEM_THROTTLED_N_COMMANDS_PER_PORT, and ATTR_MSS_PORT_MAXPOWER -/// @note Does not set runtime throttles or set registers to throttle values` +/// @note Does not set runtime throttles or set registers to throttle values /// -fapi2::ReturnCode p9a_mss_utils_to_throttle( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP> >& - i_targets ) -{ - FAPI_INF("Entering p9a_mss_utils_to_throttle"); - return fapi2::FAPI2_RC_SUCCESS; -} + fapi2::ReturnCode p9a_mss_utils_to_throttle(const std::vector<fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>>& i_targets) + { + constexpr uint64_t l_min_util = mss::power_thermal::throttle_traits<mss::mc_type::EXPLORER>::MIN_UTIL; + + FAPI_INF("Entering p9a_mss_utils_to_throttle"); + + std::vector<fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT>> l_exceeded_power; + bool l_util_error = false; + + for (const auto& l_ocmb : i_targets) + { + if (mss::count_dimm(l_ocmb) == 0) + { + FAPI_INF("Skipping %s because it has no DIMM targets", mss::c_str(l_ocmb)); + continue; + } + + uint32_t l_max_databus_util = 0; + uint32_t l_dram_clocks = 0; + uint32_t l_safemode_util = 0; + uint32_t l_safemode_throttle_per_port = 0; + uint32_t l_calc_util = 0; + + FAPI_TRY(mss::attr::get_mrw_mem_m_dram_clocks(l_dram_clocks)); + FAPI_TRY(mss::attr::get_mrw_max_dram_databus_util(l_max_databus_util)); + FAPI_TRY(mss::attr::get_mrw_safemode_dram_databus_util(l_safemode_util)); + + l_safemode_throttle_per_port = mss::power_thermal::calc_n_from_dram_util( + (l_safemode_util / mss::power_thermal::throttle_const::PERCENT_CONVERSION), + l_dram_clocks); + + for(const auto& l_port : mss::find_targets<fapi2::TARGET_TYPE_MEM_PORT>(l_ocmb)) + { + fapi2::ReturnCode l_rc; + uint32_t l_input_databus_util = 0; + bool l_safemode = false; + + // Util attribute set by OCC + FAPI_TRY( mss::attr::get_databus_util(l_port, l_input_databus_util) ); + + FAPI_INF("Input databus utilization for %s is %d", + mss::c_str(l_port), + l_input_databus_util); + + // If input utilization is zero, use mrw safemode throttle values for utilization + // else make sure we're within our maximum utilization limit + FAPI_TRY(mss::power_thermal::calc_utilization<mss::mc_type::EXPLORER>(l_port, + l_input_databus_util, + l_dram_clocks, + l_safemode_throttle_per_port, + l_max_databus_util, + l_calc_util, + l_util_error, + l_safemode)); + + // Error if utilization is less than MIN_UTIL + // Don't exit, let HWP finish and return error at end + FAPI_ASSERT_NOEXIT( !l_util_error, + fapi2::MSS_MIN_UTILIZATION_ERROR() + .set_INPUT_UTIL_VALUE(l_input_databus_util) + .set_MIN_UTIL_VALUE(l_min_util), + "%s Input utilization (%d) less than minimum utilization allowed (%d)", + mss::c_str(l_port), l_input_databus_util, l_min_util); + + // Make a throttle object in order to calculate the port power + mss::power_thermal::throttle<mss::mc_type::EXPLORER> l_throttle(l_port, l_rc); + FAPI_TRY(l_rc, "%s Error calculating mss::power_thermal::throttle constructor in p9a_mss_utils_to_throttles", + mss::c_str(l_port)); + + FAPI_TRY(l_throttle.calc_slots_and_power(l_calc_util)); + + FAPI_INF( "%s Calculated N commands per port %d, per slot %d, commands per dram clock window %d, maxpower is %d", + mss::c_str(l_port), + l_throttle.iv_n_port, + l_throttle.iv_n_slot, + l_dram_clocks, + l_throttle.iv_calc_port_maxpower); + + FAPI_TRY(mss::attr::set_port_maxpower(l_port, l_throttle.iv_calc_port_maxpower)); + FAPI_TRY(mss::attr::set_mem_throttled_n_commands_per_slot(l_port, + (l_safemode) ? l_safemode_throttle_per_port : l_throttle.iv_n_slot)); + FAPI_TRY(mss::attr::set_mem_throttled_n_commands_per_port(l_port, + (l_safemode) ? l_safemode_throttle_per_port : l_throttle.iv_n_port)); + } // ports + } // ocmbs + + // Equalize throttles to prevent variable performance + // Note that we don't do anything with any port that exceed the power limit here, as we don't have an input power limit to go from + FAPI_TRY(mss::power_thermal::equalize_throttles<mss::mc_type::EXPLORER>(i_targets, mss::throttle_type::POWER, + l_exceeded_power)); + + // Return a failing RC code if we had any input utilization values less than MIN_UTIL + if (l_util_error) + { + fapi2::current_err = fapi2::RC_MSS_MIN_UTILIZATION_ERROR; + } + + fapi_try_exit: + return fapi2::current_err; + } +}// extern C diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.mk index a60770713..95a11aab6 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_utils_to_throttle.mk @@ -25,5 +25,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_mss_utils_to_throttle -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.C index a7b1d4b38..090f8f455 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,6 +44,7 @@ // mss lib #include <generic/memory/lib/utils/c_str.H> #include <generic/memory/lib/utils/voltage/gen_mss_volt.H> +#include <generic/memory/mss_git_data_helper.H> /// /// @brief Calculate and save off rail voltages @@ -52,6 +53,8 @@ /// fapi2::ReturnCode p9a_mss_volt( const std::vector< fapi2::Target<fapi2::TARGET_TYPE_MEM_PORT> >& i_targets ) { + mss::display_git_commit_info("p9a_mss_volt"); + for (const auto& l_port : i_targets) { FAPI_TRY( (mss::setup_voltage_rail_values<mss::mc_type::EXPLORER, mss::spd::device_type::DDR4>(l_port)), diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.mk index 045691c45..70f0fe675 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_mss_volt.mk @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2018 +# Contributors Listed Below - COPYRIGHT 2018,2019 # [+] International Business Machines Corp. # # @@ -27,5 +27,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_mss_volt -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.C deleted file mode 100644 index c7f904572..000000000 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.C +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.H deleted file mode 100644 index 5f2edfc82..000000000 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.H +++ /dev/null @@ -1,24 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_ocmb_thermal_init.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C new file mode 100644 index 000000000..eaccc18c9 --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C @@ -0,0 +1,98 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.C $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_setup.C +/// @brief Setup the OMI +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#include <fapi2.H> +#include <lib/shared/axone_defaults.H> +#include <p9a_omi_setup.H> +#include <lib/mc/omi.H> +#include <generic/memory/mss_git_data_helper.H> +#include <lib/workarounds/p9a_omi_workarounds.H> + +/// +/// @brief Setup OMI for axone +/// @param[in] i_target the axone OMI target to operate on +/// @return FAPI2_RC_SUCCESS iff ok +/// +fapi2::ReturnCode p9a_omi_setup( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target ) +{ + mss::display_git_commit_info("p9a_omi_setup"); + + FAPI_INF("%s Start p9a_omi_setup", mss::c_str(i_target)); + + const auto& l_mc = mss::find_target<fapi2::TARGET_TYPE_MC>(i_target); + const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + FAPI_TRY(mss::mc::setup_mc_mcn_config(l_mc)); + FAPI_TRY(mss::mc::setup_mc_config1(i_target)); + FAPI_TRY(mss::mc::setup_mc_cya_bits(i_target)); + FAPI_TRY(mss::mc::setup_mc_error_action(i_target)); + FAPI_TRY(mss::mc::setup_mc_rmt_config(i_target)); + + if(l_ocmbs.empty()) + { + // No ocmbs, no training needed + // Ensuring we don't try to access an empty vector + return fapi2::FAPI2_RC_SUCCESS; + } + + { + // Only one OCMB per OMI for axone + const auto& l_ocmb = l_ocmbs[0]; + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(i_target); + uint8_t l_dl_x4_backoff_en = 0; + bool l_axone_workarounds_required = false; + uint8_t l_proc_type = 0; + uint8_t l_ocmb_type = 0; + + // Get BACKOFF_ENABLE CHIP_EC attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, l_ocmb, l_dl_x4_backoff_en), + "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); + + // Determine if workaround will be performed, if so, perform it + FAPI_TRY(mss::workarounds::mc::get_ocmb_proc_types(l_ocmb, l_proc, l_ocmb_type, l_proc_type)); + l_axone_workarounds_required = mss::workarounds::mc::is_prbs_omi_axone_required(l_ocmb_type, l_proc_type); + + if (l_axone_workarounds_required) + { + // TX_TRAINING_STATE1 + FAPI_TRY(mss::workarounds::mc::pre_omi_training_prbs(i_target, l_dl_x4_backoff_en)); + } + + return fapi2::FAPI2_RC_SUCCESS; + } + +fapi_try_exit: + return fapi2::current_err; +} diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H new file mode 100644 index 000000000..cf364294b --- /dev/null +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H @@ -0,0 +1,53 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.H $ */ +/* */ +/* OpenPOWER HostBoot Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2019 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/// +/// @file p9a_omi_setup.H +/// @brief Setup the OMI +/// +// *HWP HWP Owner: Mark Pizzutillo <Mark.Pizzutillo@ibm.com> +// *HWP HWP Backup: Louis Stermole <stermole@us.ibm.com> +// *HWP Team: Memory +// *HWP Level: 2 +// *HWP Consumed by: FSP:HB + +#ifndef P9A_OMI_SETUP_H_ +#define P9A_OMI_SETUP_H_ + +#include <fapi2.H> + +typedef fapi2::ReturnCode (*p9a_omi_setup_FP_t) (const fapi2::Target<fapi2::TARGET_TYPE_OMI>&); + +extern "C" +{ + /// + /// @brief Setup OMI for axone + /// @param[in] i_target the axone OMI target to operate on + /// @return FAPI2_RC_SUCCESS iff ok + /// + fapi2::ReturnCode p9a_omi_setup( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target ); +} + +#endif diff --git a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/mss_gemini.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk index acafbc603..1edeebce8 100644 --- a/src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/mss_gemini.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk @@ -1,7 +1,7 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/import/chips/ocmb/gemini/procedures/hwp/memory/lib/mss_gemini.mk $ +# $Source: src/import/chips/p9a/procedures/hwp/memory/p9a_omi_setup.mk $ # # OpenPOWER HostBoot Project # @@ -22,3 +22,8 @@ # permissions and limitations under the License. # # IBM_PROLOG_END_TAG +-include 00p9a_common.mk + +PROCEDURE=p9a_omi_setup +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) +$(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C index 70202d95f..2075dfc5a 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2018 */ +/* Contributors Listed Below - COPYRIGHT 2018,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -47,6 +47,8 @@ #include <generic/memory/lib/utils/find.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <lib/mc/omi.H> +#include <lib/workarounds/p9a_omi_workarounds.H> +#include <generic/memory/mss_git_data_helper.H> /// @@ -56,19 +58,56 @@ /// fapi2::ReturnCode p9a_omi_train( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target) { + mss::display_git_commit_info("p9a_omi_train"); + FAPI_INF("%s Start p9a_omi_train", mss::c_str(i_target)); - const auto l_mc = mss::find_target<fapi2::TARGET_TYPE_MC>(i_target); + const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + if(l_ocmbs.empty()) + { + // No ocmbs, no training needed + return fapi2::FAPI2_RC_SUCCESS; + } + + { + // Only one OCMB per OMI for axone + const auto& l_ocmb = l_ocmbs[0]; + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(l_ocmb); + uint8_t l_dl_x4_backoff_en = 0; + bool l_gem_or_non_axone_workaround = false; + bool l_axone_workarounds_required = false; + uint8_t l_proc_type = 0; + uint8_t l_ocmb_type = 0; + + // Get BACKOFF_ENABLE CHIP_EC attribute + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE, l_ocmb, l_dl_x4_backoff_en), + "Error getting ATTR_CHIP_EC_FEATURE_OMI_DL_X4_BACKOFF_ENABLE"); + + // Determine if workarounds will be performed, if so, perform them + FAPI_TRY(mss::workarounds::mc::get_ocmb_proc_types(l_ocmb, l_proc, l_ocmb_type, l_proc_type)); + l_gem_or_non_axone_workaround = mss::workarounds::mc::is_prbs_omi_required(l_ocmb_type, l_proc_type); + l_axone_workarounds_required = mss::workarounds::mc::is_prbs_omi_axone_required(l_ocmb_type, l_proc_type); + + if (l_axone_workarounds_required) + { + // TX_PATTERN_A + FAPI_TRY(mss::workarounds::mc::omi_training_prbs(i_target, l_dl_x4_backoff_en)); + } + else if (l_gem_or_non_axone_workaround) + { + // TX_TRAINING_STATE_3, TX_PATTERN_A + FAPI_TRY(mss::workarounds::mc::omi_training_prbs_gem(i_target, l_dl_x4_backoff_en)); - FAPI_TRY(mss::mc::setup_mc_mcn_config_helper(l_mc)); - FAPI_TRY(mss::mc::setup_mc_config1_helper(i_target)); - FAPI_TRY(mss::mc::setup_mc_cya_bits_helper(i_target)); - FAPI_TRY(mss::mc::setup_mc_error_action_helper(i_target)); - FAPI_TRY(mss::mc::setup_mc_rmt_config_helper(i_target)); + // 2 second delay for gemini + FAPI_TRY(fapi2::delay(2 * mss::common_timings::DELAY_1S, mss::common_timings::DELAY_1MS)); + } - // *_CONFIG0 should be the last one written, since it starts the training. - FAPI_TRY(mss::mc::setup_mc_config0_helper(i_target)); + // Enable auto training + FAPI_TRY(mss::mc::setup_mc_config0(i_target, mss::omi::train_mode::ENABLE_AUTO_TRAINING, l_dl_x4_backoff_en)); + return fapi2::FAPI2_RC_SUCCESS; + } fapi_try_exit: return fapi2::current_err; diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk index f2deb6d74..83c2d899f 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train.mk @@ -27,5 +27,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_omi_train -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C index 50119a44d..f708f9ba1 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2019 */ +/* Contributors Listed Below - COPYRIGHT 2019,2020 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -44,6 +44,7 @@ #include <generic/memory/lib/utils/buffer_ops.H> #include <generic/memory/lib/utils/shared/mss_generic_consts.H> #include <lib/mc/omi.H> +#include <generic/memory/mss_git_data_helper.H> /// /// @brief Check the omi status in Axone side @@ -52,52 +53,102 @@ /// fapi2::ReturnCode p9a_omi_train_check( const fapi2::Target<fapi2::TARGET_TYPE_OMI>& i_target) { + mss::display_git_commit_info("p9a_omi_train_check"); + FAPI_INF("%s Start p9a_omi_train_check", mss::c_str(i_target)); // Const constexpr uint8_t STATE_MACHINE_SUCCESS = 0b111; // This value is from Lonny Lambrecht - constexpr uint8_t MAX_LOOP_COUNT = 20; // Retry times + constexpr uint8_t MAX_LOOP_COUNT = 10; // Retry times // Declares variables fapi2::buffer<uint64_t> l_omi_status; fapi2::buffer<uint64_t> l_omi_training_status; + fapi2::buffer<uint64_t> l_dl0_error_hold; + fapi2::buffer<uint64_t> l_expected_dl0_error_hold; + fapi2::buffer<uint64_t> l_dl0_config1; uint8_t l_state_machine_state = 0; uint8_t l_tries = 0; + uint32_t l_omi_freq = 0; + + const auto& l_ocmbs = mss::find_targets<fapi2::TARGET_TYPE_OCMB_CHIP>(i_target); + + // Sanity check for no empty vector + if (l_ocmbs.empty()) + { + // No training could have occurred + return fapi2::FAPI2_RC_SUCCESS; + } + + const auto& l_proc = mss::find_target<fapi2::TARGET_TYPE_PROC_CHIP>(l_ocmbs[0]); FAPI_TRY(mss::mc::omi_train_status(i_target, l_state_machine_state, l_omi_status)); - while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS) + do { // Delay - fapi2::delay(mss::DELAY_100US, 10 * mss::DELAY_1MS); + fapi2::delay(500 * mss::DELAY_1MS, 10 * mss::DELAY_1MS); // Check OMI training status FAPI_TRY(mss::mc::omi_train_status(i_target, l_state_machine_state, l_omi_status)); - // Note: this is very useful debug information while trying to debug training during polling - FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_TRAINING_STATUS, l_omi_training_status)); l_tries++; + } + while (l_tries < MAX_LOOP_COUNT && l_state_machine_state != STATE_MACHINE_SUCCESS); + // Note: this is very useful debug information while trying to debug training during polling FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_TRAINING_STATUS, l_omi_training_status)); + FAPI_TRY(fapi2::getScom(i_target, P9A_MC_REG2_DL0_CONFIG1, l_dl0_config1)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_FREQ_OMI_MHZ, l_proc, l_omi_freq)); + FAPI_ASSERT(l_state_machine_state == STATE_MACHINE_SUCCESS, fapi2::P9A_OMI_TRAIN_ERR() - .set_TARGET(i_target) + .set_OMI_TARGET(i_target) + .set_OCMB_TARGET(l_ocmbs[0]) .set_EXPECTED_SM_STATE(STATE_MACHINE_SUCCESS) .set_ACTUAL_SM_STATE(l_state_machine_state) .set_DL0_STATUS(l_omi_status) - .set_DL0_TRAINING_STATUS(l_omi_training_status), - "%s OMI Training Failure, expected state:%d/actual state:%d", + .set_DL0_TRAINING_STATUS(l_omi_training_status) + .set_DL0_CONFIG1(l_dl0_config1) + .set_OMI_FREQ(l_omi_freq), + "%s P9A OMI Training Failure, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", mss::c_str(i_target), STATE_MACHINE_SUCCESS, - l_state_machine_state + l_state_machine_state, + l_omi_status, + l_omi_training_status ); - FAPI_INF("%s End p9a_omi_train_check, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", + // Check errors in ERROR_HOLD until we get a proper FIR API setup + FAPI_TRY(mss::getScom(i_target, P9A_MC_REG2_DL0_ERROR_HOLD, l_dl0_error_hold)); + + // Training completion bit set + l_expected_dl0_error_hold.setBit<P9A_OMI_REG0_DL0_ERROR_HOLD_CERR_39>(); + + // Lost block bit set: this results in p9a only, from the + // necessary pre-training workarounds, and is expected to be set + // TK - We will need to the proper FIR unmasking later + l_expected_dl0_error_hold.setBit<P9A_OMI_REG0_DL0_ERROR_HOLD_CERR_33>(); + + if (l_dl0_error_hold != l_expected_dl0_error_hold) + { + // To get to this point, we had to have completed training, so these errors are not catastrophic + // We don't need to assert out, but let's make sure we print them out + FAPI_INF("%s P9A_MC_REG2_DL0_ERROR_HOLD REG 0x%016llx " + "did not match expected value. REG contents: 0x%016llx Expected: 0x%016llx", + mss::c_str(i_target), + P9A_MC_REG2_DL0_ERROR_HOLD, + l_dl0_error_hold, + l_expected_dl0_error_hold); + } + + FAPI_DBG("%s End p9a_omi_train_check, expected state:%d/actual state:%d, DL0_STATUS:0x%016llx, DL0_TRAINING_STATUS:0x%016llx", mss::c_str(i_target), STATE_MACHINE_SUCCESS, l_state_machine_state, l_omi_status, l_omi_training_status); + return fapi2::FAPI2_RC_SUCCESS; fapi_try_exit: diff --git a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk index 9f148de86..b976082cb 100644 --- a/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk +++ b/src/import/chips/p9a/procedures/hwp/memory/p9a_omi_train_check.mk @@ -27,5 +27,5 @@ -include 00p9a_common.mk PROCEDURE=p9a_omi_train_check -$(eval $(call ADD_MEMORY_INCDIRS,$(PROCEDURE))) +$(eval $(call ADD_P9A_MEMORY_INCDIRS,$(PROCEDURE))) $(call BUILD_PROCEDURE) diff --git a/src/import/chips/p9a/procedures/xml/error_info/p9a_freq_errors.xml b/src/import/chips/p9a/procedures/xml/error_info/p9a_freq_errors.xml index 37909deb2..c20e29b05 100644 --- a/src/import/chips/p9a/procedures/xml/error_info/p9a_freq_errors.xml +++ b/src/import/chips/p9a/procedures/xml/error_info/p9a_freq_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2020 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -80,7 +80,7 @@ </callout> <callout> <childTargets> - <parent>PORT_TARGET</parent> + <parent>TARGET</parent> <childType>TARGET_TYPE_DIMM</childType> </childTargets> <priority>MEDIUM</priority> diff --git a/src/import/chips/p9a/procedures/xml/error_info/p9a_omi_train_errors.xml b/src/import/chips/p9a/procedures/xml/error_info/p9a_omi_train_errors.xml index 555c491c5..48f8f2ea2 100644 --- a/src/import/chips/p9a/procedures/xml/error_info/p9a_omi_train_errors.xml +++ b/src/import/chips/p9a/procedures/xml/error_info/p9a_omi_train_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- OpenPOWER HostBoot Project --> <!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2018 --> +<!-- Contributors Listed Below - COPYRIGHT 2018,2019 --> <!-- [+] International Business Machines Corp. --> <!-- --> <!-- --> @@ -28,22 +28,28 @@ <hwpError> <rc>RC_P9A_OMI_TRAIN_ERR</rc> <description> - Procedure: p9a_omi_train failure + p9a_omi_train_check did not see expected trained status from OMI DL0 status register </description> - <ffdc>TARGET</ffdc> + <ffdc>OMI_TARGET</ffdc> <ffdc>EXPECTED_SM_STATE</ffdc> <ffdc>ACTUAL_SM_STATE</ffdc> <ffdc>DL0_STATUS</ffdc> <ffdc>DL0_TRAINING_STATUS</ffdc> + <ffdc>DL0_CONFIG1</ffdc> + <ffdc>OMI_FREQ</ffdc> <callout> - <target>TARGET</target> + <target>OMI_TARGET</target> + <priority>HIGH</priority> + </callout> + <callout> + <bus>OMI_TARGET, OCMB_TARGET</bus> <priority>HIGH</priority> </callout> <deconfigure> - <target>TARGET</target> + <target>OMI_TARGET</target> </deconfigure> <gard> - <target>TARGET</target> + <target>OMI_TARGET</target> </gard> </hwpError> <!-- ******************************************************************** --> |
