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| author | Chris Phan <cphan@us.ibm.com> | 2013-10-11 14:51:03 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-10-22 12:35:42 -0500 |
| commit | 5a4363e0c5e41cd8895c7650c2bfe4a417289b20 (patch) | |
| tree | 531fe280efca91948793224384d19b181dcfa252 /src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule | |
| parent | e64c67b9de11ab3a5978ee7b8261560197421f51 (diff) | |
| download | talos-hostboot-5a4363e0c5e41cd8895c7650c2bfe4a417289b20.tar.gz talos-hostboot-5a4363e0c5e41cd8895c7650c2bfe4a417289b20.zip | |
PRD: add conditional capture for PCICLOCKFIRs
CQ: SW230438
Change-Id: I44692ad902b1cb1aec7b83c0a3619e456d2d3742
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6655
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: BENJAMIN J. WEISENBECK <bweisenb@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6781
Diffstat (limited to 'src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule')
| -rwxr-xr-x | src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule index 2a0eeac65..5556c53c8 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule @@ -108,6 +108,7 @@ name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012000; capture group default; + capture req funccall("phbConfigured_0"); }; register PCICLOCKFIR_1 @@ -115,6 +116,7 @@ name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012400; capture group default; + capture req funccall("phbConfigured_1"); }; register PCICLOCKFIR_2 @@ -122,8 +124,31 @@ name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012800; capture group default; + capture req funccall("phbConfigured_2"); }; + register PCI_ETU_RESET_0 + { + name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + scomaddr 0x0901200A; + capture group never; + }; + + register PCI_ETU_RESET_1 + { + name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + scomaddr 0x0901240A; + capture group never; + }; + + register PCI_ETU_RESET_2 + { + name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + scomaddr 0x0901280A; + capture group never; + }; + + ############################################################################ # PCIE Chiplet PBFFIR ############################################################################ |
