PRD: add conditional capture for PCICLOCKFIRs

CQ: SW230438
Change-Id: I44692ad902b1cb1aec7b83c0a3619e456d2d3742
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/6655
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: BENJAMIN J. WEISENBECK <bweisenb@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6781

2 files changed, 101 insertions, 0 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule
index 2a0eeac65..5556c53c8 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule
@@ -108,6 +108,7 @@
         name        "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG";
         scomaddr    0x09012000;
         capture     group default;
+        capture     req funccall("phbConfigured_0");
     };
 
     register PCICLOCKFIR_1
@@ -115,6 +116,7 @@
         name        "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG";
         scomaddr    0x09012400;
         capture     group default;
+        capture     req funccall("phbConfigured_1");
     };
 
     register PCICLOCKFIR_2
@@ -122,8 +124,31 @@
         name        "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG";
         scomaddr    0x09012800;
         capture     group default;
+        capture     req funccall("phbConfigured_2");
     };
 
+    register PCI_ETU_RESET_0
+    {
+        name        "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG";
+        scomaddr    0x0901200A;
+        capture     group never;
+    };
+
+    register PCI_ETU_RESET_1
+    {
+        name        "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG";
+        scomaddr    0x0901240A;
+        capture     group never;
+    };
+
+    register PCI_ETU_RESET_2
+    {
+        name        "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG";
+        scomaddr    0x0901280A;
+        capture     group never;
+    };
+
+
     ############################################################################
     # PCIE Chiplet PBFFIR
     ############################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
index c6de9e5f9..32474a354 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C
@@ -631,6 +631,82 @@ PLUGIN_CALLOUT_PEER_BUS( psi,  TYPE_PSI,  0 )
 
 #undef PLUGIN_CALLOUT_PEER_BUS
 
+//------------------------------------------------------------------------------
+
+/**
+ * @brief Call to check for configured PHB (before capturing FFDC)
+ * @param  i_chip             P8 chip
+ * @param  i_phbPos           PHB position
+ * @param  o_isPhbConfigured  set to true if the PHB configured
+ * @returns Success
+ */
+int32_t phbConfigured(ExtensibleChip * i_chip,
+                      uint32_t i_phbPos,
+                      bool & o_isPhbConfigured)
+{
+    #define PRDF_FUNC "[Proc::phbConfigured] "
+
+    static const uint32_t MAX_PCI_NUM = 3;
+    static const char * pciEtuResetReg[MAX_PCI_NUM] =
+                                         { "PCI_ETU_RESET_0",
+                                           "PCI_ETU_RESET_1",
+                                           "PCI_ETU_RESET_2" };
+    int32_t o_rc = SUCCESS;
+    o_isPhbConfigured = false;
+
+    do
+    {
+        if( i_phbPos >= MAX_PCI_NUM )
+        {
+            PRDF_ERR( PRDF_FUNC"invalid PCI number: %d", i_phbPos );
+            break;
+        }
+
+        SCAN_COMM_REGISTER_CLASS * etuResetReg =
+            i_chip->getRegister( pciEtuResetReg[i_phbPos] );
+
+        if(NULL == etuResetReg)
+        {
+            PRDF_ERR( PRDF_FUNC"getRegister() Failed for register:%s",
+                         pciEtuResetReg[i_phbPos] );
+            break;
+        }
+
+        o_rc = etuResetReg->Read();
+        if ( SUCCESS != o_rc )
+        {
+            PRDF_ERR( PRDF_FUNC"%s Read() failed. Target=0x%08x",
+                      pciEtuResetReg[i_phbPos], i_chip->GetId() );
+            break;
+        }
+
+        // If bit 0 is cleared then the PHB is configured
+        if ( ! etuResetReg->IsBitSet(0) )
+        {
+            o_isPhbConfigured = true;
+        }
+
+    } while(0);
+
+    return SUCCESS;
+
+}
+
+#define PLUGIN_PHB_CONFIGURED( POS ) \
+int32_t phbConfigured_##POS( ExtensibleChip * i_chip, \
+                             bool & o_isPhbConfigured ) \
+{ return phbConfigured( i_chip, POS, o_isPhbConfigured ); } \
+PRDF_PLUGIN_DEFINE( Proc, phbConfigured_##POS );
+
+PLUGIN_PHB_CONFIGURED( 0 )
+PLUGIN_PHB_CONFIGURED( 1 )
+PLUGIN_PHB_CONFIGURED( 2 )
+
+#undef PLUGIN_PHB_CONFIGURED
+
+//------------------------------------------------------------------------------
+
+
 } // end namespace Proc
 
 } // end namespace PRDF