Add EFD processing to pmic_enable

Change-Id: Id63239a4231e14a1d5e12321cd5aada2ca9c1705
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77944
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Louis Stermole <stermole@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Jennifer A Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78268
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 184 insertions, 223 deletions

diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H
index addf8ca6b..e19dea87c 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_consts.H
@@ -103,66 +103,58 @@ enum attr_eff_engine_fields
     PMIC0_SWA_VOLTAGE_SETTING           = 1,
     PMIC0_SWA_VOLTAGE_RANGE_SELECT      = 2,
     PMIC0_SWA_VOLTAGE_OFFSET            = 3,
-    PMIC0_SWA_VOLTAGE_OFFSET_DIRECTION  = 4,
-    PMIC0_SWA_SEQUENCE_DELAY            = 5,
-    PMIC0_SWA_SEQUENCE_ORDER            = 6,
-
-    PMIC0_SWB_VOLTAGE_SETTING           = 7,
-    PMIC0_SWB_VOLTAGE_RANGE_SELECT      = 8,
-    PMIC0_SWB_VOLTAGE_OFFSET            = 9,
-    PMIC0_SWB_VOLTAGE_OFFSET_DIRECTION  = 10,
-    PMIC0_SWB_SEQUENCE_DELAY            = 11,
-    PMIC0_SWB_SEQUENCE_ORDER            = 12,
-
-    PMIC0_SWC_VOLTAGE_SETTING           = 13,
-    PMIC0_SWC_VOLTAGE_RANGE_SELECT      = 14,
-    PMIC0_SWC_VOLTAGE_OFFSET            = 15,
-    PMIC0_SWC_VOLTAGE_OFFSET_DIRECTION  = 16,
-    PMIC0_SWC_SEQUENCE_DELAY            = 17,
-    PMIC0_SWC_SEQUENCE_ORDER            = 18,
-
-    PMIC0_SWD_VOLTAGE_SETTING           = 19,
-    PMIC0_SWD_VOLTAGE_RANGE_SELECT      = 20,
-    PMIC0_SWD_VOLTAGE_OFFSET            = 21,
-    PMIC0_SWD_VOLTAGE_OFFSET_DIRECTION  = 22,
-    PMIC0_SWD_SEQUENCE_DELAY            = 23,
-    PMIC0_SWD_SEQUENCE_ORDER            = 24,
-
-    PMIC1_SWA_VOLTAGE_SETTING           = 25,
-    PMIC1_SWA_VOLTAGE_RANGE_SELECT      = 26,
-    PMIC1_SWA_VOLTAGE_OFFSET            = 27,
-    PMIC1_SWA_VOLTAGE_OFFSET_DIRECTION  = 28,
-    PMIC1_SWA_SEQUENCE_DELAY            = 29,
-    PMIC1_SWA_SEQUENCE_ORDER            = 30,
-
-    PMIC1_SWB_VOLTAGE_SETTING           = 31,
-    PMIC1_SWB_VOLTAGE_RANGE_SELECT      = 32,
-    PMIC1_SWB_VOLTAGE_OFFSET            = 33,
-    PMIC1_SWB_VOLTAGE_OFFSET_DIRECTION  = 34,
-    PMIC1_SWB_SEQUENCE_DELAY            = 35,
-    PMIC1_SWB_SEQUENCE_ORDER            = 36,
-
-    PMIC1_SWC_VOLTAGE_SETTING           = 37,
-    PMIC1_SWC_VOLTAGE_RANGE_SELECT      = 38,
-    PMIC1_SWC_VOLTAGE_OFFSET            = 39,
-    PMIC1_SWC_VOLTAGE_OFFSET_DIRECTION  = 40,
-    PMIC1_SWC_SEQUENCE_DELAY            = 41,
-    PMIC1_SWC_SEQUENCE_ORDER            = 42,
-
-    PMIC1_SWD_VOLTAGE_SETTING           = 43,
-    PMIC1_SWD_VOLTAGE_RANGE_SELECT      = 44,
-    PMIC1_SWD_VOLTAGE_OFFSET            = 45,
-    PMIC1_SWD_VOLTAGE_OFFSET_DIRECTION  = 46,
-    PMIC1_SWD_SEQUENCE_DELAY            = 47,
-    PMIC1_SWD_SEQUENCE_ORDER            = 48,
-
-    PMIC0_PHASE_COMB                    = 49,
-    PMIC1_PHASE_COMB                    = 50,
-
-    PMIC0_MFG_ID                        = 51,
-    PMIC1_MFG_ID                        = 52,
-
-    DRAM_MODULE_HEIGHT                  = 53,
+    PMIC0_SWA_SEQUENCE_DELAY            = 4,
+    PMIC0_SWA_SEQUENCE_ORDER            = 5,
+
+    PMIC0_SWB_VOLTAGE_SETTING           = 6,
+    PMIC0_SWB_VOLTAGE_RANGE_SELECT      = 7,
+    PMIC0_SWB_VOLTAGE_OFFSET            = 8,
+    PMIC0_SWB_SEQUENCE_DELAY            = 9,
+    PMIC0_SWB_SEQUENCE_ORDER            = 10,
+
+    PMIC0_SWC_VOLTAGE_SETTING           = 11,
+    PMIC0_SWC_VOLTAGE_RANGE_SELECT      = 12,
+    PMIC0_SWC_VOLTAGE_OFFSET            = 13,
+    PMIC0_SWC_SEQUENCE_DELAY            = 14,
+    PMIC0_SWC_SEQUENCE_ORDER            = 15,
+
+    PMIC0_SWD_VOLTAGE_SETTING           = 16,
+    PMIC0_SWD_VOLTAGE_RANGE_SELECT      = 17,
+    PMIC0_SWD_VOLTAGE_OFFSET            = 18,
+    PMIC0_SWD_SEQUENCE_DELAY            = 19,
+    PMIC0_SWD_SEQUENCE_ORDER            = 20,
+
+    PMIC1_SWA_VOLTAGE_SETTING           = 21,
+    PMIC1_SWA_VOLTAGE_RANGE_SELECT      = 22,
+    PMIC1_SWA_VOLTAGE_OFFSET            = 23,
+    PMIC1_SWA_SEQUENCE_DELAY            = 24,
+    PMIC1_SWA_SEQUENCE_ORDER            = 25,
+
+    PMIC1_SWB_VOLTAGE_SETTING           = 26,
+    PMIC1_SWB_VOLTAGE_RANGE_SELECT      = 27,
+    PMIC1_SWB_VOLTAGE_OFFSET            = 28,
+    PMIC1_SWB_SEQUENCE_DELAY            = 29,
+    PMIC1_SWB_SEQUENCE_ORDER            = 30,
+
+    PMIC1_SWC_VOLTAGE_SETTING           = 31,
+    PMIC1_SWC_VOLTAGE_RANGE_SELECT      = 32,
+    PMIC1_SWC_VOLTAGE_OFFSET            = 33,
+    PMIC1_SWC_SEQUENCE_DELAY            = 34,
+    PMIC1_SWC_SEQUENCE_ORDER            = 35,
+
+    PMIC1_SWD_VOLTAGE_SETTING           = 36,
+    PMIC1_SWD_VOLTAGE_RANGE_SELECT      = 37,
+    PMIC1_SWD_VOLTAGE_OFFSET            = 38,
+    PMIC1_SWD_SEQUENCE_DELAY            = 39,
+    PMIC1_SWD_SEQUENCE_ORDER            = 40,
+
+    PMIC0_PHASE_COMB                    = 41,
+    PMIC1_PHASE_COMB                    = 42,
+
+    PMIC0_MFG_ID                        = 43,
+    PMIC1_MFG_ID                        = 44,
+
+    DRAM_MODULE_HEIGHT                  = 45,
 
     // Dispatcher set to last enum value
     ATTR_EFF_DISPATCHER = DRAM_MODULE_HEIGHT,
@@ -176,66 +168,58 @@ enum ffdc_codes
     SET_PMIC0_SWA_VOLTAGE_SETTING           = 0x1052,
     SET_PMIC0_SWA_VOLTAGE_RANGE_SELECT      = 0x1053,
     SET_PMIC0_SWA_VOLTAGE_OFFSET            = 0x1054,
-    SET_PMIC0_SWA_VOLTAGE_OFFSET_DIRECTION  = 0x1055,
-    SET_PMIC0_SWA_SEQUENCE_DELAY            = 0x1056,
-    SET_PMIC0_SWA_SEQUENCE_ORDER            = 0X1057,
-
-    SET_PMIC0_SWB_VOLTAGE_SETTING           = 0x1058,
-    SET_PMIC0_SWB_VOLTAGE_RANGE_SELECT      = 0x1059,
-    SET_PMIC0_SWB_VOLTAGE_OFFSET            = 0x105A,
-    SET_PMIC0_SWB_VOLTAGE_OFFSET_DIRECTION  = 0x105B,
-    SET_PMIC0_SWB_SEQUENCE_DELAY            = 0x105C,
-    SET_PMIC0_SWB_SEQUENCE_ORDER            = 0X105D,
-
-    SET_PMIC0_SWC_VOLTAGE_SETTING           = 0x105E,
-    SET_PMIC0_SWC_VOLTAGE_RANGE_SELECT      = 0x105F,
-    SET_PMIC0_SWC_VOLTAGE_OFFSET            = 0x1060,
-    SET_PMIC0_SWC_VOLTAGE_OFFSET_DIRECTION  = 0x1061,
-    SET_PMIC0_SWC_SEQUENCE_DELAY            = 0x1062,
-    SET_PMIC0_SWC_SEQUENCE_ORDER            = 0X1063,
-
-    SET_PMIC0_SWD_VOLTAGE_SETTING           = 0x1064,
-    SET_PMIC0_SWD_VOLTAGE_RANGE_SELECT      = 0x1065,
-    SET_PMIC0_SWD_VOLTAGE_OFFSET            = 0x1066,
-    SET_PMIC0_SWD_VOLTAGE_OFFSET_DIRECTION  = 0x1067,
-    SET_PMIC0_SWD_SEQUENCE_DELAY            = 0x1068,
-    SET_PMIC0_SWD_SEQUENCE_ORDER            = 0X1069,
-
-    SET_PMIC1_SWA_VOLTAGE_SETTING           = 0x106A,
-    SET_PMIC1_SWA_VOLTAGE_RANGE_SELECT      = 0x106B,
-    SET_PMIC1_SWA_VOLTAGE_OFFSET            = 0x106C,
-    SET_PMIC1_SWA_VOLTAGE_OFFSET_DIRECTION  = 0x106D,
-    SET_PMIC1_SWA_SEQUENCE_DELAY            = 0x106E,
-    SET_PMIC1_SWA_SEQUENCE_ORDER            = 0X106F,
-
-    SET_PMIC1_SWB_VOLTAGE_SETTING           = 0x1070,
-    SET_PMIC1_SWB_VOLTAGE_RANGE_SELECT      = 0x1071,
-    SET_PMIC1_SWB_VOLTAGE_OFFSET            = 0x1072,
-    SET_PMIC1_SWB_VOLTAGE_OFFSET_DIRECTION  = 0x1073,
-    SET_PMIC1_SWB_SEQUENCE_DELAY            = 0x1074,
-    SET_PMIC1_SWB_SEQUENCE_ORDER            = 0X1075,
-
-    SET_PMIC1_SWC_VOLTAGE_SETTING           = 0x1076,
-    SET_PMIC1_SWC_VOLTAGE_RANGE_SELECT      = 0x1077,
-    SET_PMIC1_SWC_VOLTAGE_OFFSET            = 0x1078,
-    SET_PMIC1_SWC_VOLTAGE_OFFSET_DIRECTION  = 0x1079,
-    SET_PMIC1_SWC_SEQUENCE_DELAY            = 0x107A,
-    SET_PMIC1_SWC_SEQUENCE_ORDER            = 0X107B,
-
-    SET_PMIC1_SWD_VOLTAGE_SETTING           = 0x107C,
-    SET_PMIC1_SWD_VOLTAGE_RANGE_SELECT      = 0x107D,
-    SET_PMIC1_SWD_VOLTAGE_OFFSET            = 0x107E,
-    SET_PMIC1_SWD_VOLTAGE_OFFSET_DIRECTION  = 0x107F,
-    SET_PMIC1_SWD_SEQUENCE_DELAY            = 0x1080,
-    SET_PMIC1_SWD_SEQUENCE_ORDER            = 0X1081,
-
-    SET_PMIC0_PHASE_COMB                    = 0x1082,
-    SET_PMIC1_PHASE_COMB                    = 0x1083,
-
-    SET_PMIC0_MFG_ID                        = 0x1084,
-    SET_PMIC1_MFG_ID                        = 0x1085,
-
-    SET_DRAM_MODULE_HEIGHT                  = 0x1086,
+    SET_PMIC0_SWA_SEQUENCE_DELAY            = 0x1055,
+    SET_PMIC0_SWA_SEQUENCE_ORDER            = 0X1056,
+
+    SET_PMIC0_SWB_VOLTAGE_SETTING           = 0x1057,
+    SET_PMIC0_SWB_VOLTAGE_RANGE_SELECT      = 0x1058,
+    SET_PMIC0_SWB_VOLTAGE_OFFSET            = 0x1059,
+    SET_PMIC0_SWB_SEQUENCE_DELAY            = 0x105A,
+    SET_PMIC0_SWB_SEQUENCE_ORDER            = 0X105B,
+
+    SET_PMIC0_SWC_VOLTAGE_SETTING           = 0x105C,
+    SET_PMIC0_SWC_VOLTAGE_RANGE_SELECT      = 0x105D,
+    SET_PMIC0_SWC_VOLTAGE_OFFSET            = 0x105E,
+    SET_PMIC0_SWC_SEQUENCE_DELAY            = 0x105F,
+    SET_PMIC0_SWC_SEQUENCE_ORDER            = 0X1060,
+
+    SET_PMIC0_SWD_VOLTAGE_SETTING           = 0x1061,
+    SET_PMIC0_SWD_VOLTAGE_RANGE_SELECT      = 0x1062,
+    SET_PMIC0_SWD_VOLTAGE_OFFSET            = 0x1063,
+    SET_PMIC0_SWD_SEQUENCE_DELAY            = 0x1064,
+    SET_PMIC0_SWD_SEQUENCE_ORDER            = 0X1065,
+
+    SET_PMIC1_SWA_VOLTAGE_SETTING           = 0x1066,
+    SET_PMIC1_SWA_VOLTAGE_RANGE_SELECT      = 0x1067,
+    SET_PMIC1_SWA_VOLTAGE_OFFSET            = 0x1068,
+    SET_PMIC1_SWA_SEQUENCE_DELAY            = 0x1069,
+    SET_PMIC1_SWA_SEQUENCE_ORDER            = 0X106A,
+
+    SET_PMIC1_SWB_VOLTAGE_SETTING           = 0x106B,
+    SET_PMIC1_SWB_VOLTAGE_RANGE_SELECT      = 0x106C,
+    SET_PMIC1_SWB_VOLTAGE_OFFSET            = 0x106D,
+    SET_PMIC1_SWB_SEQUENCE_DELAY            = 0x106E,
+    SET_PMIC1_SWB_SEQUENCE_ORDER            = 0X106F,
+
+    SET_PMIC1_SWC_VOLTAGE_SETTING           = 0x1070,
+    SET_PMIC1_SWC_VOLTAGE_RANGE_SELECT      = 0x1071,
+    SET_PMIC1_SWC_VOLTAGE_OFFSET            = 0x1072,
+    SET_PMIC1_SWC_SEQUENCE_DELAY            = 0x1073,
+    SET_PMIC1_SWC_SEQUENCE_ORDER            = 0X1074,
+
+    SET_PMIC1_SWD_VOLTAGE_SETTING           = 0x1075,
+    SET_PMIC1_SWD_VOLTAGE_RANGE_SELECT      = 0x1076,
+    SET_PMIC1_SWD_VOLTAGE_OFFSET            = 0x1077,
+    SET_PMIC1_SWD_SEQUENCE_DELAY            = 0x1078,
+    SET_PMIC1_SWD_SEQUENCE_ORDER            = 0X1079,
+
+    SET_PMIC0_PHASE_COMB                    = 0x107A,
+    SET_PMIC1_PHASE_COMB                    = 0x107B,
+
+    SET_PMIC0_MFG_ID                        = 0x107C,
+    SET_PMIC1_MFG_ID                        = 0x107D,
+
+    SET_DRAM_MODULE_HEIGHT                  = 0x107E,
 };
 
 ///
diff --git a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
index ba93774bb..835eb907c 100644
--- a/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
+++ b/src/import/chips/ocmb/common/procedures/hwp/pmic/lib/utils/pmic_enable_utils.H
@@ -63,7 +63,8 @@ enum enable_mode
 
 /// @brief pointer to PMIC attribute getters for DIMM target
 typedef fapi2::ReturnCode (*pmic_attr_ptr)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target, uint8_t& o_value);
-
+typedef fapi2::ReturnCode (*pmic_attr_ptr_signed)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        int8_t& o_value);
 // Pointers below allow for run-time attribute getter selection by PMIC ID (0,1)
 
 // Voltage Setting
@@ -111,49 +112,27 @@ static constexpr pmic_attr_ptr get_swd_voltage_range_select[] =
 };
 
 // Voltage Offset
-static constexpr pmic_attr_ptr get_swa_voltage_offset[] =
+static constexpr pmic_attr_ptr_signed get_swa_voltage_offset[] =
 {
     mss::attr::get_pmic0_swa_voltage_offset,
     mss::attr::get_pmic1_swa_voltage_offset
 };
-static constexpr pmic_attr_ptr get_swb_voltage_offset[] =
+static constexpr pmic_attr_ptr_signed get_swb_voltage_offset[] =
 {
     mss::attr::get_pmic0_swb_voltage_offset,
     mss::attr::get_pmic1_swb_voltage_offset
 };
-static constexpr pmic_attr_ptr get_swc_voltage_offset[] =
+static constexpr pmic_attr_ptr_signed get_swc_voltage_offset[] =
 {
     mss::attr::get_pmic0_swc_voltage_offset,
     mss::attr::get_pmic1_swc_voltage_offset
 };
-static constexpr pmic_attr_ptr get_swd_voltage_offset[] =
+static constexpr pmic_attr_ptr_signed get_swd_voltage_offset[] =
 {
     mss::attr::get_pmic0_swd_voltage_offset,
     mss::attr::get_pmic1_swd_voltage_offset
 };
 
-// Voltage Offset Direction
-static constexpr pmic_attr_ptr get_swa_voltage_offset_direction[] =
-{
-    mss::attr::get_pmic0_swa_voltage_offset_direction,
-    mss::attr::get_pmic1_swa_voltage_offset_direction
-};
-static constexpr pmic_attr_ptr get_swb_voltage_offset_direction[] =
-{
-    mss::attr::get_pmic0_swb_voltage_offset_direction,
-    mss::attr::get_pmic1_swb_voltage_offset_direction
-};
-static constexpr pmic_attr_ptr get_swc_voltage_offset_direction[] =
-{
-    mss::attr::get_pmic0_swc_voltage_offset_direction,
-    mss::attr::get_pmic1_swc_voltage_offset_direction
-};
-static constexpr pmic_attr_ptr get_swd_voltage_offset_direction[] =
-{
-    mss::attr::get_pmic0_swd_voltage_offset_direction,
-    mss::attr::get_pmic1_swd_voltage_offset_direction
-};
-
 // Sequence Delay
 static constexpr pmic_attr_ptr get_swa_sequence_delay[] =
 {
@@ -205,8 +184,35 @@ static constexpr pmic_attr_ptr get_phase_comb[] =
     mss::attr::get_pmic1_phase_comb
 };
 
+// EFD Fields
+
+// Offset
+static constexpr pmic_attr_ptr_signed get_efd_swa_voltage_offset[] =
+{
+    mss::attr::get_efd_pmic0_swa_voltage_offset,
+    mss::attr::get_efd_pmic1_swa_voltage_offset
+};
+
+static constexpr pmic_attr_ptr_signed get_efd_swb_voltage_offset[] =
+{
+    mss::attr::get_efd_pmic0_swb_voltage_offset,
+    mss::attr::get_efd_pmic1_swb_voltage_offset
+};
+
+static constexpr pmic_attr_ptr_signed get_efd_swc_voltage_offset[] =
+{
+    mss::attr::get_efd_pmic0_swc_voltage_offset,
+    mss::attr::get_efd_pmic1_swc_voltage_offset
+};
+
+static constexpr pmic_attr_ptr_signed get_efd_swd_voltage_offset[] =
+{
+    mss::attr::get_efd_pmic0_swd_voltage_offset,
+    mss::attr::get_efd_pmic1_swd_voltage_offset
+};
+
 // These arrays allow us to dynamically choose the right attribute getter at runtime based on the rail and mss::pmic::id
-static const pmic_attr_ptr* l_get_volt_setting[] =
+static const pmic_attr_ptr* get_volt_setting[] =
 {
     mss::pmic::get_swa_voltage_setting,
     mss::pmic::get_swb_voltage_setting,
@@ -214,7 +220,7 @@ static const pmic_attr_ptr* l_get_volt_setting[] =
     mss::pmic::get_swd_voltage_setting
 };
 
-static const pmic_attr_ptr* l_get_volt_range_select[] =
+static const pmic_attr_ptr* get_volt_range_select[] =
 {
     mss::pmic::get_swa_voltage_range_select,
     mss::pmic::get_swb_voltage_range_select,
@@ -222,7 +228,7 @@ static const pmic_attr_ptr* l_get_volt_range_select[] =
     mss::pmic::get_swd_voltage_range_select
 };
 
-static const pmic_attr_ptr* l_get_volt_offset[] =
+static const pmic_attr_ptr_signed* get_volt_offset[] =
 {
     mss::pmic::get_swa_voltage_offset,
     mss::pmic::get_swb_voltage_offset,
@@ -230,12 +236,13 @@ static const pmic_attr_ptr* l_get_volt_offset[] =
     mss::pmic::get_swd_voltage_offset
 };
 
-static const pmic_attr_ptr* l_get_volt_offset_direction[] =
+// EFD Offset + Direction functions
+static const pmic_attr_ptr_signed* get_efd_volt_offset[] =
 {
-    mss::pmic::get_swa_voltage_offset_direction,
-    mss::pmic::get_swb_voltage_offset_direction,
-    mss::pmic::get_swc_voltage_offset_direction,
-    mss::pmic::get_swd_voltage_offset_direction
+    mss::pmic::get_efd_swa_voltage_offset,
+    mss::pmic::get_efd_swb_voltage_offset,
+    mss::pmic::get_efd_swc_voltage_offset,
+    mss::pmic::get_efd_swd_voltage_offset
 };
 
 // For output traces
@@ -244,6 +251,8 @@ static const std::vector<const char*> PMIC_RAIL_NAMES = {"SWA", "SWB", "SWC", "S
 // Attribute setter FP type
 typedef fapi2::ReturnCode (*pmic_attr_setter_ptr)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
         uint8_t i_value);
+typedef fapi2::ReturnCode (*pmic_attr_setter_ptr_signed)(const fapi2::Target<fapi2::TARGET_TYPE_DIMM>& i_target,
+        int8_t i_value);
 
 // Voltage Setting
 static constexpr pmic_attr_setter_ptr set_swa_voltage_setting[] =
@@ -290,49 +299,27 @@ static constexpr pmic_attr_setter_ptr set_swd_voltage_range_select[] =
 };
 
 // Voltage Offset
-static constexpr pmic_attr_setter_ptr set_swa_voltage_offset[] =
+static constexpr pmic_attr_setter_ptr_signed set_swa_voltage_offset[] =
 {
     mss::attr::set_pmic0_swa_voltage_offset,
     mss::attr::set_pmic1_swa_voltage_offset
 };
-static constexpr pmic_attr_setter_ptr set_swb_voltage_offset[] =
+static constexpr pmic_attr_setter_ptr_signed set_swb_voltage_offset[] =
 {
     mss::attr::set_pmic0_swb_voltage_offset,
     mss::attr::set_pmic1_swb_voltage_offset
 };
-static constexpr pmic_attr_setter_ptr set_swc_voltage_offset[] =
+static constexpr pmic_attr_setter_ptr_signed set_swc_voltage_offset[] =
 {
     mss::attr::set_pmic0_swc_voltage_offset,
     mss::attr::set_pmic1_swc_voltage_offset
 };
-static constexpr pmic_attr_setter_ptr set_swd_voltage_offset[] =
+static constexpr pmic_attr_setter_ptr_signed set_swd_voltage_offset[] =
 {
     mss::attr::set_pmic0_swd_voltage_offset,
     mss::attr::set_pmic1_swd_voltage_offset
 };
 
-// Voltage Offset Direction
-static constexpr pmic_attr_setter_ptr set_swa_voltage_offset_direction[] =
-{
-    mss::attr::set_pmic0_swa_voltage_offset_direction,
-    mss::attr::set_pmic1_swa_voltage_offset_direction
-};
-static constexpr pmic_attr_setter_ptr set_swb_voltage_offset_direction[] =
-{
-    mss::attr::set_pmic0_swb_voltage_offset_direction,
-    mss::attr::set_pmic1_swb_voltage_offset_direction
-};
-static constexpr pmic_attr_setter_ptr set_swc_voltage_offset_direction[] =
-{
-    mss::attr::set_pmic0_swc_voltage_offset_direction,
-    mss::attr::set_pmic1_swc_voltage_offset_direction
-};
-static constexpr pmic_attr_setter_ptr set_swd_voltage_offset_direction[] =
-{
-    mss::attr::set_pmic0_swd_voltage_offset_direction,
-    mss::attr::set_pmic1_swd_voltage_offset_direction
-};
-
 // Sequence Delay
 static constexpr pmic_attr_setter_ptr set_swa_sequence_delay[] =
 {
@@ -384,40 +371,30 @@ static constexpr pmic_attr_setter_ptr set_phase_comb[] =
     mss::attr::set_pmic1_phase_comb
 };
 
-// TK - these will be needed in the next commit (pmic_bias).
-
-// These arrays allow us to dynamically choose the right attribute setter at runtime based on the rail and mss::pmic::id
-// static const pmic_attr_setter_ptr* l_set_volt_setting[] =
-// {
-//     mss::pmic::set_swa_voltage_setting,
-//     mss::pmic::set_swb_voltage_setting,
-//     mss::pmic::set_swc_voltage_setting,
-//     mss::pmic::set_swd_voltage_setting
-// };
-
-// static const pmic_attr_setter_ptr* l_set_volt_range_select[] =
-// {
-//     mss::pmic::set_swa_voltage_range_select,
-//     mss::pmic::set_swb_voltage_range_select,
-//     mss::pmic::set_swc_voltage_range_select,
-//     mss::pmic::set_swd_voltage_range_select
-// };
-
-// static const pmic_attr_setter_ptr* l_set_volt_offset[] =
-// {
-//     mss::pmic::set_swa_voltage_offset,
-//     mss::pmic::set_swb_voltage_offset,
-//     mss::pmic::set_swc_voltage_offset,
-//     mss::pmic::set_swd_voltage_offset
-// };
-
-// static const pmic_attr_setter_ptr* l_set_volt_offset_direction[] =
-// {
-//     mss::pmic::set_swa_voltage_offset_direction,
-//     mss::pmic::set_swb_voltage_offset_direction,
-//     mss::pmic::set_swc_voltage_offset_direction,
-//     mss::pmic::set_swd_voltage_offset_direction
-// };
+// Offset
+static constexpr pmic_attr_setter_ptr_signed set_efd_swa_voltage_offset[] =
+{
+    mss::attr::set_efd_pmic0_swa_voltage_offset,
+    mss::attr::set_efd_pmic1_swa_voltage_offset
+};
+
+static constexpr pmic_attr_setter_ptr_signed set_efd_swb_voltage_offset[] =
+{
+    mss::attr::set_efd_pmic0_swb_voltage_offset,
+    mss::attr::set_efd_pmic1_swb_voltage_offset
+};
+
+static constexpr pmic_attr_setter_ptr_signed set_efd_swc_voltage_offset[] =
+{
+    mss::attr::set_efd_pmic0_swc_voltage_offset,
+    mss::attr::set_efd_pmic1_swc_voltage_offset
+};
+
+static constexpr pmic_attr_setter_ptr_signed set_efd_swd_voltage_offset[] =
+{
+    mss::attr::set_efd_pmic0_swd_voltage_offset,
+    mss::attr::set_efd_pmic1_swd_voltage_offset
+};
 
 //-----------------------------------
 // SPD Biasing functions
@@ -521,16 +498,16 @@ inline fapi2::ReturnCode calculate_voltage_write_buffer(
     fapi2::buffer<uint8_t>& o_volt_buffer)
 {
     uint8_t l_volt = 0;
-    uint8_t l_volt_offset = 0;
-    uint8_t l_volt_offset_direction = 0;
+    int8_t l_volt_offset = 0;
+    int8_t l_efd_volt_offset = 0;
 
     // Get the attributes corresponding to the rail and PMIC indices
-    FAPI_TRY(l_get_volt_setting[i_rail][i_id](i_dimm_target, l_volt));
-    FAPI_TRY(l_get_volt_offset[i_rail][i_id](i_dimm_target, l_volt_offset));
-    FAPI_TRY(l_get_volt_offset_direction[i_rail][i_id](i_dimm_target, l_volt_offset_direction));
+    FAPI_TRY(get_volt_setting[i_rail][i_id](i_dimm_target, l_volt));
+    FAPI_TRY(get_volt_offset[i_rail][i_id](i_dimm_target, l_volt_offset));
+    FAPI_TRY(get_efd_volt_offset[i_rail][i_id](i_dimm_target, l_efd_volt_offset));
 
-    o_volt_buffer = (l_volt_offset_direction == CONSTS::OFFSET_PLUS) ?
-                    l_volt + l_volt_offset : l_volt - l_volt_offset;
+    // Set output buffer
+    o_volt_buffer = l_volt + l_volt_offset + l_efd_volt_offset;
 
 fapi_try_exit:
     return fapi2::current_err;
@@ -603,7 +580,7 @@ inline fapi2::ReturnCode bias_with_spd_voltages<mss::pmic::vendor::TI>(
         bool l_overflow = false;
 
         uint8_t l_volt_range_select = 0;
-        FAPI_TRY(l_get_volt_range_select[l_rail_index][i_id](i_dimm_target, l_volt_range_select));
+        FAPI_TRY(get_volt_range_select[l_rail_index][i_id](i_dimm_target, l_volt_range_select));
 
         // SWD supports a RANGE 1, but NOT SWA-C
         if (l_rail_index == mss::pmic::rail::SWD)