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| author | Christian Geddes <crgeddes@us.ibm.com> | 2019-04-25 13:04:51 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-14 14:54:03 -0500 |
| commit | b95951684667a2d77a76e589505e4250a0f02751 (patch) | |
| tree | 45117e7be05d6b04787717bcb95b818d0f3d8a75 /src/build/configs/simics_axone.config | |
| parent | 7ddeb4b85db8f85f1ddffcda0943efeba58e20f9 (diff) | |
| download | talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.tar.gz talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.zip | |
Force Axone simics to read all VPD from HW with config flags
This commit will set the config flags to always read from HW
rather than the old VPD cache in PNOR. Until this point in Axone
we were still using an old copy of MVPD that we write into PNOR
during the startup simics scripts. From this commit onward we will
use the actual VPD simics provides. To handle this, some updates
we needed to the PG rules for Axone.
Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/build/configs/simics_axone.config')
| -rw-r--r-- | src/build/configs/simics_axone.config | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/src/build/configs/simics_axone.config b/src/build/configs/simics_axone.config index 0b54948c0..fca0217d7 100644 --- a/src/build/configs/simics_axone.config +++ b/src/build/configs/simics_axone.config @@ -1,21 +1,21 @@ -# Force DJVPD read/write to use EEPROM layer instead of VPD cache +# Force DJVPD read/write to use EEPROM layer instead of old-style VPD cache set DJVPD_READ_FROM_HW set DJVPD_WRITE_TO_HW unset DJVPD_READ_FROM_PNOR unset DJVPD_WRITE_TO_PNOR -# Force MEMVPD read/write to PNOR ( No actual hardware ) -set MEMVPD_READ_FROM_PNOR -set MEMVPD_WRITE_TO_PNOR -unset MEMVPD_READ_FROM_HW -unset MEMVPD_WRITE_TO_HW +# Force MEMVPD read/write to use EEPROM layer instead of old-style VPD cache +# ( No concept of MEMVPD in Axone so should not matter ) +set MEMVPD_READ_FROM_HW +set MEMVPD_WRITE_TO_HW +unset MEMVPD_READ_FROM_PNOR +unset MEMVPD_WRITE_TO_PNOR -# Force MVPD read/write to use EEPROM layer instead of VPD cache -# (not working because shoddy MVPD currently) -#set MVPD_READ_FROM_HW -#set MVPD_WRITE_TO_HW -set MVPD_READ_FROM_PNOR -set MVPD_WRITE_TO_PNOR +# Force MVPD read/write to use EEPROM layer instead of old-style VPD cache +set MVPD_READ_FROM_HW +set MVPD_WRITE_TO_HW +unset MVPD_READ_FROM_PNOR +unset MVPD_WRITE_TO_PNOR #set to run cxx testcases during boot unset EARLY_TESTCASES @@ -26,9 +26,7 @@ set IPLTIME_CHECKSTOP_ANALYSIS #enable EEPROM caching set SUPPORT_EEPROM_CACHING -#Try to keep a list of things this does -# - skipping setting voltages in istep 8.12, nothing on other side of AVSbus -# in simics currently. +# Allows us to put in workarounds specifically for Axone bringup set AXONE_BRING_UP # Set this to pull in Axone on code (such as P9A/EXP MSS code) |
