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-rw-r--r--src/build/configs/simics_axone.config28
-rw-r--r--src/include/usr/hwas/common/pgLogic.H21
-rw-r--r--src/include/usr/hwas/common/vpdConstants.H123
-rw-r--r--src/usr/fapi2/test/fapi2MvpdTestCxx.H6
-rw-r--r--src/usr/hwas/common/hwas.C15
-rw-r--r--src/usr/hwas/common/pgLogic.C3
-rw-r--r--src/usr/hwas/test/hwas1test.H259
-rw-r--r--src/usr/vpd/ipvpd.C18
-rw-r--r--src/usr/vpd/pvpd.C3
9 files changed, 357 insertions, 119 deletions
diff --git a/src/build/configs/simics_axone.config b/src/build/configs/simics_axone.config
index 0b54948c0..fca0217d7 100644
--- a/src/build/configs/simics_axone.config
+++ b/src/build/configs/simics_axone.config
@@ -1,21 +1,21 @@
-# Force DJVPD read/write to use EEPROM layer instead of VPD cache
+# Force DJVPD read/write to use EEPROM layer instead of old-style VPD cache
set DJVPD_READ_FROM_HW
set DJVPD_WRITE_TO_HW
unset DJVPD_READ_FROM_PNOR
unset DJVPD_WRITE_TO_PNOR
-# Force MEMVPD read/write to PNOR ( No actual hardware )
-set MEMVPD_READ_FROM_PNOR
-set MEMVPD_WRITE_TO_PNOR
-unset MEMVPD_READ_FROM_HW
-unset MEMVPD_WRITE_TO_HW
+# Force MEMVPD read/write to use EEPROM layer instead of old-style VPD cache
+# ( No concept of MEMVPD in Axone so should not matter )
+set MEMVPD_READ_FROM_HW
+set MEMVPD_WRITE_TO_HW
+unset MEMVPD_READ_FROM_PNOR
+unset MEMVPD_WRITE_TO_PNOR
-# Force MVPD read/write to use EEPROM layer instead of VPD cache
-# (not working because shoddy MVPD currently)
-#set MVPD_READ_FROM_HW
-#set MVPD_WRITE_TO_HW
-set MVPD_READ_FROM_PNOR
-set MVPD_WRITE_TO_PNOR
+# Force MVPD read/write to use EEPROM layer instead of old-style VPD cache
+set MVPD_READ_FROM_HW
+set MVPD_WRITE_TO_HW
+unset MVPD_READ_FROM_PNOR
+unset MVPD_WRITE_TO_PNOR
#set to run cxx testcases during boot
unset EARLY_TESTCASES
@@ -26,9 +26,7 @@ set IPLTIME_CHECKSTOP_ANALYSIS
#enable EEPROM caching
set SUPPORT_EEPROM_CACHING
-#Try to keep a list of things this does
-# - skipping setting voltages in istep 8.12, nothing on other side of AVSbus
-# in simics currently.
+# Allows us to put in workarounds specifically for Axone bringup
set AXONE_BRING_UP
# Set this to pull in Axone on code (such as P9A/EXP MSS code)
diff --git a/src/include/usr/hwas/common/pgLogic.H b/src/include/usr/hwas/common/pgLogic.H
index 66e59f5f0..00b811358 100644
--- a/src/include/usr/hwas/common/pgLogic.H
+++ b/src/include/usr/hwas/common/pgLogic.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -129,6 +129,7 @@ namespace PARTIAL_GOOD
// MC
// PG/AG Masks
extern const uint16_t MC_R1_AG_MASK;
+ extern const uint16_t MC_R1_AG_MASK_AXONE;
extern const uint16_t MC_R2_PG_MASK;
extern const uint16_t MC_R3_PG_MASK;
@@ -533,17 +534,27 @@ namespace PARTIAL_GOOD
},
{ TARGETING::TYPE_MC,
{
- // MC Rule 1
+ // MC Rule 1 (Cumulus)
new PartialGoodRule
(
- {&PREDICATE_CUMULUS, &PREDICATE_AXONE},
+ {&PREDICATE_CUMULUS},
ALL_ON_PG_MASK,
MC_R1_AG_MASK,
USE_CHIPLET_ID,
APPLICABLE_TO_ALL,
NO_SPECIAL_RULE
),
- // MC Rule 2: Chiplet N1 must be checked for chip unit 1
+ // MC Rule 1 (Axone)
+ new PartialGoodRule
+ (
+ {&PREDICATE_AXONE},
+ ALL_ON_PG_MASK,
+ MC_R1_AG_MASK_AXONE,
+ USE_CHIPLET_ID,
+ APPLICABLE_TO_ALL,
+ NO_SPECIAL_RULE
+ ),
+ // MC Rule 2: Chiplet N1 must be checked for chip unit 1 (Axone & Cumulus)
new PartialGoodRule
(
{&PREDICATE_CUMULUS, &PREDICATE_AXONE},
@@ -553,7 +564,7 @@ namespace PARTIAL_GOOD
ONE_BIT_CU_MASK,
NO_SPECIAL_RULE
),
- // MC Rule 3: Chiplet N3 must be checked for chip unit 0
+ // MC Rule 3: Chiplet N3 must be checked for chip unit 0 (Axone & Cumulus)
new PartialGoodRule
(
{&PREDICATE_CUMULUS, &PREDICATE_AXONE},
diff --git a/src/include/usr/hwas/common/vpdConstants.H b/src/include/usr/hwas/common/vpdConstants.H
index 498f6d622..9461550e9 100644
--- a/src/include/usr/hwas/common/vpdConstants.H
+++ b/src/include/usr/hwas/common/vpdConstants.H
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -45,38 +45,43 @@ const uint32_t VPD_CP00_PG_DATA_ENTRIES = VPD_CP00_PG_DATA_LENGTH / 2;
// '0' = region is good (NOTE: opposite of P8 where '1' represented good)
// '1' = region is bad or does not exist
-const uint32_t VPD_CP00_PG_FSI_INDEX = 0;
+const uint32_t VPD_CP00_PG_FSI_INDEX = 0;
// all good - 4:FSI0, 5:FSI1, 6:FSIa
-const uint32_t VPD_CP00_PG_FSI_GOOD = 0xF1FF;
+const uint32_t VPD_CP00_PG_FSI_GOOD = 0xF1FF;
-const uint32_t VPD_CP00_PG_PERVASIVE_INDEX = 1;
+const uint32_t VPD_CP00_PG_PERVASIVE_INDEX = 1;
// all good - 3:VITAL, 4:PRV, 5:NET, 6:PIB, 7:OCC, 8:ANPERV, 14:PLLNEST
-const uint32_t VPD_CP00_PG_PERVASIVE_GOOD = 0xE07D;
+const uint32_t VPD_CP00_PG_PERVASIVE_GOOD = 0xE07D;
+// all good - 3:VITAL, 4:PRV, 5:NET, 6:PIB, 7:OCC, 8:BE, 9:SBE 14:PLLNEST
+const uint32_t VPD_CP00_PG_PERVASIVE_GOOD_AXONE = 0xE03D;
-const uint32_t VPD_CP00_PG_N0_INDEX = 2;
+const uint32_t VPD_CP00_PG_N0_INDEX = 2;
// all good - 3:VITAL, 4:PRV, 5:NX, 6:CXA0, 7:PBIOE0, 8:PBIOE1, 9:PBIOE2
-const uint32_t VPD_CP00_PG_N0_GOOD = 0xE03F;
+const uint32_t VPD_CP00_PG_N0_GOOD = 0xE03F;
-const uint32_t VPD_CP00_PG_N1_INDEX = 3;
+const uint32_t VPD_CP00_PG_N1_INDEX = 3;
// all good - 3:VITAL, 4:PRV, 5:MCD, 6:VA, 7:PBIOO0+, 8:PBIOO1+, 9:MCS23+
-const uint32_t VPD_CP00_PG_N1_GOOD = 0xE03F;
-const uint32_t VPD_CP00_PG_N1_PG_MASK = 0x01C0;
-const uint32_t VPD_CP00_PG_N1_PBIOO0 = 0x0100;
-const uint32_t VPD_CP00_PG_N1_PBIOO1 = 0x0080;
-const uint32_t VPD_CP00_PG_N1_MCS23 = 0x0040;
+const uint32_t VPD_CP00_PG_N1_GOOD = 0xE03F;
+const uint32_t VPD_CP00_PG_N1_PG_MASK = 0x01C0;
+const uint32_t VPD_CP00_PG_N1_PBIOO0 = 0x0100;
+const uint32_t VPD_CP00_PG_N1_PBIOO1 = 0x0080;
+const uint32_t VPD_CP00_PG_N1_MCS23 = 0x0040;
-const uint32_t VPD_CP00_PG_N2_INDEX = 4;
+const uint32_t VPD_CP00_PG_N2_INDEX = 4;
// all good - 3:VITAL, 4:PRV, 5:CXA1, 6:PCIS0, 7:PCIS1, 8:PCIS2, 9:IOPSI
-const uint32_t VPD_CP00_PG_N2_GOOD = 0xE03F;
+const uint32_t VPD_CP00_PG_N2_GOOD = 0xE03F;
+// all good - 3:VITAL, 4:PRV, 6:PCIS0, 7:PCIS1, 8:PCIS2, 9:IOPSI
+const uint32_t VPD_CP00_PG_N2_GOOD_AXONE = 0xE43F;
-const uint32_t VPD_CP00_PG_N3_INDEX = 5;
+
+const uint32_t VPD_CP00_PG_N3_INDEX = 5;
// all good - 3:VITAL, 4:PRV, 5:PB, 6:BR, 7:NPU+, 8:MM, 9:INT, 10:MCS01+
-const uint32_t VPD_CP00_PG_N3_GOOD = 0xE01F;
-const uint32_t VPD_CP00_PG_N3_PG_MASK = 0x0120;
-const uint32_t VPD_CP00_PG_N3_NPU = 0x0100;
-const uint32_t VPD_CP00_PG_N3_MCS01 = 0x0020;
+const uint32_t VPD_CP00_PG_N3_GOOD = 0xE01F;
+const uint32_t VPD_CP00_PG_N3_PG_MASK = 0x0120;
+const uint32_t VPD_CP00_PG_N3_NPU = 0x0100;
+const uint32_t VPD_CP00_PG_N3_MCS01 = 0x0020;
-const uint32_t VPD_CP00_PG_XBUS_INDEX = 6;
+const uint32_t VPD_CP00_PG_XBUS_INDEX = 6;
// all good - 3:VITAL, 4:PRV, 5:IOX0*, 6:IOX1, 7:IOX2, 8:IOPPE
// 9:PBIOX0*+, 10:PBIOX1+, 11:PBIOX2+, 14:PLLIOX
// Nimbus doesn't physically have PBIOX0 and IOX0. IOX0 is
@@ -92,14 +97,14 @@ const uint32_t VPD_CP00_PG_XBUS_INDEX = 6;
// 0xE40D --> xbus chiplet good
// and rely solely on the pbiox as the Xbus target indicator
// (0x0040, 0x0020, 0x0010) for all types of chips.
-const uint32_t VPD_CP00_PG_XBUS_GOOD_NIMBUS = 0xE40D;
-const uint32_t VPD_CP00_PG_XBUS_GOOD_CUMULUS= 0xE00D;
-const uint32_t VPD_CP00_PG_XBUS_PG_MASK = 0x00170;
-const uint32_t VPD_CP00_PG_XBUS_IOX[3] = {0x0040, 0x0020, 0x0010};
-
-const uint32_t VPD_CP00_PG_MC01_INDEX = 7;
-const uint32_t VPD_CP00_PG_MC23_INDEX = 8;
-const uint32_t VPD_CP00_PG_MCxx_INDEX[4] = {VPD_CP00_PG_MC01_INDEX,
+const uint32_t VPD_CP00_PG_XBUS_GOOD_NIMBUS = 0xE40D;
+const uint32_t VPD_CP00_PG_XBUS_GOOD_CUMULUS = 0xE00D;
+const uint32_t VPD_CP00_PG_XBUS_PG_MASK = 0x00170;
+const uint32_t VPD_CP00_PG_XBUS_IOX[3] = {0x0040, 0x0020, 0x0010};
+
+const uint32_t VPD_CP00_PG_MC01_INDEX = 7;
+const uint32_t VPD_CP00_PG_MC23_INDEX = 8;
+const uint32_t VPD_CP00_PG_MCxx_INDEX[4] = {VPD_CP00_PG_MC01_INDEX,
VPD_CP00_PG_MC01_INDEX,
VPD_CP00_PG_MC23_INDEX,
VPD_CP00_PG_MC23_INDEX}; // by MCS
@@ -109,56 +114,60 @@ const uint32_t VPD_CP00_PG_MCxx_INDEX[4] = {VPD_CP00_PG_MC01_INDEX,
// Cumulus:
// all good - 3:VITAL, 4:PRV, 5:MC01, 6:IOM01, 7:IOM01PPE, 14:PLLMEM
// all good - 3:VITAL, 4:PRV, 5:MC23, 6:IOM23, 7:IOM23PPE, 14:PLLMEM
-const uint32_t VPD_CP00_PG_MCxx_GOOD = 0xE0FD;
-const uint32_t VPD_CP00_PG_MCxx_PG_MASK = 0x0300; // Nimbus only
+// Axone:
+// all good - 3:VITAL, 4:PRV, 5:MC01, 6:OMI00, 7:OMI01, 8:OMI002 9:OMIPPE00 14:PLLOMI00
+// all good - 3:VITAL, 4:PRV, 5:MC23, 6:OMI10, 7:OMI11, 8:OMI012 9:OMIPPE10 14:PLLOMI10
+const uint32_t VPD_CP00_PG_MCxx_GOOD = 0xE0FD;
+const uint32_t VPD_CP00_PG_MCxx_GOOD_AXONE = 0xE03D;
+const uint32_t VPD_CP00_PG_MCxx_PG_MASK = 0x0300; // Nimbus only
// iom0 and iom4 need to be good for zqcal to work on any
// of the MCAs on that side
-const uint32_t VPD_CP00_PG_MCA_MAGIC_PORT_MASK = 0x0200;
-const uint32_t VPD_CP00_PG_MCxx_IOMyy[4] = {0x0200, 0x0100, 0x0200, 0x0100};
+const uint32_t VPD_CP00_PG_MCA_MAGIC_PORT_MASK = 0x0200;
+const uint32_t VPD_CP00_PG_MCxx_IOMyy[4] = {0x0200, 0x0100, 0x0200, 0x0100};
-const uint32_t VPD_CP00_PG_OB0_INDEX = 9;
-const uint32_t VPD_CP00_PG_OB3_INDEX = 12;
+const uint32_t VPD_CP00_PG_OB0_INDEX = 9;
+const uint32_t VPD_CP00_PG_OB3_INDEX = 12;
// all good - 3:VITAL, 4:PRV, 5:PLIOOAx, 6:IOOx, 14:PLLIOO; x=0, 1*, 2*, 3
-const uint32_t VPD_CP00_PG_OBUS_GOOD = 0xE1FD;
+const uint32_t VPD_CP00_PG_OBUS_GOOD = 0xE1FD;
-const uint32_t VPD_CP00_PG_PCI0_INDEX = 13;
+const uint32_t VPD_CP00_PG_PCI0_INDEX = 13;
// all good - 3:VITAL, 4:PRV, 5:PCI00, 6:IOPCI0, 14:PLLPCI0
// all good - 3:VITAL, 4:PRV, 5:PCI11, 6:PCI12, 7:IOPCI1, 14:PLLPCI1
// all good - 3:VITAL, 4:PRV, 5:PCI23, 6:PCI24, 7:PCI25, 8:IOPCI2, 14:PLLPCI2
-const uint32_t VPD_CP00_PG_PCIx_GOOD[3] = {0xE1FD, 0xE0FD, 0xE07D};
+const uint32_t VPD_CP00_PG_PCIx_GOOD[3] = {0xE1FD, 0xE0FD, 0xE07D};
-const uint32_t VPD_CP00_PG_EP0_INDEX = 16;
-const uint32_t VPD_CP00_PG_EP5_INDEX = 21;
+const uint32_t VPD_CP00_PG_EP0_INDEX = 16;
+const uint32_t VPD_CP00_PG_EP5_INDEX = 21;
// all good - 3:VITAL, 4:PRV, 5:EQPB, 6:L30+, 7:L31+,
// 8:L20+, 9:L21+, 10:AN, 11:PBLEQ, 12:REFR0, 13:REFR1, 14:DPLL
-const uint32_t VPD_CP00_PG_EPx_GOOD = 0xE001;
-const uint32_t VPD_CP00_PG_EPx_PG_MASK = 0x03CC;
-const uint32_t VPD_CP00_PG_EPx_L3L2REFR[2] = {0x0288, 0x0144};
+const uint32_t VPD_CP00_PG_EPx_GOOD = 0xE001;
+const uint32_t VPD_CP00_PG_EPx_PG_MASK = 0x03CC;
+const uint32_t VPD_CP00_PG_EPx_L3L2REFR[2] = {0x0288, 0x0144};
-const uint32_t VPD_CP00_PG_EC00_INDEX = 32;
+const uint32_t VPD_CP00_PG_EC00_INDEX = 32;
// all good - 3:VITAL, 4:PRV, 5:C00, 6:C01
-const uint32_t VPD_CP00_PG_ECxx_GOOD = 0xE1FF;
-const uint32_t VPD_CP00_PG_ECxx_MAX_ENTRIES = 24;
+const uint32_t VPD_CP00_PG_ECxx_GOOD = 0xE1FF;
+const uint32_t VPD_CP00_PG_ECxx_MAX_ENTRIES = 24;
-const uint32_t VPD_CP00_PG_MAX_USED_INDEX = 55;
-const uint32_t VPD_CP00_PG_xxx_VITAL = 0x1000;
-const uint32_t VPD_CP00_PG_xxx_PERV = 0x0800;
-const uint32_t VPD_CP00_PG_RESERVED_GOOD = 0xFFFF;
+const uint32_t VPD_CP00_PG_MAX_USED_INDEX = 55;
+const uint32_t VPD_CP00_PG_xxx_VITAL = 0x1000;
+const uint32_t VPD_CP00_PG_xxx_PERV = 0x0800;
+const uint32_t VPD_CP00_PG_RESERVED_GOOD = 0xFFFF;
// constants the platReadPR will use for looking at the VPD data
-const uint32_t VPD_VINI_PR_DATA_LENGTH = 8; //@deprecrated
+const uint32_t VPD_VINI_PR_DATA_LENGTH = 8; //@deprecrated
// constants the platReadLx will use for looking at the VPD data
-const uint32_t VPD_CRP0_LX_HDR_DATA_LENGTH = 256;
+const uint32_t VPD_CRP0_LX_HDR_DATA_LENGTH = 256;
-const uint32_t VPD_CRP0_LX_FREQ_INDEP_INDEX = 8;
-const uint32_t VPD_CRP0_LX_PORT_DISABLED = 0;
+const uint32_t VPD_CRP0_LX_FREQ_INDEP_INDEX = 8;
+const uint32_t VPD_CRP0_LX_PORT_DISABLED = 0;
-const uint8_t VPD_CRP0_LX_MIN_X = 1;
-const uint8_t VPD_CRP0_LX_MAX_X = 8;
+const uint8_t VPD_CRP0_LX_MIN_X = 1;
+const uint8_t VPD_CRP0_LX_MAX_X = 8;
// constants for the error log parser for partial good issues
-const uint8_t MODEL_PG_DATA_ENTRIES = 2;
+const uint8_t MODEL_PG_DATA_ENTRIES = 2;
}
diff --git a/src/usr/fapi2/test/fapi2MvpdTestCxx.H b/src/usr/fapi2/test/fapi2MvpdTestCxx.H
index 224879070..92d791908 100644
--- a/src/usr/fapi2/test/fapi2MvpdTestCxx.H
+++ b/src/usr/fapi2/test/fapi2MvpdTestCxx.H
@@ -326,7 +326,8 @@ public:
#ifdef CONFIG_EARLY_TESTCASES
// Requires some prereqs of step7
- FAPI_INF("Skipping poundv tests");
+ FAPI_INF("Skipping poundv tests due to CONFIG_EARLY_TESTCASES");
+
#else
fapi2::ReturnCode l_rc;
@@ -421,7 +422,8 @@ public:
#ifdef CONFIG_EARLY_TESTCASES
// Requires some prereqs of step7
- FAPI_INF("Skipping poundv tests");
+ FAPI_INF("Skipping poundw tests due to CONFIG_EARLY_TESTCASES");
+
#else
fapi2::ReturnCode l_rc;
diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C
index f0ce3ed04..580d6ef60 100644
--- a/src/usr/hwas/common/hwas.C
+++ b/src/usr/hwas/common/hwas.C
@@ -970,6 +970,13 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target,
uint16_t l_xbus = (l_model == MODEL_NIMBUS) ?
VPD_CP00_PG_XBUS_GOOD_NIMBUS : VPD_CP00_PG_XBUS_GOOD_CUMULUS;
+ uint16_t l_perv = (l_model == MODEL_AXONE) ?
+ VPD_CP00_PG_PERVASIVE_GOOD_AXONE : VPD_CP00_PG_PERVASIVE_GOOD;
+
+ uint16_t l_n2 = (l_model == MODEL_AXONE) ?
+ VPD_CP00_PG_N2_GOOD_AXONE : VPD_CP00_PG_N2_GOOD;
+
+
// Check all bits in FSI entry
if (i_pgData[VPD_CP00_PG_FSI_INDEX] !=
VPD_CP00_PG_FSI_GOOD)
@@ -985,14 +992,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target,
else
// Check all bits in PRV entry
if (i_pgData[VPD_CP00_PG_PERVASIVE_INDEX] !=
- VPD_CP00_PG_PERVASIVE_GOOD)
+ l_perv)
{
HWAS_INF("pTarget %.8X - Pervasive pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_PERVASIVE_INDEX,
i_pgData[VPD_CP00_PG_PERVASIVE_INDEX],
- VPD_CP00_PG_PERVASIVE_GOOD);
+ l_perv);
l_chipFunctional = false;
}
else
@@ -1022,14 +1029,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target,
}
else
// Check all bits in N2 entry
- if (i_pgData[VPD_CP00_PG_N2_INDEX] != VPD_CP00_PG_N2_GOOD)
+ if (i_pgData[VPD_CP00_PG_N2_INDEX] != l_n2)
{
HWAS_INF("pTarget %.8X - N2 pgData[%d]: "
"actual 0x%04X, expected 0x%04X - bad",
i_target->getAttr<ATTR_HUID>(),
VPD_CP00_PG_N2_INDEX,
i_pgData[VPD_CP00_PG_N2_INDEX],
- VPD_CP00_PG_N2_GOOD);
+ l_n2);
l_chipFunctional = false;
}
else
diff --git a/src/usr/hwas/common/pgLogic.C b/src/usr/hwas/common/pgLogic.C
index 2cc30944f..edcb41b9a 100644
--- a/src/usr/hwas/common/pgLogic.C
+++ b/src/usr/hwas/common/pgLogic.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2018 */
+/* Contributors Listed Below - COPYRIGHT 2018,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -134,6 +134,7 @@ namespace PARTIAL_GOOD
// MC
// PG/AG Masks
const uint16_t MC_R1_AG_MASK = 0xE0FD;
+ const uint16_t MC_R1_AG_MASK_AXONE = 0xE03D;
const uint16_t MC_R2_PG_MASK = 0x0040;
const uint16_t MC_R3_PG_MASK = 0x0020;
diff --git a/src/usr/hwas/test/hwas1test.H b/src/usr/hwas/test/hwas1test.H
index 6784d4408..759ad7ad7 100644
--- a/src/usr/hwas/test/hwas1test.H
+++ b/src/usr/hwas/test/hwas1test.H
@@ -48,8 +48,74 @@
#include <targeting/common/commontargeting.H>
#include <targeting/common/utilFilter.H>
+const uint16_t pgDataAllGoodAxone[HWAS::VPD_CP00_PG_DATA_ENTRIES] =
+ {(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD_AXONE,
+ (uint16_t)HWAS::VPD_CP00_PG_N0_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_N1_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_N2_GOOD_AXONE,
+ (uint16_t)HWAS::VPD_CP00_PG_N3_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_XBUS_GOOD_CUMULUS,
+ (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE,
+ (uint16_t)HWAS::VPD_CP00_PG_MCxx_GOOD_AXONE,
+ (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_OBUS_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[0],
+ (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[1],
+ (uint16_t)HWAS::VPD_CP00_PG_PCIx_GOOD[2],
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_EPx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_ECxx_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD,
+ (uint16_t)HWAS::VPD_CP00_PG_RESERVED_GOOD};
+
// Buffer with all good data (CUMULUS chip)
-const uint16_t pgDataAllGood[HWAS::VPD_CP00_PG_DATA_ENTRIES] =
+const uint16_t pgDataAllGoodCumulus[HWAS::VPD_CP00_PG_DATA_ENTRIES] =
{(uint16_t)HWAS::VPD_CP00_PG_FSI_GOOD,
(uint16_t)HWAS::VPD_CP00_PG_PERVASIVE_GOOD,
(uint16_t)HWAS::VPD_CP00_PG_N0_GOOD,
@@ -371,9 +437,20 @@ public:
? (uint16_t)VPD_CP00_PG_RESERVED_GOOD
: (uint16_t)VPD_CP00_PG_OBUS_GOOD;
uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES];
- memcpy(pgData,
- pgDataAllGood,
- VPD_CP00_PG_DATA_LENGTH);
+
+ if(MODEL_AXONE == l_model)
+ {
+ memcpy(pgData,
+ pgDataAllGoodAxone,
+ VPD_CP00_PG_DATA_LENGTH);
+ }
+ else
+ {
+ memcpy(pgData,
+ pgDataAllGoodCumulus,
+ VPD_CP00_PG_DATA_LENGTH);
+ }
+
pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus;
pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12;
pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12;
@@ -460,9 +537,18 @@ public:
l_mask);
}
- // Restore the "all good" data
- pgData[VPD_CP00_PG_PERVASIVE_INDEX] =
- (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_PERVASIVE_INDEX] =
+ (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_PERVASIVE_INDEX] =
+ (uint16_t)VPD_CP00_PG_PERVASIVE_GOOD;
+ }
}
TS_INFO( "testHWASisChipFunctional: N0 is not functional");
@@ -562,6 +648,19 @@ public:
// Restore the "all good" data
pgData[VPD_CP00_PG_N2_INDEX] =
(uint16_t)VPD_CP00_PG_N2_GOOD;
+
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_N2_INDEX] =
+ (uint16_t)VPD_CP00_PG_N2_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_N2_INDEX] =
+ (uint16_t)VPD_CP00_PG_N2_GOOD;
+ }
}
TS_INFO( "testHWASisChipFunctional: N3 is not functional");
@@ -686,9 +785,20 @@ public:
? (uint16_t)VPD_CP00_PG_RESERVED_GOOD
: (uint16_t)VPD_CP00_PG_OBUS_GOOD;
uint16_t pgData[VPD_CP00_PG_DATA_ENTRIES];
- memcpy(pgData,
- pgDataAllGood,
- VPD_CP00_PG_DATA_LENGTH);
+
+ if(MODEL_AXONE == l_model)
+ {
+ memcpy(pgData,
+ pgDataAllGoodAxone,
+ VPD_CP00_PG_DATA_LENGTH);
+ }
+ else
+ {
+ memcpy(pgData,
+ pgDataAllGoodCumulus,
+ VPD_CP00_PG_DATA_LENGTH);
+ }
+
pgData[VPD_CP00_PG_XBUS_INDEX] = l_xbus;
pgData[VPD_CP00_PG_OB0_INDEX + 1] = l_obus12;
pgData[VPD_CP00_PG_OB0_INDEX + 2] = l_obus12;
@@ -1107,9 +1217,19 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
break;
@@ -1208,8 +1328,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
break;
@@ -1307,8 +1437,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
break;
@@ -1406,8 +1546,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
break;
@@ -1506,8 +1656,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[l_indexMC] = VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[l_indexMC] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
break;
@@ -1871,9 +2031,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
- (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
@@ -1987,9 +2156,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- // Restore the "all good" data
- pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] =
- (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
}
// TEST WITH BAD MAGIC PORT (MCA0 or MCA4)
@@ -2038,8 +2216,18 @@ public:
pDesc->getAttr<ATTR_HUID>());
}
- pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] =
- (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit / 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
// Try bad MCA Port setting for MCA2/3 & MCA6/7
if ( VPD_CP00_PG_MCxx_IOMyy[l_chipUnit / 2] !=
@@ -2147,8 +2335,19 @@ public:
}
// Restore the "all good" data
- pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
- (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ if(MODEL_AXONE == l_model)
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD_AXONE;
+ }
+ else
+ {
+ // Restore the "all good" data
+ pgData[VPD_CP00_PG_MCxx_INDEX[l_chipUnit * 2]] =
+ (uint16_t)VPD_CP00_PG_MCxx_GOOD;
+ }
+
}
diff --git a/src/usr/vpd/ipvpd.C b/src/usr/vpd/ipvpd.C
index 168bc5d36..2195ab3c3 100644
--- a/src/usr/vpd/ipvpd.C
+++ b/src/usr/vpd/ipvpd.C
@@ -1896,21 +1896,31 @@ errlHndl_t IpVpdFacade::findKeywordAddr ( const char * i_keywordName,
offset,
i_recordName );
+ // convert data for SRC display
+ uint32_t exp_rec;
+ memcpy( &exp_rec, i_recordName, RECORD_BYTE_SIZE );
+ uint32_t act_rec;
+ memcpy( &act_rec, record, RECORD_BYTE_SIZE );
+
/*@
* @errortype
* @reasoncode VPD::VPD_RECORD_MISMATCH
* @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE
* @moduleid VPD::VPD_IPVPD_FIND_KEYWORD_ADDR
- * @userdata1 Current offset into VPD
- * @userdata2 Start of Record offset
+ * @userdata1[00:31] Current offset into VPD
+ * @userdata1[32:63] Start of Record offset
+ * @userdata2[00:31] Expected record name
+ * @userdata2[32:63] Found record name
* @devdesc Record name does not match value expected for
* offset read.
*/
err = new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE,
VPD::VPD_IPVPD_FIND_KEYWORD_ADDR,
VPD::VPD_RECORD_MISMATCH,
- offset,
- i_offset );
+ TWO_UINT32_TO_UINT64(offset,
+ i_offset ),
+ TWO_UINT32_TO_UINT64(exp_rec,
+ act_rec) );
// Could be the VPD of the target wasn't set up properly
// -- DECONFIG so that we can possibly keep booting
diff --git a/src/usr/vpd/pvpd.C b/src/usr/vpd/pvpd.C
index 371a87deb..8d33a24af 100644
--- a/src/usr/vpd/pvpd.C
+++ b/src/usr/vpd/pvpd.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2013,2018 */
+/* Contributors Listed Below - COPYRIGHT 2013,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -42,6 +42,7 @@
#include <config.h>
#include "pvpd.H"
#include "cvpd.H"
+#include "dvpd.H"
#include "vpd.H"
#include <initservice/initserviceif.H>
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