Refresh Memory HWPs

Change-Id: Id15d99072821587d1abd2c399042b5b64f859cef
RTC: 59193
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2690
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

59 files changed, 24606 insertions, 7088 deletions

diff --git a/src/build/citest/etc/patches/centaur.act.slew.patch b/src/build/citest/etc/patches/centaur.act.slew.patch
new file mode 100644
index 000000000..089c52ecd
--- /dev/null
+++ b/src/build/citest/etc/patches/centaur.act.slew.patch
@@ -0,0 +1,53 @@
+--- /esw/fips810/Builds/b1207x_1251.810/src/simu/data/cec-chip/centaur.act      2012-09-18 09:23:16.000000000 -0500
++++ ./centaur.act       2012-12-13 20:00:14.319266193 -0600
+@@ -29,6 +29,7 @@
+ #  ch139 F849719   ched      08/28/12  Apply Dean Sanner's fix for "OPCG SCAN0"
+ #                                      action
+ #        SW164340  bradleyb  09/18/12  temp back out mdia actions
++#        SW178996  mjjones   12/13/12  Slew calibration actions
+ #********************************************************************
+ #  
+ 
+@@ -89,6 +90,42 @@
+ }
+ 
+ CAUSE_EFFECT {
++  LABEL=[Slew calibration for MBA0 Port0]
++  WATCH=[INDSCOM_0x0301143F(0x00008039)]  # SLEW_CAL_CNTL_P0
++  CAUSE: TARGET=[INDSCOM_0x0301143F(0x00008039)] OP=[BIT,ON] BIT=[48] # Set Start bit
++  EFFECT: TARGET=[INDSCOM_0x0301143F(0x00008034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT
++    # 0x30 = Status Mask. 0x30 = Done with no errors
++    # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good
++}
++
++CAUSE_EFFECT {
++  LABEL=[Slew calibration for MBA0 Port1]
++  WATCH=[INDSCOM_0x0301143F(0x00018039)]  # SLEW_CAL_CNTL_P1
++  CAUSE: TARGET=[INDSCOM_0x0301143F(0x00018039)] OP=[BIT,ON] BIT=[48] # Set Start bit
++  EFFECT: TARGET=[INDSCOM_0x0301143F(0x00018034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT
++    # 0x30 = Status Mask. 0x30 = Done with no errors
++    # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good
++}
++
++CAUSE_EFFECT {
++  LABEL=[Slew calibration for MBA1 Port0]
++  WATCH=[INDSCOM_0x0301183F(0x00008039)]  # SLEW_CAL_CNTL_P0
++  CAUSE: TARGET=[INDSCOM_0x0301183F(0x00008039)] OP=[BIT,ON] BIT=[48] # Set Start bit
++  EFFECT: TARGET=[INDSCOM_0x0301183F(0x00008034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT
++    # 0x30 = Status Mask. 0x30 = Done with no errors
++    # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good
++}
++
++CAUSE_EFFECT {
++  LABEL=[Slew calibration for MBA0 Port1]
++  WATCH=[INDSCOM_0x0301183F(0x00018039)]  # SLEW_CAL_CNTL_P1
++  CAUSE: TARGET=[INDSCOM_0x0301183F(0x00018039)] OP=[BIT,ON] BIT=[48] # Set Start bit
++  EFFECT: TARGET=[INDSCOM_0x0301183F(0x00018034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT
++    # 0x30 = Status Mask. 0x30 = Done with no errors
++    # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good
++}
++
++CAUSE_EFFECT {
+   # copy chip ID
+   LABEL=[DEVICE_ID_REG] # TPTOP.PIB.PCBMS.DEVICE_ID_REG
+   WATCH_READ=[REG(0x000F000F)]  # if someone reads this
diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt
index 15fd3a66c..a9e47c22d 100644
--- a/src/build/citest/etc/patches/patchlist.txt
+++ b/src/build/citest/etc/patches/patchlist.txt
@@ -10,3 +10,21 @@ New actions for Centaur maint command complete
 -CMVC: D862701 is integrating the changes
 -Files: centaur.act.patch
 -Coreq: there are related changes in workarounds.postsimsetup
+
+Bus training does not set all 5 training bits at once, therefore the
+Murano Action File must cope with any bit being set.
+Proc-Cen Framelock now looks for a different status bit in a different
+register, therefore the Murano Action File must cope
+-RTC: Task 60658 will remove this patch
+-CMVC: 864393
+-Files: s1.act.io.patch
+-Coreq: None
+
+Centaur Slew calibration sets a start bit in a register and looks
+for completion and calibration values in another register, therefore
+the Centaur Action File must cope
+-RTC: Task 60658 will remove this patch
+-CMVC: 864393
+-Files: centaur.act.slew.patch
+-Coreq: None
+
diff --git a/src/build/citest/etc/patches/s1.act.io.patch b/src/build/citest/etc/patches/s1.act.io.patch
new file mode 100644
index 000000000..57b42e25c
--- /dev/null
+++ b/src/build/citest/etc/patches/s1.act.io.patch
@@ -0,0 +1,223 @@
+--- /esw/fips810/Builds/b1207x_1251.810/src/simu/data/cec-chip/s1.act   2012-11-19 16:58:36.000000000 -0600
++++ ./s1.act    2012-12-13 20:12:09.282244491 -0600
+@@ -15,6 +15,8 @@
+ #        SW170609  sankarkk  10/13/12  Added ramming support
+ #  to99  SW170119  opiet     10/23/12  Set Core 1 functional bit
+ # dds129 SW175501  jlortiz   11/19/12  changes for SBEstart action
++#        SW178996  mjjones   12/11/12  Breakout DMI run_training bits
++#                                      Update framelock FRTL actions
+ 
+ # ch110 send instruction start signal to phyp model for core 5, thread 0
+ CAUSE_EFFECT {
+@@ -95,7 +97,7 @@
+   WATCH=[REG(0x02011C4A)]  # MCI4_CFG_REG
+   CAUSE: TARGET=[REG(0x02011C4A)] OP=[BIT,ON] BIT=[8] # MCI4_CFG_REG[8] - Start Frame Lock Frtl
+   EFFECT: TARGET=[REG(0x02011C4B)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG  - Frame Lock Frtl Pass
+-  EFFECT: TARGET=[ALIAS(mymcPort4)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG  - Frame Lock Frtl Pass
++  EFFECT: TARGET=[REG(0x02011C4B)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG  - Frame Lock Channel Interlock Pass
+ }
+ 
+ CAUSE_EFFECT {
+@@ -111,7 +113,7 @@
+   WATCH=[REG(0x02011CCA)]  # MCI5_CFG_REG
+   CAUSE: TARGET=[REG(0x02011CCA)] OP=[BIT,ON] BIT=[8] # MCI5_CFG_REG[8] - Start Frame Lock Frtl
+   EFFECT: TARGET=[REG(0x02011CCB)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG  - Frame Lock Frtl Pass
+-  EFFECT: TARGET=[ALIAS(mymcPort5)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG  - Frame Lock Frtl Pass
++  EFFECT: TARGET=[REG(0x02011CCB)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG  - Frame Lock Channel Interlock Pass
+ }
+ 
+ CAUSE_EFFECT {
+@@ -127,7 +129,7 @@
+   WATCH=[REG(0x02011D4A)]  # MCI6_CFG_REG
+   CAUSE: TARGET=[REG(0x02011D4A)] OP=[BIT,ON] BIT=[8] # MCI6_CFG_REG[8] - Start Frame Lock Frtl
+   EFFECT: TARGET=[REG(0x02011D4B)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG  - Frame Lock Frtl Pass
+-  EFFECT: TARGET=[ALIAS(mymcPort6)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG  - Frame Lock Frtl Pass
++  EFFECT: TARGET=[REG(0x02011D4B)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG  - Frame Lock Channel Interlock Pass
+ }
+ 
+ CAUSE_EFFECT {
+@@ -143,39 +145,167 @@
+   WATCH=[REG(0x02011DCA)]  # MCI7_CFG_REG
+   CAUSE: TARGET=[REG(0x02011DCA)] OP=[BIT,ON] BIT=[8] # MCI7_CFG_REG[8] - Start Frame Lock Frtl
+   EFFECT: TARGET=[REG(0x02011DCB)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG  - Frame Lock Frtl Pass
+-  EFFECT: TARGET=[ALIAS(mymcPort7)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG  - Frame Lock Frtl Pass
++  EFFECT: TARGET=[REG(0x02011DCB)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG  - Frame Lock Channel Interlock Pass
+ }
+ 
+ CAUSE_EFFECT {
+-  LABEL=[IO_run_training for MCS4]
++  LABEL=[IO_run_training wiretest for MCS4]
+   WATCH=[INDSCOM_0x02011E3F(0x00088060)]  # start trigger register
+-  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0]
+-  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)]
+-  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)]
++  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[48]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[48]
+ }
+ 
+ CAUSE_EFFECT {
+-  LABEL=[IO_run_training for MCS5]
++  LABEL=[IO_run_training deskew for MCS4]
++  WATCH=[INDSCOM_0x02011E3F(0x00088060)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[49]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[49]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training eye_opt for MCS4]
++  WATCH=[INDSCOM_0x02011E3F(0x00088060)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[50]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[50]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training repair for MCS4]
++  WATCH=[INDSCOM_0x02011E3F(0x00088060)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[51]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[51]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training func_mode for MCS4]
++  WATCH=[INDSCOM_0x02011E3F(0x00088060)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[52]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[52]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training wiretest for MCS5]
++  WATCH=[INDSCOM_0x02011E3F(0x00088040)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[48]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[48]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training deskew for MCS5]
++  WATCH=[INDSCOM_0x02011E3F(0x00088040)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[49]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[49]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training eye_opt for MCS5]
++  WATCH=[INDSCOM_0x02011E3F(0x00088040)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[50]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[50]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training repair for MCS5]
++  WATCH=[INDSCOM_0x02011E3F(0x00088040)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[51]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[51]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training func_mode for MCS5]
+   WATCH=[INDSCOM_0x02011E3F(0x00088040)]  # start trigger register
+-  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0]
+-  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)]
+-  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)]
++  CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[52]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[52]
+ }
+ 
+ CAUSE_EFFECT {
+-  LABEL=[IO_run_training for MCS6]
++  LABEL=[IO_run_training wiretest for MCS6]
+   WATCH=[INDSCOM_0x02011E3F(0x00088020)]  # start trigger register
+-  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0]
+-  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)]
+-  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)]
++  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[48]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[48]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training deskew for MCS6]
++  WATCH=[INDSCOM_0x02011E3F(0x00088020)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[49]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[49]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training eye_opt for MCS6]
++  WATCH=[INDSCOM_0x02011E3F(0x00088020)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[50]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[50]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training repair for MCS6]
++  WATCH=[INDSCOM_0x02011E3F(0x00088020)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[51]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[51]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training func_mode for MCS6]
++  WATCH=[INDSCOM_0x02011E3F(0x00088020)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[52]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[52]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training wiretest for MCS7]
++  WATCH=[INDSCOM_0x02011E3F(0x00088000)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[48]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[48]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training deskew for MCS7]
++  WATCH=[INDSCOM_0x02011E3F(0x00088000)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[49]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[49]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training eye_opt for MCS7]
++  WATCH=[INDSCOM_0x02011E3F(0x00088000)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[50]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[50]
++}
++
++CAUSE_EFFECT {
++  LABEL=[IO_run_training repair for MCS7]
++  WATCH=[INDSCOM_0x02011E3F(0x00088000)]  # start trigger register
++  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[51]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[51]
+ }
+ 
+ CAUSE_EFFECT {
+-  LABEL=[IO_run_training for MCS7]
++  LABEL=[IO_run_training func_mode for MCS7]
+   WATCH=[INDSCOM_0x02011E3F(0x00088000)]  # start trigger register
+-  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0]
+-  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)]
+-  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)]
++  CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52]
++  CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[52]
++  EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[52]
+ }
+ 
+ CAUSE_EFFECT {
diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup
index 23a4f4dc7..06aadb666 100755
--- a/src/build/citest/etc/workarounds.postsimsetup
+++ b/src/build/citest/etc/workarounds.postsimsetup
@@ -32,6 +32,10 @@ mkdir -p $sb/simu/data/cec-chip/
 cp $bb/src/simu/data/cec-chip/centaur.act $sb/simu/data/cec-chip/centaur.act
 patch -p0 $sb/simu/data/cec-chip/centaur.act $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act.patch
 
+### Update centaur.act to handle slew calibration (Remove with 60568)
+echo "+++ Updating Centaur Action File to support slew calibration"
+patch -p0 $sb/simu/data/cec-chip/centaur.act $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act.slew.patch
+
 #### Update config file with new variables (Remove with RTC: 59984) ####
 echo "+++ Forcing SBE header usage till Fips defaults to ON"
 mkdir -p $sb/simu/configs
@@ -50,6 +54,10 @@ cp $BACKING_BUILD/src/simu/data/cec-chip/p8.act $sb/simu/data/cec-chip
 sed -i -e's/sbeStart, 0x03eca000,/sbeStart, FSIMBOX(0x3A),/' $sb/simu/data/cec-chip/s1.act
 sed -i -e's/sbeStart, 0x03eca000,/sbeStart, FSIMBOX(0x3A),/' $sb/simu/data/cec-chip/p8.act
 
+### Update s1.act to handle bus training and framelock (Remove with 60568)
+echo "+++ Updating Murano Action File to support bus training and framelock"
+patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.io.patch
+
 cp $BACKING_BUILD/src/simu/data/cec-chip/p8_common.chip $sb/simu/data/cec-chip
 sed -i -e's/0xE0, 32  #MBOX_SCRATCH_0/0x38, 32  #MBOX_SCRATCH_0/' $sb/simu/data/cec-chip/p8_common.chip
 sed -i -e's/0xE4, 32  #MBOX_SCRATCH_1/0x39, 32  #MBOX_SCRATCH_1/' $sb/simu/data/cec-chip/p8_common.chip
diff --git a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
index bbd926656..c4cea0ecd 100755
--- a/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
+++ b/src/include/usr/hwpf/plat/fapiPlatAttributeService.H
@@ -490,6 +490,12 @@ fapi::ReturnCode fapiPlatGetProcPcieBarSize (
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SPD_SDRAM_THERMAL_REFRESH_OPTIONS, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_MODULE_THERMAL_SENSOR_GETMACRO(ID, PTARGET, VAL) \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SPD_MODULE_THERMAL_SENSOR, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_SDRAM_DEVICE_TYPE_GETMACRO(ID, PTARGET, VAL) \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_DEVICE_TYPE, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING_GETMACRO(ID, PTARGET, VAL) \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_DEVICE_TYPE_SIGNAL_LOADING, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_SDRAM_DIE_COUNT_GETMACRO(ID, PTARGET, VAL) \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::SDRAM_DIE_COUNT, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_FINE_OFFSET_TCKMIN_GETMACRO(ID, PTARGET, VAL) \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::TCKMIN_FINE_OFFSET, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_FINE_OFFSET_TAAMIN_GETMACRO(ID, PTARGET, VAL) \
@@ -500,6 +506,8 @@ fapi::ReturnCode fapiPlatGetProcPcieBarSize (
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::TRPMIN_FINE_OFFSET, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_FINE_OFFSET_TRCMIN_GETMACRO(ID, PTARGET, VAL) \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::TRCMIN_FINE_OFFSET, &(VAL), sizeof(VAL) )
+#define ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM_GETMACRO(ID, PTARGET, VAL) \
+    fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::RMM_REGS_RDIMM, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_MODULE_SPECIFIC_SECTION_GETMACRO(ID, PTARGET, VAL) \
     fapi::platAttrSvc::fapiPlatGetSpdAttr( PTARGET, SPD::MODULE_TYPE_SPECIFIC_SECTION, &(VAL), sizeof(VAL) )
 #define ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE_GETMACRO(ID, PTARGET, VAL) \
diff --git a/src/usr/hwpf/hwp/bus_training/io_errors.xml b/src/usr/hwpf/hwp/bus_training/io_errors.xml
index db1d0e266..ab074d0fa 100644
--- a/src/usr/hwpf/hwp/bus_training/io_errors.xml
+++ b/src/usr/hwpf/hwp/bus_training/io_errors.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/bus_training/io_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/bus_training/io_errors.xml $                 -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- Error definitions for IO HWPS  -->
 <hwpErrors>
   <!-- *********************************************************************** -->
@@ -124,4 +124,29 @@
     <rc>IO_DCCAL_ZCAL_TIMEOUT_RC</rc>
     <description>io impedance cal timed out</description>
   </hwpError>
+       <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC</rc>
+    <description>Impedance calibration zcal_n value out of range</description>
+  </hwpError>
+         <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC</rc>
+    <description>Impedance calibration zcal_p value out of range</description>
+  </hwpError>
+           <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_K2_EXCEEDED_RC</rc>
+    <description>Post cursor drive ratio has exceeded 0.25</description>
+  </hwpError>
+             <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_M_EXCEEDED_RC</rc>
+    <description>Margin Ratio has exceeded 100 percentage</description>
+  </hwpError>
+               <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_M_LOW_RC</rc>
+    <description>Margin Ratio is less than 50 percent</description>
+  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index 29ffde61f..94263cb11 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/bus_training/io_funcs.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/io_funcs.C $                    */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: io_funcs.C,v 1.13 2012/12/04 08:28:37 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -104,7 +104,7 @@ ReturnCode  edi_training::run_training_functions(const Target& target, io_interf
 	rc_ecmd|=set_bits.setBitLength(16);
 	rc_ecmd|=clear_bits.setBitLength(16);
 	rc_ecmd|=set_bits.flushTo0();
-	rc_ecmd|=clear_bits.flushTo1();
+	rc_ecmd|=clear_bits.flushTo0();
 	
 	if(rc_ecmd)
 	{
@@ -164,6 +164,7 @@ ReturnCode  edi_training::run_training_functions(const Target& target, io_interf
 		// Set Start Bits for group
 		// Group address is set to 0 , since according to Discussion with Dean ,this code will run once per group.
 		rc_ecmd|=set_bits.insert(bits,0,16);
+
 		if(rc_ecmd)
 		{
 			FAPI_ERR("io_run_training:Data Buffer insertion failed !!\n");
@@ -331,6 +332,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                     
                     if (functional_status == RUNNING)
                     {
+			FAPI_DBG("functional status is Running!!");
                             state=FUNCTIONAL;
                             fail_bit=rx_func_mode_failed;
 			     //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
index aa2e79a3a..6e3883efa 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/bus_training/io_funcs.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/io_funcs.H $                    */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: io_funcs.H,v 1.12 2012/12/04 08:28:39 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -51,6 +51,9 @@
 #include "gcr_funcs.H"
 
 using namespace fapi;
+	// Bus Status State
+	typedef enum {  NOT_RUNNING, SELECTED,  RUNNING,   SUCCESSFULL  ,
+        FAILED} bus_status;
 
 class edi_training {
 public:
@@ -58,9 +61,7 @@ public:
 	// Training enums for Wire test , Deskew , Eye Opt ,Repair , Functional   ---
 	typedef   enum {  WIRE_TEST ,  DESKEW ,  EYE_OPT ,  REPAIR , FUNCTIONAL
                                            , TRAINING_TYPES} training_function;
-	// Bus Status State
-	typedef enum {  NOT_RUNNING, SELECTED,  RUNNING,   SUCCESSFULL  ,
-        FAILED} bus_status;
+
     // Selection
 	bus_status    wire_test_selected;
 	bus_status    desckew_selected;
@@ -85,19 +86,19 @@ public:
 	bool		          rx_wderf_failed[6];    // Summary 5 bit failed
 
 	// Constructor Initializes default states for status variables
-    edi_training( )
+    edi_training( bus_status wire_test=SELECTED,bus_status deskew=SELECTED,bus_status eye_opt=SELECTED,bus_status repair=SELECTED,bus_status functional=SELECTED)
     {
-        wire_test_selected     =       SELECTED;
-        desckew_selected       =       SELECTED;
-        eye_opt_selected       =       SELECTED;
-        repair_selected        =       SELECTED;
-        functional_selected    =       SELECTED;
-
-        wire_test_status        =     SELECTED;
-        desckew_status          =     SELECTED;
-        eye_opt_status          =     SELECTED;
-        repair_status           =     SELECTED;
-        functional_status       =     SELECTED;
+        wire_test_selected     =       wire_test;
+        desckew_selected       =       deskew;
+        eye_opt_selected       =       eye_opt;
+        repair_selected        =       repair;
+        functional_selected    =       functional;
+
+        wire_test_status        =     wire_test;
+        desckew_status          =     deskew;
+        eye_opt_status          =     eye_opt;
+        repair_status           =     repair;
+        functional_status       =     functional;
         
         for(int i=0;i<6;++i)
         {
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
index 222a4b818..4f3a27b31 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/bus_training/io_run_training.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/io_run_training.C $             */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: io_run_training.C,v 1.25 2012/12/04 08:29:17 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -57,6 +57,9 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
      uint32_t master_group=0;
      uint32_t slave_group=0;
      edi_training init;
+     // Workaround - HW 220654 -- Need to split WDERF into WDE + RF
+     edi_training init1(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run WDE first
+     edi_training init2( NOT_RUNNING, NOT_RUNNING, NOT_RUNNING,SELECTED,SELECTED); // Run RF next
      bool is_master=false;
      // This is a DMI/MC bus 
      if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&& (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){
@@ -65,7 +68,9 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
           slave_interface=CEN_DMI; // Centaur scom base
           master_group=3; // Design requires us to do this as per scom map and layout
           slave_group=0;
-          rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+          // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem
+          rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+          rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
      }
      //This is an X Bus
      else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT  )&& (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT )){
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H
index adc8e83f1..0ff1e9419 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.H
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.H
@@ -1,26 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/bus_training/io_run_training.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/bus_training/io_run_training.H $             */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: io_run_training.H,v 1.8 2012/12/04 08:29:20 varkeykv Exp $

 #ifndef IO_RUN_TRAINING_H_

 #define IO_RUN_TRAINING_H_

 

diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
new file mode 100644
index 000000000..b5b1693ba
--- /dev/null
+++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
@@ -0,0 +1,42 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/centaur_ec_attributes.xml $                  -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<attributes>
+<!-- ********************************************************************* -->
+  <attribute>
+    <id>ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+      Returns true if the chip needs to fix the fir_mask register in the DDRPHY.  This is for HW217419.
+	True if: Centaur EC 10
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x10</value>
+          <test>EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+</attributes>
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
index a08062b94..47e3e9d92 100644
--- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml
+++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/dimm_spd_attributes.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dimm_spd_attributes.xml $                    -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- XML file specifying DIMM SPD attributes used by HW Procedures. -->
 <attributes>
 
@@ -224,7 +224,7 @@
         CL_7  = 0x00000008,
         CL_6  = 0x00000004,
         CL_5  = 0x00000002,
-        CL_4  = 0x00000001,
+        CL_4  = 0x00000001
     </enum>
     <platInit/>
 </attribute>
@@ -387,6 +387,41 @@
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_SDRAM_DEVICE_TYPE</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type.
+        Located in DDR3 SPD byte 33, bit 7.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>STANDARD_MONOLITHIC = 0x00, NON_STANDARD = 0x80</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type Signal Loading for stacked DRAMs.
+        Located in DDR3 SPD byte 33, bits 1-0.
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NOT_SPECIFIED = 0x00, MULTI_LOAD_STACK = 0x01, SINGLE_LOAD_STACK = 0x02</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
+    <id>ATTR_SPD_SDRAM_DIE_COUNT</id> 
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        SDRAM Device Type Die Count.
+        Located in DDR3 SPD byte 33, bits 6-4.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_FINE_OFFSET_TCKMIN</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
@@ -443,6 +478,17 @@
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Number of Registers used on RDIMM.
+        Located in DDR3 SPD byte 63 bits 1-0.
+    </description> 
+    <valueType>uint8</valueType>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_MODULE_SPECIFIC_SECTION</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
index c917b54f3..77adaf7f0 100644
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
@@ -469,7 +469,6 @@ void*    call_proc_cen_framelock( void *io_pArgs )
             uint8_t l_memNum = l_mem_target->getAttr<ATTR_POSITION>();
 
             // fill out the args struct.
-            l_args.in_error_state       =   false;
             l_args.channel_init_timeout =   CHANNEL_INIT_TIMEOUT_NO_TIMEOUT;
             l_args.frtl_auto_not_manual =   true;
             l_args.frtl_manual_pu       =   0;
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index 29712d68a..85cdaf2d3 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -1,27 +1,27 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: proc_cen_framelock.C,v 1.7 2012/07/23 14:15:46 jmcgill Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+/// $Id: proc_cen_framelock.C,v 1.9 2012/12/03 22:25:37 baysah Exp $
+
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -40,16 +40,21 @@
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
-#include "p8_scom_addresses.H"
-#include "cen_scom_addresses.H"
 #include "proc_cen_framelock.H"
 
+
 extern "C"
 {
 
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
+
+// Declare Global Variables
+
+        int fl_fail   = 0;
+        int fl_pass   = 0;
+        int frtl_fail = 0;
+        int frtl_pass = 0;
+        int num_try   = 0;
+
 
 //------------------------------------------------------------------------------
 // function: utility subroutine to clear the Centaur MBI Status Register
@@ -57,12 +62,12 @@ extern "C"
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_stat_reg(
-    const fapi::Target& i_mem_target)
+    const fapi::Target& i_mem_target )
 {
     fapi::ReturnCode rc;
     ecmdDataBufferBase zero_data(64);
 
-    FAPI_DBG("proc_cen_framelock_clear_cen_mbi_stat_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_clear_cen_mbi_stat_reg: Start");
 
     rc = fapiPutScom(i_mem_target, MBI_STAT_0x0201080B, zero_data);
 
@@ -74,6 +79,7 @@ fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_stat_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to get the Centaur MBI Status Register
 // parameters: i_mem_target  => Centaur target
@@ -86,7 +92,7 @@ fapi::ReturnCode proc_cen_framelock_get_cen_mbi_stat_reg(
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_get_cen_mbi_stat_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_get_cen_mbi_stat_reg: Start");
 
     rc = fapiGetScom(i_mem_target, MBI_STAT_0x0201080B, o_data);
 
@@ -98,6 +104,7 @@ fapi::ReturnCode proc_cen_framelock_get_cen_mbi_stat_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to clear the Centaur MBI FIR Register
 // parameters: i_mem_target  => Centaur target
@@ -109,7 +116,7 @@ fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_fir_reg(
     fapi::ReturnCode rc;
     ecmdDataBufferBase zero_data(64);
 
-    FAPI_DBG("proc_cen_framelock_clear_cen_mbi_fir_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_clear_cen_mbi_fir_reg: Start");
 
     rc = fapiPutScom(i_mem_target, MBI_FIR_0x02010800, zero_data);
 
@@ -121,6 +128,7 @@ fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_fir_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to get the Centaur MBI FIR Register
 // parameters: i_mem_target  => Centaur target
@@ -133,7 +141,7 @@ fapi::ReturnCode proc_cen_framelock_get_cen_mbi_fir_reg(
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_get_cen_mbi_fir_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_get_cen_mbi_fir_reg: Start");
 
     rc = fapiGetScom(i_mem_target, MBI_FIR_0x02010800, o_data);
     if (rc)
@@ -144,6 +152,7 @@ fapi::ReturnCode proc_cen_framelock_get_cen_mbi_fir_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to clear the P8 MCI Status Register
 // parameters: i_pu_target  => P8 MCS chip unit target
@@ -151,24 +160,24 @@ fapi::ReturnCode proc_cen_framelock_get_cen_mbi_fir_reg(
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_cen_framelock_clear_pu_mci_stat_reg(
-    const fapi::Target& i_pu_target,
-    const proc_cen_framelock_args& i_args)
+    const fapi::Target& i_pu_target)
 {
     fapi::ReturnCode rc;
     ecmdDataBufferBase zero_data(64);
 
-    FAPI_DBG("proc_cen_framelock_clear_pu_mci_stat_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_clear_pu_mci_stat_reg: Start");
 
     rc = fapiPutScom(i_pu_target, MCS_MCISTAT_0x0201184B, zero_data);
 
     if (rc)
     {
-        FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error (MCI_MCISTAT_0x0201184B)");
+        FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error (MCS_MCISTAT_0x0201184B)");
     }
 
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to get the P8 MCI Status Register
 // parameters: i_pu_target  => P8 MCS chip unit target
@@ -178,12 +187,11 @@ fapi::ReturnCode proc_cen_framelock_clear_pu_mci_stat_reg(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg(
     const fapi::Target& i_pu_target,
-    const proc_cen_framelock_args& i_args,
     ecmdDataBufferBase& o_data)
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_get_pu_mci_stat_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_get_pu_mci_stat_reg: Start");
 
     rc = fapiGetScom(i_pu_target, MCS_MCISTAT_0x0201184B, o_data);
 
@@ -194,6 +202,7 @@ fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to clear the P8 MCI FIR Register
 // parameters: i_pu_target  => P8 MCS chip unit target
@@ -201,13 +210,12 @@ fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg(
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg(
-    const fapi::Target& i_pu_target,
-    const proc_cen_framelock_args& i_args)
+    const fapi::Target& i_pu_target)
 {
     fapi::ReturnCode rc;
     ecmdDataBufferBase zero_data(64);
 
-    FAPI_DBG("proc_cen_framelock_clear_pu_mci_fir_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_clear_pu_mci_fir_reg: Start");
 
     rc = fapiPutScom(i_pu_target, MCS_MCIFIR_0x02011840, zero_data);
 
@@ -219,6 +227,7 @@ fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to get the P8 MCI FIR Register
 // parameters: i_pu_target  => P8 MCS chip unit target
@@ -228,12 +237,11 @@ fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg(
 //------------------------------------------------------------------------------
 fapi::ReturnCode proc_cen_framelock_get_pu_mci_fir_reg(
     const fapi::Target& i_pu_target,
-    const proc_cen_framelock_args& i_args,
     ecmdDataBufferBase& o_data)
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_get_pu_mci_fir_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_get_pu_mci_fir_reg: Start");
 
     rc = fapiGetScom(i_pu_target, MCS_MCIFIR_0x02011840, o_data);
 
@@ -245,6 +253,7 @@ fapi::ReturnCode proc_cen_framelock_get_pu_mci_fir_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to set the Centaur MBI Config Register
 // parameters: i_mem_target => Centaur target
@@ -259,7 +268,7 @@ fapi::ReturnCode proc_cen_framelock_set_cen_mbi_cfg_reg(
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_set_cen_mbi_cfg_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_cfg_reg: Start");
     rc = fapiPutScomUnderMask(i_mem_target, MBI_CFG_0x0201080A, i_data, i_mask);
 
     if (rc)
@@ -270,6 +279,7 @@ fapi::ReturnCode proc_cen_framelock_set_cen_mbi_cfg_reg(
     return rc;
 }
 
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to set the P8 MCI Config Register
 // parameters: i_pu_target => P8 MCS chip unit target
@@ -281,12 +291,11 @@ fapi::ReturnCode proc_cen_framelock_set_cen_mbi_cfg_reg(
 fapi::ReturnCode proc_cen_framelock_set_pu_mci_cfg_reg(
     const fapi::Target& i_pu_target,
     ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask,
-    const proc_cen_framelock_args& i_args)
+    ecmdDataBufferBase& i_mask)
 {
     fapi::ReturnCode rc;
 
-    FAPI_DBG("proc_cen_framelock_set_pu_mci_cfg_reg: Start");
+    //FAPI_DBG("proc_cen_framelock_set_pu_mci_cfg_reg: Start");
 
     rc = fapiPutScomUnderMask(i_pu_target, MCS_MCICFG_0x0201184A, i_data, i_mask);
 
@@ -298,68 +307,559 @@ fapi::ReturnCode proc_cen_framelock_set_pu_mci_cfg_reg(
     return rc;
 }
 
+
+
 //------------------------------------------------------------------------------
-// function: utility subroutine to clear the P8 and Centaur Status/FIR Registers
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur target
+// function: utility subroutine to set the Centaur MBI FIR Mask Register
+// parameters: i_mem_target => Centaur target
+//             i_data       => Input data
+//             i_mask       => Input mask
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firmask_reg(
+    const fapi::Target& i_mem_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firmsk_reg: Start");
+    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRMASK_0x02010803, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firmask_reg: fapiPutScomUnderMask error (MBI_FIRMASK_0x02010803)");
+    }
+
+    return rc;
+}
+
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the Centaur MBI FIR Action0 Register
+// parameters: i_mem_target => Centaur target
+//             i_data       => Input data
+//             i_mask       => Input mask
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firact0_reg(
+    const fapi::Target& i_mem_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firact0_reg: Start");
+    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRACT0_0x02010806, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firact0_reg: fapiPutScomUnderMask error (MBI_FIRACT0_0x02010806)");
+    }
+
+    return rc;
+}
+
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the Centaur MBI FIR Action1 Register
+// parameters: i_mem_target => Centaur target
+//             i_data       => Input data
+//             i_mask       => Input mask
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firact1_reg(
+    const fapi::Target& i_mem_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firact1_reg: Start");
+    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRACT1_0x02010807, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firact1_reg: fapiPutScomUnderMask error (MBI_FIRACT1_0x02010807)");
+    }
+
+    return rc;
+}
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the P8 MCI Config Register
+// parameters: i_pu_target => P8 MCS chip unit target
+//             i_data      => Input data
+//             i_mask      => Input mask
+//             i_args      => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_pu_mci_firmask_reg(
+    const fapi::Target& i_pu_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firmask_reg: Start");
+
+    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRMASK_0x02011843, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_pu_mci_firmask_reg: fapiPutScomUnderMask error (MCS_MCIFIRMASK_0x02011843)");
+    }
+
+    return rc;
+}
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the P8 MCI Config Register
+// parameters: i_pu_target => P8 MCS chip unit target
+//             i_data      => Input data
+//             i_mask      => Input mask
+//             i_args      => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_pu_mci_firact0_reg(
+    const fapi::Target& i_pu_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firact0_reg: Start");
+
+    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRACT0_0x02011846, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_pu_mci_firact0_reg: fapiPutScomUnderMask error (MCS_MCIFIRACT0_0x02011846)");
+    }
+
+    return rc;
+}
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the P8 MCI Config Register
+// parameters: i_pu_target => P8 MCS chip unit target
+//             i_data      => Input data
+//             i_mask      => Input mask
+//             i_args      => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if operation was successful, else error
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_set_pu_mci_firact1_reg(
+    const fapi::Target& i_pu_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firact1_reg: Start");
+
+    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRACT1_0x02011847, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_pu_mci_firact1_reg: fapiPutScomUnderMask error (MCS_MCIFIRACT1_0x02011847)");
+    }
+
+    return rc;
+}
+
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to set the P8 MCI Config Register
+// parameters: i_pu_target => P8 MCS chip unit target
+//             i_data      => Input data
+//             i_mask      => Input mask
 //             i_args      => proc_cen_framelock HWP argumemt structure
 // returns: FAPI_RC_SUCCESS if operation was successful, else error
 //------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_clear_stat_fir_regs(
+fapi::ReturnCode proc_cen_framelock_set_pu_mcs_mode4_reg(
+    const fapi::Target& i_pu_target,
+    ecmdDataBufferBase& i_data,
+    ecmdDataBufferBase& i_mask)
+{
+    fapi::ReturnCode rc;
+
+    //FAPI_DBG("proc_cen_framelock_set_pu_mcs_mode4_reg: Start");
+
+    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCSMODE4_0x0201181A, i_data, i_mask);
+
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_set_pu_mcs_mode4_reg: fapiPutScomUnderMask error (MCS_MCSMODE4_0x0201181A)");
+    }
+
+    return rc;
+}
+
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to initiate P8/Centaur framelock operation and
+//           poll for completion
+// parameters: i_pu_target  => P8 MCS chip unit target
+//             i_args       => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if framelock sequence completes successfully,
+//          RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR
+//              if MCI FIR is set during framelock operation,
+//          RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR
+//              if MCI indicates framelock operation failure
+//          RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR
+//              if MCI does not post pass/fail indication after framelock
+//              operation is started,
+//          else FAPI getscom/putscom return code for failing SCOM operation
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_run_framelock(
     const fapi::Target& i_pu_target,
     const fapi::Target& i_mem_target,
     const proc_cen_framelock_args& i_args)
 {
+    // data buffers
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase mask(64);
+    ecmdDataBufferBase mbi_stat(64);
+    ecmdDataBufferBase mbi_fir(64);
+    ecmdDataBufferBase mci_stat(64);
+    ecmdDataBufferBase mci_fir(64);
+    ecmdDataBufferBase errstate(8);
+
+    // return codes
     fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
 
-    FAPI_DBG("proc_cen_framelock_clear_stat_fir_regs: Start");
 
-    do
+    FAPI_DBG("proc_cen_framelock_run_framelock: Starting framelock sequence ...");
+
+    // Clear P8 MCI FIR registers
+    rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
+    if (rc)
     {
-        // Clear Centaur MBI Status Register
-        rc = proc_cen_framelock_clear_cen_mbi_stat_reg(i_mem_target);
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI FIR regs");
+       // break;
+    }
 
+
+    // Clear P8 Status registers
+    rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI Status regs");
+       // break;
+    }
+
+
+    // set channel init timeout value in P8 MCI Configuration Register
+    // FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= mask.flushTo0();
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t) (i_args.channel_init_timeout &
+                    MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to set init timeout",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to set init timeout");
+      //  break;
+    }
+
+    // start framelock
+    // FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to initiate framelock ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to initiate framelock",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to initiate framelock");
+       // break;
+    }
+
+    // poll until framelock operation is finished, a timeout is deemed to
+    // have occurred, or an error is detected
+    uint8_t polls = 0;
+
+    while ( (fl_fail == 0) && (fl_pass == 0) )
+    {
+
+        // Read P8 MCI Status Register
+        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_cen_mbi_stat_reg");
+            FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI Status Register");
             break;
         }
 
-        // Clear Centaur MBI FIR Register
-        rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target);
+        // Read P8 MCI FIR Register
+        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
 
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_cen_mbi_fir_reg");
+            FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI FIR Register");
             break;
         }
 
-        // Clear P8 MCI Status Register
-        rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target, i_args);
 
-        if (rc)
+
+        // Fail if P8 MCI Frame Lock FAIL or MCI FIR bits are set
+        if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT)  ||
+            mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
         {
-            FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_pu_mci_stat_reg");
+            fl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI STAT OR FIR errors set");
+            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
             break;
         }
 
-        // Clear P8 MCI FIR Register
-        rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target, i_args);
 
-        if (rc)
+
+        // Success if P8 PASS bits set
+        if ((mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT)) )
+        {
+            fl_pass = 1;
+            FAPI_DBG("proc_cen_framelock_run_framelock: Framelock completed successfully!");
+            break;
+        }
+
+
+        if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
         {
-            FAPI_ERR("proc_cen_framelock_clear_stat_fir_regs: Error from proc_cen_framelock_clear_pu_mci_fir_reg");
+            // Loop count has expired, timeout
             break;
         }
+        else
+        {
+            // polls left, keep waiting for pass/fail bits to come on
+            polls++;
+            FAPI_DBG("proc_cen_framelock_run_framelock: Loop %d of %d ...",
+                     polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
+        }
+    }
+
+    return rc;
+}
+
+
+
+//  proc_cen_framelock_run_framelock  ENDS
+
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
+//           latency) determination and check for completion
+// parameters: i_pu_target  => P8 MCS chip unit target
+//             i_mem_target => Centaur chip target
+//             i_args       => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR
+//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR
+//              if MCI/MBI FIR is set during FRTL operation,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR
+//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR
+//              if MCI/MBI indicates FRTL operation failure,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR
+//              if MCI/MBI does not post pass/fail indication after FRTL
+//              operation is started,
+//          else FAPI getscom/putscom return code for failing SCOM operation
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_run_frtl(
+    const fapi::Target& i_pu_target,
+    const proc_cen_framelock_args& i_args)
+{
+    // data buffers for putscom/getscom calls
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase mask(64);
+    ecmdDataBufferBase mci_stat(64);
+    ecmdDataBufferBase mci_fir(64);
+
+    // return codes
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+
+    // mark function entry
+    FAPI_DBG("proc_cen_framelock_run_frtl: Starting FRTL sequence ...");
+
+
+
+
+
+     // start FRTL
+     // FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to initiate FRTL ...");
+     rc_ecmd |= data.flushTo0();
+     rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT);
+     rc_ecmd |= data.copy(mask);
+     if (rc_ecmd)
+     {
+         FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to initiate FRTL",
+                  rc_ecmd);
+         rc.setEcmdError(rc_ecmd);
+        // break;
+     }
+
+     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+
+     if (rc)
+     {
+         FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
+        // break;
+     }
+
+     // Poll until FRTL operation is finished, a timeout is deemed to
+     // have occurred, or an error is detected
+     uint8_t polls = 0;
+
+     while ( (frtl_fail == 0) && (frtl_pass == 0) )
+     {
+
+         // Read P8 MCI Status Register
+         rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
+         if (rc)
+         {
+             FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI Status Register");
+             break;
+         }
+
+         // Read P8 MCI FIR Register
+         rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
+         if (rc)
+         {
+             FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register");
+             break;
+         }
+
+
+         // Fail if P8 MCI Frame Lock FAIL or MCI FIR bits are set
+         if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
+             mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+             mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT) ||
+             mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
+         {
+             frtl_fail = 1;
+             FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail. P8 MCI STAT OR FIR errors set");
+             // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
+             break;
+         }
+
+
+         // Success if P8 FRTL and InterLock PASS bits are set
+         if ((mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)) &&
+             (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)))
+         {
+             frtl_pass = 1;
+             FAPI_DBG("proc_cen_framelock_run_frtl: FRTL (auto) completed successfully!");
+             break;
+         }
+
+         if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
+         {
+             // Loop count has expired, timeout
+             if (mci_stat.isBitClear(MCI_STAT_FRTL_PASS_BIT))
+             {
+                 FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!");
+             }
+             if (mci_stat.isBitClear(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT))
+             {
+                 FAPI_ERR("proc_cen_framelock_run_frtl: InterLock timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!");
+             }
+            // FAPI_SET_HWP_ERROR(rc,
+            //                    RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+             break;
+         }
+         else
+         {
+             // polls left, keep waiting for pass/fail bits to come on
+             polls++;
+             FAPI_DBG("proc_cen_framelock_run_frtl: Loop %d of %d ...\n",
+                      polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
+         }
+     }
 
-    } while(0);
 
     return rc;
 }
 
+//  proc_cen_framelock_run_frtl  ENDS
+
+
+
+
+
+
+
+
+
+
+
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to initiate P8/Centaur framelock operation and
-//           poll for completion
+//           poll for completion after the first operation fails.
 // parameters: i_pu_target  => P8 MCS chip unit target
 //             i_mem_target => Centaur chip target
 //             i_args       => proc_cen_framelock HWP argumemt structure
@@ -375,7 +875,7 @@ fapi::ReturnCode proc_cen_framelock_clear_stat_fir_regs(
 //              operation is started,
 //          else FAPI getscom/putscom return code for failing SCOM operation
 //------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_framelock(
+fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
     const fapi::Target& i_pu_target,
     const fapi::Target& i_mem_target,
     const proc_cen_framelock_args& i_args)
@@ -392,209 +892,481 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
     fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
 
-    FAPI_DBG("proc_cen_framelock_run_framelock: Starting framelock sequence ...");
 
-    do
+    // Clear global flags to start procedure in error state
+    fl_fail = 0;
+    fl_pass = 0;
+    frtl_fail = 0;
+    frtl_pass = 0;
+
+
+    FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Starting framelock Error State sequence ...");
+
+
+    // Clear MBI Channel Fail Configuration Bit
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
+    rc_ecmd |= data.copy(mask);
+    rc_ecmd |= data.clearBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MBI force channel fail bit",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+      //  break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,  mask);
+    if (rc)
     {
-        // Clear Centaur/P8 Status/FIR registers
-        rc = proc_cen_framelock_clear_stat_fir_regs(i_pu_target, i_mem_target,
-                                                    i_args);
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to clear the force channel fail bit");
+       // break;
+    }
+
+
+    //Clear MCI Force Channel Fail Configuration Bit
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
+    rc_ecmd |= data.copy(mask);
+    rc_ecmd |= data.clearBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MCI force channel fail bit",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to clear the force channel fail bit");
+      //  break;
+    }
+
+
+    // Clear Centaur MBI FIR registers
+    rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI FIR regs");
+       // break;
+    }
+
+
+    // Clear Centaur MBI Status registers
+    rc = proc_cen_framelock_clear_cen_mbi_stat_reg(i_mem_target);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI Status regs");
+       // break;
+    }
+
+
+    // Clear P8 MCI FIR registers
+    rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI FIR regs");
+       // break;
+    }
+
+
+    // Clear P8 Status registers
+    rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI Status regs");
+       // break;
+    }
+
+
+
+    // set channel init timeout value in P8 MCI Configuration Register
+    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= mask.flushTo0();
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t) (i_args.channel_init_timeout &
+                    MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to set init timeout",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to set init timeout");
+      //  break;
+    }
+
+
+    // start framelock on Centaur MBI
+    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing Centaur MBI Configuration Register to force framelock ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRAMELOCK_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to force framelock",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+      //  break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to force framelock");
+      //  break;
+    }
+
+
+    // start framelock on P8 MCI
+    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing P8 MCI Configuration Register to initiate framelock ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to initiate framelock",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to initiate framelock");
+      //  break;
+    }
+
+    // poll until framelock operation is finished, a timeout is deemed to
+    // have occurred, or an error is detected
+    uint8_t polls = 0;
+
+    while ( (fl_fail == 0) && (fl_pass == 0) )
+    {
+
+        // Read CEN MBI Status Register
+        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing Centaur/P8 Status/FIR regs");
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI status Register");
             break;
         }
 
-        // If error state is set, force framelock bit in Centaur MBI
-        // Configuration Register
-        if (i_args.in_error_state)
+        // Read CEN MBI FIR Register
+        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
+        if (rc)
         {
-            FAPI_DBG("proc_cen_framelock_run_framelock: Writing Centaur MBI Configuration Register to force framelock ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRAMELOCK_BIT);
-            rc_ecmd |= data.copy(mask);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to force framelock",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,
-                                                        mask);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error writing Centaur MBI Configuration Register to force framelock");
-                break;
-            }
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI FIR Register");
+            break;
         }
 
-        // set channel init timeout value in P8 MCI Configuration Register
-        FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ...");
-        rc_ecmd |= data.flushTo0();
-        rc_ecmd |= mask.flushTo0();
-        rc_ecmd |= data.insertFromRight(
-            (uint32_t) (i_args.channel_init_timeout &
-                        MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-            MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-            (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-             MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-        rc_ecmd |= mask.setBit(
-            MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-            (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-             MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-        if (rc_ecmd)
+
+
+
+        // Read P8 MCI Status Register
+        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
+        if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to set init timeout",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI Status Register");
             break;
         }
 
-        rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                   i_args);
+        // Read P8 MCI FIR Register
+        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to set init timeout");
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI FIR Register");
             break;
         }
 
-        // start framelock
-        FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to initiate framelock ...");
-        rc_ecmd |= data.flushTo0();
-        rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT);
-        rc_ecmd |= data.copy(mask);
-        if (rc_ecmd)
+
+
+
+        // Fail if Centaur MBI Frame Lock FAIL or MBI FIR bits are set
+        if (mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_FAIL_BIT)  ||
+            mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT)               )
+
         {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to initiate framelock",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
+            fl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. Centaur MBI STAT OR FIR errors set");
+            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR);
             break;
         }
 
-        rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                   i_args);
+
+
+        // Fail if P8 MCI Frame Lock FAIL or MCI FIR bits are set
+        if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT)  ||
+            mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
+        {
+            fl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. P8 MCI STAT OR FIR errors set");
+            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
+            break;
+        }
+
+
+
+        // Success if P8 PASS bits set
+        if ( (mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_PASS_BIT)) && (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT)) && (fl_fail == 0) )
+        {
+            fl_pass = 1;
+            FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Framelock completed successfully!");
+            break;
+        }
+
+        if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
+        {
+            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
+            break;
+        }
+        else
+        {
+            // polls left, keep waiting for pass/fail bits to come on
+            polls++;
+            FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Loop %d of %d ...",
+                     polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
+        }
+    }
+
+    return rc;
+}
+
+
+//  proc_cen_framelock_run_errstate_framelock  ENDS
+
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
+//           latency) determination and check for completion
+// parameters: i_pu_target  => P8 MCS chip unit target
+//             i_mem_target => Centaur chip target
+//             i_args       => proc_cen_framelock HWP argumemt structure
+// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR
+//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR
+//              if MCI/MBI FIR is set during FRTL operation,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR
+//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR
+//              if MCI/MBI indicates FRTL operation failure,
+//          RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR
+//              if MCI/MBI does not post pass/fail indication after FRTL
+//              operation is started,
+//          else FAPI getscom/putscom return code for failing SCOM operation
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
+    const fapi::Target& i_pu_target,
+    const fapi::Target& i_mem_target,
+    const proc_cen_framelock_args& i_args)
+{
+    // data buffers for putscom/getscom calls
+    ecmdDataBufferBase data(64);
+    ecmdDataBufferBase mask(64);
+    ecmdDataBufferBase mbi_stat(64);
+    ecmdDataBufferBase mbi_fir(64);
+    ecmdDataBufferBase mci_stat(64);
+    ecmdDataBufferBase mci_fir(64);
+
+    // return codes
+    fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+
+    // mark function entry
+    FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Starting FRTL Error State sequence ...");
+
+
+
+
+    // if error state is set, force FRTL bit in Centaur MBI
+    //FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Writing Centaur MBI Configuration register to force FRTL ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRTL_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to force FRTL",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing Centaur MBI Configuration Register to force FRTL");
+       // break;
+    }
+
+
+    // start FRTL
+    //FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Writing P8 MCI Configuration Register to initiate FRTL ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to initiate FRTL",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
+       // break;
+    }
+
+    // Poll until FRTL operation is finished, a timeout is deemed to
+    // have occurred, or an error is detected
+    uint8_t polls = 0;
+
+    while ( (frtl_fail == 0) && (frtl_pass == 0) && (fl_fail == 0) )
+    {
+        // Read Centaur MBI Status Register
+        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to initiate framelock");
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI Status Register");
             break;
         }
 
-        // poll until framelock operation is finished, a timeout is deemed to
-        // have occurred, or an error is detected
-        uint8_t polls = 0;
+        // Read Centaur MBI FIR Register
+        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
+        if (rc)
+        {
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI FIR Register");
+            break;
+        }
 
-        while (1)
+        // Read P8 MCI Status Register
+        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
+        if (rc)
         {
-            // Read Centaur MBI Status Register
-            rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target,
-                                                         mbi_stat);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error reading Centaur MBI Status Register");
-                break;
-            }
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI Status Register");
+            break;
+        }
 
-            // Read Centaur MBI FIR Register
-            rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
+        // Read P8 MCI FIR Register
+        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
+        if (rc)
+        {
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI FIR Register");
+            break;
+        }
 
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error reading Centaur MBI FIR Register");
-                break;
-            }
 
-            // Read P8 MCI Status Register
-            rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, i_args,
-                                                        mci_stat);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI Status Register");
-                break;
-            }
 
-            // Read P8 MCI FIR Register
-            rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args,
-                                                       mci_fir);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI FIR Register");
-                break;
-            }
+        // Fail if Centaur MBI FRTL FAIL or MBI FIR bits are set
+        if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT)  ||
+            mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT)               )
 
-            // Fail if any Centaur FIR bits are set
-            if (mbi_fir.getDoubleWord(0))
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. Centaur MBI FIR bit on (0x%llx)",
-                         mbi_fir.getDoubleWord(0));
-                ecmdDataBufferBase & FIR_REG = mbi_fir;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR);
-                break;
-            }
+        {
+            frtl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. Centaur MBI STAT OR FIR errors set");
+            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR);
+            break;
+        }
 
-            // Fail if any P8 FIR bits are set
-            if (mci_fir.getDoubleWord(0))
-            {
 
-                FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI FIR bit on (0x%llx)",
-                         mci_fir.getDoubleWord(0));
-                ecmdDataBufferBase & FIR_REG = mci_fir;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR);
-                break;
-            }
+        // Fail if P8 MCI FRTL FAIL or MCI FIR bits are set
+        if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
+            mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
+        {
+            frtl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. P8 MCI STAT OR FIR errors set");
+           // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
+           break;
+        }
 
-            // Fail if Centaur FAIL bit set
-            if (mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_FAIL_BIT))
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. Centaur MBI_STAT_FRAMELOCK_FAIL_BIT set");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR);
-                break;
-            }
 
-            // Fail if P8 FAIL bit set
-            if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT))
-            {
-                FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI_STAT_FRAMELOCK_FAIL_BIT set");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
-                break;
-            }
+        // Success if Centaur and P8 PASS bits set
+        if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) &&
+            (mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
+            (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
+            (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)) &&
+            (frtl_fail == 0) &&
+            (fl_fail == 0)
+           )
 
-            // Success if Centaur and P8 PASS bits set
-            if ((mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_PASS_BIT)) &&
-                (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT)))
-            {
-                FAPI_DBG("proc_cen_framelock_run_framelock: Framelock completed successfully!");
-                break;
-            }
+        {
+            frtl_pass = 1;
+            FAPI_DBG("proc_cen_framelock_run_errstate_frtl: FRTL (auto) completed successfully!");
+            break;
+        }
 
-            if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
-            {
-                // Loop count has expired, timeout
-                if (mbi_stat.isBitClear(MBI_STAT_FRAMELOCK_PASS_BIT))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_framelock: Framelock timeout waiting on pass/fail indication in Centaur MBI Status Register!");
-                }
-                if (mci_stat.isBitClear(MCI_STAT_FRAMELOCK_PASS_BIT))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_framelock: Framelock timeout waiting on pass/fail indication in P8 MCI Status Register!");
-                }
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
-                break;
-            }
-            else
-            {
-                // polls left, keep waiting for pass/fail bits to come on
-                polls++;
-                FAPI_DBG("proc_cen_framelock_run_framelock: Loop %d of %d ...",
-                         polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
-            }
+        if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
+        {
+            // Loop count has expired, timeout
+            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            break;
         }
-    } while (0);
+        else
+        {
+            // polls left, keep waiting for pass/fail bits to come on
+            polls++;
+            FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Loop %d of %d ...\n",
+                     polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
+        }
+
+    }   // End While
+
 
     return rc;
 }
 
+
+//  proc_cen_framelock_run_errstate_frtl  ENDS
+
+
+
+
+
+
+
 //------------------------------------------------------------------------------
 // function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
 //           latency) determination and check for completion
@@ -613,7 +1385,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
 //              operation is started,
 //          else FAPI getscom/putscom return code for failing SCOM operation
 //------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_frtl(
+fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
     const fapi::Target& i_pu_target,
     const fapi::Target& i_mem_target,
     const proc_cen_framelock_args& i_args)
@@ -631,502 +1403,793 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
     uint32_t rc_ecmd = 0;
 
     // mark function entry
-    FAPI_DBG("proc_cen_framelock_run_frtl: Starting FRTL sequence ...");
+    FAPI_DBG("proc_cen_framelock_run_manual_frtl: Starting FRTL manual sequence ...");
+
+
+
+
+    // Manual mode
+
+    // Disable auto FRTL mode & channel init timeout in Centaur MBI
+    // Configuration Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to disable auto FRTL mode & channel init timeout ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MBI_CFG_AUTO_FRTL_DISABLE_BIT);
+    rc_ecmd |= data.copy(mask);
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t) (CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
+                    MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
+        MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable Centaur auto FRTL mode",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+      //  break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to disable auto FRTL mode");
+       // break;
+    }
+
+    // write specified FRTL value into Centaur MBI Configuration
+    // Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to set manual FRTL value ...");
+    if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Out of range value %d presented for Centaur manual FRTL argument value!",
+                 i_args.frtl_manual_mem);
+        const proc_cen_framelock_args & ARGS = i_args;
+        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
+       // break;
+    }
+
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= mask.flushTo0();
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t) (i_args.frtl_manual_mem &
+                    MBI_CFG_MANUAL_FRTL_FIELD_MASK),
+        MBI_CFG_MANUAL_FRTL_START_BIT,
+        (MBI_CFG_MANUAL_FRTL_END_BIT -
+         MBI_CFG_MANUAL_FRTL_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MBI_CFG_MANUAL_FRTL_START_BIT,
+        (MBI_CFG_MANUAL_FRTL_END_BIT -
+         MBI_CFG_MANUAL_FRTL_START_BIT + 1));
+
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL value",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL value");
+       // break;
+    }
+
+
+    // disable auto FRTL mode & channel init timeout in P8 MCI
+    // Configuration Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to disable auto FRTL mode & channel init timeout ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_AUTO_FRTL_DISABLE_BIT);
+    rc_ecmd |= data.copy(mask);
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t)(CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
+                   MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
+        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
+         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable P8 auto FRTL mode",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+      //  break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to disable auto FRTL mode");
+       // break;
+    }
+
+    // write specified FRTL value into P8 MCI Configuration Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to set manual FRTL value ...");
+    if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Out of range value 0x%x presented for P8 manual FRTL argument value!",
+                 i_args.frtl_manual_pu);
+        const proc_cen_framelock_args & ARGS = i_args;
+        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
+       // break;
+    }
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= mask.flushTo0();
+    rc_ecmd |= data.insertFromRight(
+        (uint32_t)(i_args.frtl_manual_pu &
+                   MCI_CFG_MANUAL_FRTL_FIELD_MASK),
+        MCI_CFG_MANUAL_FRTL_START_BIT,
+        (MCI_CFG_MANUAL_FRTL_END_BIT -
+         MCI_CFG_MANUAL_FRTL_START_BIT + 1));
+    rc_ecmd |= mask.setBit(
+        MCI_CFG_MANUAL_FRTL_START_BIT,
+        (MCI_CFG_MANUAL_FRTL_END_BIT -
+         MCI_CFG_MANUAL_FRTL_START_BIT + 1));
+
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set P8 manual FRTL value",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL value");
+       // break;
+    }
+
 
-    do
+    // write FRTL manual done bit into Centaur MBI Configuration
+    // Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to set manual FRTL done bit ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MBI_CFG_MANUAL_FRTL_DONE_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR( "proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL done",
+                  rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
+    if (rc)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL done");
+       // break;
+    }
+
+    // write FRTL manual done bit into P8 MCI Configuration Register
+    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to set manual FRTL done bit ...");
+    rc_ecmd |= data.flushTo0();
+    rc_ecmd |= data.setBit(MCI_CFG_MANUAL_FRTL_DONE_BIT);
+    rc_ecmd |= data.copy(mask);
+    if (rc_ecmd)
+    {
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to write P8 manual FRTL done",
+                 rc_ecmd);
+        rc.setEcmdError(rc_ecmd);
+       // break;
+    }
+
+    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
+    if (rc)
     {
-        // Clear Centaur/P8 Status/FIR registers
-        rc = proc_cen_framelock_clear_stat_fir_regs(i_pu_target, i_mem_target,
-                                                    i_args);
+        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL done");
+       // break;
+    }
+
+
+
+
+    // Poll until FRTL operation is finished, a timeout is deemed to
+    // have occurred, or an error is detected
+    uint8_t polls = 0;
+
+    while ( (frtl_fail == 0) && (frtl_pass == 0) )
+    {
+        // Read Centaur MBI Status Register
+        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
         if (rc)
         {
-            FAPI_ERR("proc_cen_framelock_run_frtl: Error clearing Centaur/P8 Status/FIR regs");
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI Status Register");
             break;
         }
 
-        if (i_args.frtl_auto_not_manual)
+        // Read Centaur MBI FIR Register
+        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
+        if (rc)
         {
-            // Auto mode
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI FIR Register");
+            break;
+        }
 
-            // if error state is set, force FRTL bit in Centaur MBI
-            // Configuration Register
-            if (i_args.in_error_state)
-            {
-                FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to force FRTL ...");
-                rc_ecmd |= data.flushTo0();
-                rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRTL_BIT);
-                rc_ecmd |= data.copy(mask);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to force FRTL",
-                             rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
+        // Read P8 MCI Status Register
+        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
+        if (rc)
+        {
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI Status Register");
+            break;
+        }
 
-                rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,
-                                                            mask);
-                if (rc)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration Register to force FRTL");
-                    break;
-                }
-            }
+        // Read P8 MCI FIR Register
+        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
+        if (rc)
+        {
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI FIR Register");
+            break;
+        }
 
-            // set channel init timeout value in P8 MCI Configuration Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to set channel init timeout value ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= mask.flushTo0();
-            rc_ecmd |= data.insertFromRight(
-                (uint32_t) (i_args.channel_init_timeout &
-                            MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-                MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            rc_ecmd |= mask.setBit(
-                MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set init timeout",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
 
-            rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                       i_args);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set init timeout");
-                break;
-            }
 
-            // start FRTL
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to initiate FRTL ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT);
-            rc_ecmd |= data.copy(mask);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to initiate FRTL",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
+        // Fail if Centaur MBI FRTL FAIL or MBI FIR bits are set
+        if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT)  ||
+            mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT)               )
 
-            rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                       i_args);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
-                break;
-            }
+        {
+            frtl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. Centaur MBI STAT OR FIR errors set");
+            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR);
+            break;
+        }
 
-            // Poll until FRTL operation is finished, a timeout is deemed to
-            // have occurred, or an error is detected
-            uint8_t polls = 0;
 
-            while (1)
-            {
-                // Read Centaur MBI Status Register
-                rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target,
-                                                             mbi_stat);
-                if (rc)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI Status Register");
-                    break;
-                }
+        // Fail if P8 MCI FRTL FAIL or MCI FIR bits are set
+        if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
+            mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
+            mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT) ||
+            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
+        {
+            frtl_fail = 1;
+            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. P8 MCI STAT OR FIR errors set");
+            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
+            break;
+        }
 
-                // Read Centaur MBI FIR Register
-                rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target,
-                                                            mbi_fir);
-                if (rc)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI FIR Register");
-                    break;
-                }
 
-                // Read P8 MCI Status Register
-                rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, i_args,
-                                                            mci_stat);
-                if (rc)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI Status Register");
-                    break;
-                }
+            // Success if Centaur and P8 PASS bits set
+        if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) &&
+            (mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
+            (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
+            (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)))
+        {
+            frtl_pass = 1;
+            FAPI_DBG("proc_cen_framelock_run_manual_frtl: FRTL (auto) completed successfully!");
+            break;
+        }
 
-                // Read P8 MCI FIR Register
-                rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args,
-                                                           mci_fir);
-                if (rc)
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register");
-                    break;
-                }
+        if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
+        {
+            // Loop count has expired, timeout
+            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
 
-                // Fail if any Centaur FIR bits are set
-                if (mbi_fir.getDoubleWord(0))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). Centaur MBI FIR bit on (0x%llx)",
-                             mbi_fir.getDoubleWord(0));
-                    ecmdDataBufferBase & FIR_REG = mbi_fir;
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FIR_ERR);
-                    break;
-                }
+            break;
+        }
+        else
+        {
+            // polls left, keep waiting for pass/fail bits to come on
+            polls++;
+            FAPI_DBG("proc_cen_framelock_run_manual_frtl: Loop %d of %d ...\n",
+                     polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
+        }
+    }
 
-                // Fail if any P8 FIR bits are set
-                if (mci_fir.getDoubleWord(0))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). P8 MCI FIR bit on (0x%llx)",
-                             mci_fir.getDoubleWord(0));
-                    ecmdDataBufferBase & FIR_REG = mci_fir;
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR);
-                    break;
-                }
+    return rc;
+}
 
-                // Fail if Centaur FAIL bit set
-                if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). Centaur MBI_STAT_FRTL_FAIL_BIT set");
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR);
-                    break;
-                }
 
-                // Fail if P8 FAIL bit set
-                if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT))
-                {
-                    FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (auto). P8 MCI_STAT_FRTL_FAIL_BIT set");
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
-                    break;
-                }
+//  proc_cen_framelock_run_manual_frtl  ENDS
+
+
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// The Main Hardware Procedure
+// ##################################################
+// The frame lock procedure initializes the Centaur DMI memory channel.  In the
+// event of errors, it will attempt to rerun the procedure.  There will be up to 3 attempts
+// at initialization before giving up.  This procedure assumes the DMI/EDI channel training
+// states completed successfully and that the DMI fence was lowered.
+//
+// When the procedure is first run, NO SCOM will be performed on Centaur.  All the scom accesses
+// are limited to Murano/Venice.  This allows for very fast initialization of the channels.  However,
+// if the initialization does encounter a fail event, the procedure will make a second (if necessary,
+// a third attempt) at intializing the channel.  The second and third attempts require scoms to both
+// P8 and Centaur chips.
+//
+//
+//------------------------------------------------------------------------------
+fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
+                                    const fapi::Target& i_mem_target,
+                                    const proc_cen_framelock_args& i_args)
+{
+
+ // data buffers for putscom/getscom calls
+    ecmdDataBufferBase mci_data(64);
+    ecmdDataBufferBase mbi_data(64);
+    ecmdDataBufferBase mci_mask(64);
+    ecmdDataBufferBase mbi_mask(64);
+
+
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmdRc = 0;
+
+    // mark HWP entry
+    FAPI_IMP("proc_cen_framelock: Entering ...");
+
+
+    while (  ! ( (num_try > 3) || ((fl_pass == 1) && (frtl_pass == 1) && (fl_fail == 0) && (frtl_fail == 0))  )    )
+
+    {
+
+
+      //  FAPI_DBG("Number Try: %d", num_try);
+      //  FAPI_DBG("Frame Lock Pass at Value End of Loop: %d", fl_pass);
+      //  FAPI_DBG("Frame Lock Fail at Value End of Loop: %d", fl_fail);
+      //  FAPI_DBG("FRTL Pass Value at End of Loop: %d", frtl_pass);
+      //  FAPI_DBG("FRTL Fail Value at End of Loop: %d", frtl_fail);
+
+
+        // validate arguments
+        if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK)
+        {
+            FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL mem argument value!",
+                     i_args.frtl_manual_mem);
+            const proc_cen_framelock_args & ARGS = i_args;
+            FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
+            break;
+        }
+
+        if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
+        {
+            FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL pu argument value!",
+                     i_args.frtl_manual_pu);
+            const proc_cen_framelock_args & ARGS = i_args;
+            FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
+            break;
+        }
 
-                // Success if Centaur and P8 PASS bits set
-                if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) &&
-                    (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)))
-                {
-                    FAPI_DBG("proc_cen_framelock_run_frtl: FRTL (auto) completed successfully!");
-                    break;
-                }
 
-                if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
+
+        // Start FL in non error state
+
+        if( (fl_pass == 0) && (fl_fail == 0) && (frtl_pass == 0) && (frtl_fail == 0) && (num_try == 0) )
+        {
+
+           // execute framelock
+           l_rc = proc_cen_framelock_run_framelock(i_pu_target, i_mem_target,
+                                                 i_args);
+           if (l_rc)
+           {
+               break;
+           }
+
+        }
+
+
+        // Start FRTL in non error state
+
+        if( (fl_pass == 1) && (fl_fail == 0) && (frtl_pass == 0) && (frtl_fail == 0) && (num_try == 0) )
+        {
+
+            if (i_args.frtl_auto_not_manual)
+            {
+                // Auto mode
+
+                // execute FRTL
+                l_rc = proc_cen_framelock_run_frtl(i_pu_target,
+                                                 i_args);
+                if (l_rc)
                 {
-                    // Loop count has expired, timeout
-                    if (mbi_stat.isBitClear(MBI_STAT_FRTL_PASS_BIT))
-                    {
-                        FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in Centaur MBI Status Register!");
-                    }
-                    if (mci_stat.isBitClear(MCI_STAT_FRTL_PASS_BIT))
-                    {
-                        FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!");
-                    }
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
                     break;
                 }
-                else
-                {
-                    // polls left, keep waiting for pass/fail bits to come on
-                    polls++;
-                    FAPI_DBG("proc_cen_framelock_run_frtl: Loop %d of %d ...\n",
-                             polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
-                }
+
             }
-        }
-        else
-        {
-            // Manual mode
-
-            // Disable auto FRTL mode & channel init timeout in Centaur MBI
-            // Configuration Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to disable auto FRTL mode & channel init timeout ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MBI_CFG_AUTO_FRTL_DISABLE_BIT);
-            rc_ecmd |= data.copy(mask);
-            rc_ecmd |= data.insertFromRight(
-                (uint32_t) (CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
-                            MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-                MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            rc_ecmd |= mask.setBit(
-                MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            if (rc_ecmd)
+            else
             {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to disable Centaur auto FRTL mode",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
 
-            rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,
-                                                        mask);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to disable auto FRTL mode");
-                break;
-            }
+               // Manual mode
+
+               l_rc = proc_cen_framelock_run_manual_frtl(i_pu_target, i_mem_target,
+                                                         i_args);
+               if (l_rc)
+               {
+                   break;
+               }
+
+            } // end else
+        }
+
 
-            // write specified FRTL value into Centaur MBI Configuration
-            // Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to set manual FRTL value ...");
-            if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Out of range value %d presented for Centaur manual FRTL argument value!",
-                         i_args.frtl_manual_mem);
-                const proc_cen_framelock_args & ARGS = i_args;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-                break;
-            }
 
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= mask.flushTo0();
-            rc_ecmd |= data.insertFromRight(
-                (uint32_t) (i_args.frtl_manual_mem &
-                            MBI_CFG_MANUAL_FRTL_FIELD_MASK),
-                MBI_CFG_MANUAL_FRTL_START_BIT,
-                (MBI_CFG_MANUAL_FRTL_END_BIT -
-                 MBI_CFG_MANUAL_FRTL_START_BIT + 1));
-            rc_ecmd |= mask.setBit(
-                MBI_CFG_MANUAL_FRTL_START_BIT,
-                (MBI_CFG_MANUAL_FRTL_END_BIT -
-                 MBI_CFG_MANUAL_FRTL_START_BIT + 1));
-
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL value",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
 
-            rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,
-                                                        mask);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to set manual FRTL value");
-                break;
-            }
 
-            // write FRTL manual done bit into Centaur MBI Configuration
-            // Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing Centaur MBI Configuration register to set manual FRTL done bit ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MBI_CFG_MANUAL_FRTL_DONE_BIT);
-            rc_ecmd |= data.copy(mask);
-            if (rc_ecmd)
-            {
-                FAPI_ERR( "proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL done",
-                          rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
 
-            rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,
-                                                        mask);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing Centaur MBI Configuration register to set manual FRTL done");
-                break;
-            }
 
-            // disable auto FRTL mode & channel init timeout in P8 MCI
-            // Configuration Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to disable auto FRTL mode & channel init timeout ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MCI_CFG_AUTO_FRTL_DISABLE_BIT);
-            rc_ecmd |= data.copy(mask);
-            rc_ecmd |= data.insertFromRight(
-                (uint32_t)(CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
-                           MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-                MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            rc_ecmd |= mask.setBit(
-                MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-                (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-                 MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-            if (rc_ecmd)
+        // Start FL and FRTL in error state
+
+        if(  ((fl_fail == 1) || (frtl_fail == 1)) && (num_try > 0) && (num_try <= 3)   )
+
+
+        {
+
+
+            // Force MBI in Channel Fail State
+            l_ecmdRc |= mbi_data.flushTo0();
+            l_ecmdRc |= mbi_data.setBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
+            l_ecmdRc |= mbi_data.copy(mbi_mask);
+            if (l_ecmdRc)
             {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to disable P8 auto FRTL mode",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
+                FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MBI in channel fail state",
+                         l_ecmdRc);
+                l_rc.setEcmdError(l_ecmdRc);
                 break;
             }
 
-            rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                       i_args);
-            if (rc)
+            l_rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, mbi_data,  mbi_mask);
+            if (l_rc)
             {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to disable auto FRTL mode");
+                FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Configuration Register to force framelock");
                 break;
             }
 
-            // write specified FRTL value into P8 MCI Configuration Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to set manual FRTL value ...");
-            if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
+
+            //Force MCI in Channel Fail State
+            l_ecmdRc |= mci_data.flushTo0();
+            l_ecmdRc |= mci_data.setBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
+            l_ecmdRc |= mci_data.copy(mci_mask);
+            if (l_ecmdRc)
             {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Out of range value 0x%x presented for P8 manual FRTL argument value!",
-                         i_args.frtl_manual_pu);
-                const proc_cen_framelock_args & ARGS = i_args;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
+                FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MCI in channel fail state",
+                         l_ecmdRc);
+                l_rc.setEcmdError(l_ecmdRc);
                 break;
             }
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= mask.flushTo0();
-            rc_ecmd |= data.insertFromRight(
-                (uint32_t)(i_args.frtl_manual_pu &
-                           MCI_CFG_MANUAL_FRTL_FIELD_MASK),
-                MCI_CFG_MANUAL_FRTL_START_BIT,
-                (MCI_CFG_MANUAL_FRTL_END_BIT -
-                 MCI_CFG_MANUAL_FRTL_START_BIT + 1));
-            rc_ecmd |= mask.setBit(
-                MCI_CFG_MANUAL_FRTL_START_BIT,
-                (MCI_CFG_MANUAL_FRTL_END_BIT -
-                 MCI_CFG_MANUAL_FRTL_START_BIT + 1));
-
-            if (rc_ecmd)
+            l_rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, mci_data, mci_mask);
+            if (l_rc)
             {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to set P8 manual FRTL value",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
+                FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Configuration register to force MCI in channel fail state");
                 break;
             }
 
-            rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                       i_args);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set manual FRTL value");
-                break;
-            }
 
-            // write FRTL manual done bit into P8 MCI Configuration Register
-            FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration register to set manual FRTL done bit ...");
-            rc_ecmd |= data.flushTo0();
-            rc_ecmd |= data.setBit(MCI_CFG_MANUAL_FRTL_DONE_BIT);
-            rc_ecmd |= data.copy(mask);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to write P8 manual FRTL done",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
 
-            rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask,
-                                                       i_args);
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to set manual FRTL done");
-                break;
-            }
 
-            // Read Centaur MBI FIR Register
-            rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
+           // Increment the number of try and delay next attempt by 1ms, if either the FL or FRTL steps above failed
+           //num_try++;
+           //sleep(1);
+           fapiDelay(1000000, 100);   //fapiDelay(nanoseconds, simcycles)
 
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error reading Centaur MBI FIR Register");
-                break;
-            }
 
-            // Read P8 MCI FIR Register
-            rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, i_args,
-                                                       mci_fir);
+           // execute framelock
+           l_rc = proc_cen_framelock_run_errstate_framelock(i_pu_target, i_mem_target,
+                                                            i_args);
+           if (l_rc)
+           {
+               break;
+           }
 
-            if (rc)
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register");
-                break;
-            }
 
-            // Fail if any Centaur FIR bits are set
-            if (mbi_fir.getDoubleWord(0))
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (manual). Centaur MBI FIR bit on (0x%llx)",
-                         mbi_fir.getDoubleWord(0));
-                ecmdDataBufferBase & FIR_REG = mbi_fir;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FIR_ERR);
-                break;
-            }
+           // In error state attempt FRTL although FL might have failed
+           if (i_args.frtl_auto_not_manual)
+           {
+               // Auto mode
+
+               // execute FRTL
+               l_rc = proc_cen_framelock_run_errstate_frtl(i_pu_target, i_mem_target,
+                                                           i_args);
+               if (l_rc)
+               {
+                   break;
+               }
+
+           }
+           else
+           {
+
+              // Manual mode
+
+              l_rc = proc_cen_framelock_run_manual_frtl(i_pu_target, i_mem_target,
+                                                        i_args);
+              if (l_rc)
+              {
+                  break;
+              }
+
+           } // end if .... else
 
-            // Fail if any P8 FIR bits are set
-            if (mci_fir.getDoubleWord(0))
-            {
-                FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail (manual). P8 MCI FIR bit on (0x%llx)",
-                         mci_fir.getDoubleWord(0));
-                ecmdDataBufferBase & FIR_REG = mci_fir;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR);
-                break;
-            }
         }
 
-    } while (0);
 
-    return rc;
-}
 
-//------------------------------------------------------------------------------
-// Hardware Procedure
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
-                                    const fapi::Target& i_mem_target,
-                                    const proc_cen_framelock_args& i_args)
-{
-    fapi::ReturnCode rc;
+        num_try++;
+        //sleep(1);
+        fapiDelay(1000000, 200);    //fapiDelay(nanoseconds, simcycles)
 
-    // mark HWP entry
-    FAPI_IMP("proc_cen_framelock: Entering ...");
 
-    do
+        if ( (num_try > 3) && ((fl_fail == 1) || (frtl_fail == 1)) )
+        {
+
+           FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+
+
+        }
+
+
+         //FAPI_DBG("Number Try: %d", num_try);
+         //FAPI_DBG("Frame Lock Pass at Value End of Loop: %d", fl_pass);
+         //FAPI_DBG("Frame Lock Fail at Value End of Loop: %d", fl_fail);
+         //FAPI_DBG("FRTL Pass Value at End of Loop: %d", frtl_pass);
+         //FAPI_DBG("FRTL Fail Value at End of Loop: %d", frtl_fail);
+
+
+    }  // End While
+
+
+
+
+    //Clear FIR registers if frame lock is a success before exiting procedure
+
+    if( (fl_pass == 1) && (fl_fail == 0) && (frtl_pass == 1) && (frtl_fail == 0) && (num_try <= 3) )
     {
-        // validate arguments
-        if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK)
+
+
+        // Clear P8 MCI FIR registers
+        l_rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
+        if (l_rc)
         {
-            FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL mem argument value!",
-                     i_args.frtl_manual_mem);
-            const proc_cen_framelock_args & ARGS = i_args;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-            break;
+            FAPI_ERR("proc_cen_framelock: Error clearing P8 MCI FIR regs");
+           // break;
         }
 
-        if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
+        // Clear Centaur MBI FIR registers
+        l_rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target);
+        if (l_rc)
         {
-            FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL pu argument value!",
-                     i_args.frtl_manual_pu);
-            const proc_cen_framelock_args & ARGS = i_args;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-            break;
+            FAPI_ERR("proc_cen_framelock: Error clearing Centaur MBI FIR regs");
+           // break;
         }
 
-        // execute framelock
-        rc = proc_cen_framelock_run_framelock(i_pu_target, i_mem_target,
-                                              i_args);
-        if (rc)
+    }
+
+
+
+
+    // EXIT Procedure
+    // by setting the MCI and MBI fir mask and action registers according to PRD requirements.
+
+
+        // Set P8 MCI FIR Mask
+        l_ecmdRc |= mci_data.flushTo0();
+        l_ecmdRc |= mci_data.setBit(0);     //Replay Timeout
+        l_ecmdRc |= mci_data.setBit(4);     //Seqid OOO
+        l_ecmdRc |= mci_data.setBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mci_data.setBit(6);     //Replay Buffer UE
+        l_ecmdRc |= mci_data.setBit(8);     //MCI Internal Control Parity Error
+        l_ecmdRc |= mci_data.setBit(9);     //MCI Data Flow Parity Error
+        l_ecmdRc |= mci_data.setBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mci_data.setBit(12);    //Centaur Checkstop
+        l_ecmdRc |= mci_data.setBit(15);    //Centaur Recoverable Attention
+        l_ecmdRc |= mci_data.setBit(16);    //Centaur Special Attention
+        l_ecmdRc |= mci_data.setBit(17);    //Centaur Maintenance Complete
+        l_ecmdRc |= mci_data.setBit(20);    //SCOM Register Parity Error
+        l_ecmdRc |= mci_data.setBit(22);    //MCICFGQ Parity Error
+        l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
+        l_ecmdRc |= mci_data.copy(mci_mask);
+        l_ecmdRc |= mci_data.clearBit(0);     //Replay Timeout
+        l_ecmdRc |= mci_data.clearBit(4);     //Seqid OOO
+        l_ecmdRc |= mci_data.clearBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mci_data.clearBit(6);     //Replay Buffer UE
+        l_ecmdRc |= mci_data.clearBit(8);     //MCI Internal Control Parity Error
+        l_ecmdRc |= mci_data.clearBit(9);     //MCI Data Flow Parity Error
+        l_ecmdRc |= mci_data.clearBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mci_data.clearBit(12);    //Centaur Checkstop
+        l_ecmdRc |= mci_data.clearBit(15);    //Centaur Recoverable Attention
+        l_ecmdRc |= mci_data.clearBit(16);    //Centaur Special Attention
+        l_ecmdRc |= mci_data.clearBit(17);    //Centaur Maintenance Complete
+        l_ecmdRc |= mci_data.clearBit(20);    //SCOM Register Parity Error
+        l_ecmdRc |= mci_data.clearBit(22);    //MCICFGQ Parity Error
+        l_ecmdRc |= mci_data.clearBit(40);    //MCS Channel Timeout Error
+        if (l_ecmdRc)
         {
-            break;
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MCI FIRs",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
         }
 
-        // execute FRTL
-        rc = proc_cen_framelock_run_frtl(i_pu_target, i_mem_target, i_args);
-        if (rc)
+        l_rc = proc_cen_framelock_set_pu_mci_firmask_reg(i_pu_target, mci_data, mci_mask);
+        if (l_rc)
         {
-            break;
+            FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Mask Register");
+           // break;
+        }
+
+
+        // Set P8 MCI FIR ACT0
+        //     Set action regs to recoverable interrupt (action0=1, action1=0) for MCIFIR's 12,15,16 and 17
+        l_ecmdRc |= mci_data.flushTo0();
+        l_ecmdRc |= mci_data.setBit(12);    //Centaur Checkstop
+        l_ecmdRc |= mci_data.setBit(15);    //Centaur Recoverable Attention
+        l_ecmdRc |= mci_data.setBit(16);    //Centaur Special Attention
+        l_ecmdRc |= mci_data.setBit(17);    //Centaur Maintenance Complete
+        l_ecmdRc |= mci_data.copy(mci_mask);
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
+        }
+
+        l_rc = proc_cen_framelock_set_pu_mci_firact0_reg(i_pu_target, mci_data, mci_mask);
+        if (l_rc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action0 Register");
+           // break;
         }
 
-    } while (0);
+
+
+        // Set P8 MCI FIR ACT1
+        //     Set action regs to recoverable error (action0=0, action1=1) for the following MCIFIR's
+        l_ecmdRc |= mci_data.flushTo0();
+        l_ecmdRc |= mci_data.setBit(0);     //Replay Timeout
+        l_ecmdRc |= mci_data.setBit(4);     //Seqid OOO
+        l_ecmdRc |= mci_data.setBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mci_data.setBit(6);     //Replay Buffer UE
+        l_ecmdRc |= mci_data.setBit(8);     //MCI Internal Control Parity Error
+        l_ecmdRc |= mci_data.setBit(9);     //MCI Data Flow Parity Error
+        l_ecmdRc |= mci_data.setBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mci_data.setBit(20);    //Scom Register parity error
+        l_ecmdRc |= mci_data.setBit(22);    //mcicfgq parity error
+        l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
+        l_ecmdRc |= mci_data.copy(mci_mask);
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
+        }
+
+        l_rc = proc_cen_framelock_set_pu_mci_firact1_reg(i_pu_target, mci_data, mci_mask);
+        if (l_rc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action1 Register");
+           // break;
+        }
+
+
+
+        // Set P8 MCS Mode4 Register
+        //     Enable recoverable interrupt output of MCS_MCIFIR to drive host attention
+        //        MCMODE4Q[12]=0 (disable special attention output)
+        //        MCMODE4Q[13]=1 (enable host attention output)
+
+        l_ecmdRc |= mci_data.flushTo0();
+        l_ecmdRc |= mci_data.setBit(12);    //MCS FIR recov_int output drives MCS spec_attn_output
+        l_ecmdRc |= mci_data.setBit(13);    //MCS FIR recov_int output drives MCS host_attn_output
+        l_ecmdRc |= mci_data.copy(mci_mask);
+        l_ecmdRc |= mci_data.clearBit(12);  //MCS FIR recov_int output drives MCS spec_attn_output
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCS Mode4 Register",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
+        }
+
+        l_rc = proc_cen_framelock_set_pu_mcs_mode4_reg(i_pu_target, mci_data, mci_mask);
+        if (l_rc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error writing P8 MCS Mode4 Register");
+           // break;
+        }
+
+
+
+
+
+        // Set Centaur MBI FIR Mask
+        l_ecmdRc |= mbi_data.flushTo0();
+        l_ecmdRc |= mbi_data.setBit(0);     //Replay Timeout
+        l_ecmdRc |= mbi_data.setBit(4);     //Seqid ooo
+        l_ecmdRc |= mbi_data.setBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mbi_data.setBit(6);     //Replay Buffer UE
+        l_ecmdRc |= mbi_data.setBit(8);     //MBI Internal Control Parity Error
+        l_ecmdRc |= mbi_data.setBit(9);     //MBI Data Flow Parity Error
+        l_ecmdRc |= mbi_data.setBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mbi_data.setBit(16);    //SCOM Register parity
+        l_ecmdRc |= mbi_data.setBit(19);    //MBICFGQ Parity Error
+        l_ecmdRc |= mbi_data.copy(mbi_mask);
+        l_ecmdRc |= mbi_data.clearBit(0);     //Replay Timeout
+        l_ecmdRc |= mbi_data.clearBit(4);     //Seqid ooo
+        l_ecmdRc |= mbi_data.clearBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mbi_data.clearBit(6);     //Replay Buffer UE
+        l_ecmdRc |= mbi_data.clearBit(8);     //MBI Internal Control Parity Error
+        l_ecmdRc |= mbi_data.clearBit(9);     //MBI Data Flow Parity Error
+        l_ecmdRc |= mbi_data.clearBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mbi_data.clearBit(16);    //SCOM Register parity
+        l_ecmdRc |= mbi_data.clearBit(19);    //MBICFGQ Parity Error
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MBI FIRs",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
+        }
+
+        l_rc = proc_cen_framelock_set_cen_mbi_firmask_reg(i_mem_target, mbi_data, mbi_mask);
+        if (l_rc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Mask Register");
+           // break;
+        }
+
+
+        // No Bits are set in FIR ACT0
+
+        // Set P8 MBI FIR ACT1
+        l_ecmdRc |= mbi_data.flushTo0();
+        l_ecmdRc |= mbi_data.setBit(4);     //Seqid OOO
+        l_ecmdRc |= mbi_data.setBit(5);     //Replay Buffer CE
+        l_ecmdRc |= mbi_data.setBit(10);    //CRC Performance Degradation
+        l_ecmdRc |= mbi_data.setBit(16);    //Scom Register parity error
+        l_ecmdRc |= mbi_data.copy(mbi_mask);
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MBI FIR actions",
+                     l_ecmdRc);
+            l_rc.setEcmdError(l_ecmdRc);
+           // break;
+        }
+
+        l_rc = proc_cen_framelock_set_cen_mbi_firact1_reg(i_mem_target, mbi_data, mbi_mask);
+        if (l_rc)
+        {
+            FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Action1 Register");
+           // break;
+        }
+
+
+
 
     // mark HWP exit
     FAPI_IMP("proc_cen_framelock: Exiting ...");
-    return rc;
+    return l_rc;
 }
 
+
+
+
+
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
index 78c20c35b..251876ca3 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: proc_cen_framelock.H,v 1.6 2012/07/23 14:15:49 jmcgill Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_cen_framelock.H,v 1.7 2012/10/12 03:35:07 baysah Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -53,6 +52,9 @@
 //------------------------------------------------------------------------------
 
 #include <fapi.H>
+#include <fapiUtil.H>
+#include <p8_scom_addresses.H>
+#include <cen_scom_addresses.H>
 
 //------------------------------------------------------------------------------
 // Structure definitions
@@ -70,7 +72,6 @@ enum proc_cen_framelock_channel_init_timeout
 // structure to represent HWP arguments
 struct proc_cen_framelock_args
 {
-    bool in_error_state; // apply error state overrides to framelock/auto FRTL?
     proc_cen_framelock_channel_init_timeout channel_init_timeout;
                          // channel init timeout value to program for framelock/
                          // auto/FRTL
@@ -97,6 +98,7 @@ const uint8_t PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS = 5;
 const uint8_t PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS = 5;
 
 // P8 MCI Configuration Register field/bit definitions
+const uint32_t MCI_CFG_FORCE_CHANNEL_FAIL_BIT = 0;
 const uint32_t MCI_CFG_START_FRAMELOCK_BIT = 7;
 const uint32_t MCI_CFG_START_FRTL_BIT = 8;
 const uint32_t MCI_CFG_AUTO_FRTL_DISABLE_BIT = 9;
@@ -114,8 +116,22 @@ const uint32_t MCI_STAT_FRAMELOCK_PASS_BIT = 0;
 const uint32_t MCI_STAT_FRAMELOCK_FAIL_BIT = 1;
 const uint32_t MCI_STAT_FRTL_PASS_BIT = 2;
 const uint32_t MCI_STAT_FRTL_FAIL_BIT = 3;
+const uint32_t MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT = 12;
+const uint32_t MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT = 13;
+
+// P8 MCI FIR Register field/bit definitions
+const uint32_t MCI_FIR_DMI_CHANNEL_FAIL_BIT = 1;
+const uint32_t MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT = 7;
+const uint32_t MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT = 8;
+const uint32_t MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT = 9;
+const uint32_t MCI_FIR_CHANNEL_INTERLOCK_FAIL_BIT = 11;
+const uint32_t MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT = 12;
+const uint32_t MCI_FIR_FRTL_COUNTER_OVERFLOW_BIT = 19;
+const uint32_t MCI_FIR_MCICFGQ_PARITY_ERROR_BIT = 22;
+const uint32_t MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT = 31;
 
 // Centaur MBI Configuration Register field/bit defintions
+const uint32_t MBI_CFG_FORCE_CHANNEL_FAIL_BIT = 0;
 const uint32_t MBI_CFG_FORCE_FRAMELOCK_BIT = 7;
 const uint32_t MBI_CFG_FORCE_FRTL_BIT = 8;
 const uint32_t MBI_CFG_AUTO_FRTL_DISABLE_BIT = 9;
@@ -133,6 +149,19 @@ const uint32_t MBI_STAT_FRAMELOCK_PASS_BIT = 0;
 const uint32_t MBI_STAT_FRAMELOCK_FAIL_BIT = 1;
 const uint32_t MBI_STAT_FRTL_PASS_BIT = 2;
 const uint32_t MBI_STAT_FRTL_FAIL_BIT = 3;
+const uint32_t MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT = 13;
+const uint32_t MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT = 14;
+
+// Centaur MBI FIR Register field/bit definitions
+const uint32_t MBI_FIR_DMI_CHANNEL_FAIL_BIT = 1;
+const uint32_t MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT = 7;
+const uint32_t MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT = 8;
+const uint32_t MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT = 9;
+const uint32_t MBI_FIR_GLOBAL_HOST_CHECKSTOP_BIT = 11;
+const uint32_t MBI_FIR_CHANNEL_INTERLOCK_FAIL_BIT = 13;
+const uint32_t MBI_FIR_LOCAL_HOST_CHECKSTOP_BIT = 14;
+const uint32_t MBI_FIR_FRTL_COUNTER_OVERFLOW_BIT = 15;
+const uint32_t MBI_FIR_MBICFGQ_PARITY_ERROR_BIT = 19;
 
 extern "C"
 {
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
index f40659140..abb0cebfb 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_setup_bars.C,v 1.22 2012/10/03 13:39:03 gpaulraj Exp $
+// $Id: mss_setup_bars.C,v 1.25 2012/12/04 14:47:59 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -38,6 +38,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.23   | bellows  | 12/04/12| more updates
 //  1.22   | gpaulraj | 10/03/12| review updates
 //  1.21   | gpaulraj | 10/02/12| review updates
 //  1.19   | bellows  | 09/25/12| review updates
@@ -68,11 +69,13 @@ extern "C" {
     ecmdDataBufferBase MCFGPA_data(64);
     ecmdDataBufferBase MCFGPMA_data(64);
 //    uint64_t mem_base;
-    uint64_t mirror_base;
+//    uint64_t mirror_base;
     uint64_t mem_bases[8];
     uint64_t l_memory_sizes[8];
     uint64_t mirror_bases[4];
     uint64_t l_mirror_sizes[4];
+//    uint64_t alter_mem_base;
+//    uint64_t alter_mirror_base;
     uint32_t groupID[16][16];
     uint8_t groups[8];
     do
@@ -106,61 +109,22 @@ extern "C" {
         // process mirrored ranges
         //
 
-        // read chip base address attribute
-      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_chip_target, mirror_base);
+      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases);
       if (!rc.ok())
       {
-        FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
+        FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASES");
         break;
       }
-
-        // base addresses for distinct mirrored ranges
-      mirror_bases[0] = mirror_base;
-      mirror_bases[1] = 0x0;
-      mirror_bases[2] = 0x0;
-      mirror_bases[3] = 0x0;
-
-      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases[3]);
-
-      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_chip_target, mirror_bases);
+      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes);
       if (!rc.ok())
       {
-        FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES");
+        FAPI_ERR("Error  reading ATTR_PROC_MIRROR_SIZES");
         break;
       }
-
-        // sizes for distinct mirrored ranges
-      l_mirror_sizes[0]=0;
-      l_mirror_sizes[1]=0;
-      l_mirror_sizes[2]=0;
-      l_mirror_sizes[3]=0;
-
-      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]);
-      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]);
-
-      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_chip_target, l_mirror_sizes);
+      rc = FAPI_ATTR_GET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups);
       if (!rc.ok())
       {
-        FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES");
-        break;
-      }
-      groups[0]=0x0C;
-      groups[1]=0x00;
-      groups[2]=0x00;
-      groups[3]=0x00;
-      groups[4]=0x00;
-      groups[5]=0x00;
-      groups[6]=0x00;
-      groups[7]=0x00;
-      rc = FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_chip_target, groups);
-      if (!rc.ok())
-      {
-        FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP");
+        FAPI_ERR("Error  reading ATTR_MSS_MEM_MC_IN_GROUP");
         break;
       }
 
@@ -217,18 +181,6 @@ extern "C" {
           FAPI_ERR("Error Reading  MCS_MCFGPM_0x02011801");
           break;
         }	       	
-        rc = fapiGetScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
-        if (!rc.ok())
-        {
-          FAPI_ERR("Error Reading  MCS_MCFGPA_0x02011814");
-          break;
-        }	
-        rc = fapiGetScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
-        if (!rc.ok())
-        {
-          FAPI_ERR("Error Reading  MCS_MCFGPMA_0x02011815");
-          break;
-        }
         for(uint8_t i=0; (i<16)&&(rc.ok()); i++)
         {
           uint32_t temp=0;
@@ -243,35 +195,7 @@ extern "C" {
               MCFGP_data.insertFromRight(temp/2,1,3);
               MCFGP_data.insertFromRight((j-4),4,5);
 
-                     //b = groupID[i][2]>>3;
               b = ((l_memory_sizes[i]>>30) / 4) - 1;
-              // 					switch ((l_memory_sizes[i]>>30))
-              // 					{
-              // 						case 4:   b = 0;
-              // 						break;
-              //                                                case 8:   b = 1;
-              //                                                break;
-              //                                                case 16:  b = 3;
-              //            l                                    break;
-              //                                                case 32:  b = 7;
-              //                                                break;
-              //                                                case 64:  b = 15;
-              //                                                break;
-              //                                                case 128: b = 31;
-              //                                                break;
-              //                                                case 256: b = 63;
-              //                                                break;
-              //                                                case 512: b = 127;
-              //                                                break;
-              //                                                case 1024:b = 255;
-              //                                                break;
-              //                                                case 2048:b = 511;
-              //                                                break;
-              //                                                case 4096:b = 1023;
-              //                                                break;
-              //                                                case 8192:b = 2047;
-              //                                                break;
-              //                                   }
               MCFGP_data.insertFromRight(b,11,13);
               b = mem_bases[i]>>32;
               MCFGP_data.insertFromRight(b,26,18);
@@ -296,36 +220,43 @@ extern "C" {
                 FAPI_ERR("Error from fapiPutScom MCS_MCFGP_0x02011800");
                 break;
               }
+
+             if(temp>1)
+             {
+
+                //setting the MCFGPM register
+                  b = ((l_mirror_sizes[i]>>30) / 4) - 1;
+                  MCFGPM_data.insertFromRight(b,11,13);
+                  b = mirror_bases[i]>>32;
+                  MCFGPM_data.insertFromRight(b,26,18);
+                  rc = fapiPutScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
+                  if (!rc.ok())
+                  {
+                     FAPI_ERR("Error writing  MCS_MCFGPM_0x02011801");
+                     break;
+                  }		       		
+                  rc = fapiGetScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
+                  if (!rc.ok())
+                  {
+                    FAPI_ERR("Error reading  MCS_MCFGPM_0x02011801");
+                    break;
+                  }
+
+                  MCFGPM_data.setBit(0);
+                  FAPI_DBG("Writing MCS %d MCFGPM = 0x%llx",mcs_pos, MCFGPM_data.getDoubleWord(0));
+                  rc = fapiPutScom(*iter, MCS_MCFGPM_0x02011801, MCFGPM_data);
+                  if (!rc.ok())
+                  {
+                     FAPI_ERR("Error from fapiPutScom MCS_MCFGPM_0x02011801");
+                     break;
+                  }
+              }
+
               if(groupID[i][12])
+
               {
-                b = ((groupID[i][13]) / 4) - 1;
-//                            switch (groupID[i][13])
-// 				 {
-// 							case 4:   b = 0;
-// 							break;
-// 							case 8:   b = 1;
-// 							break;
-// 							case 16:  b = 3;
-// 							break;
-// 							case 32:  b = 7;
-// 							break;
-// 							case 64:  b = 15;
-// 							break;
-// 							case 128: b = 31;
-// 							break;
-// 							case 256: b = 63;
-// 							break;
-// 							case 512: b = 127;
-// 							break;
-// 							case 1024:b = 255;
-// 							break;
-// 							case 2048:b = 511;
-// 							break;
-// 							case 4096:b = 1023;
-// 							break;
-// 							case 8192:b = 2047;
-// 							break;		
-// 				 }
+
+                b = (groupID[i][13] / 4) - 1;
                 MCFGPA_data.insertFromRight(b,11,13);
                 b = groupID[i][14]>>2;
                 MCFGPA_data.insertFromRight(b,26,18);
@@ -342,19 +273,56 @@ extern "C" {
                   break;
                 }					
                 MCFGPA_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
+                FAPI_DBG("Writing MCS %d MCFGPA = 0x%llx",mcs_pos, MCFGPA_data.getDoubleWord(0));
                 rc = fapiPutScom(*iter, MCS_MCFGPA_0x02011814, MCFGPA_data);
                 if (!rc.ok())
                 {
                   FAPI_ERR("Error writing  MCS_MCFGPA_0x02011814");
                   break;
                 }		       		
+
+                if(temp>1)
+                {
+                   //setting MCFGPMA
+                   b = (groupID[i+8][13]/ 4) - 1;
+                   MCFGPMA_data.insertFromRight(b,11,13);
+                   b = groupID[i+8][14]>>2;
+                   MCFGPMA_data.insertFromRight(b,26,18);
+                   rc = fapiPutScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
+                   if (!rc.ok())
+                   {
+                     FAPI_ERR("Error writing  MCS_MCFpGPMA_0x02011815");
+                     break;
+                   }		       		
+                   rc = fapiGetScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
+                   if (!rc.ok())
+                   {
+                     FAPI_ERR("Error reading  MCS_MCFGPMA_0x02011815");
+                     break;
+                   }					
+                   MCFGPMA_data.setBit(0);  //  Read registers value and set Zero bit as per register specification
+                   FAPI_DBG("Writing MCS %d MCFGPMA = 0x%llx",mcs_pos, MCFGPMA_data.getDoubleWord(0));
+                   rc = fapiPutScom(*iter, MCS_MCFGPMA_0x02011815, MCFGPMA_data);
+                   if (!rc.ok())
+                   {
+                     FAPI_ERR("Error writing  MCS_MCFGPMA_0x02011815");
+                     break;
+                   }
+                 }
               }
             }
           }
         }
       }
-    }
-    while(0);
+       uint8_t final=1;
+       rc=FAPI_ATTR_SET( ATTR_MSS_MEM_IPL_COMPLETE, &i_chip_target ,final);
+       if (!rc.ok())
+       {
+           FAPI_ERR("Error writing  TARGET_TYPE_PROC_CHIP");
+           break;
+        }
+    }while(0);
     return rc;
   }
+
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C
index 083786e64..95a1a7327 100644
--- a/src/usr/hwpf/hwp/dram_training/dram_training.C
+++ b/src/usr/hwpf/hwp/dram_training/dram_training.C
@@ -535,7 +535,7 @@ void*  call_mss_ddr_phy_reset( void *io_pArgs )
 
         // Cast to a FAPI type of target.
         const fapi::Target l_fapi_mba_target(
-                TARGET_TYPE_MEMBUF_CHIP,
+                TARGET_TYPE_MBA_CHIPLET,
                 reinterpret_cast<void *>
         (const_cast<TARGETING::Target*>(l_mba_target)) );
 
@@ -707,7 +707,7 @@ void*    call_mss_draminit_training( void *io_pArgs )
 
         // Cast to a FAPI type of target.
         const fapi::Target l_fapi_mba_target(
-                TARGET_TYPE_MEMBUF_CHIP,
+                TARGET_TYPE_MBA_CHIPLET,
                 reinterpret_cast<void *>
         (const_cast<TARGETING::Target*>(l_mba_target)) );
 
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile
index e2ff8c7de..121e8677b 100644
--- a/src/usr/hwpf/hwp/dram_training/makefile
+++ b/src/usr/hwpf/hwp/dram_training/makefile
@@ -52,9 +52,11 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup
 OBJS =  dram_training.o \
         mss_draminit.o \
         mss_funcs.o \
+        mss_unmask_errors.o \
         mss_draminit_mc.o \
         mss_draminit_training.o \
         mss_ddr_phy_reset.o \
+        mss_termination_control.o \
         cen_mem_startclocks.o \
 		mss_scominit.o \
         cen_mem_pll_initf.o \
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
index 784577ac3..21dcbdb7c 100644
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
+++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.C,v 1.2 2012/08/27 16:05:20 mfred Exp $
+// $Id: cen_mem_pll_initf.C,v 1.3 2012/11/07 23:22:44 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -88,7 +88,7 @@ const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
 
 // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
 
-// Here are the bit definitions for the Analog PLL controller:
+// Here are the bit definitions for the Analog PLL controller:  (Checked with values from T.Diemoz Nov.7,2012)
 //
 //  Bits        Purpose                Value to be used for OutB=1600MHz (when using real HW PLL)
 // -------      --------------         ------------------------
@@ -104,7 +104,7 @@ const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
 // 46 to 54     mult                   011000000   (put different values here for different freqs)
 // 55 to 56     outsel                 00
 // 57 to 58     phasedet_tune          10
-// 59           fbksel                 1
+// 59           fbksel                 0
 // 60 to 63     rangea                 0001        (put different values here for different freqs)
 // 64 to 67     rangeb                 0011        (put different values here for different freqs)
 // 68           refdiv                 0
@@ -148,32 +148,32 @@ const uint64_t MEM_PLL_CNTRL2_SIM_FREQ_1600  = 0x0F;   // Temp value:  Put F int
 // HARDWARE-ONLY PLL SETTINGS:
 //------------------------------
 // TODO adjust this HW setting for PLL OutputB = 800 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_800   = 0x128000000A018051ull;
+const uint64_t MEM_PLL_CNTRL0_FREQ_800   = 0x128000000A018041ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_800   = 0x3000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_800   = 0x00;
 
 // TODO adjust this HW setting for PLL OutputB = 1066 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_1066  = 0x128000000A018051ull;
+const uint64_t MEM_PLL_CNTRL0_FREQ_1066  = 0x128000000A018041ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_1066  = 0x3000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_1066  = 0x00;
 
-// HW Setting for PLL OutputB = 1333 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_1333  = 0x128000000A028051ull;
+// HW Setting for PLL OutputB = 1333 Mhz (Checked with values from T.Diemoz Nov.7,2012)
+const uint64_t MEM_PLL_CNTRL0_FREQ_1333  = 0x128000000A028041ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_1333  = 0x3000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_1333  = 0x00;
 
-// HW Setting for PLL OutputB = 1600 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_1600  = 0x128000000A018051ull;
+// HW Setting for PLL OutputB = 1600 Mhz (Checked with values from T.Diemoz Nov.7,2012)
+const uint64_t MEM_PLL_CNTRL0_FREQ_1600  = 0x128000000A018041ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_1600  = 0x3000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_1600  = 0x00;
 
-// HW Setting for PLL OutputB = 1866 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_1866  = 0x128000000A038055ull;
+// HW Setting for PLL OutputB = 1866 Mhz (Checked with values from T.Diemoz Nov.7,2012)
+const uint64_t MEM_PLL_CNTRL0_FREQ_1866  = 0x128000000A038045ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_1866  = 0xB000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_1866  = 0x00;
 
 // TODO adjust this HW setting for PLL OutputB = 2133 Mhz
-const uint64_t MEM_PLL_CNTRL0_FREQ_2133  = 0x128000000A018051ull;
+const uint64_t MEM_PLL_CNTRL0_FREQ_2133  = 0x128000000A018041ull;
 const uint64_t MEM_PLL_CNTRL1_FREQ_2133  = 0x3000000200000000ull;
 const uint64_t MEM_PLL_CNTRL2_FREQ_2133  = 0x00;
 
@@ -265,12 +265,14 @@ fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
             // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz  (These are the DDR frequencies and the PLL output B frequencies.)
             if (mss_freq == 800)
             {
+FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
                 rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_800 );
                 rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_800 );
                 rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_800 );
             }
             else if (mss_freq == 1066)
             {
+FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
                 rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_1066 );
                 rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_1066 );
                 rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_1066 );
@@ -295,6 +297,7 @@ fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
             }
             else if (mss_freq == 2133)
             {
+FAPI_ERR("PLL settings not specified for this frequency.  Defaulting to 1600MHz..");
                 rc_ecmd |= pll_data.setDoubleWord( 0, MEM_PLL_CNTRL0_FREQ_2133 );
                 rc_ecmd |= pll_data.setDoubleWord( 1, MEM_PLL_CNTRL1_FREQ_2133 );
                 rc_ecmd |= pll_data.setByte(      16, MEM_PLL_CNTRL2_FREQ_2133 );
@@ -490,6 +493,9 @@ fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: cen_mem_pll_initf.C,v $
+Revision 1.3  2012/11/07 23:22:44  mfred
+Updated MEM PLL settings for HW with values from Tim Diemoz.
+
 Revision 1.2  2012/08/27 16:05:20  mfred
 committing minor updates as suggested by FW review.
 
diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
index 8a3811b8d..98b56aa52 100644
--- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml
+++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
@@ -1,25 +1,25 @@
-<!--  IBM_PROLOG_BEGIN_TAG
-     This is an automatically generated prolog.
-   
-     $Source: src/usr/hwpf/hwp/dram_training/memory_errors.xml $
-   
-     IBM CONFIDENTIAL
-   
-     COPYRIGHT International Business Machines Corp. 2012
-   
-     p1
-   
-     Object Code Only (OCO) source materials
-     Licensed Internal Code Source Materials
-     IBM HostBoot Licensed Internal Code
-   
-     The source code for this program is not published or other-
-     wise divested of its trade secrets, irrespective of what has
-     been deposited with the U.S. Copyright Office.
-   
-     Origin: 30
-   
-     IBM_PROLOG_END_TAG -->
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dram_training/memory_errors.xml $            -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
@@ -96,6 +96,11 @@
 </hwpError>
 
   <hwpError>
+    <rc>RC_MSS_INIT3_FSISTATUS_FAIL</rc>
+    <description>Failed clock region check on FSI2PIB Status Reg bit(31).</description>
+</hwpError>
+
+  <hwpError>
     <rc>RC_MSS_PLL_LOCK_TIMEOUT</rc>
     <description>Timed out waiting for PLL locks in FSI2PIB Status Reg bits(24,25). </description>
 </hwpError>
@@ -321,6 +326,113 @@
     <description>Less than 2 MBA's returned by fapiGetChildChiplets</description>
 </hwpError>
 
+  <hwpError>
+    <rc>RC_MSS_SLEW_CAL_ERROR</rc>
+    <description>Slew calibration error occurred.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_INVALID_FREQ</rc>
+    <description>MSS_FREQ attribute equals 0.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_INVALID_DRAM_GEN</rc>
+    <description>DRAM_GEN attribute is not valid; equals 0 for empty.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_IMP_INPUT_ERROR</rc>
+    <description>Impedance is invalid for driver/receiver type.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_INVALID_FN_INPUT_ERROR</rc>
+    <description>An input to FN call is out of range.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MCBIST_TIMEOUT_ERROR</rc>
+    <description>Timeout on MCBIST configuration register polling.</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_MCBIST_ERROR</rc>
+    <description>MCBIST operation failed</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_PORT_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DRIVER_IMP_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_SLEW_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_WR_DRAM_VREF_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_READ_CEN_VREF_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_RECEIVER_IMP_INPUT_ERROR</rc>
+    <description>TBD</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION</rc>
+    <description>One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.</description>
+ <!-- Deconfigure MASTER_CHIP -->
+ <deconfigure><target>MASTER_CHIP</target></deconfigure>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED</rc>
+    <description>One or more Rank Pairs Stalled Init Cal within Draminit_training</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED</rc>
+    <description>One or more Rank Pairs Failed Init Cal within Draminit_training</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DIMM_POWER_CURVE_DATA_LAB</rc>
+    <description>DIMM power curve data is lab data not MSL</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DIMM_POWER_CURVE_DATA_INVALID</rc>
+    <description>DIMM power curve data is invalid</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE</rc>
+    <description>Unable to find matching entry in DIMM power table</description>
+</hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER</rc>
+    <description>Unable to find throttle setting that has DIMM power underneath the limit</description>
+</hwpError>
+
+<hwpError>
+    <rc>RC_MSS_INPUT_ERROR</rc>
+    <description>Invalid input </description>
+</hwpError>
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
index 4032787f5..a6429eb1c 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_ddr_phy_reset.C,v 1.11 2012/07/27 16:43:25 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_ddr_phy_reset.C,v 1.17 2012/12/03 15:49:27 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -45,6 +44,9 @@
 #include <fapi.H>
 #include <cen_scom_addresses.H>
 #include <mss_ddr_phy_reset.H>
+#include <mss_termination_control.H>
+#include <mss_unmask_errors.H>
+#include <dimmBadDqBitmapFuncs.H>
 
 //  Constants
 const uint64_t  DELAY_100NS             = 100;      // general purpose 100 ns delay for HW mode   (2000 sim cycles if simclk = 20ghz)
@@ -64,12 +66,48 @@ extern "C" {
 
 using namespace fapi;
 
-   // prototype of function called in phy reset
+// prototypes of functions called in phy reset
 ReturnCode mss_deassert_force_mclk_low (const Target& i_target); 
-
+ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target);
 
 fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
 {
+
+    // Target is centaur.mba
+
+    fapi::ReturnCode rc;
+    fapi::ReturnCode slewcal_rc;
+
+    rc = mss_ddr_phy_reset_cloned(i_target);
+
+    slewcal_rc = mss_slew_cal(i_target);
+
+    // If mss_ddr_phy_reset returns an error
+    //      then log the error from mss_slew_cal (if any) and pass the error from mss_ddr_phy_reset
+    // If only mss_slew_cal returns an error
+    //      then move that error to RC and pass it along
+    if ((slewcal_rc) && (rc))
+    {
+        FAPI_ERR(" mss_slew_cal failed!   rc = 0x%08X (creator = %d)", uint32_t(slewcal_rc), slewcal_rc.getCreator());
+        fapiLogError(slewcal_rc);
+    }
+     else if (slewcal_rc)
+    {
+        rc = slewcal_rc;
+    }
+
+    // If mss_unmask_ddrphy_errors gets it's own bad rc,
+    // it will commit the passed in rc (if non-zero), and return it's own bad rc.
+    // Else if mss_unmask_ddrphy_errors runs clean,
+    // it will just return the passed in rc.
+    rc = mss_unmask_ddrphy_errors(i_target, rc);
+
+    return rc;
+}
+
+
+fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target)
+{
     // Target is centaur.mba
 
     fapi::ReturnCode rc;
@@ -77,26 +115,35 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
     uint32_t poll_count = 0;
     uint32_t done_polling = 0;
     uint8_t is_simulation = 0;
-    ecmdDataBufferBase i_data, j_data, k_data, l_data;
+    ecmdDataBufferBase i_data(64);
+    ecmdDataBufferBase dp_p0_lock_data(64);
+    ecmdDataBufferBase dp_p1_lock_data(64);
+    ecmdDataBufferBase ad_p0_lock_data(64);
+    ecmdDataBufferBase ad_p1_lock_data(64);
+    uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // 10 byte array of bad bits
+    uint8_t valid_dimms  = 0;
+    uint8_t valid_dimm[2][2];
+    uint8_t num_ranks_per_dimm[2][2];
+    uint8_t l_port       = 0;
+    uint8_t l_dimm       = 0;
+    uint8_t l_rank       = 0;
+    uint8_t new_error    = 0;
+    uint8_t P0_DP0_reg_error = 0;
+    uint8_t P0_DP1_reg_error = 0;
+    uint8_t P0_DP2_reg_error = 0;
+    uint8_t P0_DP3_reg_error = 0;
+    uint8_t P0_DP4_reg_error = 0;
+    uint8_t P1_DP0_reg_error = 0;
+    uint8_t P1_DP1_reg_error = 0;
+    uint8_t P1_DP2_reg_error = 0;
+    uint8_t P1_DP3_reg_error = 0;
+    uint8_t P1_DP4_reg_error = 0;
 
 
     FAPI_INF("********* mss_ddr_phy_reset start *********");
     do
     { 
 
-        rc_ecmd |= i_data.setBitLength(64);
-        rc_ecmd |= j_data.setBitLength(64);
-        rc_ecmd |= k_data.setBitLength(64);
-        rc_ecmd |= l_data.setBitLength(64);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer bit length.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-
-
         //
         // Here are the specific instructions from section 14.7.3 of the Centaur Chip Specification:
         //
@@ -114,12 +161,12 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
          // PLL Lock cannot happen if mclk low is asserted
         // this procedure was moved from draminit to:
         // Deassert Force_mclk_low signal
-        // see CQ 216395
+        // see CQ 216395 (HW217109)
         rc = mss_deassert_force_mclk_low(i_target);
         if(rc)
         {
             FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            return rc;
+            break;
         }
 
   
@@ -164,8 +211,8 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             break;
         }
 
-  
-  
+
+
         //
         // 3. For DD0: Deassert dfi_reset_all (GP4 bit 5 = "0")
         //    For DD1: Deassert mcbist_ddr_dfi_reset_recover = "0" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 0x03010EA7)
@@ -193,13 +240,13 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
   
   
         //
-        // 4. Write 0x0008 to PC IO PVT N/P FET driver control registers to assert ZCTL reset
-        //    and reset the internal impedance controller.(SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 4: Write 0x0008 to PC IO PVT N/P FET driver control registers to assert ZCTL reset.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000008ull);
+        // 4. Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset and enable the internal impedance controller.
+        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+        FAPI_DBG("Step 4: Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset.\n");
+        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000010ull);
         if (rc_ecmd)
         {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0008 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
+            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0010 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
@@ -215,17 +262,17 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
             break;
         }
-  
-  
-  
+
+
+
         //
-        // 5. Write 0x0000 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset
-        //                                                (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 5: Write 0x0000 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000000ull);
+        // 5. Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset while impedance controller is still enabled.
+        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+        FAPI_DBG("Step 5: Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset.\n");
+        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull);
         if (rc_ecmd)
         {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0000 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
+            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
@@ -241,13 +288,39 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
             break;
         }
-  
-  
-  
+
+
+
+        //
+        // 6. Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller.
+        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
+        FAPI_DBG("Step 6: Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller.\n");
+        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000008ull);
+        if (rc_ecmd)
+        {
+            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0008 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
+            rc.setEcmdError(rc_ecmd);
+            break;
+        }
+        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data);
+        if (rc)
+        {
+            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register.");
+            break;
+        }
+        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data);
+        if (rc)
+        {
+            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
+            break;
+        }
+
+
+
         //
-        // 6. Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active
+        // 7. Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active
         //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
-        FAPI_DBG("Step 6: Write 0x4000 into the PC Resets Regs. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active.\n");
+        FAPI_DBG("Step 7: Write 0x4000 into the PC Resets Regs. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active.\n");
         rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000004000ull);
         if (rc_ecmd)
         {
@@ -267,15 +340,17 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register.");
             break;
         }
-  
-  
-  
+
+
+
         //
-        // 7. Wait at least 1 millisecond to allow the PLLs to lock. Otherwise, poll the PC DP18 PLL Lock Status
+        // 8. Wait at least 1 millisecond to allow the PLLs to lock. Otherwise, poll the PC DP18 PLL Lock Status
         //    and the PC AD32S PLL Lock Status to determine if all PLLs have locked.
         //    PC DP18 PLL Lock Status should be 0xF800:  (SCOM Addr: 0x8000C0000301143F, 0x8001C0000301143F, 0x8000C0000301183F, 0x8001C0000301183F)
         //    PC AD32S PLL Lock Status should be 0xC000: (SCOM Addr: 0x8000C0010301143F, 0x8001C0010301143F, 0x8000C0010301183F, 0x8001C0010301183F)
-        FAPI_DBG("Step 7: Poll until DP18 and AD32S PLLs have locked....\n");
+        //------------------------
+        // 7a - Poll for lock bits
+        FAPI_DBG("Step 8: Poll until DP18 and AD32S PLLs have locked....\n");
         do
         {
             rc = fapiDelay(DELAY_1US, DELAY_20000SIMCYCLES); // wait 20000 simcycles (in sim mode) OR 1 usec (in hw mode)
@@ -285,74 +360,92 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
                 break;
             }
             done_polling = 1;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, i_data);
+            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, dp_p0_lock_data);
             if (rc)
             {
                 FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0 register.");
                 break;
             }
-            if ( i_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, j_data);
+            if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
+            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, dp_p1_lock_data);
             if (rc)
             {
                 FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1 register.");
                 break;
             }
-            if ( j_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, k_data);
+            if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
+            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, ad_p0_lock_data);
             if (rc)
             {
                 FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0 register.");
                 break;
             }
-            if ( k_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, l_data);
+            if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
+            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, ad_p1_lock_data);
             if (rc)
             {
                 FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1 register.");
                 break;
             }
-            if ( l_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
+            if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
             poll_count++;
         } while ((done_polling == 0) && (poll_count < MAX_POLL_LOOPS)); // Poll until PLLs are locked.
         if (rc) break;    // Go to end of proc if error found inside polling loop.
   
         if (poll_count == MAX_POLL_LOOPS)
         {
-            if ( i_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
+            //-------------------------------
+            // 7b - Check Port 0 DP lock bits
+            if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
             {
-                FAPI_ERR("DP18  0x0C000 PLL failed to lock!   Lock Status = %04X",i_data.getHalfWord(3));
+                FAPI_ERR("One or more DP18 port 0 (0x0C000) PLL failed to lock!   Lock Status = %04X",dp_p0_lock_data.getHalfWord(3));
                 FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_0_PLL_FAILED_TO_LOCK);
-                break;
+                if ( dp_p0_lock_data.isBitClear(48) ) { FAPI_ERR("Port 0 DP 0 PLL failed to lock!");}
+                if ( dp_p0_lock_data.isBitClear(49) ) { FAPI_ERR("Port 0 DP 1 PLL failed to lock!");}
+                if ( dp_p0_lock_data.isBitClear(50) ) { FAPI_ERR("Port 0 DP 2 PLL failed to lock!");}
+                if ( dp_p0_lock_data.isBitClear(51) ) { FAPI_ERR("Port 0 DP 3 PLL failed to lock!");}
+                if ( dp_p0_lock_data.isBitClear(52) ) { FAPI_ERR("Port 0 DP 4 PLL failed to lock!");}
+                // break;  // Don't break.  Keep going to initialize any other channels that might be good.
             }
-            if ( j_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
+            //-------------------------------
+            // 7c - Check Port 1 DP lock bits
+            if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
             {
-                FAPI_ERR("DP18  0x1C000 PLL failed to lock!   Lock Status = %04X",j_data.getHalfWord(3));
+                FAPI_ERR("One or more DP18 port 1 (0x1C000) PLL failed to lock!   Lock Status = %04X",dp_p1_lock_data.getHalfWord(3));
                 FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_1_PLL_FAILED_TO_LOCK);
-                break;
+                if ( dp_p1_lock_data.isBitClear(48) ) { FAPI_ERR("Port 1 DP 0 PLL failed to lock!");}
+                if ( dp_p1_lock_data.isBitClear(49) ) { FAPI_ERR("Port 1 DP 1 PLL failed to lock!");}
+                if ( dp_p1_lock_data.isBitClear(50) ) { FAPI_ERR("Port 1 DP 2 PLL failed to lock!");}
+                if ( dp_p1_lock_data.isBitClear(51) ) { FAPI_ERR("Port 1 DP 3 PLL failed to lock!");}
+                if ( dp_p1_lock_data.isBitClear(52) ) { FAPI_ERR("Port 1 DP 4 PLL failed to lock!");}
+                // break;  // Don't break.  Keep going to initialize any channels that might be good.
             }
-            if ( k_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
+            //-------------------------------
+            // 7d - Check Port 0 AD lock bits
+            if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
             {
-                FAPI_ERR("AD32S 0x0C001 PLL failed to lock!   Lock Status = %04X",k_data.getHalfWord(3));
+                FAPI_ERR("One or more AD32S port 0 (0x0C001) PLL failed to lock!   Lock Status = %04X",ad_p0_lock_data.getHalfWord(3));
                 FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK);
                 break;
             }
-            if ( l_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
+            //-------------------------------
+            // 7e - Check Port 1 AD lock bits
+            if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
             {
-                FAPI_ERR("AD32S 0x1C001 PLL failed to lock!   Lock Status = %04X",l_data.getHalfWord(3));
+                FAPI_ERR("One or more AD32S port 1 (0x1C001) PLL failed to lock!   Lock Status = %04X",ad_p1_lock_data.getHalfWord(3));
                 FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK);
                 break;
             }
         }
         else
         {
-            FAPI_INF("DP18 and AD32S PLLs are now locked.");
+            FAPI_INF("AD32S PLLs are now locked.  DP18 PLLs should also be locked.");
         }
-  
-  
-  
+
+
+
         //
-        // 8.Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
+        // 9.Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
         //   This takes the dphy_nclk/SysClk alignment circuit out of reset and puts the dphy_nclk/SysClk alignment circuit into the Continuous Update Mode.
         //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
         //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
@@ -360,7 +453,7 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
         //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
         //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
-        FAPI_DBG("Step 8: Write '8024'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+        FAPI_DBG("Step 9: Write '8024'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
         rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008024ull);
         if (rc_ecmd)
         {
@@ -392,72 +485,75 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
             break;
         }
+
+
+
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-            break;
+            P0_DP0_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-            break;
+            P1_DP0_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-            break;
+            P0_DP1_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-            break;
+            P1_DP1_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-            break;
+            P0_DP2_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-            break;
+            P1_DP2_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-            break;
+            P0_DP3_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-            break;
+            P1_DP3_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-            break;
+            P0_DP4_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-            break;
+            P1_DP4_reg_error = 1;
         }
-  
-  
-  
+
+
+
         //
-        // 9.Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.
-        FAPI_DBG("Step 9: Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.\n");
+        // 10.Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.
+        FAPI_DBG("Step 10: Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.\n");
         rc = fapiDelay(DELAY_100US, DELAY_2000000SIMCYCLES); // wait 2000000 simcycles (in sim mode) OR 100 usec (in hw mode)
         if (rc)
         {
@@ -465,12 +561,12 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             break;
         }
 
-  
-  
+
+
         //
-        // 10.Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset
+        // 11.Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset
         //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
-        FAPI_DBG("Step 10: Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset.\n");
+        FAPI_DBG("Step 11: Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset.\n");
         rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000000ull);
         if (rc_ecmd)
         {
@@ -490,11 +586,11 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register.");
             break;
         }
-  
-  
-  
+
+
+
         //
-        // 11.Write '8020'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
+        // 12.Write '8020'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
         //    This takes the dphy_nclk/SysClk alignment circuit out of Continuous Update Mode.
         //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
         //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
@@ -502,7 +598,7 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
         //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
         //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
-        FAPI_DBG("Step 11: Write '8020'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+        FAPI_DBG("Step 12: Write '8020'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
         rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008020ull);
         if (rc_ecmd)
         {
@@ -534,65 +630,68 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
             break;
         }
+
+
+
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-            break;
+            P0_DP0_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-            break;
+            P1_DP0_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-            break;
+            P0_DP1_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-            break;
+            P1_DP1_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-            break;
+            P0_DP2_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-            break;
+            P1_DP2_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-            break;
+            P0_DP3_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-            break;
+            P1_DP3_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-            break;
+            P0_DP4_reg_error = 1;
         }
         rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
         if (rc)
         {
             FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-            break;
+            P1_DP4_reg_error = 1;
         }
 
 
@@ -607,7 +706,7 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         }
         if (is_simulation)
         {
-            FAPI_DBG("Step 11.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+            FAPI_DBG("Step 12.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
             rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008000ull);
             if (rc_ecmd)
             {
@@ -639,69 +738,72 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
                 FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
                 break;
             }
+
+
+
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-                break;
+                P0_DP0_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-                break;
+                P1_DP0_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-                break;
+                P0_DP1_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-                break;
+                P1_DP1_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-                break;
+                P0_DP2_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-                break;
+                P1_DP2_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-                break;
+                P0_DP3_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-                break;
+                P1_DP3_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-                break;
+                P0_DP4_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-                break;
+                P1_DP4_reg_error = 1;
             }
-    
-    
-            FAPI_DBG("Step 11.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+
+
+            FAPI_DBG("Step 12.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
             rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008080ull);
             if (rc_ecmd)
             {
@@ -733,72 +835,75 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
                 FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
                 break;
             }
+
+
+
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-                break;
+                P0_DP0_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-                break;
+                P1_DP0_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-                break;
+                P0_DP1_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-                break;
+                P1_DP1_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-                break;
+                P0_DP2_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-                break;
+                P1_DP2_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-                break;
+                P0_DP3_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-                break;
+                P1_DP3_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-                break;
+                P0_DP4_reg_error = 1;
             }
             rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
             if (rc)
             {
                 FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-                break;
+                P1_DP4_reg_error = 1;
             }
         }
 
-  
+
         //
-        // 12.Wait at least 32 memory clock cycles.
-        FAPI_DBG("Step 12: Wait at least 32 memory clock cycles.\n");
+        // 13.Wait at least 32 memory clock cycles.
+        FAPI_DBG("Step 13: Wait at least 32 memory clock cycles.\n");
         rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
         if (rc)
         {
@@ -806,17 +911,17 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
             break;
         }
 
-  
-  
+
+
         //
-        // 13.Write 0x0010 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.
+        // 14.Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.
         //    This step takes approximately 2112 (64 * 33) memory clock cycles.
         //                                                (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 13: Write 0x0010 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000010ull);
+        FAPI_DBG("Step 14: Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.\n");
+        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull);
         if (rc_ecmd)
         {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0010 into the PC_IO_PVT_FET_CONTROL registers.",  rc_ecmd);
+            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into the PC_IO_PVT_FET_CONTROL registers.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
@@ -835,12 +940,111 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
 
 
 
+
+
+        //
+        // Now do some error checking and mark bad channels
+        // Check to see if there were any register access problems on DP registers, or corresponding PLLs that did not lock.
+        // If so, mark the DP pairs as bad.
+
+        // Loop through only valid (functional) dimms.
+        // For each valid dimm, loop through all the ranks belonging to that dimm.
+        // If there was either a register access error, or if the PLL did not lock, then mark the DP pair as bad.
+        // Do this by setting the dqBitmap attribute for all dimms and ranks associated with that PLL or register.
+        // Read the dqBitmap first, so that you do not clear values that may already be set.
+        // (Some DP channels may already be marked as bad.)
+
+	// Find out which dimms are functional
+        rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR,	&i_target, valid_dimms);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR");
+            break;
+        }
+        valid_dimm[0][0] = (valid_dimms & 0x80);
+        valid_dimm[0][1] = (valid_dimms & 0x40);
+        valid_dimm[1][0] = (valid_dimms & 0x08);
+        valid_dimm[1][1] = (valid_dimms & 0x04);
+
+        // Find out how many ranks are on each dimm
+        rc = FAPI_ATTR_GET( ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_EFF_NUM_RANKS_PER_DIMM.");
+            break;
+        }
+
+
+        // Loop through each PORT (0,1)
+        for(l_port=0; l_port<1; l_port++ )
+        {
+            // Loop through each DIMM:(0,1)
+            for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ )
+            {
+                if (valid_dimm[l_port][l_dimm])
+                {
+                    // Ok, this DIMM is functional. So loop through the RANKs of this dimm.
+                    for(l_rank=0; l_rank<num_ranks_per_dimm[l_port][l_dimm]; l_rank++ )
+                    {
+                        // Get the bad DQ Bitmap for l_port, l_dimm, l_rank
+                        rc = dimmGetBadDqBitmap(i_target,
+                                                l_port,
+                                                l_dimm,
+                                                l_rank,
+                                                l_dqBitmap);
+                        if (rc)
+                        {
+                            FAPI_ERR("Error from dimmGetBadDqBitmap");
+                            break;
+                        }
+            
+                        // Mark the bad bits for each register that had problems or PLL that did not lock
+                        new_error = 0;
+                        if ( l_port == 0 )
+                        {
+                            if (( P0_DP0_reg_error == 1 ) || ( dp_p0_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = 1; }
+                            if (( P0_DP1_reg_error == 1 ) || ( dp_p0_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = 1; }
+                            if (( P0_DP2_reg_error == 1 ) || ( dp_p0_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = 1; }
+                            if (( P0_DP3_reg_error == 1 ) || ( dp_p0_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = 1; }
+                            if (( P0_DP4_reg_error == 1 ) || ( dp_p0_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = 1; }
+                        } else {
+                            if (( P1_DP0_reg_error == 1 ) || ( dp_p1_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = 1; }
+                            if (( P1_DP1_reg_error == 1 ) || ( dp_p1_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = 1; }
+                            if (( P1_DP2_reg_error == 1 ) || ( dp_p1_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = 1; }
+                            if (( P1_DP3_reg_error == 1 ) || ( dp_p1_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = 1; }
+                            if (( P1_DP4_reg_error == 1 ) || ( dp_p1_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = 1; }
+                        }
+            
+                        // If there are new errors, write back the bad DQ Bitmap for l_port, l_dimm, l_rank
+                        if ( new_error == 1 )
+                        {
+                            rc = dimmSetBadDqBitmap(i_target,
+                                                    l_port,
+                                                    l_dimm,
+                                                    l_rank,
+                                                    l_dqBitmap);
+                            if (rc)
+                            {
+                                FAPI_ERR("Error from dimmPutBadDqBitmap");
+                                break;
+                            }
+                        }
+                    }  // End of loop over RANKs
+                    if (rc) break;    // Go to end of proc if error found inside loop.
+                }
+            }  // End of loop over DIMMs
+            if (rc) break;    // Go to end of proc if error found inside loop.
+        }  // End of loop over PORTs
+
+
     } while(0);
 
     FAPI_INF("********* mss_ddr_phy_reset complete *********");
+
     return rc;
 }
 
+
 // function moved from draminit because we need mclk low not asserted for pll locking
 ReturnCode mss_deassert_force_mclk_low (const Target& i_target)
 { 
@@ -875,6 +1079,25 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: mss_ddr_phy_reset.C,v $
+Revision 1.17  2012/12/03 15:49:27  mfred
+Fixed bug to allow exit from loops in case of error.
+
+Revision 1.16  2012/11/29 23:02:53  mfred
+Fix for ZQ_CAL workaround and support for partial set of dimms.
+
+Revision 1.15  2012/11/16 16:36:20  mfred
+Update code to return an error from mss_slew_cal, if any, unless there is an error from mss_ddr_phy_reset.
+
+Revision 1.14  2012/11/14 23:42:43  mfred
+Call mss_slew_cal after the ddr_phy_reset steps.
+
+Revision 1.13  2012/10/19 20:27:26  mfred
+Added support for sub-partial-good operation when only a subset of DPs are good.
+
+Revision 1.12  2012/09/06 15:01:46  gollub
+
+Calling mss_unmask_ddrphy_errors after mss_ddr_phy_reser_cloned.
+
 Revision 1.11  2012/07/27 16:43:25  bellows
 CQ216395 hardware needs force mclk low in phy reset procedure
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.C
new file mode 100644
index 000000000..940fb703b
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.C
@@ -0,0 +1,1408 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_termination_control.C,v 1.11 2012/12/06 19:16:38 sasethur Exp $
+/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2007
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE :mss_draminit_training_advanced.C
+// *! DESCRIPTION : Tools for centaur procedures
+// *! OWNER NAME : Saravanan Sethuraman          email ID:saravanans@in.ibm.com
+// *! BACKUP NAME: Menlo Wuu	 	         email ID:menlowuu@us.ibm.com
+// #! ADDITIONAL COMMENTS :
+//
+// General purpose funcs
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.11   | sasethur |07-Dec-12| Updated for fw review comments
+//  1.10   | mwuu     |28-Nov-12| Added changes suggested from FW team.
+//  1.9    | mwuu     |20-Nov-12| Changed warning status to not cause error.
+//  1.8    | sasethur |19-Nov-12| Updated for fw review comments
+//  1.7	   | mwuu     |14-Nov-12| Switched some old attributes to new, added
+//  							  Partial good support in slew_cal FN.
+//  1.6    | bellows  |13-Nov-12| SI attribute Updates
+//  1.5    | mwuu     |29-Oct-12| fixed config_drv_imp missed a '&'
+//  1.4    | mwuu     |26-Oct-12| Added mss_slew_cal FN, not 100% complete
+//  1.3    | sasethur |26-Oct-12| Updated FW review comments - fapi::, const fapi:: Target
+//  1.2    | mwuu     |17-Oct-12| Updated return codes to use common error, also
+//                                updates to the slew function
+//  1.1    | sasethur |15-Oct-12| Functions defined & moved from training adv,
+//  							  Menlo upated slew function
+
+// Saravanan - Yet to update DRV_IMP new attribute enum change
+
+// Not supported
+// DDR4, DIMM Types
+//----------------------------------------------------------------------
+//  Includes - FAPI
+//----------------------------------------------------------------------
+
+#include <fapi.H>
+
+//----------------------------------------------------------------------
+//Centaur functions
+//----------------------------------------------------------------------
+#include <mss_termination_control.H>
+#include <cen_scom_addresses.H>
+//#include <mss_draminit_training_advanced.H>
+
+/*------------------------------------------------------------------------------
+ * Function: config_drv_imp()
+ * This function will configure the Driver impedance values to the registers
+ *
+ * Parameters: target: mba;		port: 0, 1
+ * Driver_imp: OHM24 = 24, OHM30 = 30, OHM34 = 34, OHM40 = 40
+ * ---------------------------------------------------------------------------*/
+
+fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_drv_imp_dq_dqs)
+{
+
+    ecmdDataBufferBase data_buffer(64);
+    fapi::ReturnCode rc;
+    fapi::ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    uint8_t enslice_drv = 0xFF;
+    uint8_t enslice_ffedrv = 0xF;
+    uint8_t i = 0;
+
+    //Driver impedance settings are per PORT basis
+
+    if (i_port > 1)
+    {
+	FAPI_ERR("Driver impedance port input(%u) out of bounds", i_port);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+    for(i=0; i< MAX_DRV_IMP; i++)
+    {
+	if (drv_imp_array[i] == i_drv_imp_dq_dqs)
+	{
+	    switch (i)
+	    {
+		case 0:   //40 ohms
+		enslice_drv = 0x3C;
+		enslice_ffedrv =0xF;
+		break;
+		case 1:   //34 ohms
+		enslice_drv = 0x7C;
+		enslice_ffedrv =0xF;
+		break;
+		case 2:  //30 ohms
+		enslice_drv = 0x7E;
+		enslice_ffedrv = 0xF;
+		break;
+		case 3:   //24 ohms
+		enslice_drv = 0xFF;
+		enslice_ffedrv = 0xF;
+		break;
+            }
+	break;
+	}
+    }
+
+    if (i_port == 0)
+    {
+        rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F,
+		    data_buffer); if(rc) return rc;
+	rc_num = data_buffer.insertFromRight(enslice_drv,48,8);
+        rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_0x800004780301143F,
+		    data_buffer); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_0x800008780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_0x80000C780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_0x800010780301143F,
+		    data_buffer); if(rc) return rc;
+       	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_0x800000790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_0x800004790301143F,
+		    data_buffer); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_0x800008790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_0x80000C790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    else    // Port = 1
+    {
+        rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F,
+		    data_buffer); if(rc) return rc;
+	rc_num = data_buffer.insertFromRight(enslice_drv,48,8);
+        rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_0x800104780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_0x800108780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_0x80010C780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_0x800110780301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_0x800100790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_0x800104790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_0x800108790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_0x80010C790301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    return rc;
+}
+
+
+/*------------------------------------------------------------------------------
+ * Function: config_rcv_imp()
+ * This function will configure the Receiver impedance values to the registers
+ *
+ * Parameters: target: mba;		port: 0, 1
+ * receiver_imp:OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48,
+ * OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240
+ * ---------------------------------------------------------------------------*/
+
+fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_rcv_imp_dq_dqs)
+{
+
+    ecmdDataBufferBase data_buffer(64);
+    fapi::ReturnCode rc;
+    fapi::ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    uint8_t enslicepterm = 0xFF;
+    uint8_t enslicepffeterm = 0;
+    uint8_t i = 0;
+
+    if (i_port > 1)
+    {
+	FAPI_ERR("Receiver impedance port input(%u) out of bounds", i_port);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+
+
+    for(i=0; i< MAX_RCV_IMP; i++)
+    {
+	if (rcv_imp_array[i] == i_rcv_imp_dq_dqs)
+	{
+            switch (i)
+   	    {
+ 		case 0:  //120 OHMS
+		enslicepterm = 0x10;
+		enslicepffeterm =0x0;
+		break;
+	        case 1:   //80 OHMS
+		enslicepterm = 0x10;
+		enslicepffeterm =0x2;
+		break;
+	        case 2:   //60 OHMS
+		enslicepterm = 0x18;
+		enslicepffeterm =0x0;
+		break;
+	        case 3:   //48 OHMS
+		enslicepterm = 0x18;
+		enslicepffeterm =0x2;
+		break;
+	        case 4:   //40 OHMS
+		enslicepterm = 0x18;
+		enslicepffeterm =0x6;
+		break;
+	        case 5:   //34 OHMS
+		enslicepterm = 0x38;
+		enslicepffeterm =0x2;
+		break;
+	        case 6:   //30 OHMS
+		enslicepterm = 0x3C;
+		enslicepffeterm =0x0;
+		break;
+	        case 7:   //20 OHMS
+		enslicepterm = 0x7E;
+		enslicepffeterm = 0x0;
+		break;
+  	        case 8:    //15 OHMS
+		enslicepterm = 0xFF;
+		enslicepffeterm = 0x0;
+		break;
+ 	    }
+	break;
+	}
+    }
+
+
+    if (i_port == 0)
+    {
+        rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc_num = data_buffer.insertFromRight(enslicepterm,48,8);
+        rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_drv_imp: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_0x8000047A0301143F,
+		    data_buffer); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_0x8000087A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_0x80000C7A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_0x8000107A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,
+		    data_buffer); if(rc) return rc;
+        rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_0x80000C7B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_0x8000107B0301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    else
+    {
+        rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc_num = data_buffer.insertFromRight(enslicepterm,48,8);
+        rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_drv_imp: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_0x8001007B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_0x8001047B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_0x8001087B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_0x80010C7B0301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_0x8001107B0301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    return rc;
+}
+
+/*------------------------------------------------------------------------------
+ * Function: config_slew_rate()
+ * This function will configure the Slew rate values to the registers
+ *
+ * Parameters: target: mba;		port: 0, 1
+ * i_slew_type: SLEW_TYPE_DATA=0, SLEW_TYPE_ADR_ADDR=1, SLEW_TYPE_ADR_CNTL=2
+ * i_slew_imp: OHM15=15, OHM20=20, OHM24=24, OHM30=30, OHM34=34, OHM40=40
+ *		note: 15, 20, 30, 40 valid for ADR; 24, 30, 34, 40 valid for DATA
+ * i_slew_rate: SLEW_3V_NS=3, SLEW_4V_NS=4, SLEW_5V_NS=5, SLEW_6V_NS=6,
+ * SLEW_MAXV_NS=7 (note SLEW_MAXV_NS bypasses slew calibration.)
+ * ---------------------------------------------------------------------------*/
+fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba,
+	const uint8_t i_port, const uint8_t i_slew_type, const uint8_t i_slew_imp,
+	const uint8_t i_slew_rate)
+{
+    fapi::ReturnCode rc;
+    fapi::ReturnCode rc_buff;
+    ecmdDataBufferBase data_buffer(64);
+    uint32_t rc_num = 0;
+    uint8_t slew_cal_value = 0;
+    uint8_t imp_idx = 255;
+    uint8_t slew_idx = 255;
+    // array for ATTR_MSS_SLEW_RATE_DATA/ADR [2][4][4]
+	// port,imp,slew_rat	cal'd slew settings
+    uint8_t calibrated_slew_rate_table
+		[MAX_NUM_PORTS][MAX_NUM_IMP][MAX_NUM_CAL_SLEW_RATES]={{{0}}};
+
+    if (i_port >= MAX_NUM_PORTS)
+    {
+	FAPI_ERR("Slew port input(%u) out of bounds", i_port);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+
+    if (i_slew_type >= MAX_NUM_SLEW_TYPES)
+    {
+	FAPI_ERR("Slew type input(%u) out of bounds, (>= %u)",
+			i_slew_type, MAX_NUM_SLEW_TYPES);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+
+	switch (i_slew_rate)		// get slew index
+	{
+	case SLEW_MAXV_NS:			// max slew
+		FAPI_INF("Slew rate is set to MAX, using bypass mode");
+		slew_cal_value = 0;		// slew cal value for bypass mode
+		break;
+	case SLEW_6V_NS:
+		slew_idx = 3;
+		break;
+	case SLEW_5V_NS:
+		slew_idx = 2;
+		break;
+	case SLEW_4V_NS:
+		slew_idx = 1;
+		break;
+	case SLEW_3V_NS:
+		slew_idx = 0;
+		break;
+	default:
+		FAPI_ERR("Slew rate input(%u) out of bounds", i_slew_rate);
+		FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+
+    if (i_slew_type == SLEW_TYPE_DATA)
+    {
+		FAPI_INF("Setting data (dq/dqs) slew");
+        switch (i_slew_imp)		// get impedance index for data
+   	    {
+ 		case OHM40:
+			imp_idx = 3;
+			break;
+		case OHM34:
+			imp_idx = 2;
+			break;
+		case OHM30:
+			imp_idx = 1;
+			break;
+		case OHM24:
+			imp_idx = 0;
+			break;
+		default:			// OHM15 || OHM20 not valid for data
+	    	FAPI_ERR("Slew impedance input(%u) invalid "
+			   "or out of bounds, index=%u", i_slew_imp, imp_idx);
+		    FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+	    	return rc;
+		}
+
+	if (i_slew_rate != SLEW_MAXV_NS)
+	{
+		rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba,
+			calibrated_slew_rate_table); if(rc) return rc;
+
+		slew_cal_value =
+			calibrated_slew_rate_table[i_port][imp_idx][slew_idx];
+	}
+
+	FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u",
+			i_port, i_slew_type, imp_idx, slew_idx, slew_cal_value);
+
+	if (slew_cal_value > MAX_SLEW_VALUE)
+	{
+	    FAPI_ERR("!! Slew rate(0x%02x) unsupported, but continuining... !!",
+				slew_cal_value);
+		slew_cal_value = slew_cal_value & 0x0F;
+	}
+
+	if (i_port == 0)	// port dq/dqs slew
+	{
+	    rc = fapiGetScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F,
+			data_buffer); if(rc) return rc;
+
+	    rc_num = rc_num | data_buffer.insertFromRight(slew_cal_value, 56, 4);
+	    if (rc_num)
+	    {
+		FAPI_ERR("Error in setting up DATA slew buffer");
+			rc_buff.setEcmdError(rc_num);
+			return rc_buff;
+	    }
+
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F,
+			data_buffer); if(rc) return rc;
+	    }
+	else	// port 1 dq/dqs slew
+	{
+	    rc = fapiGetScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F,
+			data_buffer); if(rc) return rc;
+
+	    rc_num = rc_num | data_buffer.insertFromRight(slew_cal_value,56,4);
+	    if (rc_num)
+	    {
+		FAPI_ERR( "Error in setting up DATA slew buffer");
+		rc_buff.setEcmdError(rc_num);
+		return rc_buff;
+	    }
+
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F,
+			data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+			DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F,
+			data_buffer); if(rc) return rc;
+	    }
+	}
+    else	// Slew type = ADR
+    {
+	uint8_t adr_pos = 48;	// SLEW_CTL0(48:51) of reg for ADR command slew
+
+	switch (i_slew_type)		// get impedance index for data
+   	{
+ 	case SLEW_TYPE_ADR_ADDR:
+		// CTL0 for command slew (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE)
+	    FAPI_INF("Setting ADR command/address slew in CTL0 register");
+		adr_pos = 48;
+		break;
+ 	case SLEW_TYPE_ADR_CNTL:
+		// CTL1 for control slew (CKE0:1, CKE4:5, ODT0:3, CSN0:3)
+	    FAPI_INF("Setting ADR control slew in CTL1 register");
+		adr_pos = 52;
+		break;
+	case SLEW_TYPE_ADR_CLK:
+		// CTL2 for clock slew (CLK0:3)
+	    FAPI_INF("Setting ADR clock slew in CTL2 register");
+		adr_pos = 56;
+		break;
+ 	case SLEW_TYPE_ADR_SPCKE:
+		// CTL3 for spare clock  slew (CKE2:3)
+	    FAPI_INF("Setting ADR Spare clock in CTL3 register");
+		adr_pos = 60;
+		break;
+	}
+	for(uint8_t i=0; i < MAX_NUM_IMP; i++)	// find ADR imp index
+	{
+	    if (adr_imp_array[i] == i_slew_imp)
+		{
+		    imp_idx = i;
+		    break;
+		}
+	}
+	if ((i_slew_imp == OHM24) || (i_slew_imp == OHM34) ||
+		(imp_idx >= MAX_NUM_IMP))
+	{
+		FAPI_ERR("Slew impedance input(%u) out of bounds", i_slew_imp);
+	    FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+	    return rc;
+	}
+
+	if (i_slew_rate == SLEW_MAXV_NS)
+	{
+		slew_cal_value = 0;
+	}
+	else
+	{
+		rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba,
+			calibrated_slew_rate_table); if(rc) return rc;
+
+	    slew_cal_value =
+			calibrated_slew_rate_table[i_port][imp_idx][slew_idx];
+	}
+	FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u",
+			i_port, i_slew_type, slew_idx, imp_idx, slew_cal_value);
+
+    if (slew_cal_value > MAX_SLEW_VALUE)
+	{
+	    FAPI_ERR("!! Slew rate(0x%02x) unsupported, but continuing... !!",
+				slew_cal_value);
+	    slew_cal_value = slew_cal_value & 0x0F;
+	}
+
+	if (i_port == 0)
+	{
+   	    rc = fapiGetScom(i_target_mba,
+			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F,
+			data_buffer); if(rc) return rc;
+
+	    rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4);
+	    if (rc_num)
+	    {
+	        FAPI_ERR( "Error in setting up ADR slew buffer");
+	        rc_buff.setEcmdError(rc_num);
+	        return rc_buff;
+	    }
+
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F,
+		data_buffer); if(rc) return rc;
+        }
+        else	// port 1 ADR slew
+        {
+   	    rc = fapiGetScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F,
+		data_buffer); if(rc) return rc;
+
+	    rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4);
+	    if (rc_num)
+	    {
+	        FAPI_ERR( "Error in setting up ADR slew buffer");
+	        rc_buff.setEcmdError(rc_num);
+	        return rc_buff;
+	    }
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F,
+		data_buffer); if(rc) return rc;
+	    rc = fapiPutScom(i_target_mba,
+		DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F,
+		data_buffer); if(rc) return rc;
+        }
+    }
+    return rc;
+}
+
+/*------------------------------------------------------------------------------
+ * Function: config_wr_dram_vref()
+ * This function configures PC_VREF_DRV_CONTROL registers to vary the DIMM VREF
+ *
+ * Parameters: target: mba;		port: 0, 1
+ * Wr_dram_vref: VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440,
+ * VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470,
+ * VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500,
+ * VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530,
+ * VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560,
+ * VDD565 = 565, VDD570 = 570, VDD575 = 575
+ * ---------------------------------------------------------------------------*/
+
+fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_wr_dram_vref)
+{
+
+    ecmdDataBufferBase data_buffer(64);
+    fapi::ReturnCode rc, rc_buff;
+    uint32_t rc_num = 0;
+    uint32_t pcvref = 0;
+    uint32_t i = 0;
+
+    // For DDR3 vary from VDD*0.42 to VDD*575
+    // For DDR4 internal voltage is there this function is not required
+    if (i_port > 1)
+    {
+	FAPI_ERR("Write Vref port input(%u) out of bounds", i_port);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+    for(i=0; i< MAX_WR_VREF; i++)
+    {
+	if (wr_vref_array[i] == i_wr_dram_vref)
+	{
+            pcvref = i;
+	    break;
+	}
+    }
+
+    if (i_port == 0)
+    {
+	rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc;
+        rc_num = rc_num | data_buffer.insertFromRight(pcvref,48,5);
+        rc_num = rc_num | data_buffer.insertFromRight(pcvref,53,5);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_wr_vref: Error in setting up buffer ");
+	    rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc;
+    }
+    else
+    {
+	rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc;
+        rc_num = rc_num | data_buffer.insertFromRight(pcvref,48,5);
+        rc_num = rc_num | data_buffer.insertFromRight(pcvref,53,5);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_wr_vref: Error in setting up buffer ");
+	    rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc;
+    }
+    return rc;
+}
+/*------------------------------------------------------------------------------
+ * Function: config_rd_cen_vref()
+ * This function configures read vref registers to vary the CEN VREF
+ *
+ * Parameters: target: mba;		port: 0, 1
+ * Rd_cen_Vref: VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500,
+ * VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375,
+ * VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250,
+ * VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125,
+ * VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000,
+ * VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875,
+ * VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000
+ * DDR3 supports upto 61000
+ * ---------------------------------------------------------------------------*/
+
+fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_rd_cen_vref)
+{
+
+    ecmdDataBufferBase data_buffer(64);
+    fapi::ReturnCode rc, rc_buff;
+    uint32_t rc_num = 0;
+    uint32_t rd_vref = 0;
+
+    if (i_port > 1)
+    {
+	FAPI_ERR("Read vref port input(%u) out of bounds", i_port);
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
+	return rc;
+    }
+    for(uint8_t i=0; i< MAX_RD_VREF; i++)
+    {
+	if (rd_cen_vref_array[i] == i_rd_cen_vref)
+	{
+            rd_vref = i;
+	    break;
+	}
+    }
+
+    if (i_port == 0)
+    {
+	rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,
+		    data_buffer); if(rc) return rc;
+        rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F,
+		    data_buffer); if(rc) return rc;
+    	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    else
+    {
+	rc = fapiGetScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
+		    data_buffer); if(rc) return rc;
+        rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4);
+        if (rc_num)
+        {
+            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
+            rc_buff.setEcmdError(rc_num);
+            return rc_buff;
+        }
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F,
+		    data_buffer); if(rc) return rc;
+	rc = fapiPutScom(i_target_mba,
+		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,
+		    data_buffer); if(rc) return rc;
+    }
+    return rc;
+}
+/*------------------------------------------------------------------------------
+ * Function: mss_slew_cal()
+ * This function runs the slew calibration engine to configure MSS_SLEW_DATA/ADR
+ * attributes and calls config_slew_rate to set the slew rate in the registers.
+ *
+ * Parameters: target: mba;
+ * ---------------------------------------------------------------------------*/
+
+fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
+{
+	fapi::ReturnCode rc;
+    uint32_t rc_ecmd = 0;
+	std::vector<fapi::ReturnCode> vector_rcs;	// to capture rc's on port loop
+    uint32_t poll_count = 0;
+	uint8_t ports_valid = 0;
+	uint8_t is_sim = 0;
+
+	uint8_t freq_idx = 0;		// freq index into lookup table
+	uint32_t ddr_freq = 0;		// current ddr freq
+	uint8_t	ddr_idx = 0;		// ddr type index into lookup table
+	uint8_t ddr_type = 0;		// ATTR_EFF_DRAM_GEN{0=invalid, 1=ddr3, 2=ddr4}
+
+	uint8_t cal_status = 0;
+	// bypass slew (MAX slew rate) not included since it is not calibrated.
+	// for output ATTR_MSS_SLEW_RATE_DATA(0),
+	//            ATTR_MSS_SLEW_RATE_ADR(1), [port=2][imp=4][slew=4]
+	uint8_t calibrated_slew[2][MAX_NUM_PORTS][MAX_NUM_IMP]
+		[MAX_NUM_CAL_SLEW_RATES] = {{{{ 0 }}}};
+
+	fapi::Target l_target_centaur;	// temporary target for parent
+
+	ecmdDataBufferBase ctl_reg(64);
+	ecmdDataBufferBase stat_reg(64);
+
+	// [ddr3/4][dq/adr][speed][impedance][slew_rate]
+	// note: Assumes standard voltage for DDR3(1.35V), DDR4(1.2V),
+	// little endian, if >=128, lab only debug.
+	//
+	// ddr_type(2)	ddr3=0, ddr4=1
+	// data/adr(2)	data(dq/dqs)=0, adr(cmd/cntl)=1
+	// speed(4)		1066=0, 1333=1, 1600=2, 1866=3
+	// imped(4)		24ohms=0, 30ohms=1, 34ohms=2, 40ohms=3 for DQ/DQS
+	// imped(4)		15ohms=0, 20ohms=1, 30ohms=2, 40ohms=3 for ADR driver
+	// slew(3)		3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3
+	const uint8_t slew_table[2][2][4][4][4] = {
+//	NOTE: bit 7 = unsupported slew, and actual value is in bits 4:0
+
+/*	DDR3(0)	*/
+	{ {
+	// dq/dqs(0)
+/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______
+   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
+/*1066*/{{ 12,   9,   7, 134}, { 13,   9,   7, 133}, { 13,  10,   7, 134}, { 14,  10,   7, 132}},
+/*1333*/{{ 15,  11,   8, 135}, { 16,  12,   9, 135}, { 17,  12,   9, 135}, { 17,  12,   8, 133}},
+/*1600*/{{ 18,  13,  10, 136}, { 19,  14,  10, 136}, { 20,  15,  11, 136}, { 21,  14,  10, 134}},
+/*1866*/{{149, 143, 140, 138}, {151, 144, 140, 137}, {151, 145, 141, 138}, {152, 145, 139, 135}}
+	}, {
+	// adr(1),
+/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______
+   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
+/*1066*/{{ 17,  13,  10,   8}, { 13,  11,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}},
+/*1333*/{{ 21,  16,  12,  10}, { 17,  12,   9,   7}, { 15,  10,   6, 132}, {  9,   5, 132, 132}},
+/*1600*/{{ 25,  19,  15,  12}, { 20,  14,  13,   8}, { 19,  12,   7, 133}, { 11,   6, 133, 133}},
+/*1866*/{{157, 150, 145, 142}, {151, 145, 141, 138}, {150, 142, 136, 134}, {141, 134, 134, 134}}
+	} },
+/* DDR4(1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+	{ {
+	// dq/dqs(0)
+/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______
+   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
+/*1066*/{{138, 135, 134, 133}, {139, 136, 134, 132}, {140, 136, 134, 132}, {140, 136, 132, 132}},
+/*1333*/{{139, 137, 135, 134}, {142, 138, 135, 133}, {143, 138, 135, 133}, {143, 138, 133, 132}},
+/*1600*/{{ 15,  11,   9, 135}, { 17,  11,   9, 135}, { 18,  13,   9, 134}, { 18,  11,   6, 133}},
+/*1866*/{{ 18,  13,  10, 137}, { 19,  13,  10, 136}, { 21,  15,  10, 135}, { 21,  13,   8, 134}}
+	}, {
+	// adr(1)
+/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______
+   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
+/*1066*/{{142, 139, 136, 134}, {140, 136, 134, 133}, {138, 134, 131, 131}, {133, 131, 131, 131}},
+/*1333*/{{145, 142, 139, 136}, {143, 138, 135, 134}, {140, 135, 132, 132}, {134, 132, 132, 132}},
+/*1600*/{{ 21,  16,  13,  10}, { 18,  12,   9, 135}, { 15,   8, 133, 133}, {  7, 133, 133, 133}},
+/*1866*/{{ 24,  19,  15,  11}, { 21,  14,  10, 136}, { 17,  10, 134, 134}, {  9, 134, 134, 134}}
+	} }
+	};
+
+	// slew calibration control register
+	const uint64_t slew_cal_cntl[] = {
+		DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F, // port 0
+		DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_0x800180390301143F  // port 1
+	};
+	// slew calibration status registers
+	const uint64_t slew_cal_stat[] = {
+		DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F,
+		DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_0x800180340301143F
+	};
+	const uint8_t ENABLE_BIT = 48;
+	const uint8_t START_BIT = 49;
+	const uint8_t BB_LOCK_BIT = 56;
+	// general purpose 100 ns delay for HW mode  (2000 sim cycles if simclk = 20ghz)
+	const uint16_t	DELAY_100NS		= 100;
+	// normally 2000, but since cal doesn't work in SIM, setting to 1
+	const uint16_t	DELAY_SIMCYCLES	= 1;	
+	const uint8_t	MAX_POLL_LOOPS	= 20;
+
+	// verify which ports are functional
+	rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR,
+			&i_target, ports_valid);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: "
+				"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR");
+		return rc;
+	}
+
+	// Check if in SIM
+	rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION");
+		return rc;
+	}
+	// Get DDR type (DDR3 or DDR4)
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, ddr_type);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_DRAM_GEN");
+		return rc;
+	}
+	// ddr_type(2)	ddr3=0, ddr4=1
+	if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) {	//type=2
+		ddr_idx = 1;
+	} else if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { //type=1
+		ddr_idx = 0;
+	} else {	// EMPTY ?? how to handle?
+		FAPI_ERR("Invalid ATTR_DRAM_DRAM_GEN = %d, %s!", ddr_type,
+				i_target.toEcmdString());
+		FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_DRAM_GEN);
+		return rc;
+	}
+
+	// get freq from parent
+	rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, ddr_freq);
+	if(rc) return rc;
+
+	if (ddr_freq == 0) {
+		FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", ddr_freq,
+				i_target.toEcmdString());
+		FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FREQ);
+		return rc;
+	}
+	// speed(4)		1066=0, 1333=1, 1600=2, 1866=3
+	if (ddr_freq > 1732) {
+		freq_idx= 3;		// for 1866+
+	} else if ((ddr_freq > 1460) && (ddr_freq <= 1732)) {
+		freq_idx = 2;		// for 1600
+	} else if ((ddr_freq > 1200) && (ddr_freq <= 1460)) {
+		freq_idx = 1;		// for 1333
+	} else {		// (ddr_freq <= 1200)
+		freq_idx = 0;		// for 1066-
+	}
+
+	FAPI_INF("Enabling slew calibration engine... dram=DDR%i(%u), freq=%u(%u)",
+			(ddr_type+2), ddr_idx, ddr_freq, freq_idx);
+
+	vector_rcs.clear();		// clear rc vector
+	for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++)
+	{
+		uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port)));
+
+		if (port_val == 0) {
+			FAPI_INF("WARNING:  Port %u is invalid from "
+					"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, 0x%02x",
+					l_port, ports_valid);
+		}
+	//	Step A: Configure ADR registers and MCLK detect (done in ddr_phy_reset)
+	// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
+		rc = fapiGetScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		if (rc)
+		{
+			FAPI_ERR("Error reading DDRPHY_ADR_SLEW_CAL_CNTL register.");
+			//return rc;
+			vector_rcs.push_back(rc);
+			continue;
+		}
+
+		rc_ecmd = ctl_reg.flushTo0();
+		rc_ecmd |= ctl_reg.setBit(ENABLE_BIT);		// set enable (bit49) to 1
+		if (rc_ecmd)
+		{
+			FAPI_ERR("Error setting enable bit in ADR Slew calibration "
+					"control register.");
+			rc.setEcmdError(rc_ecmd);
+			//return rc;
+			vector_rcs.push_back(rc);
+			continue;
+		}
+
+		// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
+		rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		if (rc)
+		{
+			FAPI_ERR("Error enabling slew calibration engine in "
+					"DDRPHY_ADR_SLEW_CAL_CNTL register.");
+			//return rc;
+			vector_rcs.push_back(rc);
+			continue;
+		}
+
+		//---------------------------------------------------------------------/
+		//	Step 1. Check for BB lock.
+		FAPI_INF("Wait for BB lock in status register, bit %u", BB_LOCK_BIT);
+		for (poll_count=0; poll_count < MAX_POLL_LOOPS; poll_count++)
+		{
+			rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES);
+			if (rc) {
+				FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles");
+				//return rc;
+				vector_rcs.push_back(rc);
+				continue;
+			}
+	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
+			rc = fapiGetScom(i_target, slew_cal_stat[l_port], stat_reg);
+			if (rc)
+			{
+				FAPI_ERR("Error reading DDRPHY_ADR_SYSCLK_PR_VALUE_RO register "
+						"for BB_Lock.");
+				//return rc;
+				vector_rcs.push_back(rc);
+				continue;
+			}
+			FAPI_DBG("stat_reg = 0x%04x, count=%i",stat_reg.getHalfWord(3),
+					poll_count);
+
+			if (stat_reg.isBitSet(BB_LOCK_BIT)) break;
+		}
+
+		if (poll_count == MAX_POLL_LOOPS) {
+			FAPI_INF("Timeout on polling BB_Lock, continuing...");
+		}
+
+		//---------------------------------------------------------------------/
+		// Create calibrated slew settings
+		// dq/adr(2)	dq/dqs=0, adr=1
+		// slew(4)		3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3
+		for (uint8_t data_adr=0; data_adr < 2; data_adr++)
+		{
+			for (uint8_t imp=0; imp < MAX_NUM_IMP; imp++)
+			{
+				uint8_t cal_slew;
+
+				for (uint8_t slew=0; slew < MAX_NUM_CAL_SLEW_RATES; slew++)
+				{
+					cal_slew =
+						slew_table[ddr_idx][data_adr][freq_idx][imp][slew];
+
+					// set slew phase rotator from slew_table
+					// slew_table[ddr3/4][dq/adr][freq][impedance][slew_rate]
+					rc_ecmd |= ctl_reg.insertFromRight(cal_slew, 59, 5);
+
+					// Note: must be 2000 nclks+ after setting enable bit
+					rc_ecmd |= ctl_reg.setBit(START_BIT);	// set start bit(48)
+					FAPI_DBG("%s Slew cntl_reg(48:63)=0x%04X, i_slew=%i,0x%02x "
+						"(59:63)", (data_adr ? "ADR" : "DATA"),
+						ctl_reg.getHalfWord(3), cal_slew, cal_slew);
+					if (rc_ecmd)
+					{
+						FAPI_ERR("Error setting start bit or cal input value.");
+						rc.setEcmdError(rc_ecmd);
+						//return rc;
+						vector_rcs.push_back(rc);
+						continue;
+					}
+
+	// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
+					FAPI_INF("Starting slew calibration, ddr_idx=%i, "
+						"data_adr=%i, imp=%i, slewrate=%i", ddr_idx, data_adr,
+						imp, (slew+3));
+					rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+					if (rc)
+					{
+						FAPI_ERR("Error starting slew calibration.");
+						//return rc;
+						vector_rcs.push_back(rc);
+						continue;
+					}
+
+					// poll for calibration status done or timeout...
+					for (poll_count=0; poll_count < MAX_POLL_LOOPS;
+							poll_count++)
+					{
+						FAPI_INF("polling for calibration status, count=%i",
+								poll_count);
+	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
+						rc = fapiGetScom(i_target, slew_cal_stat[l_port],
+								stat_reg);
+						if (rc)
+						{
+							FAPI_ERR("Error reading "
+									"DDRPHY_ADR_SYSCLK_PR_VALUE_RO "
+									"register for calibration status.");
+							//return rc;
+							vector_rcs.push_back(rc);
+							continue;
+						}
+						rc_ecmd = stat_reg.extractToRight(&cal_status, 58, 2);
+						if (rc_ecmd)
+						{
+							FAPI_ERR("Error getting calibration status bits");
+							rc.setEcmdError(rc_ecmd);
+							//return rc;
+							vector_rcs.push_back(rc);
+							continue;
+						}
+						FAPI_DBG("cal_status = %i",cal_status);
+						if (cal_status != 0)
+							break;
+						 // wait (1020 mclks / MAX_POLL_LOOPS)
+						rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES);
+						if(rc)
+						{
+							//return rc;
+							vector_rcs.push_back(rc);
+							continue;
+						}
+					}
+
+					if (cal_status == 3)
+					{
+						FAPI_INF("slew calibration completed successfully");
+
+						cal_slew = cal_slew & 0x80;	// clear bits 6:0
+						rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4);
+						if (rc_ecmd)
+						{
+							FAPI_ERR("Error getting calibration output "
+									"slew value");
+							rc.setEcmdError(rc_ecmd);
+							//return rc;
+							vector_rcs.push_back(rc);
+							continue;
+						}
+						calibrated_slew[data_adr][l_port][imp][slew] = cal_slew;
+					}
+					else if (cal_status == 2)
+					{
+						FAPI_ERR("warning occurred during slew "
+								"calibration, continuing...");
+					}
+					else
+					{
+						if (cal_status == 1)
+						{
+							FAPI_ERR("error occurred during slew calibration");
+						}
+						else
+						{
+							FAPI_ERR("Slew calibration timed out");
+						}
+						FAPI_ERR("Slew calibration failed on %s slew: imp_idx="
+								"%d, slew_idx=%d, slew_table=0x%02X, "
+								"status=0x%04X on %s!",
+								(data_adr ? "ADR" : "DATA"), imp, slew,
+								cal_slew, stat_reg.getHalfWord(3),
+								i_target.toEcmdString());
+						
+						if (is_sim) {
+							// Calibration fails in sim since bb_lock not
+							// possible in cycle simulator, putting initial
+							// to be cal'd value in output table
+							FAPI_INF("In SIM setting calibrated slew array");
+							calibrated_slew[data_adr][l_port][imp][slew] =
+								cal_slew;
+						}
+						else
+						{
+							FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_ERROR);
+							//return rc;
+							vector_rcs.push_back(rc);
+							continue;
+						}
+					} // end error check
+				} // end slew
+			} // end imp
+		} // end data_adr
+
+		// disable calibration engine for port
+		ctl_reg.clearBit(ENABLE_BIT);
+		rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		if (rc)
+		{
+			FAPI_ERR("Error disabling slew calibration engine in "
+					"DDRPHY_ADR_SLEW_CAL_CNTL register.");
+			//return rc;
+			vector_rcs.push_back(rc);
+		}
+	} // end port loop
+
+	if (vector_rcs.size() != 0)
+	{
+		return vector_rcs.front();	// return first RC encountered
+	}
+	FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR");
+	// ATTR_MSS_SLEW_RATE_DATA [2][4][4]	port, imped, slew_rate
+	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target, calibrated_slew[0]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_DATA");
+		return rc;
+	}
+	// ATTR_MSS_SLEW_RATE_ADR [2][4][4]		port, imped, slew_rate
+	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_ADR, &i_target, calibrated_slew[1]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_ADR");
+		return rc;
+	}
+
+/******************************************************************************/
+	uint8_t slew_imp_val [MAX_NUM_SLEW_TYPES][2][MAX_NUM_PORTS]={{{0}}};
+	enum {
+		SLEW = 0,
+		IMP = 1,
+	};
+
+	// Get desired dq/dqs slew rate & impedance from attribute
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target,
+			slew_imp_val[SLEW_TYPE_DATA][SLEW]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_DQ_DQS");
+		return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target,
+			slew_imp_val[SLEW_TYPE_DATA][IMP]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_DQ_DQS");
+		return rc;
+	}
+	// convert enum value to actual ohms.
+	for (uint8_t j=0; j < MAX_NUM_PORTS; j++)
+	{
+		FAPI_INF("DQ_DQS IMP Attribute[%i] = %u", j,
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]);
+		
+		switch (slew_imp_val[SLEW_TYPE_DATA][IMP][j])
+		{
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0:
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=24;
+				break;
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120:
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=30;
+				break;
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120:
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=34;
+				break;
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160:
+			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120:
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=40;
+				break;
+		}
+		FAPI_DBG("switched imp to value of %u",
+				slew_imp_val[SLEW_TYPE_DATA][IMP][j]);
+	}
+	// Get desired ADR control slew rate & impedance from attribute
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_CNTL][SLEW]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CNTL");
+		return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_CNTL][IMP]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_CNTL");
+		return rc;
+	}
+	// Get desired ADR command slew rate & impedance from attribute
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_ADDR][SLEW]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_ADDR");
+		return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_ADDR][IMP]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_ADDR");
+		return rc;
+	}
+	// Get desired ADR clock slew rate & impedance from attribute
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_CLK][SLEW]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CLK");
+		return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_CLK][IMP]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_CLK");
+		return rc;
+	}
+	// Get desired ADR Spare clock slew rate & impedance from attribute
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_SPCKE][SLEW]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_SPCKE");
+		return rc;
+	}
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target,
+			slew_imp_val[SLEW_TYPE_ADR_SPCKE][IMP]);
+	if (rc)
+	{
+		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_SPCKE");
+		return rc;
+	}
+
+	for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++)
+	{
+		//uint8_t ports_mask = 0xF0;  // bits 0:3 = port0, bits 4:7 = port1
+		uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port)));
+
+		if (port_val == 0)
+		{
+			FAPI_INF("WARNING:  Port %u is invalid from "
+					"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, 0x%02x "
+					"skipping configuration of slew rate on this port",
+					l_port, ports_valid);
+			continue;
+		}
+		for (uint8_t slew_type=0; slew_type < MAX_NUM_SLEW_TYPES; slew_type++)
+		{
+			FAPI_DBG("slew_imp_val imp=%u, slew=%u",
+				slew_imp_val[slew_type][IMP][l_port],
+				slew_imp_val[slew_type][SLEW][l_port]);
+
+			config_slew_rate(i_target, l_port, slew_type,
+					slew_imp_val[slew_type][IMP][l_port],
+					slew_imp_val[slew_type][SLEW][l_port]);
+		}
+	}
+	return rc;
+}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.H b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.H
new file mode 100644
index 000000000..68e2b8fea
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.H
@@ -0,0 +1,269 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_termination_control.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_termination_control.H,v 1.9 2012/12/06 19:17:47 sasethur Exp $

+/* File is created by SARAVANAN SETHURAMAN on Thur Sept 28 2011. */

+

+//------------------------------------------------------------------------------

+// *! (C) Copyright International Business Machines Corp. 2007

+// *! All Rights Reserved -- Property of IBM

+// *! *** IBM Confidential ***

+//------------------------------------------------------------------------------

+// *! TITLE :mss_draminit_training_advanced.H

+// *! DESCRIPTION : Tools for centaur procedures

+// *! OWNER NAME :  Saravanan sethuraman    Email ID: saravanans@in.ibm.com

+// *! BACKUP NAME : Menlo Wuu               Email ID: menlowuu@us.ibm.com

+// #! ADDITIONAL COMMENTS :

+//

+// General purpose funcs

+

+//------------------------------------------------------------------------------

+// Don't forget to create CVS comments when you check in your changes!

+//------------------------------------------------------------------------------

+// CHANGE HISTORY:

+//------------------------------------------------------------------------------

+// Version:|  Author:  |  Date:   | Comment:

+//---------|---------- |--------- |---------------------------------------------

+//  1.9    | 07-Dec-12 | sasethur | Updated for fw review comments

+//  1.8	   | 16-Nov-12 | mwuu	  | Added typedef for external call of

+//                                  mss_slew_cal F

+//  1.7	   | 14-Nov-12 | mwuu	  | Changed "l_" variables to "i_" in 

+//  								config_slew_rate FN

+//  1.6	   | 14-Nov-12 | mwuu	  | Fixed revision numbering in comments

+//  1.5    | 14-Nov-12 | mwuu     | Added additional slew rates, and new const

+//  1.4    | 26-Oct-12 | mwuu     | Added additional slew types enums, need to

+//  								change MAX_NUM_SLEW_TYPES when attributes

+//  								updated.

+//  1.3    | 26-Oct-12 | sasethur | Updated FW review comments fapi::,

+//  								const fapi::Target

+//  1.2	   | 17-Oct-12 | mwuu	  | updates to enum and consts

+//  1.1    | 28-Sep-12 | sasethur | First draft

+

+

+#ifndef MSS_TERMINATION_CONTROL_H

+#define MSS_TERMINATION_CONTROL_H

+//----------------------------------------------------------------------

+//  Includes

+//----------------------------------------------------------------------

+#include <fapi.H>

+

+enum {

+	SLEW_TYPE_DATA = 0,

+	SLEW_TYPE_ADR_ADDR = 1,

+	SLEW_TYPE_ADR_CNTL = 2,

+	SLEW_TYPE_ADR_CLK = 3,

+	SLEW_TYPE_ADR_SPCKE = 4,

+

+	OHM15 = 15,

+	OHM20 = 20,

+	OHM24 = 24,

+	OHM30 = 30,

+	OHM34 = 34,

+	OHM40 = 40,

+

+	SLEW_3V_NS = 3,

+	SLEW_4V_NS = 4,

+	SLEW_5V_NS = 5,

+	SLEW_6V_NS = 6,

+	SLEW_MAXV_NS = 7,

+};

+

+const uint8_t MAX_NUM_PORTS = 2;		// max number of ports

+const uint8_t MAX_NUM_SLEW_TYPES = 5;	// data(dq/dqs), adr_cmd, adr_cntl, clk, spcke, used by slew_cal FN only

+const uint8_t MAX_NUM_IMP = 4;		// number of impedances valid per slew type

+

+//Address shmoo is not done as a part of Training advanced, so the order matches

+//attribute enum

+const uint8_t adr_imp_array[] = {

+	15,

+	20,

+	30,

+	40,

+};

+

+// bypass slew (MAX slew rate) not included since it is not calibrated.

+const uint8_t MAX_NUM_CAL_SLEW_RATES = 4 ;	// 3V/ns, 4V/ns, 5V/ns, 6V/n

+const uint8_t MAX_NUM_SLEW_RATES = 4;	// 3V/ns, 4V/ns, 5V/ns, 6V/n, MAX?

+const uint8_t slew_rate_array[] = {

+//    7,

+	6,

+	5,

+	4,

+    3,

+};

+

+const uint8_t MAX_SLEW_VALUE = 15;		// 4 bit value

+const uint8_t MAX_WR_VREF = 32;

+

+const uint32_t wr_vref_array[] = {

+	420,

+	425,

+	430,

+	435,

+	440,

+	445,

+	450,

+	455,

+	460,

+	465,

+	470,

+	475,

+	480,

+	485,

+	490,

+	495,

+	500,

+	505,

+	510,

+	515,

+	520,

+	525,

+	530,

+	535,

+	540,

+	545,

+	550,

+	555,

+	560,

+	565,

+	570,

+	575

+	};

+

+

+//The Array is re-arranged inorder to find the best Eye margin based on the

+//Fitness level - 500 is the best value

+const uint32_t wr_vref_array_fitness[] = {

+	420,

+	425,

+	575,

+	430,

+	570,

+	435,

+	565,

+	440,

+	560,

+	445,

+	555,

+	450,

+	550,

+	455,

+	545,

+	460,

+	540,

+	465,

+	535,

+	470,

+	530,

+	475,

+	525,

+	480,

+	520,

+	485,

+	515,

+	490,

+	510,

+	495,

+	505,

+	500

+	};

+

+const uint8_t MAX_RD_VREF = 16;

+const uint32_t rd_cen_vref_array[] = {

+	40375,

+	41750,

+	43125,

+	44500,

+	45875,

+	47250,

+	48625,

+	50000,

+	51375,

+	52750,

+	54125,

+	55500,

+	56875,

+	58250,

+	59625,

+	61000

+	};

+

+//The Array is re-arranged inorder to find the best Eye margin based on the

+//Fitness level - 50000 is the best value

+const uint32_t rd_cen_vref_array_fitness[] = {

+	61000,

+	59625,

+	40375,

+	58250,

+	41750,

+	56875,

+	43125,

+	55500,

+	44500,

+	54125,

+	45875,

+	52750,

+	47250,

+	51375,

+	48625,

+	50000

+	};

+

+//The Array is re-arranged inorder to find the best Eye margin based on the

+//Fitness level - 24 is the best value

+const uint8_t MAX_DRV_IMP = 4;

+const uint8_t drv_imp_array[] = {

+	40,

+	34,

+	30,

+	24

+	};

+

+//The Array is re-arranged inorder to find the best Eye margin based on the

+//Fitness level - 15 is the best value

+const uint8_t MAX_RCV_IMP = 9;

+const uint8_t rcv_imp_array[] = {

+	120,

+    80,

+    60,

+    48,

+    40,

+    34,

+    30,

+    20,

+    15

+    };

+

+typedef fapi::ReturnCode (*mss_slew_cal_FP_t)(const fapi::Target & i_target_mba);

+

+extern "C"

+{

+fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t l_wr_vref);

+fapi::ReturnCode config_rd_cen_vref(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t l_rd_cen_vref);

+fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t l_drv_imp_dq_dqs);

+fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t l_rcv_imp_dq_dqs);

+fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba,

+	const uint8_t i_port, const uint8_t l_slew_type, const uint8_t l_slew_imp,

+	const uint8_t l_slew_rate);

+fapi::ReturnCode mss_slew_cal(const fapi::Target & i_target_mba);

+} // extern C

+#endif

diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 718a52bad..f01d83112 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_draminit.C,v 1.35 2012/07/27 16:44:38 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $  */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_draminit.C,v 1.43 2012/12/07 13:44:07 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -29,6 +28,14 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.43   | bellows  | 12/06/12| Fixed Review Comment
+//  1.42   | jdsloat  | 12/02/12| SHADOW REG PRINT OUT FIX
+//  1.41   | jdsloat  | 11/19/12| RCD Bit order fix.
+//  1.40   | jdsloat  | 11/17/12| MPR operation bit (MRS3, ADDR2) fix
+//  1.39   | gollub   | 9/05/12 | Calling mss_unmask_draminit_errors after mss_draminit_cloned
+//  1.38   | jdsloat  | 8/29/12 | Fixed Shadow Regs with Regression
+//  1.37   | jdsloat  | 8/28/12 | Revert back to 1.35.
+//  1.36   | jdsloat  | 7/25/12 | Printing out contents of MRS shadow registers.
 //  1.35   | bellows  | 7/25/12 | CQ 216395 (move force mclk low deassert to phyreset, resetn toggle)
 //  1.34   | bellows  | 7/16/12 | added in Id tag
 //  1.33   | jdsloat  | 6/26/12 | Added rtt_nom rank by rank value.
@@ -82,16 +89,19 @@
 //----------------------------------------------------------------------
 #include <mss_funcs.H>
 #include "cen_scom_addresses.H"
+#include <mss_unmask_errors.H>
 
 //----------------------------------------------------------------------
 //  Constants
 //----------------------------------------------------------------------
 const uint8_t MAX_NUM_DIMMS = 2;
-const uint8_t MAX_NUM_PORTS = 2; 
+const uint8_t MAX_NUM_PORTS = 2;
+const uint8_t MAX_NUM_RANK_PAIR = 4;
 const uint8_t MRS0_BA = 0;
 const uint8_t MRS1_BA = 1;
 const uint8_t MRS2_BA = 2;
 const uint8_t MRS3_BA = 3;
+const uint8_t INVALID = 255;
 
 
 extern "C" {
@@ -103,6 +113,7 @@ ReturnCode mss_mrs_load( Target& i_target, uint32_t i_port_number, uint32_t& io_
 ReturnCode mss_assert_resetn_drive_mem_clks( Target& i_target);
 ReturnCode mss_deassert_force_mclk_low( Target& i_target);
 ReturnCode mss_assert_resetn ( Target& i_target, uint8_t value);
+ReturnCode mss_draminit_cloned(Target& i_target);
 
 const uint64_t  DELAY_100NS             = 100;      // general purpose 100 ns delay for HW mode   (2000 sim cycles if simclk = 20ghz)
 const uint64_t  DELAY_1US               = 1000;     // general purpose 1 usec delay for HW mode   (20000 sim cycles if simclk = 20ghz)
@@ -114,13 +125,54 @@ const uint64_t  DELAY_2000000SIMCYCLES  = 2000000;  // general purpose 2000000 s
 ReturnCode mss_draminit(Target& i_target)
 {
     // Target is centaur.mba
+    
+    ReturnCode rc;
+    
+    rc = mss_draminit_cloned(i_target);
+    
+	// If mss_unmask_draminit_errors gets it's own bad rc,
+	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
+	// Else if mss_unmask_draminit_errors runs clean, 
+	// it will just return the passed in rc.
+	rc = mss_unmask_draminit_errors(i_target, rc);
+
+	return rc;
+}
+
+ReturnCode mss_draminit_cloned(Target& i_target)
+{
+    // Target is centaur.mba
     //
 
     ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
     uint32_t port_number;
     uint32_t ccs_inst_cnt = 0;
     uint8_t dram_gen; 
-    uint8_t dimm_type; 
+    uint8_t dimm_type;
+    uint8_t rank_pair_group = 0;
+    ecmdDataBufferBase data_buffer_64(64);
+    ecmdDataBufferBase mrs0(16); 
+    ecmdDataBufferBase mrs1(16);
+    ecmdDataBufferBase mrs2(16);
+    ecmdDataBufferBase mrs3(16);
+    uint16_t MRS0 = 0;
+    uint16_t MRS1 = 0;
+    uint16_t MRS2 = 0;
+    uint16_t MRS3 = 0;
+    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
+ 
+    //populate primary_ranks_arrays_array
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
+    if(rc) return rc;
+
 
     rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
     if(rc) return rc;
@@ -214,6 +266,248 @@ ReturnCode mss_draminit(Target& i_target)
             FAPI_INF("No Memory configured.");
         }
 
+        // Cycle through Ports...
+        // Ports 0-1
+        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
+        {
+
+	for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++)
+	{
+	//Check if rank group exists
+	    if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID))
+	    {
+
+		if (port_number == 0){
+	    		// Get contents of MRS Shadow Regs and Print it to output
+			if (rank_pair_group == 0)
+			{
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, data_buffer_64);
+                                if(rc) return rc;
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0 );
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+
+			}
+			else if (rank_pair_group == 1)
+			{
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+
+			}
+			else if (rank_pair_group == 2)
+			{
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+			}
+			else if (rank_pair_group == 3)
+			{
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3);
+			}
+		}
+		else if (port_number == 1)
+		{
+			if (rank_pair_group == 0)
+			{
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0 );
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+
+			}
+			else if (rank_pair_group == 1)
+			{
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		    		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64);
+		    		rc_num = rc_num | data_buffer_64.reverse();
+		    		rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		    		rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		    		FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+
+			}
+			else if (rank_pair_group == 2)
+		        {
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS3);
+			}
+			else if (rank_pair_group == 3)
+			{
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS0);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS1);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  port_number, rank_pair_group, MRS2);
+
+		   	       rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64);
+		   	       rc_num = rc_num | data_buffer_64.reverse();
+		   	       rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
+		   	       rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
+		   	       FAPI_INF( "PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", port_number, rank_pair_group, MRS3);
+			}
+
+		}
+		}
+	    }
+	}
+
+	if (rc_num)
+	{
+	    FAPI_ERR( "mss_draminit: Error setting up buffers");
+	    rc_buff.setEcmdError(rc_num);
+	    return rc_buff;
+	}
+
 
         // TODO:
         // This is Commented out because RCD Parity Check has not been written yet.
@@ -423,10 +717,10 @@ ReturnCode mss_rcd_load(
                 rc_num = rc_num | bank_3.insert(rcd_number, 2, 1, 28);
 
                 //control word values RCD0 = A3, RCD1 = A4, RCD2 = BA0, RCD3 = BA1
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 0);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 1);
-                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 2);
-                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 3);
+                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 3);
+                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 2);
+                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 1);
+                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 0);
 
                 // Send out to the CCS array 
                 rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
@@ -482,6 +776,8 @@ ReturnCode mss_mrs_load(
     ReturnCode rc_buff;
     uint32_t rc_num = 0;
 
+    ecmdDataBufferBase data_buffer_64(64);
+
     ecmdDataBufferBase address_16(16);
     ecmdDataBufferBase bank_3(3);
     ecmdDataBufferBase activate_1(1);
@@ -795,11 +1091,11 @@ ReturnCode mss_mrs_load(
 
     if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
     {
-        mpr_op = 0x00;
+        mpr_op = 0xFF;
     }
     else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
     {
-        mpr_op = 0xFF;
+        mpr_op = 0x00;
     }
 
     // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
@@ -1030,6 +1326,7 @@ ReturnCode mss_mrs_load(
             }
         }
     }
+
     return rc;
 }
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index f08e71da8..e1d9537bc 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_draminit_mc.C,v 1.24 2012/07/17 13:23:51 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_draminit_mc.C,v 1.26 2012/09/11 14:35:22 jdsloat Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -45,6 +44,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.25   | jdsloat  |11-SEP-12| Changed Periodic Cal to Execute via MBA regs depending upon the ZQ Cal and MEM Cal timer values; 0 = disabled
 //  1.24   | bellows  |16-JUL-12| added in Id tag
 //  1.22   | bellows  |13-JUL-12| Fixed periodic cal bit 61 being set. HW214829
 //  1.20   | jdsloat  |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile
@@ -213,85 +213,54 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
     ecmdDataBufferBase mba01_data_buffer_64_p0(64);
     ecmdDataBufferBase mba01_data_buffer_64_p1(64);
 
-    //Determine whether or not we want to do a particular type of calibration on the given ranks
-    //ALL CALS CURRENTLY SET AS ON, ONLY CHECK RANK PAIRS PRESENT
-    //***mba01 Setup
-    rc_num = rc_num | mba01_data_buffer_64_p0.flushTo0();
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0);
-    if(rc) return rc;
-
-    rc_num = rc_num | mba01_data_buffer_64_p1.flushTo0();
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1);
-    if(rc) return rc;
+    ecmdDataBufferBase data_buffer_64(64);
 
-    uint8_t primary_rank_group0_array[2]; //[rank]
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_rank_group0_array);
+    uint32_t memcal_iterval; //  00 = Disable
+    rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_iterval);
     if(rc) return rc;
 
-    uint8_t primary_rank_group1_array[2]; //[rank]
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_rank_group1_array);
+    uint32_t zq_cal_iterval; //  00 = Disable
+    rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zq_cal_iterval);
     if(rc) return rc;
 
-    uint8_t primary_rank_group2_array[2]; //[rank]
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_rank_group2_array);
+    rc_num = rc_num | data_buffer_64.flushTo0();
+    rc = fapiGetScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
     if(rc) return rc;
 
-    uint8_t primary_rank_group3_array[2]; //[rank]
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_rank_group3_array);
-    if(rc) return rc;
+    FAPI_INF("+++ Enabling Periodic Calibration +++");
 
-    if(primary_rank_group0_array[0] != 255)
+    if (zq_cal_iterval != 0)
     {
-       //Rank Group 0 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(48);
+        //ZQ Cal Enabled
+	rc_num = rc_num | data_buffer_64.setBit(0);
+	FAPI_INF("+++ Periodic Calibration: ZQ Cal Enabled p0+++");
     }
-    if(primary_rank_group1_array[0] != 255)
+    else
     {
-       //Rank Group 1 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(49);
+        //ZQ Cal Disabled
+	rc_num = rc_num | data_buffer_64.clearBit(0);
+	FAPI_INF("+++ Periodic Calibration: ZQ Cal Disabled p0+++");
     }
-    if(primary_rank_group2_array[0] != 255)
-    {
-       //Rank Group 2 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(50);
-    }
-    if(primary_rank_group3_array[0] != 255)
-    {
-       //Rank Group 3 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(51);
-    }
-    if(primary_rank_group0_array[1] != 255)
-    {
-       //Rank Group 0 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(48);
-    }
-    if(primary_rank_group1_array[1] != 255)
-    {
-       //Rank Group 1 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(49);
-    }
-    if(primary_rank_group2_array[1] != 255)
+
+    rc = fapiPutScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
+    if(rc) return rc;
+
+    rc_num = rc_num | data_buffer_64.flushTo0();
+    rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
+    if (memcal_iterval != 0)
     {
-       //Rank Group 2 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(50);
+        //Mem Cal Enabled
+	rc_num = rc_num | data_buffer_64.setBit(0);
+	FAPI_INF("+++ Periodic Calibration: Mem Cal Enabled p0+++");
     }
-    if(primary_rank_group3_array[1] != 255)
+    else
     {
-       //Rank Group 3 Enabled
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(51);
+        //Mem Cal Disabled
+	rc_num = rc_num | data_buffer_64.clearBit(0);
+	FAPI_INF("+++ Periodic Calibration: Mem Cal Disabled p0+++");
     }
-
-    //Start the periodic Cal
-    // do not set bit 61 - HW214829
-    // rc_num = rc_num | mba01_data_buffer_64_p1.setBit(61);
-
-    //Write the mba_p01_PER_CAL_CFG_REG
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0);
-    if(rc) return rc;
-    FAPI_INF("+++ Periodic Calibration Enabled p0+++");
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1);
+    rc = fapiPutScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
     if(rc) return rc;
-    FAPI_INF("+++ Periodic Calibration Enabled p1+++");
 
     if (rc_num)
     {
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 59ef4df63..6c1e965fa 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_draminit_training.C,v 1.29 2012/07/17 13:23:56 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_draminit_training.C,v 1.43 2012/12/07 13:46:10 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -29,6 +28,21 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.42   | bellows  |06-DEC-12| Fixed up review comments
+//  1.41   | jdsloat  |02-DEC-12| Fixed RTT_NOM swap for Port 1
+//  1.40   | jdsloat  |30-NOV-12| Temporarily comment Bad Bit Mask.
+//  1.39   | jdsloat  |18-NOV-12| Fixed CAL_STEP to allow Zq Cal.
+//  1.38   | jdsloat  |16-NOV-12| Fixed Error Place holder and port addressing with BBM
+//  1.37   | jdsloat  |12-NOV-12| Fixed a bracket typo.
+//  1.36   | jdsloat  |07-NOV-12| Changed procedure to proceed through ALL rank_pair, Ports before reporting
+//         |          |         | error status for partial good support. Added Bad Bit Mask to disable regs function
+//         |          |         | and disable regs to Bad Bit Mask function.
+//  1.35   | jdsloat  |08-OCT-12| Changed Write to Read,Modify,Write of Phy Init Cal Config Reg
+//  1.34   | jdsloat  |25-SEP-12| Bit 0 of Cal Step Attribute now offers an all at once option - bit 0 =1 if stepbystep
+//  1.33   | jdsloat  |07-SEP-12| Broke init_cal down to step by step keyed off of CAL_STEP_ENABLE attribute
+//  1.32   | jdsloat  |29-AUG-12| Fixed mss_rtt_nom_rtt_wr_swap and verified with regression
+//  1.31   | bellows  |28-AUG-12| Revert back to 1.29 until regression pass again
+//  1.30   | jdsloat  |23-AUG-12| Added mss_rtt_nom_rtt_wr_swap pre and post init_cal
 //  1.29   | bellows  |16-Jul-12| bellows | added in Id tag
 //  1.28   | bellows  |02-May-12| cal ranks are 4 bits, this needed to be adjusted
 //  1.26   | asaetow  |12-Apr-12| Added "if(rc) return rc;" at line 180.
@@ -77,12 +91,6 @@
 //  1.2    | jdsloat  |14-Jul-11| Proper call name fix
 //  1.1    | jdsloat  |22-Apr-11| Initial draft
 
-//TODO:
-//Enable appropriate init cal steps in PC Initial Calibration Config0 based on CAL_STEP attribute 
-//Add error path when Cal fails 
-//Enable complex training procedure based on DIMM_TYPE
-//Check BAD BYTE attribute with DISABLE DP18
-//Figure out DISABLE DP18 mapping for each physical byte. 
 
 //----------------------------------------------------------------------
 //  FAPI function Includes
@@ -95,9 +103,34 @@
 //----------------------------------------------------------------------
 #include <cen_scom_addresses.H>
 #include <mss_funcs.H>
+#include <dimmBadDqBitmapFuncs.H>
 
 //------------End My Includes-------------------------------------------
 
+//----------------------------------------------------------------------
+//  Constants
+//----------------------------------------------------------------------
+const uint8_t MRS1_BA = 1;
+const uint8_t MRS2_BA = 2;
+
+#define MAX_PORTS 2
+#define MAX_PRI_RANKS 4
+#define TOTAL_BYTES 10
+#define BITS_PER_REG 16
+#define DP18_INSTANCES 5
+#define BITS_PER_PORT (BITS_PER_REG*DP18_INSTANCES)
+
+//----------------------------------------------------------------------
+//  Enums
+//----------------------------------------------------------------------
+
+enum mss_draminit_training_result
+{
+    MSS_INIT_CAL_COMPLETE = 1,
+    MSS_INIT_CAL_PASS = 2,
+    MSS_INIT_CAL_STALL = 3,
+    MSS_INIT_CAL_FAIL = 4
+};
 
 
 extern "C" {
@@ -105,7 +138,13 @@ extern "C" {
 using namespace fapi;
 
 ReturnCode mss_draminit_training(Target& i_target);
-ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group);
+ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group,  mss_draminit_training_result& io_status);
+ReturnCode mss_check_error_status(Target& i_target, uint8_t i_port, uint8_t i_group,  mss_draminit_training_result& io_status);
+ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt);
+ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg);
+ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg);
+ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target);
+ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target);
 
 ReturnCode mss_draminit_training(Target& i_target)
 {
@@ -116,10 +155,12 @@ ReturnCode mss_draminit_training(Target& i_target)
        MAX_NUM_PORT = 2,
        MAX_NUM_DIMM = 2,
        MAX_NUM_GROUP = 4,
+       MAX_CAL_STEPS = 7, //read course and write course will occur at the sametime
        INVALID = 255
     };
+
     const uint32_t NUM_POLL = 100;
- 
+
     ReturnCode rc;
     uint32_t rc_num = 0;
 
@@ -167,6 +208,22 @@ ReturnCode mss_draminit_training(Target& i_target)
     rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo1();
 
     ecmdDataBufferBase data_buffer_64(64);
+
+    //TEMP MBA CAL REGS bit 12 = 0
+    rc = fapiGetScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
+    if(rc) return rc;
+    rc_num = rc_num | data_buffer_64.clearBit(12);
+    FAPI_INF("+++ TEMP setting bit 12 to 0+++");
+    rc = fapiPutScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
+    if(rc) return rc;
+
+    rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
+    if(rc) return rc;
+    rc_num = rc_num | data_buffer_64.clearBit(12);
+    FAPI_INF("+++ TEMP setting bit 12 to 0+++");
+    rc = fapiPutScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
+    if(rc) return rc;
+
     if(rc_num)
     {
         rc.setEcmdError(rc_num);
@@ -175,10 +232,17 @@ ReturnCode mss_draminit_training(Target& i_target)
 
     uint8_t port = 0;
     uint8_t group = 0;
-
     uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
+    uint8_t cal_steps = 0;
+    uint8_t cur_cal_step = 0;
+    ecmdDataBufferBase cal_steps_8(8);
+    
+    enum mss_draminit_training_result cur_complete_status = MSS_INIT_CAL_COMPLETE;
+    enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS;
+
+    enum mss_draminit_training_result complete_status = MSS_INIT_CAL_COMPLETE;
+    enum mss_draminit_training_result error_status = MSS_INIT_CAL_PASS;
 
- 
     //populate primary_ranks_arrays_array
     rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
     if(rc) return rc;
@@ -189,9 +253,15 @@ ReturnCode mss_draminit_training(Target& i_target)
     rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
     if(rc) return rc;
 
+    //Get which training steps we are to run
+    rc = FAPI_ATTR_GET(ATTR_MSS_CAL_STEP_ENABLE, &i_target, cal_steps);
+    if(rc) return rc;
+    rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0);
+
     //Set up CCS Mode Reg for Init cal
     rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
     if(rc) return rc;
+
     rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0);
     rc_num = rc_num | data_buffer_64.insert(cal_timeout_cnt_buffer_16, 8, 16, 0);
     rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0);
@@ -201,114 +271,330 @@ ReturnCode mss_draminit_training(Target& i_target)
         rc.setEcmdError(rc_num);
         return rc;
     }
+
     rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
     if(rc) return rc;
 
-    for(port = 0; port < MAX_NUM_PORT; port++)
+
+    //rc = mss_set_bbm_regs (i_target);
+    //if(rc)
+    //{
+	//FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting.");
+	//return rc;
+    //}
+
+    if ( ( cal_steps_8.isBitSet(0) ) ||
+	 ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) &&
+	   (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) &&
+	   (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
+	   (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ))
     {
-        rc = mss_execute_zq_cal(i_target, port);
-        if(rc) return rc;
+	FAPI_INF( "Performing External ZQ Calibration.");
+
+        //Execute ZQ_CAL
+	for(port = 0; port < MAX_NUM_PORT; port++)
+	{
+	    rc = mss_execute_zq_cal(i_target, port);
+	    if(rc) return rc;
+	}
+
     }
 
-    //Set up for Init Cal - Done per port pair
-    rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX
-    rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1
-    rc_num = rc_num | casn_buffer_1.flushTo1();
-    rc_num = rc_num | rasn_buffer_1.flushTo1();
-    rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal
-    if(rc_num)
+    for(port = 0; port < MAX_NUM_PORT; port++)
     {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
 
-    for(group = 0; group < MAX_NUM_GROUP; group++)
-    {
-        if((primary_ranks_array[group][0] != INVALID) || (primary_ranks_array[group][1] != INVALID))
-        {  
-            //Check if rank group exists
-            FAPI_INF( "+++++++++++++++ Sending init cal on rank group: %d +++++++++++++++", group);
-            rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, 0);
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-            FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0],
-                      group, primary_ranks_array[group][1]);
-            if(primary_ranks_array[group][0] == INVALID)
-            {
-                rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][1], 0, 4, 4); // 8 bit storage, need last 4 bits
-            }
-            else
-            {
-                rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][0], 0, 4, 4); // 8 bit storage, need last 4 bits
-            }
-            rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_4, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-            FAPI_INF( "+++++++++++++++ Execute CCS array +++++++++++++++");
-            rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-            for(port = 0; port < 2; port++)
-            {
-                rc = mss_check_cal_status(i_target, port, group);
+	for(group = 0; group < MAX_NUM_GROUP; group++)
+	{
+
+	    //Check if rank group exists
+	    if(primary_ranks_array[group][port] != INVALID)
+	    {
+
+	        // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM
+		rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
                 if(rc) return rc;
-            }
-        }
+
+
+	        //Set up for Init Cal - Done per port pair
+		rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX
+		rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1
+		rc_num = rc_num | casn_buffer_1.flushTo1();
+		rc_num = rc_num | rasn_buffer_1.flushTo1();
+		rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal
+
+		FAPI_INF( "+++++++++++++++ Sending init cal on rank group: %d cal_steps: 0x%02X +++++++++++++++", group, cal_steps);
+
+		for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps
+		{
+		    //Setup the Config Reg bit for the only cal step we want
+		    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
+		    if(rc) return rc;
+
+		    rc_num = rc_num | data_buffer_64.clearBit(48);
+		    rc_num = rc_num | data_buffer_64.clearBit(50);
+		    rc_num = rc_num | data_buffer_64.clearBit(51);
+		    rc_num = rc_num | data_buffer_64.clearBit(52);
+		    rc_num = rc_num | data_buffer_64.clearBit(53);
+		    rc_num = rc_num | data_buffer_64.clearBit(54);
+		    rc_num = rc_num | data_buffer_64.clearBit(55);
+
+		    if ( (cur_cal_step == 1) && (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) &&
+			 (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) &&
+			 (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
+			 (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )
+		    {
+			FAPI_INF( "+++++ Sending ALL Cal Steps at the same time on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(48);
+			rc_num = rc_num | data_buffer_64.setBit(50);
+			rc_num = rc_num | data_buffer_64.setBit(51);
+			rc_num = rc_num | data_buffer_64.setBit(52);
+			rc_num = rc_num | data_buffer_64.setBit(53);
+			rc_num = rc_num | data_buffer_64.setBit(54);
+			rc_num = rc_num | data_buffer_64.setBit(55);
+		    }
+		    else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) )
+		    {
+			FAPI_INF( "+++++ Sending Write Leveling (WR_LVL) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(48);
+		    }
+		    else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) )
+		    {
+			FAPI_INF( "+++++ Sending DQS Align (DQS_ALIGN) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(50);
+		    }
+		    else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) )
+		    {
+			FAPI_INF( "+++++ Sending RD CLK Align (RDCLK_ALIGN) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(51);
+		    }
+		    else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) )
+		    {
+			FAPI_INF( "+++++ Sending Read Centering (READ_CTR) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(52);
+		    }
+		    else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) )
+		    {
+			FAPI_INF( "+++++ Sending Write Centering (WRITE_CTR) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(53);
+		    }
+		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) )
+		    {
+			FAPI_INF( "+++++ Sending Initial Course Write (COURSE_WR) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(54);
+		    }
+		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) )
+		    {
+			FAPI_INF( "+++++ Sending Course Read (COURSE_RD) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(55);
+		    }
+		    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) )
+		    {
+			FAPI_INF( "+++++ Sending Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) on rank group: %d +++++", group);
+			rc_num = rc_num | data_buffer_64.setBit(54);
+			rc_num = rc_num | data_buffer_64.setBit(55);
+		    }
+
+		    if(rc_num)
+		    {
+			rc.setEcmdError(rc_num);
+			return rc;
+		    }
+
+		    if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step
+		    {
+
+		        //Set the config register
+			if(port == 0)
+			{
+			    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
+			    if(rc) return rc;
+			}
+			else
+			{
+			    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
+			    if(rc) return rc;
+			}
+
+			rc = mss_ccs_inst_arry_0(i_target,
+						 instruction_number,
+						 address_buffer_16,
+						 bank_buffer_8,
+						 activate_buffer_1,
+						 rasn_buffer_1,
+						 casn_buffer_1,
+						 wen_buffer_1,
+						 cke_buffer_8,
+						 csn_buffer_8,
+						 odt_buffer_8,
+						 test_buffer_4,
+						 port);
+
+			if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
+
+			FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], group, primary_ranks_array[group][1]);
+
+
+			rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][port], 0, 4, 4); // 8 bit storage, need last 4 bits
+
+			rc = mss_ccs_inst_arry_1(i_target,
+						 instruction_number,
+						 num_idles_buffer_16,
+						 num_repeat_buffer_16,
+						 data_buffer_20,
+						 read_compare_buffer_1,
+						 rank_cal_buffer_4,
+						 ddr_cal_enable_buffer_1,
+						 ccs_end_buffer_1);
+
+			if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
+
+			FAPI_INF( "+++++++++++++++ Execute CCS array +++++++++++++++");
+
+			rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
+			if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
+
+			//Check to see if the training completes
+			rc = mss_check_cal_status(i_target, port, group, cur_complete_status);
+			if(rc) return rc;
+
+			if (cur_complete_status == MSS_INIT_CAL_STALL)
+			{
+			    complete_status = cur_complete_status;
+			}
+
+			//Check to see if the training errored out
+			rc = mss_check_error_status(i_target, port, group, cur_error_status);
+			if(rc) return rc;
+
+			if (cur_error_status == MSS_INIT_CAL_FAIL)
+			{
+			    error_status = cur_error_status;
+			}
+
+		    }
+		}//end of step loop
+
+	        // Change the RTT_NOM to RTT_WR, RTT_WR to RTT_NOM
+		rc = mss_rtt_nom_rtt_wr_swap(i_target, port, primary_ranks_array[group][port], group, instruction_number);
+	    }
+	}//end of group loop
+    }//end of port loop
+
+    if(rc) return rc;
+    //rc = mss_get_bbm_regs(i_target);
+    //if(rc)
+    //{
+	//FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting.");
+	//return rc;
+    //}
+
+    if (complete_status == MSS_INIT_CAL_STALL)
+    {
+	FAPI_ERR( "+++++++++++++++ Calibration on stalled! +++++++++++++++"); 
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED);
     }
+    else if (error_status == MSS_INIT_CAL_FAIL)
+    {
+	FAPI_ERR( "+++++++++++++++ Calibration on failed! +++++++++++++++");
+	FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED);
+    }
+
     return rc; 
 }
-ReturnCode mss_check_cal_status(
-                                Target& i_target, 
-                                uint8_t i_port,
-                                uint8_t i_group
-                               )    {
+
+ReturnCode mss_check_cal_status( Target& i_target, 
+                                 uint8_t i_port,
+                                 uint8_t i_group,
+				 mss_draminit_training_result& io_status
+                               )
+{
     ecmdDataBufferBase cal_status_buffer_64(64);
-    ecmdDataBufferBase cal_error_buffer_64(64);
+
     uint8_t cal_status_reg_offset = 0;
-    uint8_t cal_error_reg_offset = 0;
     cal_status_reg_offset = 48 + i_group;  
-    cal_error_reg_offset = 60 + i_group;
+
     uint8_t poll_count = 1;
 
     ReturnCode rc;
 
     FAPI_INF( "+++++++++++++++ Check Cal Status on port: %d rank group: %d +++++++++++++++", i_port, i_group);
+
     if(i_port == 0)
     {
         rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64);
         if(rc) return rc;
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64);
-        if(rc) return rc;
     }
     else
     {
         rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64);
         if(rc) return rc;
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64);
-        if(rc) return rc;
     }
-    while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && (!cal_error_buffer_64.isBitSet(cal_error_reg_offset)) && (poll_count <= 20))
+
+    while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) &&
+          (poll_count <= 20))
     {
         FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++++++++++++++", i_port, i_group, poll_count);
+
         poll_count++;
         if(i_port == 0)
         {
             rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64);
             if(rc) return rc;
-            rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64);
-            if(rc) return rc;
         }
         else
         {
             rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64);
             if(rc) return rc;
-            rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64);
-            if(rc) return rc;
         }
+
+    }
+
+    if(cal_status_buffer_64.isBitSet(cal_status_reg_offset))
+    {
+	FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d Completed! +++++++++++++++", i_port, i_group);
+	io_status = MSS_INIT_CAL_COMPLETE;
+    }
+    else
+    {
+	FAPI_ERR( "+++++++++++++++ Calibration on port: %d rank group: %d has stalled! +++++++++++++++", i_port, i_group);
+	io_status = MSS_INIT_CAL_STALL;
     }
+
+    return rc;
+}
+
+ReturnCode mss_check_error_status( Target& i_target, 
+                                 uint8_t i_port,
+                                 uint8_t i_group,
+				  mss_draminit_training_result& io_status
+                               )
+{
+
+    ecmdDataBufferBase cal_error_buffer_64(64);
+
+    uint8_t cal_error_reg_offset = 0;
+    cal_error_reg_offset = 60 + i_group;
+
+    ReturnCode rc;
+
+    FAPI_INF( "+++++++++++++++ Check Error Status on port: %d rank group: %d +++++++++++++++", i_port, i_group);
+
+    if(i_port == 0)
+    {
+        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64);
+        if(rc) return rc;
+    }
+    else
+    {
+        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64);
+        if(rc) return rc;
+    }
+
     if(cal_error_buffer_64.isBitSet(cal_error_reg_offset))
     {
-        //Should it be changed to FAPI_ERR once integrated to xml file. Using FAPI_INF so procedure moves to next group before erroring out.
         FAPI_ERR( "+++++++++++++++ Calibration on port: %d rank group: %d failed! +++++++++++++++", i_port, i_group);
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); 
-        //FAPI_SET_HWP_ERROR(rc, RC_MSS_INIT_CAL_FAILED);
+	io_status = MSS_INIT_CAL_FAIL;
+
         if(cal_error_buffer_64.isBitSet(48))
         {
             FAPI_ERR( "+++++++++++++++ Write leveling error occured on port: %d rank group: %d! +++++++++++++++", i_port, i_group);
@@ -348,18 +634,1080 @@ ReturnCode mss_check_cal_status(
     }
     else
     {
-        if(cal_status_buffer_64.isBitSet(cal_status_reg_offset))
+	FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d was successful! +++++++++++++++", i_port, i_group);
+	io_status = MSS_INIT_CAL_PASS;
+    }
+
+    return rc;
+}
+
+ReturnCode mss_rtt_nom_rtt_wr_swap(
+            Target& i_target,
+            uint32_t i_port_number,
+            uint8_t i_rank,
+	    uint32_t i_rank_pair_group,
+            uint32_t& io_ccs_inst_cnt
+            )
+{
+
+    ReturnCode rc;  
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+
+    ecmdDataBufferBase address_16(16);
+    ecmdDataBufferBase bank_3(3);
+    ecmdDataBufferBase activate_1(1);
+    ecmdDataBufferBase rasn_1(1);
+    rc_num = rc_num | rasn_1.clearBit(0);
+    ecmdDataBufferBase casn_1(1);
+    rc_num = rc_num | casn_1.clearBit(0);
+    ecmdDataBufferBase wen_1(1);
+    rc_num = rc_num | wen_1.clearBit(0);
+    ecmdDataBufferBase cke_4(4);
+    rc_num = rc_num | cke_4.setBit(0,4);
+    ecmdDataBufferBase csn_8(8);
+    rc_num = rc_num | csn_8.setBit(0,8);
+    ecmdDataBufferBase odt_4(4);
+    rc_num = rc_num | odt_4.setBit(0,4);
+    ecmdDataBufferBase ddr_cal_type_4(4);
+
+    ecmdDataBufferBase num_idles_16(16);
+    ecmdDataBufferBase num_repeat_16(16);
+    ecmdDataBufferBase data_20(20);
+    ecmdDataBufferBase read_compare_1(1);
+    ecmdDataBufferBase rank_cal_4(4);
+    ecmdDataBufferBase ddr_cal_enable_1(1);
+    ecmdDataBufferBase ccs_end_1(1);
+
+    ecmdDataBufferBase mrs1_16(16);
+    ecmdDataBufferBase mrs2_16(16);
+
+    ecmdDataBufferBase data_buffer_64(64);
+
+    uint16_t MRS1 = 0;
+    uint16_t MRS2 = 0;
+
+    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
+    rc_num = rc_num | csn_8.setBit(0,8);
+    rc_num = rc_num | address_16.clearBit(0, 16);
+    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
+    rc = mss_ccs_inst_arry_0( i_target,
+                              io_ccs_inst_cnt,
+                              address_16,
+                              bank_3,
+                              activate_1,
+                              rasn_1,
+                              casn_1,
+                              wen_1,
+                              cke_4,
+                              csn_8,
+                              odt_4,
+                              ddr_cal_type_4,
+                              i_port_number);	     
+    if(rc) return rc;
+    rc = mss_ccs_inst_arry_1( i_target,
+                              io_ccs_inst_cnt,
+                              num_idles_16,
+                              num_repeat_16,
+                              data_20,
+                              read_compare_1,
+                              rank_cal_4,
+                              ddr_cal_enable_1,
+                              ccs_end_1);  
+    if(rc) return rc;
+    io_ccs_inst_cnt ++;
+
+    rc_num = rc_num | csn_8.setBit(0,8);
+    if (i_rank == 0)
+    {
+	rc_num = rc_num | csn_8.clearBit(0);
+    }
+    else if (i_rank == 1)
+    {
+	rc_num = rc_num | csn_8.clearBit(1);
+    }
+    else if (i_rank == 2)
+    {
+	rc_num = rc_num | csn_8.clearBit(2);
+    }
+    else if (i_rank == 3)
+    {
+	rc_num = rc_num | csn_8.clearBit(3);
+    }
+
+    // MRS CMD to CMD spacing = 12 cycles
+    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
+
+    FAPI_INF( "SWAPPING RTT_NOM AND RTT_WR FOR PORT%d RP%d", i_port_number, i_rank_pair_group);
+
+    //MRS1
+    // Get contents of MRS 1 Shadow Reg
+
+    if (i_port_number == 0){
+    	if (i_rank_pair_group == 0)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 1)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 2)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 3)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64);
+    	}
+    }
+    else if (i_port_number == 1){
+    	if (i_rank_pair_group == 0)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 1)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 2)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64);
+    	}
+    	else if (i_rank_pair_group == 3)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64);
+    	}
+    }
+
+    rc_num = rc_num | data_buffer_64.reverse();
+    rc_num = rc_num | mrs1_16.insert(data_buffer_64, 0, 16, 0);
+    rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0);
+    FAPI_INF( "ORIGINAL MRS 1: 0x%04X", MRS1);
+
+    uint8_t dll_enable = 0x00; //DLL Enable 
+    if (mrs1_16.isBitSet(0))
+    {
+	// DLL disabled
+	dll_enable = 0xFF;
+    }
+    else if (mrs1_16.isBitClear(0))
+    {
+	// DLL enabled
+	dll_enable = 0x00;
+    }
+
+    uint8_t out_drv_imp_cntl = 0x00;
+    if ( (mrs1_16.isBitClear(1)) && (mrs1_16.isBitClear(5)) )
+    {
+	// out_drv_imp_ctrl set to 40 (Rzq/6)
+	out_drv_imp_cntl = 0x00;
+    }
+    else if ( (mrs1_16.isBitSet(1)) && (mrs1_16.isBitClear(5)) )
+    {
+	// out_drv_imp_ctrl set to 34 (Rzq/7)
+	out_drv_imp_cntl = 0x80;
+    }
+
+    uint8_t dram_rtt_wr = 0x00;
+    if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitClear(9)) )
+    {
+	// RTT_NOM set to disabled
+        //RTT WR Disabled
+	dram_rtt_wr = 0x00;
+    }
+    else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) )
+    {
+	// RTT_NOM set to 20
+        //RTT WR 60 OHM
+	dram_rtt_wr = 0x80;
+    }
+    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) )
+    {
+	// RTT_NOM set to 30
+        //RTT WR 60 OHM
+	dram_rtt_wr = 0x80;
+    }
+    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
+    {
+	// RTT_NOM set to 40
+	//RTT WR 60 OHM
+	dram_rtt_wr = 0x80;
+    }
+    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
+    {
+        // RTT_NOM set to 60
+        //RTT WR 60 OHM
+	dram_rtt_wr = 0x80;
+    }
+    else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
+    {
+	// RTT_NOM set to 120
+	// RTT_WR set to 120
+	dram_rtt_wr = 0x40;
+    }
+    
+    uint8_t dram_al = 0x00;
+    if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitClear(4)) )
+    {
+	//AL DISABLED
+        dram_al = 0x00;
+    }
+    else if ( (mrs1_16.isBitSet(3)) && (mrs1_16.isBitClear(4)) )
+    {
+	// AL = CL -1 
+        dram_al = 0x80;
+    }
+    else if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitSet(4)) )
+    {
+	// AL = CL -2 
+        dram_al = 0x40;
+    }
+ 
+    uint8_t wr_lvl = 0x00; //write leveling enable
+    if (mrs1_16.isBitClear(7))
+    {
+	// WR_LVL DISABLED
+        wr_lvl = 0x00;
+    }
+    else if (mrs1_16.isBitSet(7))
+    {
+	// WR_LVL ENABLED
+        wr_lvl = 0xFF;
+    }
+
+    uint8_t tdqs_enable = 0x00; //TDQS Enable 
+    if (mrs1_16.isBitClear(11))
+    {
+	//TDQS DISABLED
+        tdqs_enable = 0x00;
+    }
+    else if (mrs1_16.isBitSet(11))
+    {
+	//TDQS ENABLED
+        tdqs_enable = 0xFF;
+    }
+
+    uint8_t q_off = 0x00; //Qoff - Output buffer Enable 
+    if (mrs1_16.isBitSet(12))
+    {
+	//Output Buffer Disabled
+        q_off = 0xFF;
+    }
+    else if (mrs1_16.isBitClear(12))
+    {
+	//Output Buffer Enabled
+        q_off = 0x00;
+    }
+
+    //MRS2
+    // MRS CMD to CMD spacing = 12 cycles
+    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
+
+    // Get contents of MRS 1 Shadow Reg
+    if (i_port_number == 0){
+    	if (i_rank_pair_group == 0)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64);
+	}
+	else if (i_rank_pair_group == 1)
+	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64);
+        }
+        else if (i_rank_pair_group == 2)
         {
-            FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d was successful! +++++++++++++++", i_port, i_group);
+	        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64);
         }
-        else
+        else if (i_rank_pair_group == 3)
+        {
+     	        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64);
+        }
+    }
+    else if (i_port_number == 1){
+    	if (i_rank_pair_group == 0)
+    	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64);
+	}
+	else if (i_rank_pair_group == 1)
+	{
+		rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64);
+        }
+        else if (i_rank_pair_group == 2)
+        {
+	        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64);
+        }
+        else if (i_rank_pair_group == 3)
         {
-            FAPI_ERR( "+++++++++++++++ Calibration on port: %d rank group: %d has stalled! +++++++++++++++", i_port, i_group);
-            //Should it be changed to FAPI_ERR once integrated to xml file. Using FAPI_INF so procedure moves to next group before erroring out.
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); 
+     	        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64);
         }
     }
+
+    rc_num = rc_num | data_buffer_64.reverse();
+    rc_num = rc_num | mrs2_16.insert(data_buffer_64, 0, 16, 0);
+    rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0);
+    FAPI_INF( "ORIGINAL MRS 2: 0x%04X", MRS2);
+
+    uint8_t pt_arr_sr = 0x00; //Partial Array Self Refresh  
+    if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitClear(2)) )
+    {
+	//PASR FULL
+        pt_arr_sr = 0x00;
+    }
+    else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitClear(2)) )
+    {
+	//PASR FIRST HALF
+        pt_arr_sr = 0x80;
+    }
+    else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitClear(2)) )
+    {
+	// PASR FIRST QUARTER
+        pt_arr_sr = 0x40;
+    }
+    else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitClear(2)) )
+    {
+	// PASR FIRST EIGHTH
+        pt_arr_sr = 0xC0;
+    }
+    else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitSet(2)) )
+    {
+	// PASR LAST FOURTH
+        pt_arr_sr = 0x20;
+    }
+    else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitClear(1)) && (mrs2_16.isBitSet(2)) )
+    {
+	// PASR LAST HALF
+        pt_arr_sr = 0xA0;
+    }
+    else if ( (mrs2_16.isBitClear(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitSet(2)) )
+    {
+	// PASR LAST QUARTER
+        pt_arr_sr = 0x60;
+    }
+    else if ( (mrs2_16.isBitSet(0)) && (mrs2_16.isBitSet(1)) && (mrs2_16.isBitSet(2)) )
+    {
+	// PASR LAST EIGHTH
+        pt_arr_sr = 0xE0;
+    }
+
+    uint8_t cwl = 0x00; // CAS Write Latency 
+    if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitClear(5)) )
+    {
+	// CWL = 5
+        cwl = 0x00;
+    }
+    else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitClear(5)) )
+    {
+	// CWL = 6
+        cwl = 0x80;
+    }
+    else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitClear(5)) )
+    {
+	// CWL = 7
+        cwl = 0x40;
+    }
+    else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitClear(5)) )
+    {
+	// CWL = 8
+        cwl = 0xC0;
+    }
+    else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitSet(5)) )
+    {
+	// CWL = 9
+        cwl = 0x20;
+    }
+    else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitClear(4)) && (mrs2_16.isBitSet(5)) )
+    {
+	// CWL = 10
+        cwl = 0xA0;
+    }
+    else if ( (mrs2_16.isBitClear(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitSet(5)) )
+    {
+	// CWL = 11
+        cwl = 0x60;
+    }
+    else if ( (mrs2_16.isBitSet(3)) && (mrs2_16.isBitSet(4)) && (mrs2_16.isBitSet(5)) )
+    {
+	// CWL = 12
+        cwl = 0xE0;
+    }
+
+    uint8_t auto_sr = 0x00; // Auto Self-Refresh
+    if ( (mrs2_16.isBitClear(6)) )
+    {
+	//AUTO SR = SRT
+        auto_sr = 0x00;
+    }
+    else if ( (mrs2_16.isBitSet(6)) )
+    {
+	//AUTO SR = ASR ENABLE
+        auto_sr = 0xFF;
+    }
+
+    uint8_t sr_temp = 0x00; // Self-Refresh Temp Range
+    if ( (mrs2_16.isBitClear(7)) )
+    {
+	//SRT NORMAL
+        sr_temp = 0x00;
+    }
+    else if ( (mrs2_16.isBitSet(7)) )
+    {
+	//SRT EXTEND
+        sr_temp = 0xFF;
+    }
+
+    uint8_t dram_rtt_nom = 0x00;
+    if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) )
+    {
+	//RTT WR DISABLE
+	// RTT_NOM set to disabled
+	dram_rtt_nom = 0x00;
+    }
+    else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) )
+    {
+	//RTT WR 60 OHM
+        // RTT_NOM set to 60
+	dram_rtt_nom = 0x80;
+    }
+    else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) )
+    {
+	//RTT WR 120 OHM
+	// RTT_NOM set to 120
+	dram_rtt_nom = 0x40;
+    }
+
+    rc_num = rc_num | mrs1_16.insert((uint8_t) dll_enable, 0, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 1, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 2, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_al, 3, 2, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 5, 1, 1);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 6, 1, 1);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) wr_lvl, 7, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 8, 1);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 9, 1, 2);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 10, 1);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) tdqs_enable, 11, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) q_off, 12, 1, 0);
+    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 13, 3);
+
+    rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0);
+    FAPI_INF( "NEW MRS 1: 0x%04X", MRS1);
+
+    rc_num = rc_num | address_16.insert(mrs1_16, 0, 16, 0);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
+
+    if (rc_num)
+    {
+	FAPI_ERR( "mss_mrs_load: Error setting up buffers");
+	rc_buff.setEcmdError(rc_num);
+	return rc_buff;
+    }
+
+    // Send out to the CCS array 
+    rc = mss_ccs_inst_arry_0( i_target,
+			      io_ccs_inst_cnt,
+			      address_16,
+			      bank_3,
+			      activate_1,
+			      rasn_1,
+			      casn_1,
+			      wen_1,
+			      cke_4,
+			      csn_8,
+			      odt_4,
+			      ddr_cal_type_4,
+			      i_port_number);
+    if(rc) return rc;
+    rc = mss_ccs_inst_arry_1( i_target,
+			      io_ccs_inst_cnt,
+			      num_idles_16,
+			      num_repeat_16,
+			      data_20,
+			      read_compare_1,
+			      rank_cal_4,
+			      ddr_cal_enable_1,
+			      ccs_end_1);
+    if(rc) return rc;
+    io_ccs_inst_cnt++;	
+
+
+    rc_num = rc_num | mrs2_16.insert((uint8_t) pt_arr_sr, 0, 3);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) cwl, 3, 3);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) auto_sr, 6, 1);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) sr_temp, 7, 1);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) 0x00, 8, 1);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) dram_rtt_wr, 9, 2);
+    rc_num = rc_num | mrs2_16.insert((uint8_t) 0x00, 10, 6);
+
+    rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0);
+    FAPI_INF( "NEW MRS 2: 0x%04X", MRS2);
+
+    rc_num = rc_num | address_16.insert(mrs2_16, 0, 16, 0);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
+    rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
+
+    if (rc_num)
+    {
+	FAPI_ERR( "mss_mrs_load: Error setting up buffers");
+	rc_buff.setEcmdError(rc_num);
+	return rc_buff;
+    }
+
+    // Send out to the CCS array 
+    rc = mss_ccs_inst_arry_0( i_target,
+			      io_ccs_inst_cnt,
+			      address_16,
+			      bank_3,
+			      activate_1,
+			      rasn_1,
+			      casn_1,
+			      wen_1,
+			      cke_4,
+			      csn_8,
+			      odt_4,
+			      ddr_cal_type_4,
+			      i_port_number);
+    if(rc) return rc;
+    rc = mss_ccs_inst_arry_1( i_target,
+			      io_ccs_inst_cnt,
+			      num_idles_16,
+			      num_repeat_16,
+			      data_20,
+			      read_compare_1,
+			      rank_cal_4,
+			      ddr_cal_enable_1,
+			      ccs_end_1);
+    if(rc) return rc;
+    io_ccs_inst_cnt++;
+
     return rc;
+
+}
+
+fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
+{
+    // Flash to registers.
+
+
+	const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = {
+	/* port 0 */
+	{	// primary rank pair 0
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F},
+		// primary rank pair 1
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F},
+		// primary rank pair 2
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F},
+		// primary rank pair 3
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F}
+	},
+	/* port 1 */
+	{
+	   // primary rank pair 0
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F,
+                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F},
+           // primary rank pair 1 
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F},
+           // primary rank pair 2
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F},
+           // primary rank pair 3
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F}
+	}};
+	const uint8_t rg_invalid[] = {
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID,
+	};
+
+    ReturnCode rc;
+    ecmdDataBufferBase data_buffer(64);
+    ecmdDataBufferBase db_reg(BITS_PER_PORT);
+	uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
+	uint8_t prg[MAX_PRI_RANKS][MAX_PORTS];			// primary rank group values
+
+	FAPI_INF("Running set bad bits FN:mss_set_bbm_regs,"
+			" input Target: %s", mba_target.toEcmdString());
+
+	std::vector<Target> mba_dimms;
+	fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+
+	FAPI_INF("***-------- Found %i functional DIMMS --------***",
+			mba_dimms.size());
+
+	//	ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], GROUP2[port], GROUP3[port]
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]);
+	if(rc) return rc;
+
+	l_ecmdRc = data_buffer.flushTo0();
+	if (l_ecmdRc != ECMD_DBUF_SUCCESS)
+	{
+		 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
+				 "- rc 0x%.8X", l_ecmdRc);
+
+		 rc.setEcmdError(l_ecmdRc);
+		 return rc;
+	}
+	for (uint8_t port = 0; port < MAX_PORTS; port++ )	// [0:1]
+	{
+		// loop through primary ranks [0:3]
+		for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
+		{
+			uint8_t dimm = prg[prank][port] >> 2;
+			uint8_t rank = prg[prank][port] & 0x03;
+			uint16_t l_data = 0;
+
+			if (prg[prank][port] == rg_invalid[prank])	// invalid rank
+			{
+				FAPI_INF("Primary rank group %i is INVALID, continuing...",
+						prank);
+				continue;
+			}
+
+			rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg);
+			if (rc)
+			{
+				FAPI_ERR("Error from getting register bitmap port=%i: "
+						"dimm=%i, rank=%i rc=%i", port, dimm, rank,
+						static_cast<uint32_t>(rc));
+				return rc;
+			}
+			// quick test to move on to next rank if no bits need to be set
+			if (db_reg.getNumBitsSet(0, BITS_PER_PORT) == 0)
+			{
+				FAPI_INF("No bad bits found for p%i:d%i:r%i(rg%i):cs%i",
+						port, dimm, rank, prank, prg[prank][port]);
+				continue;
+			}
+
+			for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4]
+			{
+				// clear bits 48:63
+				l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG);
+				l_data = db_reg.getHalfWord(i);
+
+                                //	check or not to check(always set register)?
+				if (l_data == 0)
+				{
+					FAPI_INF("DP18_%i has no bad bits set, continuing...", i);
+					continue;
+				}
+
+				l_ecmdRc |= data_buffer.setHalfWord(3, l_data);
+				if (l_ecmdRc != ECMD_DBUF_SUCCESS)
+				{
+					 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
+							 "- rc 0x%.8X", l_ecmdRc);
+
+					 rc.setEcmdError(l_ecmdRc);
+					 return rc;
+				}
+				FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i "
+					"Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port,
+					dimm, prank, prg[prank][port], i,
+					disable_reg[port][prank][i], l_data);
+
+				rc = fapiPutScom(mba_target, disable_reg[port][prank][i],
+						data_buffer);
+				if (rc)
+				{
+					FAPI_ERR("Error from fapiPutScom writing disable reg");
+					return rc;
+				}
+			} // end DP18 instance loop
+		} // end primary rank loop
+	} // end port loop
+    return rc;
+} // end mss_set_bbm_regs
+
+
+
+fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target)
+{
+// Registers to Flash.
+
+	const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = {
+	/* port 0 */
+	{	// primary rank pair 0
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F},
+		// primary rank pair 1
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F},
+		// primary rank pair 2
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F},
+		// primary rank pair 3
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F,
+		DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F}
+	},
+	/* port 1 */
+	{
+	   // primary rank pair 0
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F,
+                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F},
+           // primary rank pair 1 
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F},
+           // primary rank pair 2
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F},
+           // primary rank pair 3
+	   {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F,
+	        DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F}
+
+	}};
+
+
+
+	const uint8_t rg_invalid[] = {
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID,
+		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID,
+	};
+
+        ReturnCode rc;
+        ecmdDataBufferBase data_buffer(64);
+        ecmdDataBufferBase db_reg(BITS_PER_PORT);
+	uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
+	uint8_t prg[MAX_PRI_RANKS][MAX_PORTS];			// primary rank group values
+
+	FAPI_INF("Running set bad bits FN:mss_set_bbm_regs \n"
+			" input Target: %s", mba_target.toEcmdString());
+
+	std::vector<Target> mba_dimms;
+	fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
+
+	FAPI_INF("***-------- Found %i functional DIMMS --------***",
+			mba_dimms.size());
+
+	// 4 dimms per MBA, 2 per port
+
+	//	ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], GROUP2[port], GROUP3[port]
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]);
+	if(rc) return rc;
+	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]);
+	if(rc) return rc;
+
+	l_ecmdRc = data_buffer.flushTo0();
+	if (l_ecmdRc != ECMD_DBUF_SUCCESS)
+	{
+		 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
+				 "- rc 0x%.8X", l_ecmdRc);
+
+		 rc.setEcmdError(l_ecmdRc);
+		 return rc;
+	}
+	for (uint8_t port = 0; port < MAX_PORTS; port++ )	// [0:1]
+	{
+		// loop through primary ranks [0:3]
+		for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
+		{
+			uint8_t dimm = prg[prank][port] >> 2;
+			uint8_t rank = prg[prank][port] & 0x03;
+			uint16_t l_data = 0;
+
+			if (prg[prank][port] == rg_invalid[prank])	// invalid rank
+			{
+				FAPI_INF("Primary rank group %i is INVALID, continuing...",
+						prank);
+				continue;
+			}
+
+			for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4]
+			{
+
+				// clear bits 48:63
+				l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG);
+
+				rc = fapiGetScom(mba_target, disable_reg[port][prank][i],
+						data_buffer);
+				if (rc)
+				{
+					FAPI_ERR("Error from fapiPutScom writing disable reg");
+					return rc;
+				}
+
+				l_data = data_buffer.getHalfWord(3);
+				if (l_ecmdRc != ECMD_DBUF_SUCCESS)
+				{
+					 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
+							 "- rc 0x%.8X", l_ecmdRc);
+
+					 rc.setEcmdError(l_ecmdRc);
+					 return rc;
+				}
+
+				l_ecmdRc |= db_reg.setHalfWord(i, l_data);
+ 
+				FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i "
+					"Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port,
+					dimm, prank, prg[prank][port], i,
+					disable_reg[port][prank][i], l_data);
+
+
+			} // end DP18 instance loop
+
+
+			rc = setC4dq2reg(mba_target, port, dimm, rank, db_reg);
+			if (rc)
+			{
+				FAPI_ERR("Error from setting register bitmap p%i: "
+						"dimm=%i, rank=%i rc=%i", port, dimm, rank,
+						static_cast<uint32_t>(rc));
+				return rc;
+			}
+
+		} // end primary rank loop
+	} // end port loop
+    return rc;
+} // end mss_set_bbm_regs
+
+// output reg = in phy based order
+ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg)
+{
+	// [port][bits per port]
+    const uint8_t lookup[4][BITS_PER_PORT] = {
+	// port 0
+	{65,66,67,64, 70,69,68,71, 21,20,23,22, 18,16,19,17,	// DP18 block 0
+	61,63,60,62, 57,58,59,56, 73,74,75,72, 78,77,79,76,	// ...  block 1
+	7, 5, 4, 6,  0, 2, 1, 3, 12,13,15,14, 10, 8,11, 9, 	// ...  block 2
+	47,44,46,45, 43,42,41,40, 31,29,30,28, 26,24,27,25,	// ...  block 3
+	55,53,54,52, 50,48,49,51, 33,34,35,32, 36,37,38,39},	// ...  block 4
+	// port 1
+	{17,16,18,19, 20,21,22,23,  2, 0, 3, 1,  7, 4, 5, 6,
+	70,71,69,68, 66,64,67,65, 27,24,26,25, 29,30,31,28,
+	37,36,38,39, 35,32,34,33, 77,76,79,78, 73,75,72,74,
+	40,42,41,43, 45,44,46,47,  9,11, 8,10, 12,13,14,15,
+	48,51,49,50, 52,53,54,55, 61,63,62,60, 56,58,59,57},
+	// port 2
+	{22,23,20,21, 19,16,17,18, 26,25,24,27, 29,28,31,30,
+	67,64,65,66, 71,70,69,68,  7, 5, 6, 4,  2, 0, 3, 1,
+	45,44,47,46, 42,43,41,40, 39,38,37,36, 33,34,35,32,
+	48,50,49,51, 54,52,53,55, 15,13,12,14,  9, 8,10,11,
+	61,60,62,63, 59,56,58,57, 74,72,73,75, 76,79,78,77},
+	// port 3
+	{25,26,27,24, 28,31,29,30, 17,19,16,18, 20,21,23,22,
+	64,67,66,65, 71,69,68,70, 75,74,72,73, 76,77,79,78,
+	4, 5, 7, 6,  0, 1, 2, 3, 12,13,14,15,  8, 9,11,10,
+	47,45,46,44, 43,41,42,40, 35,32,33,34, 39,37,36,38,
+	55,52,53,54, 51,48,49,50, 60,62,61,63, 57,59,56,58}
+    };
+
+    uint8_t l_bbm[TOTAL_BYTES] = {0};	// bad bitmap from dimmGetBadDqBitmap
+    ecmdDataBufferBase c4dqbmp(BITS_PER_PORT);	// databuffer of C4 dq bitmap
+    ReturnCode rc;
+    uint8_t l_port = i_port;	// port # relative to Centaur
+    uint8_t mba_pos = 0;
+    uint32_t ecmdrc = ECMD_DBUF_SUCCESS;
+
+    ecmdrc = o_reg.flushTo0();		// clear output databuffer
+    if (ecmdrc != ECMD_DBUF_SUCCESS)
+    {
+	FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
+		 "- rc 0x%.8X", ecmdrc);
+
+	rc.setEcmdError(ecmdrc);
+	return rc;
+    }
+    rc=FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_mba, mba_pos);
+    if (rc)
+    {
+	FAPI_ERR("Error getting ATTR_CHIP_UNIT_POS for MBA");
+	return (rc);
+    }
+
+    // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
+    rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
+    if (rc)
+    {
+	FAPI_ERR("Error from dimmGetBadDqBitmap on MBA%ip%i: "
+		 "dimm=%i, rank=%i rc=%i", mba_pos, i_port, i_dimm, i_rank,
+		 static_cast<uint32_t>(rc));
+	return rc;
+    }
+
+    // create databuffer from C4 dq bitmap array
+    ecmdrc = c4dqbmp.insertFromRight(l_bbm, 0, BITS_PER_PORT);
+    if (ecmdrc != ECMD_DBUF_SUCCESS)
+    {
+        FAPI_ERR("Error from ecmdDataBuffer insertFromRight() "
+            "- rc 0x%.8X", ecmdrc);
+
+        rc.setEcmdError(ecmdrc);
+        return rc;
+    }
+
+    // quick check if there no bits on, we're done
+    if (c4dqbmp.getNumBitsSet(0, BITS_PER_PORT) == 0)
+    {
+	return rc;
+    }
+    l_port = i_port + (mba_pos * MAX_PORTS);	// relative to Centaur
+
+    for (uint8_t i=0; i < BITS_PER_PORT; i++)
+    {
+	if (c4dqbmp.isBitSet(lookup[l_port][i]))
+	{
+	    o_reg.setBit(i);
+	    FAPI_DBG("set bad bit C4_dq=%i,\t dp18_%i_lane%i\t (bit %i)",
+		     lookup[l_port][i], (i / 16), (i % 16), i);
+	}
+    }
+
+    return rc;
+}
+
+ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg)
+{
+
+	const uint8_t lookup[4][BITS_PER_PORT] = {
+	// port 0
+	{65,66,67,64,70,69,68,71,21,20,23,22,18,16,19,17,	// DP18 block 0
+	 61,63,60,62,57,58,59,56,73,74,75,72,78,77,79,76,	// ...  block 1
+	  7, 5, 4, 6, 0, 2, 1, 3,12,13,15,14,10, 8,11, 9, 	// ...  block 2
+	 47,44,46,45,43,42,41,40,31,29,30,28,26,24,27,25,	// ...  block 3
+	 55,53,54,52,50,48,49,51,33,34,35,32,36,37,38,39},	// ...  block 4
+	// port 1
+	{17,16,18,19,20,21,22,23, 2, 0, 3, 1, 7, 4, 5, 6,
+	 70,71,69,68,66,64,67,65,27,24,26,25,29,30,31,28,
+	 37,36,38,39,35,32,34,33,77,76,79,78,73,75,72,74,
+	 40,42,41,43,45,44,46,47, 9,11, 8,10,12,13,14,15,
+	 48,51,49,50,52,53,54,55,61,63,62,60,56,58,59,57},
+	// port 2
+	{22,23,20,21,19,16,17,18,26,25,24,27,29,28,31,30,
+	 67,64,65,66,71,70,69,68, 7, 5, 6, 4, 2, 0, 3, 1,
+	 45,44,47,46,42,43,41,40,39,38,37,36,33,34,35,32,
+	 48,50,49,51,54,52,53,55,15,13,12,14, 9, 8,10,11,
+	 61,60,62,63,59,56,58,57,74,72,73,75,76,79,78,77},
+	// port 3
+	{25,26,27,24,28,31,29,30,17,19,16,18,20,21,23,22,
+	 64,67,66,65,71,69,68,70,75,74,72,73,76,77,79,78,
+	  4, 5, 7, 6, 0, 1, 2, 3,12,13,14,15, 8, 9,11,10,
+	 47,45,46,44,43,41,42,40,35,32,33,34,39,37,36,38,
+	 55,52,53,54,51,48,49,50,60,62,61,63,57,59,56,58}
+	};
+	uint8_t l_bbm [TOTAL_BYTES] = {0};
+	ecmdDataBufferBase c4dqbmp(BITS_PER_PORT);
+	ReturnCode rc;
+	uint8_t l_port = i_port;
+	uint8_t mba_pos = 0;
+	uint32_t ecmdrc = ECMD_DBUF_SUCCESS;
+
+        // clear output databuffer
+	ecmdrc = c4dqbmp.flushTo0();		
+	if (ecmdrc != ECMD_DBUF_SUCCESS)
+	{
+		FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
+			"- rc 0x%.8X", ecmdrc);
+
+		rc.setEcmdError(ecmdrc);
+		return rc;
+	}
+
+	// Set Port info
+	rc=FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_mba, mba_pos);
+	if (rc)
+	{
+		FAPI_ERR("Error getting ATTR_CHIP_UNIT_POS for MBA");
+		return (rc);
+	}
+
+	l_port = i_port + (mba_pos * MAX_PORTS);
+
+	// translate c4 from input
+	for (uint8_t i=0; i < BITS_PER_PORT; i++)
+	{
+		if (o_reg.isBitSet(i))
+		{
+		    c4dqbmp.setBit(lookup[l_port][i]);
+		}
+	}
+
+	// create array from databuffer
+	for (uint8_t b=0; b < TOTAL_BYTES; b++)
+	{
+		l_bbm[b] = c4dqbmp.getByte(b);
+	}
+
+	// set Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
+	rc = dimmSetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
+	if (rc)
+	{
+		FAPI_ERR("Error from dimmSetBadDqBitmap on MBA%ip%i: "
+				"dimm=%i, rank=%i rc=%i", mba_pos, i_port, i_dimm, i_rank,
+				static_cast<uint32_t>(rc));
+		return rc;
+	}
+
+	return rc;
 }
 
 } //end extern C
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
index 5395b5cd8..4aa0fa551 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_funcs.C,v 1.28 2012/07/17 13:24:16 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $                  */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_funcs.C,v 1.29 2012/11/19 21:18:40 jsabrow Exp $
 /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -44,6 +43,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.29   | jsabrow  | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern
 //  1.28   | bellows  | 07/16/12|added in Id tag
 //  1.27   | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function
 //  1.26   | divyakum | 3/22/12 | Fixed mss_execute_zq_cal function variable name mismatch
@@ -228,7 +228,7 @@ ReturnCode mss_ccs_inst_arry_1(
 
     rc_num = rc_num | goto_inst.insertFromRight(io_instruction_number + 1, 0, 5);
 
-    //Setting up a CSS Instruction Array Type 1
+    //Setting up a CCS Instruction Array Type 1
     rc_num = rc_num | data_buffer.insert( i_num_idles, 0, 16, 0);
     rc_num = rc_num | data_buffer.insert( i_num_repeat, 16, 16, 0);
     rc_num = rc_num | data_buffer.insert( i_data, 32, 20, 0);
@@ -250,6 +250,82 @@ ReturnCode mss_ccs_inst_arry_1(
     return rc;
 }
 
+//--------------
+ReturnCode mss_ccs_load_data_pattern(
+            Target& i_target,
+            uint32_t io_instruction_number,
+	    mss_ccs_data_pattern data_pattern)
+{
+    //Example Use:
+    //
+    ReturnCode rc;
+
+    if (data_pattern == MSS_CCS_DATA_PATTERN_00)
+      {
+	rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00000000);
+      }
+    else if (data_pattern == MSS_CCS_DATA_PATTERN_0F)
+      {
+	rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00055555);
+      }
+    else if (data_pattern == MSS_CCS_DATA_PATTERN_F0)
+      {
+	rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000aaaaa);
+      }
+    else if (data_pattern == MSS_CCS_DATA_PATTERN_FF)
+      {
+	rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000fffff);
+      }
+
+    return rc;
+}
+
+
+ReturnCode mss_ccs_load_data_pattern(
+            Target& i_target,
+            uint32_t io_instruction_number,
+	    uint32_t data_pattern)
+{
+    //Example Use:
+    //
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0; 
+    uint32_t reg_address = 0;
+
+    if (io_instruction_number > 31)
+    {
+        FAPI_INF("mss_ccs_load_data_pattern: CCS Instruction Array index out of bounds");
+    }
+    else
+    {
+      reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635;
+      ecmdDataBufferBase data_buffer(64);
+
+      //read current array1 reg
+      rc = fapiGetScom(i_target, reg_address, data_buffer);
+      if(rc) return rc;
+      
+      //modify data bits for specified pattern
+      rc_num = rc_num | data_buffer.insertFromRight(data_pattern, 32, 20);
+      if (rc_num)
+	{
+        FAPI_ERR( "mss_ccs_load_data_pattern: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+	}
+      
+      //write array1 back out
+      rc = fapiPutScom(i_target, reg_address, data_buffer);
+      if(rc) return rc;
+    }
+
+    return rc;
+}
+//--------------
+
+
+
 ReturnCode mss_ccs_mode(
             Target& i_target,
             ecmdDataBufferBase i_stop_on_err,
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
index d87c4d9b8..685ed1ef1 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_funcs.H,v 1.12 2012/07/17 13:22:58 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $                  */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_funcs.H,v 1.13 2012/11/19 21:18:41 jsabrow Exp $
 /* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -44,6 +43,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.13   | jsabrow  | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern
 //  1.12   | 07/16/12 | bellows | added in Id tag
 //  1.11   | 3/21/12  | divyakum| Added mss_execute_zq_cal function 
 //  1.10   | 2/14/12  | jdsloat | Comment section filled in, elimated unnecessary constant, added enums
@@ -90,6 +90,14 @@ enum mss_ccs_status_query_result
 };
 
 
+enum mss_ccs_data_pattern
+{
+    MSS_CCS_DATA_PATTERN_00 = 1,
+    MSS_CCS_DATA_PATTERN_0F = 2,
+    MSS_CCS_DATA_PATTERN_F0 = 3,
+    MSS_CCS_DATA_PATTERN_FF = 4
+};
+
 
 const bool MSS_CCS_START = 0;
 const bool MSS_CCS_STOP = 1;
@@ -133,6 +141,27 @@ fapi::ReturnCode mss_ccs_inst_arry_1( fapi::Target& i_target,
                                       ecmdDataBufferBase i_ddr_cal_enable,
                                       ecmdDataBufferBase i_ccs_end);
 
+
+//---------------------------------------------------------------
+// mss_ccs_load_data_pattern
+// load predefined pattern (enum) into specified array1 index
+// Target = centaur.mba
+//---------------------------------------------------------------
+fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target,
+					    uint32_t io_instruction_number,
+                                            mss_ccs_data_pattern data_pattern);
+
+
+//---------------------------------------------------------------
+// mss_ccs_load_data_pattern
+// load specified pattern (20 bits) into specified array1 index
+// Target = centaur.mba
+//---------------------------------------------------------------
+fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target,
+					    uint32_t io_instruction_number,
+                                            uint32_t data_pattern);
+
+
 //-----------------------------------------
 // mss_ccs_status_query
 // Querying the status of the CCS
@@ -141,6 +170,7 @@ fapi::ReturnCode mss_ccs_inst_arry_1( fapi::Target& i_target,
 fapi::ReturnCode mss_ccs_status_query( fapi::Target& i_target,
                                        mss_ccs_status_query_result& io_status);
 
+
 //-----------------------------------------
 // mss_ccs_start_stop
 // Issuing a start or stop of the CCS
@@ -172,6 +202,7 @@ fapi::ReturnCode mss_ccs_mode( fapi::Target& i_target,
 //-----------------------------------------
 fapi::ReturnCode mss_ccs_fail_type( fapi::Target& i_target);
 
+
 //-----------------------------------
 // mss_execute_ccs_inst_array
 // Execute the CCS intruction array
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
index 8f9d6fd8e..b94b5fbdd 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_scominit.C,v 1.11 2012/08/23 00:11:37 mwuu Exp $
+// $Id: mss_scominit.C,v 1.15 2012/11/12 03:08:50 mwuu Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -41,6 +41,11 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//	 1.15  | menlowuu |11-NOV-12| Removed include of dimmBadDqBitmapFuncs.H>
+//   1.14  | menlowuu |09-NOV-12| Removed mss_set_bbm_regs FN since now handled
+//  							  in draminit_training.
+//   1.13  | menlowuu |26-SEP-12| Changed ORing of port to SCOM address
+//   1.12  | menlowuu |19-SEP-12| Fixed some return codes.
 //   1.11  | menlowuu |22-AUG-12| Added return code for mss_set_bbm_regs FN.
 //   1.10  | menlowuu |21-AUG-12| Removed running *_mcbist files since it was
 //      					moved into the *_def files.
@@ -68,7 +73,6 @@
 //  Includes
 //----------------------------------------------------------------------
 #include <fapi.H>
-#include <dimmBadDqBitmapFuncs.H>
 #include <fapiHwpExecInitFile.H>
 
 //----------------------------------------------------------------------
@@ -82,189 +86,6 @@ extern "C" {
     using namespace fapi;
 
 //******************************************************************************
-// expects i_target = functional MBA target, MBA position (uint8_t)
-// sets bad bit mask (disable0) registers in the PHY with data from SPD
-//******************************************************************************
-fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target,
-									const uint8_t mba_pos)
-{
-	// DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007C0301143F
-	const uint64_t base_addr = 0x8000007C0301143Full;
-	const uint8_t rg_invalid[] = {
-		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID,
-		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID,
-		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID,
-		ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID,
-	};
-
-    ReturnCode rc;
-	uint64_t address = base_addr;
-    ecmdDataBufferBase data_buffer(64);
-	uint8_t prg[MAX_PRI_RANKS][MAX_PORTS];			// primary rank group values
-
-	FAPI_INF("Running set bad bits FN:mss_set_bbm_regs on \nMBA%i,"
-			" input Target: %s", mba_pos, mba_target.toEcmdString());
-
-	std::vector<Target> mba_dimms;
-	fapiGetAssociatedDimms(mba_target, mba_dimms);	// functional dimms
-
-	FAPI_INF("***-------- Found %i functional DIMMS in MBA%i --------***",
-			mba_dimms.size(), mba_pos);
-
-	// 4 dimms per MBA, 2 per port
-/*
-	RAW SPD		0 1  2 3  4 5  6 7   8 9  A B  C D  E F
-	  b0:		0000 0000 0000 0000  0000 0000 0000 0000
-	  c0: 		0000 0000 0000 0000  0000 0000 0000	0000
-	  d0: 		0000 0000 0000 0000  0000 0000 0000 0000
-	  e0: 		0000 0000 0000 0000  0000 0000 0000 00FE
-	  f0: 		0000 0000 0000 0000  0000 0000 0000 00FF
-*/
-//	uint8_t bad_dq_data[80] = {
-//	/*  spd	 |------------  HEADER  -----------------------------------------
-//	 * byte#	|--- magic number ----|-ver-|---- reserved ----|
-//	 *  0-7 */	0xBA, 0xDD, 0x44, 0x71, 0x01, 0x00, 0x00, 0x00,
-//	/* 			|------------------- DATA --------------------| ECC |SPARE|
-//	 * 			  0		1	  2		3	  4		5	  6		7	  8		9
-//	 *  8-17*/	0x00, 0x00,	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-//	/* 18-27*/ 	0x00, 0x00,	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-//	/* 28-37*/ 	0x00, 0x00,	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-//	/* 38-47*/	0x00, 0x00,	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-//	/* 48-49*/													0x00, 0x00,
-//	/* 50-59*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	0x00, 0x00,
-//	/* 60-69*/	0x00, 0x00, 0x00, 0xFE, 0x00, 0x00, 0x00, 0x00,	0x00, 0x00,
-//	/* 70-79*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,	0x00, 0xFF
-//	};
-/*
-	for (uint8_t d = 0; d < 8; d++)
-	{
-		rc=FAPI_ATTR_SET(ATTR_SPD_BAD_DQ_DATA, &mba_dimms[0], bad_dq_data);
-		if (rc)
-		{
-			FAPI_ERR("Error performing FAPI_ATTR_SET on ATTR_SPD_BAD_DQ_DATA");
-		}
-	}
-*/
-	//	ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], GROUP2[port], GROUP3[port]
-	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]);
-	if(rc) return rc;
-	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]);
-	if(rc) return rc;
-	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]);
-	if(rc) return rc;
-	rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]);
-	if(rc) return rc;
-
-	for (uint8_t port = 0; port < MAX_PORTS; port++ )	// [0:1]
-	{
-		uint8_t l_bbm[TOTAL_BYTES] = {0};				// bad bits
-
-		// port 0 = 0x8000..., port 1 = 0x8001...
-		address = address | ((uint64_t)port << 48);
-
-		// loop through primary ranks [0:3]
-		for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-		{
-			// 0x800p 0r7C 0301 143F
-			uint64_t r_addr = address | ((uint64_t)prank << 40);
-			uint8_t dimm = prg[prank][port] >> 2;
-			uint8_t rank = prg[prank][port] & 0x03;
-			uint8_t bbm_e = 0, bbm_o = 0;
-
-//			uint8_t spd_data[10] = {
-//			//		|-------------------- DATA ----------- --------| ECC |SPARE|
-//			//byte	  0		1	  2		3	  4		5	  6		7	  8		9
-//					0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
-//			};
-/*
-			rc = dimmSetBadDqBitmap(mba_target, port, dimm, rank, spd_data);
-			if (rc)
-			{
-				FAPI_ERR("Error from dimmSetBadDqBitmap on MBA%ip%i: dimm=%i,
-					rank=%i rc=%i",	mba_pos, port, dimm, rank,
-					static_cast<uint32_t>(rc));
-				return rc;
-				break;
-			}
-*/
-			if (prg[prank][port] != rg_invalid[prank])		// valid rank group
-			{
-				rc = dimmGetBadDqBitmap(mba_target, port, dimm, rank, l_bbm);
-				if (rc)
-				{
-					FAPI_ERR("Error from dimmGetBadDqBitmap on MBA%ip%i: "
-							"dimm=%i, rank=%i rc=%i", mba_pos, port, dimm, rank,
-							static_cast<uint32_t>(rc));
-
-					return rc;
-					break;
-				}
-			}
-
-			for ( uint8_t i=0; i < TOTAL_BYTES/2; i++ ) // [0:4] dp18 instances
-			{
-				uint64_t scom_addr = r_addr | ((uint64_t) i << 42);
-				uint64_t l_data = 0;
-				uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
-
-				if (prg[prank][port] == rg_invalid[prank])	// invalid rank
-				{
-					FAPI_INF("Primary rank group %i is invalid, prepare"
-							" broadcast write to all instances", prank);
-
-					l_data = 0xFFFF;				// invalidate data bits
-					// set address to broadcast to all instances in the rank
-					scom_addr = scom_addr | 0x00003C0000000000ull;
-				}
-				else
-				{	// scom signifies port dimm rank byte
-					bbm_e = l_bbm[i*2];		// even byte data
-					bbm_o = l_bbm[(i*2)+1];	// odd byte data
-					l_data = (bbm_e << 8) | bbm_o;
-					if (l_data == 0)
-					{
-						// no need to set register since bits are good?
-						continue;		// should double check!
-					}
-				}
-
-				// ecmdDataBufferBase data_buffer(64);
-				l_ecmdRc = data_buffer.setDoubleWord(0, l_data);
-
-				if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-				{
-					 FAPI_ERR("Error from ecmdDataBuffer setDoubleWord() "
-							 "- rc 0x%.8X", l_ecmdRc);
-
-					 rc.setEcmdError(l_ecmdRc);
-					 break;
-				}
-
-				FAPI_INF("+++ Setting Bad Bit Mask in MBA%ip%i: PRG%i=%i,"
-					   " addr=0x%llx, data=0x%04llx", mba_pos, port, prank,
-					   prg[prank][port], scom_addr, l_data);
-
-				rc = fapiPutScom(mba_target, scom_addr, data_buffer);
-				if (rc)
-				{
-					FAPI_ERR("Error from fapiPutScom");
-					break;
-				}
-				if (prg[prank][port] == rg_invalid[prank])  // invalid rank
-				{
-					FAPI_INF("Disabled primary rank group %i data bits"
-							" via broadcast continuing to next rank", prank);
-
-					// did broadcast to all instances in rank move to next rank
-					break;
-				}
-			} // end byte loop
-		} // end primary rank loop
-	} // end port loop
-    return rc;
-} // end mss_set_bbm_regs
-
-//******************************************************************************
 //
 //******************************************************************************
 ReturnCode mss_scominit(const Target & i_target) {
@@ -384,18 +205,6 @@ ReturnCode mss_scominit(const Target & i_target) {
 						FAPI_INF("MBA scom initfile %s passed", mba_if[itr]);
 					}
 				} // end for loop, running MBA/PHY initfiles
-
-				// set bad bits from SPD into disable bit registers
-				rc=mss_set_bbm_regs(vector_targets[i], l_unitPos);
-				if (rc)
-				{
-					FAPI_INF("Error setting disable bit mask registers");
-					return (rc);
-				}
-				else
-				{
-					FAPI_INF("mss_set_bbm_regs FN passed on MBA%i", l_unitPos);
-				}
 			} // end else, MBA fapiHwpExecInitFile
 		} // end for loop, valid chip unit pos
 	} // found functional MBAs
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
index 7319bfd6f..2654a42c2 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_scominit.H,v 1.6 2012/08/15 23:07:26 mwuu Exp $
+// $Id: mss_scominit.H,v 1.7 2012/11/10 02:53:17 mwuu Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -41,6 +41,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.7   | menlowuu |09-NOV-12| Removed mss_set_bbm_regs since now done in
+//   							  draminit_training
 //   1.6   | menlowuu |15-AUG-12| added bad bitmask function
 //   1.5   |bellows   |16-JUL-12| added in Id tag
 //   1.4   | menlowuu |20-JUN-12| added type to the typedef
@@ -64,8 +66,6 @@
 #include <fapi.H>
 
 typedef fapi::ReturnCode (*mss_scominit_FP_t)(const fapi::Target & i_target);
-typedef fapi::ReturnCode (*mss_set_bbm_regs_FP_t)(const fapi::Target 
-								& mba_target, const uint8_t mba_pos);
 
 extern "C" {
 
@@ -78,18 +78,6 @@ extern "C" {
 
 fapi::ReturnCode mss_scominit(const fapi::Target & i_target);
 
-
-//******************************************************************************
-// mss_set_bbm_regs
-//******************************************************************************
-// mss_set_bbm_regs procedure [Sets disable bits in PHY registers for bad bit lanes]
-// param[in] i_target [Reference to target, expecting MBA target],
-// 			mba_pos [mba position, 0=mba01, 1=mba23]
-// return ReturnCode
-
-fapi::ReturnCode mss_set_bbm_regs(const fapi::Target & mba_target,
-									const uint8_t mba_pos);
-
 } // extern "C"
 
 #endif // MSS_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C
new file mode 100644
index 000000000..5efa72815
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C
@@ -0,0 +1,2743 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_unmask_errors.C $          */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_unmask_errors.C,v 1.1 2012/09/05 21:04:52 gollub Exp $
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|   Date:  | Author: | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.1   | 09/05/12 | gollub  | Created
+
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+
+#include <mss_unmask_errors.H>
+#include <cen_scom_addresses.H>
+using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+// Constants and enums
+//------------------------------------------------------------------------------
+        
+
+//------------------------------------------------------------------------------
+// mss_unmask_inband_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    FAPI_INF("ENTER mss_unmask_inband_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // MBS_FIR_REG
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbs_fir_mask(64);
+    ecmdDataBufferBase l_mbs_fir_mask_or(64);    
+    ecmdDataBufferBase l_mbs_fir_mask_and(64);
+    ecmdDataBufferBase l_mbs_fir_action0(64);
+    ecmdDataBufferBase l_mbs_fir_action1(64);
+    
+    // Read mask 
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }    
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+
+    l_ecmd_rc |= l_mbs_fir_action0.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_action1.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1();
+
+    // 0    host_protocol_error     channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(0);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(0);
+    
+    // 1    int_protocol_error      channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(1);
+    
+    // 2    invalid_address_error   channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(2);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(2);
+
+    // 3    external_timeout        channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(3);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(3);
+    
+    // 4    internal_timeout        channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(4);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(4);
+
+    // 5    int_buffer_ce           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(5);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(5);
+
+    // 6    int_buffer_ue           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(6);
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(6);
+
+    // 7    int_buffer_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(7);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(7);
+
+    // 8    int_parity_error        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(8); 
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(8); 
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(8);
+
+    // 9    cache_srw_ce            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(9);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(9);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(9);
+
+    // 10    cache_srw_ue           recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(10);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(10);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(10);
+
+    // 11    cache_srw_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(11);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(11);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(11);
+
+    // 12    cache_co_ce            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(12);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(12);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(12);
+
+    // 13    cache_co_ue            recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(13);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(13);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(13);
+
+    // 14    cache_co_sue           recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(14);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(14);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(14);
+
+    // 15    dir_ce                 recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(15);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(15);
+
+    // 16    dir_ue                 channel checkstop   mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(16);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(16);
+
+    // 17    dir_member_deleted     recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(17);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(17);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(17);
+
+    // 18    dir_all_members_deleted channel checkstop  mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(18);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(18);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(18);
+
+    // 19    lru_error               recoverable        mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(19);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(19);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(19);
+
+    // 20    eDRAM error             channel checkstop  mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(20);            
+    l_ecmd_rc |= l_mbs_fir_action1.clearBit(20);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(20);
+
+    // 21    emergency_throttle_set  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(21);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(21);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(21);
+
+    // 22    Host Inband Read Error  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(22);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(22);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(22);
+
+    // 23    Host Inband Write Error recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(23);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(23);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(23);
+
+    // 24    OCC Inband Read Error   recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(24);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(24);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(24);
+
+    // 25    OCC Inband Write Error  recoverable        mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(25);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(25);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(25);
+
+    // 26    srb_buffer_ce           recoverable        mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(26);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(26);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(26);
+
+    // 27    srb_buffer_ue           recoverable         mask (until unmask_fetch_errors)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(27);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(27);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(27);
+
+    // 28    srb_buffer_sue          recoverable         mask (forever)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(28);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(28);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(28);
+
+    // 29    internal_scom_error     recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(29);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(29);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(29);
+
+    // 30    internal_scom_error_copy recoverable        mask (tbd)
+    l_ecmd_rc |= l_mbs_fir_action0.clearBit(30);            
+    l_ecmd_rc |= l_mbs_fir_action1.setBit(30);
+    l_ecmd_rc |= l_mbs_fir_mask_or.setBit(30);
+
+    // 31:63    Reserved                not implemented, so won't touch these
+    
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_OR_0x02011405, l_mbs_fir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_inband_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_ddrphy_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    FAPI_INF("ENTER mss_unmask ddrphy_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // DDRPHY_FIR_REG
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_ddrphy_fir_mask(64);
+    ecmdDataBufferBase l_ddrphy_fir_mask_or(64);
+    ecmdDataBufferBase l_ddrphy_fir_mask_and(64);        
+    ecmdDataBufferBase l_ddrphy_fir_action0(64);
+    ecmdDataBufferBase l_ddrphy_fir_action1(64);
+
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+        
+    l_ecmd_rc |= l_ddrphy_fir_action0.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_action1.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.flushTo0();
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.setBit(48,16);
+        
+    // 0:47 Reserved                not implemented, so won't touch these
+    
+    // 48   ddr0_fsm_ckstp          channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(48);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(48);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(48);
+    
+    // 49   ddr0_parity_ckstp       channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(49);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(49);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(49);
+
+    // 50   ddr0_calibration_error  recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(50);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(50);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(50);
+
+    // 51   ddr0_fsm_err            recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(51);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(51);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(51);
+
+    // 52   ddr0_parity_err         recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(52);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(52);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(52);
+
+    // 53   ddr01_fir_parity_err    recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(53);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(53);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(53);
+    
+    // 54   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(54);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(54);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(54);
+
+    // 55   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(55);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(55);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(55);
+
+    // 56   ddr1_fsm_ckstp          channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(56);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(56);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(56);
+    
+    // 57   ddr1_parity_ckstp       channel checkstop   unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(57);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(57);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(57);
+
+    // 58   ddr1_calibration_error  recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(58);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(58);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(58);
+
+    // 59   ddr1_fsm_err            recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(59);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(59);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(59);
+
+    // 60   ddr1_parity_err         recoverable         unmask
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(60);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(60);
+    l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(60);
+
+    // 61   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(61);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(61);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(61);
+
+    // 62   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(62);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(62);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(62);
+
+    // 63   Reserved                recoverable         mask (forever)
+    l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(63);            
+    l_ecmd_rc |= l_ddrphy_fir_action1.setBit(63);
+    l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(63);
+
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_OR_0x800200950301143f, l_ddrphy_fir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_AND_0x800200940301143f, l_ddrphy_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f, l_ddrphy_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    //*************************
+    //*************************
+    // MBAFIR
+    //*************************
+    //*************************
+    
+    ecmdDataBufferBase l_mbafir_mask(64);
+    ecmdDataBufferBase l_mbafir_mask_or(64);
+    ecmdDataBufferBase l_mbafir_mask_and(64);
+    ecmdDataBufferBase l_mbafir_action0(64);
+    ecmdDataBufferBase l_mbafir_action1(64);
+            
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_0x03010603,
+                               l_mbafir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbafir_action0.flushTo0();
+    l_ecmd_rc |= l_mbafir_action1.flushTo0();
+    l_ecmd_rc |= l_mbafir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbafir_mask_and.flushTo1();
+
+
+    // 0	Invalid_Maint_Cmd           recoverable         masked (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(0);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(0);
+    
+    // 1	Invalid_Maint_Address       recoverable         masked (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(1);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(1);
+
+    // 2	Multi_address_Maint_timeout recoverable         masked (until mss_unmask_maint_errors)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(2);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(2);
+
+    // 3	Internal_fsm_error          recoverable         unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(3);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(3);
+
+    // 4	MCBIST_Error                recoverable         mask (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(4);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(4);
+    
+    // 5	scom_cmd_reg_pe             recoverable         unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(5);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(5);
+
+    // 6	channel_chkstp_err          channel checkstop   unmask
+    l_ecmd_rc |= l_mbafir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbafir_action1.clearBit(6);
+    l_ecmd_rc |= l_mbafir_mask_and.clearBit(6);
+
+    // 7	wrd_caw2_data_ce_ue_err     recoverable         masked (until mss_unmask_maint_errors)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(7);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(7);
+
+    // 8:14	RESERVED                    recoverable         mask (forever)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(8,7);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(8,7);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(8,7);
+
+    // 15	internal scom error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(15);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(15);
+
+    // 16	internal scom error clone   recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbafir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbafir_action1.setBit(16);
+    l_ecmd_rc |= l_mbafir_mask_or.setBit(16);
+
+
+    // 17:63 RESERVED           not implemented, so won't touch these
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRACT0_0x03010606,
+                               l_mbafir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRACT1_0x03010607,
+                               l_mbafir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_OR_0x03010605,
+                               l_mbafir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_AND_0x03010604,
+                               l_mbafir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRACT0_0x03010606,
+                               l_mbafir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRACT1_0x03010607,
+                               l_mbafir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target,
+                               MBA01_MBAFIRMASK_0x03010603,
+                               l_mbafir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_ddrphy_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    FAPI_INF("ENTER mss_unmask_draminit_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_or(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);        
+    ecmdDataBufferBase l_mbacalfir_action0(64);
+    ecmdDataBufferBase l_mbacalfir_action1(64);
+
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+        
+    l_ecmd_rc |= l_mbacalfir_action0.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_action1.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+    
+    // 0	MBA Recoverable Error       recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(0);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(0);
+
+    // 1	MBA Nonrecoverable Error    channel checkstop   mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(1);
+
+    // 2	Refresh Overrun             recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(2);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(2);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(2);
+
+    // 3	WAT error                   recoverable         mask (forever)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(3);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(3);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(3);
+
+    // 4	RCD Parity Error 0          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(4);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(4);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4);
+
+    // 5	ddr0_cal_timeout_err        recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(5);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(5);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(5);
+
+    // 6	ddr1_cal_timeout_err        recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(6);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(6);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(6);
+
+    // 7	RCD Parity Error 1          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(7);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(7);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7);
+
+
+    // 8	mbx to mba par error        channel checkstop   mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(8);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(8);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(8);
+
+    // 9	mba_wrd ue                  recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(9);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(9);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(9);
+
+    // 10	mba_wrd ce                  recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(10);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(10);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(10);
+
+    // 11	mba_maint ue                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(11);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(11);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(11);
+
+    // 12	mba_maint ce                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(12);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(12);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(12);
+
+    // 13	ddr_cal_reset_timeout       channel checkstop   mask
+    // TODO: Leaving masked until I find proper spot to unmask this
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(13);            
+    l_ecmd_rc |= l_mbacalfir_action1.clearBit(13);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(13);
+
+    // 14	wrq_data_ce                 recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(14);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(14);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(14);
+
+    // 15	wrq_data_ue                 recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(15);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(15);
+
+    // 16	wrq_data_sue                recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(16);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(16);
+
+    // 17	wrq_rrq_hang_err            recoverable         mask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(17);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(17);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(17);
+
+    // 18	sm_1hot_err                 recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(18);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(18);
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(18);
+
+    // 19	wrd_scom_error              recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(19);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(19);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(19);
+
+    // 20	internal_scom_error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(20);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(20);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(20);
+
+    // 21	internal_scom_error_copy    recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbacalfir_action0.clearBit(21);            
+    l_ecmd_rc |= l_mbacalfir_action1.setBit(21);
+    l_ecmd_rc |= l_mbacalfir_mask_or.setBit(21);
+
+    // 22-63	Reserved            not implemented, so won't touch these          
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_draminit_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_training_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_training_errors( 
+                                             const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    FAPI_INF("ENTER mss_unmask_draminit_training_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already unmasked the approproiate MBACALFIR errors
+    // following mss_draminit. So all we will do here is unmask a few more
+    // errors that would be considered valid after the mss_draminit_training
+    // procedure. 
+    
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+        
+    // 0	MBA Recoverable Error       recoverable         umask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(0);
+
+    // 4	RCD Parity Error 0          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+
+    // 7	RCD Parity Error 1          recoverable         unmask (only if set)
+    // TODO: Unmask, only if set, only if ISD DIMM
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    
+    
+    FAPI_INF("EXIT mss_unmask_draminit_training_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_training_advanced_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( 
+                                             const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    FAPI_INF("ENTER mss_unmask_draminit_training_advanced_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors and 
+    // mss_unmask_draminit_training has already been
+    // called, which has already unmasked the approproiate MBACALFIR errors
+    // following mss_draminit and mss_draminit_training. So all we will do here
+    // is unmask a few more errors that would be considered valid after the
+    // mss_draminit_training_advanced procedure. 
+    
+
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();            
+    
+    // 4	RCD Parity Error 0          recoverable         unmask 
+    // TODO: Unmask, only if ISD DIMM
+
+    // 7	RCD Parity Error 1          recoverable         unmask 
+    // TODO: Unmask, only if ISD DIMM
+
+    // 8	mbx to mba par error        channel checkstop   unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(8);
+
+    // 11	mba_maint ue                recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(11);
+
+    // 12	mba_maint ce                recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(12);
+
+    // 17	wrq_rrq_hang_err            recoverable         unmask
+    l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(17);
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************ 
+    
+
+    //*************************
+    //*************************
+    // MBSFIR
+    //*************************
+    //*************************    
+    
+    fapi::Target l_targetCentaur;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+    uint32_t l_mbsfir_mask_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_0x02011603,     MBS23_MBSFIRMASK_0x02011703};
+
+    uint32_t l_mbsfir_mask_or_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_OR_0x02011605,  MBS23_MBSFIRMASK_OR_0x02011705};
+
+    uint32_t l_mbsfir_mask_and_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRMASK_AND_0x02011604, MBS23_MBSFIRMASK_AND_0x02011704};
+
+    uint32_t l_mbsfir_action0_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRACT0_0x02011606,     MBS23_MBSFIRACT0_0x02011706};
+
+    uint32_t l_mbsfir_action1_address[2]={
+    // port0/1                       port2/3
+    MBS01_MBSFIRACT1_0x02011607,     MBS23_MBSFIRACT1_0x02011707};
+
+    ecmdDataBufferBase l_mbsfir_mask(64);
+    ecmdDataBufferBase l_mbsfir_mask_or(64);
+    ecmdDataBufferBase l_mbsfir_mask_and(64);        
+    ecmdDataBufferBase l_mbsfir_action0(64);
+    ecmdDataBufferBase l_mbsfir_action1(64);
+
+    // Get Centaur target for the given MBA
+    l_rc = fapiGetParentChip(i_target, l_targetCentaur);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting Centaur parent target for the given MBA");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // Get MBA position: 0 = mba01, 1 = mba23
+    l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting MBA position");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_address[l_mbaPosition], 
+                               l_mbsfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+                
+    l_ecmd_rc |= l_mbsfir_action0.flushTo0();
+    l_ecmd_rc |= l_mbsfir_action1.flushTo0();
+    l_ecmd_rc |= l_mbsfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_mbsfir_mask_and.flushTo1();
+
+    // 0	scom_par_errors             recoverable         unmask
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(0);
+    l_ecmd_rc |= l_mbsfir_mask_and.clearBit(0);
+
+    // 1	mbx_par_errors              channel checkstop   unmask
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_mbsfir_action1.clearBit(1);
+    l_ecmd_rc |= l_mbsfir_mask_and.clearBit(1);
+
+    // 2:14	RESERVED                    recoverable         mask (forever)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(2,13);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(2,13);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(2,13);
+
+    // 15	internal scom error         recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(15);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(15);
+
+    // 16	internal scom error clone   recoverable         mask (tbd)
+    l_ecmd_rc |= l_mbsfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_mbsfir_action1.setBit(16);
+    l_ecmd_rc |= l_mbsfir_mask_or.setBit(16);
+
+    // 17:63 RESERVED           not implemented, so won't touch these
+    
+        
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action0_address[l_mbaPosition], 
+                               l_mbsfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action1_address[l_mbaPosition], 
+                               l_mbsfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_or_address[l_mbaPosition], 
+                               l_mbsfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_and_address[l_mbaPosition], 
+                               l_mbsfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action0_address[l_mbaPosition], 
+                               l_mbsfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_action1_address[l_mbaPosition], 
+                               l_mbsfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    l_rc = fapiGetScom_w_retry(l_targetCentaur, 
+                               l_mbsfir_mask_address[l_mbaPosition], 
+                               l_mbsfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+   
+    
+    FAPI_INF("EXIT mss_unmask_draminit_training_advanced_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_maint_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    // Target: Centaur
+    
+    FAPI_INF("ENTER mss_unmask_maint_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0; 
+    std::vector<fapi::Target> l_mbaChiplets;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);    
+
+    ecmdDataBufferBase l_mbafir_mask(64);
+    ecmdDataBufferBase l_mbafir_mask_and(64);
+           
+    ecmdDataBufferBase l_mbaspa_mask(64);
+
+    uint32_t l_mbeccfir_mask_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_0x02011443,    MBS_ECC1_MBECCFIR_MASK_0x02011483};
+
+    uint32_t l_mbeccfir_mask_or_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485};
+
+    uint32_t l_mbeccfir_mask_and_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484};
+
+    uint32_t l_mbeccfir_action0_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_ACTION0_0x02011446, MBS_ECC1_MBECCFIR_ACTION0_0x02011486};
+
+    uint32_t l_mbeccfir_action1_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_ACTION1_0x02011447, MBS_ECC1_MBECCFIR_ACTION1_0x02011487};
+
+    ecmdDataBufferBase l_mbeccfir_mask(64);
+    ecmdDataBufferBase l_mbeccfir_mask_or(64);
+    ecmdDataBufferBase l_mbeccfir_mask_and(64);
+    ecmdDataBufferBase l_mbeccfir_action0(64);
+    ecmdDataBufferBase l_mbeccfir_action1(64);
+
+
+
+    // Get associated functional MBAs on this centaur
+    l_rc = fapiGetChildChiplets(i_target,
+                                fapi::TARGET_TYPE_MBA_CHIPLET,
+                                l_mbaChiplets);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting functional MBAs on this Centaur");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+
+
+
+
+        //*************************
+        //*************************
+        // MBACALFIR
+        //*************************
+        //*************************    
+
+
+        // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+        // called, which has already set the MBACALFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_draminit_errors,
+        // mss_unmask_draminit_training and mss_unmask_draminit_training_advanced
+        // have already been called, which have already unmasked the approproiate
+        // MBACALFIR errors following mss_draminit, mss_draminit_training, and
+        // mss_unmask_draminit_training_advanced. So all we will do here
+        // is unmask a few more errors that would be considered valid after the
+        // mss_draminit_mc procedure. 
+    
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask);       
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+        
+        l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();            
+                    
+        // 1	MBA Nonrecoverable Error    channel checkstop   unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(1);
+
+        // 2	Refresh Overrun             recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(2);
+        
+        // 5	ddr0_cal_timeout_err        recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(5);
+
+        // 6	ddr1_cal_timeout_err        recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(6);
+        
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_AND_0x03010404,
+                                   l_mbacalfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask);       
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************ 
+    
+
+        //*************************
+        //*************************
+        // MBAFIR
+        //*************************
+        //*************************    
+        
+        // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors has already been
+        // called, which has already set the MBAFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors,
+        // has already been called, which has already unmasked the approproiate
+        // MBAFIR errors following mss_ddr_phy_reset. So all we will do here
+        // is unmask a few more errors that would be considered valid after the
+        // mss_draminit_mc procedure. 
+        
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_0x03010603,
+                                   l_mbafir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+                    
+        l_ecmd_rc |= l_mbafir_mask_and.flushTo1();
+
+        // 2	Multi_address_Maint_timeout recoverable         unmask
+        l_ecmd_rc |= l_mbafir_mask_and.clearBit(2);
+
+
+        // 7	wrd_caw2_data_ce_ue_err     recoverable         unmask
+        l_ecmd_rc |= l_mbafir_mask_and.clearBit(7);
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_AND_0x03010604,
+                                   l_mbafir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBAFIRMASK_0x03010603,
+                                   l_mbafir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+
+
+        //*************************
+        //*************************
+        // MBASPA
+        //*************************
+        //*************************
+        
+                
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        // 0	Command_Complete                             masked (DD1 broken)
+        l_ecmd_rc |= l_mbaspa_mask.setBit(0);            
+
+        // 1	Hard_CE_ETE_Attn                             unmask
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Hards counted during super fast read, but can't be called 
+        // true hard CEs since super fast read doesn't write back and read again.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(1);            
+
+        // 2	Soft_CE_ETE_Attn                             unmask
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Softs not counted during super fast read.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(2);            
+
+        // 3	Intermittent_ETE_Attn                        unmask
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        // NOTE: Intermittents not counted during super fast read.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(3);            
+
+        // 4	RCE_ETE_Attn                                 unmask
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(4);            
+
+        // 5	Emergency_Throttle_Attn                      masked
+        l_ecmd_rc |= l_mbaspa_mask.setBit(5);            
+
+        // 6	Firmware_Attn0                               masked
+        l_ecmd_rc |= l_mbaspa_mask.setBit(6);            
+
+        // 7	Firmware_Attn1                               masked
+        l_ecmd_rc |= l_mbaspa_mask.setBit(7);            
+
+        // 8	wat_debug_attn                               unmask (DD1 workaround)
+        l_ecmd_rc |= l_mbaspa_mask.clearBit(8);            
+
+        // 9	Spare_Attn1                                  masked
+        l_ecmd_rc |= l_mbaspa_mask.setBit(9);            
+
+        // 10	MCBIST_Done                                  masked
+        l_ecmd_rc |= l_mbaspa_mask.setBit(10);            
+
+        // 11:63 RESERVED     not implemented, so won't touch these
+                    
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+        
+        // Write mask
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBSPAMSKQ_0x03010614,
+                                   l_mbaspa_mask);
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        //************************************************    
+
+
+
+        //*************************
+        //*************************
+        // MBECCFIR
+        //*************************
+        //*************************    
+        
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+        
+        // Read mask
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+
+
+        //(Action0, Action1, Mask)
+        //
+        // (0,0,0) = checkstop
+        // (0,1,0) = recoverable error
+        // (1,0,0) = report unused
+        // (1,1,0) = machine check
+        // (x,x,1) = error is masked
+                    
+        l_ecmd_rc |= l_mbeccfir_action0.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_action1.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0();
+        l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1();
+
+        // 0:7	Memory MPE Rank 0:7         recoverable         mask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(0,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(0,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(0,8);
+
+        // 8:15	Reserved                    recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(8,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(8,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(8,8);
+        
+        // 16	Memory NCE                  recoverable         mask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(16);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(16);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(16);
+
+        // 17	Memory RCE                  recoverable         mask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(17);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(17);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(17);
+
+        // 18	Memory SUE                  recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(18);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(18);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(18);
+
+        // 19	Memory UE                   recoverable         mask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(19);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(19);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(19);
+
+        // 20:27	Maint MPE Rank 0:7      recoverable         unmask
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(20,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(20,8);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8);
+
+        // 28:35	Reserved                recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(28,8);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(28,8);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(28,8);
+        
+        // 36	Maintenance NCE             recoverable         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(36);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(36);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(36);
+
+        // 37	Maintenance SCE             recoverable         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(37);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(37);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(37);
+
+        // 38	Maintenance MCE             recoverable         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(38);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(38);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(38);
+
+        // 39	Maintenance RCE             recoverable         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(39);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(39);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(39);
+
+        // 40	Maintenance SUE             recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(40);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(40);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(40);
+
+        // 41	Maintenance UE              recoverable         unmask (tbd)
+        // NOTE: FW memdiags may want to mask this if they want to wait till
+        // cmd gets to end of rank before getting any attention.
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(41);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(41);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41);
+
+        // 42	MPE during maintenance mark mode  recoverable   mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(42);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(42);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(42);
+
+        // 43	Prefetch Memory UE          recoverable         mask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(43);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(43);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(43);
+
+        // 44	Memory RCD parity error     recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(44);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(44);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(44);
+
+        // 45	Maint RCD parity error.     recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(45);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(45);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45);
+
+        // 46	Recoverable reg parity      recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(46);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(46);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(46);
+
+
+        // 47	Unrecoverable reg parity    channel checkstop   unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(47);            
+        l_ecmd_rc |= l_mbeccfir_action1.clearBit(47);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(47);
+
+        // 48	Maskable reg parity error   recoverable         mask (forever)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(48);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(48);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(48);
+
+        // 49	ecc datapath parity error   channel checkstop   unmask
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(49);            
+        l_ecmd_rc |= l_mbeccfir_action1.clearBit(49);
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(49);
+
+        // 50	internal scom error         recovereble         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(50);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(50);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(50);
+
+        // 51	internal scom error clone   recovereble         mask (tbd)
+        l_ecmd_rc |= l_mbeccfir_action0.clearBit(51);            
+        l_ecmd_rc |= l_mbeccfir_action1.setBit(51);
+        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(51);
+
+        // 52:63	Reserved    not implemented, so won't touch these
+
+
+        
+            
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write action0
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_action0_address[l_mbaPosition], 
+                                   l_mbeccfir_action0); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        // Write action1
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_action1_address[l_mbaPosition], 
+                                   l_mbeccfir_action1); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        
+        // Write mask OR
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_or_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_or); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_and_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_action0_address[l_mbaPosition], 
+                                   l_mbeccfir_action0); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_action1_address[l_mbaPosition], 
+                                   l_mbeccfir_action1); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+
+   } // End for loop through functional MBAs on this Centaur
+    
+    FAPI_INF("EXIT mss_unmask_maint_errors()"); 
+
+    return i_bad_rc;
+}
+
+
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_fetch_errors
+//------------------------------------------------------------------------------
+                                           
+fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc )
+                                           
+{
+
+    // Target: Centaur
+
+    FAPI_INF("ENTER mss_unmask_fetch_errors()"); 
+    
+    fapi::ReturnCode l_rc;
+    uint32_t l_ecmd_rc = 0;            
+
+
+    //*************************
+    //*************************
+    // SCAC_LFIR
+    //*************************
+    //*************************    
+    
+    ecmdDataBufferBase l_scac_lfir_mask(64);
+    ecmdDataBufferBase l_scac_lfir_mask_or(64);
+    ecmdDataBufferBase l_scac_lfir_mask_and(64);
+    ecmdDataBufferBase l_scac_lfir_action0(64);
+    ecmdDataBufferBase l_scac_lfir_action1(64);
+    
+    // Read mask
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+
+    //(Action0, Action1, Mask)
+    //
+    // (0,0,0) = checkstop
+    // (0,1,0) = recoverable error
+    // (1,0,0) = report unused
+    // (1,1,0) = machine check
+    // (x,x,1) = error is masked
+
+    l_ecmd_rc |= l_scac_lfir_action0.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_action1.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_mask_or.flushTo0();
+    l_ecmd_rc |= l_scac_lfir_mask_and.flushTo1();
+                
+    // 0	I2CMInvAddr                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(0);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(0);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(0);
+    
+    // 1	I2CMInvWrite                recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(1);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(1);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(1);
+
+    // 2	I2CMInvRead                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(2);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(2);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(2);
+
+    // 3	I2CMApar                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(3);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(3);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(3);
+
+    // 4	I2CMPar                     recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(4);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(4);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(4);
+
+    // 5	I2CMLBPar                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(5);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(5);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(5);
+
+    // 6:9	Expansion                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(6,4);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(6,4);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(6,4);    
+    
+    // 10	I2CMInvCmd                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(10);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(10);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(10);
+
+    // 11	I2CMPErr                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(11);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(11);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(11);
+
+    // 12	I2CMOverrun                 recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(12);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(12);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(12);
+
+    // 13	I2CMAccess                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(13);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(13);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(13);
+
+    // 14	I2CMArb                     recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(14);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(14);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(14);
+
+    // 15	I2CMNack                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(15);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(15);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(15);
+
+    // 16	I2CMStop                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(16);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(16);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(16);
+
+    // 17	LocalPib1                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(17);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(17);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(17);
+
+    // 18	LocalPib2                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(18);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(18);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(18);
+
+    // 19	LocalPib3                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(19);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(19);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(19);
+
+    // 20	LocalPib4                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(20);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(20);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(20);
+
+    // 21	LocalPib5                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(21);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(21);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(21);
+
+    // 22	LocalPib6                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(22);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(22);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(22);
+
+    // 23	LocalPib7                   recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(23);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(23);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(23);
+
+    // 24	StallError                  recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(24);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(24);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(24);
+
+    // 25	RegParErr                   channel checkstop   unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(25);            
+    l_ecmd_rc |= l_scac_lfir_action1.clearBit(25);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(25);
+
+    // 26	RegParErrX                  channel checkstop   unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(26);            
+    l_ecmd_rc |= l_scac_lfir_action1.clearBit(26);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(26);
+
+    // 27:31	Reserved                recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(27,5);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(27,5);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(27,5);
+    
+    // 32	SMErr                       recoverable         unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(32);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(32);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(32);
+    
+    // 33	RegAccErr                   recoverable         unmask
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(33);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(33);
+    l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(33);
+
+    // 34	ResetErr                    recoverable         masked (forever)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(34);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(34);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(34);
+
+    // 35	internal_scom_error         recoverable         masked (tbd)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(35);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(35);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(35);
+
+    // 36	internal_scom_error_clone   recoverable         masked (tbd)
+    l_ecmd_rc |= l_scac_lfir_action0.clearBit(36);            
+    l_ecmd_rc |= l_scac_lfir_action1.setBit(36);
+    l_ecmd_rc |= l_scac_lfir_mask_or.setBit(36);
+
+    // 37:63	Reserved
+    // Can we write to these bits?
+
+
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write action0
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write action1
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1);
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    
+    // Write mask OR
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_OR_0x020115C5, l_scac_lfir_mask_or); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_AND_0x020115C4, l_scac_lfir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+    l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+
+
+    //*************************
+    //*************************
+    // MBS_FIR_REG
+    //*************************
+    //*************************
+    
+    
+    // NOTE: In the IPL sequence, mss_unmask_inband_errors has already been
+    // called, which has already set the MBS_FIR_REG action regs to their 
+    // runtime values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, mss_unmask_inband_errors,
+    // has already been called, which has already unmasked the approproiate
+    // MBS_FIR_REG errors following mss_unmask_inband_errors. So all we will do 
+    // here is unmask errors requiring mainline traffic which would be 
+    // considered valid after the mss_thermal_init procedure. 
+    
+
+    ecmdDataBufferBase l_mbs_fir_mask(64);
+    ecmdDataBufferBase l_mbs_fir_mask_and(64);
+    
+    // Read mask 
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }    
+    
+    // TODO: Here is where I could clear bits that were bogus, before I unmask 
+    //       them. But typically we are expecting the bit set at this point
+    //       to be valid errors for PRD to log.
+
+    l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1();
+    
+    // 2    invalid_address_error   channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(2);
+
+    // 3    external_timeout        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(3);
+    
+    // 4    internal_timeout        channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(4);
+
+    // 9    cache_srw_ce            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(9);
+
+    // 10    cache_srw_ue           recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(10);
+
+    // 12    cache_co_ce            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(12);
+
+    // 13    cache_co_ue            recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(13);
+
+    // 15    dir_ce                 recoverable         unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(15);
+
+    // 16    dir_ue                 channel checkstop   unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(16);
+
+    // 18    dir_all_members_deleted channel checkstop  unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(18);
+
+    // 19    lru_error               recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(19);
+
+    // 20    eDRAM error             channel checkstop  unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(20);
+
+    // 26    srb_buffer_ce           recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(26);
+
+    // 27    srb_buffer_ue           recoverable        unmask
+    l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(27);
+    
+    if(l_ecmd_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+        l_rc.setEcmdError(l_ecmd_rc);
+        return l_rc;
+    }                                                                              
+
+    // Write mask AND
+    l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+
+    //************************************************    
+    // DEBUG: read them all back to verify
+    l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); 
+    if(l_rc)
+    {
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);        
+        return l_rc;
+    }
+
+    //************************************************    
+
+
+    //*************************
+    //*************************
+    // MBECCFIR
+    //*************************
+    //*************************    
+    
+    std::vector<fapi::Target> l_mbaChiplets;
+    uint8_t l_mbaPosition;             // 0 = mba01, 1 = mba23
+
+
+    uint32_t l_mbeccfir_mask_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_0x02011443,MBS_ECC1_MBECCFIR_MASK_0x02011483};
+
+    uint32_t l_mbeccfir_mask_and_address[2]={
+    // port0/1                            port2/3
+    MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484};
+
+    ecmdDataBufferBase l_mbeccfir_mask(64);
+    ecmdDataBufferBase l_mbeccfir_mask_and(64);
+
+
+    // Get associated functional MBAs on this centaur
+    l_rc = fapiGetChildChiplets(i_target,
+                                fapi::TARGET_TYPE_MBA_CHIPLET,
+                                l_mbaChiplets);
+    if(l_rc)
+    {
+        FAPI_ERR("Error getting functional MBAs on this Centaur");
+        // Log passed in error before returning with new error
+        if (i_bad_rc) fapiLogError(i_bad_rc);                
+        return l_rc;
+    }    
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Get MBA position: 0 = mba01, 1 = mba23
+        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition);
+        if(l_rc)
+        {
+            FAPI_ERR("Error getting MBA position");
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);                
+            return l_rc;
+        }    
+    
+        // Read mask
+        l_rc = fapiGetScom_w_retry(i_target, 
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+    
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+                    
+        // NOTE: In the IPL sequence, mss_unmask_maint_errors has already been
+        // called, which has already set the MBECCFIR action regs to their runtime
+        // values, so no need to touch the action regs here.
+
+        // NOTE: In the IPL sequence, mss_unmask_maint_errors,
+        // has already been called, which has already unmasked the approproiate
+        // MBECCFIR errors following mss_unmask_maint_errors. So all we will do 
+        // here is unmask errors requiring mainline traffic which would be 
+        // considered valid after the mss_thermal_init procedure. 
+
+        l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1();
+
+        // 0:7	Memory MPE Rank 0:7         recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(0,8);
+
+        // 16	Memory NCE                  recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(16);
+
+        // 17	Memory RCE                  recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(17);
+
+        // 19	Memory UE                   recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(19);
+        
+        // 43	Prefetch Memory UE          recoverable         unmask
+        l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(43);
+
+            
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+        
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(i_target,
+                                   l_mbeccfir_mask_and_address[l_mbaPosition], 
+                                   l_mbeccfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(i_target,
+                                   l_mbeccfir_mask_address[l_mbaPosition], 
+                                   l_mbeccfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+    }
+    
+    
+    //*************************
+    //*************************
+    // MBACALFIR
+    //*************************
+    //*************************
+
+    ecmdDataBufferBase l_mbacalfir_mask(64);
+    ecmdDataBufferBase l_mbacalfir_mask_and(64);        
+    
+    // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been
+    // called, which has already set the MBACALFIR action regs to their runtime
+    // values, so no need to touch the action regs here.
+
+    // NOTE: In the IPL sequence, various bits have already been unmasked
+    // after the approproiate procedures. So all we will do here is unmask
+    // errors requiring mainline traffic which would be considered valid after
+    // the mss_thermal_init procedure. 
+
+    // Loop through functional MBAs on this Centaur
+    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
+    {
+
+        // Read mask
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+        
+        // TODO: Here is where I could clear bits that were bogus, before I unmask 
+        //       them. But typically we are expecting the bit set at this point
+        //       to be valid errors for PRD to log.
+            
+        l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();        
+        
+        // 9	mba_wrd ue                  recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(9);
+
+        // 10	mba_wrd ce                  recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(10);
+
+        // 14	wrq_data_ce                 recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(14);
+
+        // 15	wrq_data_ue                 recoverable         unmask
+        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(15);
+
+        if(l_ecmd_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+
+            l_rc.setEcmdError(l_ecmd_rc);
+            return l_rc;
+        }                                                                              
+
+        // Write mask AND
+        l_rc = fapiPutScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_AND_0x03010404,
+                                   l_mbacalfir_mask_and); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+
+        //************************************************    
+        // DEBUG: read them all back to verify
+        l_rc = fapiGetScom_w_retry(l_mbaChiplets[i],
+                                   MBA01_MBACALFIR_MASK_0x03010403,
+                                   l_mbacalfir_mask); 
+        if(l_rc)
+        {
+            // Log passed in error before returning with new error
+            if (i_bad_rc) fapiLogError(i_bad_rc);        
+            return l_rc;
+        }
+
+        //************************************************    
+    }
+
+
+   
+    
+    FAPI_INF("EXIT mss_unmask_fetch_errors()"); 
+
+    return i_bad_rc;
+}
+
+//------------------------------------------------------------------------------
+// fapiGetScom_w_retry
+//------------------------------------------------------------------------------
+fapi::ReturnCode fapiGetScom_w_retry(const fapi::Target& i_target,
+                                     const uint64_t i_address,
+                                     ecmdDataBufferBase & o_data)
+{
+    fapi::ReturnCode l_rc;
+    
+    l_rc = fapiGetScom(i_target, i_address, o_data);
+    if(l_rc)
+    {
+        FAPI_ERR("1st Centaur fapiGetScom failed, so attempting retry.");
+
+        // Log centaur scom error
+        fapiLogError(l_rc);        
+
+        // Retry centaur scom with assumption that retry is done via FSI,
+        // which may still work.
+        // NOTE: If scom fail was due to channel fail a retry via FSI may
+        // work. But if scom fail was due to PIB error, retry via FSI may
+        // also fail.
+        l_rc = fapiGetScom(i_target, i_address, o_data); 
+        if(l_rc)
+        {
+            FAPI_ERR("fapiGetScom retry via FSI failed.");       
+            // Retry didn't work either so give up and pass 
+            // back centaur scom error
+        }
+    }    
+    
+    return l_rc;
+}
+
+
+//------------------------------------------------------------------------------
+// fapiPutScom_w_retry
+//------------------------------------------------------------------------------
+fapi::ReturnCode fapiPutScom_w_retry(const fapi::Target& i_target,
+                                     const uint64_t i_address,
+                                     ecmdDataBufferBase & i_data)
+{
+    fapi::ReturnCode l_rc;
+    
+    // NOTE: Inband scom device driver takes care of read to special reg after
+    // an inband scom write in order to detect SUE
+    l_rc = fapiPutScom(i_target, i_address, i_data);
+    if(l_rc)
+    {
+        FAPI_ERR("1st Centaur fapiPutScom failed, so attempting retry.");
+
+        // Log centaur scom error
+        fapiLogError(l_rc);        
+
+        // Retry centaur scom with assumption that retry is done via FSI,
+        // which may still work.
+        // NOTE: If scom fail was due to channel fail a retry via FSI may
+        // work. But if scom fail was due to PIB error, retry via FSI may
+        // also fail.
+        l_rc = fapiPutScom(i_target, i_address, i_data); 
+        if(l_rc)
+        {
+            FAPI_ERR("fapiPutScom retry via FSI failed.");       
+            // Retry didn't work either so give up and pass 
+            // back centaur scom error
+        }
+    }    
+    
+    return l_rc;
+}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H
new file mode 100644
index 000000000..e779b9725
--- /dev/null
+++ b/src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H
@@ -0,0 +1,275 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_training/mss_unmask_errors.H $          */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_unmask_errors.H,v 1.1 2012/09/05 21:04:20 gollub Exp $
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|   Date:  | Author: | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.1   | 09/05/12 | gollub  | Created
+
+#ifndef _MSS_UNMASK_ERRORS_H
+#define _MSS_UNMASK_ERRORS_H
+
+/** @file  mss_unmask_errors.H
+ *  @brief Utility functions to set action regs and unmask FIR bits 
+ *         at the end of various mss IPL procedures.
+ */
+
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include <ecmdDataBufferBase.H>
+
+
+
+//------------------------------------------------------------------------------
+// Constants and enums
+//------------------------------------------------------------------------------
+
+
+
+
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_inband_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of proc_cen_set_inband_addr.C
+ *         Sets action regs and mask settings for inband errors to their 
+ *         runtime settings.
+ *
+ * @param  i_target         Centaur target
+ * @param  i_bad_rc         If proc_cen_set_inband_addr.C already has a bad rc
+ *                          before it calls this function, we pass it in as 
+ *                          i_bad_rc. If this function gets it's own bad local 
+ *                          l_rc, i_bad_rc will be commited, and l_rc will be 
+ *                          passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_ddrphy_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_ddr_phy_reset.C.
+ *         Sets action regs and mask settings for ddr phy errors to their 
+ *         runtime settings.
+ *
+ * @param  i_target         MBA target
+ * @param  i_bad_rc         If mss_ddr_phy_reset.C already has a bad rc
+ *                          before it calls this function, we pass it in as 
+ *                          i_bad_rc. If this function gets it's own bad local 
+ *                          l_rc, i_bad_rc will be commited, and l_rc will be 
+ *                          passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target,
+                                           fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_draminit.C.
+ *         Sets MBACALFIR action regs to their runtime settings, and unmasks
+ *         errors that are valid for PRD to handle after mss_draminit procedure.
+ *
+ * @param  i_target         MBA target
+ * @param  i_bad_rc         If mss_draminit.C already has a bad rc
+ *                          before it calls this function, we pass it in as 
+ *                          i_bad_rc. If this function gets it's own bad local 
+ *                          l_rc, i_bad_rc will be commited, and l_rc will be 
+ *                          passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target,
+                                             fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_training_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_draminit_training.C.
+ *         Unmasks MBACALFIR errors that are valid for PRD to handle after
+ *         mss_draminit_training procedure.
+ *
+ * @param  i_target         MBA target
+ * @param  i_bad_rc         If mss_draminit_training.C already has a bad rc
+ *                          before it calls this function, we pass it in as 
+ *                          i_bad_rc. If this function gets it's own bad local 
+ *                          l_rc, i_bad_rc will be commited, and l_rc will be 
+ *                          passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_draminit_training_errors( 
+                                            const fapi::Target & i_target,
+                                            fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_draminit_training_advanced_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_draminit_training_advanced.C.
+ *         Unmasks MBACALFIR errors that are valid for PRD to handle after
+ *         mss_draminit_training_advanced procedure.
+ *
+ * @param  i_target         MBA target
+ * @param  i_bad_rc         If mss_draminit_training_advanced.C already has a 
+ *                          bad rc before it calls this function, we pass it in 
+ *                          as i_bad_rc. If this function gets it's own bad  
+ *                          local l_rc, i_bad_rc will be commited, and l_rc will 
+ *                          be passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( 
+                                            const fapi::Target & i_target,
+                                            fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_maint_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_draminit_mc.C.
+ *         Sets action regs and unmasks maint errors prior to the maint logic
+ *         being used in memdiags so that PRD will be able to handle them 
+ *         if they happen during memdiags.
+ *
+ * @param  i_target         MBA target
+ * @param  i_bad_rc         If mss_draminit_mc already has a 
+ *                          bad rc before it calls this function, we pass it in 
+ *                          as i_bad_rc. If this function gets it's own bad  
+ *                          local l_rc, i_bad_rc will be commited, and l_rc will 
+ *                          be passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc );
+
+
+//------------------------------------------------------------------------------
+// mss_unmask_fetch_errors
+//------------------------------------------------------------------------------
+
+
+/**
+ * @brief  To be called at the end of mss_thermal_init.C.
+ *         Sets action regs and unmasks fetch errors prior to the start of
+ *         mainline traffic.
+ *
+ * @param  i_target         Centaur target
+ * @param  i_bad_rc         If mss_thermal_init already has a 
+ *                          bad rc before it calls this function, we pass it in 
+ *                          as i_bad_rc. If this function gets it's own bad  
+ *                          local l_rc, i_bad_rc will be commited, and l_rc will 
+ *                          be passed back as return value. Else if no l_rc, 
+ *                          i_bad_rc will be be passed back as return value.
+ * @return Non-SUCCESS if i_bad_rc Non_SUCCESS, or if internal function fails, 
+ *         SUCCESS otherwise.
+ */
+fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target,
+                                         fapi::ReturnCode i_bad_rc );
+
+
+
+//------------------------------------------------------------------------------
+// fapiGetScom_w_retry
+//------------------------------------------------------------------------------
+
+/**
+ * @brief     Reads a SCOM register from a Chip and retries once if SCOM fails.
+ *            Retry is done with assumption that hostboot will switch from
+ *            inband SCOM to FSI, so if inband failed due to channel fail,
+ *            FSI may still work.
+ * @param[in] i_target      Target to operate on
+ * @param[in] i_address     Scom address to read from
+ * @param[out] o_data       ecmdDataBufferBase object that holds data read from
+ *                             address
+ * @return ReturnCode. Zero on success, else platform specified error
+ */
+fapi::ReturnCode fapiGetScom_w_retry(const fapi::Target& i_target,
+                                     const uint64_t i_address,
+                                     ecmdDataBufferBase & o_data);
+
+//------------------------------------------------------------------------------
+// fapiPutScom_w_retry
+//------------------------------------------------------------------------------
+
+/**
+ * @brief     Writes a SCOM register on a Chip and retries once if SCOM fails.
+ *            Retry is done with assumption that hostboot will switch from
+ *            inband SCOM to FSI, so if inband failed due to channel fail,
+ *            FSI may still work.
+ * @param[in] i_target Target to operate on
+ * @param[in] i_address Scom address to write to
+ * @param[in] i_data ecmdDataBufferBase object that holds data to write into
+ *                   address
+ * @return ReturnCode. Zero on success, else platform specified error
+ */
+fapi::ReturnCode fapiPutScom_w_retry(const fapi::Target& i_target,
+                                     const uint64_t i_address,
+                                     ecmdDataBufferBase & i_data);
+
+
+
+
+
+
+#endif /* _MSS_UNMASK_ERRORS_H */
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 0b69218b0..45dadf589 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.28 2012/09/10 14:34:14 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.45 2012/11/20 18:51:15 lapietra Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,7 +44,20 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//         |          |         |
+//  1.44   | sglancy  |19-Nov-12| added ECID addresses
+//  1.42   | pardeik  |09-Nov-12| add N/M throttle register in (again)
+//  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
+//         |          |         | Added MBSPA AND/OR MASK registers
+//  1.38   | pardeik  |31-Oct-12| Added N/M Throttling Control Register
+//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers 
+//  1.36   | menlowuu |25-Oct-12| Added PHY port 1 disable bit registers
+//  1.35   | menlowuu |25-Oct-12| Added PHY disable bit registers
+//  1.34   | aditya   |12-Oct-12| Added MCBIST and DPHY registers
+//  1.33   | baysah   |11-Oct-12| Added MBI FIR mask and action registers
+//  1.32   | menlowuu |11-Oct-12| Added PHY slew calibration registers
+//  1.31   | bellows  |10-Oct-12| Per Joab Request, remove duplicate trace_data reg
+//  1.30   | menlowuu |09-Oct-12| Added PHY slew registers
+//  1.29   | sglancy  |28-Sep-12| Added registers for loopback
 //  1.28   | jdsloat  |10-Sep-12| Fixed MBA CAL Names
 //  1.27   | gollub   |07-Sep-12| Fixed address for MBA01_MBA_WRD_MODE
 //         |          |         | Added Maint Read Buffers 65th Byte
@@ -142,6 +155,12 @@
 
 
 /******************************************************************************/
+/************************************  ECID  **********************************/
+/******************************************************************************/
+CONST_UINT64_T( ECID_PART_0_0x00010000                , ULL(0x00010000) );
+CONST_UINT64_T( ECID_PART_1_0x00010001                , ULL(0x00010001) );
+
+/******************************************************************************/
 /**********************************  CHIPLET  *********************************/
 /******************************************************************************/
 //      use for lpcs P0, <chipletID>
@@ -161,7 +180,7 @@ CONST_UINT64_T( CEN_READ_ARRAY_REPAIR_STATUS_0x00050003,   ULL(0x00050003) );
 CONST_UINT64_T( CEN_READ_ECC_TRAP_REGISTER_0x00050004,     ULL(0x00050004) );
 
 CONST_UINT64_T( TP_TRACE_DATA_HI_0x01010440            , ULL(0x01010440) );
-CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441            , ULL(0x01010441) ); 
+CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441            , ULL(0x01010441) );
 
 /******************************************************************************/
 /*******************************  NEST CHIPLET  *******************************/
@@ -172,6 +191,9 @@ CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441            , ULL(0x01010441) );
 //------------------------------------------------------------------------------
 // MBI
 CONST_UINT64_T( MBI_FIR_0x02010800                     , ULL(0x02010800) );
+CONST_UINT64_T( MBI_FIRMASK_0x02010803                 , ULL(0x02010803) );
+CONST_UINT64_T( MBI_FIRACT0_0x02010806                 , ULL(0x02010806) );
+CONST_UINT64_T( MBI_FIRACT1_0x02010807                 , ULL(0x02010807) );
 CONST_UINT64_T( MBI_CFG_0x0201080A                     , ULL(0x0201080A) );
 CONST_UINT64_T( MBI_STAT_0x0201080B                    , ULL(0x0201080B) );
 
@@ -216,6 +238,7 @@ CONST_UINT64_T( MEM_MBA23_CCS_MODEQ_0x03010EA7         , ULL(0x03010EA7) );
 //------------------------------------------------------------------------------
 //      MEM TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( MEM_TRACE_STATUS_0x03010004            , ULL(0x03010004) );
 CONST_UINT64_T( MEM_TRACE_DATA_HI_MBA01_0x03010880     , ULL(0x03010880) );
 CONST_UINT64_T( MEM_TRACE_DATA_LO_MBA01_0x03010881     , ULL(0x03010881) );
 CONST_UINT64_T( MEM_TRACE_DATA_HI_MBA23_0x030110C0     , ULL(0x030110C0) );
@@ -269,7 +292,7 @@ CONST_UINT64_T( MEM_MCGR4_0x030F0004                   , ULL(0x030F0004) );
 CONST_UINT64_T( MEM_GP3_0x030F0012                     , ULL(0x030F0012) );
 CONST_UINT64_T( MEM_GP3_AND_0x030F0013                 , ULL(0x030F0013) );
 CONST_UINT64_T( MEM_GP3_OR_0x030F0014                  , ULL(0x030F0014) );
- 
+
 //------------------------------------------------------------------------------
 //      MEM CHIPLET INDIRECT SCOM ADDRESSES (DPHY REGISTERS)
 //------------------------------------------------------------------------------
@@ -331,6 +354,8 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F,                       ULL(0x8001C00E0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F,           ULL(0x8000C0140301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F,           ULL(0x8001C0140301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_STATUS_P0_0x8000C01B0301143F,            ULL(0x8000C01B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_STATUS_P1_0x8001C01B0301143F,            ULL(0x8001C01B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F,                  ULL(0x8000C01C0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F,                  ULL(0x8000C01D0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F,                  ULL(0x8000C01E0301143F) );
@@ -348,6 +373,107 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F,                  ULL(0x8000C31E0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F,                  ULL(0x8000C31F0301143F) );
 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C02C0301143F,                  ULL(0x8000C02C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C02D0301143F,                  ULL(0x8000C02D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C02E0301143F,                  ULL(0x8000C02E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P0_0x8000C02F0301143F,                  ULL(0x8000C02F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C12C0301143F,                  ULL(0x8000C12C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C12D0301143F,                  ULL(0x8000C12D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C12E0301143F,                  ULL(0x8000C12E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P0_0x8000C12F0301143F,                  ULL(0x8000C12F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C22C0301143F,                  ULL(0x8000C22C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C22D0301143F,                  ULL(0x8000C22D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C22E0301143F,                  ULL(0x8000C22E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P0_0x8000C22F0301143F,                  ULL(0x8000C22F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C32C0301143F,                  ULL(0x8000C32C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C32D0301143F,                  ULL(0x8000C32D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C32E0301143F,                  ULL(0x8000C32E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P0_0x8000C32F0301143F,                  ULL(0x8000C32F0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F,                  ULL(0x8001C01C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F,                  ULL(0x8001C01D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F,                  ULL(0x8001C01E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F,                  ULL(0x8001C01F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F,                  ULL(0x8001C11C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F,                  ULL(0x8001C11D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F,                  ULL(0x8001C11E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F,                  ULL(0x8001C11F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F,                  ULL(0x8001C21C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F,                  ULL(0x8001C21D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F,                  ULL(0x8001C21E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F,                  ULL(0x8001C21F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F,                  ULL(0x8001C31C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F,                  ULL(0x8001C31D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F,                  ULL(0x8001C31E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F,                  ULL(0x8001C31F0301143F) );
+
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C02C0301143F,                  ULL(0x8001C02C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C02D0301143F,                  ULL(0x8001C02D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C02E0301143F,                  ULL(0x8001C02E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP0_P1_0x8001C02F0301143F,                  ULL(0x8001C02F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C12C0301143F,                  ULL(0x8001C12C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C12D0301143F,                  ULL(0x8001C12D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C12E0301143F,                  ULL(0x8001C12E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP1_P1_0x8001C12F0301143F,                  ULL(0x8001C12F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C22C0301143F,                  ULL(0x8001C22C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C22D0301143F,                  ULL(0x8001C22D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C22E0301143F,                  ULL(0x8001C22E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP2_P1_0x8001C22F0301143F,                  ULL(0x8001C22F0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C32C0301143F,                  ULL(0x8001C32C0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C32D0301143F,                  ULL(0x8001C32D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C32E0301143F,                  ULL(0x8001C32E0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P1_0x8001C32F0301143F,                  ULL(0x8001C32F0301143F) );
+//------------------------------------------------------------------------------
+//   DISABLE BIT SCOM ADDRESSES (DPHY REGISTERS)
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F,		ULL(0x8000007c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F,		ULL(0x8000047c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F,		ULL(0x8000087c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F,		ULL(0x80000c7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F,		ULL(0x8000107c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F,		ULL(0x8000017c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F,		ULL(0x8000057c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F,		ULL(0x8000097c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F,		ULL(0x80000d7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F,		ULL(0x8000117c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F,		ULL(0x8000027c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F,		ULL(0x8000067c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F,		ULL(0x80000a7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F,		ULL(0x80000e7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F,		ULL(0x8000127c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F,		ULL(0x8000037c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F,		ULL(0x8000077c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F,		ULL(0x80000b7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F,		ULL(0x80000f7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F,		ULL(0x8000137c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F,		ULL(0x8001007c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F,		ULL(0x8001047c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F,		ULL(0x8001087c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F,		ULL(0x80010c7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F,		ULL(0x8001107c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F,		ULL(0x8001017c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F,		ULL(0x8001057c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F,		ULL(0x8001097c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F,		ULL(0x80010d7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F,		ULL(0x8001117c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F,		ULL(0x8001027c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F,		ULL(0x8001067c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F,		ULL(0x80010a7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F,		ULL(0x80010e7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F,		ULL(0x8001127c0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F,		ULL(0x8001037c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F,		ULL(0x8001077c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F,		ULL(0x80010b7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F,		ULL(0x80010f7c0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F,		ULL(0x8001137c0301143F) );
 //------------------------------------------------------------------------------
 //      CALIBRATION SCOM ADDRESSES (DPHY REGISTERS)
 //------------------------------------------------------------------------------
@@ -421,6 +547,8 @@ CONST_UINT64_T( MBA01_MBECTLQ_0x03010610           , ULL(0x03010610) );
 //      MBA Special Attention Register
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MBSPAQ_0x03010611           , ULL(0x03010611) );
+CONST_UINT64_T( MBA01_MBSPAQ_AND_0x03010612       , ULL(0x03010612) );
+CONST_UINT64_T( MBA01_MBSPAQ_OR_0x03010613        , ULL(0x03010613) );
 CONST_UINT64_T( MBA01_MBSPAMSKQ_0x03010614        , ULL(0x03010614) );
 
 //------------------------------------------------------------------------------
@@ -499,6 +627,8 @@ CONST_UINT64_T( MBAXCR23Q_0x0201140C           , ULL(0x0201140C) );
 //      MBS ECC Decoder FIR Registers
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_ECC0_MBECCFIR_0x02011440           , ULL(0x02011440) );
+CONST_UINT64_T( MBS_ECC0_MBECCFIR_AND_0x02011441       , ULL(0x02011441) );
+CONST_UINT64_T( MBS_ECC0_MBECCFIR_OR_0x02011442        , ULL(0x02011442) );
 CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_0x02011443      , ULL(0x02011443) );
 CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_AND_0x02011444  , ULL(0x02011444) );
 CONST_UINT64_T( MBS_ECC0_MBECCFIR_MASK_OR_0x02011445   , ULL(0x02011445) );
@@ -506,6 +636,8 @@ CONST_UINT64_T( MBS_ECC0_MBECCFIR_ACTION0_0x02011446   , ULL(0x02011446) );
 CONST_UINT64_T( MBS_ECC0_MBECCFIR_ACTION1_0x02011447   , ULL(0x02011447) );
 
 CONST_UINT64_T( MBS_ECC1_MBECCFIR_0x02011480           , ULL(0x02011480) );
+CONST_UINT64_T( MBS_ECC0_MBECCFIR_AND_0x02011481       , ULL(0x02011481) );
+CONST_UINT64_T( MBS_ECC0_MBECCFIR_OR_0x02011482        , ULL(0x02011482) );
 CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_0x02011483      , ULL(0x02011483) );
 CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_AND_0x02011484  , ULL(0x02011484) );
 CONST_UINT64_T( MBS_ECC1_MBECCFIR_MASK_OR_0x02011485   , ULL(0x02011485) );
@@ -737,6 +869,479 @@ CONST_UINT64_T( SCAC_FIRMASK_OR_0x020115C5      , ULL(0x020115C5) );
 CONST_UINT64_T( SCAC_FIRACTION0_0x020115C6      , ULL(0x020115C6) );
 CONST_UINT64_T( SCAC_FIRACTION1_0x020115C7      , ULL(0x020115C7) );
 
+//------------------------------------------------------------------------------
+//      DQ/DQS Slew Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F , ULL(0x800000750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F , ULL(0x800004750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F , ULL(0x800008750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F , ULL(0x80000C750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F , ULL(0x800010750301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F , ULL(0x800100750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F , ULL(0x800104750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F , ULL(0x800108750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F , ULL(0x80010C750301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F , ULL(0x800110750301143F) );
+
+//------------------------------------------------------------------------------
+//      ADR Slew Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F , ULL(0x8000401A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F , ULL(0x8000441A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F , ULL(0x8000481A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F , ULL(0x80004C1A0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F , ULL(0x8001401A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F , ULL(0x8001441A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F , ULL(0x8001481A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F , ULL(0x80014C1A0301143F) );
+
+//------------------------------------------------------------------------------
+//      ADR Slew Calibration Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F , ULL(0x800080390301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S1_0x800084390301143F , ULL(0x800084390301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_0x800180390301143F , ULL(0x800180390301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S1_0x800184390301143F , ULL(0x800184390301143F) );
+
+//------------------------------------------------------------------------------
+//      DQ/DQS Slew Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_0_0x800000730301143F , ULL(0x800000730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_1_0x800004730301143F , ULL(0x800004730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_2_0x800008730301143F , ULL(0x800008730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_3_0x80000C730301143F , ULL(0x80000C730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P0_4_0x800010730301143F , ULL(0x800010730301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_0_0x800100730301143F , ULL(0x800100730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_1_0x800104730301143F , ULL(0x800104730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_2_0x800108730301143F , ULL(0x800108730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_3_0x80010C730301143F , ULL(0x80010C730301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_VALUE_P1_4_0x800110730301143F , ULL(0x800110730301143F) );
+
+//------------------------------------------------------------------------------
+//      ADR Slew Calibration Status Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F , ULL(0x800080340301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S1_0x800084340301143F , ULL(0x800084340301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_0x800180340301143F , ULL(0x800180340301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S1_0x800184340301143F , ULL(0x800184340301143F) );
+
+//------------------------------------------------------------------------------
+// DP18 IO Driver N FET Slice Termination Enable Registers
+//------------------------------------------------------------------------------
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F,	           ULL(0x8000007A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_0x8000047A0301143F,	           ULL(0x8000047A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_0x8000087A0301143F,	           ULL(0x8000087A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_0x80000C7A0301143F,	           ULL(0x80000C7A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_0x8000107A0301143F,	           ULL(0x8000107A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F,	           ULL(0x8001007A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,	           ULL(0x8001047A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,	           ULL(0x8001087A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,	           ULL(0x80010C7A0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,	           ULL(0x8001107A0301143F) );
+                                                                                       
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,	           ULL(0x8000007B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,	           ULL(0x8000047B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,	           ULL(0x8000087B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_0x80000C7B0301143F,	           ULL(0x80000C7B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_0x8000107B0301143F,	           ULL(0x8000107B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_0x8001007B0301143F,	           ULL(0x8001007B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_0x8001047B0301143F,	           ULL(0x8001047B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_0x8001087B0301143F,	           ULL(0x8001087B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_0x80010C7B0301143F,	           ULL(0x80010C7B0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_0x8001107B0301143F,	           ULL(0x8001107B0301143F) );
+
+//------------------------------------------------------------------------------
+// PC VREF Driver Control Registers
+//------------------------------------------------------------------------------
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F,  ULL(0x8000c0150301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F,  ULL(0x8001c0150301143F) );
+
+//------------------------------------------------------------------------------
+// DP18 IO RX Configuration Registers
+//------------------------------------------------------------------------------
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,    ULL(0x800000060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F,	   ULL(0x800004060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F,	   ULL(0x800008060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F,	   ULL(0x80000c060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F,	   ULL(0x800010060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,	   ULL(0x800100060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F,	   ULL(0x800104060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F,	   ULL(0x800108060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F,	   ULL(0x80010c060301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,	   ULL(0x800110060301143F) );
+
+
+//------------------------------------------------------------------------------
+//      NFET Slice Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F , ULL(0x800000780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_0x800004780301143F , ULL(0x800004780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_0x800008780301143F , ULL(0x800008780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_0x80000C780301143F , ULL(0x80000C780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_0x800010780301143F , ULL(0x800010780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F , ULL(0x800100780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_0x800104780301143F , ULL(0x800104780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_0x800108780301143F , ULL(0x800108780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_0x80010C780301143F , ULL(0x80010C780301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_0x800110780301143F , ULL(0x800110780301143F) );
+
+//------------------------------------------------------------------------------
+//      PFET Slice Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_0x800000790301143F , ULL(0x800000790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_0x800004790301143F , ULL(0x800004790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_0x800008790301143F , ULL(0x800008790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_0x80000C790301143F , ULL(0x80000C790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F , ULL(0x800010790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_0x800100790301143F , ULL(0x800100790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_0x800104790301143F , ULL(0x800104790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_0x800108790301143F , ULL(0x800108790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_0x80010C790301143F , ULL(0x80010C790301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F , ULL(0x800110790301143F) );
+
+//------------------------------------------------------------------------------
+//      DFT Wrap Status Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_0_0x8000001D0301143F , ULL(0x8000001D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_1_0x8000041D0301143F , ULL(0x8000041D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_2_0x8000081D0301143F , ULL(0x8000081D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_3_0x80000C1D0301143F , ULL(0x80000C1D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P0_4_0x8000101D0301143F , ULL(0x8000101D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_0_0x8001001D0301143F , ULL(0x8001001D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_1_0x8001041D0301143F , ULL(0x8001041D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_2_0x8001081D0301143F , ULL(0x8001081D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_3_0x80010C1D0301143F , ULL(0x80010C1D0301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DFT_WRAP_STATUS_P1_4_0x8001101D0301143F , ULL(0x8001101D0301143F) );
+
+//------------------------------------------------------------------------------
+//      Data Bit Enable 0 Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_0x800000000301143F , ULL(0x800000000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1_0x800004000301143F , ULL(0x800004000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2_0x800008000301143F , ULL(0x800008000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3_0x80000C000301143F , ULL(0x80000C000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4_0x800010000301143F , ULL(0x800010000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0_0x800100000301143F , ULL(0x800100000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1_0x800104000301143F , ULL(0x800104000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2_0x800108000301143F , ULL(0x800108000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3_0x80010C000301143F , ULL(0x80010C000301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_0x800110000301143F , ULL(0x800110000301143F) );
+
+//------------------------------------------------------------------------------
+//      Data Bit Enable 1 Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0_0x800000010301143F , ULL(0x800000010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1_0x800004010301143F , ULL(0x800004010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2_0x800008010301143F , ULL(0x800008010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3_0x80000C010301143F , ULL(0x80000C010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4_0x800010010301143F , ULL(0x800010010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0_0x800100010301143F , ULL(0x800100010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1_0x800104010301143F , ULL(0x800104010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2_0x800108010301143F , ULL(0x800108010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3_0x80010C010301143F , ULL(0x80010C010301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4_0x800110010301143F , ULL(0x800110010301143F) );
+
+//------------------------------------------------------------------------------
+//      DQS CLK Phase Rotators 0
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_0_0x800000300301143F , ULL(0x800000300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_1_0x800004300301143F , ULL(0x800004300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_2_0x800008300301143F , ULL(0x800008300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_3_0x80000C300301143F , ULL(0x80000C300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P0_4_0x800010300301143F , ULL(0x800010300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_0_0x800100300301143F , ULL(0x800100300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_1_0x800104300301143F , ULL(0x800104300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_2_0x800108300301143F , ULL(0x800108300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_3_0x80010C300301143F , ULL(0x80010C300301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR0_P1_4_0x800110300301143F , ULL(0x800110300301143F) );
+
+//------------------------------------------------------------------------------
+//      DQS CLK Phase Rotators 1
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_0_0x800000310301143F , ULL(0x800000310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_1_0x800004310301143F , ULL(0x800004310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_2_0x800008310301143F , ULL(0x800008310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_3_0x80000C310301143F , ULL(0x80000C310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P0_4_0x800010310301143F , ULL(0x800010310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_0_0x800100310301143F , ULL(0x800100310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_1_0x800104310301143F , ULL(0x800104310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_2_0x800108310301143F , ULL(0x800108310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_3_0x80010C310301143F , ULL(0x80010C310301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR0_P1_4_0x800110310301143F , ULL(0x800110310301143F) );
+
+
+//------------------------------------------------------------------------------
+//      Read clock Address for all rank pairs and all ports and all DP18s
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0_0x800000040301143F , ULL(0x800000040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_0_0x800001040301143F , ULL(0x800001040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_0_0x800002040301143F , ULL(0x800002040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_0_0x800003040301143F , ULL(0x800003040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1_0x800004040301143F , ULL(0x800004040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_1_0x800005040301143F , ULL(0x800005040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_1_0x800006040301143F , ULL(0x800006040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_1_0x800007040301143F , ULL(0x800007040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2_0x800008040301143F , ULL(0x800008040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_2_0x800009040301143F , ULL(0x800009040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_2_0x80000A040301143F , ULL(0x80000A040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_2_0x80000B040301143F , ULL(0x80000B040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3_0x80000C040301143F , ULL(0x80000C040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_3_0x80000D040301143F , ULL(0x80000D040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_3_0x80000E040301143F , ULL(0x80000E040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_3_0x80000F040301143F , ULL(0x80000F040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4_0x800010040301143F , ULL(0x800010040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P0_4_0x800011040301143F , ULL(0x800011040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P0_4_0x800012040301143F , ULL(0x800012040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P0_4_0x800013040301143F , ULL(0x800013040301143F));
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0_0x800100040301143F , ULL(0x800100040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_0_0x800101040301143F , ULL(0x800101040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_0_0x800102040301143F , ULL(0x800102040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_0_0x800103040301143F , ULL(0x800103040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1_0x800104040301143F , ULL(0x800104040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_1_0x800105040301143F , ULL(0x800105040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_1_0x800106040301143F , ULL(0x800106040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_1_0x800107040301143F , ULL(0x800107040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2_0x800108040301143F , ULL(0x800108040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_2_0x800109040301143F , ULL(0x800109040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_2_0x80010A040301143F , ULL(0x80010A040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_2_0x80010B040301143F , ULL(0x80010B040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3_0x80010C040301143F , ULL(0x80010C040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_3_0x80010D040301143F , ULL(0x80010D040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_3_0x80010E040301143F , ULL(0x80010E040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_3_0x80010F040301143F , ULL(0x80010F040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4_0x800110040301143F , ULL(0x800110040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR1_P1_4_0x800111040301143F , ULL(0x800111040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR2_P1_4_0x800112040301143F , ULL(0x800112040301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR3_P1_4_0x800113040301143F , ULL(0x800113040301143F));
+
+//------------------------------------------------------------------------------
+//     Write Clock Enable registers for Rank Pair 0
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_0_0x800000050301143F , ULL(0x800000050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1_0x800004050301143F , ULL(0x800004050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2_0x800008050301143F , ULL(0x800008050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3_0x80000C050301143F , ULL(0x80000C050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4_0x800010050301143F , ULL(0x800010050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0_0x800100050301143F , ULL(0x800100050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1_0x800104050301143F , ULL(0x800104050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2_0x800108050301143F , ULL(0x800108050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3_0x80010C050301143F , ULL(0x80010C050301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4_0x800110050301143F , ULL(0x800110050301143F) );
+
+//------------------------------------------------------------------------------
+//     DQS Phase Select Rank Pair 0
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F , ULL(0x800000090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F , ULL(0x800004090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F , ULL(0x800008090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F , ULL(0x80000C090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F , ULL(0x800010090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F , ULL(0x800100090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F , ULL(0x800104090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F , ULL(0x800108090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F , ULL(0x80010C090301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F , ULL(0x800110090301143F) );
+
+
+//------------------------------------------------------------------------------
+//     DQS Gate Delay Rank Pair 0
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F , ULL(0x800000130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F , ULL(0x800004130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F , ULL(0x800008130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F , ULL(0x80000C130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F , ULL(0x800010130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F , ULL(0x800100130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F , ULL(0x800104130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F , ULL(0x800108130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F , ULL(0x80010C130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F , ULL(0x800110130301143F) );
+
+
+//------------------------------------------------------------------------------
+//    RC config registers 0 and 3
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_RC_CONFIG0_P0_0x8000C8000301143F , ULL (0x8000C8000301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_RC_CONFIG0_P1_0x8001C8000301143F , ULL (0x8001C8000301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_RC_CONFIG3_P0_0x8000C8070301143F , ULL (0x8000C8070301143F));
+CONST_UINT64_T( DPHY01_DDRPHY_RC_CONFIG3_P1_0x8001C8070301143F , ULL (0x8001C8070301143F));
+//------------------------------------------------------------------------------
+//     MBS Fixed Data Seed Registers
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD0Q_0x02011681  , ULL(0x02011681) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD1Q_0x02011682  , ULL(0x02011682) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD2Q_0x02011683  , ULL(0x02011683) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD3Q_0x02011684  , ULL(0x02011684) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD4Q_0x02011685  , ULL(0x02011685) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD5Q_0x02011686  , ULL(0x02011686) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD6Q_0x02011687  , ULL(0x02011687) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFD7Q_0x02011688  , ULL(0x02011688) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFDQ_0x02011689   , ULL(0x02011689) );
+CONST_UINT64_T( MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A , ULL(0x0201168A) );
+
+
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD0Q_0x02011781  , ULL(0x02011781) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD1Q_0x02011782  , ULL(0x02011782) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD2Q_0x02011783  , ULL(0x02011783) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD3Q_0x02011784  , ULL(0x02011784) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD4Q_0x02011785  , ULL(0x02011785) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) ); 
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD6Q_0x02011787  , ULL(0x02011787) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD7Q_0x02011788  , ULL(0x02011788) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDQ_0x02011789   , ULL(0x02011789) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A , ULL(0x0201178A) );
+//------------------------------------------------------------------------------
+//     MBA Configured Command Sequence Registers
+//------------------------------------------------------------------------------
+
+CONST_UINT64_T( MBA01_CCS_MODEQ_0x030106a7       		, ULL(0x030106a7) );
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) ); 
+//------------------------------------------------------------------------------
+//     MBA MCBIST Configuration Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBCFGQ_0x030106e0  		, ULL(0x030106e0) );
+
+//------------------------------------------------------------------------------
+//     MBS Error Map Register
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) ); 
+//------------------------------------------------------------------------------
+//     MBA MCBIST Memory Register
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) ); 
+CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) ); 
+//------------------------------------------------------------------------------
+//     MBA Fixed Data Seed Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBFD0Q_0x030106be  		, ULL(0x030106be) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) ); 
+//------------------------------------------------------------------------------
+//     MBA Data Rotate Configuration Register
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBDRCRQ_0x030106bd 		, ULL(0x030106bd) );
+//------------------------------------------------------------------------------
+//    MBS Compare Mask Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_MCBIST01_MCBCMA1Q_0x02011672 		, ULL(0x02011672) );
+
+CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );      
+CONST_UINT64_T( MBS_MCBIST01_MCBCMABQ_0x02011674 		, ULL(0x02011674) );
+//------------------------------------------------------------------------------
+//    MBA MCBIST Control Register
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLQ_0x030106db		, ULL(0x030106db) );
+//------------------------------------------------------------------------------
+//    MBA MCBIST Memory Parameter Register
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) ); 
+//------------------------------------------------------------------------------
+//    MBA Address Map Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );    
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );       
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) ); 
+      
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );  
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) ); 
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );   
+
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) ); 
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBAGRAQ_0x030106d6  , ULL(0x030106d6) );
+//------------------------------------------------------------------------------
+//    MBA Performance monitor  Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );  
+//------------------------------------------------------------------------------
+//    MBA Maintenance Buffer Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );   
+//------------------------------------------------------------------------------
+//    DPHY01 PC Rank Pair Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) ); 
+//------------------------------------------------------------------------------
+//    MCBIST Random Data Seed Registers
+
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS0Q_0x030106b2                     , ULL(0x030106b2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS1Q_0x030106b3                     , ULL(0x030106b3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS2Q_0x030106b4                     , ULL(0x030106b4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS3Q_0x030106b5                     , ULL(0x030106b5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS4Q_0x030106b6                     , ULL(0x030106b6) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS5Q_0x030106b7                     , ULL(0x030106b7) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS6Q_0x030106b8                     , ULL(0x030106b8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS7Q_0x030106b9                     , ULL(0x030106b9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRDS8Q_0x030106ba                     , ULL(0x030106ba) );
+CONST_UINT64_T( MBA01_MCBIST_MCBDRSRQ_0x030106bc                     , ULL(0x030106bc) );
+//------------------------------------------------------------------------------
+//    N/M Throttling Control Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBA_FARB3Q_0x03010416, ULL(0x03010416) );
+
 
 /******************************************************************************/
 /*********  MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/
@@ -758,6 +1363,59 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.45  2012/11/20 18:51:15  lapietra
+Fixed errors in get_data
+
+Revision 1.44  2012/11/19 16:17:47  lapietra
+Added ECID Addresses
+
+Revision 1.43  2012/11/19 05:08:15  jmcgill
+add mem chiplet debug status register
+
+Revision 1.42  2012/11/09 14:53:43  pardeik
+added N/M throttle register back in... somehow it was removed
+
+Revision 1.41  2012/11/09 14:47:30  gollub
+
+Added MBECCFIR AND/OR MASK registers
+Added MBSPA AND/OR MASK registers
+
+Revision 1.40  2012/11/08 15:54:21  lapietra
+Added addresses necessary for loopback characerization test
+
+Revision 1.39  2012/10/31 13:44:30  pardeik
+Added N/M throttling control register
+
+Revision 1.38  2012/10/26 09:44:56  sasethur
+ Added MCBIST Random Data Seed Registers
+
+Revision 1.37  2012/10/26 02:05:07  mwuu
+Added PHY port 1 disable bit registers
+
+Revision 1.36  2012/10/26 00:19:53  mwuu
+Added PHY disable bit registers
+
+Revision 1.35  2012/10/16 03:44:53  jmcgill
+restore TP trace array address constants (Centaur addresses here are unique and are not the same as those included in common_scom_addresses header)
+
+Revision 1.34  2012/10/12 12:43:32  sasethur
+Added MCBIST and DPHY registers
+
+Revision 1.33  2012/10/12 03:17:07  baysah
+Added MBI FIR mask and action registers.
+
+Revision 1.32  2012/10/11 22:39:53  mwuu
+Added PHY slew calibration registers
+
+Revision 1.31  2012/10/10 21:26:29  bellows
+removed duplicate scom address
+
+Revision 1.30  2012/10/09 18:15:46  mwuu
+Added PHY slew registers
+
+Revision 1.29  2012/09/28 13:32:34  lapietra
+Added registers for loopback (NFET/PFET Slice, DFT Wrap Status, Data Bit Enable 0/1, Read clock, write clock, and RC config 0 and 3 registers)
+
 Revision 1.28  2012/09/10 14:34:14  jdsloat
 Fixed MBA CAL Names
 
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 316fc0c2f..df744ac9a 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: common_scom_addresses.H,v 1.34 2012/10/25 11:54:47 koenig Exp $
+// $Id: common_scom_addresses.H,v 1.38 2012/11/17 19:53:05 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -199,6 +199,7 @@ CONST_UINT32_T( CFAM_FSI_SHIFT_CTRL_0x00000C10        , ULL(0x00000C10) );
 CONST_UINT32_T( CFAM_FSI_DATA_0_0x00001000            , ULL(0x00001000) );
 CONST_UINT32_T( CFAM_FSI_DATA_1_0x00001001            , ULL(0x00001001) );
 CONST_UINT32_T( CFAM_FSI_CMD_REG_0x00001002           , ULL(0x00001002) );
+CONST_UINT32_T( CFAM_FSI_RESET_0x00001006             , ULL(0x00001006) );
 CONST_UINT32_T( CFAM_FSI_STATUS_0x00001007            , ULL(0x00001007) );
 CONST_UINT32_T( CFAM_FSI_GP1_0x00001010               , ULL(0x00001010) );
 CONST_UINT32_T( CFAM_FSI_GP2_0x00001011               , ULL(0x00001011) );
@@ -274,9 +275,14 @@ CONST_UINT64_T( MBOX_SCRATCH_REG3_0x0005003B          , ULL(0x0005003B) );
 //------------------------------------------------------------------------------
 //      TP ADDITIONAL REGISTER
 //------------------------------------------------------------------------------
-CONST_UINT64_T( TP_PLL_LOCK_0x010F0019                 , ULL(0x010F0019) );
-CONST_UINT64_T( TP_CLK_ADJ_SET_0x010F0016              , ULL(0x010F0016) );
+CONST_UINT64_T( TP_PLL_LOCK_0x010F0019                , ULL(0x010F0019) );
+CONST_UINT64_T( TP_CLK_ADJ_SET_0x010F0016             , ULL(0x010F0016) );
 
+//------------------------------------------------------------------------------
+//      ECCB REGISTERS
+//------------------------------------------------------------------------------
+
+CONST_UINT64_T( ECCB_ECC_ADDR_REG_0x000C0004          , ULL(0x000C0004) );
 
 //------------------------------------------------------------------------------
 //      I2C MASTER (MEMS0)
@@ -318,6 +324,7 @@ CONST_UINT64_T( TP_SCOM_0x01010000                    , ULL(0x01010000) );
 //------------------------------------------------------------------------------
 //      TP TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( TP_TRACE_STATUS_0x01010004            , ULL(0x01010004) );
 CONST_UINT64_T( TP_TRACE_DATA_HI_0x01010400           , ULL(0x01010400) );
 CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010401           , ULL(0x01010401) );
 
@@ -406,6 +413,11 @@ CONST_UINT64_T( NEST_GP4_OR_0x02000007                , ULL(0x02000007) );
 CONST_UINT64_T( NEST_SCOM_0x02010000                  , ULL(0x02010000) );
 
 //------------------------------------------------------------------------------
+//      NEST TRACE
+//------------------------------------------------------------------------------
+CONST_UINT64_T( NEST_TRACE_STATUS_0x02010004          , ULL(0x02010004) );
+
+//------------------------------------------------------------------------------
 //      NEST CLOCK CONTROL
 //------------------------------------------------------------------------------
 CONST_UINT64_T( NEST_OPCG_CNTL0_0x02030002            , ULL(0x02030002) );
@@ -550,6 +562,7 @@ CONST_UINT64_T( SCAN_ALLREGIONEXVITAL,              ULL(0x0FF00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_ALL,                       ULL(0x0FF00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_ALLEXDPLL,                 ULL(0x0FE00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_ALL_BUT_PLL,               ULL(0x0FE00E0000000000) );
+CONST_UINT64_T( SCAN_CLK_PLL,                       ULL(0x00100E0000000000) );
 CONST_UINT64_T( SCAN_CLK_CORE_ONLY,                 ULL(0x06000E0000000000) );
 
 
@@ -559,6 +572,8 @@ CONST_UINT64_T( SCAN_ALL_BUT_GPTRTIMEREP,           ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALDPLLGPTRTIME,     ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_GPTR_TIME_REP,                 ULL(0x0FF0023000000000) );
+CONST_UINT64_T( SCAN_PLL_GPTR,                      ULL(0x0010020000000000) );
+CONST_UINT64_T( SCAN_PLL_BNDY_FUNC,                 ULL(0x0010080800000000) );
 CONST_UINT64_T( SCAN_TIME_REP,                      ULL(0x0CF0003000000000) );
 
 CONST_UINT64_T( SCAN_CORE_ALL,                      ULL(0x06000FFE00000000) );
@@ -595,6 +610,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.38  2012/11/17 19:53:05  jmcgill
+add trace status registers
+
+Revision 1.37  2012/11/16 15:19:48  jeshua
+Added defines for PLL scan0
+
+Revision 1.36  2012/11/16 04:06:18  jmcgill
+add FSI2PIB reset register
+
+Revision 1.35  2012/10/30 15:28:50  koenig
+New ECCB register for ecc enable - AK
+
 Revision 1.34  2012/10/25 11:54:47  koenig
 Added some hangcounter register - AK
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 9b5769265..47870de06 100644
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.117 2012/11/12 18:46:14 jmcgill Exp $
+// $Id: p8_scom_addresses.H,v 1.124 2012/12/07 21:32:13 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -103,8 +103,8 @@
 /******************************************************************************/
 //      use for lpcs P0, <chipletID>
 CONST_UINT64_T( X_BUS_CHIPLET_0x04000000              , ULL(0x04000000) );
-CONST_UINT64_T( PCIE_CHIPLET_0x08000000               , ULL(0x08000000) );
-CONST_UINT64_T( A_BUS_CHIPLET_0x09000000              , ULL(0x09000000) );
+CONST_UINT64_T( PCIE_CHIPLET_0x09000000               , ULL(0x09000000) );
+CONST_UINT64_T( A_BUS_CHIPLET_0x08000000              , ULL(0x08000000) );
 // EX00_CHIPLET - EX15_CHIPLET defined in the EX CHIPLET section
 // "Multicast" chiplets
 CONST_UINT64_T( ALL_CHIPLETS_OR_0x40000000            , ULL(0x40000000) );
@@ -142,12 +142,6 @@ CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000            , ULL(0x6A000000) );
 /******************************************************************************/
 
 //------------------------------------------------------------------------------
-//      FSI2PIB (CFAM)
-//------------------------------------------------------------------------------
-CONST_UINT64_T( FSI2PIB_RESET_0x00001006              , ULL(0x00001006) );
-CONST_UINT64_T( FSI2PIB_STATUS_0x00001007             , ULL(0x00001007) );
-
-//------------------------------------------------------------------------------
 //      FSI MBOX (CFAM)
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00002838          , ULL(0x00002838) );
@@ -378,6 +372,8 @@ CONST_UINT64_T( OCC_LFIR_MASK_OR_0x01010805           , ULL(0x01010805) );
 CONST_UINT64_T( OCC_LFIR_ACT0_0x01010806              , ULL(0x01010806) );
 CONST_UINT64_T( OCC_LFIR_ACT1_0x01010807              , ULL(0x01010807) );
 
+CONST_UINT64_T( OCC_PMC_LFIR_AND_0x01010C01           , ULL(0x01010C01) );
+
 // sram registers
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC0_0x00066004         , ULL(0x00066004) );
 CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005         , ULL(0x00066005) );
@@ -392,11 +388,18 @@ CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007         , ULL(0x00066007) );
 
 CONST_UINT64_T( PMC_MODE_REG_0x00062000               , ULL(0x00062000) );
 CONST_UINT64_T( PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002, ULL(0x00062002)) ;
-CONST_UINT64_T( PMC_PARAMETER_REG1_0x00062006         , ULL(0x00062006))
-CONST_UINT64_T( PMC_STATUS_REG_0x00062009             , ULL(0x00062009)) ;
-CONST_UINT64_T( PMC_OCC_HEARTBEAT_REG_0x00062066      , ULL(0x00062066)) ;
+CONST_UINT64_T( PMC_PARAMETER_REG1_0x00062006         , ULL(0x00062006) );
+CONST_UINT64_T( PMC_STATUS_REG_0x00062009             , ULL(0x00062009) );
+CONST_UINT64_T( PMC_OCC_HEARTBEAT_REG_0x00062066      , ULL(0x00062066) );
 CONST_UINT64_T( PMC_CORE_DECONFIG_REG_0x0006200D      , ULL(0x0006200D) );
 CONST_UINT64_T( PMC_FSMSTATE_STATUS_REG_0x00062000    , ULL(0x00062020) );
+CONST_UINT64_T( PMC_PORRR0_REG_0x0006208E             , ULL(0x0006208E) );
+CONST_UINT64_T( PMC_PORRR1_REG_0x0006208F             , ULL(0x0006208F) );
+CONST_UINT64_T( PMC_PORRS_REG_0x00062090              , ULL(0x00062090) );
+CONST_UINT64_T( PMC_DEEPEXIT_MASK_0x00062092          , ULL(0x00062092) );
+CONST_UINT64_T( PMC_DEEPEXIT_MASK_WAND_0x000620A0     , ULL(0x000620A0) );
+CONST_UINT64_T( PMC_DEEPEXIT_MASK_WOR_0x000620A0      , ULL(0x000620A1) );
+
 // SPIVID Controller
 CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040        , ULL(0x00062040) );
 CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00062041        , ULL(0x00062041) );
@@ -418,6 +421,15 @@ CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058          , ULL(0x00062058) );
 CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059          , ULL(0x00062059) );
 // PORE interface
 CONST_UINT64_T( PMC_PORE_REQ_STAT_REG_0x00062090      , ULL(0x00062090) );
+// PMC LFIR
+CONST_UINT64_T( PMC_LFIR_0x01010840                   , ULL(0x01010840) );
+CONST_UINT64_T( PMC_LFIR_AND_0x01010841               , ULL(0x01010841) );
+CONST_UINT64_T( PMC_LFIR_OR_0x01010842                , ULL(0x01010842) );
+CONST_UINT64_T( PMC_LFIR_MASK_0x01010843              , ULL(0x01010843) );
+CONST_UINT64_T( PMC_LFIR_MASK_AND_0x01010844          , ULL(0x01010844) );
+CONST_UINT64_T( PMC_LFIR_MASK_OR_0x01010845           , ULL(0x01010845) );
+CONST_UINT64_T( PMC_LFIR_ACT0_0x01010846              , ULL(0x01010846) );
+CONST_UINT64_T( PMC_LFIR_ACT1_0x01010847              , ULL(0x01010847) );
 
 // OCI Space Addresses
 
@@ -706,11 +718,17 @@ CONST_UINT64_T( PSI_NOTRUST_BAR0_MASK_0x02013F42      , ULL(0x02013F42) );
 CONST_UINT64_T( PSI_NOTRUST_BAR1_MASK_0x02013F43      , ULL(0x02013F43) );
 
 
+CONST_UINT64_T( EN_TPC_PSIHB_FIR_AND_0x02010901      , ULL(0x02010901) );
+
 //------------------------------------------------------------------------------
 //      HCA
 //------------------------------------------------------------------------------
 CONST_UINT64_T( HCA_MODE_0x0201094F                   , ULL(0x0201094F) );
 
+CONST_UINT64_T( HCA_EN_FIR_AND_0x02010941             , ULL(0x02010941) );
+CONST_UINT64_T( HCA_EN_EHHCA_FIR_AND_0x02010981       , ULL(0x02010981) );
+
+
 //------------------------------------------------------------------------------
 //     INTERRUPT CONTROL PRESENTER  (ICP)
 //------------------------------------------------------------------------------
@@ -718,6 +736,8 @@ CONST_UINT64_T( ICP_BAR_0x020109CA                    , ULL(0x020109CA) );
 CONST_UINT64_T( ICP_SYNC_MODE_REG0_0x020109CB         , ULL(0x020109CB) );
 CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC            , ULL(0x020109CC) );
 
+CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_AND_0x020109C1   , ULL(0x020109C1) );
+
 
 //------------------------------------------------------------------------------
 //      NEST PB EH
@@ -843,6 +863,7 @@ CONST_UINT64_T( MCS_MCFGP_0x02011800                  , ULL(0x02011800) );
 CONST_UINT64_T( MCS_MCFGPM_0x02011801                 , ULL(0x02011801) );
 CONST_UINT64_T( MCS_MCFGPR_0x02011802                 , ULL(0x02011802) );
 CONST_UINT64_T( MCS_MCSMODE1_0x02011808               , ULL(0x02011808) );
+CONST_UINT64_T( MCS_MCSMODE4_0x0201181A               , ULL(0x0201181A) );
 CONST_UINT64_T( MCS_MCFGPA_0x02011814                 , ULL(0x02011814) );
 CONST_UINT64_T( MCS_MCFGPMA_0x02011815                , ULL(0x02011815) );
 CONST_UINT64_T( MCS_MCEPS_0x02011816                  , ULL(0x02011816) );
@@ -859,6 +880,13 @@ CONST_UINT64_T( MCS_MCIFIRACT1_0x02011847             , ULL(0x02011847) );
 CONST_UINT64_T( MCS_MCICFG_0x0201184A                 , ULL(0x0201184A) );
 CONST_UINT64_T( MCS_MCISTAT_0x0201184B                , ULL(0x0201184B) );
 
+
+CONST_UINT64_T( MC1_BUSCNTL_FIR_AND_0x02011E01        , ULL(0x02011E01) );
+CONST_UINT64_T( MC2_MCS0_RIGHT_FIR_AND_0x02011C41     , ULL(0x02011C41) );
+CONST_UINT64_T( MC2_MCS1_RIGHT_FIR_AND_0x02011CC1     , ULL(0x02011CC1) );
+CONST_UINT64_T( MC3_MCS0_RIGHT_FIR_AND_0x02011D41     , ULL(0x02011D41) );
+CONST_UINT64_T( MC3_MCS1_RIGHT_FIR_AND_0x02011DC1     , ULL(0x02011DC1) );
+
 //------------------------------------------------------------------------------
 //      NEST Alter-Diplay Unit (ADU)
 //------------------------------------------------------------------------------
@@ -868,6 +896,7 @@ CONST_UINT64_T( ADU_STATUS_0x02020002                 , ULL(0x02020002) );
 CONST_UINT64_T( ADU_DATA_0x02020003                   , ULL(0x02020003) );
 CONST_UINT64_T( ADU_XSCOM_BASE_0x02020005             , ULL(0x02020005) );
 CONST_UINT64_T( ADU_FORCE_ECC_0x02020010              , ULL(0x02020010) );
+CONST_UINT64_T( ADU_MALF_REG_0x02020011               , ULL(0x02020011) );
 CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B             , ULL(0x0202000B) );
 CONST_UINT64_T( ADU_UNTRUSTED_BAR_0x02020015          , ULL(0x02020015) );
 CONST_UINT64_T( ADU_UNTRUSTED_BAR_MASK_0x02020016     , ULL(0x02020016) );
@@ -877,6 +906,7 @@ CONST_UINT64_T( ADU_TBROM_BAR_0x02020017              , ULL(0x02020017) );
 //      PCIe
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PCIE0_FIR_0x02012000                  , ULL(0x02012000) );
+CONST_UINT64_T( PCIE0_FIR_AND_0x02012001              , ULL(0x02012001) );
 CONST_UINT64_T( PCIE0_FIR_MASK_0x02012003             , ULL(0x02012003) );
 CONST_UINT64_T( PCIE0_FIR_ACTION0_0x02012006          , ULL(0x02012006) );
 CONST_UINT64_T( PCIE0_FIR_ACTION1_0x02012007          , ULL(0x02012007) );
@@ -897,6 +927,7 @@ CONST_UINT64_T( PCIE0_IO_MASK1_0x02012044             , ULL(0x02012044) );
 CONST_UINT64_T( PCIE0_IO_BAR_EN_0x02012045            , ULL(0x02012045) );
 
 CONST_UINT64_T( PCIE1_FIR_0x02012400                  , ULL(0x02012400) );
+CONST_UINT64_T( PCIE1_FIR_AND_0x02012401              , ULL(0x02012401) );
 CONST_UINT64_T( PCIE1_FIR_MASK_0x02012403             , ULL(0x02012403) );
 CONST_UINT64_T( PCIE1_FIR_ACTION0_0x02012406          , ULL(0x02012406) );
 CONST_UINT64_T( PCIE1_FIR_ACTION1_0x02012407          , ULL(0x02012407) );
@@ -917,6 +948,7 @@ CONST_UINT64_T( PCIE1_IO_MASK1_0x02012444             , ULL(0x02012444) );
 CONST_UINT64_T( PCIE1_IO_BAR_EN_0x02012445            , ULL(0x02012445) );
 
 CONST_UINT64_T( PCIE2_FIR_0x02012800                  , ULL(0x02012800) );
+CONST_UINT64_T( PCIE2_FIR_AND_0x02012801              , ULL(0x02012801) );
 CONST_UINT64_T( PCIE2_FIR_MASK_0x02012803             , ULL(0x02012803) );
 CONST_UINT64_T( PCIE2_FIR_ACTION0_0x02012806          , ULL(0x02012806) );
 CONST_UINT64_T( PCIE2_FIR_ACTION1_0x02012807          , ULL(0x02012807) );
@@ -958,6 +990,15 @@ CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B             , ULL(0x0201309B) );
 CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C              , ULL(0x0201309C) );
 CONST_UINT64_T( NX_CQ_EPS_0x0201309D                  , ULL(0x0201309D) );
 
+
+CONST_UINT64_T( NX_CAPP_FIR_AND_0x02013001            , ULL(0x02013001) );
+CONST_UINT64_T( NX_DMA_ENG_FIR_AND_0x02013101         , ULL(0x02013101) );
+CONST_UINT64_T( NX_CQ_FIR_AND_0x02013081              , ULL(0x02013081) );
+CONST_UINT64_T( NX_AS_FIR_AND_0x020130C1              , ULL(0x020130C1) );
+
+CONST_UINT64_T( EH_PB_MCDCTL_FIR_AND_0x02013401       , ULL(0x02013401) );
+
+
 //------------------------------------------------------------------------------
 //      MCD
 //------------------------------------------------------------------------------
@@ -995,16 +1036,21 @@ CONST_UINT64_T( X_SCOM_0x04010000                     , ULL(0x04010000) );
 //------------------------------------------------------------------------------
 //      X-BUS TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( X_TRACE_STATUS_0x04010004             , ULL(0x04010004) );
 CONST_UINT64_T( X_TRACE_DATA_HI_T0_0x04010400         , ULL(0x04010400) );
 CONST_UINT64_T( X_TRACE_DATA_LO_T0_0x04010401         , ULL(0x04010401) );
 CONST_UINT64_T( X_TRACE_DATA_HI_T1_0x04010800         , ULL(0x04010800) );
 CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010801         , ULL(0x04010801) );
 
+
+
 //------------------------------------------------------------------------------
 //      X-BUS PBEN
 //------------------------------------------------------------------------------
 CONST_UINT64_T( PB_X_MODE_0x04010C0A                  , ULL(0x04010C0A) );
 
+CONST_UINT64_T( X_PBEN_MISC_FIR_AND_0x04010C01       , ULL(0x04010C01) );
+
 //------------------------------------------------------------------------------
 //      X-BUS IOPSI
 //------------------------------------------------------------------------------
@@ -1043,6 +1089,8 @@ CONST_UINT64_T( X_PERV_LFIR_MASK_OR_0x0404000F        , ULL(0x0404000F) );
 CONST_UINT64_T( X_PERV_LFIR_ACT0_0x04040010           , ULL(0x04040010) );
 CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011           , ULL(0x04040011) );
 
+CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_AND_0x04011401    , ULL(0x04011401) );
+
 //------------------------------------------------------------------------------
 //      X-BUS THERMAL
 //------------------------------------------------------------------------------
@@ -1095,6 +1143,7 @@ CONST_UINT64_T( A_SCOM_0x08010000                     , ULL(0x08010000) );
 //------------------------------------------------------------------------------
 //      A-BUS TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( A_TRACE_STATUS_0x08010004             , ULL(0x08010004) );
 CONST_UINT64_T( A_TRACE_DATA_HI_0x08010400            , ULL(0x08010400) );
 CONST_UINT64_T( A_TRACE_DATA_LO_0x08010401            , ULL(0x08010401) );
 
@@ -1129,6 +1178,8 @@ CONST_UINT64_T( A_PERV_LFIR_MASK_OR_0x0804000F        , ULL(0x0804000F) );
 CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010           , ULL(0x08040010) );
 CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011           , ULL(0x08040011) );
 
+CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_AND_0x08010C01     , ULL(0x08010C01) );
+
 //------------------------------------------------------------------------------
 //      PLL LOCK
 //------------------------------------------------------------------------------
@@ -1209,6 +1260,7 @@ CONST_UINT64_T( PB_F_FMR_CFG_0x09010813               , ULL(0x09010813) );
 //------------------------------------------------------------------------------
 //      PCIE-BUS TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( PCIE_TRACE_STATUS_0x09010004          , ULL(0x09010004) );
 CONST_UINT64_T( PCIE_TRACE_DATA_HI_0x09010400         , ULL(0x09010400) );
 CONST_UINT64_T( PCIE_TRACE_DATA_LO_0x09010401         , ULL(0x09010401) );
 
@@ -1255,6 +1307,11 @@ CONST_UINT64_T( PCIE_PERV_LFIR_MASK_OR_0x0904000F     , ULL(0x0904000F) );
 CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010        , ULL(0x09040010) );
 CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011        , ULL(0x09040011) );
 
+CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_AND_0x09010801   , ULL(0x09010801) );
+
+CONST_UINT64_T( PCIE_PLL_CNTL_FIR_AND_0x09011401      , ULL(0x09011401) );
+CONST_UINT64_T( PCIE_PLL1_CNTL_FIR_AND_0x09011841     , ULL(0x09011841) );
+
 //------------------------------------------------------------------------------
 //      PLL LOCK
 //------------------------------------------------------------------------------
@@ -1379,6 +1436,7 @@ CONST_UINT64_T( EX_L2_PURGE_CMD_PHYP_0x1001280F       , ULL(0x1001280F) );
 //------------------------------------------------------------------------------
 //      EX/CORE TRACE
 //------------------------------------------------------------------------------
+CONST_UINT64_T( EX_TRACE_STATUS_0x10010004            , ULL(0x10010004) );
 CONST_UINT64_T( EX_TRACE_DATA_HI_ECO_0x10010400       , ULL(0x10010400) );
 CONST_UINT64_T( EX_TRACE_DATA_LO_ECO_0x10010401       , ULL(0x10010401) );
 CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T0_0x10012000     , ULL(0x10012000) );
@@ -1544,6 +1602,9 @@ CONST_UINT64_T( EX_GP3_0x100F0012                     , ULL(0x100F0012) );
 CONST_UINT64_T( EX_GP3_AND_0x100F0013                 , ULL(0x100F0013) );
 CONST_UINT64_T( EX_GP3_OR_0x100F0014                  , ULL(0x100F0014) );
 
+// Atomic Lock
+CONST_UINT64_T( EX_ATOMIC_LOCK_0x100F03FF             , ULL(0x100F03FF) );
+
 //Chiplet specific names (probably won't ever be used)
 CONST_UINT64_T( EX00_GP3_0x100F0012                   , ULL(0x100F0012) );
 CONST_UINT64_T( EX00_GP3_AND_0x100F0013               , ULL(0x100F0013) );
@@ -1643,6 +1704,7 @@ CONST_UINT64_T( EX_PMGP1_REG_0_WANDx100F0104
 CONST_UINT64_T( EX_PMGP1_REG_0_WORx100F0105                                         , ULL(0x100F0105) );
 CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106                                     , ULL(0x100F0106) );
 CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E                                     , ULL(0x100F010E) );
+CONST_UINT64_T( EX_PMErr_REG_0x100F0109                                             , ULL(0x100F0109) );
 CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A                                         , ULL(0x100F010A) );
 CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B                                      , ULL(0x100F010B) );
 CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C                                      , ULL(0x100F010C) );
@@ -1691,7 +1753,12 @@ CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105
 CONST_UINT64_T( EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156                             , ULL(0x690F0156) );       // PCBSLV Mode Multicast Group1
 CONST_UINT64_T( EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D            , ULL(0x690F015D) );       // PCBSLV PM Bounds Multicast Group1
 
-
+//******************************************************************************/
+//*********  ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/
+//******************************************************************************/
+CONST_UINT8_T( SCAN_CHIPLET_XBUS,                   ULL(0x04) );
+CONST_UINT8_T( SCAN_CHIPLET_ABUS,                   ULL(0x08) );
+CONST_UINT8_T( SCAN_CHIPLET_PCIE,                   ULL(0x09) );
 
 //******************************************************************************/
 //*********  MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/
@@ -1719,6 +1786,27 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.124  2012/12/07 21:32:13  stillgs
+Fix ECO PFET Delay register name problem
+
+Revision 1.123  2012/12/03 22:28:51  baysah
+Added mcs mode4 register.
+
+Revision 1.122  2012/11/30 03:39:35  klhillp8
+Added the FIR_AND register addresses for mpipl_clear_xstop.
+
+Revision 1.121  2012/11/26 03:16:48  stillgs
+Add PMC LFIR and other addresses needed for SLW recovery
+
+Revision 1.120  2012/11/17 19:52:43  jmcgill
+add trace status registers, chiplet scan constants
+
+Revision 1.119  2012/11/16 11:14:43  koenig
+Corrected ABUS and PCI chiplet offsets - AK
+
+Revision 1.118  2012/11/16 04:05:59  jmcgill
+remove FSI2PIB addresses already in common address file
+
 Revision 1.117  2012/11/12 18:46:14  jmcgill
 updates for FSI2IB cfam registers, MCS SCOM registers
 
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
index bdc2e1e0c..5768a4397 100755
--- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
@@ -1,8 +1,27 @@
-#-- $Id: cen_ddrphy.initfile,v 1.9 2012/06/28 00:48:44 mwuu Exp $
+#-- $Id: cen_ddrphy.initfile,v 1.19 2012/12/12 20:46:54 mwuu Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.19|mwuu    |12/12/12|Commented out settings for SIM, changed attribute
+#           |        |        |to CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE
+#--		1.18|mwuu	 |12/03/12|Changed DP18_PLL_CONFIG1 VCO setting
+#--		1.17|mwuu	 |11/30/12|Changed DP18_PLL_CONFIG0/1 registers & 
+#           |        |        |DP18_IO_TX_CONFIG0 INTERP_SIG_SLEW field
+#--		1.16|mwuu	 |11/28/12|Changed ADR TSYS to 0x70 and DP18 TSYS to 0x6B.
+#           |        |        |Changed ADR_PLL_VREG_CONFIG0/1 registers.
+#--		1.15|mwuu	 |11/19/12|Updated TSYS_WR ADR+DP18 with slow process numbers
+#--		1.14|mwuu	 |11/13/12|Fixed define of Swizzle check, was wrong before.
+#--		1.13|mwuu	 |11/09/12|Updated SI settings from Paul, new attributes.
+#		Added dqs swizzle for Glacier0. Added TSYS settings based on freq.
+#		Changed FW_WR_RD to match DD0 setting. Changed ABORT_ON_CAL_ERR to be
+#		default. Divided up ADR blocks into ADDR, CNTL, CLK, SPCKE. Added FFE
+#		settings for drv_imp_dq_dqs. Changed PLL_TUNEMDIV to be same as DD0.
+#--		1.12|bwieman |10/08/12|attempt to restore
+#--		1.11|bellows |10/08/12|moved inifiles to scom sub directory
+#--		1.10|mwuu	 |08/15/12|Removed bit_disable settings, to be set in FN.
+#		Cleaned up the settings for sim. Added  DIMM functional attribute,
+#		FIR unmask scom, PC_RESET register
 #--		1.9	|mwuu	 |06/27/12|Added SYS to IS_SIMULATION attribute
 #--		1.8	|mwuu	 |06/18/12|Changed to use spares based on DIMM_TYPE, also
 #       changed FW_RD_WR field to use AL, CL instead of hardcoded value
@@ -26,22 +45,17 @@
 #--Master list of variables that can be used in this file is at:
 #--<Attribute Definition Location>
 
-# 5/07/12	Switched to using ENUM values for many attributes
-# 5/04/12	Temp workaround for MSS_FREQ and MSS_VOLT
-# 4/11/12	Fixed address for DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0
-# 			started adding expressions for this register, but need bad_bit_mask
-# 			changed
-# 4/6/12	Made initfile similar to dial settings for misc registers(PLL,etc.)
-# 3/29/12	Added DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0 and
-# 			DPHY01_DDRPHY_DP18_DQSCLK_OFFSET settings for SIM.
-
 SyntaxVersion = 1
 
-# Jan 15th?		SIM uses type 1C 4Rx8/port CDIMM first config
-# Jan 31st		1B ISDIMM DDR3 4 DIMMS (1 per port)
-# Feb 15		Initfile delivered to Firmware
-# interim date	some other configs, maybe LR DIMM
-# May 15		final initfile complete all configs
+# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+# !!  data fields are right aligned  !!
+# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+#
+# SIM uses type 1B CDIMM, 2Rx8/drop, dual drop, 1600
+#
+# 0 = false, anything else = true
+#
+# need to figure out GPO, WLO, RLO...
 
 #-- -----------------------------------------------------------------------------
 #-- -----------------------------------------------------------------------------
@@ -60,23 +74,20 @@ define CEN = TGT1;	# parent Centaur
 # short test for simulation
 define def_is_sim		=	(SYS.ATTR_IS_SIMULATION == 1)	;
 
-# TSYS_WRCLK		!!NOTE: different depending on EC level
-define def_ADR32_TSYS_WRCLK	= 0x60	;
-define def_DP18_TSYS_WRCLK	= 0x60	;
+# FAST_SIM_PER_CNTR for periodic calibrations
+define def_FAST_SIM_PC	=	1	;
 
-# for real HW uncomment,  !!FIX once ATTR_EFF_DIMM_SPARE available
+# for real HW uncomment,  !!FIX once ATTR_EFF_DIMM_SPARE available [2][4][4] port, dimm, rank
 define def_has_spare	=	(ATTR_EFF_DIMM_TYPE == 0)	;	# CDIMM
 define def_no_spare		=	(ATTR_EFF_DIMM_TYPE != 0)	;	# others, ISDIMMs, LRDIMM, etc.
-#define def_no_spare	=	(SYS.ATTR_IS_SIMULATION==1);
-#define def_has_spare	=	(SYS.ATTR_IS_SIMULATION==0);
 
-# ports 0,1 must have dimms with ranks to be valid
-define def_valid_p0		=	((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] > 0) || (ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] > 0))	;
-define def_valid_p1		=	((ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] > 0) || (ATTR_EFF_NUM_RANKS_PER_DIMM[1][1] > 0))	;
+# ports 0,1 must have functional dimms to be valid
+define def_valid_p0		=	(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4);
+define def_valid_p1		=	(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR & 0x0F);
 
 # short test for MBA01 or MBA23
 define def_is_mba01		=	(ATTR_CHIP_UNIT_POS == 0)	;	# MBA01
-define def_is_mba23		=	(ATTR_CHIP_UNIT_POS == 1)	;	# MBA01
+define def_is_mba23		=	(ATTR_CHIP_UNIT_POS == 1)	;	# MBA23
 
 # Port 0  valid rank pair[0:3]_p0
 # PRIMARY RANK GROUP
@@ -122,24 +133,6 @@ define def_val_qrg1_p1	= (ATTR_EFF_QUATERNARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_QU
 define def_val_qrg2_p1	= (ATTR_EFF_QUATERNARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP2_INVALID)	;	# valid rank group 2 port0
 define def_val_qrg3_p1	= (ATTR_EFF_QUATERNARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP3_INVALID)	;	# valid rank group 3 port0
 
-# bitwise | is not working
-#
-# ena_rank_pair[0:3]_p0
-#define def_val_rp0_3_p0	= def_val_rp0_p0 << 3 | def_val_rp1_p0 << 2 | def_val_rp2_p0 << 1 | def_val_rp3_p0	;
-#	60		,	def_val_rp0_p0	,	any						;	# enable rank pair 0
-#	61		,	def_val_rp1_p0	,	any						;	# enable rank pair 1
-#	62		,	def_val_rp2_p0	,	any						;	# enable rank pair 2
-#	63		,	def_val_rp3_p0	,	any						;	# enable rank pair 3
-#	60:63	,	def_val_rp0_3_p0,	any						;	# enable rank pair0:3 on port 0
-#
-# ena_rank_pair[0:3]_p1
-#define def_ena_rp0_3_p1	= def_ena_rp0_p1 << 3 | def_ena_rp1_p1 << 2 | def_ena_rp2_p1 << 1 | def_ena_rp3_p1	;
-# 	60		,	def_ena_rp0_p1	,	any						;	# enable rank pair 0
-#	61		,	def_ena_rp1_p1	,	any						;	# enable rank pair 1
-#	62		,	def_ena_rp2_p1	,	any						;	# enable rank pair 2
-#	63		,	def_ena_rp3_p1	,	any						;	# enable rank pair 3
-#	60:63	,	def_ena_rp0_3_p1,	any						;	# enable rank pair0:3 on port 1
-
 # shorter test for DRAM gen
 #define def_is_empty	=	(ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_EMPTY)	;	# EMPTY, no dram?
 define def_is_ddr3	=	(ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_DDR3)	;	# DDR3 = 1
@@ -163,36 +156,107 @@ define def_is_bl8		=	(ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL8)	;	# burst leng
 #define def_is_bl_otf	=	(ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_OTF)	;	# burst length on the fly = (1)
 #define def_is_bl4		=	(ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL4)	;	# burst length 4 = (2)
 
+# shorter test for Centaur receiver impedance DQ / DQS
+define def_cri_dqs_ohm15_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15)		;	# OHM15  = 0x0F  (15)
+define def_cri_dqs_ohm20_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20)		;	# OHM20  = 0x14  (20)
+define def_cri_dqs_ohm30_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30)		;	# OHM30  = 0x1E  (30)
+define def_cri_dqs_ohm40_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40)		;	# OHM40  = 0x28  (40)
+define def_cri_dqs_ohm48_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48)		;	# OHM48  = 0x30  (48)
+define def_cri_dqs_ohm60_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60)		;	# OHM60  = 0x3C  (60)
+define def_cri_dqs_ohm80_p0	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80)		;	# OHM80  = 0x50  (80)
+define def_cri_dqs_ohm120_p0=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120)		;	# OHM120 = 0x78 (120)
+define def_cri_dqs_ohm160_p0=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160)		;	# OHM160 = 0xA0 (160)
+define def_cri_dqs_ohm240_p0=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240)		;	# OHM240 = 0xF0 (240)
+
+define def_cri_dqs_ohm15_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15)		;	# OHM15  = 0x0F  (15)
+define def_cri_dqs_ohm20_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20)		;	# OHM20  = 0x14  (20)
+define def_cri_dqs_ohm30_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30)		;	# OHM30  = 0x1E  (30)
+define def_cri_dqs_ohm40_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40)		;	# OHM40  = 0x28  (40)
+define def_cri_dqs_ohm48_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48)		;	# OHM48  = 0x30  (48)
+define def_cri_dqs_ohm60_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60)		;	# OHM60  = 0x3C  (60)
+define def_cri_dqs_ohm80_p1	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80)		;	# OHM80  = 0x50  (80)
+define def_cri_dqs_ohm120_p1=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120)		;	# OHM120 = 0x78 (120)
+define def_cri_dqs_ohm160_p1=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160)		;	# OHM160 = 0xA0 (160)
+define def_cri_dqs_ohm240_p1=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240)		;	# OHM240 = 0xF0 (240)
+
 # shorter test for Centaur driver impedance DQ / DQS
-define def_cdi_dqs_ohm24	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24)	;	# OHM24 = 0x18 (24)
-define def_cdi_dqs_ohm30	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30)	;	# OHM30 = 0x1E (30)
-define def_cdi_dqs_ohm34	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34)	;	# OHM34 = 0x22 (34)
-define def_cdi_dqs_ohm40	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40)	;	# OHM40 = 0x28 (40)
-
-# shorter test for Centaur driver impedance command
-define def_cdi_cmd_ohm15	=	(ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM15)	;	# OHM15 = 0x0F (15)
-define def_cdi_cmd_ohm20	=	(ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM20)	;	# OHM20 = 0x14 (20)
-define def_cdi_cmd_ohm30	=	(ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM30)	;	# OHM30 = 0x1E (30)
-define def_cdi_cmd_ohm40	=	(ATTR_EFF_CEN_DRV_IMP_CMD == ENUM_ATTR_EFF_CEN_DRV_IMP_CMD_OHM40)	;	# OHM40 = 0x28 (40)
-
-# shorter test for Centaur driver impedance control
-define def_cdi_ctl_ohm15	=	(ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15)	;	# OHM15 = 0x0F (15)
-define def_cdi_ctl_ohm20	=	(ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20)	;	# OHM20 = 0x14 (20)
-define def_cdi_ctl_ohm30	=	(ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30)	;	# OHM30 = 0x1E (30)
-define def_cdi_ctl_ohm40	=	(ATTR_EFF_CEN_DRV_IMP_CNTL == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40)	;	# OHM40 = 0x28 (40)
+define def_cdi_dqs_ohm24_p0	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; 	# OHM24 = 0x18 (24)
+
+define def_cdi_dqs_ohm30_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120))	;	# OHM30 = 0x1E (30)
+
+define def_cdi_dqs_ohm34_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120))	;	# OHM34 = 0x22 (34)
+
+define def_cdi_dqs_ohm40_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120))	;	# OHM40 = 0x28 (40)
+
+define def_cdi_dqs_ohm24_p1	=	(ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; 	# OHM24 = 0x18 (24)
+
+define def_cdi_dqs_ohm30_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120))	;	# OHM30 = 0x1E (30)
+
+define def_cdi_dqs_ohm34_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120))	;	# OHM34 = 0x22 (34)
+
+define def_cdi_dqs_ohm40_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120))	;	# OHM40 = 0x28 (40)
+
+# shorter test for number of FFE slices to enable in TX_CONFIG register
+define def_ffe1_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480))	;
+
+define def_ffe2_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240))	;
+
+define def_ffe3_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160))	;
+
+define def_ffe4_p0	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120))	;
+
+define def_ffe1_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480))	;
+
+define def_ffe2_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240))	;
+
+define def_ffe3_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160))	;
+
+define def_ffe4_p1	=	((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120))	;
+
+# shorter test for Centaur driver impedance command/address (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE)
+define def_cdi_addr_ohm15_p0=	(ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_addr_ohm20_p0=	(ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_addr_ohm30_p0=	(ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_addr_ohm40_p0=	(ATTR_EFF_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40)	;	# OHM40 = 0x28 (40)
+
+define def_cdi_addr_ohm15_p1=	(ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_addr_ohm20_p1=	(ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_addr_ohm30_p1=	(ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_addr_ohm40_p1=	(ATTR_EFF_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40)	;	# OHM40 = 0x28 (40)
+
+# shorter test for Centaur driver impedance control (CKE0:1, CKE4:5, ODT0:3, CSN0:7)
+define def_cdi_ctl_ohm15_p0	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_ctl_ohm20_p0	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_ctl_ohm30_p0	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_ctl_ohm40_p0	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40)	;	# OHM40 = 0x28 (40)
+
+define def_cdi_ctl_ohm15_p1	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_ctl_ohm20_p1	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_ctl_ohm30_p1	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_ctl_ohm40_p1	=	(ATTR_EFF_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40)	;	# OHM40 = 0x28 (40)
+
+# shorter test for Centaur driver impedance clocks (CLK0:3)
+define def_cdi_clk_ohm15_p0	=	(ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_clk_ohm20_p0	=	(ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_clk_ohm30_p0	=	(ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_clk_ohm40_p0	=	(ATTR_EFF_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40)	;	# OHM40 = 0x28 (40)
+
+define def_cdi_clk_ohm15_p1	=	(ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_clk_ohm20_p1	=	(ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_clk_ohm30_p1	=	(ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_clk_ohm40_p1	=	(ATTR_EFF_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40)	;	# OHM40 = 0x28 (40)
+
+# shorter test for Centaur driver impedance spare clocks (CKE2:3, CKE6:7)
+define def_cdi_spcke_ohm15_p0	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_spcke_ohm20_p0	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_spcke_ohm30_p0	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_spcke_ohm40_p0	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40)	;	# OHM40 = 0x28 (40)
+
+define def_cdi_spcke_ohm15_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM15)	;	# OHM15 = 0x0F (15)
+define def_cdi_spcke_ohm20_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM20)	;	# OHM20 = 0x14 (20)
+define def_cdi_spcke_ohm30_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM30)	;	# OHM30 = 0x1E (30)
+define def_cdi_spcke_ohm40_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40)	;	# OHM40 = 0x28 (40)
 
-# shorter test for Centaur receiver impedance DQ / DQS
-define def_cri_dqs_ohm15	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15)		;	# OHM15  = 0x0F  (15)
-define def_cri_dqs_ohm20	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20)		;	# OHM20  = 0x14  (20)
-define def_cri_dqs_ohm30	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30)		;	# OHM30  = 0x1E  (30)
-define def_cri_dqs_ohm40	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40)		;	# OHM40  = 0x28  (40)
-define def_cri_dqs_ohm48	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48)		;	# OHM48  = 0x30  (48)
-define def_cri_dqs_ohm60	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60)		;	# OHM60  = 0x3C  (60)
-define def_cri_dqs_ohm120	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120)	;	# OHM120 = 0x78 (120)
-#ddr4?  80 160 240
-#define def_cri_dqs_ohm80	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80)		;	# OHM80  = 0x50  (80)
-#define def_cri_dqs_ohm160	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160)	;	# OHM160 = 0xA0 (160)
-#define def_cri_dqs_ohm240	=	(ATTR_EFF_CEN_RCV_IMP_DQ_DQS == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240)	;	# OHM240 = 0xF0 (240)
 
 # SIMPLIFY
 # ================================================================================
@@ -218,6 +282,9 @@ define def_tODTL_DDR4		= (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_A
 define def_p2p_jitter		=	2600										;	# DQS peak to peak jitter in ps
 define def_dqs_offset		=	(11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000))	;
 
+# define for glacier1(1), glacier2=normal(0)
+define def_is_type1	=	((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_DIMM_TYPE != ENUM_ATTR_EFF_DIMM_TYPE_CDIMM))	;
+
 #---------------------------------------------------------------------------------
 
 # =====================================================================================================
@@ -247,45 +314,47 @@ define def_dqs_offset		=	(11 + ((def_p2p_jitter * CEN.ATTR_MSS_FREQ) / 4000000))
 # DPHY01.DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 	= 0x8020
 # DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0				= 0x8020
 # DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0		= 0x0010
-
-# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-# DPHY01 PC IO PVT N/P FET Driver Control		!! need to set this?
-#
-# set to 0x0008, then 0x0000
-#
-#	[01:23]							[0:1]
-# DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0		0x8000c0140301143f
-# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG20_L2(0:12)
-#
-# 48:52	0	PVTP			RW	PFET Driver PVTP value to send to all output drivers when PVT_OVERRIDE is set.
-# 53:57	0	PVTN			RW	NFET Driver PVTN value to send to all output drivers when PVT_OVERRIDE is set.
-# 58	0	PVT_OVERRIDE	RW	'1'b - All drivers are updated with the PVTP and PVTN values in this register imeadiately.
-# 								'0'b - All drivers are updated with the PVTP and PVTN values from the impedance calibration state machine.
-# 59	0	ENABLE_ZCAL		RW	'1'b - Enable Impedance Controller.
-# 								'0'b - Disable Impedance Controller.
-# 60	0	RESET_ZCAL		RW	Reset Impedance Controller. The value of this field is driven to the zcntl_reset_o
-# 								output for optional connection to the reset of an Impedance Controller.
-# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 # ---------------------------------------------------------------------------------------
 # Pervasive FIR registers
 #
+# Error mask register where (Action0, Action1, Mask) = Action Select;
+#
+# (0,0,x) = No Error reported
+# (0,1,0) = Recoverable Error
+# (1,0,0) = Checkstop Error
+# (1,1,0) = Local Core Checkstop
+# (x,x,1) = MASKED
+#
+# PHY01_DDRPHY_FIR_REG			default=0	0x800200900301143f
+# PHY01_DDRPHY_FIR_MASK_REG		default=0	0x800200930301143f
 # PHY01_DDRPHY_FIR_ACTION0_REG	default=0	0x800200960301143f
 # PHY01_DDRPHY_FIR_ACTION1_REG	default=0	0x800200970301143f
-# PHY01_DDRPHY_FIR_MASK_REG		default=0	0x800200930301143f
-# PHY01_DDRPHY_FIR_REG			default=0	0x800200900301143f
 # PHY01_DDRPHY_FIR_WOF_REG		default=0	0x800200980301143f
 #
+# PHY01_DDRPHY_FIR_MASK_REG		default=0	0x800200930301143f
+# scomx.fir0.fir_mask_lt
+scom 0x800200930301143f {	# covers both ports
+	# 48:52 = port0 { FSM, parity, cal, FSM recover, parity recover }
+	# 53 = port 0/1 FIR parity recover error
+	# 56:60 = port1 { FSM, parity, cal, FSM recover, parity recover }
+	scom_data			,	expr										;
+	# fix for DD1 mask all PHY FIR bits.
+	0x000000000000FFFF	,	(CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE)	;
+	0x0000000000000000	,	any											;
+}
 
 # ---------------------------------------------------------------------------------------
 # PC Config0
 #
 # ddr3=0x0000, ddr4=0x1202	# !! set in ddr_phy_reset
 #
-# DPHY01.DDRPHY_PC_CONFIG0_P[0:1] from (alias spydef)
-# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG12_L2			0x00C	0x8000c00c0301143f
+# DPHY01.DDRPHY_PC_CONFIG0_P[0:1]		0x00C	0x8000c00c0301143f
+# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG12_L2
 scom 0x800(0,1)C00C0301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	# Protocol, 0=DDR3, 1=DDR4, 2=RLDRAM2 CIO, 4=RLDRAM3
 	48:51	,	0b0001		,	(def_is_ddr4)	;	# ATTR_EFF_DRAM_GEN=2=DDR4
 	48:51	,	0b0000		,	(def_not_ddr4)	;	# ATTR_EFF_DRAM_GEN=1=DDR3 or 0=empty
@@ -296,37 +365,58 @@ scom 0x800(0,1)C00C0301143F {	# _P[0:1]
 	55		,	0b0			,	any				;	# SysClK 2x Mem Internal CLK
 	56		,	0b0			,	any				;	# Rank Override enable
 	57:59	,	0b000		,	any				;	# Rank Override value
+#	DDR4_RD_PREAMBLE_TRAIN ?
 	60		,	0b0			,	any				;	# low latency (ERS Mode), 1=force off, 0=auto
+#	DDR4_BANK_REFRESH ?
 #	61		,	0b0			,	any				;	# reserved
 	62		,	0b1			,	(def_is_ddr4)	;	# enable DDR4_VLEVEL_BANK_GROUP
 	62		,	0b0			,	(def_not_ddr4)	;	# disable for DDR3
-#	63		,	0b0			,	any				;	# reserved
+#	DDR4_DQ_LINK_TRAIN ?
+	63		,	0b0			,	any				;	# ZCAL_NOT_CONT	(set to continuously int zcal)
 }
-#
+
 # ---------------------------------------------------------------------------------------
 # PC_CONFIG1
 #
-# DPHY01.DDRPHY_PC_CONFIG1_P0 from (alias spydef)
+# DPHY01.DDRPHY_PC_CONFIG1_P0
 scom 0x800(0,1)C00D0301143F {
 	bits	,	scom_data	,	expr								;
+#	0:47	,	0x000000000000,	any		;	# reserved
 # 	# WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1
- 	48:51	,	0b0001		,	(def_is_rdimm)						;	# RDIMM
- 	48:51	,	0b0000		,	any									;	# WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7)
+# DD0 = PORT_BUFFER_LATENCY
+ 	48:51	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+ 	48:51	,	0x0			,	any									;	# WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7)
 # 	# 9.4.12.2	RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM}
- 	52:55	,	0b0000		,	(def_is_cdimm)						;	# CDIMM
- 	52:55	,	0b0001		,	(def_is_rdimm)						;	# RDIMM
- 	52:55	,	0b0010		,	(def_is_lrdimm)						;	# LRDIMM
+ 	52:55	,	0x0			,	(def_is_cdimm)						;	# CDIMM
+ 	52:55	,	0x1			,	(def_is_rdimm)						;	# RDIMM
+ 	52:55	,	0x2			,	(def_is_lrdimm)						;	# LRDIMM
  	56		,	0b0			,	any									;	# MEMCTL_CIC_FAST
  	57		,	0b0			,	any									;	# MEMCTL_CTRN_IGNORE
  	58		,	0b0			,	any									;	# DISABLE_MEMCTL_CAL
+# 	Memory Type
 # 	# 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM)
  	59:61	,	0b000		,	(def_is_cdimm)						;	# CDIMM
  	59:61	,	0b001		,	((def_is_rdimm) && (def_is_ddr3))	;	# DDR3 RDIMM
  	59:61	,	0b011		,	((def_is_lrdimm) && (def_is_ddr3))	;	# DDR3 LRDIMM
  	59:61	,	0b101		,	((def_is_rdimm) && (def_is_ddr4))	;	# DDR4 RDIMM
  	59:61	,	0b111		,	((def_is_lrdimm) && (def_is_ddr4))	;	# DDR4 LRDIMM
-#	62:63	,	0b00		,	any									;	# reserved
- }
+#	62		,	0b1			,	any									;	# DDR4 Latency Chicken SW
+#	63		,	0b0			,	any									;	# Retain_Percal_SW
+}
+
+# ---------------------------------------------------------------------------------------
+# PC Resets register			default=0xC000
+#
+# This register provides the capability to initiate resets in the hard cores.
+#
+# DPHY01_DDRPHY_PC_RESETS_P0	0x8000c00e0301143f
+scom 0x800(0,1)C00E0301143F {	# Port[0:1]
+	bits	,	scom_data	;
+#	0:47	,	0x000000000000	;	# reserved
+ 	48		,	0b1			;	# PLL_RESET	(all PLL's)
+ 	49		,	0b1			;	# SYSCLK_RESET (all logic in sysclk domain)
+#	50:63	,	0x0000		;	# reserved
+}
 
 # ---------------------------------------------------------------------------------------
 # ADR PLL VREG Config0		default=0	!! register definition for TUNEF not correct for '111b'?
@@ -342,14 +432,32 @@ scom 0x800(0,1)C00D0301143F {
 #scom 0x8000(80,84)300301143F {		# PHY01 Port0 ADR32S[0:1]
 scom 0x800(0,1)BC300301143F {		# PHY01 Port[0:1] broadcast ADR32S[0:1]
 	bits	,	scom_data	,	expr						;
-# 	# 0b111 000 111011 00 00	20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low
- 	48:63	,	0xE3B0		,	((CEN.ATTR_MSS_FREQ/2) < 600)	;	# 300-599.9 MHz, < 1200 MT/s
+#	0:47	,	0x000000000000,	any		;	# reserved
+#	# 0b110 100 101011 00 00	22.22uA, gain 5, SE(3pF, 24pF, 800 ohms), VCO=low, PLLXTR
+#	48:59	,	0xD2B		,	(def_is_sim)					;	# same as DD0
 
-#	# 0b010 000 111000 00 00	40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low
- 	48:63	,	0x4380		,	((CEN.ATTR_MSS_FREQ/2) < 1000)	;	# 600-999.9 MHz, 1200-2000 MT/s
+# 	# 0b111 000 111011 00 00	20uA, gain 1, SE(3pF, 24pF, 200 ohms), VCO=low
+# 	48:63	,	0xE3B0		,	((CEN.ATTR_MSS_FREQ/2) < 600)	;	# 300-599.9 MHz, < 1200 MT/s
+
+#	# 0b010 000 111000 00 00	40uA, gain 1, SE(2pF, 16pF, 200 ohms), VCO=low
+# 	48:63	,	0x4380		,	((CEN.ATTR_MSS_FREQ/2) < 1000)	;	# 600-999.9 MHz, 1200-2000 MT/s
+
+# 	# 0b100 011 111011 01 00	28.57uA, gain 4, SE(3pF, 24pF, 200 ohms), VCO=high
+# 	48:63	,	0x8FB4		,	((CEN.ATTR_MSS_FREQ/2) >= 1000)	;	# 1000-1066 MHz, >=2000 MT/s
+
+#	new setting from Joe Iadanza 11/30
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ < 1200)		;	# < 600 MHz, 1200 MT/s
+
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ < 1460)		;	# < 730 MHz, < 1460 MT/s
+
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ > 1459)		;	# >= 730 MHz, >=1460 MT/s
+
+	60:63	,	0x4			,	(def_is_ddr4)					;	# VCO = high for DDR4
+	60:63	,	0x0			,	any								;	# VCO = low for DDR3 
 
-# 	# 0b100 011 111011 01 00	28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high
- 	48:63	,	0x8FB4		,	((CEN.ATTR_MSS_FREQ/2) >= 1000)	;	# 1000-1066 MHz, >=2000 MT/s
 }
 
 # ---------------------------------------------------------------------------------------
@@ -360,46 +468,50 @@ scom 0x800(0,1)BC300301143F {		# PHY01 Port[0:1] broadcast ADR32S[0:1]
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.P_REG_31_L2
 #scom 0x8000(80,84)310301143f {		# PHY01 Port0 ADR32S[0:1]
 scom 0x800(0,1)BC310301143f {		# PHY01 Port[0:1] broadcast ADR32S[0:1]
-	bits	,	scom_data	,	expr												;
+	bits	,	scom_data	,	expr							;
+#	0:47	,	0x000000000000,	any								;	# reserved
 	# PLL_TUNETDIV(0:2) PLLTESTOUT (000=logic 1, 001=MDIVOUT div by 64, 01x=MDIVOUT div by 1, 1xx=dsabled, logic 0)
-	48:50	,	0b100		,	any													;	# disabled
+#	48:50	,	0b100		,	(def_is_sim)					;	# disabled, for SIM
+	48:50	,	0b111		,	any								;	# disabled, was '100'
 
-	# !! PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value"
-#	51:52	,	0b00		,	any													;	# workaround?
-	51:52	,	0b00		,	((CEN.ATTR_MSS_FREQ/2) < 800)							;	# < 1600 MT/s
-	51:52	,	0b01		,	((CEN.ATTR_MSS_FREQ/2) >= 800)							;	# >=1600 MT/s
+	# PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value(00)"
+	51:52	,	0b00		,	any								;	# same as DD0
+#	51:52	,	0b00		,	((CEN.ATTR_MSS_FREQ/2) < 800)	;	# < 1600 MT/s
+#	51:52	,	0b01		,	((CEN.ATTR_MSS_FREQ/2) >= 800)	;	# >=1600 MT/s
 
 	# PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required"
-	53		,	0b0			,	any													;	# HiZ
+	53		,	0b0			,	any								;	# HiZ
 
 	# VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V)
-	# !! Need to change if using 1.25V since overlap occurs!
- 	54:55	,	0b11		,	CEN.ATTR_MSS_VOLT <= 1271								;	# set to 1.2V
- 	54:55	,	0b01		,	((CEN.ATTR_MSS_VOLT > 1271) && (CEN.ATTR_MSS_VOLT <= 1421))	;	# set to 1.35V
- 	54:55	,	0b00		,	CEN.ATTR_MSS_VOLT > 1421								;	# set to 1.5V
+#	54:55	,	0b01		,	(def_is_sim)					;	# set to 1.35 for SIM
+ 	54:55	,	0b11		,	(CEN.ATTR_MSS_VOLT <= 1271)		;	# set to 1.2V
+ 	54:55	,	0b00		,	any								;	# set to 1.35V & 1.5V
 
 	# VREG_VREGSPARE, Extra pins for later expansion.	should be put to 0
-	56		,	0b0			,	any													;
+	56		,	0b0			,	any								;
 
 	# VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV)
-# !recent
-	57:58	,	0b00		,	(def_is_sim)										;	# match dials
-#	57:58	,	0b10		,	any													;	# standard operating point
+	57:58	,	0b10		,	any								;	# standard operating point
 
 	# INTERP_SIG_SLEW(0:3), Interpolated Signal Slew (PRSTCH pins on ADR16)				clk freq
-#	!! Temp workaround for attribute
- 	59:62	,	0b0000		,	any			;	# match dials
-	59:62	,	0b1001		,	(CEN.ATTR_MSS_FREQ > 2260)								;	# 2400
-	59:62	,	0b1001		,	((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260))	;	# 2133
-	59:62	,	0b0110		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
-	59:62	,	0b1010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
-	59:62	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
-	59:62	,	0b1100		,	((CEN.ATTR_MSS_FREQ > 1013) && (CEN.ATTR_MSS_FREQ <= 1200))	;	# 1066
-	59:62	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 933) && (CEN.ATTR_MSS_FREQ <= 1113))	;	#  800
-	59:62	,	0b1000		,	(CEN.ATTR_MSS_FREQ <= 933)								;	#  666
+#	59:62	,	0b1010		,	(def_is_sim)												;	# for SIM
+#	new setting from Joe Iadanza 11/30
+	59:62	,	0b1000		,	(CEN.ATTR_MSS_FREQ <= 1200)									;	# -1066
+	59:62	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+	59:62	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+	59:62	,	0b1100		,	(CEN.ATTR_MSS_FREQ > 1732)									;	# 1866+
+
+#	59:62	,	0b1001		,	(CEN.ATTR_MSS_FREQ > 2260)									;	# 2400
+#	59:62	,	0b1001		,	((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260))	;	# 2133
+#	59:62	,	0b0110		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
+#	59:62	,	0b1010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+#	59:62	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+#	59:62	,	0b1100		,	((CEN.ATTR_MSS_FREQ > 1013) && (CEN.ATTR_MSS_FREQ <= 1200))	;	# 1066
+#	59:62	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 933) && (CEN.ATTR_MSS_FREQ <= 1113))	;	#  800
+#	59:62	,	0b1000		,	(CEN.ATTR_MSS_FREQ <= 933)									;	#  666
 
 	# ANALOG_WRAPON, Wrap Data control to attached ADR16(s)/ADR12(s)
-	63		,	0b0			,	any													;
+	63		,	0b0			,	any								;
 }
 
 # ---------------------------------------------------------------------------------------
@@ -410,15 +522,33 @@ scom 0x800(0,1)BC310301143f {		# PHY01 Port[0:1] broadcast ADR32S[0:1]
 # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG0_L2
 # scom 0x8000(00,04,08,0C,10)760301143f {	# CONFIG0_P0_[0:4]
 scom 0x800(0,1)3C760301143F {			# CONFIG0_P[0:1] broadcast [0:4]
-	bits	,	scom_data	,	expr						;
- 	# 0b111 000 111011 00 00	20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low
- 	48:63	,	0xE3B0		,	((CEN.ATTR_MSS_FREQ/2) < 600)	;	# 300-599.9 MHz, < 1200 MT/s
+	bits	,	scom_data	,	expr							;
+#	0:47	,	0x000000000000,	any								;	# reserved
+#  	# 0b111 000 111011 00 00	20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low
+#	# 300-599.9 MHz, < 1200 MT/s
+#  	48:59	,	0xE3B		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ < 1200))	;
+# 
+#  	# 0b010 000 111000 00 00	40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low
+#	# 600-999.9 MHz, 1200-2000 MT/s
+#  	48:59	,	0x438		,	((def_is_sim) &&  (CEN.ATTR_MSS_FREQ < 2000))	;	
+# 
+# 	# 0b100 011 111011 01 00	28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high
+#	# 1000-1066 MHz, >=2000 MT/s
+#  	48:59	,	0x8FB		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ >= 2000))	;
 
- 	# 0b010 000 111000 00 00	40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low
- 	48:63	,	0x4380		,	((CEN.ATTR_MSS_FREQ/2) < 1000)	;	# 600-999.9 MHz, 1200-2000 MT/s
+#	new setting from Joe Iadanza 11/30
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ < 1200)		;	# < 600 MHz, 1200 MT/s
 
-	# 0b100 011 111011 01 00	28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high
- 	48:63	,	0x8FB4		,	((CEN.ATTR_MSS_FREQ/2) >= 1000)	;	# 1000-1066 MHz, >=2000 MT/s
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ < 1460)		;	# < 730 MHz, < 1460 MT/s
+
+#	# 0b011 010 101 00 1		33.33uA, gain 3, SE(400 ohms, 16pF, 3pF)
+ 	48:59	,	0x6A9		,	(CEN.ATTR_MSS_FREQ > 1459)		;	# >= 730 MHz, >=1460 MT/s
+
+#	60:63	,	0x0			,	(def_is_sim)					;	# for SIM
+	60:63	,	0x4			,	(CEN.ATTR_MSS_FREQ > 1459)		;	# VCO = high for >= 730MHz or 1460 MT/s
+	60:63	,	0x0			,	any								;	# VCO = low for < 730MHz 
 }
 
 # ---------------------------------------------------------------------------------------
@@ -428,37 +558,36 @@ scom 0x800(0,1)3C760301143F {			# CONFIG0_P[0:1] broadcast [0:4]
 # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG1_L2
 # scom 0x8000(00,04,08,0C,10)770301143f {	# CONFIG1_P0_[0:4]
 scom 0x800(0,1)3C770301143F {	# CONFIG1_P[0:1] broadcast [0:4]
-	bits	,	scom_data	,	expr												;
+	bits	,	scom_data	,	expr							;
+#	0:47	,	0x000000000000,	any								;	# reserved
 	# PLL_TUNETDIV(0:2) PLLTESTOUT (all freq 1xx required)
-	48:50	,	0b100		,	any													;	# disabled
+#	48:50	,	0b100		,	(def_is_sim)					;	# disabled
+	48:50	,	0b111		,	any								;	# disabled
 
-	# !! PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value"
-#	51:52	,	0b00		,	any													;	# workaround?
-	51:52	,	0b00		,	((CEN.ATTR_MSS_FREQ/2) < 800)							;	# < 1600 MT/s
-	51:52	,	0b01		,	((CEN.ATTR_MSS_FREQ/2) >= 800)							;	# >=1600 MT/s
+	# PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value"
+#	51:52	,	0b01		,	(def_is_sim)					;	# 2
+	51:52	,	0b00		,	any								;	# 1
 
 	# PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required"
-	53		,	0b0			,	any													;	# HiZ
+	53		,	0b0			,	any								;	# HiZ
 
 	# VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V)
 	# !! Need to change if using 1.25V since overlap occurs!
- 	54:55	,	0b11		,	CEN.ATTR_MSS_VOLT <= 1271								;	# set to 1.2V
- 	54:55	,	0b01		,	((CEN.ATTR_MSS_VOLT > 1271) && (CEN.ATTR_MSS_VOLT <= 1421))	;	# set to 1.35V
- 	54:55	,	0b00		,	CEN.ATTR_MSS_VOLT > 1421								;	# set to 1.5V
+# 	54:55	,	0b01		,	(def_is_sim)					;	# set to 1.35V for sim
+ 	54:55	,	0b11		,	(CEN.ATTR_MSS_VOLT <= 1271)		;	# set to 1.2V
+ 	54:55	,	0b00		,	any								;	# set to 1.35V, & 1.5V
 
 	# CE0DLTVCCA
-	56		,	0b0			,	any													;	# must be 0
+	56		,	0b0			,	any								;	# must be 0
 
 	# VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV)
-#	!recent
-	57:58	,	0b00		,	(def_is_sim)										;	# match dials
-#	57:58	,	0b10		,	any													;	# standard = 860
+	57:58	,	0b10		,	any								;	# standard = 860
 
-	59		,	0b0			,	any													;	# CE0DLTVCCD1, must be 0
-	60		,	0b0			,	any													;	# CE0DLTVCCD2, must be 0
-	61		,	0b0			,	any													;	# S0INSDLYTAP, must be 0
-	62		,	0b0			,	any													;	# S1INSDLYTAP, must be 0
-#	63		,	0b0			,	any													;	# Reserved
+	59		,	0b0			,	any								;	# CE0DLTVCCD1, must be 0
+	60		,	0b0			,	any								;	# CE0DLTVCCD2, must be 0
+	61		,	0b0			,	any								;	# S0INSDLYTAP, must be 0
+	62		,	0b0			,	any								;	# S1INSDLYTAP, must be 0
+#	63		,	0b0			,	any								;	# reserved
 }
 
 # freq ranges
@@ -487,41 +616,68 @@ scom 0x800(0,1)3C770301143F {	# CONFIG1_P[0:1] broadcast [0:4]
 #	 CEN.ATTR_MSS_FREQ
 #	 ATTR_EFF_CEN_SLEW_RATE_DQ_DQS	[0:15]	0=slow, 15=fast
 #
+#	 FFE=feed forward equalization, DFE=decision feedback equalization
+#
 #	[01:23]						  [0:1][0:4]
 # DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0		0x075	0x800000750301143f
 # PHYW.PHYX.GEN_DP#1.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_CONFIG0_L2
 #scom 0x8000(00,04,08,0C,10)750301143F {	# CONFIG0_P0_[0:4]
-scom 0x800(0,1)3C750301143F {				# CONFIG0_P[0:1] broadcast [0:4]
-	bits	,	scom_data	,	expr												;
+scom 0x80003C750301143F {				# CONFIG0_P0 broadcast [0:4]
+	bits	,	scom_data	,	expr									;
+#	0:47	,	0x000000000000,	any										;	# reserved
+	# INTERP_SIG_SLEW for phase rotator
+# 	48:51	,	0b1100		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200))				;	# 1066
+# 	48:51	,	0b0010		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+# 	48:51	,	0b1010		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+# 	48:51	,	0b0110		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
+# 	48:51	,	0b1001		,	((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260))	;	# 2133
+# 	48:51	,	0b1001		,	(CEN.ATTR_MSS_FREQ > 2260)									;	# 2400
+
+#	new setting from Joe Iadanza 11/30
+ 	48:51	,	0b1000		,	(CEN.ATTR_MSS_FREQ <= 1200)									;	# 1066
+ 	48:51	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+ 	48:51	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+ 	48:51	,	0b1100		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
+
+	# Post Cursor, tap coefficient for FFE, 0=no equalization
+	52:55	,	0b0001		,	(def_ffe1_p0)							;
+	52:55	,	0b0011		,	(def_ffe2_p0)							;
+	52:55	,	0b0111		,	(def_ffe3_p0)							;
+	52:55	,	0b1111		,	(def_ffe4_p0)							;
+	52:55	,	0b0000		,	any										;
+
+	# Slew rate set in ddrphy_reset procedure via slew FN call
+#	56:59	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 0)	;	# SLEW_CTL, slowest
+#	60:63	,	0b0000		,	any										;	# reserved
+}
+
+# DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0		0x075	0x800100750301143f
+scom 0x80013C750301143F {				# CONFIG0_P1 broadcast [0:4]
+	bits	,	scom_data	,	expr									;
+#	0:47	,	0x000000000000,	any										;	# reserved
 	# INTERP_SIG_SLEW for phase rotator
- 	48:51	,	0b1001		,	(CEN.ATTR_MSS_FREQ > 2260)								;	# 2400
- 	48:51	,	0b1001		,	((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260))	;	# 2133
- 	48:51	,	0b0110		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
- 	48:51	,	0b1010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
- 	48:51	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
- 	48:51	,	0b1100		,	(CEN.ATTR_MSS_FREQ <= 1200)								;	# 1066
-
-	# Post Cursor, tap coefficient for FFE, 0=no equalization, will be taken out for DD1?
-	52:55	,	0b0000		,	any													;
-
-	#  choices... 0=2.83, 1=3.35, 2=4.35, 3=5.16, 4=6.16, 5=6.50 V/ns, 6..F ~180mV/step
-	56:59	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 0)				;	# SLEW_CTL, slowest
-	56:59	,	0b0001		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 1)				;	# faster .
-	56:59	,	0b0010		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 2)				;	# faster ..
-	56:59	,	0b0011		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 3)				;	# faster ...
-	56:59	,	0b0100		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 4)				;	# faster ....
-	56:59	,	0b0101		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 5)				;	# faster .....
-	56:59	,	0b0110		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 6)				;	# faster ......
-	56:59	,	0b0111		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 7)				;	# faster .......
-	56:59	,	0b1000		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 8)				;	# faster ........
-	56:59	,	0b1001		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 9)				;	# faster .........
-	56:59	,	0b1010		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 10)				;	# faster ..........
-	56:59	,	0b1011		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 11)				;	# faster ...........
-	56:59	,	0b1100		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 12)				;	# faster ............
-	56:59	,	0b1101		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 13)				;	# faster .............
-	56:59	,	0b1110		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 14)				;	# faster ..............
-	56:59	,	0b1111		,	(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 15)				;	# fastest...............
-#	60:63	,	0b0000		,	any													;	# reserved
+# 	48:51	,	0b1100		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200))				;	# 1066
+# 	48:51	,	0b0010		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+# 	48:51	,	0b1010		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+# 	48:51	,	0b0110		,	((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
+# 	48:51	,	0b1001		,	((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260))	;	# 2133
+# 	48:51	,	0b1001		,	(CEN.ATTR_MSS_FREQ > 2260)									;	# 2400
+
+#	new setting from Joe Iadanza 11/30
+ 	48:51	,	0b1000		,	(CEN.ATTR_MSS_FREQ <= 1200)									;	# 1066
+ 	48:51	,	0b0100		,	((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460))	;	# 1333
+ 	48:51	,	0b0010		,	((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732))	;	# 1600
+ 	48:51	,	0b1100		,	((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993))	;	# 1866
+	
+	# Post Cursor, tap coefficient for FFE, 0=no equalization
+	52:55	,	0b0001		,	(def_ffe1_p1)							;
+	52:55	,	0b0011		,	(def_ffe2_p1)							;
+	52:55	,	0b0111		,	(def_ffe3_p1)							;
+	52:55	,	0b1111		,	(def_ffe4_p1)							;
+	52:55	,	0b0000		,	any										;
+	# Slew rate set in ddrphy_reset procedure via slew FN call
+#	56:59	,	0b0000		,	any										;
+#	60:63	,	0b0000		,	any										;	# reserved
 }
 
 # ---------------------------------------------------------------------------------------
@@ -535,7 +691,7 @@ scom 0x800(0,1)3C750301143F {				# CONFIG0_P[0:1] broadcast [0:4]
 # 48:55 = N/P FET slices (0-7), 56:59 = N/P FET FFE slices (0-4)
 # 2 slices of 480 (FFE) = 1 slice of 240 (non-FFE)
 #
-# for DDR4 where VDDR (POD)
+# for DDR4 where VDDR (POD=Pseudo Open Drain)
 # DDR4 ohms = 1 / ((1 / (total 240 slices / 240)) + (1 / (total 480 slices / 480)))
 #
 # for DDR3 VDDR/2
@@ -545,67 +701,106 @@ scom 0x800(0,1)3C750301143F {				# CONFIG0_P[0:1] broadcast [0:4]
 # DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0	0x07A	0x8000007a0301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_TERM_L2(0:11)
 #scom 0x8000(00,04,08,0C,10)7A0301143f {	# NFET_TERM_P0_[0:4]	broadcast
-scom 0x800(0,1)3C7A0301143f {				# NFET_TERM_P[0:1]_[0:4]	broadcast
+scom 0x80003C7A0301143f {				# NFET_TERM_P0_[0:4]	broadcast
 	bits	,	scom_data	,	expr								;
+#	0:47	,	0x000000000000,	any									;	# reserved
 	# 						for DDR3 = 1				ohms			# ohm/slices
-	48:59	,	0xFF0	,	((def_is_ddr3) && (def_cri_dqs_ohm15))	;	# 240/8, 480/0
-	48:59	,	0x7E0	,	((def_is_ddr3) && (def_cri_dqs_ohm20))	;	# 240/6, 480/0
-	48:59	,	0x182	,	((def_is_ddr3) && (def_cri_dqs_ohm48))	;	# 240/2, 480/1
-
-	48:59	,	0x03F	,	((def_is_ddr3) && (def_cri_dqs_ohm30))	;	# 240/2, 480/4
-	48:59	,	0x01F	,	((def_is_ddr3) && (def_cri_dqs_ohm40))	;	# 240/1, 480/4
-	48:59	,	0x00F	,	((def_is_ddr3) && (def_cri_dqs_ohm60))	;	# 240/0, 480/4
-	48:59	,	0x007	,	((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/0, 480/3
-	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm120))	;	# 240/0, 480/2
-# Joe Iadanza's spreadsheet (from Saravana note 3/28/12 11:20A) has this...
-# 	48:59	,	0x3C0	,	((def_is_ddr3) && (def_cri_dqs_ohm30))	;	# 240/4, 480/0
-# 	48:59	,	0x186	,	((def_is_ddr3) && (def_cri_dqs_ohm40))	;	# 240/2, 480/2
-# 	48:59	,	0x180	,	((def_is_ddr3) && (def_cri_dqs_ohm60))	;	# 240/2, 480/0
-# 	48:59	,	0x102	,	((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/1, 480/1
-# 	48:59	,	0x100	,	((def_is_ddr3) && (def_cri_dqs_ohm120))	;	# 240/1, 480/0
-#
-#   !! need to find out if supporting POD Mode Termination (DDR4 only?)
-#   if no, then remove def_is_ddr3 from statements above
-#	if yes, then leave above statements and remove commented section below.
-#
-#	Note 6) For POD Mode Termination, the slice vector is only applied to the PFET portion of the Driver (High).
-#	The	NFET portion of the Driver uses vector 0,0 for high impedance
-#
-#	48:59	,	0x03F	,	((def_is_ddr4) && (def_cri_dqs_ohm60))	;	# 240/2, 480/4
-#	48:59	,	0x01F	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/1, 480/4
-#	48:59	,	0x00F	,	((def_is_ddr4) && (def_cri_dqs_ohm120))	;	# 240/0, 480/4
-#	48:59	,	0x007	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160))	;	# 240/0, 480/3
-#	48:59	,	0x003	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240))	;	# 240/0, 480/2
-#							for DDR4 will catch DDR3 & not valid imp
-	48:59	,	0x000	,	any										;	# 240/0, 480/0
+# Joe Iadanza's spreadsheet (from Saravanan note 3/28/12 11:20A) has this...
+	48:59	,	0xFF0	,	((def_is_ddr3) && (def_cri_dqs_ohm15_p0))	;	# 240/8, 480/0
+	48:59	,	0x7E0	,	((def_is_ddr3) && (def_cri_dqs_ohm20_p0))	;	# 240/6, 480/0
+ 	48:59	,	0x3C0	,	((def_is_ddr3) && (def_cri_dqs_ohm30_p0))	;	# 240/4, 480/0
+# 	48:59	,	0x382	,	((def_is_ddr3) && (def_cri_dqs_ohm34_p0))	;	# 240/3, 480/1
+ 	48:59	,	0x186	,	((def_is_ddr3) && (def_cri_dqs_ohm40_p0))	;	# 240/2, 480/2
+	48:59	,	0x182	,	((def_is_ddr3) && (def_cri_dqs_ohm48_p0))	;	# 240/2, 480/1
+ 	48:59	,	0x180	,	((def_is_ddr3) && (def_cri_dqs_ohm60_p0))	;	# 240/2, 480/0
+ 	48:59	,	0x102	,	((def_is_ddr3) && (def_cri_dqs_ohm80_p0))	;	# 240/1, 480/1
+ 	48:59	,	0x100	,	((def_is_ddr3) && (def_cri_dqs_ohm120_p0))	;	# 240/1, 480/0
+	48:59	,	0x007	,	((def_is_ddr3) && (def_cri_dqs_ohm160_p0))	;	# 240/0, 480/3
+	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm240_p0))	;	# 240/0, 480/2
+	48:59	,	0x000	,	any											;	# 240/0, 480/0
+#	60:63	,	0b0000	,	any											;	# reserved
 }
 # DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0	0x07B	0x8000007B0301143f
 #scom 0x8000(00,04,08,0C,10)7B0301143f {	# PFET_TERM_P0_[0:4]
-scom 0x800(0,1)3C7B0301143f {				# PFET_TERM_P[0:1]_[0:4]	broadcast
+scom 0x80003C7B0301143f {				# PFET_TERM_P0_[0:4]	broadcast
+	bits	,	scom_data,	expr									;
+#	0:47	,	0x000000000000,	any									;	# reserved
+	# 						for DDR3 = 1		 		  ohms			# ohm/slices
+	48:59	,	0xFF0	,	((def_is_ddr3) && (def_cri_dqs_ohm15_p0))	;	# 240/8, 480/0
+	48:59	,	0x7E0	,	((def_is_ddr3) && (def_cri_dqs_ohm20_p0))	;	# 240/6, 480/0
+ 	48:59	,	0x3C0	,	((def_is_ddr3) && (def_cri_dqs_ohm30_p0))	;	# 240/4, 480/0
+ #	48:59	,	0x382	,	((def_is_ddr3) && (def_cri_dqs_ohm34_p0))	;	# 240/3, 480/1
+ 	48:59	,	0x186	,	((def_is_ddr3) && (def_cri_dqs_ohm40_p0))	;	# 240/2, 480/2
+	48:59	,	0x182	,	((def_is_ddr3) && (def_cri_dqs_ohm48_p0))	;	# 240/2, 480/1
+ 	48:59	,	0x180	,	((def_is_ddr3) && (def_cri_dqs_ohm60_p0))	;	# 240/2, 480/0
+ 	48:59	,	0x102	,	((def_is_ddr3) && (def_cri_dqs_ohm80_p0))	;	# 240/1, 480/1
+ 	48:59	,	0x100	,	((def_is_ddr3) && (def_cri_dqs_ohm120_p0))	;	# 240/1, 480/0
+	48:59	,	0x007	,	((def_is_ddr3) && (def_cri_dqs_ohm160_p0))	;	# 240/0, 480/3
+	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm240_p0))	;	# 240/0, 480/2
+	#						for DDR4 = 2
+ #	48:59	,	0x7E6	,	((def_is_ddr4) && (def_cri_dqs_ohm34_p0))	;	# 240/8, 480/2
+ 	48:59	,	0x7E0	,	((def_is_ddr4) && (def_cri_dqs_ohm40_p0))	;	# 240/8, 480/0
+ 	48:59	,	0x3C6	,	((def_is_ddr4) && (def_cri_dqs_ohm48_p0))	;	# 240/4, 480/2
+ 	48:59	,	0x3C0	,	((def_is_ddr4) && (def_cri_dqs_ohm60_p0))	;	# 240/4, 480/0
+ 	48:59	,	0x186	,	((def_is_ddr4) && (def_cri_dqs_ohm80_p0))	;	# 240/2, 480/2
+ 	48:59	,	0x180	,	((def_is_ddr4) && (def_cri_dqs_ohm120_p0))	;	# 240/2, 480/0
+# 	48:59	,	0x---	,	((def_is_ddr4) && (def_cri_dqs_ohm160_p0))	;	# 240/?, 480/?
+ 	48:59	,	0x100	,	((def_is_ddr4) && (def_cri_dqs_ohm240_p0))	;	# 240/1, 480/0
+# 	48:59	,	0x002	,	((def_is_ddr4) && (def_cri_dqs_ohm480_p0))	;	# 240/0, 480/1
+ 	48:59	,	0x000	,	any											;	# 240/0, 480/0
+#	60:63	,	0b0000	,	any											;	# reserved
+}
+
+# DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0	0x07A	0x8001007a0301143f
+#scom 0x8001(00,04,08,0C,10)7A0301143f {	# NFET_TERM_P1_[0:4]	broadcast
+scom 0x80013C7A0301143f {				# NFET_TERM_P1_[0:4]	broadcast
+	bits	,	scom_data	,	expr								;
+#	0:47	,	0x000000000000,	any									;	# reserved
+	# 						for DDR3 = 1				ohms			# ohm/slices
+	48:59	,	0xFF0	,	((def_is_ddr3) && (def_cri_dqs_ohm15_p1))	;	# 240/8, 480/0
+	48:59	,	0x7E0	,	((def_is_ddr3) && (def_cri_dqs_ohm20_p1))	;	# 240/6, 480/0
+ 	48:59	,	0x3C0	,	((def_is_ddr3) && (def_cri_dqs_ohm30_p1))	;	# 240/4, 480/0
+# 	48:59	,	0x382	,	((def_is_ddr3) && (def_cri_dqs_ohm34_p1))	;	# 240/3, 480/1
+ 	48:59	,	0x186	,	((def_is_ddr3) && (def_cri_dqs_ohm40_p1))	;	# 240/2, 480/2
+	48:59	,	0x182	,	((def_is_ddr3) && (def_cri_dqs_ohm48_p1))	;	# 240/2, 480/1
+ 	48:59	,	0x180	,	((def_is_ddr3) && (def_cri_dqs_ohm60_p1))	;	# 240/2, 480/0
+ 	48:59	,	0x102	,	((def_is_ddr3) && (def_cri_dqs_ohm80_p1))	;	# 240/1, 480/1
+ 	48:59	,	0x100	,	((def_is_ddr3) && (def_cri_dqs_ohm120_p1))	;	# 240/1, 480/0
+	48:59	,	0x007	,	((def_is_ddr3) && (def_cri_dqs_ohm160_p1))	;	# 240/0, 480/3
+	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm240_p1))	;	# 240/0, 480/2
+	48:59	,	0x000	,	any											;	# 240/0, 480/0
+#	60:63	,	0b0000	,	any											;	# reserved
+}
+# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0	0x07B	0x8000007B0301143f
+#scom 0x8000(00,04,08,0C,10)7B0301143f {	# PFET_TERM_P1_[0:4]
+scom 0x80013C7B0301143f {				# PFET_TERM_P1_[0:4]	broadcast
 	bits	,	scom_data,	expr									;
+#	0:47	,	0x000000000000,	any									;	# reserved
 	# 						for DDR3 = 1		 		  ohms			# ohm/slices
-	48:59	,	0x03F	,	((def_is_ddr3) && (def_cri_dqs_ohm30))	;	# 240/2, 480/4
-	48:59	,	0x01F	,	((def_is_ddr3) && (def_cri_dqs_ohm40))	;	# 240/1, 480/4
-	48:59	,	0x00F	,	((def_is_ddr3) && (def_cri_dqs_ohm60))	;	# 240/0, 480/4
-	48:59	,	0x007	,	((def_is_ddr3) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/0, 480/3
-	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm120))	;	# 240/0, 480/2
+	48:59	,	0xFF0	,	((def_is_ddr3) && (def_cri_dqs_ohm15_p1))	;	# 240/8, 480/0
+	48:59	,	0x7E0	,	((def_is_ddr3) && (def_cri_dqs_ohm20_p1))	;	# 240/6, 480/0
+ 	48:59	,	0x3C0	,	((def_is_ddr3) && (def_cri_dqs_ohm30_p1))	;	# 240/4, 480/0
+# 	48:59	,	0x382	,	((def_is_ddr3) && (def_cri_dqs_ohm34_p1))	;	# 240/3, 480/1
+ 	48:59	,	0x186	,	((def_is_ddr3) && (def_cri_dqs_ohm40_p1))	;	# 240/2, 480/2
+	48:59	,	0x182	,	((def_is_ddr3) && (def_cri_dqs_ohm48_p1))	;	# 240/2, 480/1
+ 	48:59	,	0x180	,	((def_is_ddr3) && (def_cri_dqs_ohm60_p1))	;	# 240/2, 480/0
+ 	48:59	,	0x102	,	((def_is_ddr3) && (def_cri_dqs_ohm80_p1))	;	# 240/1, 480/1
+ 	48:59	,	0x100	,	((def_is_ddr3) && (def_cri_dqs_ohm120_p1))	;	# 240/1, 480/0
+	48:59	,	0x007	,	((def_is_ddr3) && (def_cri_dqs_ohm160_p1))	;	# 240/0, 480/3
+	48:59	,	0x003	,	((def_is_ddr3) && (def_cri_dqs_ohm240_p1))	;	# 240/0, 480/2
 	#						for DDR4 = 2
-	48:59	,	0x03F	,	((def_is_ddr4) && (def_cri_dqs_ohm60))	;	# 240/2, 480/4
-	48:59	,	0x01F	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/1, 480/4
-#	48:59	,	0x01F	,	((def_is_ddr4) && (def_cri_dqs_ohm80))	;	# 240/1, 480/4
-	48:59	,	0x00F	,	((def_is_ddr4) && (def_cri_dqs_ohm120))	;	# 240/0, 480/4
-	48:59	,	0x007	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160))	;	# 240/0, 480/3
-	48:59	,	0x003	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240))	;	# 240/0, 480/2
-	48:59	,	0x000	,	any										;	# 240/0, 480/0
-# Joe Iadanza's spreadsheet (from Saravana note 3/28/12 11:20A) has this...
-# 	48:59	,	0x3C0	,	((def_is_ddr4) && (def_cri_dqs_ohm60))	;	# 240/4, 480/0
-# 	48:59	,	0x186	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 80))	;	# 240/2, 480/2
-# 	48:59	,	0x180	,	((def_is_ddr4) && (def_cri_dqs_ohm120))	;	# 240/2, 480/0
-# 	48:59	,	0x---	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 160))	;	# 240/?, 480/?
-# 	48:59	,	0x100	,	((def_is_ddr4) && (ATTR_EFF_CEN_RCV_IMP_DQ_DQS == 240))	;	# 240/1, 480/0
-# 	48:59	,	0x000	,	any										;	# 240/0, 480/0
+# 	48:59	,	0x7E6	,	((def_is_ddr4) && (def_cri_dqs_ohm34_p1))	;	# 240/8, 480/2
+ 	48:59	,	0x7E0	,	((def_is_ddr4) && (def_cri_dqs_ohm40_p1))	;	# 240/8, 480/0
+ 	48:59	,	0x3C6	,	((def_is_ddr4) && (def_cri_dqs_ohm48_p1))	;	# 240/4, 480/2
+ 	48:59	,	0x3C0	,	((def_is_ddr4) && (def_cri_dqs_ohm60_p1))	;	# 240/4, 480/0
+ 	48:59	,	0x186	,	((def_is_ddr4) && (def_cri_dqs_ohm80_p1))	;	# 240/2, 480/2
+ 	48:59	,	0x180	,	((def_is_ddr4) && (def_cri_dqs_ohm120_p1))	;	# 240/2, 480/0
+# 	48:59	,	0x---	,	((def_is_ddr4) && (def_cri_dqs_ohm160_p1))	;	# 240/?, 480/?
+ 	48:59	,	0x100	,	((def_is_ddr4) && (def_cri_dqs_ohm240_p1))	;	# 240/1, 480/0
+# 	48:59	,	0x002	,	((def_is_ddr4) && (def_cri_dqs_ohm480_p1))	;	# 240/0, 480/1
+ 	48:59	,	0x000	,	any											;	# 240/0, 480/0
+#	60:63	,	0b0000	,	any											;	# reserved
 }
-
 # ---------------------------------------------------------------------------------------
 # Output(DQ/DQS) driver impedance settings
 #
@@ -613,26 +808,33 @@ scom 0x800(0,1)3C7B0301143f {				# PFET_TERM_P[0:1]_[0:4]	broadcast
 #
 #  [01:23]				 [N:P]	[0:1][0:4]
 # DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0	0x078	0x800000780301143f
+# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0	0x079	0x800000790301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_SLICE_L2(0:11)
-#scom 0x800(0,1)3C780301143f {	# NFET_SLICE_P[0:1]_[0:4]	broadcast
-scom 0x800(0,1)3C7(8,9)0301143F {	# [N:P]FET_SLICE_P[0:1]_[0:4]	broadcast
-	bits	,	scom_data	,	expr				;	# ohm/slices
-	48:59	,	0xFFF		,	(def_cdi_dqs_ohm24)	;	# 240/8, 480/4
-	48:59	,	0x3FF		,	(def_cdi_dqs_ohm30)	;	# 240/6, 480/4
-	48:59	,	0x1FF		,	(def_cdi_dqs_ohm34)	;	# 240/5, 480/4
-	48:59	,	0x0FF		,	(def_cdi_dqs_ohm40)	;	# 240/4, 480/4
-	48:59	,	0x000		,	any					;	# 240/0, 480/0
+# (00,04,08,0C,10)
+#scom 0x80003C780301143f {	# NFET_SLICE_P0_[0:4]	broadcast
+scom 0x80003C7(8,9)0301143F {	# [N:P]FET_SLICE_P0_[0:4]	broadcast
+	bits	,	scom_data	,	expr					;	# ohm/slices
+#	0:47	,	0x000000000000,	any						;	# reserved
+	48:59	,	0xFFF		,	(def_cdi_dqs_ohm24_p0)	;	# 240/8, 480/4
+	48:59	,	0x7EF		,	(def_cdi_dqs_ohm30_p0)	;	# 240/6, 480/4
+	48:59	,	0x3EF		,	(def_cdi_dqs_ohm34_p0)	;	# 240/5, 480/4
+	48:59	,	0x3CF		,	(def_cdi_dqs_ohm40_p0)	;	# 240/4, 480/4
+	48:59	,	0x000		,	any						;	# 240/0, 480/0
+#	60:63	,	0b0000		,	any							;	# reserved
+}
+
+# DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0	0x078	0x800100780301143f
+# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0	0x079	0x800100790301143f
+scom 0x80013C7(8,9)0301143F {	# [N:P]FET_SLICE_P1_[0:4]	broadcast
+	bits	,	scom_data	,	expr					;	# ohm/slices
+#	0:47	,	0x000000000000,	any						;	# reserved
+	48:59	,	0xFFF		,	(def_cdi_dqs_ohm24_p1)	;	# 240/8, 480/4
+	48:59	,	0x7EF		,	(def_cdi_dqs_ohm30_p1)	;	# 240/6, 480/4
+	48:59	,	0x3EF		,	(def_cdi_dqs_ohm34_p1)	;	# 240/5, 480/4
+	48:59	,	0x3CF		,	(def_cdi_dqs_ohm40_p1)	;	# 240/4, 480/4
+	48:59	,	0x000		,	any						;	# 240/0, 480/0
+#	60:63	,	0b0000		,	any						;	# reserved
 }
-# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0	0x079	0x800000790301143f
-#scom 0x800(0,1)3C790301143f {	# PFET_SLICE_P[0:1]_[0:4]	broadcast
-#	bits	,	scom_data,	expr;
-#	48:55	,	0xFF		,	(def_cdi_dqs_ohm24)	;	# 240/8
-#	48:55	,	0x3F		,	(def_cdi_dqs_ohm30)	;	# 240/6
-#	48:55	,	0x1F		,	(def_cdi_dqs_ohm34)	;	# 240/5
-#	48:55	,	0x0F		,	(def_cdi_dqs_ohm40)	;	# 240/4
-#	48:55	,	0x00		,	any									;	# 240/0
-#	56:59	,	0x0F		,	any									;	# FFE=480/4
-#}
 
 #**********************************************************************************
 #!! DO NOT NEED to set for Centaur from Joe Iadanza.
@@ -654,22 +856,24 @@ scom 0x800(0,1)3C7(8,9)0301143F {	# [N:P]FET_SLICE_P[0:1]_[0:4]	broadcast
 #! ---------------------------------------------------------------------------------------
 #! ---  PHY01 ADR IO NFET SLICE EN[0:3] P[0:1] ADR[0:3] ---------------------------
 #! ---------------------------------------------------------------------------------------
-#!DPHY01.DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0 from (alias spydef)
+#!DPHY01.DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0
 #!scom 0x800(0,1)(40,44,48,4C)100301143F {
 #!scom 0x800(0,1)(40,44,48,4C)(10,11,12,13)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3]
 #!scom 0x800(0,1)7C(10,11,12,13)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3] via broadcast
 #!	bits	,	scom_data	;
+#	0:47	,	0x000000000000			;	# reserved
 #!	48:63	,	0b1111111111110000		;
 #!}
 #!
 #! ---------------------------------------------------------------------------------------
 #! ---     PHY01 ADR IO PFET SLICE EN[0:3] P[0:1] ADR[0:3]    ---------------------------
 #! ---------------------------------------------------------------------------------------
-#!DPHY01.DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0 from (alias spydef)
+#!DPHY01.DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0
 #!scom 0x800(0,1)(40,44,48,4C)140301143F {
 #!scom 0x800(0,1)(40,44,48,4C)(14,15,16,17)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3]
 #!scom 0x800(0,1)7C(14,15,16,17)0301143F {	# EN[0:3]_P[0:1]_ADR[0:3] via broadcast
 #!	bits	,	scom_data	;
+#	0:47	,	0x000000000000			;	# reserved
 #!	48:63	,	0b1111111111110000		;
 #!}
 #**********************************************************************************
@@ -692,53 +896,80 @@ scom 0x800(0,1)3C7(8,9)0301143F {	# [N:P]FET_SLICE_P[0:1]_[0:4]	broadcast
 # 11b = 40 ohm
 #
 # ---------------------------------------------------------------------------------
-# -----------------  Port 0  ADR 0  -----------------------------------------------
+# -----------------  Port 0  ADR 0  -------------------------- !! board wiring dependent !!
 # ---------------------------------------------------------------------------------
 #  [01:23]                         [0:1][0:1][0:3]
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0	0x020	0x800040200301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.REG_A_20_L2(0:15)
 scom 0x800040200301143f {
-	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL0
-	48:49	,	0b11		,	any					;	# SEL0, 40 or anything
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3
-#	48:55	,	0b00000000	,	(def_cdi_ctl_ohm15)	;	# SEL0:SEL3
-#	48:55	,	0b01010101	,	(def_cdi_ctl_ohm20)	;	# SEL0:SEL3
-#	48:55	,	0b10101010	,	(def_cdi_ctl_ohm30)	;	# SEL0:SEL3
-#	48:55	,	0b11111111	,	(def_cdi_ctl_ohm40)	;	# SEL0:SEL3
-#	48:55	,	0x00		,	(def_cdi_ctl_ohm15)	;	# SEL0:SEL3
-#	48:55	,	0x55		,	(def_cdi_ctl_ohm20)	;	# SEL0:SEL3
-#	48:55	,	0xAA		,	(def_cdi_ctl_ohm30)	;	# SEL0:SEL3
-#	48:55	,	0xFF		,	(def_cdi_ctl_ohm40)	;	# SEL0:SEL3
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+	bits	,	scom_data	,	expr					;
+#	0:47	,	0x000000000000,	any						;	# reserved
+#  ------ PORT 0  ADR 0  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 0, A1_CKE1
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0)	&& (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0)	&& (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) 	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 1, A0_CS3n
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 2, A1_CKE0
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 3, A0_ODT0
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 4, A_A15
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 5, A_PAR
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 6, A0_CKE1
+	60:61	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 7, A0_CS1n
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 0  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 0, C0_CS0n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0)	&& (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0)	&& (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) 	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 1, C_A3
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 2, C1_CS3n
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 3, C_RASn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 4, C_A12
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 5, C_A7
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 6, C0_CLK1_p
+	60:61	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	60:61	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	60:61	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	62:63	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 7, C0_CLK1_n
+	62:63	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
 #	48:63	,	0x0000		,	any									;	# SEL0-7
 }
 # ADR I/O FET Slice Enable Map 1, register 1 containing lanes 8:15
@@ -746,209 +977,410 @@ scom 0x800040200301143f {
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0
 scom 0x800040210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL10 clk
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL10 clk
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL10 clk
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL10 clk
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL11 clk
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL11 clk
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL11 clk
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL11 clk
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 0  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 8, A0_CKE0
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 9, A1_ODT0
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 10, A0_CLK0_p
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 11, A0_CLK0_n
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 0  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 8, C1_CLK1_p
+	48:49	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 9, C1_CLK1_n
+	50:51	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba23));	# 10, C1_CKE2
+	52:53	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba23));
+	52:53	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba23));
+	52:53	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba23));
+	54:55	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba23));	# 11, C0_CKE2
+	54:55	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba23));
+	54:55	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba23));
+	54:55	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba23));
+#	56:63	,	0x00		,	any					;	# reserved
 }
 # -----------------  Port 0  ADR 1  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1
 scom 0x800044200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL3
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 1  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 0, A0_CS0n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba01));	# 1, A1_CKE3
+	50:51	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba01));
+	50:51	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba01));
+	50:51	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba01));
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 2, A1_ODT1
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 3, A_A2
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 4, A_A6
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 5, A_A1
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 6, A_A14
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba01));	# 7, A0_CKE2
+	62:63	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba01));
+	62:63	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba01));
+	62:63	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba01));
+#  ------ PORT 2  ADR 1  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 0, C_BA2
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 1, C1_CKE1
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 2, C0_ODT1
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 3, C_WEn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 4, C0_CS1n
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 5, C_A11
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba23));	# 6, C0_CKE3
+	60:61	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba23));
+	60:61	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba23));
+	60:61	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba23));
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 7, C0_CS2n
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1
 scom 0x800044210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL11
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 1  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 8, A1_CS2n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba01));	# 9, A1_CKE2
+	50:51	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba01));
+	50:51	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba01));
+	50:51	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba01));
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 10, A_A4
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 11, A_RASn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 1  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 8, C0_ODT0
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 9, C_A8
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 10, C_A5
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 11, C1_CS0n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+#	56:63	,	0x00		,	any					;	# reserved
 }
 # -----------------  Port 0  ADR 2  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2
 scom 0x800048200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL4 clk
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL4 clk
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL4 clk
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL4 clk
-	58:59	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL5 clk
-	58:59	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL5 clk
-	58:59	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL5 clk
-	58:59	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL5 clk
-	60:61	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 2  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 0, A_A12
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 1, A_A0
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba01));	# 2, A0_CKE3
+	52:53	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba01));
+	52:53	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba01));
+	52:53	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba01));
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 3, A1_CS3n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 4, A1_CLK0_p
+	56:57	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 5, A1_CLK0_n
+	58:59	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 6, A0_ODT1
+	60:61	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 7, A1_CS0n
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 2  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 0, C_A1
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 1, C_A6
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 2, C_A13
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 3, C0_CKE0
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 4, C1_ODT0
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 5, C1_CS1n
+	58:59	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 6, C0_CKE1
+	60:61	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	60:61	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	60:61	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 7, C1_CKE0
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2
 scom 0x800048210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL10 clk
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL10 clk
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL10 clk
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL10 clk
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL11 clk
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL11 clk
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL11 clk
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL11 clk
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL12 clk
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL12 clk
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL12 clk
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL12 clk
-	58:59	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL13 clk
-	58:59	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL13 clk
-	58:59	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL13 clk
-	58:59	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL13 clk
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 2  lanes 8:13 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 8, A1_CS1n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 9, A_A10
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 10, A0_CLK1_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 11, A0_CLK1_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 12, A1_CLK1_n
+	56:57	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba01))	;	# 13, A1_CLK1_p
+	58:59	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 2  lanes 8:13 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 8, C_A0
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 9, C_BA1
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 10, C0_CLK0_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 11, C0_CLK0_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 12, C1_CS2n
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 13, C_A10
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+#	60:63	,	0b0000		,	any					;	# reserved
 }
 # -----------------  Port 0  ADR 3  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3
 scom 0x80004c200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 3  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 0, A_A13
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 1, A_BA0
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 2, A_WEn
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba01))	;	# 3, A0_CS2n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 4, A_BA1
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 5, A_CASn
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 6, A_A5
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 7, A_A3
+	62:63	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 3  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 0, C_PAR
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 1, C1_ODT1
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 2, C1_CLK0_p
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p0) && (def_is_mba23))	;	# 3, C1_CLK0_n
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 4, C_A14
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 5, C_A9
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 6, C_ACTn
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	62:63	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 7, C_A2
+	62:63	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3
 scom 0x80004c210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL11
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL12
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL12
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL12
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL12
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL13
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL13
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL13
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL13
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 0  ADR 3  lanes 8:13 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 8, A_BA2
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 9, A_A11
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 10, A_A7
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 11, A_ACTn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 12, A_A9
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba01))	;	# 13, A_A8
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba01))	;
+#  ------ PORT 2  ADR 3  lanes 8:13 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_spcke_ohm15_p0) && (def_is_mba23));	# 8, C1_CKE3
+	48:49	,	0b01		,	((def_cdi_spcke_ohm20_p0) && (def_is_mba23));
+	48:49	,	0b10		,	((def_cdi_spcke_ohm30_p0) && (def_is_mba23));
+	48:49	,	0b11		,	((def_cdi_spcke_ohm40_p0) && (def_is_mba23));
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 9, C_A15
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 10, C_BA0
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 11, C_CASn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p0) && (def_is_mba23))	;	# 12, C_A4
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p0) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p0) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p0) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_ctl_ohm15_p0) && (def_is_mba23))	;	# 13, C0_CS3n
+	58:59	,	0b01		,	((def_cdi_ctl_ohm20_p0) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_ctl_ohm30_p0) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_ctl_ohm40_p0) && (def_is_mba23))	;
+#	60:63	,	0b0000		,	any					;	# reserved
 }
 # =================================================================================
 # -----------------  Port 1  ADR 0  -----------------------------------------------
@@ -956,328 +1388,510 @@ scom 0x80004c210301143f {
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0
 scom 0x800140200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL0 clk
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL0 clk
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL0 clk
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL0 clk
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL1 clk
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL1 clk
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL1 clk
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL1 clk
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL2 clk
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL2 clk
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL2 clk
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL2 clk
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3 clk
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3 clk
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3 clk
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3 clk
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 0  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 0, B1_CLK0_n
+	48:49	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 1, B1_CLK0_p
+	50:51	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 2, B1_CLK1_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 3, B1_CLK1_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba01));	# 4, B0_CKE3
+	56:57	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba01));
+	56:57	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba01));
+	56:57	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba01));
+	58:59	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 5, B0_CS3n
+	58:59	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 6, B_BA0
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 7, B1_ODT1
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 0  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 0, D1_CKE1
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 1, D_BA2
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 2, D_A1
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 3, D_A5
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 4, D_A12
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 5, D_BA0
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba23));	# 6, D1_CKE2
+	60:61	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba23));
+	60:61	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba23));
+	60:61	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba23));
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 7, D1_CS1n
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0
 scom 0x800140210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL11
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 0  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba01));	# 8, B1_CKE3
+	48:49	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba01));
+	48:49	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba01));
+	48:49	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba01));
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 9, B_A15
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 10, B1_CS2n
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 11, B0_CKE1
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 0  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 8, D0_CKE0
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 9, D0_CS2n
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 10, D1_CLK0_p
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 11, D1_CLK0_n
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+#	56:63	,	0x00		,	any					;	# reserved
 }
 # -----------------  Port 1  ADR 1  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1
 scom 0x800144200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 1  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba01));	# 0, B0_CKE2
+	48:49	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba01));
+	48:49	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba01));
+	48:49	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba01));
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 1, B_A7
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 2, B_A10
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 3, B1_CKE1
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 4, B0_CS1n
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 5, B_A8
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 6, B_A6
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 7, B1_CS3n
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 1  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 0, D_A8
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 1, D_A13
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 2, D0_ODT1
+	52:53	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 3, D_PAR
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 4, D1_CS0n
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 5, D_A11
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 6, D0_CKE1
+	60:61	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	60:61	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	60:61	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	62:63	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 7, D_WEn
+	62:63	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1
 scom 0x800144210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL11
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 1  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 8, B_A4
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 9, B1_CS1n
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 10, B_A1
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 11, B_BA1
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 1  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba23));	# 8, D0_CKE3
+	48:49	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba23));
+	48:49	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba23));
+	48:49	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba23));
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 9, D1_ODT0
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 10, D_RASn
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 11, D0_CS1n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+#	56:63	,	0x00		,	any					;	# reserved
 }
 # -----------------  Port 1  ADR 2  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2
 scom 0x800148200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL2
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL2
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL2
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL2
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL3
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL3
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL3
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL3
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 2  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 0, B0_CS2n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 1, B0_ODT0
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 2, B_WEn
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 3, B_A2
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 4, B0_ODT1
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 5, B0_CS0n
+	58:59	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 6, B_A3
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	62:63	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 7, B_A0
+	62:63	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 2  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 0, D0_CS0n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 1, D_A10
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 2, D_A4
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 3, D1_CS3n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 4, D_ACTn
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 5, D_A9
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba23));	# 6, D1_CKE3
+	60:61	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba23));
+	60:61	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba23));
+	60:61	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba23));
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 7, D1_CKE0
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2
 scom 0x800148210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL8 clk
-	48:49	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL8 clk
-	48:49	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL8 clk
-	48:49	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL8 clk
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL9 clk
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL9 clk
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL9 clk
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL9 clk
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL11
-	56:57	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL12
-	56:57	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL12
-	56:57	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL12
-	56:57	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL12
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL13
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL13
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL13
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL13
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 2  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 8, B0_CLK1_p
+	48:49	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 9, B0_CLK1_n
+	50:51	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 10, B_CASn
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 11, B1_CS0n
+	54:55	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 12, B1_CKE0
+	56:57	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 13, B_A12
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 2  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 8, D0_CS3n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 9, D_A2
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 10, D1_CLK1_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 11, D1_CLK1_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 12, D0_CLK1_n
+	56:57	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 13, D0_CLK1_p
+	58:59	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+#	60:63	,	0b0000		,	any					;	# reserved
 }
 # -----------------  Port 1  ADR 3  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3
 scom 0x80014c200301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL0
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL0
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL0
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL0
-	50:51	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL1
-	50:51	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL1
-	50:51	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL1
-	50:51	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL1
-	52:53	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL2 clk
-	52:53	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL2 clk
-	52:53	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL2 clk
-	52:53	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL2 clk
-	54:55	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL3 clk
-	54:55	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL3 clk
-	54:55	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL3 clk
-	54:55	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL3 clk
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL4
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL4
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL4
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL4
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL5
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL5
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL5
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL5
-	60:61	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL6
-	60:61	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL6
-	60:61	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL6
-	60:61	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL6
-	62:63	,	0b00		,	(def_cdi_ctl_ohm15)	;	# SEL7
-	62:63	,	0b01		,	(def_cdi_ctl_ohm20)	;	# SEL7
-	62:63	,	0b10		,	(def_cdi_ctl_ohm30)	;	# SEL7
-	62:63	,	0b11		,	(def_cdi_ctl_ohm40)	;	# SEL7
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 3  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 0, B_A11
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 1, B0_CKE0
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 2, B0_CLK0_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba01))	;	# 3, B0_CLK0_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 4, B_A13
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 5, B_A14
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	60:61	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba01));	# 6, B1_CKE2
+	60:61	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba01));
+	60:61	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba01));
+	60:61	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba01));
+	62:63	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba01))	;	# 7, B1_ODT0
+	62:63	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba01))	;
+	62:63	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba01))	;
+	62:63	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 3  lanes 0:7 ---------------------------------------------
+	48:49	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 0, D1_CS2n
+	48:49	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 1, D0_ODT0
+	50:51	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 2, D0_CLK0_n
+	52:53	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_clk_ohm15_p1) && (def_is_mba23))	;	# 3, D0_CLK0_p
+	54:55	,	0b01		,	((def_cdi_clk_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_clk_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_clk_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 4, D_A6
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_ctl_ohm15_p1) && (def_is_mba23))	;	# 5, D1_ODT1
+	58:59	,	0b01		,	((def_cdi_ctl_ohm20_p1) && (def_is_mba23))	;
+	58:59	,	0b10		,	((def_cdi_ctl_ohm30_p1) && (def_is_mba23))	;
+	58:59	,	0b11		,	((def_cdi_ctl_ohm40_p1) && (def_is_mba23))	;
+	60:61	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 6, D_A0
+	60:61	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	60:61	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	60:61	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	62:63	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 7, D_CASn
+	62:63	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	62:63	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	62:63	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
 }
 # DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3
 scom 0x80014c210301143f {
 	bits	,	scom_data	,	expr				;
-	48:49	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL8
-	48:49	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL8
-	48:49	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL8
-	48:49	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL8
-	50:51	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL9
-	50:51	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL9
-	50:51	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL9
-	50:51	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL9
-	52:53	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL10
-	52:53	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL10
-	52:53	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL10
-	52:53	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL10
-	54:55	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL11
-	54:55	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL11
-	54:55	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL11
-	54:55	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL11
-	56:57	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL12
-	56:57	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL12
-	56:57	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL12
-	56:57	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL12
-	58:59	,	0b00		,	(def_cdi_cmd_ohm15)	;	# SEL13
-	58:59	,	0b01		,	(def_cdi_cmd_ohm20)	;	# SEL13
-	58:59	,	0b10		,	(def_cdi_cmd_ohm30)	;	# SEL13
-	58:59	,	0b11		,	(def_cdi_cmd_ohm40)	;	# SEL13
+#	0:47	,	0x000000000000,	any					;	# reserved
+#  ------ PORT 1  ADR 3  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 8, B_A9
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 9, B_BA2
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 10, B_RASn
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 11, B_ACTn
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 12, B_A5
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+	58:59	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba01))	;	# 13, B_PAR
+	58:59	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba01))	;
+	58:59	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba01))	;
+	58:59	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba01))	;
+#  ------ PORT 3  ADR 3  lanes 8:11 --------------------------------------------
+	48:49	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 8, D_A14
+	48:49	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	48:49	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	48:49	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	50:51	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 9, D_A3
+	50:51	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	50:51	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	50:51	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	52:53	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 10, D_A7
+	52:53	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	52:53	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	52:53	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	54:55	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 11, D_A15
+	54:55	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	54:55	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	54:55	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	56:57	,	0b00		,	((def_cdi_addr_ohm15_p1) && (def_is_mba23))	;	# 12, D_BA1
+	56:57	,	0b01		,	((def_cdi_addr_ohm20_p1) && (def_is_mba23))	;
+	56:57	,	0b10		,	((def_cdi_addr_ohm30_p1) && (def_is_mba23))	;
+	56:57	,	0b11		,	((def_cdi_addr_ohm40_p1) && (def_is_mba23))	;
+	58:59	,	0b00		,	((def_cdi_spcke_ohm15_p1) && (def_is_mba23));	# 13, D0_CKE2
+	58:59	,	0b01		,	((def_cdi_spcke_ohm20_p1) && (def_is_mba23));
+	58:59	,	0b10		,	((def_cdi_spcke_ohm30_p1) && (def_is_mba23));
+	58:59	,	0b11		,	((def_cdi_spcke_ohm40_p1) && (def_is_mba23));
+#	60:63	,	0b0000		,	any					;	# reserved
 }
 
 #**********************************************************************************
 # ADR Slew Calibration control		default=0
-#
-# Controls the circuit that performs the ADR slew calibration.
-#
-# 	[01:23]						 [0:1]   [0:1]
 # DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0	0x039	0x800080390301143f
-# Controls the circuit that performs the ADR slew calibration.
 #
-scom 0x800080390301143f {
-	bits	,	scom_data	;
-	48		,	0b0			;	# enable
-	49		,	0b1			;	# start
-#	50		,	0b0			;	# reserved
-	51		,	0b1			;	# override enable
-	52:55	,	0b0100		;	# override vector
-#	56:58	,	0b010		;	# reserved
-	59:63	,	0b10111		;	# slew target phase rotator offset
-}
-#
-# 	!! looks like 4,5,6V/ns for 1.35V and 4,5V/ns at 1.2V, need to add this to the
-# 	ddr_reset_phy procedure.  Waiting on details from analog PHY team for settings.
-#
-#**********************************************************************************
-
-# ---------------------------------------------------------------------------------------
-# Configure slew rate mux(CTL) registers(4)
-# CTL0 = CMD, CTL1 = CNTL, CTL2 = unused, CTL3 = unused
-#
-#	 ATTR_EFF_CEN_SLEW_RATE_CMD		0=slow, 15=fast		use in CTL0
-#	 ATTR_EFF_CEN_SLEW_RATE_CNTL	0=slow, 15=fast		use in CTL1
-#
-#  choices... 0=3.61, 1=4.33, 2=5.41, 3=6.69, 4=8.11, 5=8.58 V/ns
-#				 6..F is approximately 180mV/step, F=10.56 V/ns
+# ---------------------------------------------------------------------------------
+# Configure slew rate mux(CTL) registers(4)		slew mapping/slew mux
+# set in ddrphy_reset procedure via FN call
+# CTL0 = CMD, CTL1 = CNTL, CTL2 = CLK, CTL3 = SPCKE
 #
-#  [01:23]								  [0:1][0:3]
+#  [01:23]							 [0:1][0:3]
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0	0x01A	0x8000401a0301143f
 #scom 0x8000(40,44,48,4c)1A0301143f {	# VALUE_P0_ADR[0:3]
-scom 0x800(0,1)7C1A0301143f {			# VALUE_P[0:1]_ADR[0:3] broadcast
-	bits	,	scom_data	,	expr								;
-	# SLEW_CTL0, used for command
-	48:51	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 0)	;	# slow
-	48:51	,	0b0001		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 1)	;	# faster .
-	48:51	,	0b0010		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 2)	;	# faster ..
-	48:51	,	0b0011		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 3)	;	# faster ...
-	48:51	,	0b0100		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 4)	;	# faster ....
-	48:51	,	0b0101		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 5)	;	# faster .....
-	48:51	,	0b0110		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 6)	;	# faster ......
-	48:51	,	0b0111		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 7)	;	# faster .......
-	48:51	,	0b1000		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 8)	;	# faster ........
-	48:51	,	0b1001		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 9)	;	# faster .........
-	48:51	,	0b1010		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 10)	;	# faster ..........
-	48:51	,	0b1011		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 11)	;	# faster ...........
-	48:51	,	0b1100		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 12)	;	# faster ............
-	48:51	,	0b1101		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 13)	;	# faster .............
-	48:51	,	0b1110		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 14)	;	# faster ..............
-	48:51	,	0b1111		,	(ATTR_EFF_CEN_SLEW_RATE_CMD == 15)	;	# fastest...............
-	# SLEW_CTL1, used for control
-	52:55	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 0)	;	# slow
-	52:55	,	0b0001		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 1)	;	# faster .
-	52:55	,	0b0010		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 2)	;	# faster ..
-	52:55	,	0b0011		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 3)	;	# faster ...
-	52:55	,	0b0100		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 4)	;	# faster ....
-	52:55	,	0b0101		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 5)	;	# faster .....
-	52:55	,	0b0110		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 6)	;	# faster ......
-	52:55	,	0b0111		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 7)	;	# faster .......
-	52:55	,	0b1000		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 8)	;	# faster ........
-	52:55	,	0b1001		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 9)	;	# faster .........
-	52:55	,	0b1010		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 10)	;	# faster ..........
-	52:55	,	0b1011		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 11)	;	# faster ...........
-	52:55	,	0b1100		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 12)	;	# faster ............
-	52:55	,	0b1101		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 13)	;	# faster .............
-	52:55	,	0b1110		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 14)	;	# faster ..............
-	52:55	,	0b1111		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL == 15)	;	# fastest...............
-	# SLEW_CTL2	3.61 V/ns, not used currently
-	56:59	,	0b0000		,	any									;	# slow
-	# SLEW_CTL3	3.61 V/ns, not used currently
-	60:63	,	0b0000		,	any									;	# slow
-}
+#scom 0x800(0,1)7C1A0301143f {			# VALUE_P[0:1]_ADR[0:3] broadcast
+#	bits	,	scom_data	,	expr								;
+#	0:47	,	0x000000000000,	any									;	# reserved
+	# SLEW_CTL0, used for command (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE)
+#	48:51	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_ADDR[0])	;
+	# SLEW_CTL1, used for control (CKE0:1, CKE4:5, ODT, CSN0:7)
+#	52:55	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_CNTL[0])	;
+	# SLEW_CTL2,	used for clocks (CLK0:3)
+#	56:59	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_CLK[0])		;
+	# SLEW_CTL3, used for spare drams (CKE2:3, CKE6:7)
+#	60:63	,	0b0000		,	(ATTR_EFF_CEN_SLEW_RATE_SPCKE[0)	;
+#}
+#**********************************************************************************
 
-# ---------------------------------------------------------------------------------------
+# ---------------------------------------------------------------------------------
 # Set slew rate to select CMD(CTL0) or CNTL(CTL1)
 #
 # MAP0 = SLEW_CTL_SEL{0:7}	MAP1 = SLEW_CTL_SEL{8:15}
@@ -1288,23 +1902,30 @@ scom 0x800(0,1)7C1A0301143f {			# VALUE_P[0:1]_ADR[0:3] broadcast
 # -----------------  Port 0  ADR 0  -----------------------------------------------
 scom 0x8000402a0301143f {		# MAP0_P0_ADR0
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL0
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL2
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
-	# -----------------  Port 2  ADR 0  Map 0  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL0
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL1
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL2
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL3
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6 clk
-	62:63	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL7 clk
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 0  lanes 0:7 ---------------------------------------------
+# A1_CKE1, A0_CS3n, A1_CKE0, A0_ODT0, A_A15, A_PAR, A0_CKE1, A0_CS1n
+#	48:63	,	0x5505		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 0  lanes 0:7 ---------------------------------------------
+# C0_CS0n, C_A3, C1_CS3n, C_RASn, C_A12, C_A7, C0_CLK1_p, C0_CLK1_n
+#	48:63	,	0x440A		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 0 CNTL	, A1_CKE1
+	50:51	,	0b01		,	(def_is_mba01)	;	# 1 CNTL	, A0_CS3n
+	52:53	,	0b01		,	(def_is_mba01)	;	# 2 CNTL	, A1_CKE0
+	54:55	,	0b01		,	(def_is_mba01)	;	# 3 CNTL	, A0_ODT0
+	56:57	,	0b00		,	(def_is_mba01)	;	# 4 ADDR	, A_A15
+	58:59	,	0b00		,	(def_is_mba01)	;	# 5 ADDR	, A_PAR
+	60:61	,	0b01		,	(def_is_mba01)	;	# 6 CNTL	, A0_CKE1
+	62:63	,	0b01		,	(def_is_mba01)	;	# 7 CNTL	, A0_CS1n
+	# -----------------  Port 2  ADR 0  Map 0  ----------------------
+	48:49	,	0b01		,	(def_is_mba23)	;	# 0 CNTL	, C0_CS0n
+	50:51	,	0b00		,	(def_is_mba23)	;	# 1 ADDR	, C_A3
+	52:53	,	0b01		,	(def_is_mba23)	;	# 2 CNTL	, C1_CS3n
+	54:55	,	0b00		,	(def_is_mba23)	;	# 3 ADDR	, C_RASn
+	56:57	,	0b00		,	(def_is_mba23)	;	# 4 ADDR	, C_A12
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, C_A7
+	60:61	,	0b10		,	(def_is_mba23)	;	# 6 CLK		, C0_CLK1_p
+	62:63	,	0b10		,	(def_is_mba23)	;	# 7 CLK		, C0_CLK1_n
 }
 # ADR I/O FET Slice Enable Map 1
 # Register 1 containing lanes 8:15
@@ -1312,128 +1933,181 @@ scom 0x8000402a0301143f {		# MAP0_P0_ADR0
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0	0x02b	0x8000402b0301143f
 scom 0x8000402b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL8
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL9
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL10 clk
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL11 clk
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 0  lanes 8:11 --------------------------------------------
+# A0_CKE0, A1_ODT0, A0_CLK0_p, A0_CLK0_n
+#	48:55	,	0x5A		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 0  lanes 8:11 --------------------------------------------
+# C1_CLK1_p, C1_CLK1_n, C1_CKE2, C0_CKE2
+#	48:55	,	0xAF		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 8 CNTL	, A0_CKE0
+	50:51	,	0b01		,	(def_is_mba01)	;	# 9 CNTL	, A1_ODT0
+	52:53	,	0b10		,	(def_is_mba01)	;	#10 CLK		, A0_CLK0_p
+	54:55	,	0b10		,	(def_is_mba01)	;	#11 CLK		, A0_CLK0_n
 	# -----------------  Port 2  ADR 0  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8 clk
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL9 clk
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL10
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11
+	48:49	,	0b10		,	(def_is_mba23)	;	# 8 CLK		, C1_CLK1_p
+	50:51	,	0b10		,	(def_is_mba23)	;	# 9 CLK		, C1_CLK1_n
+	52:53	,	0b11		,	(def_is_mba23)	;	#10 SPCKE	, C1_CKE2
+	54:55	,	0b11		,	(def_is_mba23)	;	#11 SPCKE	, C0_CKE2
+#	56:63	,	0b00000000	,	any				;	# reserved
 }
 # -----------------  Port 0  ADR 1  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1
 scom 0x8000442a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL0
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL2
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL3
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL5
-	60:61	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 1  lanes 0:7 ---------------------------------------------
+# A0_CS0n, A1_CKE3, A1_ODT1, A_A2, A_A6, A_A1, A_A14, A0_CKE2
+#	48:63	,	0x7403		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 1  lanes 0:7 ---------------------------------------------
+# C_BA2, C1_CKE1, C0_ODT1, C_WEn, C0_CS1n, C_A11, C0_CKE3, C0_CS2n
+#	48:63	,	0x144D		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 0 CNTL	, A0_CS0n
+	50:51	,	0b11		,	(def_is_mba01)	;	# 1 SPCKE	, A1_CKE3
+	52:53	,	0b01		,	(def_is_mba01)	;	# 2 CNTL	, A1_ODT1
+	54:55	,	0b00		,	(def_is_mba01)	;	# 3 ADDR	, A_A2
+	56:57	,	0b00		,	(def_is_mba01)	;	# 4 ADDR	, A_A6
+	58:59	,	0b00		,	(def_is_mba01)	;	# 5 ADDR	, A_A1
+	60:61	,	0b00		,	(def_is_mba01)	;	# 6 ADDR	, A_A14
+	62:63	,	0b11		,	(def_is_mba01)	;	# 7 SPCKE	, A0_CKE2
 	# -----------------  Port 2  ADR 1  Map 0  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL0
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL2
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL3
-	56:57	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL7
+	48:49	,	0b00		,	(def_is_mba23)	;	# 0 ADDR	, C_BA2
+	50:51	,	0b01		,	(def_is_mba23)	;	# 1 CNTL	, C1_CKE1
+	52:53	,	0b01		,	(def_is_mba23)	;	# 2 CNTL	, C0_ODT1
+	54:55	,	0b00		,	(def_is_mba23)	;	# 3 ADDR	, C_WEn
+	56:57	,	0b01		,	(def_is_mba23)	;	# 4 CNTL	, C0_CS1n
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, C_A11
+	60:61	,	0b11		,	(def_is_mba23)	;	# 6 SPCKE	, C0_CKE3
+	62:63	,	0b01		,	(def_is_mba23)	;	# 7 CNTL	, C0_CS2n
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1
 scom 0x8000442b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL8
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL9
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL11
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 1  lanes 8:11 --------------------------------------------
+# A1_CS2n, A1_CKE2, A_A4, A_RASn
+#	48:55	,	0x70		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 1  lanes 8:11 --------------------------------------------
+# C0_ODT0, C_A8, C_A5, C1_CS0n
+#	48:55	,	0x41		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 8 CNTL	, A1_CS2n
+	50:51	,	0b11		,	(def_is_mba01)	;	# 9 SPCKE	, A1_CKE2
+	52:53	,	0b00		,	(def_is_mba01)	;	#10 ADDR	, A_A4
+	54:55	,	0b00		,	(def_is_mba01)	;	#11 ADDR	, A_RASn
 	# -----------------  Port 2  ADR 1  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL9
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL10
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11
+	48:49	,	0b01		,	(def_is_mba23)	;	# 8 CNTL	, C0_ODT0
+	50:51	,	0b00		,	(def_is_mba23)	;	# 9 ADDR	, C_A8
+	52:53	,	0b00		,	(def_is_mba23)	;	#10 ADDR	, C_A5
+	54:55	,	0b01		,	(def_is_mba23)	;	#11 CNTL	, C1_CS0n
+#	56:63	,	0b00000000	,	any				;	# reserved
 }
 # -----------------  Port 0  ADR 2  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2
 scom 0x8000482a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL0
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL1
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL2
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL4 clk
-	58:59	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL5 clk
-	60:61	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 2  lanes 0:7 ---------------------------------------------
+# A_A12, A_A0, A0_CKE3, A1_CS3n, A1_CLK0_p, A1_CLK0_n, A0_ODT1, A1_CS0n
+#	48:63	,	0x0DA5		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 2  lanes 0:7 ---------------------------------------------
+# C_A1, C_A6, C_A13, C0_CKE0, C1_ODT0, C1_CS1n, C0_CKE1, C1_CKE0
+#	48:63	,	0x0155		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 0 ADDR	, A_A12
+	50:51	,	0b00		,	(def_is_mba01)	;	# 1 ADDR	, A_A0
+	52:53	,	0b11		,	(def_is_mba01)	;	# 2 SPCKE	, A0_CKE3
+	54:55	,	0b01		,	(def_is_mba01)	;	# 3 CNTL	, A1_CS3n
+	56:57	,	0b10		,	(def_is_mba01)	;	# 4 CLK		, A1_CLK0_p
+	58:59	,	0b10		,	(def_is_mba01)	;	# 5 CLK		, A1_CLK0_n
+	60:61	,	0b01		,	(def_is_mba01)	;	# 6 CNTL	, A0_ODT1
+	62:63	,	0b01		,	(def_is_mba01)	;	# 7 CNTL	, A1_CS0n
 	# -----------------  Port 2  ADR 2  Map 0  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL0
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL1
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL2
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL3
-	56:57	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL4
-	58:59	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL7
+	48:49	,	0b00		,	(def_is_mba23)	;	# 0 ADDR	, C_A1
+	50:51	,	0b00		,	(def_is_mba23)	;	# 1 ADDR	, C_A6
+	52:53	,	0b00		,	(def_is_mba23)	;	# 2 ADDR	, C_A13
+	54:55	,	0b01		,	(def_is_mba23)	;	# 3 CNTL	, C0_CKE0
+	56:57	,	0b01		,	(def_is_mba23)	;	# 4 CNTL	, C1_ODT0
+	58:59	,	0b01		,	(def_is_mba23)	;	# 5 CNTL	, C1_CS1n
+	60:61	,	0b01		,	(def_is_mba23)	;	# 6 CNTL	, C0_CKE1
+	62:63	,	0b01		,	(def_is_mba23)	;	# 7 CNTL	, C1_CKE0
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2
 scom 0x8000482b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL8
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL9
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL10 clk
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL11 clk
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL12 clk
-	58:59	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL13 clk
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 2  lanes 8:13 --------------------------------------------
+# A1_CS1n, A_A10, A0_CLK1_n, A0_CLK1_p, A1_CLK1_n, A1_CLK1_p
+#	48:59	,	0x4AA		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 2  lanes 8:13 --------------------------------------------
+# C_A0, C_BA1, C0_CLK0_n, C0_CLK0_p, C1_CS2n, C_A10
+#	48:59	,	0x0A4		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 8 CNTL	, A1_CS1n
+	50:51	,	0b00		,	(def_is_mba01)	;	# 9 ADDR	, A_A10
+	52:53	,	0b10		,	(def_is_mba01)	;	#10 CLK		, A0_CLK1_n
+	54:55	,	0b10		,	(def_is_mba01)	;	#11 CLK		, A0_CLK1_p
+	56:57	,	0b10		,	(def_is_mba01)	;	#12 CLK		, A1_CLK1_n
+	58:59	,	0b10		,	(def_is_mba01)	;	#13 CLK		, A1_CLK1_p
 	# -----------------  Port 2  ADR 2  Map 1  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL8
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL9
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL10 clk
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11 clk
-	56:57	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL12
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL13
+	48:49	,	0b00		,	(def_is_mba23)	;	# 8 ADDR	, C_A0
+	50:51	,	0b00		,	(def_is_mba23)	;	# 9 ADDR	, C_BA1
+	52:53	,	0b10		,	(def_is_mba23)	;	#10 CLK		, C0_CLK0_n
+	54:55	,	0b10		,	(def_is_mba23)	;	#11 CLK		, C0_CLK0_p
+	56:57	,	0b01		,	(def_is_mba23)	;	#12 CNTL	, C1_CS2n
+	58:59	,	0b00		,	(def_is_mba23)	;	#13 ADDR	, C_A10
+#	60:63	,	0b0000		,	any				;	# reserved
 }
 # -----------------  Port 0  ADR 3  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3
 scom 0x80004c2a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL0
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL1
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL2
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL5
-	60:61	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL6
-	62:63	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 3  lanes 0:7 ---------------------------------------------
+# A_A13, A_BA0, A_WEn, A0_CS2n, A_BA1, A_CASn, A_A5, A_A3
+#	48:63	,	0x0100		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 3  lanes 0:7 ---------------------------------------------
+# C_PAR, C1_ODT1, C1_CLK0_p, C1_CLK0_n, C_A14, C_A9, C_ACTn, C_A2
+#	48:63	,	0x1A00		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 0 ADDR	, A_A13
+	50:51	,	0b00		,	(def_is_mba01)	;	# 1 ADDR	, A_BA0
+	52:53	,	0b00		,	(def_is_mba01)	;	# 2 ADDR	, A_WEn
+	54:55	,	0b01		,	(def_is_mba01)	;	# 3 CNTL	, A0_CS2n
+	56:57	,	0b00		,	(def_is_mba01)	;	# 4 ADDR	, A_BA1
+	58:59	,	0b00		,	(def_is_mba01)	;	# 5 ADDR	, A_CASn
+	60:61	,	0b00		,	(def_is_mba01)	;	# 6 ADDR	, A_A5
+	62:63	,	0b00		,	(def_is_mba01)	;	# 7 ADDR	, A_A3
 	# -----------------  Port 2  ADR 3  Map 0  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL0
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL2 clk
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL3 clk
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL6
-	62:63	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL7
+	48:49	,	0b00		,	(def_is_mba23)	;	# 0 ADDR	, C_PAR
+	50:51	,	0b01		,	(def_is_mba23)	;	# 1 CNTL	, C1_ODT1
+	52:53	,	0b10		,	(def_is_mba23)	;	# 2 CLK		, C1_CLK0_p
+	54:55	,	0b10		,	(def_is_mba23)	;	# 3 CLK		, C1_CLK0_n
+	56:57	,	0b00		,	(def_is_mba23)	;	# 4 ADDR	, C_A14
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, C_A9
+	60:61	,	0b00		,	(def_is_mba23)	;	# 6 ADDR	, C_ACTn
+	62:63	,	0b00		,	(def_is_mba23)	;	# 7 ADDR	, C_A2
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3
 scom 0x80004c2b0301143f {
-	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL8
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL9
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL11
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL12
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL13
+	bits	,	scom_data	,	expr			;					# signal
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 0  ADR 3  lanes 8:13 --------------------------------------------
+# A_BA2, A_A11, A_A7, A_ACTn, A_A9, A_A8
+#	48:59	,	0x000		,	(def_is_mba01)	;
+#  ------ PORT 2  ADR 3  lanes 8:13 --------------------------------------------
+# C1_CKE3, C_A15, C_BA0, C_CASn, C_A4, C0_CS3n
+#	48:59	,	0xC01		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 8 ADDR	, A_BA2
+	50:51	,	0b00		,	(def_is_mba01)	;	# 9 ADDR	, A_A11
+	52:53	,	0b00		,	(def_is_mba01)	;	#10 ADDR	, A_A7
+	54:55	,	0b00		,	(def_is_mba01)	;	#11 ADDR	, A_ACTn
+	56:57	,	0b00		,	(def_is_mba01)	;	#12 ADDR	, A_A9
+	58:59	,	0b00		,	(def_is_mba01)	;	#13 ADDR	, A_A8
 	# -----------------  Port 2  ADR 3  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL9
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL11
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL12
-	58:59	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL13
+	48:49	,	0b11		,	(def_is_mba23)	;	# 8 SPCKE	, C1_CKE3
+	50:51	,	0b00		,	(def_is_mba23)	;	# 9 ADDR	, C_A15
+	52:53	,	0b00		,	(def_is_mba23)	;	#10 ADDR	, C_BA0
+	54:55	,	0b00		,	(def_is_mba23)	;	#11 ADDR	, C_CASn
+	56:57	,	0b00		,	(def_is_mba23)	;	#12 ADDR	, C_A4
+	58:59	,	0b01		,	(def_is_mba23)	;	#13 CNTL	, C0_CS3n
+#	60:63	,	0b0000		,	any				;	# reserved
 }
 # =================================================================================
 # -----------------  Port 1  ADR 0  -----------------------------------------------
@@ -1441,179 +2115,220 @@ scom 0x80004c2b0301143f {
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0
 scom 0x8001402a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL0 clk
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL1 clk
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL2 clk
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3 clk
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL4
-	58:59	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL5
-	60:61	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 0  lanes 0:7 ---------------------------------------------
+# B1_CLK0_n, B1_CLK0_p, B1_CLK1_n, B1_CLK1_p, B0_CKE3, B0_CS3n, B_BA0, B1_ODT1
+#	48:63	,	0xAAD1		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 0  lanes 0:7 ---------------------------------------------
+# D1_CKE1, D_BA2, D_A1, D_A5, D_A12, D_BA0, D1_CKE2, D1_CS1n
+#	48:63	,	0x400D		,	(def_is_mba23)	;
+	48:49	,	0b10		,	(def_is_mba01)	;	# 0 CLK		, B1_CLK0_n
+	50:51	,	0b10		,	(def_is_mba01)	;	# 1 CLK		, B1_CLK0_p
+	52:53	,	0b10		,	(def_is_mba01)	;	# 2 CLK		, B1_CLK1_n
+	54:55	,	0b10		,	(def_is_mba01)	;	# 3 CLK		, B1_CLK1_p
+	56:57	,	0b11		,	(def_is_mba01)	;	# 4 SPCKE	, B0_CKE3
+	58:59	,	0b01		,	(def_is_mba01)	;	# 5 CNTL	, B0_CS3n
+	60:61	,	0b00		,	(def_is_mba01)	;	# 6 ADDR	, B_BA0
+	62:63	,	0b01		,	(def_is_mba01)	;	# 7 CNTL	, B1_ODT1
 	# -----------------  Port 3  ADR 0  Map 0  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL0
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL1
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL2
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL3
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL7
+	48:49	,	0b01		,	(def_is_mba23)	;	# 0 CNTL	, D1_CKE1
+	50:51	,	0b00		,	(def_is_mba23)	;	# 1 ADDR	, D_BA2
+	52:53	,	0b00		,	(def_is_mba23)	;	# 2 ADDR	, D_A1
+	54:55	,	0b00		,	(def_is_mba23)	;	# 3 ADDR	, D_A5
+	56:57	,	0b00		,	(def_is_mba23)	;	# 4 ADDR	, D_A12
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, D_BA0
+	60:61	,	0b11		,	(def_is_mba23)	;	# 6 SPCKE	, D1_CKE2
+	62:63	,	0b01		,	(def_is_mba23)	;	# 7 CNTL	, D1_CS1n
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0
 scom 0x8001402b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL8
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL9
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL10
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL11
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 0  lanes 8:11 --------------------------------------------
+# B1_CKE3, B_A15, B1_CS2n, B0_CKE1
+#	48:55	,	0xC5		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 0  lanes 8:11 --------------------------------------------
+# D0_CKE0, D0_CS2n, D1_CLK0_p, D1_CLK0_n
+#	48:55	,	0x5A		,	(def_is_mba23)	;
+	48:49	,	0b11		,	(def_is_mba01)	;	# 8 SPCKE	, B1_CKE3
+	50:51	,	0b00		,	(def_is_mba01)	;	# 9 ADDR	, B_A15
+	52:53	,	0b01		,	(def_is_mba01)	;	#10 CNTL	, B1_CS2n
+	54:55	,	0b01		,	(def_is_mba01)	;	#11 CNTL	, B0_CKE1
 	# -----------------  Port 3  ADR 0  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL9
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL10 clk
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11 clk
+	48:49	,	0b01		,	(def_is_mba23)	;	# 8 CNTL	, D0_CKE0
+	50:51	,	0b01		,	(def_is_mba23)	;	# 9 CNTL	, D0_CS2n
+	52:53	,	0b10		,	(def_is_mba23)	;	#10 CLK		, D1_CLK0_p
+	54:55	,	0b10		,	(def_is_mba23)	;	#11 CLK		, D1_CLK0_n
+#	56:63	,	0b00000000	,	any				;	# reserved
 }
 # -----------------  Port 1  ADR 1  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1
 scom 0x8001442a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL0
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL1
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL2
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL4
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL5
-	60:61	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 1  lanes 0:7 ---------------------------------------------
+# B0_CKE2, B_A7, B_A10, B1_CKE1, B0_CS1n, B_A8, B_A6, B1_CS3n
+#	48:63	,	0xC141		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 1  lanes 0:7 ---------------------------------------------
+# D_A8, D_A13, D0_ODT1, D_PAR, D1_CS0n, D_A11, D0_CKE1, D_WEn
+#	48:63	,	0x0444		,	(def_is_mba23)	;
+	48:49	,	0b11		,	(def_is_mba01)	;	# 0 SPCKE	, B0_CKE2
+	50:51	,	0b00		,	(def_is_mba01)	;	# 1 ADDR	, B_A7
+	52:53	,	0b00		,	(def_is_mba01)	;	# 2 ADDR	, B_A10
+	54:55	,	0b01		,	(def_is_mba01)	;	# 3 CNTL	, B1_CKE1
+	56:57	,	0b01		,	(def_is_mba01)	;	# 4 CNTL	, B0_CS1n
+	58:59	,	0b00		,	(def_is_mba01)	;	# 5 ADDR	, B_A8
+	60:61	,	0b00		,	(def_is_mba01)	;	# 6 ADDR	, B_A6
+	62:63	,	0b01		,	(def_is_mba01)	;	# 7 CNTL	, B1_CS3n
 	# -----------------  Port 3  ADR 1  Map 0  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL0
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL1
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL2
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL3
-	56:57	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6
-	62:63	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL7
+	48:49	,	0b00		,	(def_is_mba23)	;	# 0 ADDR	, D_A8
+	50:51	,	0b00		,	(def_is_mba23)	;	# 1 ADDR	, D_A13
+	52:53	,	0b01		,	(def_is_mba23)	;	# 2 CNTL	, D0_ODT1
+	54:55	,	0b00		,	(def_is_mba23)	;	# 3 ADDR	, D_PAR
+	56:57	,	0b01		,	(def_is_mba23)	;	# 4 CNTL	, D1_CS0n
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, D_A11
+	60:61	,	0b01		,	(def_is_mba23)	;	# 6 CNTL	, D0_CKE1
+	62:63	,	0b00		,	(def_is_mba23)	;	# 7 ADDR	, D_WEn
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1
 scom 0x8001442b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL8
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL9
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL11
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 1  lanes 8:11 --------------------------------------------
+# B_A4, B1_CS1n, B_A1, B_BA1
+#	48:55	,	0x10		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 1  lanes 8:11 --------------------------------------------
+# D0_CKE3, D1_ODT0, D_RASn, D0_CS1n
+#	48:55	,	0xD1		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 8 ADDR	, B_A4
+	50:51	,	0b01		,	(def_is_mba01)	;	# 9 CNTL	, B1_CS1n
+	52:53	,	0b00		,	(def_is_mba01)	;	#10 ADDR	, B_A1
+	54:55	,	0b00		,	(def_is_mba01)	;	#11 ADDR	, B_BA1
 	# -----------------  Port 3  ADR 1  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL9
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL10
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11
+	48:49	,	0b11		,	(def_is_mba23)	;	# 8 CNTL	, D0_CKE3
+	50:51	,	0b01		,	(def_is_mba23)	;	# 9 CNTL	, D1_ODT0
+	52:53	,	0b00		,	(def_is_mba23)	;	#10 ADDR	, D_RASn
+	54:55	,	0b01		,	(def_is_mba23)	;	#11 CNTL	, D0_CS1n
+#	56:63	,	0b00000000	,	any				;	# reserved
 }
 # -----------------  Port 1  ADR 2  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2
 scom 0x8001482a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL0
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL1
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL2
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL3
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL4
-	58:59	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL5
-	60:61	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL6
-	62:63	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 2  lanes 0:7 ---------------------------------------------
+# B0_CS2n, B0_ODT0, B_WEn, B_A2, B0_ODT1, B0_CS0n, B_A3, B_A0
+#	48:63	,	0x5050		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 2  lanes 0:7 ---------------------------------------------
+# D0_CS0n, D_A10, D_A4, D1_CS3n, D_ACTn, D_A9, D1_CKE3, D1_CKE0
+#	48:63	,	0x410D		,	(def_is_mba23)	;
+	48:49	,	0b01		,	(def_is_mba01)	;	# 0 CNTL	, B0_CS2n
+	50:51	,	0b01		,	(def_is_mba01)	;	# 1 CNTL	, B0_ODT0
+	52:53	,	0b00		,	(def_is_mba01)	;	# 2 ADDR	, B_WEn
+	54:55	,	0b00		,	(def_is_mba01)	;	# 3 ADDR	, B_A2
+	56:57	,	0b01		,	(def_is_mba01)	;	# 4 CNTL	, B0_ODT1
+	58:59	,	0b01		,	(def_is_mba01)	;	# 5 CNTL	, B0_CS0n
+	60:61	,	0b00		,	(def_is_mba01)	;	# 6 ADDR	, B_A3
+	62:63	,	0b00		,	(def_is_mba01)	;	# 7 ADDR	, B_A0
 	# -----------------  Port 3  ADR 2  Map 0  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL0
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL1
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL2
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL3
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL7
+	48:49	,	0b01		,	(def_is_mba23)	;	# 0 CNTL	, D0_CS0n
+	50:51	,	0b00		,	(def_is_mba23)	;	# 1 ADDR	, D_A10
+	52:53	,	0b00		,	(def_is_mba23)	;	# 2 ADDR	, D_A4
+	54:55	,	0b01		,	(def_is_mba23)	;	# 3 CNTL	, D1_CS3n
+	56:57	,	0b00		,	(def_is_mba23)	;	# 4 ADDR	, D_ACTn
+	58:59	,	0b00		,	(def_is_mba23)	;	# 5 ADDR	, D_A9
+	60:61	,	0b11		,	(def_is_mba23)	;	# 6 SPCKE	, D1_CKE3
+	62:63	,	0b01		,	(def_is_mba23)	;	# 7 CNTL	, D1_CKE0
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2
 scom 0x8001482b0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL8 clk
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL9 clk
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL10
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL11
-	56:57	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL12
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL13
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 2  lanes 8:11 --------------------------------------------
+# B0_CLK1_p, B0_CLK1_n, B_CASn, B1_CS0n, B1_CKE0, B_A12
+#	48:59	,	0xA14		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 2  lanes 8:11 --------------------------------------------
+# D0_CS3n, D_A2, D1_CLK1_n, D1_CLK1_p, D0_CLK1_n, D0_CLK1_p
+#	48:59	,	0x4AA		,	(def_is_mba23)	;
+	48:49	,	0b10		,	(def_is_mba01)	;	# 8 CLK		, B0_CLK1_p
+	50:51	,	0b10		,	(def_is_mba01)	;	# 9 CLK		, B0_CLK1_n
+	52:53	,	0b00		,	(def_is_mba01)	;	#10 ADDR	, B_CASn
+	54:55	,	0b01		,	(def_is_mba01)	;	#11 CNTL	, B1_CS0n
+	56:57	,	0b01		,	(def_is_mba01)	;	#12 CNTL	, B1_CKE0
+	58:59	,	0b00		,	(def_is_mba01)	;	#13 ADDR	, B_A12
 	# -----------------  Port 3  ADR 2  Map 1  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL8
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL9
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL10 clk
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL11 clk
-	56:57	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL12 clk
-	58:59	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL13 clk
+	48:49	,	0b01		,	(def_is_mba23)	;	# 8 CNTL	, D0_CS3n
+	50:51	,	0b00		,	(def_is_mba23)	;	# 9 ADDR	, D_A2
+	52:53	,	0b10		,	(def_is_mba23)	;	#10 CLK		, D1_CLK1_n
+	54:55	,	0b10		,	(def_is_mba23)	;	#11 CLK		, D1_CLK1_p
+	56:57	,	0b10		,	(def_is_mba23)	;	#12 CLK		, D0_CLK1_n
+	58:59	,	0b10		,	(def_is_mba23)	;	#13 CLK		, D0_CLK1_p
+#	60:63	,	0b0000		,	any				;	# reserved
 }
 # -----------------  Port 1  ADR 3  -----------------------------------------------
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3
 scom 0x80014c2a0301143f {
 	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL0
-	50:51	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL2 clk
-	54:55	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL3 clk
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL4
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL5
-	60:61	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL6
-	62:63	,	0b01		,	(def_is_mba01)	;	# CNTL	# SEL7
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 3  lanes 0:7 ---------------------------------------------
+# B_A11, B0_CKE0, B0_CLK0_n, B0_CLK0_p, B_A13, B_A14, B1_CKE2, B1_ODT0
+#	48:63	,	0x1A0D		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 3  lanes 0:7 ---------------------------------------------
+# D1_CS2n, D0_ODT0, D0_CLK0_n, D0_CLK0_p, D_A6, D1_ODT1, D_A0, D_CASn
+#	48:63	,	0x5A10		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 0 ADDR	, B_A11
+	50:51	,	0b01		,	(def_is_mba01)	;	# 1 CNTL	, B0_CKE0
+	52:53	,	0b10		,	(def_is_mba01)	;	# 2 CLK		, B0_CLK0_n
+	54:55	,	0b10		,	(def_is_mba01)	;	# 3 CLK		, B0_CLK0_p
+	56:57	,	0b00		,	(def_is_mba01)	;	# 4 ADDR	, B_A13
+	58:59	,	0b00		,	(def_is_mba01)	;	# 5 ADDR	, B_A14
+	60:61	,	0b11		,	(def_is_mba01)	;	# 6 SPCKE	, B1_CKE2
+	62:63	,	0b01		,	(def_is_mba01)	;	# 7 CNTL	, B1_ODT0
 	# -----------------  Port 3  ADR 3  Map 0  ------------------------------------
-	48:49	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL0
-	50:51	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL1
-	52:53	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL2 clk
-	54:55	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL3 clk
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL4
-	58:59	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL5
-	60:61	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL6
-	62:63	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL7
+	48:49	,	0b01		,	(def_is_mba23)	;	# 0 CNTL	, D1_CS2n
+	50:51	,	0b01		,	(def_is_mba23)	;	# 1 CNTL	, D0_ODT0
+	52:53	,	0b10		,	(def_is_mba23)	;	# 2 CLK		, D0_CLK0_n
+	54:55	,	0b10		,	(def_is_mba23)	;	# 3 CLK		, D0_CLK0_p
+	56:57	,	0b00		,	(def_is_mba23)	;	# 4 ADDR	, D_A6
+	58:59	,	0b01		,	(def_is_mba23)	;	# 5 CNTL	, D1_ODT1
+	60:61	,	0b00		,	(def_is_mba23)	;	# 6 ADDR	, D_A0
+	62:63	,	0b00		,	(def_is_mba23)	;	# 7 ADDR	, D_CASn
 }
 # DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3
 scom 0x80014c2b0301143f {
-	bits	,	scom_data	,	expr			;
-	48:49	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL8
-	50:51	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL9
-	52:53	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL11
-	56:57	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL12
-	58:59	,	0b00		,	(def_is_mba01)	;	# CMD	# SEL13
+	bits	,	scom_data	,	expr			;				# signal
+#	0:47	,	0x000000000000,	any				;	# reserved
+#  ------ PORT 1  ADR 3  lanes 8:11 --------------------------------------------
+# B_A9, B_BA2, B_RASn, B_ACTn, B_A5, B_PAR
+#	48:59	,	0x000		,	(def_is_mba01)	;
+#  ------ PORT 3  ADR 3  lanes 8:11 --------------------------------------------
+# D_A14, D_A3, D_A7, D_A15, D_BA1, D0_CKE2
+#	48:59	,	0x003		,	(def_is_mba23)	;
+	48:49	,	0b00		,	(def_is_mba01)	;	# 8 ADDR	, B_A9
+	50:51	,	0b00		,	(def_is_mba01)	;	# 9 ADDR	, B_BA2
+	52:53	,	0b00		,	(def_is_mba01)	;	#10 ADDR	, B_RASn
+	54:55	,	0b00		,	(def_is_mba01)	;	#11 ADDR	, B_ACTn
+	56:57	,	0b00		,	(def_is_mba01)	;	#12 ADDR	, B_A5
+	58:59	,	0b00		,	(def_is_mba01)	;	#13 ADDR	, B_PAR
 	# -----------------  Port 3  ADR 3  Map 1  ------------------------------------
-	48:49	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL8
-	50:51	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL9
-	52:53	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL10
-	54:55	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL11
-	56:57	,	0b00		,	(def_is_mba23)	;	# CMD	# SEL12
-	58:59	,	0b01		,	(def_is_mba23)	;	# CNTL	# SEL13
+	48:49	,	0b00		,	(def_is_mba23)	;	# 8 ADDR	, D_A14
+	50:51	,	0b00		,	(def_is_mba23)	;	# 9 ADDR	, D_A3
+	52:53	,	0b00		,	(def_is_mba23)	;	#10 ADDR	, D_A7
+	54:55	,	0b00		,	(def_is_mba23)	;	#11 ADDR	, D_A15
+	56:57	,	0b00		,	(def_is_mba23)	;	#12 ADDR	, D_BA1
+	58:59	,	0b11		,	(def_is_mba23)	;	#13 SPCKE	, D0_CKE2
+#	60:63	,	0b0000		,	any				;	# reserved
 }
 
 # ---------------------------------------------------------------------------------------
-# ADR I/O Post Cursor Value Register	default=0		!! need to set?
-#
-# This register contains four Driver Post Cursor Slice values. The registers described in
-# Section 5.2.2.7 ADR I/O Post Cursor Value Map {0-1} on page 303 selects which one of
-# these four values are sent to each ADR output pin.
-#
-# The POST_CURSOR* control vectors select the amount of equalization enabled in the address
-# drivers. While the vectors determine whether a subset of the slices in each I/O operate
-# in either a normal data or post cursor data regime, it is the data history which determines
-# the amount of equalization provided at the driver output at any time.
-#
+# ADR I/O Post Cursor Value Register	default=0					not needed anymore
 # DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_P0_ADR0	0x018	0x800040180301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_18_L2
 #
-
 # ---------------------------------------------------------------------------------------
-# ADR I/O Post Cursor Value Map {0-1} Register		default=0		!! need to set?
-#
-# Each predefined pin pair on the ADR can be mapped to one of four Post Cursor values. These
-# registers determine which of the four Post Cursor values in the register described in
-# Section 5.2.2.6 ADR I/O Post Cursor Value on page 301 are used for the given ADR output pin.
-# Pins are defined by the mnemonic {{0-1}*8+n}, with n = 0 - 7, with register 0 containing
-# lanes 0:7 and register 1 containing lanes 8:15
-#
+# ADR I/O Post Cursor Value Map {0-1} Register		default=0		not needed anymore
 # DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0_P0_ADR0	0x028	0x800040280301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_28_L2
-#
 
 # ---------------------------------------------------------------------------------------
 # Centaur Vref Trimmer Control & RCM	default=0		!! need to set RCM for DDR3/4
@@ -1639,39 +2354,225 @@ scom 0x80014c2b0301143f {
 # 0x9 = 0.52750	 0x6 = 0.41750	|  0x9 = 0.72750  0x6 = 0.61750
 # 0x8 = 0.51375	 0x7 = 0.40375	|  0x8 = 0.71375  0x7 = 0.60375
 #
+# DP18_IO_RX_CONFIG0
 #	[01:23]					P[0:1]_[0:4]
 # DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0		0x006	0x800000060301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.RCVRPEAK_L2
 #scom 0x800(0,1)(00,04,08,0C,10)060301143f {	# _P[0:1]_[0:4]
-scom 0x800(0,1)3C060301143f {	# _P[0:1]_[0:4] via broadcast
+scom 0x80003C060301143f {	# _P[0:1]_[0:4] via broadcast
+	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
+	48:50	,	0b000		,	any				;	# PEAK_AMP_CTL_SIDE0, amp ctl bits
+#	51		,	0b0			,	any				;	# reserved, 0=no peaking, [1:7]=0.3dB-0.9dB
+	52:54	,	0b000		,	any				;	# PEAK_AMP_CTL_SIDE1, amp ctl bits
+#	55		,	0b0			,	any				;	# reserved
+	# SxMCVREF_0_3, Vref trim ctl signals				  DDR3								DDR4
+	56:59	,	0xF			,	((ATTR_EFF_CEN_RD_VREF[0] == 61000) || (ATTR_EFF_CEN_RD_VREF[0] == 81000))	;
+	56:59	,	0xE			,	((ATTR_EFF_CEN_RD_VREF[0] == 59625) || (ATTR_EFF_CEN_RD_VREF[0] == 79625))	;
+	56:59	,	0xD			,	((ATTR_EFF_CEN_RD_VREF[0] == 58250) || (ATTR_EFF_CEN_RD_VREF[0] == 78250))	;
+	56:59	,	0xC			,	((ATTR_EFF_CEN_RD_VREF[0] == 56875) || (ATTR_EFF_CEN_RD_VREF[0] == 76875))	;
+	56:59	,	0xB			,	((ATTR_EFF_CEN_RD_VREF[0] == 55500) || (ATTR_EFF_CEN_RD_VREF[0] == 75500))	;
+	56:59	,	0xA			,	((ATTR_EFF_CEN_RD_VREF[0] == 54125) || (ATTR_EFF_CEN_RD_VREF[0] == 74125))	;
+	56:59	,	0x9			,	((ATTR_EFF_CEN_RD_VREF[0] == 52750) || (ATTR_EFF_CEN_RD_VREF[0] == 72750))	;
+	56:59	,	0x8			,	((ATTR_EFF_CEN_RD_VREF[0] == 51375) || (ATTR_EFF_CEN_RD_VREF[0] == 71375))	;
+	56:59	,	0x0			,	((ATTR_EFF_CEN_RD_VREF[0] == 50000) || (ATTR_EFF_CEN_RD_VREF[0] == 70000))	;
+	56:59	,	0x1			,	((ATTR_EFF_CEN_RD_VREF[0] == 48625) || (ATTR_EFF_CEN_RD_VREF[0] == 68625))	;
+	56:59	,	0x2			,	((ATTR_EFF_CEN_RD_VREF[0] == 47250) || (ATTR_EFF_CEN_RD_VREF[0] == 67250))	;
+	56:59	,	0x3			,	((ATTR_EFF_CEN_RD_VREF[0] == 45875) || (ATTR_EFF_CEN_RD_VREF[0] == 65875))	;
+	56:59	,	0x4			,	((ATTR_EFF_CEN_RD_VREF[0] == 44500) || (ATTR_EFF_CEN_RD_VREF[0] == 64500))	;
+	56:59	,	0x5			,	((ATTR_EFF_CEN_RD_VREF[0] == 43125) || (ATTR_EFF_CEN_RD_VREF[0] == 63125))	;
+	56:59	,	0x6			,	((ATTR_EFF_CEN_RD_VREF[0] == 41750) || (ATTR_EFF_CEN_RD_VREF[0] == 61750))	;
+	56:59	,	0x7			,	((ATTR_EFF_CEN_RD_VREF[0] == 40375) || (ATTR_EFF_CEN_RD_VREF[0] == 60375))	;
+	56:59	,	0x0			,	any				;
+	60		,	0b1			,	(def_is_ddr4)	;	# SxPODVREF, if DDR4, POD=0.7*VDD
+	60		,	0b0			,	any				;	# else (DDR3), POD=0.5*VDD
+	61		,	0b0			,	any				;	# 1=DISABLE_TERMINATION, for dq/dqs pins
+	# READ_CENTERING_MODE
+	# (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data
+	62:63	,	0b11		,	def_is_ddr4		;	# for DDR4
+	62:63	,	0b00		,	any				;	#
+}
+
+scom 0x80013C060301143f {	# _P1_[0:4] via broadcast
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:50	,	0b000		,	any				;	# PEAK_AMP_CTL_SIDE0, amp ctl bits
 #	51		,	0b0			,	any				;	# reserved, 0=no peaking, [1:7]=0.3dB-0.9dB
 	52:54	,	0b000		,	any				;	# PEAK_AMP_CTL_SIDE1, amp ctl bits
 #	55		,	0b0			,	any				;	# reserved
 	# SxMCVREF_0_3, Vref trim ctl signals				  DDR3								DDR4
-	56:59	,	0xF			,	((ATTR_EFF_CEN_RD_VREF == 61000) || (ATTR_EFF_CEN_RD_VREF == 81000))	;
-	56:59	,	0xE			,	((ATTR_EFF_CEN_RD_VREF == 59625) || (ATTR_EFF_CEN_RD_VREF == 79625))	;
-	56:59	,	0xD			,	((ATTR_EFF_CEN_RD_VREF == 58250) || (ATTR_EFF_CEN_RD_VREF == 78250))	;
-	56:59	,	0xC			,	((ATTR_EFF_CEN_RD_VREF == 56875) || (ATTR_EFF_CEN_RD_VREF == 76875))	;
-	56:59	,	0xB			,	((ATTR_EFF_CEN_RD_VREF == 55500) || (ATTR_EFF_CEN_RD_VREF == 75500))	;
-	56:59	,	0xA			,	((ATTR_EFF_CEN_RD_VREF == 54125) || (ATTR_EFF_CEN_RD_VREF == 74125))	;
-	56:59	,	0x9			,	((ATTR_EFF_CEN_RD_VREF == 52750) || (ATTR_EFF_CEN_RD_VREF == 72750))	;
-	56:59	,	0x8			,	((ATTR_EFF_CEN_RD_VREF == 51375) || (ATTR_EFF_CEN_RD_VREF == 71375))	;
-	56:59	,	0x0			,	((ATTR_EFF_CEN_RD_VREF == 50000) || (ATTR_EFF_CEN_RD_VREF == 70000))	;
-	56:59	,	0x1			,	((ATTR_EFF_CEN_RD_VREF == 48625) || (ATTR_EFF_CEN_RD_VREF == 68625))	;
-	56:59	,	0x2			,	((ATTR_EFF_CEN_RD_VREF == 47250) || (ATTR_EFF_CEN_RD_VREF == 67250))	;
-	56:59	,	0x3			,	((ATTR_EFF_CEN_RD_VREF == 45875) || (ATTR_EFF_CEN_RD_VREF == 65875))	;
-	56:59	,	0x4			,	((ATTR_EFF_CEN_RD_VREF == 44500) || (ATTR_EFF_CEN_RD_VREF == 64500))	;
-	56:59	,	0x5			,	((ATTR_EFF_CEN_RD_VREF == 43125) || (ATTR_EFF_CEN_RD_VREF == 63125))	;
-	56:59	,	0x6			,	((ATTR_EFF_CEN_RD_VREF == 41750) || (ATTR_EFF_CEN_RD_VREF == 61750))	;
-	56:59	,	0x7			,	((ATTR_EFF_CEN_RD_VREF == 40375) || (ATTR_EFF_CEN_RD_VREF == 60375))	;
+	56:59	,	0xF			,	((ATTR_EFF_CEN_RD_VREF[1] == 61000) || (ATTR_EFF_CEN_RD_VREF[1] == 81000))	;
+	56:59	,	0xE			,	((ATTR_EFF_CEN_RD_VREF[1] == 59625) || (ATTR_EFF_CEN_RD_VREF[1] == 79625))	;
+	56:59	,	0xD			,	((ATTR_EFF_CEN_RD_VREF[1] == 58250) || (ATTR_EFF_CEN_RD_VREF[1] == 78250))	;
+	56:59	,	0xC			,	((ATTR_EFF_CEN_RD_VREF[1] == 56875) || (ATTR_EFF_CEN_RD_VREF[1] == 76875))	;
+	56:59	,	0xB			,	((ATTR_EFF_CEN_RD_VREF[1] == 55500) || (ATTR_EFF_CEN_RD_VREF[1] == 75500))	;
+	56:59	,	0xA			,	((ATTR_EFF_CEN_RD_VREF[1] == 54125) || (ATTR_EFF_CEN_RD_VREF[1] == 74125))	;
+	56:59	,	0x9			,	((ATTR_EFF_CEN_RD_VREF[1] == 52750) || (ATTR_EFF_CEN_RD_VREF[1] == 72750))	;
+	56:59	,	0x8			,	((ATTR_EFF_CEN_RD_VREF[1] == 51375) || (ATTR_EFF_CEN_RD_VREF[1] == 71375))	;
+	56:59	,	0x0			,	((ATTR_EFF_CEN_RD_VREF[1] == 50000) || (ATTR_EFF_CEN_RD_VREF[1] == 70000))	;
+	56:59	,	0x1			,	((ATTR_EFF_CEN_RD_VREF[1] == 48625) || (ATTR_EFF_CEN_RD_VREF[1] == 68625))	;
+	56:59	,	0x2			,	((ATTR_EFF_CEN_RD_VREF[1] == 47250) || (ATTR_EFF_CEN_RD_VREF[1] == 67250))	;
+	56:59	,	0x3			,	((ATTR_EFF_CEN_RD_VREF[1] == 45875) || (ATTR_EFF_CEN_RD_VREF[1] == 65875))	;
+	56:59	,	0x4			,	((ATTR_EFF_CEN_RD_VREF[1] == 44500) || (ATTR_EFF_CEN_RD_VREF[1] == 64500))	;
+	56:59	,	0x5			,	((ATTR_EFF_CEN_RD_VREF[1] == 43125) || (ATTR_EFF_CEN_RD_VREF[1] == 63125))	;
+	56:59	,	0x6			,	((ATTR_EFF_CEN_RD_VREF[1] == 41750) || (ATTR_EFF_CEN_RD_VREF[1] == 61750))	;
+	56:59	,	0x7			,	((ATTR_EFF_CEN_RD_VREF[1] == 40375) || (ATTR_EFF_CEN_RD_VREF[1] == 60375))	;
 	56:59	,	0x0			,	any				;
 	60		,	0b1			,	(def_is_ddr4)	;	# SxPODVREF, if DDR4, POD=0.7*VDD
 	60		,	0b0			,	any				;	# else (DDR3), POD=0.5*VDD
 	61		,	0b0			,	any				;	# 1=DISABLE_TERMINATION, for dq/dqs pins
+	# READ_CENTERING_MODE
 	# (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data
-	62:63	,	0b00		,	any				;	# READ_CENTERING_MODE
+	62:63	,	0b11		,	def_is_ddr4		;	# for DDR4
+	62:63	,	0b00		,	any				;	#
+}
+
+#-------------------------------------------------------------------------------
+# DDR Vref Output Driver Control register		default=0, output to DIMM
+#
+#    ATTR_EFF_DRAM_WR_VREF	DDR3 = [420, 425, 430, ... 575]
+#    Note:  NOT valid for DDR4.
+#
+# Vref driven to the DIMM(s) in 0.5% increments from 0.420 to 0.575.
+# Example: VDD=1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500,
+# 		Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V
+#
+# sign bit, VREFDQ[0:3]D
+# 01111 = 575+ 	01110 = 535		10000 = 495 	10001 = 455
+# 00111 = 570 	00110 = 530 	11000 = 490 	11001 = 450
+# 01011 = 565 	01010 = 525 	10100 = 485 	10101 = 445
+# 00011 = 560 	00010 = 520 	11100 = 480 	11101 = 440
+# 01101 = 555 	01100 = 515 	10010 = 475 	10011 = 435
+# 00101 = 550 	00100 = 510 	11010 = 470 	11011 = 430
+# 01001 = 545 	01000 = 505 	10110 = 465 	10111 = 425
+# 00001 = 540	00000 = 500*	11110 = 460		11111 = 420-
+#
+#	[01:23]						   [0:1]
+# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0		0x015	0x8000c0150301143f
+scom 0x8000c0150301143f {
+	bits	,	scom_data	,	expr							;
+#	0:47	,	0x000000000000,	any				;	# reserved
+	48		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF[0] < 500)	;	# VREF[0]DQ0 sign bit
+	48		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF[0] >= 500)	;	# VREF[0]DQ0 sign bit
+	# VREF[0]DQ0D bit enables
+	49:52	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420))	;
+	49:52	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425))	;
+	49:52	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430))	;
+	49:52	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435))	;
+	49:52	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440))	;
+	49:52	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445))	;
+	49:52	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450))	;
+	49:52	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455))	;
+	49:52	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460))	;
+	49:52	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465))	;
+	49:52	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470))	;
+	49:52	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475))	;
+	49:52	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480))	;
+	49:52	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485))	;
+	49:52	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490))	;
+	49:52	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495))	;
+	49:52	,	0b0000		,	any								;	# VREF[0]DQ0D bit enables
+	53		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF[0] < 500)	;	# VREF[0]DQ1 sign bit
+	53		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF[0] >= 500)	;	# VREF[0]DQ1 sign bit
+	# VREF[0]DQ1D bit enables
+	54:57	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420))	;
+	54:57	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425))	;
+	54:57	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430))	;
+	54:57	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435))	;
+	54:57	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440))	;
+	54:57	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445))	;
+	54:57	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450))	;
+	54:57	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455))	;
+	54:57	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460))	;
+	54:57	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465))	;
+	54:57	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470))	;
+	54:57	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475))	;
+	54:57	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480))	;
+	54:57	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485))	;
+	54:57	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490))	;
+	54:57	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495))	;
+	54:57	,	0b0000		,	any								;
+#	58:63	,	0b000000	,	any								;	# reserved
+
+# 	48:57	,	0x1EF		,	(ATTR_EFF_DRAM_WR_VREF[0] == 575)	;	# 0b 0 1111 0 1111	,	0b01 1110 1111
+# 	48:57	,	0x0E7		,	(ATTR_EFF_DRAM_WR_VREF[0] == 570)	;	# 0b 0 0111 0 0111	,	0b00 1110 0111
+# 	48:57	,	0x16B		,	(ATTR_EFF_DRAM_WR_VREF[0] == 565)	;	# 0b 0 1011 0 1011	,	0b01 0110 1011
+# 	48:57	,	0x063		,	(ATTR_EFF_DRAM_WR_VREF[0] == 560)	;	# 0b 0 0011 0 0011	,	0b00 0110 0011
+# 	48:57	,	0x1AD		,	(ATTR_EFF_DRAM_WR_VREF[0] == 555)	;	# 0b 0 1101 0 1101	,	0b01 1010 1101
+# 	48:57	,	0x0A5		,	(ATTR_EFF_DRAM_WR_VREF[0] == 550)	;	# 0b 0 0101 0 0101	,	0b00 1010 0101
+# 	48:57	,	0x129		,	(ATTR_EFF_DRAM_WR_VREF[0] == 545)	;	# 0b 0 1001 0 1001	,	0b01 0010 1001
+# 	48:57	,	0x029		,	(ATTR_EFF_DRAM_WR_VREF[0] == 540)	;	# 0b 0 0001 0 0001	,	0b00 0010 0001
+# 	48:57	,	0x1CE		,	(ATTR_EFF_DRAM_WR_VREF[0] == 535)	;	# 0b 0 1110 0 1110	,	0b01 1100 1110
+# 	48:57	,	0x0C6		,	(ATTR_EFF_DRAM_WR_VREF[0] == 530)	;	# 0b 0 0110 0 0110	,	0b00 1100 0110
+# 	48:57	,	0x14A		,	(ATTR_EFF_DRAM_WR_VREF[0] == 525)	;	# 0b 0 1010 0 1010	,	0b01 0100 1010
+# 	48:57	,	0x042		,	(ATTR_EFF_DRAM_WR_VREF[0] == 520)	;	# 0b 0 0010 0 0010	,	0b00 0100 0010
+# 	48:57	,	0x01C		,	(ATTR_EFF_DRAM_WR_VREF[0] == 515)	;	# 0b 0 1100 0 1100	,	0b01 1000 1100
+# 	48:57	,	0x004		,	(ATTR_EFF_DRAM_WR_VREF[0] == 510)	;	# 0b 0 0100 0 0100	,	0b00 1000 0100
+# 	48:57	,	0x108		,	(ATTR_EFF_DRAM_WR_VREF[0] == 505)	;	# 0b 0 1000 0 1000	,	0b01 0000 1000
+# 	48:57	,	0x000		,	(ATTR_EFF_DRAM_WR_VREF[0] == 500)	;	# 0b 0 0000 0 0000	,	0b00 0000 0000
+# 	48:57	,	0x210		,	(ATTR_EFF_DRAM_WR_VREF[0] == 495)	;	# 0b 1 0000 1 0000	,	0b10 0001 0000
+# 	48:57	,	0x318		,	(ATTR_EFF_DRAM_WR_VREF[0] == 490)	;	# 0b 1 1000 1 1000	,	0b11 0001 1000
+# 	48:57	,	0x294		,	(ATTR_EFF_DRAM_WR_VREF[0] == 485)	;	# 0b 1 0100 1 0100	,	0b10 1001 0100
+# 	48:57	,	0x39C		,	(ATTR_EFF_DRAM_WR_VREF[0] == 480)	;	# 0b 1 1100 1 1100	,	0b11 1001 1100
+# 	48:57	,	0x252		,	(ATTR_EFF_DRAM_WR_VREF[0] == 475)	;	# 0b 1 0010 1 0010	,	0b10 0101 0010
+# 	48:57	,	0x35A		,	(ATTR_EFF_DRAM_WR_VREF[0] == 470)	;	# 0b 1 1010 1 1010	,	0b11 0101 1010
+# 	48:57	,	0x2D6		,	(ATTR_EFF_DRAM_WR_VREF[0] == 465)	;	# 0b 1 0110 1 0110	,	0b10 1101 0110
+# 	48:57	,	0x3DE		,	(ATTR_EFF_DRAM_WR_VREF[0] == 460)	;	# 0b 1 1110 1 1110	,	0b11 1101 1110
+# 	48:57	,	0x231		,	(ATTR_EFF_DRAM_WR_VREF[0] == 455)	;	# 0b 1 0001 1 0001	,	0b10 0011 0001
+# 	48:57	,	0x339		,	(ATTR_EFF_DRAM_WR_VREF[0] == 450)	;	# 0b 1 1001 1 1001	,	0b11 0011 1001
+# 	48:57	,	0x2B5		,	(ATTR_EFF_DRAM_WR_VREF[0] == 445)	;	# 0b 1 0101 1 0101	,	0b10 1011 0101
+# 	48:57	,	0x3BD		,	(ATTR_EFF_DRAM_WR_VREF[0] == 440)	;	# 0b 1 1101 1 1101	,	0b11 1011 1101
+# 	48:57	,	0x273		,	(ATTR_EFF_DRAM_WR_VREF[0] == 435)	;	# 0b 1 0011 1 0011	,	0b10 0111 0011
+# 	48:57	,	0x37B		,	(ATTR_EFF_DRAM_WR_VREF[0] == 430)	;	# 0b 1 1011 1 1011	,	0b11 0111 1011
+# 	48:57	,	0x2F7		,	(ATTR_EFF_DRAM_WR_VREF[0] == 425)	;	# 0b 1 0111 1 0111	,	0b10 1111 0111
+# 	48:57	,	0x3FF		,	(ATTR_EFF_DRAM_WR_VREF[0] == 420)	;	# 0b 1 1111 1 1111	,	0b11 1111 1111
+#	58:63	,	0b000000	,	any								;	# reserved
+}
+# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1		0x015	0x8001c0150301143f
+scom 0x8001c0150301143f {
+	bits	,	scom_data	,	expr							;
+#	0:47	,	0x000000000000,	any				;	# reserved
+	48		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF[1] < 500)	;	# VREF[1]DQ0 sign bit
+	48		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF[1] >= 500)	;	# VREF[1]DQ0 sign bit
+	# VREF[1]DQ0D bit enables
+	49:52	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420))	;
+	49:52	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425))	;
+	49:52	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430))	;
+	49:52	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435))	;
+	49:52	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440))	;
+	49:52	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445))	;
+	49:52	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450))	;
+	49:52	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455))	;
+	49:52	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460))	;
+	49:52	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465))	;
+	49:52	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470))	;
+	49:52	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475))	;
+	49:52	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480))	;
+	49:52	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485))	;
+	49:52	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490))	;
+	49:52	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495))	;
+	49:52	,	0b0000		,	any								;	# VREF[1]DQ0D bit enables
+	53		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF[1] < 500)	;	# VREF[1]DQ1 sign bit
+	53		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF[1] >= 500)	;	# VREF[1]DQ1 sign bit
+	# VREF[1]DQ1D bit enables
+	54:57	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420))	;
+	54:57	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425))	;
+	54:57	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430))	;
+	54:57	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435))	;
+	54:57	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440))	;
+	54:57	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445))	;
+	54:57	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450))	;
+	54:57	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455))	;
+	54:57	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460))	;
+	54:57	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465))	;
+	54:57	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470))	;
+	54:57	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475))	;
+	54:57	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480))	;
+	54:57	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485))	;
+	54:57	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490))	;
+	54:57	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495))	;
+	54:57	,	0b0000		,	any								;
+#	58:63	,	0b000000	,	any								;	# reserved
 }
 
 # ---------------------------------------------------------------------------------------
@@ -1698,18 +2599,22 @@ scom 0x800(0,1)3C060301143f {	# _P[0:1]_[0:4] via broadcast
 #
 #						    [0:1]
 # DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P0		0x000-0x001		0x8000c4000301143f
+# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P0
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.RD_WR_DATA0_L2
 scom 0x8000c40(0,1)0301143f {
 	bits	,	scom_data	,	expr			;	#				beat 12345678
-	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
+#	0:47	,	0x000000000000,	any				;	# reserved
+#	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
 	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
 #	48:63	,	0xD896		,	any				;	# 1st half-nibble of EA0CA653 pattern
 }
 
-# DPHY01_DDRPHY_SEQ_RD_WR_DATA[0:1]_P1
+# DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P1
+# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P1
 scom 0x8001c40(0,1)0301143f {
 	bits	,	scom_data	,	expr			;	#				beat 12345678
-	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
+#	0:47	,	0x000000000000,	any				;	# reserved
+#	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
 	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
 #	48:63	,	0xCD03		,	any				;	# 2st half-nibble of EA0CA653 pattern
 }
@@ -1750,117 +2655,6 @@ scom 0x8001c40(0,1)0301143f {
 #
 
 #-------------------------------------------------------------------------------
-# DDR Vref Output Driver Control register		default=0, output to DIMM
-#
-#    ATTR_EFF_DRAM_WR_VREF	DDR3 = [420, 425, 430, ... 575]
-#    Note:  NOT valid for DDR4.
-#
-# Vref driven to the DIMM(s) in 0.5% increments from 0.420 to 0.575.
-# Example: VDD=1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500,
-# 		Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V
-#
-# sign bit, VREFDQ[0:3]D
-# 01111 = 575+ 	01110 = 535		10000 = 495 	10001 = 455
-# 00111 = 570 	00110 = 530 	11000 = 490 	11001 = 450
-# 01011 = 565 	01010 = 525 	10100 = 485 	10101 = 445
-# 00011 = 560 	00010 = 520 	11100 = 480 	11101 = 440
-# 01101 = 555 	01100 = 515 	10010 = 475 	10011 = 435
-# 00101 = 550 	00100 = 510 	11010 = 470 	11011 = 430
-# 01001 = 545 	01000 = 505 	10110 = 465 	10111 = 425
-# 00001 = 540	00000 = 500*	11110 = 460		11111 = 420-
-#
-#	[01:23]						   [0:1]
-# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0		0x015	0x8000c0150301143f
-scom 0x8000c0150301143f {
-	bits	,	scom_data	,	expr							;
-	48		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF < 500)	;	# VREFDQ0 sign bit
-	48		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF >= 500)	;	# VREFDQ0 sign bit
-	# VREFDQ0D bit enables
-	49:52	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF == 575) || (ATTR_EFF_DRAM_WR_VREF == 420))	;
-	49:52	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF == 570) || (ATTR_EFF_DRAM_WR_VREF == 425))	;
-	49:52	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF == 565) || (ATTR_EFF_DRAM_WR_VREF == 430))	;
-	49:52	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF == 560) || (ATTR_EFF_DRAM_WR_VREF == 435))	;
-	49:52	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF == 555) || (ATTR_EFF_DRAM_WR_VREF == 440))	;
-	49:52	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF == 550) || (ATTR_EFF_DRAM_WR_VREF == 445))	;
-	49:52	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF == 545) || (ATTR_EFF_DRAM_WR_VREF == 450))	;
-	49:52	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF == 540) || (ATTR_EFF_DRAM_WR_VREF == 455))	;
-	49:52	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF == 535) || (ATTR_EFF_DRAM_WR_VREF == 460))	;
-	49:52	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF == 530) || (ATTR_EFF_DRAM_WR_VREF == 465))	;
-	49:52	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF == 525) || (ATTR_EFF_DRAM_WR_VREF == 470))	;
-	49:52	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF == 520) || (ATTR_EFF_DRAM_WR_VREF == 475))	;
-	49:52	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF == 515) || (ATTR_EFF_DRAM_WR_VREF == 480))	;
-	49:52	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF == 510) || (ATTR_EFF_DRAM_WR_VREF == 485))	;
-	49:52	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF == 505) || (ATTR_EFF_DRAM_WR_VREF == 490))	;
-	49:52	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF == 500) || (ATTR_EFF_DRAM_WR_VREF == 495))	;
-	49:52	,	0b0000		,	any								;	# VREFDQ0D bit enables
-	53		,	0b1			,	(ATTR_EFF_DRAM_WR_VREF < 500)	;	# VREFDQ1 sign bit
-	53		,	0b0			,	(ATTR_EFF_DRAM_WR_VREF >= 500)	;	# VREFDQ1 sign bit
-	# VREFDQ1D bit enables
-	54:57	,	0xF			,	((ATTR_EFF_DRAM_WR_VREF == 575) || (ATTR_EFF_DRAM_WR_VREF == 420))	;
-	54:57	,	0x7			,	((ATTR_EFF_DRAM_WR_VREF == 570) || (ATTR_EFF_DRAM_WR_VREF == 425))	;
-	54:57	,	0xB			,	((ATTR_EFF_DRAM_WR_VREF == 565) || (ATTR_EFF_DRAM_WR_VREF == 430))	;
-	54:57	,	0x3			,	((ATTR_EFF_DRAM_WR_VREF == 560) || (ATTR_EFF_DRAM_WR_VREF == 435))	;
-	54:57	,	0xD			,	((ATTR_EFF_DRAM_WR_VREF == 555) || (ATTR_EFF_DRAM_WR_VREF == 440))	;
-	54:57	,	0x5			,	((ATTR_EFF_DRAM_WR_VREF == 550) || (ATTR_EFF_DRAM_WR_VREF == 445))	;
-	54:57	,	0x9			,	((ATTR_EFF_DRAM_WR_VREF == 545) || (ATTR_EFF_DRAM_WR_VREF == 450))	;
-	54:57	,	0x1			,	((ATTR_EFF_DRAM_WR_VREF == 540) || (ATTR_EFF_DRAM_WR_VREF == 455))	;
-	54:57	,	0xE			,	((ATTR_EFF_DRAM_WR_VREF == 535) || (ATTR_EFF_DRAM_WR_VREF == 460))	;
-	54:57	,	0x6			,	((ATTR_EFF_DRAM_WR_VREF == 530) || (ATTR_EFF_DRAM_WR_VREF == 465))	;
-	54:57	,	0xA			,	((ATTR_EFF_DRAM_WR_VREF == 525) || (ATTR_EFF_DRAM_WR_VREF == 470))	;
-	54:57	,	0x2			,	((ATTR_EFF_DRAM_WR_VREF == 520) || (ATTR_EFF_DRAM_WR_VREF == 475))	;
-	54:57	,	0xC			,	((ATTR_EFF_DRAM_WR_VREF == 515) || (ATTR_EFF_DRAM_WR_VREF == 480))	;
-	54:57	,	0x4			,	((ATTR_EFF_DRAM_WR_VREF == 510) || (ATTR_EFF_DRAM_WR_VREF == 485))	;
-	54:57	,	0x8			,	((ATTR_EFF_DRAM_WR_VREF == 505) || (ATTR_EFF_DRAM_WR_VREF == 490))	;
-	54:57	,	0x0			,	((ATTR_EFF_DRAM_WR_VREF == 500) || (ATTR_EFF_DRAM_WR_VREF == 495))	;
-	54:57	,	0b0000		,	any								;
-#	58:63	,	0b000000	,	any								;	# reserved
-
-# sign bit, VREFDQ[0:3]D
-# 01111 = 575+ 	01110 = 535		10000 = 495 	10001 = 455
-# 00111 = 570 	00110 = 530 	11000 = 490 	11001 = 450
-# 01011 = 565 	01010 = 525 	10100 = 485 	10101 = 445
-# 00011 = 560 	00010 = 520 	11100 = 480 	11101 = 440
-# 01101 = 555 	01100 = 515 	10010 = 475 	10011 = 435
-# 00101 = 550 	00100 = 510 	11010 = 470 	11011 = 430
-# 01001 = 545 	01000 = 505 	10110 = 465 	10111 = 425
-# 00001 = 540	00000 = 500*	11110 = 460		11111 = 420-
-#
-#																	D0SIGN, D0ENA, D1SIGN, D1ENA
-# 	48:57	,	0x1EF		,	(ATTR_EFF_DRAM_WR_VREF == 575)	;	# 0b 0 1111 0 1111	,	0b01 1110 1111
-# 	48:57	,	0x0E7		,	(ATTR_EFF_DRAM_WR_VREF == 570)	;	# 0b 0 0111 0 0111	,	0b00 1110 0111
-# 	48:57	,	0x16B		,	(ATTR_EFF_DRAM_WR_VREF == 565)	;	# 0b 0 1011 0 1011	,	0b01 0110 1011
-# 	48:57	,	0x063		,	(ATTR_EFF_DRAM_WR_VREF == 560)	;	# 0b 0 0011 0 0011	,	0b00 0110 0011
-# 	48:57	,	0x1AD		,	(ATTR_EFF_DRAM_WR_VREF == 555)	;	# 0b 0 1101 0 1101	,	0b01 1010 1101
-# 	48:57	,	0x0A5		,	(ATTR_EFF_DRAM_WR_VREF == 550)	;	# 0b 0 0101 0 0101	,	0b00 1010 0101
-# 	48:57	,	0x129		,	(ATTR_EFF_DRAM_WR_VREF == 545)	;	# 0b 0 1001 0 1001	,	0b01 0010 1001
-# 	48:57	,	0x029		,	(ATTR_EFF_DRAM_WR_VREF == 540)	;	# 0b 0 0001 0 0001	,	0b00 0010 0001
-# 	48:57	,	0x1CE		,	(ATTR_EFF_DRAM_WR_VREF == 535)	;	# 0b 0 1110 0 1110	,	0b01 1100 1110
-# 	48:57	,	0x0C6		,	(ATTR_EFF_DRAM_WR_VREF == 530)	;	# 0b 0 0110 0 0110	,	0b00 1100 0110
-# 	48:57	,	0x14A		,	(ATTR_EFF_DRAM_WR_VREF == 525)	;	# 0b 0 1010 0 1010	,	0b01 0100 1010
-# 	48:57	,	0x042		,	(ATTR_EFF_DRAM_WR_VREF == 520)	;	# 0b 0 0010 0 0010	,	0b00 0100 0010
-# 	48:57	,	0x01C		,	(ATTR_EFF_DRAM_WR_VREF == 515)	;	# 0b 0 1100 0 1100	,	0b01 1000 1100
-# 	48:57	,	0x004		,	(ATTR_EFF_DRAM_WR_VREF == 510)	;	# 0b 0 0100 0 0100	,	0b00 1000 0100
-# 	48:57	,	0x108		,	(ATTR_EFF_DRAM_WR_VREF == 505)	;	# 0b 0 1000 0 1000	,	0b01 0000 1000
-# 	48:57	,	0x000		,	(ATTR_EFF_DRAM_WR_VREF == 500)	;	# 0b 0 0000 0 0000	,	0b00 0000 0000
-# 	48:57	,	0x210		,	(ATTR_EFF_DRAM_WR_VREF == 495)	;	# 0b 1 0000 1 0000	,	0b10 0001 0000
-# 	48:57	,	0x318		,	(ATTR_EFF_DRAM_WR_VREF == 490)	;	# 0b 1 1000 1 1000	,	0b11 0001 1000
-# 	48:57	,	0x294		,	(ATTR_EFF_DRAM_WR_VREF == 485)	;	# 0b 1 0100 1 0100	,	0b10 1001 0100
-# 	48:57	,	0x39C		,	(ATTR_EFF_DRAM_WR_VREF == 480)	;	# 0b 1 1100 1 1100	,	0b11 1001 1100
-# 	48:57	,	0x252		,	(ATTR_EFF_DRAM_WR_VREF == 475)	;	# 0b 1 0010 1 0010	,	0b10 0101 0010
-# 	48:57	,	0x35A		,	(ATTR_EFF_DRAM_WR_VREF == 470)	;	# 0b 1 1010 1 1010	,	0b11 0101 1010
-# 	48:57	,	0x2D6		,	(ATTR_EFF_DRAM_WR_VREF == 465)	;	# 0b 1 0110 1 0110	,	0b10 1101 0110
-# 	48:57	,	0x3DE		,	(ATTR_EFF_DRAM_WR_VREF == 460)	;	# 0b 1 1110 1 1110	,	0b11 1101 1110
-# 	48:57	,	0x231		,	(ATTR_EFF_DRAM_WR_VREF == 455)	;	# 0b 1 0001 1 0001	,	0b10 0011 0001
-# 	48:57	,	0x339		,	(ATTR_EFF_DRAM_WR_VREF == 450)	;	# 0b 1 1001 1 1001	,	0b11 0011 1001
-# 	48:57	,	0x2B5		,	(ATTR_EFF_DRAM_WR_VREF == 445)	;	# 0b 1 0101 1 0101	,	0b10 1011 0101
-# 	48:57	,	0x3BD		,	(ATTR_EFF_DRAM_WR_VREF == 440)	;	# 0b 1 1101 1 1101	,	0b11 1011 1101
-# 	48:57	,	0x273		,	(ATTR_EFF_DRAM_WR_VREF == 435)	;	# 0b 1 0011 1 0011	,	0b10 0111 0011
-# 	48:57	,	0x37B		,	(ATTR_EFF_DRAM_WR_VREF == 430)	;	# 0b 1 1011 1 1011	,	0b11 0111 1011
-# 	48:57	,	0x2F7		,	(ATTR_EFF_DRAM_WR_VREF == 425)	;	# 0b 1 0111 1 0111	,	0b10 1111 0111
-# 	48:57	,	0x3FF		,	(ATTR_EFF_DRAM_WR_VREF == 420)	;	# 0b 1 1111 1 1111	,	0b11 1111 1111
-}
-
-#-------------------------------------------------------------------------------
 # 	ODT Default Configuration Register
 #
 # Determines the ODT values sent to all ranks during MRS commands
@@ -1887,24 +2681,28 @@ scom 0x8000c0150301143f {
 scom 0x8000C40E0301143F {
 #		      ODT 01234567
 	bits	,	scom_data					;	# DIMM0, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[0][0][0]	;	# when Read of Rank0
 	56:63	,	ATTR_EFF_ODT_RD[0][0][1]	;	# when Read of Rank1
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P0
 scom 0x8000C40F0301143F {
 	bits	,	scom_data					;	# DIMM0, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[0][0][2]	;	# when Read of Rank2
 	56:63	,	ATTR_EFF_ODT_RD[0][0][3]	;	# when Read of Rank3
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P0
 scom 0x8000C4100301143F {
 	bits	,	scom_data					;	# DIMM1, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[0][1][0]	;	# when Read of Rank4
 	56:63	,	ATTR_EFF_ODT_RD[0][1][1]	;	# when Read of Rank5
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P0
 scom 0x8000C4110301143F {
 	bits	,	scom_data					;	# DIMM1, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[0][1][2]	;	# when Read of Rank6
 	56:63	,	ATTR_EFF_ODT_RD[0][1][3]	;	# when Read of Rank7
 }
@@ -1912,24 +2710,28 @@ scom 0x8000C4110301143F {
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P1
 scom 0x8001C40E0301143F {
 	bits	,	scom_data					;	# DIMM2, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[1][0][0]	;	# when Read of Rank0
 	56:63	,	ATTR_EFF_ODT_RD[1][0][1]	;	# when Read of Rank1
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P1
 scom 0x8001C40F0301143F {
 	bits	,	scom_data					;	# DIMM2, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[1][0][2]	;	# when Read of Rank2
 	56:63	,	ATTR_EFF_ODT_RD[1][0][3]	;	# when Read of Rank3
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P1
 scom 0x8001C4100301143F {
 	bits	,	scom_data					;	# DIMM3, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[1][1][0]	;	# when Read of Rank4
 	56:63	,	ATTR_EFF_ODT_RD[1][1][1]	;	# when Read of Rank5
 }
 # DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P1
 scom 0x8001C4110301143F {
 	bits	,	scom_data					;	# DIMM3, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_RD[1][1][2]	;	# when Read of Rank6
 	56:63	,	ATTR_EFF_ODT_RD[1][1][3]	;	# when Read of Rank7
 }
@@ -1943,24 +2745,28 @@ scom 0x8001C4110301143F {
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.ODT_WR_CONFIG0_L2
 scom 0x8000C40A0301143F {
 	bits	,	scom_data					;	# DIMM0, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[0][0][0]	;	# when write of Rank0
 	56:63	,	ATTR_EFF_ODT_WR[0][0][1]	;	# when write of Rank1
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P0
 scom 0x8000C40B0301143F {
 	bits	,	scom_data					;	# DIMM0, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[0][0][2]	;	# when write of Rank2
 	56:63	,	ATTR_EFF_ODT_WR[0][0][3]	;	# when write of Rank3
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P0
 scom 0x8000C40C0301143F {
 	bits	,	scom_data					;	# DIMM1, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[0][1][0]	;	# when write of Rank4
 	56:63	,	ATTR_EFF_ODT_WR[0][1][1]	;	# when write of Rank5
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P0
 scom 0x8000C40D0301143F {
 	bits	,	scom_data					;	# DIMM1, Port0
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[0][1][2]	;	# when write of Rank6
 	56:63	,	ATTR_EFF_ODT_WR[0][1][3]	;	# when write of Rank7
 }
@@ -1968,24 +2774,28 @@ scom 0x8000C40D0301143F {
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P1
 scom 0x8001C40A0301143F {
 	bits	,	scom_data					;	# DIMM2, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[1][0][0]	;	# when write of Rank0
 	56:63	,	ATTR_EFF_ODT_WR[1][0][1]	;	# when write of Rank1
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P1
 scom 0x8001C40B0301143F {
 	bits	,	scom_data					;	# DIMM2, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[1][0][2]	;	# when write of Rank2
 	56:63	,	ATTR_EFF_ODT_WR[1][0][3]	;	# when write of Rank3
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P1
 scom 0x8001C40C0301143F {
 	bits	,	scom_data					;	# DIMM3, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[1][1][0]	;	# when write of Rank4
 	56:63	,	ATTR_EFF_ODT_WR[1][1][1]	;	# when write of Rank5
 }
 # DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P1
 scom 0x8001C40D0301143F {
 	bits	,	scom_data					;	# DIMM3, Port1
+#	0:47	,	0x000000000000				;	# reserved
 	48:55	,	ATTR_EFF_ODT_WR[1][1][2]	;	# when write of Rank6
 	56:63	,	ATTR_EFF_ODT_WR[1][1][3]	;	# when write of Rank7
 }
@@ -1995,46 +2805,13 @@ scom 0x8001C40D0301143F {
 #
 # DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0		0x01C	0x8000c01c0301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG28_RP0_L2
-#
-# ~~~~~~~~~~~~  Mode Register settings  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-# -- MR0 --		DDRPHY_PC_MR0_PRI_RP[0:3]_P[0:1]	0x01C	0x8000c01c0301143f
-# ATTR_EFF_DRAM_DLL_PPD						# 0=slow exit, 1=fast exit
-# ATTR_EFF_DRAM_WR
-# ATTR_EFF_DRAM_DLL_RESET					# 0=no, 1=yes
-# ATTR_EFF_DRAM_TM							# 0=normal, 1= Test
-# ATTR_EFF_DRAM_CL
-# ATTR_EFF_DRAM_RBT							# 0=sequential, 1=interleave
-# ATTR_EFF_DRAM_BL							# 0=BL8, OTF=1, BC4=2
-# -- MR1 --		DDRPHY_PC_MR1_PRI_RP[0:3]_P[0:1]	0x01D	0x8000c01d0301143f
-# ATTR_EFF_DRAM_OUTPUT_BUFFER				# 0=enable, 1=disable
-# ATTR_EFF_DRAM_TDQS						# 0=disable, 1=enable
-# ATTR_EFF_DRAM_RTT_NOM	[0..1][0..1][0..3]	# 0, 20, 30, 34(DDR4), 40, 48(DDR4), 50, 80(DDR4), 120, 240(DDR4)
-# ATTR_EFF_DRAM_WR_LVL_ENABLE				# 0=disable, 1=enable
-# ATTR_EFF_DRAM_RON	[0..1][0..1]			# 34, 40(DDR3)
-# ATTR_EFF_DRAM_AL							# 0=disable, 1=CL-1, 2=CL-2
-# ATTR_EFF_DRAM_DLL_ENABLE					# 0=enable 1=disable
-# -- MR2 --		DDRPHY_PC_MR2_PRI_RP[0:3]_P[0:1]	0x01E	0x8000c01e0301143f
-# ATTR_EFF_DRAM_RTT_WR	[0..1][0..1][0..3]	# 0, 60, 120
-# ATTR_EFF_DRAM_SRT							# 0=normal, 1=extend
-# ATTR_EFF_DRAM_ASR							# 0=SRT, 1=ASR
-# ATTR_EFF_DRAM_CWL
-# ATTR_EFF_DRAM_PASR	# 0=full, 1=1st 1/2, 2=1st 1/4, 3=1st 1/8, 4=last 3/4, 5=last 1/2, 6=last 1/4, 7=last 1/8
-# -- MR3 --		DDRPHY_PC_MR3_PRI_RP[0:3]_P[0:1]	0x01F	0x8000c01f0301143f
-# ATTR_EFF_MPR_MODE							# 0=disable, 1=enable
-# ATTR_EFF_MPR_LOC
-# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-#
-# ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15	[0..1][0..1]	uint64
-#
-# RCD_LRDIM_CNTL_WORD0_15Q	0x000000dd
-# CWD=BA1,BA0,A4,A3	0:3=CWD0, 4:7=CWD1, 8:11=CWD2, etc.
-# last RCD or LRDIMM control word that was programmed using CCS.
 
 # ---------------------------------------------------------------------------------------
-# PC Chip select ID configuration register	default=0	!! need to set?
+# PC Chip select ID configuration register	default=0		NEED to be programmed for DDR4/TSV dimms.
+# 															HERE MW
 #
 # This register controls the value of Chip Select (CS) signals not selected
-# by any of the PC Rank Pair registers during initial calibration.
+# by any of the PC Rank Pair registers during initial calibration for DDR4 / TSV dimms.
 #
 # DPHY01_DDRPHY_PC_CSID_CFG_P0		0x033	0x8000c0330301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG51_L2
@@ -2062,6 +2839,7 @@ scom 0x8001C40D0301143F {
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.DQSOFFSET_L2(0:6)
 scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 	bits	,	scom_data		,	expr			;
+#	0:47	,	0x000000000000	,	any				;	# reserved
 #	48		,	0b0				,	any				;	# reserved
 #	49:55	,	0b0010000		,	(def_is_sim)	;	# DQS_OFFSET
 	49:55	,	def_dqs_offset ,	any				;	# DQS_OFFSET, 7 bits
@@ -2090,6 +2868,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # _RP[0:3]_P[0:1]_[0:4], all instances and rank pairs via broadcast, both ports
 # scom 0x800(0,1)3CFE0301143f {	# _RP[0:3]_P[0:1]_[0:4]
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	48:51	,	0x0			,	any				;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	any				;	# DQ_WR_OFFSET_N1
 # 	56:59	,	0x0			,	any				;	# DQ_WR_OFFSET_N2
@@ -2098,6 +2877,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 #
 # scom 0x80003C7E0301143f {	# _RP0_P0_[0:4], rank pair 0, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2111,6 +2891,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003D7E0301143f {	# _RP1_P0_[0:4], rank pair 1, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2124,6 +2905,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003E7E0301143f {	# _RP2_P0_[0:4], rank pair 2, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2137,6 +2919,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80003F7E0301143f {	# _RP3_P0_[0:4], rank pair 3, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 0  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2151,6 +2934,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # ===============================================================================
 # scom 0x80013C7E0301143f {	# _RP0_P1_[0:4], rank pair 0, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2164,6 +2948,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013D7E0301143f {	# _RP1_P1_[0:4], rank pair 1, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2177,6 +2962,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013E7E0301143f {	# _RP2_P1_[0:4], rank pair 2, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2190,6 +2976,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 # scom 0x80013F7E0301143f {	# _RP3_P1_[0:4], rank pair 3, all instances via broadcast
 # 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 # 	~~~~~~~~~~~~~~~  Port 1  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 # 	48:51	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N0
 # 	52:55	,	0x0			,	(def_is_mba01)		;	# DQ_WR_OFFSET_N1
@@ -2203,7 +2990,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # }
 
 # ---------------------------------------------------------------------------------------
-# DP18 Write Delay Value {0-23} Register	default=0x0008		!! need to set this?
+# DP18 Write Delay Value {0-23} Register	default=0x0008		!! set after characterization
 #
 # Attributes
 # Read/Write via programming interface. Write via hardware.
@@ -2223,7 +3010,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 #
 
 # ---------------------------------------------------------------------------------------
-# DP18 Read Delay Value {0-11} Register		default=0x4040		!! need to set this?
+# DP18 Read Delay Value {0-11} Register		default=0x4040		!! characterization req'd
 #
 # Attributes
 # Read/Write via programming interface. Write via hardware. Each register holds the delay value
@@ -2241,7 +3028,7 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 #
 
 # ---------------------------------------------------------------------------------------
-# DP18 Drift Limits Register		default=0		!! need to set this?
+# DP18 Drift Limits Register		default=0		!! set after characterization
 #
 # Description
 # This register holds the limits for periodic drift of the data eye and the received strobe.
@@ -2249,6 +3036,8 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # DPHY01_DDRPHY_DP18_DRIFT_LIMITS_P0_0		0x00A		0x8000000a0301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.LIMITS_L2
 #
+# min_rd_eye_size, max_dqs_drift
+# 0 disables check
 
 # ---------------------------------------------------------------------------------------
 # DP18 DQS Gate Delay Register		default=0		!! need to set this?
@@ -2286,19 +3075,20 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG22_L2
 scom 0x8000C0160301143F {	# Port 0
 	bits	,	scom_data	,	expr				;
-	48		,	0b1			,	(def_is_sim)		;	# ENA_WR_LEVEL
-	49		,	0b0			,	(def_is_sim)		;	# ENA_INITIAL_PAT_WR, for custom pattern
-	50		,	0b1			,	(def_is_sim)		;	# ENA_DQS_ALIGN
-	51		,	0b1			,	(def_is_sim)		;	# ENA_RDCLK_ALIGN
+#	0:47	,	0x000000000000,	any					;	# reserved
+	48		,	0b1			,	any					;	# ENA_WR_LEVEL
+	49		,	0b0			,	any					;	# ENA_INITIAL_PAT_WR, for custom pattern
+	50		,	0b1			,	any					;	# ENA_DQS_ALIGN
+	51		,	0b1			,	any					;	# ENA_RDCLK_ALIGN
 
-	52		,	0b1			,	(def_is_sim)		;	# ENA_READ_CTR
-	53		,	0b1			,	(def_is_sim)		;	# ENA_WRITE_CTR
-	54		,	0b1			,	(def_is_sim)		;	# ENA_INITIAL_COARSE_WR
-	55		,	0b1			,	(def_is_sim)		;	# ENA_COARSE_RD
+	52		,	0b1			,	any					;	# ENA_READ_CTR
+	53		,	0b1			,	any					;	# ENA_WRITE_CTR
+	54		,	0b1			,	any					;	# ENA_INITIAL_COARSE_WR
+	55		,	0b1			,	any					;	# ENA_COARSE_RD
 
 	56		,	0b0			,	any					;	# ENA_CUSTOM_RD
 	57		,	0b0			,	any					;	# ENA_CUSTOM_WR
-	58		,	0b1			,	(def_is_sim)		;	# ABORT_ON_CAL_ERROR
+	58		,	0b1			,	any					;	# ABORT_ON_CAL_ERROR
 	59		,	0b0			,	any					;	# ENA_DIGITAL_EYE
 
 	# ENA_RANK_GROUP[0:3], 4 bits
@@ -2315,6 +3105,7 @@ scom 0x8000C0160301143F {	# Port 0
 # DPHY01.DDRPHY_PC_INIT_CAL_CONFIG0_P1
 scom 0x8001C0160301143F {	# Port 1
 	bits	,	scom_data	,	expr				;
+#	0:47	,	0x000000000000,	any					;	# reserved
 	48		,	0b1			,	(def_is_sim)		;	# ENA_WR_LEVEL
 	49		,	0b0			,	(def_is_sim)		;	# ENA_INITIAL_PAT_WR, for custom pattern
 	50		,	0b1			,	(def_is_sim)		;	# ENA_DQS_ALIGN
@@ -2340,23 +3131,35 @@ scom 0x8001C0160301143F {	# Port 1
 
 # ---------------------------------------------------------------------------------------
 # Initial calibration sequence Config1 register		default=0
+# EFF_DRAM_TRFI
 #
 # Controls refreshes during calibration, and regular refresh interval.
-# !! Needed? 	Does a procedure do this?
-#
-# EFF_DRAM_TRFI
+# if DDR3/4 with custom pattern then need refresh since pattern written into memory
+#
+# REFRESH_CONTROL {	00 = Refresh commands are only sent at start of initial calibration,
+#					based on the value in the .REFRESH_COUNT. field. Disables if count=0
+#					01 = Use the internal Refresh Interval timer to determine when refresh
+#					commands are sent; allow refreshes to occur between calibration routines.
+#					10 = Reserved
+#					11 = Use the internal Refresh Interval timer to determine when refresh
+#					commands should be sent; in addition to allowing refreshes commands to be
+#					issued between calibration routines, also allow refreshes to interrupt each
+#					calibration routine (as required). This is the recommended setting when
+#					refreshes are required during initial calibration.
+#					}
 #
 # DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0		0x017	0x8000c0170301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG23_L2
 scom 0x800(0,1)C0170301143F {	# _P[0:1]
 	bits	,	scom_data		,	expr			;
+#	0:47	,	0x000000000000	,	any				;	# reserved
 	48:51	,	0b0000			,	any				;	# REFRESH_COUNT, num of refreshes before cal
 	52:53	,	0b00			,	any				;	# REFRESH_CONTROL during initial calibration
 	54		,	0b0				,	any				;	# REFRESH_ALL_RANKS, during calibration
 #	55:56	,	0b00			,	any				;	# reserved
 	# REFRESH_INTERVAL, defaults to 6 if value < 6, value*256=num clks between refreshes
 	# ATTR_EFF_DRAM_TRFI = refresh interval in clocks
-	57:63	,	0b0000000		,	(def_is_sim)	;	# match dials
+#	57:63	,	0b0000000		,	(def_is_sim)	;	# match dials
 	57:63	,	(ATTR_EFF_DRAM_TRFI >> 8)	,	any	;	# field needs refresh/256
 }
 
@@ -2368,53 +3171,57 @@ scom 0x800(0,1)C0170301143F {	# _P[0:1]
 # DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0		0x00B	0x8000c00b0301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG11_L2
 scom 0x8000C00B0301143F {	# Port 0
-	bits	,	scom_data	,	expr				;
+	bits	,	scom_data	,	expr					;
+#	0:47	,	0x000000000000,	any						;	# reserved
 	# PER_ENA_RANK_GROUP[0:3], 4 bits
-	48		,	0b1			,	(def_val_prg0_p0)	;	# enable primary rank group 0
-	48		,	0b0			,	any					;	# disable primary rank group 0
-	49		,	0b1			,	(def_val_prg1_p0)	;	# enable primary rank group 1
-	49		,	0b0			,	any					;	# disable primary rank group 1
-	50		,	0b1			,	(def_val_prg2_p0)	;	# enable primary rank group 2
-	50		,	0b0			,	any					;	# disable primary rank group 2
-	51		,	0b1			,	(def_val_prg3_p0)	;	# enable primary rank group 3
-	51		,	0b0			,	any					;	# disable primary rank group 3
-
-	52		,	0b1			,	any					;	# PER_ENA_ZCAL
-	53		,	0b1			,	any					;	# PER_ENA_SYSCLK_ALIGN
-	54		,	0b1			,	any					;	# ENA_PER_RDCLK_ALIGN
-	55		,	0b1			,	any					;	# ENA_PER_DQS_ALIGN
-	56		,	0b1			,	any					;	# ENA_PER_READ_CTR
-	57:58	,	0b00		,	any					;	# PER_NEXT_RANK_group
-	59		,	0b1			,	any					;	# FAST_SIM_PER_CNTR
-	60		,	0b0			,	any					;	# START_INIT_CAL
-	61		,	0b0			,	any					;	# START_PER_CAL
-	62		,	0b0			,	any					;	# ABORT_ON_ERR_EN
-	63		,	0b0			,	any					;	# ZCAL_UPDATE_MODE
+	48		,	0b1			,	(def_val_prg0_p0)		;	# enable primary rank group 0
+	48		,	0b0			,	any						;	# disable primary rank group 0
+	49		,	0b1			,	(def_val_prg1_p0)		;	# enable primary rank group 1
+	49		,	0b0			,	any						;	# disable primary rank group 1
+	50		,	0b1			,	(def_val_prg2_p0)		;	# enable primary rank group 2
+	50		,	0b0			,	any						;	# disable primary rank group 2
+	51		,	0b1			,	(def_val_prg3_p0)		;	# enable primary rank group 3
+	51		,	0b0			,	any						;	# disable primary rank group 3
+
+	52		,	0b1			,	any						;	# PER_ENA_ZCAL
+	53		,	0b1			,	any						;	# PER_ENA_SYSCLK_ALIGN
+	54		,	0b1			,	any						;	# ENA_PER_RDCLK_ALIGN
+	55		,	0b1			,	any						;	# ENA_PER_DQS_ALIGN
+	56		,	0b1			,	any						;	# ENA_PER_READ_CTR
+	57:58	,	0b00		,	any						;	# PER_NEXT_RANK_PAIR
+	59		,	0b1			,	(def_FAST_SIM_PC==1)	;	# FAST_SIM_PER_CNTR
+	59		,	0b0			,	(def_FAST_SIM_PC==0)	;	# FAST_SIM_PER_CNTR
+	60		,	0b0			,	any						;	# START_INIT_CAL
+	61		,	0b0			,	any						;	# START_PER_CAL
+	62		,	0b0			,	any						;	# ABORT_ON_ERR_EN
+	63		,	0b0			,	any						;	# ZCAL_UPDATE_MODE
 }
 # DPHY01.DDRPHY_PC_PER_CAL_CONFIG_P1
 scom 0x8001C00B0301143F {	# Port 1
-	bits	,	scom_data	,	expr				;
+	bits	,	scom_data	,	expr					;
+#	0:47	,	0x000000000000,	any						;	# reserved
 	# PER_ENA_RANK_GROUP[0:3], 4 bits
-	48		,	0b1			,	(def_val_prg0_p1)	;	# enable primary rank group 0
-	48		,	0b0			,	any					;	# disable primary rank group 0
-	49		,	0b1			,	(def_val_prg1_p1)	;	# enable primary rank group 1
-	49		,	0b0			,	any					;	# disable primary rank group 1
-	50		,	0b1			,	(def_val_prg2_p1)	;	# enable primary rank group 2
-	50		,	0b0			,	any					;	# disable primary rank group 2
-	51		,	0b1			,	(def_val_prg3_p1)	;	# enable primary rank group 3
-	51		,	0b0			,	any					;	# disable primary rank group 3
-
-	52		,	0b1			,	any					;	# PER_ENA_ZCAL
-	53		,	0b1			,	any					;	# PER_ENA_SYSCLK_ALIGN
-	54		,	0b1			,	any					;	# ENA_PER_RDCLK_ALIGN
-	55		,	0b1			,	any					;	# ENA_PER_DQS_ALIGN
-	56		,	0b1			,	any					;	# ENA_PER_READ_CTR
-	57:58	,	0b00		,	any					;	# PER_NEXT_RANK_PAIR
-	59		,	0b1			,	any					;	# FAST_SIM_PER_CNTR
-	60		,	0b0			,	any					;	# START_INIT_CAL
-	61		,	0b0			,	any					;	# START_PER_CAL
-	62		,	0b0			,	any					;	# ABORT_ON_ERR_EN
-	63		,	0b0			,	any					;	# ZCAL_UPDATE_MODE
+	48		,	0b1			,	(def_val_prg0_p1)		;	# enable primary rank group 0
+	48		,	0b0			,	any						;	# disable primary rank group 0
+	49		,	0b1			,	(def_val_prg1_p1)		;	# enable primary rank group 1
+	49		,	0b0			,	any						;	# disable primary rank group 1
+	50		,	0b1			,	(def_val_prg2_p1)		;	# enable primary rank group 2
+	50		,	0b0			,	any						;	# disable primary rank group 2
+	51		,	0b1			,	(def_val_prg3_p1)		;	# enable primary rank group 3
+	51		,	0b0			,	any						;	# disable primary rank group 3
+
+	52		,	0b1			,	any						;	# PER_ENA_ZCAL
+	53		,	0b1			,	any						;	# PER_ENA_SYSCLK_ALIGN
+	54		,	0b1			,	any						;	# ENA_PER_RDCLK_ALIGN
+	55		,	0b1			,	any						;	# ENA_PER_DQS_ALIGN
+	56		,	0b1			,	any						;	# ENA_PER_READ_CTR
+	57:58	,	0b00		,	any						;	# PER_NEXT_RANK_PAIR
+	59		,	0b1			,	(def_FAST_SIM_PC==1)	;	# FAST_SIM_PER_CNTR
+	59		,	0b0			,	(def_FAST_SIM_PC==0)	;	# FAST_SIM_PER_CNTR
+	60		,	0b0			,	any						;	# START_INIT_CAL
+	61		,	0b0			,	any						;	# START_PER_CAL
+	62		,	0b0			,	any						;	# ABORT_ON_ERR_EN
+	63		,	0b0			,	any						;	# ZCAL_UPDATE_MODE
 }
 
 # ---------------------------------------------------------------------------------------
@@ -2436,10 +3243,9 @@ scom 0x8001C00B0301143F {	# Port 1
 # DPHY01_DDRPHY_PC_RELOAD_VALUE0_P0		0x005	0x8000c0050301143f
 scom 0x800(0,1)C0050301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48		,	0b0			,	any				;	# PERIODIC_CAL_REQ_EN
 	49:63	,	0x0001		,	any				;	# PERIODIC_RELOAD_VALUE0
-# !! problem with right alignment that needs to be 0x0002 instead of 0x0001
-#	49:63	,	0x0002		,	any				;	# PERIODIC_RELOAD_VALUE0
 }
 
 # ---------------------------------------------------------------------------------------
@@ -2464,23 +3270,23 @@ scom 0x800(0,1)C0050301143F {	# _P[0:1]
 # DPHY01_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0	0x008	0x8000c0080301143f
 # PHYE.PHYX.SYNTHX.D3SIDEA.PCX.REG08_L2
 scom 0x800(0,1)c0080301143f {	# _P[0:1]
-	bits	,	scom_data								,	expr			;	# must be >= 2...
-	48:63	,	0x0000									,	(def_is_sim)	;	# match dials
-#	need to fix...
-#	48:63	,	((ATTR_EFF_MEMCAL_INTERVAL/196605)+1)	,	any				;	# FAST_SIM_PER_CNTR=0
-#	48:63	,	((ATTR_EFF_MEMCAL_INTERVAL/765)+1)		,	any				;	# FAST_SIM_PER_CNTR=1
-	48:63	,	0x01D1									,	any				;	# 464 = 114ms @ 1600MHz
+	bits	,	scom_data								,	expr					;	# must be >= 2...
+#	0:47	,	0x000000000000							,	any						;	# reserved
+#	48:63	,	0x0000									,	(def_is_sim)			;	# match dials
+	48:63	,	((ATTR_EFF_MEMCAL_INTERVAL/196605)+1)	,	(def_FAST_SIM_PC==0)	;	# FAST_SIM_PER_CNTR=0
+	48:63	,	((ATTR_EFF_MEMCAL_INTERVAL/765)+1)		,	(def_FAST_SIM_PC==1)	;	# FAST_SIM_PER_CNTR=1
+#	48:63	,	0x01D1									,	any						;	# 464 = 114ms @ 1600MHz
 }
 
 
 # ---------------------------------------------------------------------------------------
 #  Periodic ZQcal configuration register		default=0
 #
-# DPHY01.DDRPHY_PC_PER_ZCAL_CONFIG_P0 from (alias spydef)
 # DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0		0x00F	0x8000c00f0301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG15_L2
 scom 0x8000C00F0301143F {	# Port0
 	bits	,	scom_data	,	expr										;
+#	0:47	,	0x000000000000,	any											;	# reserved
 	# PER_ZCAL_ENA_RANK for ranks [0:7]
 	48:51	,	0b1000		,	(ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 1)	;	# dimm0 = 1 rank
 	48:51	,	0b1100		,	(ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 2)	;	# dimm0 = 2 rank
@@ -2496,9 +3302,11 @@ scom 0x8000C00F0301143F {	# Port0
 	56:58	,	0b000		,	any											;
 	# START_PER_ZCAL
 	59		,	0b0			,	any											;
+#	60:63	,	0x0			,	any											;	reserved
 }
 scom 0x8001C00F0301143F {	# Port1
 	bits	,	scom_data	,	expr										;
+#	0:47	,	0x000000000000,	any											;	# reserved
 	# PER_ZCAL_ENA_RANK for ranks [0:7]
 	48:51	,	0b1000		,	(ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 1)	;	# dimm0 = 1 rank
 	48:51	,	0b1100		,	(ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 2)	;	# dimm0 = 2 rank
@@ -2514,6 +3322,7 @@ scom 0x8001C00F0301143F {	# Port1
 	56:58	,	0b000		,	any											;
 	# START_PER_ZCAL
 	59		,	0b0			,	any											;
+#	60:63	,	0x0			,	any											;	reserved
 }
 
 # ---------------------------------------------------------------------------------------
@@ -2535,51 +3344,66 @@ scom 0x8001C00F0301143F {	# Port1
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG09_L2
 scom 0x8000c0090301143f {
 	bits	,	scom_data								,	expr					;	# must be >= 2...
-#	fix needed from Anuwat to set the attribute value...
-#	48:63	,	((ATTR_EFF_ZQCAL_INTERVAL/196605)+1)	,	(SYS.ATTR_IS_SIMULATION==0)	;	# FAST_SIM_PER_CNTR=0
-#	48:63	,	((ATTR_EFF_ZQCAL_INTERVAL/765)+1)		,	any						;	# FAST_SIM_PER_CNTR=1
-	48:63	,	0x002E									,	any						;	# 46 = 11ms @ 1600MHz
+#	0:47	,	0x000000000000							,	any						;	# reserved
+	48:63	,	((ATTR_EFF_ZQCAL_INTERVAL/196605)+1)	,	(def_FAST_SIM_PC==0)	;	# FAST_SIM_PER_CNTR=0
+	48:63	,	((ATTR_EFF_ZQCAL_INTERVAL/765)+1)		,	(def_FAST_SIM_PC==1)	;	# FAST_SIM_PER_CNTR=1
+#	48:63	,	0x002E									,	any						;	# 46 = 11ms @ 1600MHz
 }
 
 # ---------------------------------------------------------------------------------------
-#  DPHY01 PC Power Down 1		default=0
+#  DPHY01 PC Power Down 1		default=0			!! need to set this?
 #
-# !! need to set this?
 # This register provides control of the power down modes of the DDR PHY.
 #
 # DPHY01_DDRPHY_PC_POWERDOWN_1_P0	0x010	0x8000c0100301143f
+#
+# asking Ken...
 
-
-# PC Rank Group Register
-# DDRPHY_PC_RANK_GROUP		PC 0x011
-# This register provides control of the rank groups.
-# ADDR_MIRROR_RP0_PRI
-# ADDR_MIRROR_RP0_SEC
-# ADDR_MIRROR_RP1_PRI
-# ADDR_MIRROR_RP1_SEC
-# ADDR_MIRROR_RP2_PRI
-# ADDR_MIRROR_RP2_SEC
-# ADDR_MIRROR_RP3_PRI
-# ADDR_MIRROR_RP3_SEC
-# RANK_GROUPING
-# ADDR_MIRROR_A3_A4
-# ADDR_MIRROR_A5_A6
-# ADDR_MIRROR_A7_A8
-# ADDR_MIRROR_A11_A13
-# ADDR_MIRROR_BA0_BA1
-# ADDR_MIRROR_BG0_BG1
-
+# ---------------------------------------------------------------------------------------
+# PC Rank Group Register		no need to set since using RDIMMs
+#
+# This register provides control of mirrored address bits. Mainly? used for
+# UDIMMs?
+#
+# DPHY01_DDRPHY_PC_RANK_GROUP_P0		0x11	0x8000c0110301143f
+# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG17_L2
+#scom 0x8000c0110301143f {
+#	bits	,	scom_data	,	expr		;
+#	0:47	,	0x000000000000,	any			;	# reserved
+#	48		,	0b0			,	any			;	# ADDR_MIRROR_RP0_PRI
+#	49		,	0b0			,	any			;	# ADDR_MIRROR_RP0_SEC
+#	50		,	0b0			,	any			;	# ADDR_MIRROR_RP1_PRI
+#	51		,	0b0			,	any			;	# ADDR_MIRROR_RP1_SEC
+#	52		,	0b0			,	any			;	# ADDR_MIRROR_RP2_PRI
+#	53		,	0b0			,	any			;	# ADDR_MIRROR_RP2_SEC
+#	54		,	0b0			,	any			;	# ADDR_MIRROR_RP3_PRI
+#	55		,	0b0			,	any			;	# ADDR_MIRROR_RP3_SEC
+#	56:57	,	0b0			,	any			;	# RANK_GROUPING
+#	58		,	0b0			,	any			;	# ADDR_MIRROR_A3_A4
+#	59		,	0b0			,	any			;	# ADDR_MIRROR_A5_A6
+#	60		,	0b0			,	any			;	# ADDR_MIRROR_A7_A8
+#	61		,	0b0			,	any			;	# ADDR_MIRROR_A11_A13
+#	62		,	0b0			,	any			;	# ADDR_MIRROR_BA0_BA1
+#	63		,	0b0			,	any			;	# ADDR_MIRROR_BG0_BG1
+#}
+# ---------------------------------------------------------------------------------------
 # PC Rank Group Extension Register
-# DDRPHY_PC_RANK_GROUP_EXT		0x035
-# ADDR_MIRROR_RP0_TER
-# ADDR_MIRROR_RP0_QUA
-# ADDR_MIRROR_RP1_TER
-# ADDR_MIRROR_RP1_QUA
-# ADDR_MIRROR_RP2_TER
-# ADDR_MIRROR_RP2_QUA
-# ADDR_MIRROR_RP3_TER
-# ADDR_MIRROR_RP3_QUA
-
+#
+# DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0	0x035		0x8000c0350301143f
+# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG53_L2
+#scom 0x8000c0350301143f {
+#	bits	,	scom_data	,	expr		;
+#	0:47	,	0x000000000000,	any			;	# reserved
+#	48		,	0b0			,	any			;	# ADDR_MIRROR_RP0_TER
+#	49		,	0b0			,	any			;	# ADDR_MIRROR_RP0_QUA
+#	50		,	0b0			,	any			;	# ADDR_MIRROR_RP1_TER
+#	51		,	0b0			,	any			;	# ADDR_MIRROR_RP1_QUA
+#	52		,	0b0			,	any			;	# ADDR_MIRROR_RP2_TER
+#	53		,	0b0			,	any			;	# ADDR_MIRROR_RP2_QUA
+#	54		,	0b0			,	any			;	# ADDR_MIRROR_RP3_TER
+#	55		,	0b0			,	any			;	# ADDR_MIRROR_RP3_QUA
+#	56:63	,	0x00		,	any			;	# reserved
+#}
 
 # ---------------------------------------------------------------------------------------
 # Rank pair 0 configuration register	default=0
@@ -2592,11 +3416,14 @@ scom 0x8000c0090301143f {
 # ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1]		CS, 255=invalid
 # ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1]	CS, 255=invalid
 #
-# DPHY01.DDRPHY_PC_RANK_PAIR0_P0 from (alias spydef)
 # DPHY01_DDRPHY_PC_RANK_PAIR0_P0		0x002	0x8000c0020301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG02_L2
 scom 0x8000C0020301143F {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
+#	possible way to simplify...
+#	48:51	,	((ATTR_EFF_PRIMARY_RANK_GROUP0[0]<<1) | 0x1)	,	(def_val_prg1_p1)	;	# P1_RP1_PRI = 9
+#	48:51	,	0b0000											,	any					;	# P1_RP1_PRI invalid
 	48:50	,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0])	,	(def_val_prg0_p0)	;	# P0_RP0_PRI
 	48:50	,	0b000								,	any					;	# P0_RP0_PRI
 	51		,	0b1									,	(def_val_prg0_p0)	;	# P0_RP0_PRI_V
@@ -2616,9 +3443,10 @@ scom 0x8000C0020301143F {
 }
 
 # -=-=-=-=-=-=-=-  PC_RANK_PAIR0  Port 1  -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
-# DPHY01.DDRPHY_PC_RANK_PAIR0_P1 from (alias spydef)
+# DPHY01.DDRPHY_PC_RANK_PAIR0_P1
 scom 0x8001C0020301143F {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
 	48:50	,	(ATTR_EFF_PRIMARY_RANK_GROUP0[1])	,	(def_val_prg0_p1)	;	# P1_RP0_PRI
 	48:50	,	0b000								,	any					;	# P1_RP0_PRI invalid
 	51		,	0b1									,	(def_val_prg0_p1)	;	# P1_RP0_PRI_V
@@ -2627,8 +3455,6 @@ scom 0x8001C0020301143F {
 	52:54	,	0b000								,	any					;	# P1_RP0_SEC invalid
 	55		,	0b1									,	(def_val_srg0_p1)	;	# P1_RP0_SEC_V
 	55		,	0b0									,	any					;	# P1_RP0_SEC_V invalid
-#	56:59	,	((ATTR_EFF_PRIMARY_RANK_GROUP1[1]<<1) | 0x1)	,	(def_val_prg1_p1)	;	# P1_RP1_PRI = 9
-#	56:59	,	0b0000											,	any					;	# P1_RP1_PRI invalid
  	56:58	,	(ATTR_EFF_PRIMARY_RANK_GROUP1[1])	,	(def_val_prg1_p1)	;	# P1_RP1_PRI
  	56:58	,	0b000								,	any					;	# P1_RP1_PRI invalid
  	59		,	0b1									,	(def_val_prg1_p1)	;	# P1_RP1_PRI_V
@@ -2648,9 +3474,10 @@ scom 0x8001C0020301143F {
 # ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1]		CS, 255=invalid
 # ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1]	CS, 255=invalid
 #
-# DPHY01.DDRPHY_PC_RANK_PAIR1_P0 from (alias spydef)
+# DPHY01.DDRPHY_PC_RANK_PAIR1_P0
 scom 0x8000C0030301143F {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
 	48:50	,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0])	,	(def_val_prg2_p0)	;	# P0_RP2_PRI
 	48:50	,	0b000								,	any					;	# P0_RP2_PRI invalid
 	51		,	0b1									,	(def_val_prg2_p0)	;	# P0_RP2_PRI_V
@@ -2670,9 +3497,10 @@ scom 0x8000C0030301143F {
 }
 
 # -=-=-=-=-=-=-=-  PC_RANK_PAIR1  Port 1  -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
-# DPHY01.DDRPHY_PC_RANK_PAIR1_P1 from (alias spydef)
+# DPHY01.DDRPHY_PC_RANK_PAIR1_P1
 scom 0x8001C0030301143F {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
 	48:50	,	(ATTR_EFF_PRIMARY_RANK_GROUP2[1])	,	(def_val_prg2_p1)	;	# P1_RP2_PRI
 	48:50	,	0b000								,	any					;	# P1_RP2_PRI invalid
 	51		,	0b1									,	(def_val_prg2_p1)	;	# P1_RP2_PRI_V
@@ -2704,6 +3532,7 @@ scom 0x8001C0030301143F {
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG48_L2
 scom 0x8000c0300301143f {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
  	48:50	,	(ATTR_EFF_TERTIARY_RANK_GROUP0[0])	,	(def_val_trg0_p0)	;	# P0_RP0_TER
 	48:50	,	0b000								,	any					;	# P0_RP0_TER invalid
  	51		,	0b1									,	(def_val_trg0_p0)	;	# P0_RP0_TER_V
@@ -2726,6 +3555,7 @@ scom 0x8000c0300301143f {
 # DPHY01.DDRPHY_PC_RANK_PAIR2_P1
 scom 0x8001c0300301143f {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
  	48:50	,	(ATTR_EFF_TERTIARY_RANK_GROUP0[1])	,	(def_val_trg0_p1)	;	# P1_RP0_TER
 	48:50	,	0b000								,	any					;	# P1_RP0_TER invalid
  	51		,	0b1									,	(def_val_trg0_p1)	;	# P1_RP0_TER_V
@@ -2757,6 +3587,7 @@ scom 0x8001c0300301143f {
 # PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG49_L2
 scom 0x8000c0310301143f {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
  	48:50	,	(ATTR_EFF_TERTIARY_RANK_GROUP2[0])	,	(def_val_trg2_p0)	;	# P0_RP2_TER
 	48:50	,	0b000								,	any					;	# P0_RP2_TER invalid
  	51		,	0b1									,	(def_val_trg2_p0)	;	# P0_RP2_TER_V
@@ -2779,6 +3610,7 @@ scom 0x8000c0310301143f {
 # DPHY01.DDRPHY_PC_RANK_PAIR3_P1
 scom 0x8001c0310301143f {
 	bits	,	scom_data							,	expr				;
+#	0:47	,	0x000000000000						,	any					;	# reserved
  	48:50	,	(ATTR_EFF_TERTIARY_RANK_GROUP2[1])	,	(def_val_trg2_p1)	;	# P1_RP2_TER
 	48:50	,	0b000								,	any					;	# P1_RP2_TER invalid
  	51		,	0b1									,	(def_val_trg2_p1)	;	# P1_RP2_TER_V
@@ -2800,18 +3632,31 @@ scom 0x8001c0310301143f {
 # ---------------------------------------------------------------------------------------
 # Read Control Configuration 0		default=0x0002
 #
-# DPHY01.DDRPHY_RC_CONFIG0_P0 from (alias spydef)
-# DPHY01.DDRPHY_RC_CONFIG0_P1 from (alias spydef)
+# DPHY01.DDRPHY_RC_CONFIG0_P0
+# DPHY01.DDRPHY_RC_CONFIG0_P1
+#
+# num of tCK cycles = 300 + [(PER_REPEAT_COUNT + 1) * 600]
 #
 # DPHY01_DDRPHY_RC_CONFIG0_P0		0x000	0x8000c8000301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG0_L2
 scom 0x800(0,1)C8000301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
-	# min GPO=5
+#	0:47	,	0x000000000000,	any				;	# reserved
+	#
+	# System_Delay = ( ( (ADR_DELAY - 64) +
+	# {wire delay from the PHY memory clock output to the DRAM module converted to units of 1/128th of a MEMINTCLKO clock cycle} +
+	# {delay of DQS at the memory module pin relative to memory clock at the memory module pin introduced by the memory module
+	# (that is, tDQSCK) converted to units of 1/128th of a MEMINTCLKO clock cycle} +
+	# {wire delay from the DRAM DQS output to the PHY converted to units of 1/128th of a MEMINTCLKO clock cycle}) / 128) +
+	# {number of pipeline stages in the addr/cmd path} +
+	# {number of pipeline stages in the read data path}
+	#
+	# min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN
+	# max GPO = 11 if in 2:1, 13 if in 4:1
 	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), 2:1 max=11, 4:1 max=13
-	52		,	0b0			,	any				;	# ADVANCE_RD_VALID
+	52		,	0b0			,	any				;	# ADVANCE_RD_VALID	ask Yuen
 	53		,	0b0			,	any				;	# ERS_MODE, reserved
-	54:56	,	0b000		,	any				;	# PER_REPEAT_COUNT
+	54:56	,	0b000		,	any				;	# PER_REPEAT_COUNT, (value+1)=num bits per peridic cal
 	57		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP0
 	58		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP1
 	59		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP2
@@ -2825,13 +3670,14 @@ scom 0x800(0,1)C8000301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # Read Control Configuration 1      default=0x0000
 #
-# DPHY01.DDRPHY_RC_CONFIG1_P0 from (alias spydef)
-# DPHY01.DDRPHY_RC_CONFIG1_P1 from (alias spydef)
+# DPHY01.DDRPHY_RC_CONFIG1_P0
+# DPHY01.DDRPHY_RC_CONFIG1_P1
 #
 # DPHY01_DDRPHY_RC_CONFIG1_P0       0x001   0x8000c8010301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.ITERATION_COUNT_L2
 scom 0x800(0,1)C8010301143F {	# _P[0:1]
 	bits	,	scom_data			;
+#	0:47	,	0x000000000000		;	# reserved
 	48:61	,	0b00000000000000	;	# OUTER_LOOP_CNT
 #	62:63	,	0b00				;	# reserved
 }
@@ -2839,14 +3685,15 @@ scom 0x800(0,1)C8010301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # Read Control Configuration 2      default=0x4008
 #
-# DPHY01.DDRPHY_RC_CONFIG2_P0 from (alias spydef)
-# DPHY01.DDRPHY_RC_CONFIG2_P1 from (alias spydef)
+# DPHY01.DDRPHY_RC_CONFIG2_P0
+# DPHY01.DDRPHY_RC_CONFIG2_P1
 #
 # DPHY01_DDRPHY_RC_CONFIG2_P0		0x002	0x8000c8020301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG2_L2
 scom 0x800(0,1)C8020301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
-	48:52	,	0b00000		,	(def_is_sim)	;	# CONSEQ_PASS	sim value
+#	0:47	,	0x000000000000,	any				;	# reserved
+#	48:52	,	0b00000		,	(def_is_sim)	;	# CONSEQ_PASS	sim value
 	48:52	,	0b00110		,	(def_is_bl8)	;	# CONSEQ_PASS	6 min for BL8
 	48:52	,	0b01100		,	any				;	# CONSEQ_PASS	12 min for BL4, or OTF
 #	53:56	,	0b0000		,	any				;	# reserved
@@ -2860,24 +3707,24 @@ scom 0x800(0,1)C8020301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # Read Control Configuration 3      default=0x0800
 #
-# DPHY01.DDRPHY_RC_CONFIG3_P0 from (alias spydef)
-# DPHY01.DDRPHY_RC_CONFIG3_P1 from (alias spydef)
+# DPHY01.DDRPHY_RC_CONFIG3_P0
+# DPHY01.DDRPHY_RC_CONFIG3_P1
 #
 # DPHY01_DDRPHY_RC_CONFIG3_P0		0x007	0x8000c8070301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG3_L2(0:6),PHYW.PHYX.SYNTHX.D3SIDEA.RCX.DQSDQ_ENUM_COUNT_L2
 scom 0x800(0,1)C8070301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	# FINE_CAL_STEP_SIZE (000=1/128, 001=1/64, 010=3/128, 011=1/32...)
 	48:50	,	0b000		,	any				;	# 1/128
 
 	# COARSE_CAL_STEP_SIZE same as above but 8-16 reserved, but when DIGITAL_EYE_EN=1
 	# in DFT_DIG_EYE register, 51:52 reserved, 53=DIGEYE_16_NOT_1, 54= DIGEYE_REFRESH
-	#51:54	,	0b0100		,	(def_is_sim)	;	# COARSE_CAL_STEP_SIZE = 4 = 5/128  # old 5/18
-	#51:54	,	0b1100		,	any				;	# COARSE_CAL_STEP_SIZE				# old 5/18
-	51:54	,	0b1010		,	(def_is_sim)	;	# COARSE_CAL_STEP_SIZE
-	51:54	,	0b0000		,	any				;	# COARSE_CAL_STEP_SIZE
+	51:54	,	0b1010		,	(def_is_sim)	;	# COARSE_CAL_STEP_SIZE	# old=4=5/128 (5/18)
+	51:54	,	0b0000		,	any				;	# COARSE_CAL_STEP_SIZE = 1/128
 	55:56	,	0b00		,	any				;	# DQ_SEL_QUAD
 	57:59	,	0b000		,	any				;	# DQ_SEL_LANE
+#	60:63	,	0b0000		,	any				;	# reserved
 }
 
 # ---------------------------------------------------------------------------------------
@@ -2889,19 +3736,23 @@ scom 0x800(0,1)C8070301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # SEQ Configuration 0 Register		default=0		!! need to review settings
 #
-# DPHY01.DDRPHY_SEQ_CONFIG0_P0 from (alias spydef)
-# DPHY01.DDRPHY_SEQ_CONFIG0_P1 from (alias spydef)
+# DPHY01.DDRPHY_SEQ_CONFIG0_P0
+# DPHY01.DDRPHY_SEQ_CONFIG0_P1
 #
 # DPHY01_DDRPHY_SEQ_CONFIG0_P0		CTL 0x002	0x8000c4020301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MPR_PATTERN_DATA_L2
 scom 0x800(0,1)C4020301143F {	# _P[0:1]
 	bits	,	scom_data		;
+#	0:47	,	0x000000000000	;	# reserved
 	48		,	0b0				;	# MPR_PATTERN_BIT
 	49		,	0b0				;	# TWO_CYCLE_ADDR_EN (must be set to 0), need 1 in sim ?  2N
 	50:53	,	0b0000			;	# MR_MASK_EN (mode register[0:3] mask during calibration)
-	54		,	0b0				;	# PARITY_DLY (only for DDR4, DDR3 don't care)
+	54		,	0b0				;	# DELAYED_PARITY (only for DDR4, DDR3 don't care)
 	55		,	0b0				;	# LRDIMM_CONTEXT
-#	56:63	,	0b00000000		;	# reserved
+	56		,	0b0				;	# FORCE_RESERVED
+	57		,	0b0				;	# HALT_ROTATION
+	58		,	0b0				;	# FORCE_MPR
+#	59:63	,	0b00000			;	# reserved
 }
 
 # ---------------------------------------------------------------------------------------
@@ -2962,30 +3813,26 @@ scom 0x800(0,1)C4020301143F {	# _P[0:1]
 # 2259 =	.8853ns 10.624 ns	14.16 ns	17			21.25 ns*
 # 3200 0.625ns
 #
-# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 from (alias spydef)
 # 	[01:23]					   [0:2] [0:1]
 # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0	CTL	0x012	0x8000c4120301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM0_L2
 scom 0x800(0,1)C4120301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr														;
+#	0:47	,	0x000000000000,	any															;	# reserved
 	# TMOD_CYCLES, DDR3=max(12nCK, 15ns), DDR4=max(24nCK, 15ns)
-#	48:51	,	0x7			,	(def_is_sim)		;	# match dials
- 	48:51	,	0x4			,	((CEN.ATTR_MSS_FREQ <= 2133) && (def_is_ddr3))					;	# DDR3 && < 2133, 2^4 = 16clks
- 	48:51	,	0x5			,	((CEN.ATTR_MSS_FREQ > 2133) && (def_is_ddr3))					;	# DDR3 && > 2133, 2^5 = 32clks
- 	48:51	,	0x5			,	((CEN.ATTR_MSS_FREQ < 3200) && (def_is_ddr4))					;	# DDR4 && < 3200, 2^5 = 32clks
+ 	48:51	,	0x4			,	((CEN.ATTR_MSS_FREQ <= 2133) && (def_is_ddr3))				;	# DDR3 && < 2133, 2^4 = 16clks
+ 	48:51	,	0x5			,	((CEN.ATTR_MSS_FREQ > 2133) && (def_is_ddr3))				;	# DDR3 && > 2133, 2^5 = 32clks
+ 	48:51	,	0x5			,	((CEN.ATTR_MSS_FREQ < 3200) && (def_is_ddr4))				;	# DDR4 && < 3200, 2^5 = 32clks
 	# TRCD_CYCLES
-#	52:55	,	0x7			,	(def_is_sim)												;	# match dials
 	52:55	,	0x4			,	((ATTR_EFF_DRAM_TRCD > 8) && (ATTR_EFF_DRAM_TRCD <= 16))	;	# 2^4 = 16 clks
 	52:55	,	0x3			,	(ATTR_EFF_DRAM_TRCD <= 8)									;	# 2^3 = 8 clks
 	52:55	,	0x5			,	(ATTR_EFF_DRAM_TRCD > 16)									;	# 2^5 = 32 clks
 	# TRP_CYCLES
-#	56:59	,	0x7			,	(def_is_sim)												;	# match dials
 	56:59	,	0x3			,	(ATTR_EFF_DRAM_TRP < 8)										;	# 2^3 = 8 clks
 	56:59	,	0x4			,	((ATTR_EFF_DRAM_TRP > 8) && (ATTR_EFF_DRAM_TRP <= 16))		;	# 2^4 = 16 clks
 	56:59	,	0x5			,	(ATTR_EFF_DRAM_TRP > 16)									;	# 2^5 = 32 clks
 	# TRFC_CYCLES, based on Gb density (512=90ns 1Gb=110ns 2Gb=160ns 4Gb=300ns 8Gb=350ns)
 	# ATTR_EFF_DRAM_TRFC in clocks = tRFC / clock
-#	60:63	,	0x7			,	(def_is_sim)												;	# match dials
 	60:63	,	0x6			,	((ATTR_EFF_DRAM_TRFC <= 64) && (ATTR_EFF_DRAM_TRFC > 32))	;	# 2^6 = 64 clks
 	60:63	,	0x7			,	((ATTR_EFF_DRAM_TRFC <= 128) && (ATTR_EFF_DRAM_TRFC > 64))	;	# 2^7 = 128 clks
 	60:63	,	0x8			,	((ATTR_EFF_DRAM_TRFC <= 256) && (ATTR_EFF_DRAM_TRFC > 128))	;	# 2^8 = 256 clks
@@ -2998,27 +3845,23 @@ scom 0x800(0,1)C4120301143F {	# _P[0:1]
 # Memory Timing Parameters to be used during calibration.  Each nibble is used as
 # exponent of 2, to calculate # of clock cycles.  Ex: TZQCS_CYCLES=6, 2^6 clocks
 #
-# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 from (alias spydef)
 # 	[01:23]					   [0:2] [0:1]
 # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0	CTL	0x013	0x8000c4130301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM1_L2
 scom 0x800(0,1)C4130301143F {	# _P[0:1]
-	bits	,	scom_data	,	expr										;
+	bits	,	scom_data	,	expr											;
+#	0:47	,	0x000000000000,	any												;	# reserved
 	# TZQINIT_CYCLES max(tZQINIT,tZQOPER)	DDR3=max(512nCK, 640ns)	DDR4=1024nCK
-#	48:51	,	0x7			,	(def_is_sim)								;	# match dials
  	48:51	,	0x9			,	((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600))	;	# DDR3 & freq <= 1600, 512 clks
  	48:51	,	0xA			,	((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600))	;	# DDR4 || freq > 1600, 1024 clks
 	# TZQCS_CYCLES		DDR3=max(64nCK, 80ns)	DDR4=128nCK
-#	52:55	,	0x7			,	(def_is_sim)								;	# match dials
  	52:55	,	0x6			,	((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600))	;	# DDR3 & freq <= 1600, 64 clks
  	52:55	,	0xA			,	((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600))	;	# DDR4 || freq > 1600, 128 clks
+# *Note: max values system dependent
 	# TWLDQSEN_CYCLES	DDR3/4=min(25nCK)*
-#	56:59	,	0x7			,	(def_is_sim)								;	# match dials
-	56:59	,	0x5			,	any											;	# 2^5 = 32 clks
+	56:59	,	0x5			,	any												;	# 2^5 = 32 clks
 	# TWLMRD_CYCLES		DDR3/4=min(40nCK)*
-#	60:63	,	0x7			,	(def_is_sim)								;	# match dials
-	60:63	,	0x6			,	any											;	# 2^6 = 64 clks
-# *Note: max values system dependent
+	60:63	,	0x6			,	any												;	# 2^6 = 64 clks
 }
 
 # ---------------------------------------------------------------------------------------
@@ -3027,16 +3870,15 @@ scom 0x800(0,1)C4130301143F {	# _P[0:1]
 # Memory Timing Parameters to be used during calibration.  Each nibble is used as
 # exponent of 2, to calculate # of clock cycles.  Ex: TRCS_CYCLES=0, 2^0 clocks
 #
-# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 from (alias spydef)
 # 	[01:23]					   [0:2] [0:1]
 # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0	CTL	0x014	0x8000c4140301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM2_L2
-# DPHY01.DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 from (alias spydef)
 #
 # TODTLON_OFF_CYCLES	DDR3=CWL+AL-2	DDR4 if 2tCK, CWL+AL-3
 # define def_tODTL_DDR3_AL0	=	def_tODTL_DDR3 - ATTR_EFF_DRAM_CL	;
 # scom 0x800(0,1)C4140301143F {	# _P[0:1]
 # 	bits	,	scom_data	,	ATTR_EFF_DRAM_GEN	,	ATTR_EFF_DRAM_AL	,	expr						;
+#	0:47	,	0x000000000000,	any					,	any					,	any							;	# reserved
 # 	#--------------- DDR3 -------------------------------------------------------------------------
 # 	48:51	,	0x3			,	1	,	0	,	(def_tODTL_DDR3_AL0 <= 8)									;	#  8 clks
 # 	48:51	,	0x4			,	1	,	0	,	((def_tODTL_DDR3_AL0 <= 16) && (def_tODTL_DDR3_AL0 > 8))	;	# 16 clks
@@ -3057,20 +3899,19 @@ scom 0x800(0,1)C4130301143F {	# _P[0:1]
 #  	48:51	,	0x6			,	2	,	any	,	((def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32))			;	# 64 clks
 # 	48:51	,	0x0			,	any	,	any	,	any															;	#  0 clks
 # 	# TRC_CYCLES
-# 	52:55	,	0x7			,	(def_is_sim)														;	# match dials
 # 	52:55	,	0x7			,	((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128))			;	# 2^7 = 128 clks
 # 	52:55	,	0x6			,	((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64))				;	# 2^6 = 64 clks
 # 	52:55	,	0x5			,	((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32))				;	# 2^5 = 32 clks
 # 	52:55	,	0x4			,	((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16))				;	# 2^4 = 16 clks
 # 	52:55	,	0x3			,	(ATTR_EFF_DRAM_TRC <= 8)											;	# 2^3 = 8 clks
 # 	# TMRSC_CYCLES	for RLDRAMs, set to 0 for everything else
-# 	56:59	,	0x7			,	(def_is_sim)														;	# match dials
 # 	56:59	,	0x0			,	any																	;
 # #	60:63	,	0x0			,	any																	;	# reserved
 # }
 
 scom 0x800(0,1)C4140301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr																;
+#	0:47	,	0x000000000000,	any																	;	# reserved
 	# TODTLON_OFF_CYCLES	DDR3=CWL+AL-2	DDR4 if 2tCK, CWL+AL-3
 	#--------------- DDR3 -------------------------------------------------------------------------
 	48:51	,	0x3			,	((def_is_ddr3) && (def_tODTL_DDR3 <= 8))							;	#  8 clks
@@ -3084,19 +3925,19 @@ scom 0x800(0,1)C4140301143F {	# _P[0:1]
 	48:51	,	0x6			,	((def_is_ddr4) && (def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32))	;	# 64 clks
 	48:51	,	0x0			,	any																	;	#  0 clks
 	# TRC_CYCLES
-	52:55	,	0x7			,	(def_is_sim)														;	# match dials
+#	52:55	,	0x7			,	(def_is_sim)														;	# match dials
 	52:55	,	0x7			,	((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128))			;	# 2^7 = 128 clks
 	52:55	,	0x6			,	((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64))				;	# 2^6 = 64 clks
 	52:55	,	0x5			,	((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32))				;	# 2^5 = 32 clks
 	52:55	,	0x4			,	((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16))				;	# 2^4 = 16 clks
 	52:55	,	0x3			,	(ATTR_EFF_DRAM_TRC <= 8)											;	# 2^3 = 8 clks
 	# TMRSC_CYCLES	for RLDRAMs, set to 0 for everything else
-	56:59	,	0x7			,	(def_is_sim)														;	# match dials
+#	56:59	,	0x7			,	(def_is_sim)														;	# match dials
 	56:59	,	0x0			,	any																	;
 #	60:63	,	0x0			,	any																	;	# reserved
 }
 # ---------------------------------------------------------------------------------------
-# SEQ Low Power Termination Address		default=0xFFFF		!! need to set this?
+# SEQ Low Power Termination Address		default=0xFFFF
 #
 # bit positions and mapping of the Address/BA/BG pins in DDR3/DDR4 of the low power
 # termination address{2-4}
@@ -3118,6 +3959,7 @@ scom 0x800(0,1)C4140301143F {	# _P[0:1]
 #DPHY01_DDRPHY_SEQ_LPT_ADDR2_P0		0x017	0x8000c4170301143f
 #scom 0x8000c4170301143f {
 #	bits	,	scom_data		;
+#	0:47	,	0x000000000000	;	# reserved
 #	48:63	,	0xFFFF			;	# LPT_ADDR2
 #}
 
@@ -3130,15 +3972,22 @@ scom 0x800(0,1)C4140301143F {	# _P[0:1]
 # DPHY01_DDRPHY_WC_CONFIG0_P0	0x000	0x8000cc000301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG0_L2
 scom 0x800(0,1)CC000301143F {	# _P[0:1]
-	bits	,	scom_data	,	expr			;
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+# !! need to review
 	# = 12 + max(tWLDQSEN-tMOD,tWLO+tWLOE) + (longest DQS wire delay in CKs) + (longest DQ wire delay in CKs)
+	48:55	,	0x10				,	any										;	# TWLO_TWLOE = 16	(same as DD0)
 	# @ 1600, = 12 + max(13,3) + ldqs + ldq = 25 + ldqs + ldq
-	48:55	,	0x10		,	(def_is_sim)	;	# TWLO_TWLOE = 16
-	48:55	,	0x1B		,	any				;	# TWLO_TWLOE = 27
-	#48:55	,	(25+ldqs+ldq),	< 1866			;	# TWLO_TWLOE
-	56		,	0b1			,	any				;	# WL_ONE_DQS_PULSE = enable
-	57:62	,	0b000000	,	any				;	# FW_WR_RD
-	63		,	0b0			,	any				;	# CUSTOM_INIT_WRITE
+	#48:55	,	0x1B				,	any										;	# TWLO_TWLOE = 27
+	#48:55	,	(25+ldqs+ldq)		,	(CEN.ATTR_MSS_FREQ > 1460)				;	# TWLO_TWLOE	(> 1333)
+	56		,	0b1					,	any										;	# WL_ONE_DQS_PULSE = enable
+	# FW_WR_RD = max(tWTR+8,AL+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0
+	57:62	,	0b000000			,	(def_is_sim)							;
+	57:62	,	0b010001			,	any										;	# same as DD0, right aligned here, 17d
+	57:62	,	(def_TWTR_PLUS_8)	,	(def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL)	;	# TWTR + 8 >= TRTP + AL
+	57:62	,	(def_TRTP_PLUS_AL)	,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
+
+	63		,	0b0					,	any										;	# CUSTOM_INIT_WRITE
 }
 # ---------------------------------------------------------------------------------------
 # Write control logic configuration 1	default=0x2350	addr=0xCC01
@@ -3147,6 +3996,8 @@ scom 0x800(0,1)CC000301143F {	# _P[0:1]
 # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG1_L2
 scom 0x800(0,1)CC010301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
+# !! need to review
 	48:51	,	0b1100		,	(def_is_sim)	;	# BIG_STEP = 12	(changed from default for SIM)
 	48:51	,	0b0010		,	any				;	# BIG_STEP = 2	(default)
 	52:54	,	0b001		,	any				;	# SMALL_STEP = 1	(!! recommend setting to 0)
@@ -3157,12 +4008,11 @@ scom 0x800(0,1)CC010301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # Write control logic configuration 2	default=0x5440
 #
-# DPHY01.DDRPHY_WC_CONFIG2_P0 from (alias spydef)
-#
 # DPHY01_DDRPHY_WC_CONFIG2_P0	0x002	0x8000cc020301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG2_L2
 scom 0x800(0,1)CC020301143F {	# _P[0:1]
 	bits	,	scom_data			,	expr			;
+#	0:47	,	0x000000000000		,	any				;	# reserved
 	48:51	,	0x3					,	(def_is_sim)	;	# NUM_VALID_SAMPLES = 3 (changed from defaults)
 	48:51	,	0x5					,	any				;	# NUM_VALID_SAMPLES = 5 (defaults)
 
@@ -3170,6 +4020,13 @@ scom 0x800(0,1)CC020301143F {	# _P[0:1]
 	52:57	,	(def_TWTR_PLUS_8)	,	(def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL)	;	# TWTR + 8 >= TRTP + AL
 	52:57	,	(def_TRTP_PLUS_AL)	,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
 
+# RL=CL+AL, WL=CWL+AL	!! Need to fix
+# = CL + 2tCK + tCCD/x   x=1 if
+# Read to write = RL + tCCD + 2tCK - WL (in DDR3 JEDEC for Read BL8 to Write BL8)
+# Read to write = RL + tCCD/2 + 2tCK - WL (in DDR3 JEDEC for Read BC4 to Write BC4/BL8 OTF)
+#	52:57	,	def_fw_rd_wr,		,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
+
+
 #	58:62	,	0b00000				,	any				;	# reserved
 
 	# DP18_WR_DELAY_VALUE_{0-23}_RP{0-3}_REG are reset to 0 at the start of WL cal for rank pair 0 when '1'
@@ -3179,14 +4036,14 @@ scom 0x800(0,1)CC020301143F {	# _P[0:1]
 # ---------------------------------------------------------------------------------------
 # Write control logic configuration 3	default=0x01F8
 #
-# DPHY01.DDRPHY_WC_CONFIG3_P0 from (alias spydef)
-#
 # DPHY01_DDRPHY_WC_CONFIG3_P0	0x005	0x8000cc050301143f
 # PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG3_L2
 scom 0x800(0,1)CC050301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr				;
+#	0:47	,	0x000000000000,	any					;	# reserved
 	48		,	0b1			,	(def_is_ddr4)		;	# if DDR4, drive DQ pins in DATA_BIT_ENABLE1
 	48		,	0b0			,	(def_not_ddr4)		;	# if not DDR4, set to 0
+# !! need to review
 	# MRS_CMD_DQ_ON determines the WL_per_DRAM_addr time.
 	# WL_per_DRAM_addr = 10 + MRS_CMD_DQ_ON 	in 2:1 mode
 	# WL_per_DRAM_addr = 18 + 2 * MRS_CMD_DQ_ON in 4:1 mode
@@ -3197,7 +4054,7 @@ scom 0x800(0,1)CC050301143F {	# _P[0:1]
 }
 
 # ---------------------------------------------------------------------------------------
-# DP18 Data Bit Direction 0		defaults to 0's		!! need to set this?
+# DP18 Data Bit Direction 0		defaults to 0's		no longer need to set this.
 #
 # 1 indicates output only
 #
@@ -3209,20 +4066,17 @@ scom 0x800(0,1)CC050301143F {	# _P[0:1]
 #
 # '1'b indicates DP18 bit is an output and continously drives out a signal
 #
-# DPHY01.DDRPHY_DP18_DATA_BIT_DIR1_P0_0 from (alias spydef)
 # DPHY01_DDRPHY_DP18_DATA_BIT_DIR1_P0_0		0x003	0x800000030301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DIR1_L2
 #scom 0x800(0,1)(00,04,08,0C,10)030301143f {	# DIR1_P[0:1]_[0:4]
 scom 0x800(0,1)3C030301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 	bits	,	scom_data	,	expr			;
-	48:55	,	0b00000000	,	any				;	# DATA_BIT_DIR_16_23
+#	0:47	,	0x000000000000,	any				;	# reserved
+#	48:54	,	0b0000000	,	any				;	# reserved... used to be DATA_BIT_DIR_16_23
+	55		,	0b0			,	any				;	# ATEST_MUX_CTL_EN
 	56		,	0b0			,	any				;	# WL_ADVANCE_DISABLE
 	57		,	0b0			,	any				;	# DISABLE_PING_PONG
-# !recent
-#	58		,	0b0			,	(def_is_sim)	;	# DELAY_PING_PONG_HALF, to match dials
 	58		,	0b1			,	any				;	# DELAY_PING_PONG_HALF, must be 1 from definition
-# !recent
-#	59		,	0b0			,	(def_is_sim)	;	# ADVANCE_PING_PONG. to match dials
 	59		,	0b1			,	any				;	# ADVANCE_PING_PONG. must be 1 from definition
 	60:63	,	0b0000		,	any				;	# ATEST_MUX_CTL[0:3]
 }
@@ -3241,69 +4095,78 @@ scom 0x800(0,1)3C030301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 # P2_4{56:63}, P3_1{56:63} = 0xFF if spares enabled else 0x00
 # all others (P2_[0:3], P3_0, P3_[2:4]) = 0xFFFF
 #
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0		0x800000000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2		0x800008000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3		0x80000C000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0		0x800100000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3		0x80010C000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4		0x800110000301143f
-#
 #   [01:23]					 [0:1]_[0:1]_[0:4]
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0		0x000	0x800000000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2				0x800008000301143f
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3				0x80000C000301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_ENABLE0_L2
-# ENABLE0_(P0_0, P0_2, P0_3, P2_0, P2_2, P2_3)
+#
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0		0x800000000301143f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2		0x800008000301143f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3		0x80000C000301143f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_0		0x800000000301183f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_2		0x800008000301183f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_3		0x80000C000301183f
 scom 0x800(000,008,00C)000301143f {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:63	,	0xFFFF		,	(def_valid_p0)	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0x0000		,	any				;
 }
+
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0		0x800100000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3		0x80010C000301143f
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4		0x800110000301143f
-# ENABLE0_(P1_0, P1_3, P1_4, P3_0, P3_3, P3_4)
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_0		0x800100000301183f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_3		0x80010C000301183f
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_4		0x800110000301183f
 scom 0x800(100,10C,110)000301143f {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:63	,	0xFFFF		,	(def_valid_p1)	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0x0000		,	any				;
 }
 
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4		0x800010000301143f
-scom 0x800(010)000301143f {
+scom 0x800010000301143f {
 	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
 	48:63	,	0xFFFF		,	((def_is_mba01) && (def_valid_p0))					;	# enable DATA_BIT_ENABLE_0_15
-# ENABLE0_(P2_4)
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_4		0x800010000301183f
 	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p0) && (def_has_spare))	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0xFF00		,	((def_is_mba23) && (def_valid_p0) && (def_no_spare))	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0x0000		,	any													;
 }
+
 # DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1		0x800104000301143f
-scom 0x800(104)000301143f {
+scom 0x800104000301143f {
 	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
 	48:63	,	0xFFFF		,	((def_is_mba01) && (def_valid_p1))					;	# enable DATA_BIT_ENABLE_0_15
-# ENABLE0_(P3_1)
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_1		0x800104000301183f
 	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p1) && (def_has_spare))	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0xFF00		,	((def_is_mba23) && (def_valid_p1) && (def_no_spare))	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0x0000		,	any													;
 }
 
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_1		0x800004000301183f
-scom 0x800(004)000301143f {
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1		0x800004000301143f
+scom 0x800004000301143f {
 	bits	,	scom_data	,	expr												;
-	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p0))					;	# enable DATA_BIT_ENABLE_0_15
-# ENABLE0_(P0_1)
+#	0:47	,	0x000000000000,	any													;	# reserved
 	48:63	,	0xFFFF		,	((def_is_mba01) && (def_valid_p0) && (def_has_spare))	;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0xFF00		,	((def_is_mba01) && (def_valid_p0) && (def_no_spare))	;	# enable DATA_BIT_ENABLE_0_15
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_1		0x800004000301183f
+	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p0))					;	# enable DATA_BIT_ENABLE_0_15
 	48:63	,	0x0000		,	any													;
 }
-# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2		0x800108000301183f
-scom 0x800(108)000301143f {						# DATA_BIT_ENABLE_0_15
+
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2		0x800108000301143f
+scom 0x800108000301143f {
 	bits	,	scom_data	,	expr												;	# spare = 8_15
-	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p1))					;	# P3_2
-# ENABLE0_(P1_2)
+#	0:47	,	0x000000000000,	any													;	# reserved
 	48:63	,	0xFFFF		,	((def_is_mba01) && (def_valid_p1) && (def_has_spare))	;	# P1_2, enable spare if CDIMM
 	48:63	,	0xFF00		,	((def_is_mba01) && (def_valid_p1) && (def_no_spare))	;	# P1_2, disable spare
+# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2		0x800108000301183f
+	48:63	,	0xFFFF		,	((def_is_mba23) && (def_valid_p1))					;	# P3_2
+	48:63	,	0x0000		,	any													;
 }
 
 # ---------------------------------------------------------------------------------------
@@ -3316,6 +4179,7 @@ scom 0x800(108)000301143f {						# DATA_BIT_ENABLE_0_15
 #scom 0x800(0,1)(00,04,08,0C,10)010301143f {	# ENABLE1_P[0:1]_[0:4]
 # scom 0x800(0,1)3C010301143f {	# ENABLE0_P[0:1]_[0:4] via broadcast
 # 	bits	,	scom_data		;
+#	0:47	,	0x000000000000	;	# reserved
 # 	48:55	,	0b00000000		;	# data_bit_enable_16_23
 # 	56		,	0b0				;	# DFT_FORCE_OUTPUTS
 # 	57		,	0b0				;	# DFT_PRBS7_GEN_EN
@@ -3330,152 +4194,12 @@ scom 0x800(108)000301143f {						# DATA_BIT_ENABLE_0_15
 #---------------------------------------------------------------------------
 # DP18 Data Bit Disable 0	default=0		per Rank Group/Pair
 #
-# This register is used to disable each of the 24 pins on the DP18. During calibration
-# operations, the hardware sets the bit in this register which corresponds to a pin on the
-# DP18 which failed a calibration step. This register indicates which DQ pins on the DP18
-# failed a calibration step. This register does not indicate which calibration step failed.
-#
-# !! does the reset clear these 2 registers?  does the initfile need to set these?
-# ATTR_MSS_BAD_BIT_MASK[port][dimm][rank][byte]
-# PHY logic registers only care about bits on a rank pair/port, so dimm will not be needed.
-#
-# get rank pair via ATTR_EFF_PRIMARY_RANK_GROUP0[0],sec,ter,qua then 'or' the byte together to form
-# the value needed for register
-#
-# NOTE:  No need to disable spare dram bits since it should not be enabled.
-# port P0_1, P0_4,
-#	56:63	,	0xFF		,	((def_no_spare) && (def_is_mba01))	;	# disable spare bits
-#
-#define def_bb_p0_rp0_d = ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2;
-#define def_bb_p0_rp0_r = ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03;
-#define SYS.ATTR_SCRATCH_UINT8_1 = ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2;
-#define SYS.ATTR_SCRATCH_UINT8_2 = ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03;
-# define def_bb_p0_rp1_d = ATTR_EFF_PRIMARY_RANK_GROUP1[0] >> 2;
-# define def_bb_p0_rp1_r = ATTR_EFF_PRIMARY_RANK_GROUP1[0] & 0x03;
-# define def_bb_p0_rp2_d = ATTR_EFF_PRIMARY_RANK_GROUP2[0] >> 2;
-# define def_bb_p0_rp2_r = ATTR_EFF_PRIMARY_RANK_GROUP2[0] & 0x03;
-# define def_bb_p0_rp3_d = ATTR_EFF_PRIMARY_RANK_GROUP3[0] >> 2;
-# define def_bb_p0_rp3_r = ATTR_EFF_PRIMARY_RANK_GROUP3[0] & 0x03;
+# Procedure function to set this register, pulling data from the SPD.
+# 1 = disable dq bit
 #
 # DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0		0x07C	0x8000007c0301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_L2
-scom 0x8000007C0301143f {	# DATA_BIT_DISABLE0_RP0_P0_0
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-#	48:55	,	(ATTR_MSS_BAD_BIT_MASK[0][(ATTR_EFF_PRIMARY_RANK_GROUP0[0] >> 2)][(ATTR_EFF_PRIMARY_RANK_GROUP0[0] & 0x03)][0]	,	any	;
-#	48:55	,	(ATTR_MSS_BAD_BIT_MASK[0][def_bb_p0_rp0_d][def_bb_p0_rp0_r][0])	,	any	;	# expr for byte0
-#	48:55	,	0x55		,	(ATTR_MSS_BAD_BIT_MASK[0][SYS.ATTR_SCRATCH_UINT8_1][0][0] == 0x04)
-#	48:55	,	0x55		,	(ATTR_EFF_DIMM_SIZE[0][SYS.ATTR_SCRATCH_UINT8_1] == 0x00);
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-	#56:63	,	(ATTR_MSS_BAD_BIT_MASK[0][def_bb_p0_rp0_d][def_bb_p0_rp0_r][1])	,	any	;	# expr for byte1
-}
-scom 0x8000047C0301143f {	# DATA_BIT_DISABLE0_RP0_P0_1
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-}
-scom 0x8000087C0301143f {	# DATA_BIT_DISABLE0_RP0_P0_2
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-}
-scom 0x80000C7C0301143f {	# DATA_BIT_DISABLE0_RP0_P0_3
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-}
-scom 0x8000107C0301143f {	# DATA_BIT_DISABLE0_RP0_P0_4
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP0[0]==255)	;	# invalid rank pair0
-}
-
-# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0		0x17C	0x8000017c0301143f
-scom 0x8000017C0301143f {	# DATA_BIT_DISABLE0_RP1_P0_0
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-}
-scom 0x8000057C0301143f {	# DATA_BIT_DISABLE0_RP1_P0_1
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-}
-scom 0x8000097C0301143f {	# DATA_BIT_DISABLE0_RP1_P0_2
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-}
-scom 0x80000D7C0301143f {	# DATA_BIT_DISABLE0_RP1_P0_3
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-}
-scom 0x8000117C0301143f {	# DATA_BIT_DISABLE0_RP1_P0_4
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP1[0]==255)	;	# invalid rank pair1
-}
-
-# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0		0x27C	0x8000027c0301143f
-scom 0x8000027C0301143f {	# DATA_BIT_DISABLE0_RP2_P0_0
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-}
-scom 0x8000067C0301143f {	# DATA_BIT_DISABLE0_RP2_P0_1
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-}
-scom 0x80000A7C0301143f {	# DATA_BIT_DISABLE0_RP2_P0_2
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-}
-scom 0x80000E7C0301143f {	# DATA_BIT_DISABLE0_RP2_P0_3
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-}
-scom 0x8000127C0301143f {	# DATA_BIT_DISABLE0_RP2_P0_4
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP2[0]==255)	;	# invalid rank pair2
-}
-
-# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0		0x37C	0x8000037c0301143f
-scom 0x8000037C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_0
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-}
-scom 0x8000077C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_1
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-}
-scom 0x80000B7C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_2
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-}
-scom 0x80000F7C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_3
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-}
-scom 0x8000137C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_4
-	bits	,	scom_data	,	expr									;	# bits 0:15
-	48:55	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-	56:63	,	0xFF		,	(ATTR_EFF_PRIMARY_RANK_GROUP3[0]==255)	;	# invalid rank pair3
-}
-
-# Port1, MBA01 = instance 2
-#	56:63	,	0xFF		,	((def_no_spare) && (def_is_mba01))	;	# disable spare bits
-# Port1, MBA23 = instance 1
-#	56:63	,	0xFF		,	((def_no_spare) && (def_is_mba23))	;	# disable spare bits
-
+#
 #---------------------------------------------------------------------------
 # DP18 Data Bit Disable 1	default=0
 #
@@ -3483,34 +4207,22 @@ scom 0x8000137C0301143f {	# DATA_BIT_DISABLE0_RP3_P0_4
 #
 # DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_0		0x07D	0x8000007d0301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_L2
-#scom 0x80007D000301143f {	# DATA_BIT_DISABLE1_RP0_P0_0
-#	bits	,	scom_data	,	expr		;	# bits 16:23
-#	48:55	,	0x00		,	any			;	# ATTR_MSS_BAD_BIT_MASK[2][2][8][10]
-#	56:63	,	0x00		,	any			;	# reserved
-#}
 
 #---------------------------------------------------------------------------
 #  ADR BIT ENABLE P[0:1] ADR[0:3]	default=0
 #
-# Note: refined this so that bits 12:15 not used in ADR[0:1],
-# and bits 14:15 not used in ADR[2:3].
+# Turn off of deconfigured the ports handled in a clean up procedure
 #
 # DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0		0x000	0x800040000301143f
-# DPHY01.DDRPHY_ADR_BIT_ENABLE_P0_ADR0 from (alias spydef)
-#scom 0x800(0,1)(40,44,48,4c)000301143f {	# _P[0:1]_ADR[0:3]
-# scom 0x800(0,1)7C000301143F {	# _P[0:1]_ADR[0:3] via broadcast
-# 	bits	,	scom_data		;
-# 	48:63	,	0xFFFF			;	# enable all ADR bits
-# }
-
-# need to turn off if deconfiguring the ports, should be handled in a
-# clean up procedure
+# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.P_REG_A_00_L2
 scom 0x800(040,044,140,144)000301143F {	# _P[0:1]_ADR[0:1]
+#	0:47	,	0x000000000000	;	# reserved
 	bits	,	scom_data		;
 	48:63	,	0xFFF0			;	# bits 12:15 not used in ADR[0:1]
 }
 scom 0x800(048,04C,148,14C)000301143F {	# _P[0:1]_ADR[2:3]
 	bits	,	scom_data		;
+#	0:47	,	0x000000000000	;	# reserved
 	48:63	,	0xFFFC			;	# 14:15 not used in ADR[2:3]
 }
 
@@ -3538,98 +4250,438 @@ scom 0x800(048,04C,148,14C)000301143F {	# _P[0:1]_ADR[2:3]
 # 49:55 = value0, 57:63 = value1,
 # 0x40 = 64 (for single data rate), 0x20 = 32 (for double data rate)
 #
-# -------------   Port 0   ---------------------------------------------
 #  [01:23]			[0:7] [0:1] [0:3]
-# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0		0x004	0x800040090301143f
+# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0		0x004-00B	0x800040040301143f
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_09_L2
-scom 0x800040090301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 10:11, clk0_p/n
-}
-# DPHY01.DDRPHY_ADR_DELAY5_P0_ADR2 from (alias spydef)
-# DPHY23_DDRPHY_ADR_DELAY5_P0_ADR2
-scom 0x800048090301143F {
-	# -------------   Port 0 & 2   -------------------------------------
-	bits	,	scom_data	,	expr			;
-	# for port 0 & port 2, lane 10:11, Port0=clk1_n/p, Port2=clk0_n/p
-	48:63	,	0x4040		,	any				;	# for both mba01 & mba23
-	#48:63	,	0x4040		,	((def_is_mba01) || (def_is_mba23))	;
-}
-# DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2 from (alias spydef)
-scom 0x800048060301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 4:5, clk2_p/n
-}
-# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2 from (alias spydef)
-scom 0x8000480A0301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 12:13, clk3_n/p
-}
-
-# -------------   Port 2   ---------------------------------------------
-# DPHY23_DDRPHY_ADR_DELAY3_P0_ADR0
-scom 0x800040070301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 6:7, clk1_p/n
-	48:63	,	0x0000		,	any				;	# mba01
-}
-#DPHY23_DDRPHY_ADR_DELAY1_P0_ADR3
-scom 0x80004C050301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 2:3, clk2_p/n
-	48:63	,	0x0000		,	any				;	# mba01
-}
-# DPHY23_DDRPHY_ADR_DELAY4_P0_ADR0
-scom 0x800040080301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 8:9, clk3_p/n
-	48:63	,	0x0000		,	any				;	# mba01
-}
-
-# -------------   Port 1   ---------------------------------------------
-# DPHY01.DDRPHY_ADR_DELAY1_P1_ADR3 from (alias spydef)
-# DPHY23_DDRPHY_ADR_DELAY1_P1_ADR3
-scom 0x80014C050301143F {
-	# -------------   Port 1 & 3   -------------------------------------
-	bits	,	scom_data	,	expr			;
-	# lane 2:3, Port1=clk0_n/p, Port3=clk0_n/p
-	48:63	,	0x4040		,	any				;	# for mba01 & mba23
-	#48:63	,	0x4040		,	((def_is_mba01) || (def_is_mba23))	;
-}
-# DPHY01.DDRPHY_ADR_DELAY4_P1_ADR2 from (alias spydef)
-scom 0x800148080301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 8:9, clk1_p/n
-}
-# DPHY01.DDRPHY_ADR_DELAY0_P1_ADR0 from (alias spydef)
-scom 0x800140040301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 0:1, clk2_n/p
-}
-# DPHY01.DDRPHY_ADR_DELAY1_P1_ADR0 from (alias spydef)
-scom 0x800140050301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba01)	;	# lane 2:3, clk3_n/p
-}
-
-# -------------   Port 3   ---------------------------------------------
-# DPHY23_DDRPHY_ADR_DELAY6_P1_ADR2
-scom 0x8001480A0301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 12:13, clk1_n/p
-	48:63	,	0x0000		,	any				;	#
-}
-# DPHY23_DDRPHY_ADR_DELAY5_P1_ADR0
-scom 0x800140090301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 10:11, clk2_p/n
-	48:63	,	0x0000		,	any				;	#
-}
-# DPHY23_DDRPHY_ADR_DELAY5_P1_ADR2
-scom 0x800148090301143F {
-	bits	,	scom_data	,	expr			;
-	48:63	,	0x4040		,	(def_is_mba23)	;	# lane 10:11, clk3_n/p
-	48:63	,	0x0000		,	any				;	#
+#====================================================================================
+#   PORT 0 / 2 
+#====================================================================================
+#-- Port 0/2  ADR 0 ------------------------------------------------------------
+scom 0x800040040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0])	,	(def_is_mba01)	;	# P0 L0	, A1_CKE1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0])	,	(def_is_mba01)	;	# P0 L1	, A0_CS3n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0])	,	(def_is_mba23)	;	# P2 L0	, C0_CS0n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0])		,	(def_is_mba23)	;	# P2 L1	, C_A3
+}
+scom 0x800040050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0])	,	(def_is_mba01)	;	# P0 L2	, A1_CKE0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0])	,	(def_is_mba01)	;	# P0 L3	, A0_ODT0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0])	,	(def_is_mba23)	;	# P2 L2	, C1_CS3n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0])		,	(def_is_mba23)	;	# P2 L3	, C_RASn
+}
+scom 0x800040060301143F {	# DPHY01_DDRPHY_ADR_DELAY2_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0])		,	(def_is_mba01)	;	# P0 L4	, A_A15
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_PAR[0])			,	(def_is_mba01)	;	# P0 L5	, A_PAR
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0])		,	(def_is_mba23)	;	# P2 L4	, C_A12
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0])		,	(def_is_mba23)	;	# P2 L5	, C_A7
+}
+scom 0x800040070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0])	,	(def_is_mba01)	;	# P0 L6	, A0_CKE1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0])	,	(def_is_mba01)	;	# P0 L7	, A0_CS1n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba23)	;	# P2 L6	, C0_CLK1_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba23)	;	# P2 L7	, C0_CLK1_n
+}
+scom 0x800040080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0])	,	(def_is_mba01)	;	# P0 L8	, A0_CKE0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0])	,	(def_is_mba01)	;	# P0 L9	, A1_ODT0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0])		,	(def_is_mba23)	;	# P2 L8	, C1_CLK1_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0])		,	(def_is_mba23)	;	# P2 L9	, C1_CLK1_n
+}
+scom 0x800040090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba01)	;	# P0 L10, A0_CLK0_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba01)	;	# P0 L11, A0_CLK0_n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0])	,	(def_is_mba23)	;	# P2 L10, C1_CKE2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0])	,	(def_is_mba23)	;	# P2 L11, C0_CKE2
+}
+#-- Port 0/2  ADR 1 ------------------------------------------------------------
+scom 0x800044040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[0])	,	(def_is_mba01)	;	# P0 L0	, A0_CS0n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0])	,	(def_is_mba01)	;	# P0 L1	, A1_CKE3
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0])		,	(def_is_mba23)	;	# P2 L0	, C_BA2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[0])	,	(def_is_mba23)	;	# P2 L1	, C1_CKE1
+}
+scom 0x800044050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0])	,	(def_is_mba01)	;	# P0 L2	, A1_ODT1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0])		,	(def_is_mba01)	;	# P0 L3	, A_A2
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0])	,	(def_is_mba23)	;	# P2 L2	, C0_ODT1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0])		,	(def_is_mba23)	;	# P2 L3	, C_WEn
+}
+scom 0x800044060301143F {	# DPHY01_DDRPHY_ADR_DELAY2_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0])		,	(def_is_mba01)	;	# P0 L4	, A_A6
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0])		,	(def_is_mba01)	;	# P0 L5	, A_A1
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[0])	,	(def_is_mba23)	;	# P2 L4	, C0_CS1n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0])		,	(def_is_mba23)	;	# P2 L5	, C_A11
+}
+scom 0x800044070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0])		,	(def_is_mba01)	;	# P0 L6	, A_A14
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[0])	,	(def_is_mba01)	;	# P0 L7	, A0_CKE2
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0])	,	(def_is_mba23)	;	# P2 L6	, C0_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0])	,	(def_is_mba23)	;	# P2 L7	, C0_CS2n
+}
+scom 0x800044080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0])	,	(def_is_mba01)	;	# P0 L8	, A1_CS2n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[0])	,	(def_is_mba01)	;	# P0 L9	, A1_CKE2
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[0])	,	(def_is_mba23)	;	# P2 L8	, C0_ODT0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[0])		,	(def_is_mba23)	;	# P2 L9	, C_A8
+}
+scom 0x800044090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0])		,	(def_is_mba01)	;	# P0 L10, A_A4
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[0])		,	(def_is_mba01)	;	# P0 L11, A_RASn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0])		,	(def_is_mba23)	;	# P2 L10, C_A5
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0])	,	(def_is_mba23)	;	# P2 L11, C1_CS0n
+}
+#-- Port 0/2  ADR 2 ------------------------------------------------------------
+scom 0x800048040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[0])		,	(def_is_mba01)	;	# P0 L0	, A_A12
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0])		,	(def_is_mba01)	;	# P0 L1	, A_A0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[0])		,	(def_is_mba23)	;	# P2 L0	, C_A1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[0])		,	(def_is_mba23)	;	# P2 L1	, C_A6
+}
+scom 0x800048050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[0])	,	(def_is_mba01)	;	# P0 L2	, A0_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[0])	,	(def_is_mba01)	;	# P0 L3	, A1_CS3n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0])		,	(def_is_mba23)	;	# P2 L2	, C_A13
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[0])	,	(def_is_mba23)	;	# P2 L3	, C0_CKE0
+}
+scom 0x800048060301143F {	# DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0])		,	(def_is_mba01)	;	# P0 L4	, A1_CLK0_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0])		,	(def_is_mba01)	;	# P0 L5	, A1_CLK0_n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[0])	,	(def_is_mba23)	;	# P2 L4	, C1_ODT0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0])	,	(def_is_mba23)	;	# P2 L5	, C1_CS1n
+}
+scom 0x800048070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[0])	,	(def_is_mba01)	;	# P0 L6	, A0_ODT1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[0])	,	(def_is_mba01)	;	# P0 L7	, A1_CS0n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[0])	,	(def_is_mba23)	;	# P2 L6	, C0_CKE1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[0])	,	(def_is_mba23)	;	# P2 L7	, C1_CKE0
+}
+scom 0x800048080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[0])	,	(def_is_mba01)	;	# P0 L8	, A1_CS1n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0])		,	(def_is_mba01)	;	# P0 L9	, A_A10
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[0])		,	(def_is_mba23)	;	# P2 L8	, C_A0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0])		,	(def_is_mba23)	;	# P2 L9	, C_BA1
+}
+scom 0x800048090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L12, A0_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L13, A0_CLK1_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L12, C0_CLK0_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L13, C0_CLK0_p
+}
+scom 0x8000480A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L12, A1_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[0])		,	(def_is_mba01)	;	# P0 L13, A1_CLK1_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[0])	,	(def_is_mba23)	;	# P2 L12, C1_CS2n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[0])		,	(def_is_mba23)	;	# P2 L13, C_A10
+}
+#-- Port 0/2  ADR 3 ------------------------------------------------------------
+scom 0x80004C040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[0])		,	(def_is_mba01)	;	# P0 L0	, A_A13
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0])		,	(def_is_mba01)	;	# P0 L1	, A_BA0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_PAR[0])			,	(def_is_mba23)	;	# P2 L0	, C_PAR
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[0])	,	(def_is_mba23)	;	# P2 L1	, C1_ODT1
+}
+scom 0x80004C050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[0])		,	(def_is_mba01)	;	# P0 L2	, A_WEn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[0])	,	(def_is_mba01)	;	# P0 L3	, A0_CS2n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L2	, C1_CLK0_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[0])		,	(def_is_mba23)	;	# P2 L3	, C1_CLK0_n
+}
+scom 0x80004C060301143F {	# DPHY01.DDRPHY_ADR_DELAY2_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[0])		,	(def_is_mba01)	;	# P0 L4	, A_BA1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0])		,	(def_is_mba01)	;	# P0 L5	, A_CASn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[0])		,	(def_is_mba23)	;	# P2 L4	, C_A14
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0])		,	(def_is_mba23)	;	# P2 L5	, C_A9
+}
+scom 0x80004C070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[0])		,	(def_is_mba01)	;	# P0 L6	, A_A5
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[0])		,	(def_is_mba01)	;	# P0 L7	, A_A3
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0])			,	(def_is_mba23)	;	# P2 L6	, C_ACTn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[0])		,	(def_is_mba23)	;	# P2 L7	, C_A2
+}
+scom 0x80004C080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[0])		,	(def_is_mba01)	;	# P0 L8	, A_BA2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[0])		,	(def_is_mba01)	;	# P0 L9	, A_A11
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[0])	,	(def_is_mba23)	;	# P2 L8	, C1_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[0])		,	(def_is_mba23)	;	# P2 L9	, C_A15
+}
+scom 0x80004C090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[0])		,	(def_is_mba01)	;	# P0 L12, A_A7
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[0])			,	(def_is_mba01)	;	# P0 L13, A_ACTn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[0])		,	(def_is_mba23)	;	# P2 L12, C_BA0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[0])		,	(def_is_mba23)	;	# P2 L13, C_CASn
+}
+scom 0x80004C0A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0])		,	(def_is_mba01)	;	# P0 L12, A_A9
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[0])		,	(def_is_mba01)	;	# P0 L13, A_A8
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[0])		,	(def_is_mba23)	;	# P2 L12, C_A4
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[0])	,	(def_is_mba23)	;	# P2 L13, C0_CS3n
+}
+#====================================================================================
+#   PORT 1 / 3 
+#====================================================================================
+#-- Port 1/3  ADR 0------------------------------------------------------------
+scom 0x800140040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1])		,	(def_is_mba01)	;	# P1 L0	, B1_CLK0_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1])		,	(def_is_mba01)	;	# P1 L1	, B1_CLK0_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1])	,	(def_is_mba23)	;	# P3 L0	, D1_CKE1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1])		,	(def_is_mba23)	;	# P3 L1	, D_BA2
+}
+scom 0x800140050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1])		,	(def_is_mba01)	;	# P1 L2	, B1_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1])		,	(def_is_mba01)	;	# P1 L3	, B1_CLK1_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1])		,	(def_is_mba23)	;	# P3 L2	, D_A1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1])		,	(def_is_mba23)	;	# P3 L3	, D_A5
+}
+scom 0x800140060301143F {	# DPHY01_DDRPHY_ADR_DELAY2_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1])	,	(def_is_mba01)	;	# P1 L4	, B0_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1])	,	(def_is_mba01)	;	# P1 L5	, B0_CS3n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1])		,	(def_is_mba23)	;	# P3 L4	, D_A12
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1])		,	(def_is_mba23)	;	# P3 L5	, D_BA0
+}
+scom 0x800140070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0[1])		,	(def_is_mba01)	;	# P1 L6	, B_BA0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1])	,	(def_is_mba01)	;	# P1 L7	, B1_ODT1
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1])	,	(def_is_mba23)	;	# P3 L6	, D1_CKE2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1])	,	(def_is_mba23)	;	# P3 L7	, D1_CS1n
+}
+scom 0x800140080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1])	,	(def_is_mba01)	;	# P1 L8	, B1_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1])		,	(def_is_mba01)	;	# P1 L9	, B_A15
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1])	,	(def_is_mba23)	;	# P3 L8	, D0_CKE0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1])	,	(def_is_mba23)	;	# P3 L9	, D0_CS2n
+}
+scom 0x800140090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P1_ADR0
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1])	,	(def_is_mba01)	;	# P1 L10, B1_CS2n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1])	,	(def_is_mba01)	;	# P1 L11, B0_CKE1
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1])		,	(def_is_mba23)	;	# P3 L10, D1_CLK0_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0[1])		,	(def_is_mba23)	;	# P3 L11, D1_CLK0_n
+}
+#-- Port 1/3  ADR 1 ------------------------------------------------------------
+scom 0x800144040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1])	,	(def_is_mba01)	;	# P1 L0	, B0_CKE2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1])		,	(def_is_mba01)	;	# P1 L1	, B_A7
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1])		,	(def_is_mba23)	;	# P3 L0	, D_A8
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1])		,	(def_is_mba23)	;	# P3 L1	, D_A13
+}
+scom 0x800144050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1])		,	(def_is_mba01)	;	# P1 L2	, B_A10
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1[1])	,	(def_is_mba01)	;	# P1 L3	, B1_CKE1
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1])	,	(def_is_mba23)	;	# P3 L2	, D0_ODT1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_PAR[1])			,	(def_is_mba23)	;	# P3 L3	, D_PAR
+}
+scom 0x800144060301143F {	# DPHY01_DDRPHY_ADR_DELAY2_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1])	,	(def_is_mba01)	;	# P1 L4	, B0_CS1n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8[1])		,	(def_is_mba01)	;	# P1 L5	, B_A8
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1])	,	(def_is_mba23)	;	# P3 L4	, D1_CS0n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1])		,	(def_is_mba23)	;	# P3 L5	, D_A11
+}
+scom 0x800144070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1])		,	(def_is_mba01)	;	# P1 L6	, B_A6
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1])	,	(def_is_mba01)	;	# P1 L7	, B1_CS3n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1[1])	,	(def_is_mba23)	;	# P3 L6	, D0_CKE1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1])		,	(def_is_mba23)	;	# P3 L7	, D_WEn
+}
+scom 0x800144080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1])		,	(def_is_mba01)	;	# P1 L8	, B_A4
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1[1])	,	(def_is_mba01)	;	# P1 L9	, B1_CS1n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3[1])	,	(def_is_mba23)	;	# P3 L8	, D0_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1])	,	(def_is_mba23)	;	# P3 L9	, D1_ODT0
+}
+scom 0x800144090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P1_ADR1
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1[1])		,	(def_is_mba01)	;	# P1 L10, B_A1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1])		,	(def_is_mba01)	;	# P1 L11, B_BA1
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1])		,	(def_is_mba23)	;	# P3 L10, D_RASn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1[1])	,	(def_is_mba23)	;	# P3 L11, D0_CS1n
+}
+#-- Port 1/3  ADR 2 ------------------------------------------------------------
+scom 0x800148040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2[1])	,	(def_is_mba01)	;	# P1 L0	, B0_CS2n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1])	,	(def_is_mba01)	;	# P1 L1	, B0_ODT0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1])	,	(def_is_mba23)	;	# P3 L0	, D0_CS0n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10[1])		,	(def_is_mba23)	;	# P3 L1	, D_A10
+}
+scom 0x800148050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN[1])		,	(def_is_mba01)	;	# P1 L2	, B_WEn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1])		,	(def_is_mba01)	;	# P1 L3	, B_A2
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4[1])		,	(def_is_mba23)	;	# P3 L2	, D_A4
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3[1])	,	(def_is_mba23)	;	# P3 L3	, D1_CS3n
+}
+scom 0x800148060301143F {	# DPHY01.DDRPHY_ADR_DELAY2_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1[1])	,	(def_is_mba01)	;	# P1 L4	, B0_ODT1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0[1])	,	(def_is_mba01)	;	# P1 L5	, B0_CS0n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1])			,	(def_is_mba23)	;	# P3 L4	, D_ACTn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1])		,	(def_is_mba23)	;	# P3 L5	, D_A9
+}
+scom 0x800148070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1])		,	(def_is_mba01)	;	# P1 L6	, B_A3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1])		,	(def_is_mba01)	;	# P1 L7	, B_A0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3[1])	,	(def_is_mba23)	;	# P3 L6	, D1_CKE3
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1])	,	(def_is_mba23)	;	# P3 L7	, D1_CKE0
+}
+scom 0x800148080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1])		,	(def_is_mba01)	;	# P1 L8	, B0_CLK1_p
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1])		,	(def_is_mba01)	;	# P1 L9	, B0_CLK1_n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3[1])	,	(def_is_mba23)	;	# P3 L8	, D0_CS3n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2[1])		,	(def_is_mba23)	;	# P3 L9	, D_A2
+}
+scom 0x800148090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1])		,	(def_is_mba01)	;	# P1 L10, B_CASn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0[1])	,	(def_is_mba01)	;	# P1 L11, B1_CS0n
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1])		,	(def_is_mba23)	;	# P3 L10, D1_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1[1])		,	(def_is_mba23)	;	# P3 L11, D1_CLK1_p
+}
+scom 0x8001480A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P1_ADR2
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0[1])	,	(def_is_mba01)	;	# P1 L12, B1_CKE0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12[1])		,	(def_is_mba01)	;	# P1 L13, B_A12
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1])		,	(def_is_mba23)	;	# P3 L12, D0_CLK1_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1[1])		,	(def_is_mba23)	;	# P3 L13, D0_CLK1_p
+}
+#-- Port 1/3  ADR 3 ------------------------------------------------------------
+scom 0x80014C040301143F {	# DPHY01_DDRPHY_ADR_DELAY0_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11[1])		,	(def_is_mba01)	;	# P1 L0	, B_A11
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0[1])	,	(def_is_mba01)	;	# P1 L1	, B0_CKE0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2[1])	,	(def_is_mba23)	;	# P3 L0	, D1_CS2n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0[1])	,	(def_is_mba23)	;	# P3 L1	, D0_ODT0
+}
+scom 0x80014C050301143F {	# DPHY01_DDRPHY_ADR_DELAY1_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1])		,	(def_is_mba01)	;	# P1 L2	, B0_CLK0_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1])		,	(def_is_mba01)	;	# P1 L3	, B0_CLK0_p
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1])		,	(def_is_mba23)	;	# P3 L2	, D0_CLK0_n
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0[1])		,	(def_is_mba23)	;	# P3 L3	, D0_CLK0_p
+}
+scom 0x80014C060301143F {	# DPHY01.DDRPHY_ADR_DELAY2_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13[1])		,	(def_is_mba01)	;	# P1 L4	, B_A13
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1])		,	(def_is_mba01)	;	# P1 L5	, B_A14
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6[1])		,	(def_is_mba23)	;	# P3 L4	, D_A6
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1[1])	,	(def_is_mba23)	;	# P3 L5	, D1_ODT1
+}
+scom 0x80014C070301143F {	# DPHY01_DDRPHY_ADR_DELAY3_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2[1])	,	(def_is_mba01)	;	# P1 L6	, B1_CKE2
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0[1])	,	(def_is_mba01)	;	# P1 L7	, B1_ODT0
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0[1])		,	(def_is_mba23)	;	# P3 L6	, D_A0
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN[1])		,	(def_is_mba23)	;	# P3 L7	, D_CASn
+}
+scom 0x80014C080301143F {	# DPHY01_DDRPHY_ADR_DELAY4_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9[1])		,	(def_is_mba01)	;	# P1 L8	, B_A9
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2[1])		,	(def_is_mba01)	;	# P1 L9	, B_BA2
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14[1])		,	(def_is_mba23)	;	# P3 L8	, D_A14
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3[1])		,	(def_is_mba23)	;	# P3 L9	, D_A3
+}
+scom 0x80014C090301143F {	# DPHY01_DDRPHY_ADR_DELAY5_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN[1])		,	(def_is_mba01)	;	# P1 L10, B_RASn
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_ACTN[1])			,	(def_is_mba01)	;	# P1 L11, B_ACTn
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7[1])		,	(def_is_mba23)	;	# P3 L10, D_A7
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15[1])		,	(def_is_mba23)	;	# P3 L11, D_A15
+}
+scom 0x80014C0A0301143F {	# DPHY01.DDRPHY_ADR_DELAY6_P1_ADR3
+	bits	,	scom_data			,	expr									;
+#	0:47	,	0x000000000000		,	any										;	# reserved
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5[1])		,	(def_is_mba01)	;	# P1 L12, B_A5
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M_PAR[1])			,	(def_is_mba01)	;	# P1 L13, B_PAR
+	48:55	,	(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1[1])		,	(def_is_mba23)	;	# P3 L12, D_BA1
+	56:63	,	(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2[1])	,	(def_is_mba23)	;	# P3 L13, D0_CKE2
 }
 
 #================================================================================
@@ -3645,60 +4697,70 @@ scom 0x800148090301143F {
 # PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_01_L2
 scom 0x800040010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0x04		,	(def_is_mba01)	;	# lane 10:11(clk0)
 	# -------------   Port 2   -------------------------------------
 	# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0
 	48:55	,	0x18		,	(def_is_mba23)	;	# lane 6:7(clk1), 8:9(clk3)
+#	56:63	,	0x00		,	any				;	# reserved
 }
-# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 from (alias spydef)
+# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2
 scom 0x800048010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0x26		,	(def_is_mba01)	;	# lane 4:5(clk2), 10:11(clk1), 12:13(clk3)
 	# -------------   Port 2   -------------------------------------
 	# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2
 	48:55	,	0x04		,	(def_is_mba23)	;	# lane 10:11(clk0)
+#	56:63	,	0x00		,	any				;	# reserved
 }
 
 # -------------   Port 2   ---------------------------------------------
 # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3
 scom 0x80004C010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0x40		,	(def_is_mba23)	;	# lane 2:3(clk2)
 	48:55	,	0x00		,	any				;	# for mba01
+#	56:63	,	0x00		,	any				;	# reserved
 }
 
 # -------------   Port 1   ---------------------------------------------
-# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 from (alias spydef)
+# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0
 scom 0x800140010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0xC0		,	(def_is_mba01)	;	# lane 0:1(clk2), 2:3(clk3)
 	# -------------   Port 3   -------------------------------------
 	# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0
 	48:55	,	0x04		,	(def_is_mba23)	;	# lane 10:11(clk2)
+#	56:63	,	0x00		,	any				;	# reserved
 }
-# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 from (alias spydef)
+# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2
 scom 0x800148010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0x08		,	(def_is_mba01)	;	# lane 8:9(clk1)
 	# -------------   Port 3   -------------------------------------
 	# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2
 	48:55	,	0x06		,	(def_is_mba23)	;	# lane 10:11(clk3), 12:13(clk1)
+#	56:63	,	0x00		,	any				;	# reserved
 }
-# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 from (alias spydef)
+# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3
 scom 0x80014C010301143F {
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48:55	,	0x40		,	(def_is_mba01)	;	# lane 2:3(clk0)
 	# -------------   Port 3   -------------------------------------
 	# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3
 	48:55	,	0x40		,	(def_is_mba23)	;	# lane 2:3(clk0)
+#	56:63	,	0x00		,	any				;	# reserved
 }
 
 #	!! need updates to these clock registers from PHY / SIM team
 # set to 0x8070, reset seq sets it to 0x8024
 #---------------------------------------------------------------------------------------
-#   ADR SYSCLK settings		default=0x8074
-#
-# DPHY01.DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 from (alias spydef)
+#	ADR SYSCLK settings		default=0x8074
 #
 # Controls the circuit which aligns the internal SysClk to the incoming dphy_nclk clock.
 #
@@ -3707,45 +4769,63 @@ scom 0x80014C010301143F {
 #scom 0x800(0,1)(80,84)320301143F {	# _P[0:1]_ADR32S[0:1]
 scom 0x800(0,1)BC320301143F {		# _P[0:1]_ADR32S[0:1] via broadcast
 	bits	,	scom_data	,	expr			;
-	48		,	0b0			,	(def_is_sim)	;	# made to match dials
+#	0:47	,	0x000000000000,	any				;	# reserved
+# old dials value = 0x0080
 	48		,	0b1			,	any				;	# ADR32_SYSCLK_ENABLE
 
 	49:55	,	0b0000000	,	any				;	# ADR32_SYSCLK_ROT_OVERRIDE
 
-	56		,	0b1			,	(def_is_sim)	;	# made to match dials
 	56		,	0b0			,	any				;	# ADR32_SYSCLK_ROT_OVERRIDE_EN
 
-	57		,	0b0			,	(def_is_sim)	;	# made to match dials
 	57		,	0b1			,	any				;	# ADR32_SYSCLK_PHASE_ALIGN_RESET
 
-	58		,	0b0			,	(def_is_sim)	;	# made to match dials
 	58		,	0b1			,	any				;	# ADR32_SYSCLK_PHASE_CNTL_EN
 
-	59		,	0b0			,	(def_is_sim)	;	# made to match dials
 	59		,	0b1			,	any				;	# ADR32_SYSCLK_PHASE_DEFAULT_EN
 
 	60		,	0b0			,	any				;	# ADR32_SYSCLK_POS_EDGE_ALIGN
-	61		,	0b0			,	any				;	# ADR32_CONTINUOUS_UPDATE
+# recent 7/3
+	61		,	0b1			,	any				;	# ADR32_CONTINUOUS_UPDATE
 	62:63	,	0b00		,	any				;	# CE0DLTVCC, must be '00'b
 }
 
 # ---------------------------------------------------------------------------------------
-# DPHY01.DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 from (alias spydef)
+#	ADR WRClk Phase Rotator Offset Value		default=0
 #
-# !!NOTE different depending on EC level
+# !! NOTE different depending on EC level
 #
 # ADR Phase Rotator Static Offset value used to determine the
 # Phase of the WrClk with respect to SysClk. Adjusts for race
 # condition between combinatorial logic for WrClk to SysClk.
 #
-# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_33_L2
 #	[01:23]										[0:1]	[0:1]
 # DPHY01_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0		0x033	0x800080330301143f
+# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_33_L2
+# 0x800080330301143F  0x800084330301143F  0x800180330301143F  0x800184330301143F
 #scom 0x800(0,1)(80,84)330301143F {	# _P[0:1]_ADR32S[0:1]
 scom 0x800(0,1)BC330301143F {		# _P[0:1]_ADR32S[0:1] via broadcast
-	bits	,	scom_data				,	expr			;	# !!NOTE different depending on EC level
-	48:55	,	def_ADR32_TSYS_WRCLK	,	any				;	# ADR32_TSYS_WRCLK	for sim set to 0x60
-#	56:63	,	0x00					,	any				;	# reserved
+	bits	,	scom_data	,	expr						;
+#	0:47	,	0x000000000000,	any							;	# reserved
+#	48		,	0b0			,	any							;	# reserved
+	# !! NOTE different depending on EC level, system voltage too?
+	# value in the scom_data field is right aligned
+	48:55	,	0x60		,	(def_is_sim)				;	# ADR32_TSYS_WRCLK	sim set to 0x60
+# below is for fast process parts
+#	48:55	,	0x15		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (21)
+#	48:55	,	0x19		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (25)
+#	48:55	,	0x1E		,	any							;	# 1866 Mbps (30)
+# group below is for most parts process...
+##	48:55	,	0x22		,	(CEN.ATTR_MSS_FREQ < 1191)	;	# 1066 Mbps, 120
+#	48:55	,	0x22		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (34)
+#	48:55	,	0x28		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (40)
+#	48:55	,	0x2F		,	any							;	# 1866 Mbps (47)
+# below is for slow process parts
+# 	48:55	,	0x2D		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (45)
+# 	48:55	,	0x35		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (53)
+# 	48:55	,	0x3E		,	any							;	# 1866 Mbps (62)
+#-------- debug -----------------------------
+ 	48:55	,	0x70		,	any							;
+#	56:63	,	0x00		,	any							;	# reserved
 }
 
 #  ---------------------------------------------------------------------------------------
@@ -3753,7 +4833,7 @@ scom 0x800(0,1)BC330301143F {		# _P[0:1]_ADR32S[0:1] via broadcast
 #  ---------------------------------------------------------------------------------------
 # DPHY01.DDRPHY_DP18_WRCLK_PR_P0_0 		default=0
 #
-# !!NOTE different depending on EC level
+# !! NOTE different depending on EC level
 #
 # DP18 Phase Rotator Static Offset value used to
 # determine the Phase of the WrClk with respect to SysClk.
@@ -3763,18 +4843,34 @@ scom 0x800(0,1)BC330301143F {		# _P[0:1]_ADR32S[0:1] via broadcast
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_WRCLK_PR_L2
 #scom 0x800(0,1)(00,04,08,0C,10)740301143F {	#_P[0:1]_[0:4]
 scom 0x800(0,1)3C740301143F {					#_P[0:1]_[0:4] via broadcast
-	bits	,	scom_data			,	expr			;	 # !!NOTE different depending on EC level
-#	48		,	0b0					,	any				;	# reserved
-#	below yields 0x3000 in register instead of 0x6000 if not right aligned.
-#	49:55	,	0b1100000			,	(def_is_sim)	;	# DP18_TSYS_WRCLK	# for sim set to 0x60
-	49:55	,	def_DP18_TSYS_WRCLK	,	any				;	# DP18_TSYS_WRCLK
-#	56:63	,	0x00				,	any				;	# reserved
+	bits	,	scom_data	,	expr						;
+#	0:47	,	0x000000000000,	any							;	# reserved
+#	48		,	0b0			,	any							;	# reserved
+	# !! NOTE different depending on EC level
+	# value in the scom_data field is right aligned
+	48:55	,	0x60		,	(def_is_sim)				;	# DP18_TSYS_WRCLK	sim set to 0x60
+# below is for fast process parts
+#	48:55	,	0x14		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (20)
+#	48:55	,	0x18		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (24)
+#	48:55	,	0x1C		,	any							;	# 1866 Mbps (28)
+# group below is for most parts process...
+##	48:55	,	0x78		,	(CEN.ATTR_MSS_FREQ < 1191)	;	# 1066 Mbps
+#	48:55	,	0x20		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (32)
+#	48:55	,	0x27		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (39)
+#	48:55	,	0x2D		,	any							;	# 1866 Mbps (45)
+# below is for slow process parts
+#	48:55	,	0x2C		,	(CEN.ATTR_MSS_FREQ < 1458)	;	# 1333 Mbps, and 1066 (44)
+#	48:55	,	0x35		,	(CEN.ATTR_MSS_FREQ < 1724)	;	# 1600 Mbps (53)
+#	48:55	,	0x3E		,	any							;	# 1866 Mbps (62)
+#-------- debug -----------------------------
+ 	48:55	,	0x6B		,	any							;
+#	56:63	,	0x00		,	any							;	# reserved
 }
 
 #  ---------------------------------------------------------------------------------------
 #  ---     DP18 SYSCLK_PR P[0:1]_[0:4]   Phase Rotator   ---------------------------
 #  ---------------------------------------------------------------------------------------
-# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 from (alias spydef)		default=0x8070
+# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0		default=0x8070
 #
 # to Align bang-bang
 #
@@ -3790,6 +4886,7 @@ scom 0x800(0,1)3C740301143F {					#_P[0:1]_[0:4] via broadcast
 #scom 0x800(0,1)(00,04,08,0C,10)070301143F {	#_P[0:1]_[0:4]
 scom 0x800(0,1)3C070301143F {					#_P[0:1]_[0:4] via broadcast
 	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
 	48		,	0b1			,	any				;	# DP18_SYSCLK_ENABLE
 	49:55	,	0b0000000	,	any				;	# DP18_SYSCLK_ROT_OVERRIDE
 
@@ -3821,8 +4918,66 @@ scom 0x800(0,1)3C070301143F {					#_P[0:1]_[0:4] via broadcast
 #  These are settings for the read and write clock enables of the rank pair for
 #  x4 & x8 DRAM devices with and without spare DRAMs.
 #
+#  Configuration Requirements:
+#  1) If bit 49, 50, or 51 are set, either bit 48 or 52 must also be set.
+#  2) If bit 52 is set, then bit 49 or 53 must also be set unless bit 52 was only set to satisfy requirement 1.
+#  3) If bit 55 is set, then bit 50, 54, or 56 must also be set.
+#  4) If bit 56 is set, then bit 51, 55, or 57 must also be set unless bit 56 was only set to satisfy requirement 3.
+#
+#  [X:Y] represent DP18 lanes(24)
+#  lanes 0:15 used for dq bits
+#  lanes 16:23 used for dqs signal pairs (16:17, 18:19, 20:21, 22:23)
+#
+#						if x4 & no swizzle		if x8 and no swizzle
+#  quad0 = dq[0:3]		clk16 = dqs[16:17]		clk16 = dqs[16:17]
+#  quad1 = dq[4:7]		clk18 = dqs[18:19]		clk16 = dqs[16:17]
+#  quad2 = dq[8:11]		clk20 = dqs[20:21]		clk20 = dqs[20:21]
+#  quad3 = dq[12:15]	clk22 = dqs[22:23]		clk20 = dqs[20:21]
+#
+#  or another way to look at it...
+#
+#  for x4:
+#  dqs lane pairs	16/17 18/19 20/21 22/23
+#  dq quad nibbles 	  0	    1	  2		3		// no swizzle
+#					  1		0	  2		3		// swizzle lane pairs 16/17 with 18/19
+#					  0		1	  3		2		// swizzle lane pairs 20/21 with 22/23
+#					  1		0	  3		2		// swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23
+#
+#  for x8:
+#  dqs lane pairs	16/17 18/19 20/21 22/23
+#  dq quad nibbles 	 0:1   n/a   2:3   n/a		// no swizzle
+#					 n/a   0:1   2:3   n/a		// swizzle lane pairs 16/17 with 18/19
+#					 0:1   n/a   n/a   2:3		// swizzle lane pairs 20/21 with 22/23
+#					 n/a   0:1   n/a   2:3		// swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23
+#
+#  quadx_clk#      16     18    20    22
+#  quad#	    0 1 2 3   0 1  2 3   2 3
+#       ----------------------------------
+#       bits	0 1 2 3   4 5  6 7   8 9  10 11 (10:15 unused)
+#       ==============================================================
+#     possible spare (x4)
+#       0x8640  1 0 0 0   0 1  1 0   0 1  0 0  = x4 no-swizzle, 			q0=16, q1=18, q2=20, q3=22
+#       0x4A40  0 1 0 0   1 0  1 0   0 1  0 0  = x4 swizzle quad0/1,		q0=18, q1=16, q2=20, q3=22
+#       0x8580  1 0 0 0   0 1  0 1   1 0  0 0  = x4 swizzle quad2/3,		q0=16, q1=18, q2=22, q3=20
+#       0x4980  0 1 0 0   1 0  0 1   1 0  0 0  = x4 swizzle quad0/1 & 2/3,	q0=18, q1=16, q2=22, q3=20
+#
+#	  no spare (x4)
+#       0x8400  1 0 0 0   0 1  0 0   0 0  0 0  = x4 no-swizzle,				q0=16, q1=18, q2=n/a, q3=n/a
+#       0x4800  0 1 0 0   1 0  0 0   0 0  0 0  = x4 swizzle quad0/1,		q0=18, q1=16, q2=n/a, q3=n/a
+#
+#	  possible spare (x8)
+#       0xC300  1 1 0 0   0 0  1 1   0 0  0 0  = x8 no-swizzle,				q0:1=16, q2:3=20
+#       0x0F00  0 0 0 0   1 1  1 1   0 0  0 0  = x8 swizzle quad0/1,		q0:1=18, q2:3=20
+#       0xC0C0  1 1 0 0   0 0  0 0   1 1  0 0  = x8 swizzle quad2/3,		q0:1=16, q2:3=22
+#       0x0CC0  0 0 0 0   1 1  0 0   1 1  0 0  = x8 swizzle quad0/1 & 2/3,	q0:1=18, q2:3=22
+#
+#	  no spare (x8)
+#       0xC000  1 1 0 0   0 0  0 0   0 0  0 0  = x8 no swizzle
+#       0x0C00  0 0 0 0   1 1  0 0   0 0  0 0  = x8 swizzle quad0/1
+#
+#
 #  For Centaur:
-#  Spares on P0_1, P1_2, P2_4, P3_1, DQS in lanes 2:3, DQ in lanes 8:15
+#  Spares on P0_1, P1_2, P2_4, P3_1, DQ in lanes 0:15, DQS in lanes 16:23
 #
 # DP18 Read Clock Enable & Selection RP0
 #  [01:23]						PAIR[0:3]_P[0:1]_[0:4]
@@ -3843,149 +4998,173 @@ scom 0x800(0,1)3C070301143F {					#_P[0:1]_[0:4] via broadcast
 #
 # instance _0=00, _1=04, _2=08, _3=0C, _4=10
 #   RANK_PAIR[0:3], RP[0:3] _P0_0
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 	(4)
-# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_0				(5)
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 	(4)	0x800000040301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 	(4)	0x800004040301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 	(4)	0x800008040301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 	(4)	0x80000C040301143F
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 	(4)	0x800010040301143F
+# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_0				(5)	0x800000050301143F
+# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_1				(5)	0x800004050301143F
+# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_2				(5)	0x800008050301143F
+# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_3				(5)	0x80000C050301143F
+# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_4				(5)	0x800010050301143F
 scom 0x8000008(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_0
-	bits	,	scom_data	,	expr							;
-	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))	;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4))						;	# x4 swizzle quad2/3
+	48:63	,	0xC0C0		,	((def_is_mba01) && (def_is_x8) && (def_is_type1))	;	# x8 swizzle quad 2/3
+	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))						;	# x8 no swizzle
 # P2_0
-	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0x0F00		,	((def_is_mba23) && (def_is_x8))	;	# x8
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4 no swizzle
+	48:63	,	0x0F00		,	((def_is_mba23) && (def_is_x8))	;	# x8 swizzle quad0/1
 	48:63	,	0x0000		,	any								;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_1
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1		0x800004840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1				0x800004850301143F
 scom 0x8000048(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_1
-	bits	,	scom_data	,	expr											;
-	48:63	,	0x8580		,	((def_is_mba01) && (def_has_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x8400		,	((def_is_mba01) && (def_no_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba01) && (def_has_spare) && (def_is_x8))	;	# x8
-	48:63	,	0x0C00		,	((def_is_mba01) && (def_no_spare) && (def_is_x8))	;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8580		,	((def_is_mba01) && (def_has_spare) && (def_is_x4))	;	# x4 spare swizzle quad2/3
+	48:63	,	0x8400		,	((def_is_mba01) && (def_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_has_spare) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
+	48:63	,	0x0C00		,	((def_is_mba01) && (def_no_spare) && (def_is_x8))	;	# x8 swizzle quad0/1
 # P2_1
-	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4
-	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))					;	# x8
+	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4 swizzle quad2/3
+	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))					;	# x8 no swizzle
 	48:63	,	0x0000		,	any												;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_2
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2		0x800008840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2				0x800008850301143F
 scom 0x8000088(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_2
 	bits	,	scom_data	,	expr							;
-	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba01) && (def_is_x8))	;	# x8
+#	0:47	,	0x000000000000,	any								;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))	;	# x4 no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
 # P2_2
-	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba23) && (def_is_x8))	;	# x8
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4 no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba23) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
 	48:63	,	0x0000		,	any								;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_3
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3		0x80000C840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3				0x80000C850301143F
 scom 0x80000C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_3
-	bits	,	scom_data	,	expr							;
-	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba01) && (def_is_x8))	;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))						;	# x4 no swizzle
+	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8) && (def_is_type1))	;	# x8 swizzle quad0/1
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_is_x8))						;	# x8 swizzle quad0/1 & 2/3
 # P2_3
-	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0xC0C0		,	((def_is_mba23) && (def_is_x8))	;	# x8
-	48:63	,	0x0000		,	any								;
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))						;	# x4 no swizzle
+	48:63	,	0xC0C0		,	((def_is_mba23) && (def_is_x8))						;	# x8 swizzle quad2/3
+	48:63	,	0x0000		,	any													;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P0_4
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4		0x800010840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4				0x800010850301143F
 scom 0x8000108(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P0_4
 	bits	,	scom_data	,	expr											;
-	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))					;	# x4
-	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))					;	# x8
+#	0:47	,	0x000000000000,	any												;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))					;	# x4 no swizzle
+	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))					;	# x8 swizzle quad0/1
 # P2_4
-	48:63	,	0x8640		,	((def_is_mba23) && (def_has_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x8400		,	((def_is_mba23) && (def_no_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x0F00		,	((def_is_mba23) && (def_has_spare) && (def_is_x8))	;	# x8
-	48:63	,	0x0C00		,	((def_is_mba23) && (def_no_spare) && (def_is_x8))	;	# x8
-	48:63	,	0x0000		,	any												;
+	48:63	,	0x8640		,	((def_is_mba23) && (def_has_spare) && (def_is_x4))	;	# x4 spare no swizzle
+	48:63	,	0x8400		,	((def_is_mba23) && (def_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0x0F00		,	((def_is_mba23) && (def_has_spare) && (def_is_x8))	;	# x8 swizzle quad0/1
+	48:63	,	0x0C00		,	((def_is_mba23) && (def_no_spare) && (def_is_x8))	;	# x8 swizzle quad0/1
+	48:63	,	0x0000		,	any													;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_0
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0		0x800100840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0				0x800100850301143F
 scom 0x8001008(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_0
-	bits	,	scom_data	,	expr							;
-	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))	;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))						;	# x4 swizzle quad0/1
+	48:63	,	0xC0C0		,	((def_is_mba01) && (def_is_x8) && (def_is_type1))	;	# x8 swizzle quad2/3
+	48:63	,	0x0F00		,	((def_is_mba01) && (def_is_x8))						;	# x8 swizzle quad0/1
 # P3_0
-	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))	;	# x8
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4 no swizzle
+	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))	;	# x8 no swizzle
 	48:63	,	0x0000		,	any								;
 }
 
 #   RANK_PAIR[0:3]_, P1_1
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1		0x800104840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1				0x800104850301143F
 scom 0x8001048(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_1
-	bits	,	scom_data	,	expr											;
-	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))					;	# x4
-	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))					;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4) && (def_is_type1))	;	# x4 no swizzle
+	48:63	,	0x4A40		,	((def_is_mba01) && (def_is_x4))						;	# x4 swizzle quad0/1
+	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))						;	# x8 no swizzle
 # P3_1
-	48:63	,	0x8640		,	((def_is_mba23) && (def_has_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x8400		,	((def_is_mba23) && (def_no_spare) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba23) && (def_has_spare) && (def_is_x8))	;	# x8
-	48:63	,	0xC000		,	((def_is_mba23) && (def_no_spare) && (def_is_x8))	;	# x8
-	48:63	,	0x0000		,	any												;
+	48:63	,	0x8640		,	((def_is_mba23) && (def_has_spare) && (def_is_x4))	;	# x4 spare no swizzle
+	48:63	,	0x8400		,	((def_is_mba23) && (def_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0xC300		,	((def_is_mba23) && (def_has_spare) && (def_is_x8))	;	# x8 no swizzle
+	48:63	,	0xC000		,	((def_is_mba23) && (def_no_spare) && (def_is_x8))	;	# x8 no swizzle
+	48:63	,	0x0000		,	any													;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_2
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2		0x800108840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2				0x800108850301143F
 scom 0x8001088(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_2
 	bits	,	scom_data	,	expr											;
-	48:63	,	0x8640		,	((def_is_mba01) && (def_has_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x8400		,	((def_is_mba01) && (def_no_spare) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba01) && (def_has_spare) && (def_is_x8))	;	# x8
-	48:63	,	0x0C00		,	((def_is_mba01) && (def_no_spare) && (def_is_x8))	;	# x8
+#	0:47	,	0x000000000000,	any												;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_has_spare) && (def_is_x4))	;	# x4 spare no swizzle
+	48:63	,	0x8400		,	((def_is_mba01) && (def_no_spare) && (def_is_x4))	;	# x4 no-spare no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba01) && (def_has_spare) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
+	48:63	,	0x0C00		,	((def_is_mba01) && (def_no_spare) && (def_is_x8))	;	# x8 swizzle quad0/1
 # P3_2
-	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4
-	48:63	,	0x0F00		,	((def_is_mba23) && (def_is_x8))					;	# x8
+	48:63	,	0x8580		,	((def_is_mba23) && (def_is_x4))					;	# x4 swizzle quad2/3
+	48:63	,	0x0F00		,	((def_is_mba23) && (def_is_x8))					;	# x8 swizzle quad0/1
 	48:63	,	0x0000		,	any												;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_3
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3		0x80010C840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3				0x80010C850301143F
 scom 0x80010C8(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_3
-	bits	,	scom_data	,	expr							;
-	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))	;	# x8
+	bits	,	scom_data	,	expr												;
+#	0:47	,	0x000000000000,	any													;	# reserved
+	48:63	,	0x8640		,	((def_is_mba01) && (def_is_x4))						;	# x4 no swizzle
+	48:63	,	0xC0C0		,	((def_is_mba01) && (def_is_x8) && (def_is_type1))	;	# x8 swizzle quad2/3
+	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))						;	# x8 no swizzle
 # P3_3
-	48:63	,	0x4A40		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))	;	# x8
+	48:63	,	0x4A40		,	((def_is_mba23) && (def_is_x4))	;	# x4 swizzle quad0/1
+	48:63	,	0xC300		,	((def_is_mba23) && (def_is_x8))	;	# x8 no swizzle
 	48:63	,	0x0000		,	any								;
 }
 
 #   RANK_PAIR[0:3], RP[0:3] _P1_4
-# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4
-# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4
+# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4		0x800110840301143F
+# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4				0x800110850301143F
 scom 0x8001108(4,5)0301143F {	# _RP[0:3] via broadcast bit
 # P1_4
 	bits	,	scom_data	,	expr							;
-	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4))	;	# x4
-	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))	;	# x8
+#	0:47	,	0x000000000000,	any								;	# reserved
+	48:63	,	0x8580		,	((def_is_mba01) && (def_is_x4))	;	# x4 swizzle quad2/3
+	48:63	,	0xC300		,	((def_is_mba01) && (def_is_x8))	;	# x8 no swizzle
 # P3_4
-	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4
-	48:63	,	0x0CC0		,	((def_is_mba23) && (def_is_x8))	;	# x8
+	48:63	,	0x8640		,	((def_is_mba23) && (def_is_x4))	;	# x4 no swizzle
+	48:63	,	0x0CC0		,	((def_is_mba23) && (def_is_x8))	;	# x8 swizzle quad0/1 & 2/3
 	48:63	,	0x0000		,	any								;
 }
+
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 44ad8471f..6df8eb25d 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,17 @@
 
-#-- $Id: mba_def.initfile,v 1.11 2012/08/20 16:00:27 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.22 2012/12/04 16:03:26 mwuu Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.22|menlowuu|12/04/12|changed CCS_Mode register to set RAS, CAS, WE to high on idles
+#--     1.21|tschang |11/14/12|added throttle control for n/m
+#--     1.20|tschang |11/13/12|updated file for new IBM_TYPE defnitions and added MCBIST ADDR and ADDR mapping fro SCHMOO
+#--     1.16|tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL
+#--     1.15|tschang |09/18/12|update periodic cal registers bit register definitions
+#--     1.14|tschang |09/11/12|update periodic cal registers
+#--     1.13|tschang |09/11/12|backout periodic cal registers settings change
+#--     1.12|tschang |09/10/12|added periodic cal registers settings
 #--     1.11|tschang |08/20/12|added mba mcbist setup values for simple write and read test
 #--		1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line
 #--		1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line
@@ -46,8 +54,12 @@ define def_equal_test     =  (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
 # ATTR_EFF_MBA_POS (0=01, 1=2/3)
 #
 # ATTR_EFF_IBM_TYPE [][] 2x2 array
+# OLD
 # UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12,
 # TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25
+# NEW
+## UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13,
+#  TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum>
 #
 # ATTR_EFF_NUM_DROPS_PER_PORT
 # EMPTY = 0, SINGLE = 1, DUAL = 2
@@ -67,6 +79,151 @@ define def_equal_test     =  (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
 # ATTR_CHIP_UNIT_POS
 # 0 = MBA0 (mba01), 1 = MBA1 (mba23)
 #
+#    <id>ATTR_EFF_MEMCAL_INTERVAL</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the memcal interval in clocks.</description>
+#    <valueType>uint32</valueType>
+#    <enum>DISABLE = 0</enum>
+
+#    <id>ATTR_EFF_ZQCAL_INTERVAL</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the zqcal interval in clocks.</description>
+#    <valueType>uint32</valueType>
+#    <enum>DISABLE = 0</enum>
+
+#<attribute>
+#    <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+#Dimensions are [port][dimm]  A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
+#creator: mss_eff_cnfg
+#consumer: various
+#firmware notes: none</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#    <array> 2 2</array>
+#    <persistRuntime/>
+#</attribute>
+#
+#<attribute>
+#    <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the number of master ranks per DIMM.</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#    <array> 2 2</array>
+#</attribute>
+#
+#<attribute>
+#    <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+#values are 0,1,2, 4 up to 32
+#creator: mss_eff_cnfg
+#consumer: various
+#firmware notes: none</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#    <array> 2 2</array>
+#    <persistRuntime/>
+#</attribute>
+#
+#<attribute>
+#    <id>ATTR_EFF_DRAM_BANKS</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Number of DRAM banks.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+#creator: mss_eff_cnfg
+#consumer: various
+#firmware notes: none</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute>
+#
+#<attribute>
+#    <id>ATTR_EFF_DRAM_ROWS</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Number of DRAM rows.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+#creator: mss_eff_cnfg
+#consumer: various
+#firmware notes: none</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute>
+#
+#<attribute>
+#    <id>ATTR_EFF_DRAM_COLS</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Number of DRAM columns.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
+#creator: mss_eff_cnfg
+#consumer: various
+#firmware notes: none</description>
+#    <valueType>uint8</valueType>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute
+
+
+###############################################################
+# SHMOO ATTRIBUTE to be used by MCBIST to setup the ADDR ranges
+###############################################################
+#<attribute>
+#    <id>ATTR_EFF_SCHMOO_MODE</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
+#    <valueType>uint8</valueType>
+#    <enum>FAST = 0, ONE_SLOW = 1, QUARTER_SLOW = 2, HALF_SLOW = 3, FULL_SLOW = 4, ONE_CHAR = 5, QUARTER_CHAR = 6, HALF_CHAR = 7, FULL_CHAR = 8</enum>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute>
+#
+#
+#<attribute>
+#    <id>ATTR_EFF_SCHMOO_ADDR_MODE</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the schmoo mode to use during draminit_train_adv.</description>
+#    <valueType>uint8</valueType>
+#    <enum>SINGLE (or) FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute>
+#
+#Since the address range is not matter between seq or random..we just need to cut into 1/2 or 1/4 etc... Thanks!
+#
+#
+#2. <attribute>
+#    <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
+#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+#    <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
+#    <valueType>uint8</valueType>
+#    <enum>
+#    <writeable/>
+#    <odmVisable/>
+#    <odmChangeable/>
+#</attribute>
+#Below is what i have defined in the code
+#enum shmoo_test
+#{
+#        NONE = 0x00,
+#        MCBIST = 0x01,
+#        WR_EYE = 0x02,
+#        RD_EYE = 0x04,
+#        WR_DQS = 0x08,
+#        RD_DQS = 0x10,
+#};
+
 
 define def_no_spare     =   (SYS.ATTR_IS_SIMULATION==1) ;
 define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
@@ -101,82 +258,82 @@ define def_1c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TY
 ## Current they is no 1D IBM type in the attribute
 #define def_1d_1socket       = 0;
 #define def_1d_2socket       = 0;
-define def_1d_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_1d_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-#define def_1d_1socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-#define def_1d_2socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+#define def_1d_1socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+#define def_1d_2socket        = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
+define def_1d_1socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_1d_2socket       = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
 
 ## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs
-define def_2a_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm));
-define def_2a_2socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm));
-define def_2a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
-define def_2a_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm));
-define def_2a_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm));
-define def_2a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
-
-define def_2b_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm));
-define def_2b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_2b_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));      # same as type2B 1 socket cfg
-define def_2b_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm));
-define def_2b_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm));
-define def_2b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2B 1 socket DDR4 cfg
+define def_2a_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm));
+define def_2a_2socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm));
+define def_2a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
+define def_2a_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm));
+define def_2a_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm));
+define def_2a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
+
+define def_2b_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm));
+define def_2b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_2b_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));      # same as type2B 1 socket cfg
+define def_2b_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm));
+define def_2b_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm));
+define def_2b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2B 1 socket DDR4 cfg
 
 # centuar spec only has DDR4 for 2C cfg
-define def_2c_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm));
-define def_2c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_2c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type2C 1 socket cfg
-define def_2c_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm));
-define def_2c_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3c_ddr4_cdimm));
-define def_2c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 1 socket DDR4 cfg
+define def_2c_1socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm));
+define def_2c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_2c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type2C 1 socket cfg
+define def_2c_1socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm));
+define def_2c_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3c_ddr4_cdimm));
+define def_2c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 1 socket DDR4 cfg
 
-define def_3a_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_3a_2socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_cdimm));
-#define def_3a_cdimm         = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2A 2 socket cfg
-define def_3a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DRAM_GEN == 1));  # same as type2A 2 socket DDR4 cfg
-define def_3a_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_3a_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_ddr4_cdimm));
-define def_3a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DRAM_GEN == 2));  # same as type2A 2 socket DDR4 cfg
+define def_3a_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_3a_2socket        = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_cdimm));
+#define def_3a_cdimm         = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2A 2 socket cfg
+define def_3a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DRAM_GEN == 1));  # same as type2A 2 socket DDR4 cfg
+define def_3a_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_3a_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_ddr4_cdimm));
+define def_3a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 0) && (ATTR_EFF_DRAM_GEN == 2));  # same as type2A 2 socket DDR4 cfg
 
-define def_3b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_3b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_3b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2B 2 socket DDR4 cfg
-define def_3b_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2B 2 socket DDR4 cfg   ??
+define def_3b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_3b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_3b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2B 2 socket DDR4 cfg
+define def_3b_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));     # same as type2B 2 socket DDR4 cfg   ??
 
-define def_3c_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_3c_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4c_ddr4_cdimm));
-define def_3c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 2 socket DDR4 cfg
-define def_3c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 2 socket DDR4 cfg
+define def_3c_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_3c_2socket_ddr4   = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4c_ddr4_cdimm));
+define def_3c_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 2 socket DDR4 cfg
+define def_3c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));  # same as type2C 2 socket DDR4 cfg
 
-define def_4a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3A 2 socket cfg
-define def_4a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3A 2 socket DDR4 cfg
+define def_4a_cdimm          = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3A 2 socket cfg
+define def_4a_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3A 2 socket DDR4 cfg
 
-define def_4b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3B 2 socket DDR4 cfg
+define def_4b_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 12)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 12))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3B 2 socket DDR4 cfg
 
-define def_4c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 12)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 12))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3C 2 socket DDR4 cfg
+define def_4c_ddr4_cdimm     = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 13)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 13))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 0));       # same as type3C 2 socket DDR4 cfg
 
-define def_5b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 14)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 14))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_5b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 14)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 14))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
-define def_5c_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_5c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5c_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
-define def_5d_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_5d_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5d_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_5d_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
-define def_7a_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 20)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 20))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7a_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 20)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 20))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7a_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 20)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 20))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7a_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 20)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 20))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7a_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7a_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7a_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7a_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
-define def_7b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7b_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7b_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7b_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7b_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7b_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7b_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
-define def_7c_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7c_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
-define def_7c_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7c_1socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7c_2socket        = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7c_1socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3));
+define def_7c_2socket_ddr4   = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3));
 
 
 define def_mtype_1a = ((def_1a_1socket     )||(def_1a_2socket     )); #||(def_1b_cdimm));
@@ -371,6 +528,12 @@ define  def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR
 define  def_ddr4_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3));
 define  def_ddr4_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3));
 
+define  def_ddr4_1600_12_12_12    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
+define  def_ddr4_1600_12_12_12R   = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 ));
+define  def_ddr4_1600_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
+define  def_ddr4_1600_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3));
+define  def_ddr4_1600_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3));
+
 # DDR4 1866
 define  def_ddr4_1866_11_11_11    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
 define  def_ddr4_1866_11_11_11R   = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 ));
@@ -383,6 +546,12 @@ define  def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR
 define  def_ddr4_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3));
 define  def_ddr4_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3));
 
+define  def_ddr4_1866_13_13_13    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
+define  def_ddr4_1866_13_13_13R   = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 ));
+define  def_ddr4_1866_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
+define  def_ddr4_1866_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 1 ) && (ATTR_EFF_DIMM_TYPE == 3));
+define  def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 3));
+
 # DDR4 2133 12 -13  - not supported
 #define  def_ddr4_2133_12_12_12    = 0;
 #define  def_ddr4_2133_12_12_12R   = 0;
@@ -467,17 +636,19 @@ define  def_ddr4_2400_14_14_14_LR = (SYS.ATTR_IS_SIMULATION==0);
 #define  def_ddr4_2400_14_14_14    = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( def_ATTR_EFF_DRAM_2N_MODE == 0 ) && (ATTR_EFF_DIMM_TYPE == 0 || ATTR_EFF_DIMM_TYPE == 2));
 
 # new 7,8,9
-define  def_mba_tmr0q_RW_dlys7  = ((def_ddr3_1066_6_6_6_group )||( def_ddr4_1600_9_9_9       )||(def_ddr4_1600_9_9_9_2N    )||(def_ddr4_1600_9_9_9R));
-define  def_mba_tmr0q_RW_dlys8  = ((def_ddr3_1066_7_7_7_group )||( def_ddr3_1333_8_8_8       )||(def_ddr3_1600_9_9_9       )||(def_ddr3_1333_8_8_8_2N    )||(def_ddr3_1600_9_9_9_2N    )||(def_ddr3_1333_8_8_8R      )||(def_ddr3_1600_9_9_9R      )||(def_ddr4_1600_10_10_10    )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R));
-define  def_mba_tmr0q_RW_dlys9  = ((def_ddr3_1066_8_8_8_group )||( def_ddr3_1333_9_9_9       )||(def_ddr3_1600_10_10_10    )||(def_ddr3_1333_9_9_9_2N    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1333_9_9_9R      )||(def_ddr3_1600_10_10_10R   )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1866_11_11_11    )||(def_ddr4_2133_12_12_12    )||(def_ddr4_2133_13_13_13    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_2133_12_12_12R   )||(def_ddr4_2133_13_13_13R));
-define  def_mba_tmr0q_RW_dlys10 = ((def_ddr3_1600_11_11_11    )||(def_ddr3_1866_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1866_11_11_11R   )||(def_ddr4_1866_12_12_12    )||(def_ddr4_2400_13_13_13    )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_1866_12_12_12R   )||(def_ddr4_2400_13_13_13R));
-define  def_mba_tmr0q_RW_dlys11 = ((def_ddr3_1866_12_12_12    )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R   )||(def_ddr4_2400_14_14_14    )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R   )||(def_ddr4_1600_9_9_9_LR    )||(def_ddr4_1600_9_9_9_L2));
-define  def_mba_tmr0q_RW_dlys12 = ((def_ddr3_1333_8_8_8_LR    )||(def_ddr3_1600_9_9_9_LR    )||(def_ddr3_1333_8_8_8_L2    )||(def_ddr3_1600_9_9_9_L2    )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2));
-define  def_mba_tmr0q_RW_dlys13 = ((def_ddr3_1333_9_9_9_LR    )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1333_9_9_9_L2    )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )||(def_ddr4_2133_13_13_13_L2));
-define  def_mba_tmr0q_RW_dlys14 = ((def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13_L2));
-define  def_mba_tmr0q_RW_dlys15 = ((def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2));
+
+define  def_mba_tmr0q_RW_dlys7  = ((def_ddr3_1066_6_6_6      )||( def_ddr3_1066_6_6_6_2N    )||( def_ddr3_1066_6_6_6R      )||( def_ddr4_1600_9_9_9       )||(def_ddr4_1600_9_9_9_2N    )||(def_ddr4_1600_9_9_9R));
+define  def_mba_tmr0q_RW_dlys8  = ((def_ddr3_1066_7_7_7      )||( def_ddr3_1066_7_7_7_2N    )||( def_ddr3_1066_7_7_7R      )||( def_ddr3_1333_8_8_8       )||(def_ddr3_1600_9_9_9       )||(def_ddr3_1333_8_8_8_2N    )||(def_ddr3_1600_9_9_9_2N    )||(def_ddr3_1333_8_8_8R      )||(def_ddr3_1600_9_9_9R      )||(def_ddr4_1600_10_10_10    )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R));
+define  def_mba_tmr0q_RW_dlys9  = ((def_ddr3_1066_8_8_8      )||( def_ddr3_1066_8_8_8_2N    )||( def_ddr3_1066_8_8_8R      )||( def_ddr3_1333_9_9_9       )||(def_ddr3_1600_10_10_10    )||(def_ddr3_1333_9_9_9_2N    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1333_9_9_9R      )||(def_ddr3_1600_10_10_10R   )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1866_11_11_11    )||(def_ddr4_2133_12_12_12    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_2133_12_12_12R   ));
+define  def_mba_tmr0q_RW_dlys10 = ((def_ddr4_1600_12_12_12)||(def_ddr4_1600_12_12_12_2N)||(def_ddr4_1600_12_12_12R)||(def_ddr4_2133_13_13_13R)||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13    )||(def_ddr3_1600_11_11_11    )||(def_ddr3_1866_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1866_11_11_11R   )||(def_ddr4_1866_12_12_12    )||(def_ddr4_2400_13_13_13    )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_1866_12_12_12R   )||(def_ddr4_2400_13_13_13R));
+define  def_mba_tmr0q_RW_dlys11 = ((def_ddr4_1866_13_13_13)||(def_ddr4_1866_13_13_13_2N)||(def_ddr4_1866_13_13_13R)||(def_ddr3_1066_6_6_6_L2)||( def_ddr3_1066_6_6_6_LR    )||(def_ddr3_1866_12_12_12    )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R   )||(def_ddr4_2400_14_14_14    )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R   )||(def_ddr4_1600_9_9_9_LR    )||(def_ddr4_1600_9_9_9_L2));
+define  def_mba_tmr0q_RW_dlys12 = (( def_ddr3_1066_7_7_7_L2)||( def_ddr3_1066_7_7_7_LR    )||(def_ddr3_1333_8_8_8_LR    )||(def_ddr3_1600_9_9_9_LR    )||(def_ddr3_1333_8_8_8_L2    )||(def_ddr3_1600_9_9_9_L2    )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2));
+define  def_mba_tmr0q_RW_dlys13 = (( def_ddr3_1066_8_8_8_L2)||( def_ddr3_1066_8_8_8_LR    )||(def_ddr3_1333_9_9_9_LR    )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1333_9_9_9_L2    )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 ));
+define  def_mba_tmr0q_RW_dlys14 = ((def_ddr4_1600_12_12_12_LR)||(def_ddr4_1600_12_12_12_L2)||(def_ddr4_2133_13_13_13_L2)||(def_ddr4_2133_13_13_13_LR )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13_L2));
+define  def_mba_tmr0q_RW_dlys15 = ((def_ddr4_1866_13_13_13_LR)||(def_ddr4_1866_13_13_13_L2)||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2));
 
 #new  19,20,21
+
 define  def_mba_tmr0q_WRSM_dlys19 = (def_ddr3_1066_6_6_6_group);
 define  def_mba_tmr0q_WRSM_dlys20 = (def_ddr3_1066_7_7_7_group);
 define  def_mba_tmr0q_WRSM_dlys21 = (def_ddr3_1066_8_8_8_group);
@@ -487,23 +658,23 @@ define  def_mba_tmr0q_WRSM_dlys24 = ((def_ddr3_1333_9_9_9       )||(def_ddr3_133
 define  def_mba_tmr0q_WRSM_dlys25 = ((def_ddr4_1600_9_9_9       )||(def_ddr4_1600_9_9_9_2N    )||(def_ddr4_1600_9_9_9R      )||(def_ddr4_1600_9_9_9_LR    )||(def_ddr4_1600_9_9_9_L2    ));
 define  def_mba_tmr0q_WRSM_dlys26 = ((def_ddr3_1600_9_9_9       )||(def_ddr3_1600_9_9_9_2N    )||(def_ddr3_1600_9_9_9R      )||(def_ddr3_1600_9_9_9_LR    )||(def_ddr3_1600_9_9_9_L2    )||(def_ddr4_1600_10_10_10    )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R   )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2 ));
 define  def_mba_tmr0q_WRSM_dlys27 = ((def_ddr3_1600_10_10_10    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R   )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2 ));
-define  def_mba_tmr0q_WRSM_dlys28 = ((def_ddr3_1600_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11    )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2 ));
+define  def_mba_tmr0q_WRSM_dlys28 = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11    )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2 ));
 define  def_mba_tmr0q_WRSM_dlys29 = ((def_ddr4_1866_12_12_12    )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R   )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2 ));
 define  def_mba_tmr0q_WRSM_dlys30 = ((def_ddr4_2133_12_12_12    )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R   )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2 ));
 define  def_mba_tmr0q_WRSM_dlys31 = ((def_ddr3_1866_11_11_11    )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1866_11_11_11R   )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_2133_13_13_13    )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R   )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2 ));
-define  def_mba_tmr0q_WRSM_dlys32 = ((def_ddr3_1866_12_12_12    )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R   )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13    )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R   )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2 ));
+define  def_mba_tmr0q_WRSM_dlys32 = (def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1866_12_12_12    )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R   )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13    )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R   )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2 ));
 define  def_mba_tmr0q_WRSM_dlys33 = ((def_ddr4_2400_14_14_14    )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R   )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2 ));
 
 #new 7,6,5
-define  def_mba_tmr0q_WRDM_dlys4 = ((def_ddr3_1600_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2));
-define  def_mba_tmr0q_WRDM_dlys5 = ((def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_9_9_9       )||(def_ddr3_1600_10_10_10    )||(def_ddr3_1866_12_12_12    )||(def_ddr3_1333_9_9_9_2N    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1333_9_9_9R      )||(def_ddr3_1600_10_10_10R   )||(def_ddr3_1866_12_12_12R   )||(def_ddr3_1333_9_9_9_LR    )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1333_9_9_9_L2    )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2));
+define  def_mba_tmr0q_WRDM_dlys4 = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2));
+define  def_mba_tmr0q_WRDM_dlys5 = (def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_9_9_9       )||(def_ddr3_1600_10_10_10    )||(def_ddr3_1866_12_12_12    )||(def_ddr3_1333_9_9_9_2N    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1333_9_9_9R      )||(def_ddr3_1600_10_10_10R   )||(def_ddr3_1866_12_12_12R   )||(def_ddr3_1333_9_9_9_LR    )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1333_9_9_9_L2    )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2));
 define  def_mba_tmr0q_WRDM_dlys6 = ((def_ddr3_1066_7_7_7_group )||(def_ddr3_1333_8_8_8       )||(def_ddr3_1600_9_9_9       )||(def_ddr3_1866_11_11_11    )||(def_ddr3_1333_8_8_8_2N    )||(def_ddr3_1600_9_9_9_2N    )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1333_8_8_8R      )||(def_ddr3_1600_9_9_9R      )||(def_ddr3_1866_11_11_11R   )||(def_ddr3_1333_8_8_8_LR    )||(def_ddr3_1600_9_9_9_LR    )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1333_8_8_8_L2    )||(def_ddr3_1600_9_9_9_L2    )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_10_10_10    )||(def_ddr4_1866_12_12_12    )||(def_ddr4_2133_13_13_13    )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_1600_10_10_10R   )||(def_ddr4_1866_12_12_12R   )||(def_ddr4_2133_13_13_13R   )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_1600_10_10_10_L2 )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2133_13_13_13_L2));
 define  def_mba_tmr0q_WRDM_dlys7 = ((def_ddr3_1066_6_6_6_group )||(def_ddr4_1600_9_9_9       )||(def_ddr4_1866_11_11_11    )||(def_ddr4_2133_12_12_12    )||(def_ddr4_2400_14_14_14    )||(def_ddr4_1600_9_9_9_2N    )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_1600_9_9_9R      )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_2133_12_12_12R   )||(def_ddr4_2400_14_14_14R   )||(def_ddr4_1600_9_9_9_LR    )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_1600_9_9_9_L2    )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )||(def_ddr4_2400_14_14_14_L2));
 define  def_mba_tmr0q_WRDM_dlys8 = ((def_ddr4_2400_13_13_13    )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R   )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2));
 
 #new all 0
 define  def_mba_tmr1q_RRSBG_dlys0 = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_1066_7_7_7_group )||( def_ddr3_1066_8_8_8_group )||( def_ddr3_1600_11_11_11    )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R   )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr3_1333_9_9_9       )||( def_ddr3_1600_10_10_10    )||( def_ddr3_1333_9_9_9_2N    )||( def_ddr3_1600_10_10_10_2N )||( def_ddr3_1333_9_9_9R      )||( def_ddr3_1600_10_10_10R   )||( def_ddr3_1333_9_9_9_LR    )||( def_ddr3_1600_10_10_10_LR )||( def_ddr3_1333_9_9_9_L2    )||( def_ddr3_1600_10_10_10_L2 )||( def_ddr3_1333_8_8_8       )||( def_ddr3_1600_9_9_9       )||( def_ddr3_1333_8_8_8_2N    )||( def_ddr3_1600_9_9_9_2N    )||( def_ddr3_1333_8_8_8R      )||( def_ddr3_1600_9_9_9R      )||( def_ddr3_1333_8_8_8_LR    )||( def_ddr3_1600_9_9_9_LR    )||( def_ddr3_1333_8_8_8_L2    )||( def_ddr3_1600_9_9_9_L2    )||( def_ddr3_1866_12_12_12    )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R   )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr3_1866_11_11_11    )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R   )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2));
-define  def_mba_tmr1q_RRSBG_dlys5 = ((def_ddr4_1600_11_11_11    )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R   )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2 )||( def_ddr4_1600_10_10_10    )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R   )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2 )||( def_ddr4_1600_9_9_9       )||( def_ddr4_1600_9_9_9_2N    )||( def_ddr4_1600_9_9_9R      )||( def_ddr4_1600_9_9_9_LR    )||( def_ddr4_1600_9_9_9_L2    )||( def_ddr4_1866_12_12_12    )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R   )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2 )||( def_ddr4_1866_11_11_11    )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R   )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2));
+define  def_mba_tmr1q_RRSBG_dlys5 = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ||def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr4_1600_11_11_11    )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R   )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2 )||( def_ddr4_1600_10_10_10    )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R   )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2 )||( def_ddr4_1600_9_9_9       )||( def_ddr4_1600_9_9_9_2N    )||( def_ddr4_1600_9_9_9R      )||( def_ddr4_1600_9_9_9_LR    )||( def_ddr4_1600_9_9_9_L2    )||( def_ddr4_1866_12_12_12    )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R   )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2 )||( def_ddr4_1866_11_11_11    )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R   )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2));
 define  def_mba_tmr1q_RRSBG_dlys6 = ((def_ddr4_2133_13_13_13    )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R   )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2 )||( def_ddr4_2133_12_12_12    )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R   )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2 )||( def_ddr4_2400_14_14_14    )||( def_ddr4_2400_14_14_14_2N )||( def_ddr4_2400_14_14_14R   )||( def_ddr4_2400_14_14_14_LR )||( def_ddr4_2400_14_14_14_L2 )||( def_ddr4_2400_13_13_13    )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R   )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2));
 
 #new all 0
@@ -511,8 +682,10 @@ define  def_mba_tmr1q_WRSBG_dlys0   = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_
 define  def_mba_tmr1q_WRSBG_dlys26  = ((def_ddr4_1600_9_9_9       )||( def_ddr4_1600_9_9_9_2N    )||( def_ddr4_1600_9_9_9R      )||( def_ddr4_1600_9_9_9_LR    )||( def_ddr4_1600_9_9_9_L2));
 define  def_mba_tmr1q_WRSBG_dlys27  = ((def_ddr4_1600_10_10_10    )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R   )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2));
 define  def_mba_tmr1q_WRSBG_dlys28  = ((def_ddr4_1600_11_11_11    )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R   )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2));
+define  def_mba_tmr1q_WRSBG_dlys29  = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2  );
 define  def_mba_tmr1q_WRSBG_dlys30  = ((def_ddr4_1866_11_11_11    )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R   )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2));
 define  def_mba_tmr1q_WRSBG_dlys31  = ((def_ddr4_1866_12_12_12    )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R   )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2));
+#define  def_mba_tmr1q_WRSBG_dlys32  = (def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2  );
 #define  def_mba_tmr1q_WRSBG_dlys33 = ((def_ddr4_2133_12_12_12    )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R   )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2));
 #define  def_mba_tmr1q_WRSBG_dlys34 = ((def_ddr4_2133_13_13_13    )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R   )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2));
 #define  def_mba_tmr1q_WRSBG_dlys36 = ((def_ddr4_2400_13_13_13    )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R   )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2));
@@ -529,8 +702,10 @@ define  def_mba_tmr1q_cfg_trap37 = ((def_ddr3_1600_9_9_9       )||(def_ddr3_1600
 define  def_mba_tmr1q_cfg_trap38 = ((def_ddr3_1600_10_10_10    )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R   )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_10_10_10    )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R   )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2));
 define  def_mba_tmr1q_cfg_trap39 = ((def_ddr3_1600_11_11_11    )||(def_ddr3_1866_11_11_11    )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R   )||(def_ddr3_1866_11_11_11R   )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11    )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R   )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2));
 define  def_mba_tmr1q_cfg_trap40 = ((def_ddr3_1866_12_12_12    )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R   )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2));
+define  def_mba_tmr1q_cfg_trap42 = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2);
 define  def_mba_tmr1q_cfg_trap43 = ((def_ddr4_1866_11_11_11    )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R   )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2));
 define  def_mba_tmr1q_cfg_trap44 = ((def_ddr4_1866_12_12_12    )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R   )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2));
+define  def_mba_tmr1q_cfg_trap46 = (def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2);
 #define  def_mba_tmr1q_cfg_trap48 = ((def_ddr4_2133_12_12_12    )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R   )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2));
 #define  def_mba_tmr1q_cfg_trap49 = ((def_ddr4_2133_13_13_13    )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R   )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2));
 #define  def_mba_tmr1q_cfg_trap52 = ((def_ddr4_2400_13_13_13    )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R   )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2));
@@ -546,8 +721,10 @@ define  def_mba_tmr1q_cfg_twap39  = (def_mba_tmr1q_cfg_trap33);
 define  def_mba_tmr1q_cfg_twap42  = (def_mba_tmr1q_cfg_trap37);
 define  def_mba_tmr1q_cfg_twap44  = (def_mba_tmr1q_cfg_trap38);
 define  def_mba_tmr1q_cfg_twap46  = ((def_ddr3_1600_11_11_11    )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R   )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr4_1600_11_11_11    )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R   )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2));
+define  def_mba_tmr1q_cfg_twap48  = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2);
 define  def_mba_tmr1q_cfg_twap49  = ((def_ddr3_1866_11_11_11    )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R   )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2 )||( def_ddr4_1866_11_11_11    )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R   )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2));
 define  def_mba_tmr1q_cfg_twap51  = ((def_ddr3_1866_12_12_12    )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R   )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr4_1866_12_12_12    )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R   )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2));
+define  def_mba_tmr1q_cfg_twap53  = (def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2);
 #define  def_mba_tmr1q_cfg_twap54  = (def_mba_tmr1q_cfg_trap48);
 #define  def_mba_tmr1q_cfg_twap56  = (def_mba_tmr1q_cfg_trap49);
 #define  def_mba_tmr1q_cfg_twap59  = (def_mba_tmr1q_cfg_trap52);
@@ -564,14 +741,14 @@ define  def_mba_dsm0q_cfg_rdtag_dly17  = (def_ddr3_1066_8_8_8R      ||def_ddr3_1
 define  def_mba_dsm0q_cfg_rdtag_dly18  = (def_ddr3_1066_7_7_7_L2    ||def_ddr3_1600_10_10_10    ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1333_9_9_9R      ||def_ddr3_1333_8_8_8_L2    ||def_ddr4_1600_10_10_10);
 define  def_mba_dsm0q_cfg_rdtag_dly19  = (def_ddr3_1066_7_7_7_LR    ||def_ddr3_1066_8_8_8_L2    ||def_ddr3_1600_10_10_10R   ||def_ddr3_1333_8_8_8_LR    ||def_ddr3_1600_9_9_9_L2    ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1600_9_9_9_L2);
 define  def_mba_dsm0q_cfg_rdtag_dly20  = (def_ddr3_1066_8_8_8_LR    ||def_ddr3_1600_11_11_11    ||def_ddr3_1866_11_11_11    ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_9_9_9_LR    ||def_ddr3_1333_9_9_9_L2    ||def_ddr4_1600_11_11_11    ||def_ddr4_1866_11_11_11    ||def_ddr4_1600_9_9_9_LR);
-define  def_mba_dsm0q_cfg_rdtag_dly21  = (def_ddr3_1600_11_11_11R   ||def_ddr3_1866_11_11_11R   ||def_ddr3_1333_9_9_9_LR    ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_11_11_11R   ||def_ddr4_1600_10_10_10_L2);
-define  def_mba_dsm0q_cfg_rdtag_dly22  = (def_ddr3_1866_12_12_12    ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1866_12_12_12    ||def_ddr4_2133_12_12_12    ||def_ddr4_2400_13_13_13_2N ||def_ddr4_1600_10_10_10_LR);
-define  def_mba_dsm0q_cfg_rdtag_dly23  = (def_ddr3_1866_12_12_12R   ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_2400_13_13_13    ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_12_12_12R   ||def_ddr4_1600_11_11_11_L2 ||def_ddr4_1866_11_11_11_L2);
-define  def_mba_dsm0q_cfg_rdtag_dly24  = (def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_LR ||def_ddr4_2133_13_13_13    ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2400_13_13_13R   ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_LR);
-define  def_mba_dsm0q_cfg_rdtag_dly25  = (def_ddr3_1866_12_12_12_L2 ||def_ddr4_2400_14_14_14    ||def_ddr4_2133_13_13_13R   ||def_ddr4_1866_12_12_12_L2 ||def_ddr4_2133_12_12_12_L2);
-define  def_mba_dsm0q_cfg_rdtag_dly26  = (def_ddr3_1866_12_12_12_LR ||def_ddr4_2400_14_14_14R   ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_L2);
-define  def_mba_dsm0q_cfg_rdtag_dly27  = (def_ddr4_2400_13_13_13_LR ||def_ddr4_2133_13_13_13_L2);
-define  def_mba_dsm0q_cfg_rdtag_dly28  = (def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly21  = (def_ddr4_1600_12_12_12_2N ||def_ddr3_1600_11_11_11R   ||def_ddr3_1866_11_11_11R   ||def_ddr3_1333_9_9_9_LR    ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_11_11_11R   ||def_ddr4_1600_10_10_10_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly22  = (def_ddr4_1600_12_12_12    ||def_ddr3_1866_12_12_12    ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1866_12_12_12    ||def_ddr4_2133_12_12_12    ||def_ddr4_2400_13_13_13_2N ||def_ddr4_1600_10_10_10_LR);
+define  def_mba_dsm0q_cfg_rdtag_dly23  = (def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R   ||def_ddr3_1866_12_12_12R   ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_2400_13_13_13    ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_12_12_12R   ||def_ddr4_1600_11_11_11_L2 ||def_ddr4_1866_11_11_11_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly24  = (def_ddr4_1866_13_13_13    ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_LR ||def_ddr4_2133_13_13_13    ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2400_13_13_13R   ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_LR);
+define  def_mba_dsm0q_cfg_rdtag_dly25  = (def_ddr4_1866_13_13_13R   ||def_ddr4_1600_12_12_12_L2 ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_2400_14_14_14    ||def_ddr4_2133_13_13_13R   ||def_ddr4_1866_12_12_12_L2 ||def_ddr4_2133_12_12_12_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly26  = (def_ddr4_1600_12_12_12_LR ||def_ddr3_1866_12_12_12_LR ||def_ddr4_2400_14_14_14R   ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly27  = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2133_13_13_13_L2);
+define  def_mba_dsm0q_cfg_rdtag_dly28  = (def_ddr4_1866_13_13_13_LR ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_L2);
 define  def_mba_dsm0q_cfg_rdtag_dly29  = (def_ddr4_2400_14_14_14_LR);
 
 #mixed
@@ -585,11 +762,11 @@ define  def_mba_dsm0q_cfg_wrdata_dly8   = (def_ddr3_1333_9_9_9       ||def_ddr3_
 define  def_mba_dsm0q_cfg_wrdata_dly9   = (def_ddr3_1600_9_9_9       ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R      ||def_ddr3_1600_9_9_9_LR    ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1600_9_9_9_2N    ||def_ddr4_1600_9_9_9_L2);
 define  def_mba_dsm0q_cfg_wrdata_dly10  = (def_ddr3_1600_10_10_10    ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1600_9_9_9R      ||def_ddr3_1600_10_10_10_LR ||def_ddr3_1600_11_11_11_L2 ||def_ddr4_1600_9_9_9       ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_9_9_9_LR    ||def_ddr4_1600_10_10_10_L2);
 define  def_mba_dsm0q_cfg_wrdata_dly11  = (def_ddr3_1600_11_11_11    ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R   ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10    ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1600_9_9_9R      ||def_ddr4_1600_10_10_10_LR ||def_ddr4_1600_11_11_11_L2);
-define  def_mba_dsm0q_cfg_wrdata_dly12  = (def_ddr3_1866_11_11_11    ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R   ||def_ddr3_1866_11_11_11_LR ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11    ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_L2);
-define  def_mba_dsm0q_cfg_wrdata_dly13  = (def_ddr3_1866_12_12_12    ||def_ddr3_1866_11_11_11R   ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_11_11_11    ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_11_11_11_LR ||def_ddr4_1866_12_12_12_L2);
-define  def_mba_dsm0q_cfg_wrdata_dly14  = (def_ddr3_1866_12_12_12R   ||def_ddr4_1866_12_12_12    ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R   ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_L2);
-define  def_mba_dsm0q_cfg_wrdata_dly15  = (def_ddr4_2133_12_12_12    ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2133_13_13_13_L2);
-define  def_mba_dsm0q_cfg_wrdata_dly16  = (def_ddr4_2133_13_13_13    ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R   ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_13_13_13_L2);
+define  def_mba_dsm0q_cfg_wrdata_dly12  = (def_ddr4_1600_12_12_12_L2 ||def_ddr4_1600_12_12_12_2N ||def_ddr3_1866_11_11_11    ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R   ||def_ddr3_1866_11_11_11_LR ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11    ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_L2);
+define  def_mba_dsm0q_cfg_wrdata_dly13  = (def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12    ||def_ddr3_1866_12_12_12    ||def_ddr3_1866_11_11_11R   ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_11_11_11    ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_11_11_11_LR ||def_ddr4_1866_12_12_12_L2);
+define  def_mba_dsm0q_cfg_wrdata_dly14  = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R   ||def_ddr3_1866_12_12_12R   ||def_ddr4_1866_12_12_12    ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R   ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_L2);
+define  def_mba_dsm0q_cfg_wrdata_dly15  = (def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13    ||def_ddr4_2133_12_12_12    ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2133_13_13_13_L2);
+define  def_mba_dsm0q_cfg_wrdata_dly16  = (def_ddr4_1866_13_13_13R   ||def_ddr4_2133_13_13_13    ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R   ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_13_13_13_L2);
 define  def_mba_dsm0q_cfg_wrdata_dly17  = (def_ddr4_2400_13_13_13    ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2133_13_13_13R   ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_14_14_14_L2);
 define  def_mba_dsm0q_cfg_wrdata_dly18  = (def_ddr4_2400_14_14_14    ||def_ddr4_2400_13_13_13R   ||def_ddr4_2400_14_14_14_LR);
 define  def_mba_dsm0q_cfg_wrdata_dly19  = (def_ddr4_2400_14_14_14R);
@@ -600,13 +777,15 @@ define  def_mba_dsm0q_CFG_RODT_start_dly0  = (def_ddr3_1066_6_6_6_group);
 define  def_mba_dsm0q_CFG_RODT_start_dly1  = (def_ddr3_1066_7_7_7_group ||def_ddr3_1333_8_8_8_2N    ||def_ddr3_1333_8_8_8_L2    ||def_ddr3_1333_8_8_8       ||def_ddr3_1333_8_8_8_LR    ||def_ddr3_1600_9_9_9_2N    ||def_ddr3_1333_8_8_8R      ||def_ddr3_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9       ||def_ddr3_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9_2N    ||def_ddr4_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9R      ||def_ddr4_1600_9_9_9       ||def_ddr4_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9R);
 define  def_mba_dsm0q_CFG_RODT_start_dly2  = (def_ddr3_1066_8_8_8_group ||def_ddr3_1333_9_9_9_2N    ||def_ddr3_1333_9_9_9_L2    ||def_ddr3_1333_9_9_9       ||def_ddr3_1333_9_9_9_LR    ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R      ||def_ddr3_1600_10_10_10_L2 ||def_ddr3_1600_10_10_10    ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_10_10_10_L2 ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R   ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10    ||def_ddr4_1600_10_10_10_LR ||def_ddr3_1866_11_11_11    ||def_ddr3_1866_11_11_11_LR ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1866_11_11_11_L2 ||def_ddr3_1866_11_11_11R   ||def_ddr4_1866_11_11_11    ||def_ddr4_1866_11_11_11_LR ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R   ||def_ddr4_2133_12_12_12_L2 ||def_ddr4_2133_12_12_12    ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R   ||def_ddr4_2400_13_13_13_L2 ||def_ddr4_2400_13_13_13    ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_13_13_13R);
 define  def_mba_dsm0q_CFG_RODT_start_dly3  = (def_ddr3_1600_11_11_11_2N ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1600_11_11_11    ||def_ddr3_1600_11_11_11_LR ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1600_11_11_11_L2 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R   ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11    ||def_ddr4_1600_11_11_11_LR ||def_ddr3_1866_12_12_12    ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_12_12_12_L2 ||def_ddr3_1866_12_12_12R   ||def_ddr4_1866_12_12_12    ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_13_13_13_L2 ||def_ddr4_2133_13_13_13    ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2133_13_13_13R   ||def_ddr4_2400_14_14_14_L2 ||def_ddr4_2400_14_14_14    ||def_ddr4_2400_14_14_14_LR ||def_ddr4_2400_14_14_14R);
+define  def_mba_dsm0q_CFG_RODT_start_dly4  = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ||def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2);
 
 # 5,6,7
 define  def_mba_dsm0q_CFG_RODT_end_dly5 = (def_ddr3_1066_6_6_6_group);
 
-define  def_mba_dsm0q_CFG_RODT_end_dly6 = (def_ddr3_1066_7_7_7_group ||def_ddr3_1333_8_8_8_2N    ||def_ddr3_1333_8_8_8_L2    ||def_ddr3_1333_8_8_8       ||def_ddr3_1333_8_8_8_LR    ||def_ddr3_1600_9_9_9_2N    ||def_ddr3_1333_8_8_8R      ||def_ddr3_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9       ||def_ddr3_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9R      ||def_ddr4_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9R);
-define  def_mba_dsm0q_CFG_RODT_end_dly7 = (def_ddr3_1066_8_8_8_group ||def_ddr4_1600_9_9_9_2N    ||def_ddr4_1600_9_9_9       ||def_ddr3_1333_9_9_9_2N    ||def_ddr3_1333_9_9_9_L2    ||def_ddr3_1333_9_9_9       ||def_ddr3_1333_9_9_9_LR    ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R      ||def_ddr3_1600_10_10_10_L2 ||def_ddr3_1600_10_10_10    ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_10_10_10_L2 ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R   ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10    ||def_ddr4_1600_10_10_10_LR ||def_ddr3_1866_11_11_11    ||def_ddr3_1866_11_11_11_LR ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1866_11_11_11_L2 ||def_ddr3_1866_11_11_11R   ||def_ddr4_1866_11_11_11    ||def_ddr4_1866_11_11_11_LR ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R   ||def_ddr4_2133_12_12_12_L2 ||def_ddr4_2133_12_12_12    ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R   ||def_ddr4_2400_13_13_13_L2 ||def_ddr4_2400_13_13_13    ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_13_13_13R);
+define  def_mba_dsm0q_CFG_RODT_end_dly6 = (def_ddr4_1600_9_9_9_2N    ||def_ddr4_1600_9_9_9       ||def_ddr3_1066_7_7_7_group ||def_ddr3_1333_8_8_8_2N    ||def_ddr3_1333_8_8_8_L2    ||def_ddr3_1333_8_8_8       ||def_ddr3_1333_8_8_8_LR    ||def_ddr3_1600_9_9_9_2N    ||def_ddr3_1333_8_8_8R      ||def_ddr3_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9       ||def_ddr3_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9_L2    ||def_ddr3_1600_9_9_9R      ||def_ddr4_1600_9_9_9_LR    ||def_ddr4_1600_9_9_9R);
+define  def_mba_dsm0q_CFG_RODT_end_dly7 = (def_ddr3_1066_8_8_8_group ||def_ddr3_1333_9_9_9_2N    ||def_ddr3_1333_9_9_9_L2    ||def_ddr3_1333_9_9_9       ||def_ddr3_1333_9_9_9_LR    ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R      ||def_ddr3_1600_10_10_10_L2 ||def_ddr3_1600_10_10_10    ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_10_10_10_L2 ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R   ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10    ||def_ddr4_1600_10_10_10_LR ||def_ddr3_1866_11_11_11    ||def_ddr3_1866_11_11_11_LR ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R   ||def_ddr4_1866_11_11_11_L2 ||def_ddr3_1866_11_11_11R   ||def_ddr4_1866_11_11_11    ||def_ddr4_1866_11_11_11_LR ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R   ||def_ddr4_2133_12_12_12_L2 ||def_ddr4_2133_12_12_12    ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R   ||def_ddr4_2400_13_13_13_L2 ||def_ddr4_2400_13_13_13    ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_13_13_13R);
 define  def_mba_dsm0q_CFG_RODT_end_dly8 = (def_ddr3_1600_11_11_11_2N ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1600_11_11_11    ||def_ddr3_1600_11_11_11_LR ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1600_11_11_11_L2 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R   ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11    ||def_ddr4_1600_11_11_11_LR ||def_ddr3_1866_12_12_12    ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R   ||def_ddr4_1866_12_12_12_L2 ||def_ddr3_1866_12_12_12R   ||def_ddr4_1866_12_12_12    ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R   ||def_ddr4_2133_13_13_13_L2 ||def_ddr4_2133_13_13_13    ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2133_13_13_13R   ||def_ddr4_2400_14_14_14_L2 ||def_ddr4_2400_14_14_14    ||def_ddr4_2400_14_14_14_LR ||def_ddr4_2400_14_14_14R);
+define  def_mba_dsm0q_CFG_RODT_end_dly9 = (def_ddr4_1600_12_12_12    ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R   ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ||def_ddr4_1866_13_13_13    ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R   ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2);
 
 # 5,6,7
 define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 = (def_ddr3_1066_6_6_6_group);
@@ -614,41 +793,89 @@ define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 = (def_ddr3_1066_6_6_6_group);
 define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 = (def_ddr3_1066_7_7_7_group  ||def_mba_dsm0q_CFG_RODT_end_dly6);
 define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 = (def_ddr3_1066_8_8_8_group  ||def_mba_dsm0q_CFG_RODT_end_dly7);
 define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY8 = (def_mba_dsm0q_CFG_RODT_end_dly8);
-
-define  def_mba_tmr1q_cfg_tfaw_dly20  = (def_1066_2gb                       ||def_1066_4gb                       ||def_1066_8gb                       ||def_1066_2gb_fast_exit_pd          ||def_1066_4gb_fast_exit_pd          ||def_1066_8gb_fast_exit_pd          ||def_1333_2gb                       ||def_1333_4gb                       ||def_1333_2gb_fast_exit_pd          ||def_1333_4gb_fast_exit_pd);
-define  def_mba_tmr1q_cfg_tfaw_dly24  = (def_1600_2gb                       ||def_1600_4gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_4gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_4gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4     ||def_1600_4gb_fast_exit_pd_ddr4    );
-define  def_mba_tmr1q_cfg_tfaw_dly29  = (def_1866_2gb                       ||def_1866_4gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_4gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_4gb_ddr4                  ||def_2133_2gb_ddr4                  ||def_2133_4gb_ddr4                  ||def_2400_2gb_ddr4                  ||def_2400_4gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4     ||def_1866_4gb_fast_exit_pd_ddr4    );
-define  def_mba_tmr1q_cfg_tfaw_dly30  = (def_1333_8gb                       ||def_1333_8gb_fast_exit_pd          ||def_2133_2gb_fast_exit_pd_ddr4     ||def_2133_4gb_fast_exit_pd_ddr4    );
-define  def_mba_tmr1q_cfg_tfaw_dly32  = (def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4     ||def_2400_2gb_fast_exit_pd_ddr4     ||def_2400_4gb_fast_exit_pd_ddr4    );
-define  def_mba_tmr1q_cfg_tfaw_dly34  = (def_2133_8gb_fast_exit_pd_ddr4);
-define  def_mba_tmr1q_cfg_tfaw_dly38  = (def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4    );
-define  def_mba_tmr1q_cfg_tfaw_dly40  = (def_2400_8gb_fast_exit_pd_ddr4);
+define  def_mba_dsm0q_CFG_RODT_BC4_END_DLY9 = (def_mba_dsm0q_CFG_RODT_end_dly9);
+
+# old settings
+#define  def_mba_tmr1q_cfg_tfaw_dly20  = (def_1066_2gb                       ||def_1066_4gb                       ||def_1066_8gb                       ||def_1066_2gb_fast_exit_pd          ||def_1066_4gb_fast_exit_pd          ||def_1066_8gb_fast_exit_pd          ||def_1333_2gb                       ||def_1333_4gb                       ||def_1333_2gb_fast_exit_pd          ||def_1333_4gb_fast_exit_pd);
+#define  def_mba_tmr1q_cfg_tfaw_dly24  = (def_1600_2gb                       ||def_1600_4gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_4gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_4gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4     ||def_1600_4gb_fast_exit_pd_ddr4    );
+#define  def_mba_tmr1q_cfg_tfaw_dly29  = (def_1866_2gb                       ||def_1866_4gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_4gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_4gb_ddr4                  ||def_2133_2gb_ddr4                  ||def_2133_4gb_ddr4                  ||def_2400_2gb_ddr4                  ||def_2400_4gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4     ||def_1866_4gb_fast_exit_pd_ddr4    );
+#define  def_mba_tmr1q_cfg_tfaw_dly30  = (def_1333_8gb                       ||def_1333_8gb_fast_exit_pd          ||def_2133_2gb_fast_exit_pd_ddr4     ||def_2133_4gb_fast_exit_pd_ddr4    );
+#define  def_mba_tmr1q_cfg_tfaw_dly32  = (def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4     ||def_2400_2gb_fast_exit_pd_ddr4     ||def_2400_4gb_fast_exit_pd_ddr4    );
+#define  def_mba_tmr1q_cfg_tfaw_dly34  = (def_2133_8gb_fast_exit_pd_ddr4);
+#define  def_mba_tmr1q_cfg_tfaw_dly38  = (def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4    );
+#define  def_mba_tmr1q_cfg_tfaw_dly40  = (def_2400_8gb_fast_exit_pd_ddr4);
+
+define  def_mba_tmr1q_cfg_tfaw_dly20  = (def_1066_2gb                   ||def_1066_4gb                   ||def_1333_2gb                   ||def_1333_4gb                   ||def_1066_2gb_fast_exit_pd      ||def_1066_4gb_fast_exit_pd      ||def_1333_2gb_fast_exit_pd      ||def_1333_4gb_fast_exit_pd      ||def_1600_2gb_ddr4              ||def_1600_4gb_ddr4              ||def_1600_8gb_ddr4              ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 );
+define  def_mba_tmr1q_cfg_tfaw_dly22  = (def_1866_2gb_ddr4              ||def_1866_4gb_ddr4              ||def_1866_8gb_ddr4              ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 );
+define  def_mba_tmr1q_cfg_tfaw_dly23  = (def_2133_2gb_ddr4              ||def_2133_4gb_ddr4              ||def_2133_8gb_ddr4              ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 );
+define  def_mba_tmr1q_cfg_tfaw_dly24  = (def_1600_2gb                   ||def_1600_4gb                   ||def_1600_2gb_fast_exit_pd      ||def_1600_4gb_fast_exit_pd      );
+define  def_mba_tmr1q_cfg_tfaw_dly26  = (def_1866_2gb                   ||def_1866_4gb                   ||def_1866_2gb_fast_exit_pd      ||def_1866_4gb_fast_exit_pd      ||def_2400_2gb_ddr4              ||def_2400_4gb_ddr4              ||def_2400_8gb_ddr4              ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 );
+define  def_mba_tmr1q_cfg_tfaw_dly27  = (def_1066_8gb                   ||def_1066_8gb_fast_exit_pd      );
+define  def_mba_tmr1q_cfg_tfaw_dly30  = (def_1333_8gb                   ||def_1333_8gb_fast_exit_pd      );
+define  def_mba_tmr1q_cfg_tfaw_dly32  = (def_1600_8gb                   ||def_1600_8gb_fast_exit_pd      );
+define  def_mba_tmr1q_cfg_tfaw_dly33  = (def_1866_8gb                   ||def_1866_8gb_fast_exit_pd      );
 
 # 86,160,187
-define  def_MBAREF0Q_cfg_trfc_dly86  = (def_1066_2gb                       ||def_1066_2gb_fast_exit_pd);
-#define  def_MBAREF0Q_cfg_trfc_dly160 = (def_1066_4gb                       ||def_1066_4gb_fast_exit_pd);
-define  def_MBAREF0Q_cfg_trfc_dly187 = (def_1066_8gb                       ||def_1066_8gb_fast_exit_pd);
-
-define  def_MBAREF0Q_cfg_trfc_dly107 = (def_1333_2gb                       ||def_1333_2gb_fast_exit_pd);
-define  def_MBAREF0Q_cfg_trfc_dly128 = (def_1600_2gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly150 = (def_1866_2gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly160 = (def_1066_4gb                       ||def_1066_4gb_fast_exit_pd          ||def_2133_2gb_ddr4                  ||def_2133_2gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly180 = (def_2400_2gb_ddr4                  ||def_2400_2gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly200 = (def_1333_4gb                       ||def_1333_4gb_fast_exit_pd);
-define  def_MBAREF0Q_cfg_trfc_dly234 = (def_1333_8gb                       ||def_1333_8gb_fast_exit_pd);
-define  def_MBAREF0Q_cfg_trfc_dly240 = (def_1600_4gb                       ||def_1600_4gb_fast_exit_pd          ||def_1600_4gb_ddr4                  ||def_1600_4gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly260 = (def_2133_4gb_fast_exit_pd_ddr4);
-define  def_MBAREF0Q_cfg_trfc_dly265 = (def_2133_4gb_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly280 = (def_2400_4gb_ddr4                  ||def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4     ||def_2400_4gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly281 = (def_1866_4gb                       ||def_1866_4gb_fast_exit_pd          ||def_1866_4gb_ddr4                  ||def_1866_4gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly328 = (def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4    );
-define  def_MBAREF0Q_cfg_trfc_dly350 = (def_2133_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_2400_8gb_fast_exit_pd_ddr4    );
-
-# 3
-define  def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb                       ||def_1066_2gb_fast_exit_pd          ||def_1066_4gb                       ||def_1066_4gb_fast_exit_pd          ||def_1066_8gb                       ||def_1066_8gb_fast_exit_pd         );
-
-define  def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb                       ||def_1333_2gb_fast_exit_pd          ||def_1600_2gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4     ||def_1333_4gb                       ||def_1333_4gb_fast_exit_pd          ||def_1333_8gb                       ||def_1333_8gb_fast_exit_pd          ||def_1600_4gb                       ||def_1600_4gb_fast_exit_pd          ||def_1600_4gb_ddr4                  ||def_1600_4gb_fast_exit_pd_ddr4     ||def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4    );
-define  def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4     ||def_2133_2gb_ddr4                  ||def_2133_2gb_fast_exit_pd_ddr4     ||def_2400_2gb_ddr4                  ||def_2400_2gb_fast_exit_pd_ddr4     ||def_2133_4gb_fast_exit_pd_ddr4     ||def_2133_4gb_ddr4                  ||def_2400_4gb_ddr4                  ||def_2400_4gb_fast_exit_pd_ddr4     ||def_1866_4gb                       ||def_1866_4gb_fast_exit_pd          ||def_1866_4gb_ddr4                  ||def_1866_4gb_fast_exit_pd_ddr4     ||def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_2400_8gb_fast_exit_pd_ddr4    );
+# old
+#define  def_MBAREF0Q_cfg_trfc_dly86  = (def_1066_2gb                       ||def_1066_2gb_fast_exit_pd);
+##define  def_MBAREF0Q_cfg_trfc_dly160 = (def_1066_4gb                       ||def_1066_4gb_fast_exit_pd);
+#define  def_MBAREF0Q_cfg_trfc_dly187 = (def_1066_8gb                       ||def_1066_8gb_fast_exit_pd);
+#
+#define  def_MBAREF0Q_cfg_trfc_dly107 = (def_1333_2gb                       ||def_1333_2gb_fast_exit_pd);
+#define  def_MBAREF0Q_cfg_trfc_dly128 = (def_1600_2gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly150 = (def_1866_2gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly160 = (def_1066_4gb                       ||def_1066_4gb_fast_exit_pd          ||def_2133_2gb_ddr4                  ||def_2133_2gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly180 = (def_2400_2gb_ddr4                  ||def_2400_2gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly200 = (def_1333_4gb                       ||def_1333_4gb_fast_exit_pd);
+#define  def_MBAREF0Q_cfg_trfc_dly234 = (def_1333_8gb                       ||def_1333_8gb_fast_exit_pd);
+#define  def_MBAREF0Q_cfg_trfc_dly240 = (def_1600_4gb                       ||def_1600_4gb_fast_exit_pd          ||def_1600_4gb_ddr4                  ||def_1600_4gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly260 = (def_2133_4gb_fast_exit_pd_ddr4);
+#define  def_MBAREF0Q_cfg_trfc_dly265 = (def_2133_4gb_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly280 = (def_2400_4gb_ddr4                  ||def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4     ||def_2400_4gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly281 = (def_1866_4gb                       ||def_1866_4gb_fast_exit_pd          ||def_1866_4gb_ddr4                  ||def_1866_4gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly328 = (def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4    );
+#define  def_MBAREF0Q_cfg_trfc_dly350 = (def_2133_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_2400_8gb_fast_exit_pd_ddr4    );
+
+#new
+define  def_MBAREF0Q_cfg_trfc_dly86  = (def_1066_2gb                   || def_1066_2gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly107 = (def_1333_2gb                   || def_1333_2gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly128 = (def_1600_2gb_ddr4              || def_1600_2gb_fast_exit_pd_ddr4 || def_1600_2gb                   || def_1600_2gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly150 = (def_1866_2gb_ddr4              || def_1866_2gb_fast_exit_pd_ddr4 || def_1866_2gb                   || def_1866_2gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly160 = (def_1066_4gb                   || def_1066_4gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly171 = (def_2133_2gb_ddr4              || def_2133_2gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly187 = (def_1066_8gb                   || def_1066_8gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly192 = (def_2400_2gb_ddr4              || def_2400_2gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly200 = (def_1333_4gb                   || def_1333_4gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly208 = (def_1600_4gb_ddr4              || def_1600_4gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly234 = (def_1333_8gb                   || def_1333_8gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly240 = (def_1600_4gb                   || def_1600_4gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly243 = (def_1866_4gb_ddr4              || def_1866_4gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly278 = (def_2133_4gb_ddr4              || def_2133_4gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly280 = (def_1600_8gb_ddr4              || def_1600_8gb_fast_exit_pd_ddr4 || def_1600_8gb                   || def_1600_8gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly281 = (def_1866_4gb                   || def_1866_4gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly312 = (def_2400_4gb_ddr4              || def_2400_4gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly327 = (def_1866_8gb_ddr4              || def_1866_8gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly328 = (def_1866_8gb                   || def_1866_8gb_fast_exit_pd      );
+define  def_MBAREF0Q_cfg_trfc_dly374 = (def_2133_8gb_ddr4              || def_2133_8gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_trfc_dly420 = (def_2400_8gb_ddr4              || def_2400_8gb_fast_exit_pd_ddr4 );
+
+
+#
+define  def_MBAREF0Q_cfg_refr_tsv_stack_dly32 = (def_1066_2gb                   || def_1333_2gb                   || def_1600_2gb                   || def_1866_2gb                   || def_1066_2gb_fast_exit_pd      || def_1333_2gb_fast_exit_pd      || def_1600_2gb_fast_exit_pd      || def_1866_2gb_fast_exit_pd      || def_1600_2gb_ddr4              || def_1866_2gb_ddr4              || def_2133_2gb_ddr4              || def_2400_2gb_ddr4              || def_1600_2gb_fast_exit_pd_ddr4 || def_1866_2gb_fast_exit_pd_ddr4 || def_2133_2gb_fast_exit_pd_ddr4 || def_2400_2gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_refr_tsv_stack_dly48 = (def_1066_4gb                   || def_1333_4gb                   || def_1600_4gb                   || def_1866_4gb                   || def_1066_4gb_fast_exit_pd      || def_1333_4gb_fast_exit_pd      || def_1600_4gb_fast_exit_pd      || def_1866_4gb_fast_exit_pd      || def_1600_4gb_ddr4              || def_1866_4gb_ddr4              || def_2133_4gb_ddr4              || def_2400_4gb_ddr4              || def_1600_4gb_fast_exit_pd_ddr4 || def_1866_4gb_fast_exit_pd_ddr4 || def_2133_4gb_fast_exit_pd_ddr4 || def_2400_4gb_fast_exit_pd_ddr4 );
+define  def_MBAREF0Q_cfg_refr_tsv_stack_dly64 = (def_1066_8gb                   || def_1333_8gb                   || def_1600_8gb                   || def_1866_8gb                   || def_1066_8gb_fast_exit_pd      || def_1333_8gb_fast_exit_pd      || def_1600_8gb_fast_exit_pd      || def_1866_8gb_fast_exit_pd      || def_1600_8gb_ddr4              || def_1866_8gb_ddr4              || def_2133_8gb_ddr4              || def_2400_8gb_ddr4              || def_1600_8gb_fast_exit_pd_ddr4 || def_1866_8gb_fast_exit_pd_ddr4 || def_2133_8gb_fast_exit_pd_ddr4 || def_2400_8gb_fast_exit_pd_ddr4 );
+
+# 3 -- old
+#define  def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb                       ||def_1066_2gb_fast_exit_pd          ||def_1066_4gb                       ||def_1066_4gb_fast_exit_pd          ||def_1066_8gb                       ||def_1066_8gb_fast_exit_pd         );
+#
+#define  def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb                       ||def_1333_2gb_fast_exit_pd          ||def_1600_2gb                       ||def_1600_2gb_fast_exit_pd          ||def_1600_2gb_ddr4                  ||def_1600_2gb_fast_exit_pd_ddr4     ||def_1333_4gb                       ||def_1333_4gb_fast_exit_pd          ||def_1333_8gb                       ||def_1333_8gb_fast_exit_pd          ||def_1600_4gb                       ||def_1600_4gb_fast_exit_pd          ||def_1600_4gb_ddr4                  ||def_1600_4gb_fast_exit_pd_ddr4     ||def_1600_8gb                       ||def_1600_8gb_fast_exit_pd          ||def_1600_8gb_ddr4                  ||def_1600_8gb_fast_exit_pd_ddr4    );
+#define  def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb                       ||def_1866_2gb_fast_exit_pd          ||def_1866_2gb_ddr4                  ||def_1866_2gb_fast_exit_pd_ddr4     ||def_2133_2gb_ddr4                  ||def_2133_2gb_fast_exit_pd_ddr4     ||def_2400_2gb_ddr4                  ||def_2400_2gb_fast_exit_pd_ddr4     ||def_2133_4gb_fast_exit_pd_ddr4     ||def_2133_4gb_ddr4                  ||def_2400_4gb_ddr4                  ||def_2400_4gb_fast_exit_pd_ddr4     ||def_1866_4gb                       ||def_1866_4gb_fast_exit_pd          ||def_1866_4gb_ddr4                  ||def_1866_4gb_fast_exit_pd_ddr4     ||def_1866_8gb                       ||def_1866_8gb_fast_exit_pd          ||def_1866_8gb_ddr4                  ||def_1866_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_fast_exit_pd_ddr4     ||def_2133_8gb_ddr4                  ||def_2400_8gb_ddr4                  ||def_2400_8gb_fast_exit_pd_ddr4    );
+
+# new
+define  def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb                   ||def_1066_4gb                   ||def_1066_8gb                   ||def_1066_2gb_fast_exit_pd      ||def_1066_4gb_fast_exit_pd      ||def_1066_8gb_fast_exit_pd      );
+define  def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb                   ||def_1333_4gb                   ||def_1333_8gb                   ||def_1600_2gb                   ||def_1600_4gb                   ||def_1600_8gb                   ||def_1333_2gb_fast_exit_pd      ||def_1333_4gb_fast_exit_pd      ||def_1333_8gb_fast_exit_pd      ||def_1600_2gb_fast_exit_pd      ||def_1600_4gb_fast_exit_pd      ||def_1600_8gb_fast_exit_pd      ||def_1600_2gb_ddr4              ||def_1600_4gb_ddr4              ||def_1600_8gb_ddr4              ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb                   ||def_1866_4gb                   ||def_1866_8gb                   ||def_1866_2gb_fast_exit_pd      ||def_1866_4gb_fast_exit_pd      ||def_1866_8gb_fast_exit_pd      ||def_1866_2gb_ddr4              ||def_1866_4gb_ddr4              ||def_1866_8gb_ddr4              ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_pdn_dly6 = (def_2133_2gb_ddr4              ||def_2133_4gb_ddr4              ||def_2133_8gb_ddr4              ||def_2400_2gb_ddr4              ||def_2400_4gb_ddr4              ||def_2400_8gb_ddr4              ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 );
 
 #3
 #define  def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_1066_2gb                       ||def_1066_2gb_fast_exit_pd          ||def_1066_4gb                       ||def_1066_4gb_fast_exit_pd          ||def_1066_8gb                       ||def_1066_8gb_fast_exit_pd         );
@@ -661,16 +888,31 @@ define  def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_MBARPC0Q_cfg_pup_pdn_dly3);
 
 define  def_MBARPC0Q_cfg_pdn_pup_dly4 = (def_MBARPC0Q_cfg_pup_pdn_dly4);
 define  def_MBARPC0Q_cfg_pdn_pup_dly5 = (def_MBARPC0Q_cfg_pup_pdn_dly5);
+define  def_MBARPC0Q_cfg_pdn_pup_dly6 = (def_MBARPC0Q_cfg_pup_pdn_dly6);
 
-# 13
-define  def_MBARPC0Q_cfg_pup_avail_dly13 = (def_1066_2gb                       )||(def_1066_4gb                       )||(def_1066_8gb);
+# 13 -- old
+#define  def_MBARPC0Q_cfg_pup_avail_dly13 = (def_1066_2gb                       )||(def_1066_4gb                       )||(def_1066_8gb);
+#
+#define  def_MBARPC0Q_cfg_pup_avail_dly4  = ((def_1066_2gb_fast_exit_pd          )||(def_1066_4gb_fast_exit_pd          )||(def_1066_8gb_fast_exit_pd          )||(def_1333_2gb_fast_exit_pd          )||(def_1333_4gb_fast_exit_pd          )||(def_1333_8gb_fast_exit_pd));
+#define  def_MBARPC0Q_cfg_pup_avail_dly5  = ((def_1600_2gb_fast_exit_pd          )||(def_1600_2gb_fast_exit_pd_ddr4     )||(def_1600_4gb_fast_exit_pd          )||(def_1600_4gb_fast_exit_pd_ddr4     )||(def_1600_8gb_fast_exit_pd          )||(def_1600_8gb_fast_exit_pd_ddr4    ));
+#define  def_MBARPC0Q_cfg_pup_avail_dly6  = ((def_1866_2gb_fast_exit_pd          )||(def_1866_2gb_fast_exit_pd_ddr4     )||(def_2133_2gb_fast_exit_pd_ddr4     )||(def_2400_2gb_fast_exit_pd_ddr4     )||(def_2133_4gb_fast_exit_pd_ddr4     )||(def_2400_4gb_fast_exit_pd_ddr4     )||(def_1866_4gb_fast_exit_pd          )||(def_1866_4gb_fast_exit_pd_ddr4     )||(def_1866_8gb_fast_exit_pd          )||(def_1866_8gb_fast_exit_pd_ddr4     )||(def_2133_8gb_fast_exit_pd_ddr4     )||(def_2400_8gb_fast_exit_pd_ddr4    ));
+#define  def_MBARPC0Q_cfg_pup_avail_dly16 = ((def_1333_2gb                       )||(def_1333_4gb                       )||(def_1333_8gb));
+#define  def_MBARPC0Q_cfg_pup_avail_dly20 = ((def_1600_2gb                       )||(def_1600_2gb_ddr4                  )||(def_1600_4gb                       )||(def_1600_4gb_ddr4                  )||(def_1600_8gb                       )||(def_1600_8gb_ddr4    ));
+#define  def_MBARPC0Q_cfg_pup_avail_dly23 = ((def_1866_2gb                       )||(def_1866_2gb_ddr4                  )||(def_2133_2gb_ddr4                  )||(def_2400_2gb_ddr4                  )||(def_2133_4gb_ddr4                  )||(def_2400_4gb_ddr4                  )||(def_1866_4gb                       )||(def_1866_4gb_ddr4                  )||(def_1866_8gb                       )||(def_1866_8gb_ddr4                  )||(def_2133_8gb_ddr4                  )||(def_2400_8gb_ddr4    ));
+
+# new
+define  def_MBARPC0Q_cfg_pup_avail_dly4  = (        def_1066_2gb_fast_exit_pd      ||def_1066_4gb_fast_exit_pd      ||def_1066_8gb_fast_exit_pd      ||def_1333_2gb_fast_exit_pd      ||def_1333_4gb_fast_exit_pd      ||def_1333_8gb_fast_exit_pd      );
+define  def_MBARPC0Q_cfg_pup_avail_dly5  = (        def_1600_2gb_fast_exit_pd      ||def_1600_4gb_fast_exit_pd      ||def_1600_8gb_fast_exit_pd      ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_avail_dly6  = (        def_1866_2gb_fast_exit_pd      ||def_1866_4gb_fast_exit_pd      ||def_1866_8gb_fast_exit_pd      ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_avail_dly7  = (        def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_avail_dly8  = (        def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 );
+define  def_MBARPC0Q_cfg_pup_avail_dly13 = (        def_1066_2gb                   ||def_1066_4gb                   ||def_1066_8gb                   );
+define  def_MBARPC0Q_cfg_pup_avail_dly16 = (        def_1333_2gb                   ||def_1333_4gb                   ||def_1333_8gb                   );
+define  def_MBARPC0Q_cfg_pup_avail_dly20 = (        def_1600_2gb                   ||def_1600_4gb                   ||def_1600_8gb                   ||def_1600_2gb_ddr4              ||def_1600_4gb_ddr4              ||def_1600_8gb_ddr4              );
+define  def_MBARPC0Q_cfg_pup_avail_dly23 = (        def_1866_2gb                   ||def_1866_4gb                   ||def_1866_8gb                   ||def_1866_2gb_ddr4              ||def_1866_4gb_ddr4              ||def_1866_8gb_ddr4              );
+define  def_MBARPC0Q_cfg_pup_avail_dly26 = (        def_2133_2gb_ddr4              ||def_2133_4gb_ddr4              ||def_2133_8gb_ddr4              );
+define  def_MBARPC0Q_cfg_pup_avail_dly29 = (        def_2400_2gb_ddr4              ||def_2400_4gb_ddr4              ||def_2400_8gb_ddr4              );
 
-define  def_MBARPC0Q_cfg_pup_avail_dly4  = ((def_1066_2gb_fast_exit_pd          )||(def_1066_4gb_fast_exit_pd          )||(def_1066_8gb_fast_exit_pd          )||(def_1333_2gb_fast_exit_pd          )||(def_1333_4gb_fast_exit_pd          )||(def_1333_8gb_fast_exit_pd));
-define  def_MBARPC0Q_cfg_pup_avail_dly5  = ((def_1600_2gb_fast_exit_pd          )||(def_1600_2gb_fast_exit_pd_ddr4     )||(def_1600_4gb_fast_exit_pd          )||(def_1600_4gb_fast_exit_pd_ddr4     )||(def_1600_8gb_fast_exit_pd          )||(def_1600_8gb_fast_exit_pd_ddr4    ));
-define  def_MBARPC0Q_cfg_pup_avail_dly6  = ((def_1866_2gb_fast_exit_pd          )||(def_1866_2gb_fast_exit_pd_ddr4     )||(def_2133_2gb_fast_exit_pd_ddr4     )||(def_2400_2gb_fast_exit_pd_ddr4     )||(def_2133_4gb_fast_exit_pd_ddr4     )||(def_2400_4gb_fast_exit_pd_ddr4     )||(def_1866_4gb_fast_exit_pd          )||(def_1866_4gb_fast_exit_pd_ddr4     )||(def_1866_8gb_fast_exit_pd          )||(def_1866_8gb_fast_exit_pd_ddr4     )||(def_2133_8gb_fast_exit_pd_ddr4     )||(def_2400_8gb_fast_exit_pd_ddr4    ));
-define  def_MBARPC0Q_cfg_pup_avail_dly16 = ((def_1333_2gb                       )||(def_1333_4gb                       )||(def_1333_8gb));
-define  def_MBARPC0Q_cfg_pup_avail_dly20 = ((def_1600_2gb                       )||(def_1600_2gb_ddr4                  )||(def_1600_4gb                       )||(def_1600_4gb_ddr4                  )||(def_1600_8gb                       )||(def_1600_8gb_ddr4    ));
-define  def_MBARPC0Q_cfg_pup_avail_dly23 = ((def_1866_2gb                       )||(def_1866_2gb_ddr4                  )||(def_2133_2gb_ddr4                  )||(def_2400_2gb_ddr4                  )||(def_2133_4gb_ddr4                  )||(def_2400_4gb_ddr4                  )||(def_1866_4gb                       )||(def_1866_4gb_ddr4                  )||(def_1866_8gb                       )||(def_1866_8gb_ddr4                  )||(def_2133_8gb_ddr4                  )||(def_2400_8gb_ddr4    ));
 
 define  def_MBA_TMR0Q_Trrd_dly4 = ((def_1066_2gb                       )||(def_1066_2gb_fast_exit_pd          )||(def_1066_4gb                       )||(def_1066_4gb_fast_exit_pd          )||(def_1066_8gb                       )||(def_1066_8gb_fast_exit_pd         )||(def_1333_2gb                       )||(def_1333_2gb_fast_exit_pd          )||(def_1600_2gb_ddr4                  )||(def_1600_2gb_fast_exit_pd_ddr4     )||(def_1866_2gb_ddr4                  )||(def_1866_2gb_fast_exit_pd_ddr4     )||(def_2133_2gb_ddr4                  )||(def_2133_2gb_fast_exit_pd_ddr4     )||(def_2400_2gb_ddr4                  )||(def_2400_2gb_fast_exit_pd_ddr4     )||(def_1333_4gb                       )||(def_1333_4gb_fast_exit_pd          )||(def_1600_4gb_ddr4                  )||(def_1600_4gb_fast_exit_pd_ddr4     )||(def_2133_4gb_fast_exit_pd_ddr4     )||(def_2133_4gb_ddr4                  )||(def_2400_4gb_ddr4                  )||(def_1600_8gb_ddr4                  )||(def_1600_8gb_fast_exit_pd_ddr4     )||(def_2400_4gb_fast_exit_pd_ddr4     )||(def_1866_4gb_ddr4                  )||(def_1866_4gb_fast_exit_pd_ddr4     )||(def_1866_8gb_ddr4                  )||(def_1866_8gb_fast_exit_pd_ddr4     )||(def_2133_8gb_fast_exit_pd_ddr4     )||(def_2133_8gb_ddr4                  )||(def_2400_8gb_ddr4                  )||(def_2400_8gb_fast_exit_pd_ddr4    ));
 define  def_MBA_TMR0Q_Trrd_dly5 = ((def_1600_2gb                       )||(def_1600_2gb_fast_exit_pd          )||(def_1333_8gb                       )||(def_1333_8gb_fast_exit_pd          )||(def_1600_4gb                       )||(def_1600_4gb_fast_exit_pd));
@@ -695,19 +937,739 @@ define  def_odt_mapping_5d1dimm      = (def_5d_1socket);
 define  def_odt_mapping_5d2dimm      = (def_5d_2socket);
 
 
+## MCBIST address map defines
+## cols
+define  def_mcb_addr_col13_29 =  (ATTR_EFF_DRAM_COLS == 12);
+define  def_mcb_addr_unset_col13 = ((ATTR_EFF_DRAM_COLS == 10) || (ATTR_EFF_DRAM_COLS == 11));
+
+define  def_mcb_addr_col11_30 = ((ATTR_EFF_DRAM_COLS == 11) || (ATTR_EFF_DRAM_COLS == 12));
+define  def_mcb_addr_unset_col11 =  (ATTR_EFF_DRAM_COLS == 10);
+
+
+## banks
+define  def_mcb_addr_bank3_27 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16));
+define  def_mcb_addr_bank3_26 =  ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16));
+define  def_mcb_addr_bank3_25 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16));
+define  def_mcb_addr_unset_bank3 =  (ATTR_EFF_DRAM_BANKS == 8);
+
+define  def_mcb_addr_bank2_28 =  ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank2_27 =  ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank2_26 =  ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+
+define  def_mcb_addr_bank1_29 =  ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank1_28 =  ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank1_27 =  ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+
+define  def_mcb_addr_bank0_30 =  ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank0_29 =  ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+define  def_mcb_addr_bank0_28 =  ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8)));
+
+## Rows
+define  def_mcb_addr_row16_11 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17));
+define  def_mcb_addr_row16_10 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row16_9  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row16_8  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17));
+define  def_mcb_addr_unset_row16 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16));
+
+define  def_mcb_addr_row15_12 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row15_11 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row15_10 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row15_9  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_unset_row15 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15));
+
+define  def_mcb_addr_row14_13 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row14_12 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row14_11 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row14_10 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_unset_row14 =  (ATTR_EFF_DRAM_ROWS == 14);
+
+define  def_mcb_addr_row13_14 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row13_13 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row13_12 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row13_11 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row12_15 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row12_14 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row12_13 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row12_12 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row11_16 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row11_15 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row11_14 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row11_13 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row10_17 =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row10_16 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row10_15 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row10_14 =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row9_18  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row9_17  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row9_16  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row9_15  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row8_19  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row8_18  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row8_17  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row8_16  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row7_20  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row7_19  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row7_18  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row7_17  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row6_21  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row6_20  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row6_19  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row6_18  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row5_22  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row5_21  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row5_20  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row5_19  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row4_23  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row4_22  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row4_21  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row4_20  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row3_24  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row3_23  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row3_22  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row3_21  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row2_25  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row2_24  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row2_23  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row2_22  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row1_26  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row1_25  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row1_24  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row1_23  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row0_27  =  ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row0_26  = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row0_25  = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))));
+define  def_mcb_addr_row0_24  =  ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)));
+
+
+define  def_mcb_srank0_unset    = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8);
+define  def_mcb_srank1_unset    = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4);
+define  def_mcb_srank2_unset    = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2);
+
+## SRANKS
+#############################################  SRANK bits Col = 10 , banks = 16
+define  def_mcb_addr_col10_bnk16_srank2_12  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk16_srank1_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk16_srank0_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk16_srank2_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk16_srank1_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk16_srank0_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk16_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk16_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk16_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk16_srank2_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col10_bnk16_srank1_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col10_bnk16_srank0_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   SRANK bits Col = 10 , banks = 8
+define  def_mcb_addr_col10_bnk8_srank2_13  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk8_srank1_12  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk8_srank0_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col10_bnk8_srank2_12  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk8_srank1_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk8_srank0_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col10_bnk8_srank2_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk8_srank1_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk8_srank0_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col10_bnk8_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col10_bnk8_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col10_bnk8_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################  SRANK bits Col = 11 , banks = 16
+define  def_mcb_addr_col11_bnk16_srank2_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk16_srank1_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk16_srank0_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk16_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk16_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk16_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk16_srank2_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk16_srank1_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk16_srank0_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk16_srank2_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col11_bnk16_srank1_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col11_bnk16_srank0_6   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   SRANK bits Col = 11 , banks = 8
+define  def_mcb_addr_col11_bnk8_srank2_12  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk8_srank1_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk8_srank0_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col11_bnk8_srank2_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk8_srank1_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk8_srank0_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col11_bnk8_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk8_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk8_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col11_bnk8_srank2_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col11_bnk8_srank1_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col11_bnk8_srank0_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################  SRANK bits Col = 12 , banks = 16
+define  def_mcb_addr_col12_bnk16_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col12_bnk16_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col12_bnk16_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col12_bnk16_srank2_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col12_bnk16_srank1_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col12_bnk16_srank0_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col12_bnk16_srank2_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk16_srank1_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk16_srank0_6   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk16_srank2_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col12_bnk16_srank1_6   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col12_bnk16_srank0_5   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   SRANK bits Col = 12 , banks = 8
+define  def_mcb_addr_col12_bnk8_srank2_11  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_col12_bnk8_srank1_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
 
+define  def_mcb_addr_col12_bnk8_srank0_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14)));
 
-## Temp defines until the code adds these attributes
-#define  def_ATTR_MSS_CACHE_ENABLE = 0;                                   # cache disable
-#define  def_ATTR_MSS_PREFETCH_ENABLE = 0;                                # prefetch disable
-#define  def_ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT = 0;                        # no MBA interleave
-#define  def_01ATTR_MSS_HASH_MODE = 1;
-#define  def_23ATTR_MSS_HASH_MODE = 0;
-#define  def_01ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
-#define  def_23ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
-#define  def_01ATTR_EFF_MBA_POS = 0;
-#define  def_23ATTR_EFF_MBA_POS = 1;
+define  def_mcb_addr_col12_bnk8_srank2_10  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
 
+define  def_mcb_addr_col12_bnk8_srank1_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col12_bnk8_srank0_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_col12_bnk8_srank2_9   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk8_srank1_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk8_srank0_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_col12_bnk8_srank2_8   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col12_bnk8_srank1_7   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_col12_bnk8_srank0_6   = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+### MRANKS
+
+define  def_mcb_mrank1_unset    = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8);
+define  def_mcb_mrank2_unset    = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4);
+define  def_mcb_mrank3_unset    = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 0);
+
+#############################################  MRANK bits Col = 10 , banks = 16
+define  def_mcb_addr_row14_col10_bnk16_mrank3_12  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank2_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank1_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk16_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col10_bnk16_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row16_col10_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col10_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   MRANK bits Col = 10 , banks = 8
+define  def_mcb_addr_row14_col10_bnk8_mrank3_13  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank2_12  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank1_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk8_mrank3_12  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank2_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank1_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col10_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col10_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col10_bnk8_mrank3_12  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank2_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank1_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col10_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col10_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+
+define  def_mcb_addr_row16_col10_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col10_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col10_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col10_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col10_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col10_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################  MRANK bits Col = 11 , banks = 16
+define  def_mcb_addr_row14_col11_bnk16_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col11_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row16_col11_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col11_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk16_mrank3_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank2_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk16_mrank1_3   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   MRANK bits Col = 11 , banks = 8
+define  def_mcb_addr_row14_col11_bnk8_mrank3_12  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank2_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank1_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col11_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col11_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col11_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col11_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col11_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row16_col11_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col11_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col11_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col11_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col11_bnk8_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col11_bnk8_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################  MRANK bits Col = 12 , banks = 16
+define  def_mcb_addr_row14_col12_bnk16_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col12_bnk16_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row16_col12_bnk16_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk16_mrank3_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank2_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk16_mrank1_3   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col12_bnk16_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk16_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk16_mrank3_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank2_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank1_3   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk16_mrank3_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank2_3   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk16_mrank1_2   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+#############################################   MRANK bits Col = 12 , banks = 8
+define  def_mcb_addr_row14_col12_bnk8_mrank3_11  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank2_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank1_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row14_col12_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+define  def_mcb_addr_row14_col12_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14)));
+
+define  def_mcb_addr_row15_col12_bnk8_mrank3_10  = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank2_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank1_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row15_col12_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+define  def_mcb_addr_row15_col12_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15)));
+
+define  def_mcb_addr_row16_col12_bnk8_mrank3_9   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank2_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank1_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row16_col12_bnk8_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+define  def_mcb_addr_row16_col12_bnk8_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16)));
+
+define  def_mcb_addr_row17_col12_bnk8_mrank3_8   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank2_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank1_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk8_mrank3_7   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank2_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank1_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk8_mrank3_6   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank2_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank1_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+define  def_mcb_addr_row17_col12_bnk8_mrank3_5   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank2_4   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+define  def_mcb_addr_row17_col12_bnk8_mrank1_3   = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17)));
+
+# ADDRESS setup for different SCHMOO setting
+define  def_mcb_addr_total28_max28  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 ));
+define  def_mcb_addr_total28_max29  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 ));
+define  def_mcb_addr_total28_max30  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 ));
+define  def_mcb_addr_total28_max31  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 ));
+
+define  def_mcb_addr_total27_max27  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 ));
+define  def_mcb_addr_total27_max28  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 ));
+define  def_mcb_addr_total27_max29  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 ));
+define  def_mcb_addr_total27_max30  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 ));
+
+define  def_mcb_addr_total26_max26  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 ));
+define  def_mcb_addr_total26_max27  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 ));
+define  def_mcb_addr_total26_max28  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 ));
+define  def_mcb_addr_total26_max29  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 ));
+
+define  def_mcb_addr_total25_max25  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 ));
+define  def_mcb_addr_total25_max26  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 ));
+define  def_mcb_addr_total25_max27  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 ));
+define  def_mcb_addr_total25_max28  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 ));
+
+define  def_mcb_addr_total24_max24  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 ));
+define  def_mcb_addr_total24_max25  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 ));
+define  def_mcb_addr_total24_max26  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 ));
+define  def_mcb_addr_total24_max27  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 ));
+
+define  def_mcb_addr_total23_max23  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 ));
+define  def_mcb_addr_total23_max24  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 ));
+define  def_mcb_addr_total23_max25  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 ));
+define  def_mcb_addr_total23_max26  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 ));
+
+define  def_mcb_addr_total22_max22  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) <  2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 ));
+define  def_mcb_addr_total22_max23  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 ));
+define  def_mcb_addr_total22_max24  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 ));
+define  def_mcb_addr_total22_max25  = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 ));
+
+#######################################
+#MBA01 MBASRQ Base Address:  0x03010416
+#MBA23 MBASRQ Base Address:  0x03010C16
+#######################################
+#
+#Register Name	N/M Throttling Control
+#Mnemonic	MBA_FARB3Q
+#Attributes	PAR:EVEN	Bit	Field Mnemonic	Attribute or Setting to use
+#Description	N/M throttling control (Centaur only)
+#		0:14	cfg_nm_n_per_mba	MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
+#		15:30	cfg_nm_n_per_chip	MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
+#		31:44	cfg_nm_m	MSS_MEM_THROTTLE_DENOMINATOR
+#		51	cfg_nm_per_slot_enabled	1
+#		52	cfg_nm_count_other_mba_dis	Set to 0 for CDIMM, Set to 1 for everything else
+
+
+scom 0x03010416     {
+    bits    ,   scom_data                                 ,       ATTR_FUNCTIONAL,     expr;
+    0:14    ,   ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA   ,            1            ,     any;          # cfg_nm_n_per_mba	MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
+    15:30   ,   ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP  ,            1            ,     any;          # cfg_nm_n_per_chip	MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
+    31:44   ,   ATTR_MSS_MEM_THROTTLE_DENOMINATOR         ,            1            ,     any;          # cfg_nm_m	MSS_MEM_THROTTLE_DENOMINATOR
+    51      ,   0b1                                       ,            1            ,     any;          # cfg_nm_per_slot_enabled	1
+    52      ,   0b0                                       ,            1            ,     (ATTR_EFF_DIMM_TYPE == 0);          # cfg_nm_count_other_mba_dis	Set to 0 for CDIMM, Set to 1 for everything else
+    52      ,   0b1                                       ,            1            ,     ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 2) || (ATTR_EFF_DIMM_TYPE == 3));          # cfg_nm_count_other_mba_dis	Set to 0 for CDIMM, Set to 1 for everything else
+}
+
+# ATTR_EFF_DIMM_TYPE
+# CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
 ###################################
 # Turn on DDR PHY clks
 ###################################
@@ -715,9 +1677,12 @@ define  def_odt_mapping_5d2dimm      = (def_5d_2socket);
 # Turn on DDR phy clk p and n
 
 scom 0x030106A7     {
-    bits    ,   scom_data   , expr;
-    4:5     ,   0b01, any;          # ddr_dphy_nclk  00 = off , 01 = on
-    6:7     ,   0b10, any;          # ddr_dphy_pclk  00 = off , 10 = on
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    4:5     ,   0b01        ,            1            ,     any;          # ddr_dphy_nclk  00 = off , 01 = on
+    6:7     ,   0b10        ,            1            ,     any;          # ddr_dphy_pclk  00 = off , 10 = on
+	52		,	0b1			,			 1			  ,		any;		  # RAS# high
+	53		,	0b1			,			 1			  ,		any;		  # CAS# high
+	54		,	0b1			,			 1			  ,		any;		  # WE# high
 }
 
 
@@ -729,176 +1694,176 @@ scom 0x030106A7     {
 # MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming
 #
 scom 0x03010414     {
-    bits    ,   scom_data   , expr;
-    0:5     ,   0b011100, (def_C3b                                == 1);          # cfg_M0S0_cs
-    0:5     ,   0b011100, (def_C3c                                == 1);          # cfg_M0S0_cs
-    0:5     ,   0b010000, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S0_cs
-    0:5     ,   0b010100, (def_C4A_ddr4                           == 1);          # cfg_M0S0_cs
-    0:5     ,   0b011100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S0_cs
-    0:5     ,   0b010000, (def_IS3b_IS7b                          == 1);          # cfg_M0S0_cs
-    0:5     ,   0b010000, (def_IS5D                               == 1);          # cfg_M0S0_cs
-    0:5     ,   0b010000, (def_IS7C                               == 1);          # cfg_M0S0_cs
-    0:5     ,   0b011100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S0_cs
-    6:11    ,   0b101100, (def_C3b                                == 1);          # cfg_M0S1_cs
-    6:11    ,   0b101100, (def_C3c                                == 1);          # cfg_M0S1_cs
-    6:11    ,   0b011000, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S1_cs
-    6:11    ,   0b011100, (def_C4A_ddr4                           == 1);          # cfg_M0S1_cs
-    6:11    ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S1_cs
-    6:11    ,   0b011000, (def_IS3b_IS7b                          == 1);          # cfg_M0S1_cs
-    6:11    ,   0b011000, (def_IS5D                               == 1);          # cfg_M0S1_cs
-    6:11    ,   0b011000, (def_IS7C                               == 1);          # cfg_M0S1_cs
-    6:11    ,   0b110100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S1_cs
-    12:17   ,   0b110100, (def_C3b                                == 1);          # cfg_M0S2_cs
-    12:17   ,   0b110100, (def_C3c                                == 1);          # cfg_M0S2_cs
-    12:17   ,   0b010100, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S2_cs
-    12:17   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S2_cs
-    12:17   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S2_cs
-    12:17   ,   0b010100, (def_IS3b_IS7b                          == 1);          # cfg_M0S2_cs
-    12:17   ,   0b010100, (def_IS5D                               == 1);          # cfg_M0S2_cs
-    12:17   ,   0b010100, (def_IS7C                               == 1);          # cfg_M0S2_cs
-    12:17   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S2_cs
-    18:23   ,   0b111000, (def_C3b                                == 1);          # cfg_M0S3_cs
-    18:23   ,   0b111000, (def_C3c                                == 1);          # cfg_M0S3_cs
-    18:23   ,   0b011100, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S3_cs
-    18:23   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S3_cs
-    18:23   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S3_cs
-    18:23   ,   0b011100, (def_IS3b_IS7b                          == 1);          # cfg_M0S3_cs
-    18:23   ,   0b011100, (def_IS5D                               == 1);          # cfg_M0S3_cs
-    18:23   ,   0b011100, (def_IS7C                               == 1);          # cfg_M0S3_cs
-    18:23   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S3_cs
-    24:29   ,   0b111100, (def_C3b                                == 1);          # cfg_M0S4_cs
-    24:29   ,   0b011110, (def_C3c                                == 1);          # cfg_M0S4_cs
-    24:29   ,   0b010001, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S4_cs
-    24:29   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S4_cs
-    24:29   ,   0b110100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S4_cs
-    24:29   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M0S4_cs
-    24:29   ,   0b100000, (def_IS5D                               == 1);          # cfg_M0S4_cs
-    24:29   ,   0b010010, (def_IS7C                               == 1);          # cfg_M0S4_cs
-    24:29   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S4_cs
-    30:35   ,   0b111100, (def_C3b                                == 1);          # cfg_M0S5_cs
-    30:35   ,   0b101110, (def_C3c                                == 1);          # cfg_M0S5_cs
-    30:35   ,   0b011001, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S5_cs
-    30:35   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S5_cs
-    30:35   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S5_cs
-    30:35   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M0S5_cs
-    30:35   ,   0b101000, (def_IS5D                               == 1);          # cfg_M0S5_cs
-    30:35   ,   0b011010, (def_IS7C                               == 1);          # cfg_M0S5_cs
-    30:35   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S5_cs
-    36:41   ,   0b111100, (def_C3b                                == 1);          # cfg_M0S6_cs
-    36:41   ,   0b110110, (def_C3c                                == 1);          # cfg_M0S6_cs
-    36:41   ,   0b010101, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S6_cs
-    36:41   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S6_cs
-    36:41   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S6_cs
-    36:41   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M0S6_cs
-    36:41   ,   0b100100, (def_IS5D                               == 1);          # cfg_M0S6_cs
-    36:41   ,   0b010110, (def_IS7C                               == 1);          # cfg_M0S6_cs
-    36:41   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S6_cs
-    42:47   ,   0b111100, (def_C3b                                == 1);          # cfg_M0S7_cs
-    42:47   ,   0b111010, (def_C3c                                == 1);          # cfg_M0S7_cs
-    42:47   ,   0b011101, (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S7_cs
-    42:47   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M0S7_cs
-    42:47   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S7_cs
-    42:47   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M0S7_cs
-    42:47   ,   0b101100, (def_IS5D                               == 1);          # cfg_M0S7_cs
-    42:47   ,   0b011110, (def_IS7C                               == 1);          # cfg_M0S7_cs
-    42:47   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S7_cs
-    48:51   ,   0b1111,   (def_C3b                                == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1111,   (def_C3c                                == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1100,   (def_C3c_C4C_ddr4                       == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1101,   (def_C4A_ddr4                           == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1111,   (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1100,   (def_IS3b_IS7b                          == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1100,   (def_IS5D                               == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1100,   (def_IS7C                               == 1);          # cfg_cs_s0_mask
-    48:51   ,   0b1111,   (def_IS7a_C4a_C3a                       == 1);          # cfg_cs_s0_mask
-    52      ,   0b0   ,   (def_C3b                                == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_C3c                                == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_C3c_C4C_ddr4                       == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_C4A_ddr4                           == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_IS3b_IS7b                          == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b1   ,   (def_IS5D                               == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_IS7C                               == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
-    52      ,   0b0   ,   (def_IS7a_C4a_C3a                       == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,    expr;
+    0:5     ,   0b011100,             1            ,      (def_C3b                                == 1);          # cfg_M0S0_cs
+    0:5     ,   0b011100,             1            ,      (def_C3c                                == 1);          # cfg_M0S0_cs
+    0:5     ,   0b010000,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S0_cs
+    0:5     ,   0b010100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S0_cs
+    0:5     ,   0b011100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S0_cs
+    0:5     ,   0b010000,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S0_cs
+    0:5     ,   0b010000,             1            ,      (def_IS5D                               == 1);          # cfg_M0S0_cs
+    0:5     ,   0b010000,             1            ,      (def_IS7C                               == 1);          # cfg_M0S0_cs
+    0:5     ,   0b011100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S0_cs
+    6:11    ,   0b101100,             1            ,      (def_C3b                                == 1);          # cfg_M0S1_cs
+    6:11    ,   0b101100,             1            ,      (def_C3c                                == 1);          # cfg_M0S1_cs
+    6:11    ,   0b011000,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S1_cs
+    6:11    ,   0b011100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S1_cs
+    6:11    ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S1_cs
+    6:11    ,   0b011000,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S1_cs
+    6:11    ,   0b011000,             1            ,      (def_IS5D                               == 1);          # cfg_M0S1_cs
+    6:11    ,   0b011000,             1            ,      (def_IS7C                               == 1);          # cfg_M0S1_cs
+    6:11    ,   0b110100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S1_cs
+    12:17   ,   0b110100,             1            ,      (def_C3b                                == 1);          # cfg_M0S2_cs
+    12:17   ,   0b110100,             1            ,      (def_C3c                                == 1);          # cfg_M0S2_cs
+    12:17   ,   0b010100,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S2_cs
+    12:17   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S2_cs
+    12:17   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S2_cs
+    12:17   ,   0b010100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S2_cs
+    12:17   ,   0b010100,             1            ,      (def_IS5D                               == 1);          # cfg_M0S2_cs
+    12:17   ,   0b010100,             1            ,      (def_IS7C                               == 1);          # cfg_M0S2_cs
+    12:17   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S2_cs
+    18:23   ,   0b111000,             1            ,      (def_C3b                                == 1);          # cfg_M0S3_cs
+    18:23   ,   0b111000,             1            ,      (def_C3c                                == 1);          # cfg_M0S3_cs
+    18:23   ,   0b011100,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S3_cs
+    18:23   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S3_cs
+    18:23   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S3_cs
+    18:23   ,   0b011100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S3_cs
+    18:23   ,   0b011100,             1            ,      (def_IS5D                               == 1);          # cfg_M0S3_cs
+    18:23   ,   0b011100,             1            ,      (def_IS7C                               == 1);          # cfg_M0S3_cs
+    18:23   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S3_cs
+    24:29   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M0S4_cs
+    24:29   ,   0b011110,             1            ,      (def_C3c                                == 1);          # cfg_M0S4_cs
+    24:29   ,   0b010001,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S4_cs
+    24:29   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S4_cs
+    24:29   ,   0b110100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S4_cs
+    24:29   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S4_cs
+    24:29   ,   0b100000,             1            ,      (def_IS5D                               == 1);          # cfg_M0S4_cs
+    24:29   ,   0b010010,             1            ,      (def_IS7C                               == 1);          # cfg_M0S4_cs
+    24:29   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S4_cs
+    30:35   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M0S5_cs
+    30:35   ,   0b101110,             1            ,      (def_C3c                                == 1);          # cfg_M0S5_cs
+    30:35   ,   0b011001,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S5_cs
+    30:35   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S5_cs
+    30:35   ,   0b101000,             1            ,      (def_IS5D                               == 1);          # cfg_M0S5_cs
+    30:35   ,   0b011010,             1            ,      (def_IS7C                               == 1);          # cfg_M0S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S5_cs
+    36:41   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M0S6_cs
+    36:41   ,   0b110110,             1            ,      (def_C3c                                == 1);          # cfg_M0S6_cs
+    36:41   ,   0b010101,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S6_cs
+    36:41   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S6_cs
+    36:41   ,   0b100100,             1            ,      (def_IS5D                               == 1);          # cfg_M0S6_cs
+    36:41   ,   0b010110,             1            ,      (def_IS7C                               == 1);          # cfg_M0S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S6_cs
+    42:47   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M0S7_cs
+    42:47   ,   0b111010,             1            ,      (def_C3c                                == 1);          # cfg_M0S7_cs
+    42:47   ,   0b011101,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M0S7_cs
+    42:47   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M0S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M0S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M0S7_cs
+    42:47   ,   0b101100,             1            ,      (def_IS5D                               == 1);          # cfg_M0S7_cs
+    42:47   ,   0b011110,             1            ,      (def_IS7C                               == 1);          # cfg_M0S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M0S7_cs
+    48:51   ,   0b1111,               1            ,      (def_C3b                                == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1111,               1            ,      (def_C3c                                == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1100,               1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1101,               1            ,      (def_C4A_ddr4                           == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1111,               1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1100,               1            ,      (def_IS3b_IS7b                          == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1100,               1            ,      (def_IS5D                               == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1100,               1            ,      (def_IS7C                               == 1);          # cfg_cs_s0_mask
+    48:51   ,   0b1111,               1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_cs_s0_mask
+    52      ,   0b0   ,               1            ,      (def_C3b                                == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_C3c                                == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_C3c_C4C_ddr4                       == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_C4A_ddr4                           == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_IS3b_IS7b                          == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b1   ,               1            ,      (def_IS5D                               == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_IS7C                               == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
+    52      ,   0b0   ,               1            ,      (def_IS7a_C4a_C3a                       == 1);          # MBA_FARB1Q_CFG_S0_DIS_SMDR
 }
 
-# Name = MBA01.FARB.FARB_CS (scomdef)
+
 # MBA_FARB2Q Slot0, Master Rank 1/3 chip select programming
 #
 scom 0x03010415     {
-    bits    ,   scom_data   , expr;
-    0:5     ,   0b111100, (def_C3b                                == 1);          # cfg_M1S0_cs
-    0:5     ,   0b111100, (def_C3c                                == 1);          # cfg_M1S0_cs
-    0:5     ,   0b100000, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S0_cs
-    0:5     ,   0b100100, (def_C4A_ddr4                           == 1);          # cfg_M1S0_cs
-    0:5     ,   0b101100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S0_cs
-    0:5     ,   0b100000, (def_IS3b_IS7b                          == 1);          # cfg_M1S0_cs
-    0:5     ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S0_cs
-    0:5     ,   0b100000, (def_IS7C                               == 1);          # cfg_M1S0_cs
-    0:5     ,   0b101100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S0_cs
-    6:11    ,   0b111100, (def_C3b                                == 1);          # cfg_M1S1_cs
-    6:11    ,   0b111100, (def_C3c                                == 1);          # cfg_M1S1_cs
-    6:11    ,   0b101000, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S1_cs
-    6:11    ,   0b101100, (def_C4A_ddr4                           == 1);          # cfg_M1S1_cs
-    6:11    ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S1_cs
-    6:11    ,   0b101000, (def_IS3b_IS7b                          == 1);          # cfg_M1S1_cs
-    6:11    ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S1_cs
-    6:11    ,   0b101000, (def_IS7C                               == 1);          # cfg_M1S1_cs
-    6:11    ,   0b111000, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S1_cs
-    12:17   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S2_cs
-    12:17   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S2_cs
-    12:17   ,   0b100100, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S2_cs
-    12:17   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S2_cs
-    12:17   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S2_cs
-    12:17   ,   0b100100, (def_IS3b_IS7b                          == 1);          # cfg_M1S2_cs
-    12:17   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S2_cs
-    12:17   ,   0b100100, (def_IS7C                               == 1);          # cfg_M1S2_cs
-    12:17   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S2_cs
-    18:23   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S3_cs
-    18:23   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S3_cs
-    18:23   ,   0b101100, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S3_cs
-    18:23   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S3_cs
-    18:23   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S3_cs
-    18:23   ,   0b101100, (def_IS3b_IS7b                          == 1);          # cfg_M1S3_cs
-    18:23   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S3_cs
-    18:23   ,   0b101100, (def_IS7C                               == 1);          # cfg_M1S3_cs
-    18:23   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S3_cs
-    24:29   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S4_cs
-    24:29   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S4_cs
-    24:29   ,   0b100001, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S4_cs
-    24:29   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S4_cs
-    24:29   ,   0b011100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S4_cs
-    24:29   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M1S4_cs
-    24:29   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S4_cs
-    24:29   ,   0b100010, (def_IS7C                               == 1);          # cfg_M1S4_cs
-    24:29   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S4_cs
-    30:35   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S5_cs
-    30:35   ,   0b101001, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S5_cs
-    30:35   ,   0b101010, (def_IS7C                               == 1);          # cfg_M1S5_cs
-    30:35   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S5_cs
-    36:41   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S6_cs
-    36:41   ,   0b100101, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S6_cs
-    36:41   ,   0b100110, (def_IS7C                               == 1);          # cfg_M1S6_cs
-    36:41   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S6_cs
-    42:47   ,   0b111100, (def_C3b                                == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_C3c                                == 1);          # cfg_M1S7_cs
-    42:47   ,   0b101101, (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_C4A_ddr4                           == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_IS3b_IS7b                          == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_IS5D                               == 1);          # cfg_M1S7_cs
-    42:47   ,   0b101110, (def_IS7C                               == 1);          # cfg_M1S7_cs
-    42:47   ,   0b111100, (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S7_cs
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,    expr;
+    0:5     ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S0_cs
+    0:5     ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S0_cs
+    0:5     ,   0b100000,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S0_cs
+    0:5     ,   0b100100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S0_cs
+    0:5     ,   0b101100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S0_cs
+    0:5     ,   0b100000,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S0_cs
+    0:5     ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S0_cs
+    0:5     ,   0b100000,             1            ,      (def_IS7C                               == 1);          # cfg_M1S0_cs
+    0:5     ,   0b101100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S0_cs
+    6:11    ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S1_cs
+    6:11    ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S1_cs
+    6:11    ,   0b101000,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S1_cs
+    6:11    ,   0b101100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S1_cs
+    6:11    ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S1_cs
+    6:11    ,   0b101000,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S1_cs
+    6:11    ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S1_cs
+    6:11    ,   0b101000,             1            ,      (def_IS7C                               == 1);          # cfg_M1S1_cs
+    6:11    ,   0b111000,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S1_cs
+    12:17   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S2_cs
+    12:17   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S2_cs
+    12:17   ,   0b100100,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S2_cs
+    12:17   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S2_cs
+    12:17   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S2_cs
+    12:17   ,   0b100100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S2_cs
+    12:17   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S2_cs
+    12:17   ,   0b100100,             1            ,      (def_IS7C                               == 1);          # cfg_M1S2_cs
+    12:17   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S2_cs
+    18:23   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S3_cs
+    18:23   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S3_cs
+    18:23   ,   0b101100,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S3_cs
+    18:23   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S3_cs
+    18:23   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S3_cs
+    18:23   ,   0b101100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S3_cs
+    18:23   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S3_cs
+    18:23   ,   0b101100,             1            ,      (def_IS7C                               == 1);          # cfg_M1S3_cs
+    18:23   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S3_cs
+    24:29   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S4_cs
+    24:29   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S4_cs
+    24:29   ,   0b100001,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S4_cs
+    24:29   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S4_cs
+    24:29   ,   0b011100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S4_cs
+    24:29   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S4_cs
+    24:29   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S4_cs
+    24:29   ,   0b100010,             1            ,      (def_IS7C                               == 1);          # cfg_M1S4_cs
+    24:29   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S4_cs
+    30:35   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S5_cs
+    30:35   ,   0b101001,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S5_cs
+    30:35   ,   0b101010,             1            ,      (def_IS7C                               == 1);          # cfg_M1S5_cs
+    30:35   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S5_cs
+    36:41   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S6_cs
+    36:41   ,   0b100101,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S6_cs
+    36:41   ,   0b100110,             1            ,      (def_IS7C                               == 1);          # cfg_M1S6_cs
+    36:41   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S6_cs
+    42:47   ,   0b111100,             1            ,      (def_C3b                                == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_C3c                                == 1);          # cfg_M1S7_cs
+    42:47   ,   0b101101,             1            ,      (def_C3c_C4C_ddr4                       == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_C4A_ddr4                           == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS3b_IS7b                          == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS5D                               == 1);          # cfg_M1S7_cs
+    42:47   ,   0b101110,             1            ,      (def_IS7C                               == 1);          # cfg_M1S7_cs
+    42:47   ,   0b111100,             1            ,      (def_IS7a_C4a_C3a                       == 1);          # cfg_M1S7_cs
 }
 
 
@@ -918,136 +1883,142 @@ scom 0x03010415     {
 #> B0.C0.M00A.CENTAUR.MBU.MBA23.MBA_SRQ.MBA_TMR0Q(0:63) = 0x4479996DB5447445
 #
 scom 0x0301040B     {
-    bits    ,   scom_data   , expr;
-    0:3     ,   0b0100     , any; # RRSMSR_dly is 4 for all cfgs     1                                                      D
-    4:7     ,   0b0100     , any; # RRSMDR_dly is 4 for all cfgs     2                                                      D
-    8:11    ,   0b0111     , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly     3    D
-    8:11    ,   0b1000     , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly     3                             D
-    8:11    ,   0b1001     , (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly     3                                                      D
-    12:15   ,   0b0001     , (def_mba_tmr0q_RW_dlys7  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1000     , (def_mba_tmr0q_RW_dlys8  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1001     , (def_mba_tmr0q_RW_dlys9  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1010     , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1011     , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1100     , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1101     , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1110     , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1111     , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly   4
-    16:19   ,   0b0001     , (def_mba_tmr0q_RW_dlys7  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1000     , (def_mba_tmr0q_RW_dlys8  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1001     , (def_mba_tmr0q_RW_dlys9  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1010     , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1011     , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1100     , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1101     , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1110     , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1111     , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly   5
-    20:23   ,   0b0001     , (def_mba_tmr0q_RW_dlys7  == 1); # RWDM_dly	 6
-    20:23   ,   0b1000     , (def_mba_tmr0q_RW_dlys8  == 1); # RWDM_dly	 6
-    20:23   ,   0b1001     , (def_mba_tmr0q_RW_dlys9  == 1); # RWDM_dly	 6
-    20:23   ,   0b1010     , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly	 6
-    20:23   ,   0b1011     , (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly	 6
-    20:23   ,   0b1100     , (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly	 6
-    20:23   ,   0b1101     , (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly	 6
-    20:23   ,   0b1110     , (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly	 6
-    20:23   ,   0b1111     , (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly	 6
-    24:29   ,   0b010011   , (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010100   , (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010101   , (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010111   , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011000   , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011001   , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011010   , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011011   , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011100   , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011101   , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011110   , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011111   , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly   7
-    24:29   ,   0b100000   , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly   7
-    24:29   ,   0b100001   , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly   7
-    30:35   ,   0b010111   , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011000   , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011001   , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011010   , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011011   , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011100   , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011101   , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011110   , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011111   , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly   8
-    30:35   ,   0b100000   , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly   8
-    30:35   ,   0b100001   , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly   8
-    36:39   ,   0b0100     , (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly     9
-    36:39   ,   0b0101     , (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly     9
-    36:39   ,   0b0110     , (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly     9
-    36:39   ,   0b0111     , (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly     9
-    36:39   ,   0b1000     , (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly     9
-    40:43   ,   0b0100     , any; # WWSMSR_dly is 4 for all cfgs     10                                      D
-    44:47   ,   0b0100     , any; # WWSMDR_dly is 4 for all cfgs     11                                      D
-    48:51   ,   0b0111     , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600);  # WWDM_dly     12     D
-    48:51   ,   0b1000     , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133);  # WWDM_dly     12                              D
-    48:51   ,   0b1001     , (CENTAUR.ATTR_MSS_FREQ == 2400);                           # WWDM_dly     12                              D
-    52:55   ,   0b0100     , any; # RROP_dly is 4 for all cfgs       13                                                        D
-    56:59   ,   0b0100     , any; # WWOP_dly is 4 for all cfgs       14                                                        D
-    60:63   ,   0b0100     , (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0101     , (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0110     , (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0111     , (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd     15
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,    expr;
+    0:3     ,   0b0100     ,             1            ,   any; # RRSMSR_dly is 4 for all cfgs     1                                                      D
+    4:7     ,   0b0100     ,             1            ,   any; # RRSMDR_dly is 4 for all cfgs     2                                                      D
+    8:11    ,   0b0111     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly     3    D
+    8:11    ,   0b1000     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly     3                             D
+    8:11    ,   0b1001     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly     3                                                      D
+    12:15   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly   4
+    16:19   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly   5
+    20:23   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWDM_dly	 6
+    20:23   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWDM_dly	 6
+    20:23   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWDM_dly	 6
+    20:23   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly	 6
+    20:23   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly	 6
+    20:23   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly	 6
+    20:23   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly	 6
+    20:23   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly	 6
+    20:23   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly	 6
+    24:29   ,   0b010011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011010   ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011110   ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly   7
+    24:29   ,   0b100000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly   7
+    24:29   ,   0b100001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly   7
+    30:35   ,   0b010111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011010   ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011110   ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly   8
+    30:35   ,   0b100000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly   8
+    30:35   ,   0b100001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly   8
+    36:39   ,   0b0100     ,             1            ,   (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly     9
+    36:39   ,   0b0101     ,             1            ,   (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly     9
+    36:39   ,   0b0110     ,             1            ,   (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly     9
+    36:39   ,   0b0111     ,             1            ,   (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly     9
+    36:39   ,   0b1000     ,             1            ,   (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly     9
+    40:43   ,   0b0100     ,             1            ,   any; # WWSMSR_dly is 4 for all cfgs     10                                      D
+    44:47   ,   0b0100     ,             1            ,   any; # WWSMDR_dly is 4 for all cfgs     11                                      D
+    48:51   ,   0b0111     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600);  # WWDM_dly     12     D
+    48:51   ,   0b1000     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133);  # WWDM_dly     12                              D
+    48:51   ,   0b1001     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400);                           # WWDM_dly     12                              D
+    52:55   ,   0b0100     ,             1            ,   any; # RROP_dly is 4 for all cfgs       13                                                        D
+    56:59   ,   0b0100     ,             1            ,   any; # WWOP_dly is 4 for all cfgs       14                                                        D
+    60:63   ,   0b0100     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0101     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0110     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0111     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd     15
 }
 
 # MBA_TMR1Q  mba01 timer settings
 #
 scom 0x0301040C     {
-    bits    ,   scom_data   , expr;
-    0:6     ,   0b0011010    , (def_mba_tmr1q_cfg_trap26 == 1); # cfg_trap     16
-    0:6     ,   0b0011011    , (def_mba_tmr1q_cfg_trap27 == 1); # cfg_trap     16
-    0:6     ,   0b0011100    , (def_mba_tmr1q_cfg_trap28 == 1); # cfg_trap     16
-    0:6     ,   0b0100000    , (def_mba_tmr1q_cfg_trap32 == 1); # cfg_trap     16
-    0:6     ,   0b0100001    , (def_mba_tmr1q_cfg_trap33 == 1); # cfg_trap     16
-    0:6     ,   0b0100101    , (def_mba_tmr1q_cfg_trap37 == 1); # cfg_trap     16
-    0:6     ,   0b0100110    , (def_mba_tmr1q_cfg_trap38 == 1); # cfg_trap     16
-    0:6     ,   0b0100111    , (def_mba_tmr1q_cfg_trap39 == 1); # cfg_trap     16
-    0:6     ,   0b0101000    , (def_mba_tmr1q_cfg_trap40 == 1); # cfg_trap     16
-    0:6     ,   0b0101011    , (def_mba_tmr1q_cfg_trap43 == 1); # cfg_trap     16
-    0:6     ,   0b0101100    , (def_mba_tmr1q_cfg_trap44 == 1); # cfg_trap     16
-#    0:6     ,   0b0110000    , (def_mba_tmr1q_cfg_trap48 == 1); # cfg_trap ## 2133 and 2400 DRM not supported    16
-#    0:6     ,   0b0110001    , (def_mba_tmr1q_cfg_trap49 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
-#    0:6     ,   0b0110100    , (def_mba_tmr1q_cfg_trap52 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
-#    0:6     ,   0b0110101    , (def_mba_tmr1q_cfg_trap53 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
-    7:13    ,   0b0011110    , (def_mba_tmr1q_cfg_twap30 == 1); # cfg_twap     17
-    7:13    ,   0b0100000    , (def_mba_tmr1q_cfg_twap32 == 1); # cfg_twap     17
-    7:13    ,   0b0100010    , (def_mba_tmr1q_cfg_twap34 == 1); # cfg_twap     17
-    7:13    ,   0b0100101    , (def_mba_tmr1q_cfg_twap37 == 1); # cfg_twap     17
-    7:13    ,   0b0100111    , (def_mba_tmr1q_cfg_twap39 == 1); # cfg_twap     17
-    7:13    ,   0b0101010    , (def_mba_tmr1q_cfg_twap42 == 1); # cfg_twap     17
-    7:13    ,   0b0101100    , (def_mba_tmr1q_cfg_twap44 == 1); # cfg_twap     17
-    7:13    ,   0b0101110    , (def_mba_tmr1q_cfg_twap46 == 1); # cfg_twap     17
-    7:13    ,   0b0110001    , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap     17
-    7:13    ,   0b0110011    , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap     17
-#    7:13    ,   0b0110110    , (def_mba_tmr1q_cfg_twap54 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
-#    7:13    ,   0b0111000    , (def_mba_tmr1q_cfg_twap56 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
-#    7:13    ,   0b0111011    , (def_mba_tmr1q_cfg_twap59 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
-#    7:13    ,   0b0111101    , (def_mba_tmr1q_cfg_twap61 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
-    14:19   ,   0b010100    , (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw     18
-    14:19   ,   0b011000    , (def_mba_tmr1q_cfg_tfaw_dly24 == 1); # cfg_tfaw     18
-    14:19   ,   0b011101    , (def_mba_tmr1q_cfg_tfaw_dly29 == 1); # cfg_tfaw     18
-    14:19   ,   0b011110    , (def_mba_tmr1q_cfg_tfaw_dly30 == 1); # cfg_tfaw     18
-    14:19   ,   0b100000    , (def_mba_tmr1q_cfg_tfaw_dly32 == 1); # cfg_tfaw     18
-    14:19   ,   0b100010    , (def_mba_tmr1q_cfg_tfaw_dly34 == 1); # cfg_tfaw     18
-    14:19   ,   0b100110    , (def_mba_tmr1q_cfg_tfaw_dly38 == 1); # cfg_tfaw     18
-    14:19   ,   0b101000    , (def_mba_tmr1q_cfg_tfaw_dly40 == 1); # cfg_tfaw     18
-    20:23   ,   0b0000      , (def_mba_tmr1q_RRSBG_dlys0 == 1); # RRSBG_dly    19
-    20:23   ,   0b0101      , (def_mba_tmr1q_RRSBG_dlys5 == 1); # RRSBG_dly    19
-    20:23   ,   0b0110      , (def_mba_tmr1q_RRSBG_dlys6 == 1); # RRSBG_dly    19
-    24:28   ,   0b00000     , (def_mba_tmr1q_WRSBG_dlys0  == 1); # WRSBG_dly    20
-    24:28   ,   0b11010     , (def_mba_tmr1q_WRSBG_dlys26 == 1); # WRSBG_dly    20
-    24:28   ,   0b11011     , (def_mba_tmr1q_WRSBG_dlys27 == 1); # WRSBG_dly    20
-    24:28   ,   0b11100     , (def_mba_tmr1q_WRSBG_dlys28 == 1); # WRSBG_dly    20
-    24:28   ,   0b11110     , (def_mba_tmr1q_WRSBG_dlys30 == 1); # WRSBG_dly    20
-    24:28   ,   0b11111     , (def_mba_tmr1q_WRSBG_dlys31 == 1); # WRSBG_dly    20
-#    24:28   ,   0b00000     , (def_mba_tmr1q_WRSBG_dlys33 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
-#    24:28   ,   0b00000     , (def_mba_tmr1q_WRSBG_dlys34 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
-#    24:28   ,   0b00000     , (def_mba_tmr1q_WRSBG_dlys36 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
-#    24:28   ,   0b00000     , (def_mba_tmr1q_WRSBG_dlys37 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+    0:6     ,   0b0011010    ,          1            ,   (def_mba_tmr1q_cfg_trap26 == 1); # cfg_trap     16
+    0:6     ,   0b0011011    ,          1            ,   (def_mba_tmr1q_cfg_trap27 == 1); # cfg_trap     16
+    0:6     ,   0b0011100    ,          1            ,   (def_mba_tmr1q_cfg_trap28 == 1); # cfg_trap     16
+    0:6     ,   0b0100000    ,          1            ,   (def_mba_tmr1q_cfg_trap32 == 1); # cfg_trap     16
+    0:6     ,   0b0100001    ,          1            ,   (def_mba_tmr1q_cfg_trap33 == 1); # cfg_trap     16
+    0:6     ,   0b0100101    ,          1            ,   (def_mba_tmr1q_cfg_trap37 == 1); # cfg_trap     16
+    0:6     ,   0b0100110    ,          1            ,   (def_mba_tmr1q_cfg_trap38 == 1); # cfg_trap     16
+    0:6     ,   0b0100111    ,          1            ,   (def_mba_tmr1q_cfg_trap39 == 1); # cfg_trap     16
+    0:6     ,   0b0101000    ,          1            ,   (def_mba_tmr1q_cfg_trap40 == 1); # cfg_trap     16
+    0:6     ,   0b0101010    ,          1            ,   (def_mba_tmr1q_cfg_trap42 == 1); # cfg_trap     16
+    0:6     ,   0b0101011    ,          1            ,   (def_mba_tmr1q_cfg_trap43 == 1); # cfg_trap     16
+    0:6     ,   0b0101100    ,          1            ,   (def_mba_tmr1q_cfg_trap44 == 1); # cfg_trap     16
+    0:6     ,   0b0101110    ,          1            ,   (def_mba_tmr1q_cfg_trap46 == 1); # cfg_trap     16
+#    0:6     ,   0b0110000    ,          1            ,   (def_mba_tmr1q_cfg_trap48 == 1); # cfg_trap ## 2133 and 2400 DRM not supported    16
+#    0:6     ,   0b0110001    ,          1            ,   (def_mba_tmr1q_cfg_trap49 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
+#    0:6     ,   0b0110100    ,          1            ,   (def_mba_tmr1q_cfg_trap52 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
+#    0:6     ,   0b0110101    ,          1            ,   (def_mba_tmr1q_cfg_trap53 == 1); # cfg_trap ## 2133 and 2400 DRM not supported     16
+    7:13    ,   0b0011110    ,          1            ,   (def_mba_tmr1q_cfg_twap30 == 1); # cfg_twap     17
+    7:13    ,   0b0100000    ,          1            ,   (def_mba_tmr1q_cfg_twap32 == 1); # cfg_twap     17
+    7:13    ,   0b0100010    ,          1            ,   (def_mba_tmr1q_cfg_twap34 == 1); # cfg_twap     17
+    7:13    ,   0b0100101    ,          1            ,   (def_mba_tmr1q_cfg_twap37 == 1); # cfg_twap     17
+    7:13    ,   0b0100111    ,          1            ,   (def_mba_tmr1q_cfg_twap39 == 1); # cfg_twap     17
+    7:13    ,   0b0101010    ,          1            ,   (def_mba_tmr1q_cfg_twap42 == 1); # cfg_twap     17
+    7:13    ,   0b0101100    ,          1            ,   (def_mba_tmr1q_cfg_twap44 == 1); # cfg_twap     17
+    7:13    ,   0b0101110    ,          1            ,   (def_mba_tmr1q_cfg_twap46 == 1); # cfg_twap     17
+    7:13    ,   0b0110000    ,          1            ,   (def_mba_tmr1q_cfg_twap48 == 1); # cfg_twap     17
+    7:13    ,   0b0110001    ,          1            ,   (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap     17
+    7:13    ,   0b0110011    ,          1            ,   (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap     17
+    7:13    ,   0b0110101    ,          1            ,   (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap     17
+#    7:13    ,   0b0110110    ,          1            ,   (def_mba_tmr1q_cfg_twap54 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
+#    7:13    ,   0b0111000    ,          1            ,   (def_mba_tmr1q_cfg_twap56 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
+#    7:13    ,   0b0111011    ,          1            ,   (def_mba_tmr1q_cfg_twap59 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
+#    7:13    ,   0b0111101    ,          1            ,   (def_mba_tmr1q_cfg_twap61 == 1); # cfg_twap  ## 2133 and 2400 DRM not supported    17
+    14:19   ,   0b010100    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly20 == 1); # cfg_tfaw     18
+    14:19   ,   0b010110    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly22 == 1); # cfg_tfaw     18
+    14:19   ,   0b010111    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly23 == 1); # cfg_tfaw     18
+    14:19   ,   0b011000    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly24 == 1); # cfg_tfaw     18
+    14:19   ,   0b011010    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly26 == 1); # cfg_tfaw     18
+    14:19   ,   0b011011    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly27 == 1); # cfg_tfaw     18
+    14:19   ,   0b011110    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly30 == 1); # cfg_tfaw     18
+    14:19   ,   0b100000    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly32 == 1); # cfg_tfaw     18
+    14:19   ,   0b100001    ,          1             ,   (def_mba_tmr1q_cfg_tfaw_dly33 == 1); # cfg_tfaw     18
+    20:23   ,   0b0000      ,          1             ,   (def_mba_tmr1q_RRSBG_dlys0 == 1); # RRSBG_dly    19
+    20:23   ,   0b0101      ,          1             ,   (def_mba_tmr1q_RRSBG_dlys5 == 1); # RRSBG_dly    19
+    20:23   ,   0b0110      ,          1             ,   (def_mba_tmr1q_RRSBG_dlys6 == 1); # RRSBG_dly    19
+    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys0  == 1); # WRSBG_dly    20
+    24:28   ,   0b11010     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys26 == 1); # WRSBG_dly    20
+    24:28   ,   0b11011     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys27 == 1); # WRSBG_dly    20
+    24:28   ,   0b11100     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys28 == 1); # WRSBG_dly    20
+    24:28   ,   0b11101     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys29 == 1); # WRSBG_dly    20
+    24:28   ,   0b11110     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys30 == 1); # WRSBG_dly    20
+    24:28   ,   0b11111     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys31 == 1); # WRSBG_dly    20
+#    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys33 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
+#    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys34 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
+#    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys36 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
+#    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys37 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
 }
 
 # MBA_DSM0Q  mba01 data state machine settings
@@ -1055,339 +2026,353 @@ scom 0x0301040C     {
 #> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800
 
 scom 0x0301040A     {
-    bits    ,   scom_data   , expr;
-    0:5     ,   0b000000    , (def_mba_dsm0q_CFG_RODT_start_dly0 == 1); # CFG_RODT_start_dly   21
-    0:5     ,   0b000001    , (def_mba_dsm0q_CFG_RODT_start_dly1 == 1); # CFG_RODT_start_dly   21
-    0:5     ,   0b000010    , (def_mba_dsm0q_CFG_RODT_start_dly2 == 1); # CFG_RODT_start_dly   21
-    0:5     ,   0b000011    , (def_mba_dsm0q_CFG_RODT_start_dly3 == 1); # CFG_RODT_start_dly   21
-    6:11    ,   0b000101    , (def_mba_dsm0q_CFG_RODT_end_dly5 == 1); # CFG_RODT_end_dly     22
-    6:11    ,   0b000110    , (def_mba_dsm0q_CFG_RODT_end_dly6 == 1); # CFG_RODT_end_dly     22
-    6:11    ,   0b000111    , (def_mba_dsm0q_CFG_RODT_end_dly7 == 1); # CFG_RODT_end_dly     22
-    6:11    ,   0b001000    , (def_mba_dsm0q_CFG_RODT_end_dly8 == 1); # CFG_RODT_end_dly     22
-    12:17   ,   0b000001    , any; # CFG_WODT_start_dly is 1 for all cfgs   23                     D
-    18:23   ,   0b000110    , any; # CFG_WODT_end_dly is 6 for all cfgs     24                     D
-    24:29   ,   0b011000    , any; # wrdone_dly is 24 for all cfgs 25                              D
-    30:35   ,   0b000011    , (def_mba_dsm0q_cfg_wrdata_dly3  == 1); # wrdata_dly		26
-    30:35   ,   0b000100    , (def_mba_dsm0q_cfg_wrdata_dly4  == 1); # wrdata_dly		26
-    30:35   ,   0b000101    , (def_mba_dsm0q_cfg_wrdata_dly5  == 1); # wrdata_dly		26
-    30:35   ,   0b000110    , (def_mba_dsm0q_cfg_wrdata_dly6  == 1); # wrdata_dly		26
-    30:35   ,   0b000111    , (def_mba_dsm0q_cfg_wrdata_dly7  == 1); # wrdata_dly		26
-    30:35   ,   0b001000    , (def_mba_dsm0q_cfg_wrdata_dly8  == 1); # wrdata_dly		26
-    30:35   ,   0b001001    , (def_mba_dsm0q_cfg_wrdata_dly9  == 1); # wrdata_dly		26
-    30:35   ,   0b001010    , (def_mba_dsm0q_cfg_wrdata_dly10 == 1); # wrdata_dly		26
-    30:35   ,   0b001011    , (def_mba_dsm0q_cfg_wrdata_dly11 == 1); # wrdata_dly		26
-    30:35   ,   0b001100    , (def_mba_dsm0q_cfg_wrdata_dly12 == 1); # wrdata_dly		26
-    30:35   ,   0b001101    , (def_mba_dsm0q_cfg_wrdata_dly13 == 1); # wrdata_dly		26
-    30:35   ,   0b001110    , (def_mba_dsm0q_cfg_wrdata_dly14 == 1); # wrdata_dly		26
-    30:35   ,   0b001111    , (def_mba_dsm0q_cfg_wrdata_dly15 == 1); # wrdata_dly		26
-    30:35   ,   0b010000    , (def_mba_dsm0q_cfg_wrdata_dly16 == 1); # wrdata_dly		26
-    30:35   ,   0b010001    , (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly		26
-    30:35   ,   0b010010    , (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly		26
-    30:35   ,   0b010011    , (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly		26
-    36:41   ,   0b001100    , (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
-    36:41   ,   0b001101    , (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly		27
-    36:41   ,   0b001110    , (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly		27
-    36:41   ,   0b001111    , (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly		27
-    36:41   ,   0b010000    , (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly		27
-    36:41   ,   0b010001    , (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly		27
-    36:41   ,   0b010010    , (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly		27
-    36:41   ,   0b010011    , (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly		27
-    36:41   ,   0b010100    , (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly		27
-    36:41   ,   0b010101    , (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly		27
-    36:41   ,   0b010110    , (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly		27
-    36:41   ,   0b010111    , (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly		27
-    36:41   ,   0b011000    , (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly		27
-    36:41   ,   0b011001    , (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly		27
-    36:41   ,   0b011010    , (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly		27
-    36:41   ,   0b011011    , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly		27
-    36:41   ,   0b011100    , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly		27
-    36:41   ,   0b011101    , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly		27
-    43:48   ,   0b000101    , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28
-    43:48   ,   0b000110    , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28
-    43:48   ,   0b000111    , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28
-    43:48   ,   0b001000    , (def_mba_dsm0q_CFG_RODT_BC4_END_DLY8 == 1); # CFG_RODT_BC4_END_DLY 28
-    49:54   ,   0b000100    , any; # CFG_WODT_BC4_END_DLY is 4 for all cfgs 29                     D
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,    expr;
+    0:5     ,   0b000000    ,           1            ,    (def_mba_dsm0q_CFG_RODT_start_dly0 == 1); # CFG_RODT_start_dly   21
+    0:5     ,   0b000001    ,           1            ,    (def_mba_dsm0q_CFG_RODT_start_dly1 == 1); # CFG_RODT_start_dly   21
+    0:5     ,   0b000010    ,           1            ,    (def_mba_dsm0q_CFG_RODT_start_dly2 == 1); # CFG_RODT_start_dly   21
+    0:5     ,   0b000011    ,           1            ,    (def_mba_dsm0q_CFG_RODT_start_dly3 == 1); # CFG_RODT_start_dly   21
+    0:5     ,   0b000100    ,           1            ,    (def_mba_dsm0q_CFG_RODT_start_dly4 == 1); # CFG_RODT_start_dly   21
+    6:11    ,   0b000101    ,           1            ,    (def_mba_dsm0q_CFG_RODT_end_dly5 == 1); # CFG_RODT_end_dly     22
+    6:11    ,   0b000110    ,           1            ,    (def_mba_dsm0q_CFG_RODT_end_dly6 == 1); # CFG_RODT_end_dly     22
+    6:11    ,   0b000111    ,           1            ,    (def_mba_dsm0q_CFG_RODT_end_dly7 == 1); # CFG_RODT_end_dly     22
+    6:11    ,   0b001000    ,           1            ,    (def_mba_dsm0q_CFG_RODT_end_dly8 == 1); # CFG_RODT_end_dly     22
+    6:11    ,   0b001001    ,           1            ,    (def_mba_dsm0q_CFG_RODT_end_dly9 == 1); # CFG_RODT_end_dly     22
+    12:17   ,   0b000001    ,           1            ,    any; # CFG_WODT_start_dly is 1 for all cfgs   23                     D
+    18:23   ,   0b000110    ,           1            ,    any; # CFG_WODT_end_dly is 6 for all cfgs     24                     D
+    24:29   ,   0b011000    ,           1            ,    any; # wrdone_dly is 24 for all cfgs 25                              D
+    30:35   ,   0b000011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly3  == 1); # wrdata_dly		26
+    30:35   ,   0b000100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly4  == 1); # wrdata_dly		26
+    30:35   ,   0b000101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly5  == 1); # wrdata_dly		26
+    30:35   ,   0b000110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly6  == 1); # wrdata_dly		26
+    30:35   ,   0b000111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly7  == 1); # wrdata_dly		26
+    30:35   ,   0b001000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly8  == 1); # wrdata_dly		26
+    30:35   ,   0b001001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly9  == 1); # wrdata_dly		26
+    30:35   ,   0b001010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly10 == 1); # wrdata_dly		26
+    30:35   ,   0b001011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly11 == 1); # wrdata_dly		26
+    30:35   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly12 == 1); # wrdata_dly		26
+    30:35   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly13 == 1); # wrdata_dly		26
+    30:35   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly14 == 1); # wrdata_dly		26
+    30:35   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly15 == 1); # wrdata_dly		26
+    30:35   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly16 == 1); # wrdata_dly		26
+    30:35   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly		26
+    30:35   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly		26
+    30:35   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly		26
+    36:41   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
+    36:41   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly		27
+    36:41   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly		27
+    36:41   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly		27
+    36:41   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly		27
+    36:41   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly		27
+    36:41   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly		27
+    36:41   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly		27
+    36:41   ,   0b010100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly		27
+    36:41   ,   0b010101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly		27
+    36:41   ,   0b010110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly		27
+    36:41   ,   0b010111    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly		27
+    36:41   ,   0b011000    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly		27
+    36:41   ,   0b011001    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly		27
+    36:41   ,   0b011010    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly		27
+    36:41   ,   0b011011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly		27
+    36:41   ,   0b011100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly		27
+    36:41   ,   0b011101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly		27
+    43:48   ,   0b000101    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28
+    43:48   ,   0b000110    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28
+    43:48   ,   0b000111    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28
+    43:48   ,   0b001000    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY8 == 1); # CFG_RODT_BC4_END_DLY 28
+    43:48   ,   0b001001    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY9 == 1); # CFG_RODT_BC4_END_DLY 28
+    49:54   ,   0b000100    ,           1            ,    any; # CFG_WODT_BC4_END_DLY is 4 for all cfgs 29                     D
 }
 
 # MBAREF0Q   mba01 refresh settings
 #
 scom 0x03010432    {
-    bits    ,   scom_data    , expr;
-     4:7    ,   0b0111       , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs      30     ?
-# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008
-     8:18   ,   0b00010110000, any; # MBAREF0Q_refresh intveral set to 176 decimal                 31     ?		!!FIXME
-# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008
-    19:29   ,   0b00011000010, any; # MBAREF0Q_refresh reset interval set to 194 decimal           32     ?		!!FIXME
-    30:39   ,   0b0001010110 , (def_MBAREF0Q_cfg_trfc_dly86  == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0001101011 , (def_MBAREF0Q_cfg_trfc_dly107 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0010000000 , (def_MBAREF0Q_cfg_trfc_dly128 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0010010110 , (def_MBAREF0Q_cfg_trfc_dly150 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0010100000 , (def_MBAREF0Q_cfg_trfc_dly160 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0010110100 , (def_MBAREF0Q_cfg_trfc_dly180 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0010111011 , (def_MBAREF0Q_cfg_trfc_dly187 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0011001000 , (def_MBAREF0Q_cfg_trfc_dly200 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0011101010 , (def_MBAREF0Q_cfg_trfc_dly234 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0011110000 , (def_MBAREF0Q_cfg_trfc_dly240 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0100000100 , (def_MBAREF0Q_cfg_trfc_dly260 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0100001001 , (def_MBAREF0Q_cfg_trfc_dly265 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0100011000 , (def_MBAREF0Q_cfg_trfc_dly280 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0100011001 , (def_MBAREF0Q_cfg_trfc_dly281 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0101001000 , (def_MBAREF0Q_cfg_trfc_dly328 == 1); # MBAREF0Q_cfg_trfc   33
-    30:39   ,   0b0101011110 , (def_MBAREF0Q_cfg_trfc_dly350 == 1); # MBAREF0Q_cfg_trfc   33
-#    30:39   ,   0b0001101011 , any; # MBAREF0Q_cfg_trfc set to 107 decimal
-    40:49   ,   0b0000011000 , any; # MBAREF0Q_cfg_refr_tsv_stack is 24 for all cfgs               34      D
-# refr_check_interval=desired_tREFI_in_us/DRAM_command_clock_cycle_in_ns/.008
-    50:60   ,   0b01100001100, any; # MBAREF0Q_refresh check intveral set to 780 decimal            35
+    bits    ,   scom_data    ,      ATTR_FUNCTIONAL,    expr;
+     4:7    ,   0b0111       ,           1            ,    any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs      30     ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008
+     8:18   ,   0b00010110000,           1            ,    any; # MBAREF0Q_refresh intveral set to 176 decimal                 31     ?		!!FIXME# reset check interval = tREFI(7.8) / DRAM clk(ns) / 0.008
+    19:29   ,   0b00011000010,           1            ,    any; # MBAREF0Q_refresh reset interval set to 194 decimal           32     ?		!!FIXME
+    30:39   ,   0b0001010110 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly86  == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0001101011 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly107 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0010000000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly128 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0010010110 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly150 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0010100000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly160 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0010101011 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly171 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0010111011 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly187 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011000000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly192 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011001000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly200 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011010000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly208 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011101010 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly234 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011110000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly240 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0011110011 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly243 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0100010110 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly278 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0100011000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly280 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0100011001 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly281 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0100111000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly312 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0101000111 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly327 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0101001000 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly328 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0101110110 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly374 == 1); # MBAREF0Q_cfg_trfc   33
+    30:39   ,   0b0110100100 ,           1            ,    (def_MBAREF0Q_cfg_trfc_dly420 == 1); # MBAREF0Q_cfg_trfc   33
+#    30:39   ,   0b0001101011 ,           1            ,    any; # MBAREF0Q_cfg_trfc set to 107 decimal
+    40:49   ,   0b0000100000 ,           1            ,    (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack   33
+    40:49   ,   0b0000110000 ,           1            ,    (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack   33
+    40:49   ,   0b0001000000 ,           1            ,    (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack   33
+#    40:49   ,   0b0000011000 ,           1            ,    any; # MBAREF0Q_cfg_refr_tsv_stack is 24 for all cfgs               34      D
+    50:60   ,   0b01100001100,           1            ,    any; # MBAREF0Q_refresh check intveral set to 780 decimal            35
 }
 
 # MBAPC0Q    power control settings reg 1
 #
 scom 0x03010434    {
-    bits    ,   scom_data   , expr;
-    6:10    ,   0b00100     , (def_MBARPC0Q_cfg_pup_avail_dly4  == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b00101     , (def_MBARPC0Q_cfg_pup_avail_dly5  == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b00110     , (def_MBARPC0Q_cfg_pup_avail_dly6  == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b01101     , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b10000     , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b10100     , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1); # MBARPC0Q_cfg_pup_avail     36
-    6:10    ,   0b10111     , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1); # MBARPC0Q_cfg_pup_avail     36
-    11:15   ,   0b00011     , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup       37
-    11:15   ,   0b00100     , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup       37
-    11:15   ,   0b00101     , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup       37
-    16:20   ,   0b00011     , (def_MBARPC0Q_cfg_pup_pdn_dly3 == 1); # MBARPC0Q_cfg_pup_pdn       38
-    16:20   ,   0b00100     , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn       38
-    16:20   ,   0b00101     , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn       38
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+    6:10    ,   0b00100     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly4  == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b00101     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly5  == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b00110     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly6  == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b00111     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly7  == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b01000     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly8  == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b01101     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly13 == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b10000     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly16 == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b10100     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly20 == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b10111     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly23 == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b11010     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly26 == 1); # MBARPC0Q_cfg_pup_avail     36
+    6:10    ,   0b11101     ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly29 == 1); # MBARPC0Q_cfg_pup_avail     36
+    11:15   ,   0b00011     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup       37
+    11:15   ,   0b00100     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup       37
+    11:15   ,   0b00101     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup       37
+    11:15   ,   0b00110     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly6 == 1); # MBARPC0Q_cfg_pup_pup       37
+    16:20   ,   0b00011     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly3 == 1); # MBARPC0Q_cfg_pup_pdn       38
+    16:20   ,   0b00100     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn       38
+    16:20   ,   0b00101     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn       38
+    16:20   ,   0b00110     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn       38
 }
 
 # MBAPC1Q    power control settings reg 1
 #
 scom 0x03010435    {
-    bits    ,   scom_data   , expr;
-    0:3     ,   0x8         , (def_odt_mapping_1a        == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xC         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xD         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x8         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x9         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xC         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x8         , (def_odt_mapping_2abc      == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x8         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x8         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0xC         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk0_rd_cke    36
-    0:3     ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_rd_cke    36
-    4:7     ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xC         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xE         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x4         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x5         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xC         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x7         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x4         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0x4         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xC         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk1_rd_cke    36
-    4:7     ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk1_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x9         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x8         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x8         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk2_rd_cke    36
-    8:11    ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk2_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x5         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x7         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x4         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x4         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk3_rd_cke    36
-    12:15   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk3_rd_cke    36
-    16:19   ,   0x2         , (def_odt_mapping_1a        == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x7         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x2         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0xA         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x3         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x2         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x2         , (def_odt_mapping_2abc      == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x2         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk4_rd_cke    36
-    16:19   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk4_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0xB         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x1         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x9         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x3         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0xD         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x1         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x1         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk5_rd_cke    36
-    20:23   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk5_rd_cke    36
-    24:27   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0xA         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x2         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x2         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk6_rd_cke    37
-    24:27   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk6_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x9         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0xD         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x1         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x1         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk7_rd_cke    37
-    28:31   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk7_rd_cke    37
-    32:35   ,   0x8         , (def_odt_mapping_1a        == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0x8         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xD         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0x8         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xA         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xC         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0x8         , (def_odt_mapping_2abc      == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0x8         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0x8         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xC         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk0_wr_cke    38
-    32:35   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_wr_cke    38
-    36:39   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x4         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xE         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x4         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x6         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xC         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x7         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x4         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0x4         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xC         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk1_wr_cke    38
-    36:39   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk1_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0xA         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x8         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x8         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk2_wr_cke    38
-    40:43   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk2_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x6         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0xC         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x7         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0xC         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x4         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x4         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk3_wr_cke    38
-    44:47   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk3_wr_cke    38
-    48:51   ,   0x2         , (def_odt_mapping_1a        == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x7         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x2         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x6         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x3         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x2         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x2         , (def_odt_mapping_2abc      == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x2         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk4_wr_cke    38
-    48:51   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk4_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0xB         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x1         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x5         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x3         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0xD         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x1         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x1         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk5_wr_cke    38
-    52:55   ,   0xF         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk5_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x6         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0xF         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x2         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x2         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk6_wr_cke    38
-    56:59   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk6_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1a        == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x5         , (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0xD         , (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x1         , (def_odt_mapping_1dx4      == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_2abc      == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_56781lrdm == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x1         , (def_odt_mapping_56782lrdm == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk7_wr_cke    38
-    60:63   ,   0x0         , (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk7_wr_cke    38
-
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+    0:3     ,   0x8         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xC         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xD         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x8         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x9         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xC         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x8         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x8         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x8         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0xC         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk0_rd_cke    36
+    0:3     ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_rd_cke    36
+    4:7     ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xC         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xE         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x4         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x5         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xC         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x7         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x4         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0x4         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xC         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk1_rd_cke    36
+    4:7     ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk1_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x9         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x8         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x8         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk2_rd_cke    36
+    8:11    ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk2_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x5         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x7         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x4         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x4         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk3_rd_cke    36
+    12:15   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk3_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x7         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0xA         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x3         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x2         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk4_rd_cke    36
+    16:19   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk4_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0xB         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x1         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x9         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x3         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0xD         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x1         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x1         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk5_rd_cke    36
+    20:23   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk5_rd_cke    36
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0xA         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x2         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x2         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk6_rd_cke    37
+    24:27   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk6_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x9         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0xD         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x1         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x1         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk7_rd_cke    37
+    28:31   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk7_rd_cke    37
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xD         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xA         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xC         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0x8         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xC         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk0_wr_cke    38
+    32:35   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_wr_cke    38
+    36:39   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x4         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xE         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x4         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x6         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xC         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x7         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x4         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0x4         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xC         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk1_wr_cke    38
+    36:39   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk1_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0xA         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x8         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x8         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk2_wr_cke    38
+    40:43   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk2_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x6         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0xC         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x7         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0xC         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x4         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x4         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk3_wr_cke    38
+    44:47   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk3_wr_cke    38
+    48:51   ,   0x2         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x7         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x2         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x6         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x3         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x2         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x2         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x2         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk4_wr_cke    38
+    48:51   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk4_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0xB         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x1         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x5         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x3         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0xD         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x1         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x1         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk5_wr_cke    38
+    52:55   ,   0xF         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk5_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x6         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0xF         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x2         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x2         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk6_wr_cke    38
+    56:59   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk6_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1a        == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1b1dimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1b2dimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1bcdimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x5         ,          1            ,    (def_odt_mapping_1c2dimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1c1dimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_1ccdimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0xD         ,          1            ,    (def_odt_mapping_1dx82dimm == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x1         ,          1            ,    (def_odt_mapping_1dx4      == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_2abc      == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_56781lrdm == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x1         ,          1            ,    (def_odt_mapping_56782lrdm == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_5d1dimm   == 1); # cfg_mrnk7_wr_cke    38
+    60:63   ,   0x0         ,          1            ,    (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk7_wr_cke    38
 }
 
 
@@ -1401,26 +2386,81 @@ scom 0x03010435    {
 # MBAREF1Q   MBA01 Rank-to-primary-CKE mapping table
 #
 scom 0x03010433      {
-    bits    ,   scom_data    , expr;
-    0:3     ,   0b1000       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk0_prim_cke
-    0:3     ,   0b1100       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk0_prim_cke
-    4:7     ,   0b0100       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk1_prim_cke
-    4:7     ,   0b1000       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk1_prim_cke
-    8:11    ,   0b1000       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk2_prim_cke
-    8:11    ,   0b0100       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk2_prim_cke
-    12:15   ,   0b0100       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk3_prim_cke
-    12:15   ,   0b0100       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk3_prim_cke
-    16:19   ,   0b0010       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk4_prim_cke
-    16:19   ,   0b0011       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk4_prim_cke
-    20:23   ,   0b0001       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk5_prim_cke
-    20:23   ,   0b0010       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk5_prim_cke
-    24:27   ,   0b0010       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk6_prim_cke
-    24:27   ,   0b0001       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk6_prim_cke
-    28:31   ,   0b0001       , (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk7_prim_cke
-    28:31   ,   0b0001       , (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk7_prim_cke
+    bits    ,   scom_data    ,       ATTR_FUNCTIONAL,   expr;
+    0:3     ,   0b1000       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk0_prim_cke
+    0:3     ,   0b1100       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk0_prim_cke
+    4:7     ,   0b0100       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk1_prim_cke
+    4:7     ,   0b1000       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk1_prim_cke
+    8:11    ,   0b1000       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk2_prim_cke
+    8:11    ,   0b0100       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk2_prim_cke
+    12:15   ,   0b0100       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk3_prim_cke
+    12:15   ,   0b0100       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk3_prim_cke
+    16:19   ,   0b0010       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk4_prim_cke
+    16:19   ,   0b0011       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk4_prim_cke
+    20:23   ,   0b0001       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk5_prim_cke
+    20:23   ,   0b0010       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk5_prim_cke
+    24:27   ,   0b0010       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk6_prim_cke
+    24:27   ,   0b0001       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk6_prim_cke
+    28:31   ,   0b0001       ,          1            ,     (def_prim_map_a == 1); # MBAREF1Q_cfg_mrnk7_prim_cke
+    28:31   ,   0b0001       ,          1            ,     (def_prim_map_c == 1); # MBAREF1Q_cfg_mrnk7_prim_cke
 }
 
+#define def_zqcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001)
+define def_zq_intv  = (ATTR_EFF_ZQCAL_INTERVAL / 16384);
+#define def_memcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001)
+define def_mem_intv =  (ATTR_EFF_MEMCAL_INTERVAL / 16384);
+#    ATTR_EFF_MEMCAL_INTERVAL are in clock cycles
+#    ATTR_EFF_ZQCAL_INTERVAL are in clock cycles
 
+# MBA_CAL0Q (this timer to be used for zq cal)
+#
+scom 0x0301040F    {
+
+    bits    ,   scom_data        ,       ATTR_FUNCTIONAL,   expr;
+    0       ,   0b0              ,          1            ,     any;    #disable timer initially
+    1:2     ,   0b10             ,          1            ,     any;    #timebase; use 16384 cycle timebase; zqcal_timebase_in_ms=16384*(1/DRAM_freq_in_MHz)*1e-3
+    3:11    ,   def_zq_intv      ,          1            ,     any;    #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    12      ,   0b1              ,          1            ,     any;    #enable for type1
+    13:16   ,   0b0100           ,          1            ,     any;    #select external zq cal for type1
+    17      ,   0b1              ,          1            ,     any;    #wait for done from DDR for type1
+    18      ,   0b0              ,          1            ,     any;    #disable type2 timer
+    19:22   ,   0b0000           ,          1            ,     any;    #type2 cal type
+    23      ,   0b0              ,          1            ,     any;    #disable type2 done
+    24      ,   0b0              ,          1            ,     any;    #disable type3 timer
+    25:28   ,   0b0000           ,          1            ,     any;    #type3 cal type
+    29      ,   0b0              ,          1            ,     any;    #disable type3 done
+    30:38   ,   0b000000000      ,          1            ,     any;    #set timer to 0 for z sync
+    39:46   ,   0b01000000       ,          1            ,     any;    #reset tmr
+    47:48   ,   0b00             ,          1            ,     any;    #reset tb
+    49      ,   0b0              ,          1            ,     any;    #disable for soft reset on cal timeout
+    50      ,   0b1              ,          1            ,     any;    #use single rank mode
+    51      ,   0b0              ,          1            ,     any;    #cal0_pare_err
+    52      ,   0b0              ,          1            ,     any;    #1hot_sm_err
+    53:55   ,   0b000            ,          1            ,     any;    #cal_single_port_mode off
+    56:63   ,   0b00000000       ,          1            ,     any;    #reserved
+}
+
+# MBA_CAL1Q (this timer to be used for mem cal)
+#
+scom 0x03010410    {
+
+    bits    ,   scom_data                      ,       ATTR_FUNCTIONAL,   expr;
+    0       ,   0b0                            ,          1            ,    any;    #disable timer initially
+    1:2     ,   0b10                           ,          1            ,    any;    #timebase; use 16384 cycle timebase; memcal_timebase_in_ms=16384*(1/DRAM_freq_in_MHz)*1e-3
+    3:11    ,   def_mem_intv                   ,          1            ,    any;    #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds)
+    12      ,   0b1                            ,          1            ,    any;    #enable for type1
+    13:16   ,   0b0100                         ,          1            ,    any;    #select external zq cal for type1
+    17      ,   0b1                            ,          1            ,    any;    #wait for done from DDR for type1
+    18      ,   0b0                            ,          1            ,    any;    #disable type2 timer
+    19:22   ,   0b0000                         ,          1            ,    any;    #type2 cal type
+    23      ,   0b0                            ,          1            ,    any;    #disable type2 done
+    24      ,   0b0                            ,          1            ,    any;    #disable type3 timer
+    25:28   ,   0b0000                         ,          1            ,    any;    #type3 cal type
+    29      ,   0b0                            ,          1            ,    any;    #disable type3 done
+    30:38   ,   0b000000000                    ,          1            ,    any;    #set timer to 0 for z sync
+    39      ,   0b0                            ,          1            ,    any;    #use single rank mode
+    40:63   ,   0b000000000000000000000000     ,          1            ,     any;    #reserved to 0
+}
 
 ###########################################################################################
 # MBA MCBIST SETUP SECTION                                                                #
@@ -1435,43 +2475,43 @@ scom 0x03010433      {
 # Setup subtest 1 is a read with fixed data
 
 scom 0x030106A8     {
-    bits    ,   scom_data   , expr;
-    0:2     ,   0b000, any;         # cfg_test00_op_type is a write
-    3       ,   0b0,   any;         # cfg_test00_compl_1st_cmd
-    4       ,   0b0,   any;         # cfg_test00_compl_2nd_cmd
-    5       ,   0b0,   any;         # cfg_test00_compl_3rd_cmd
-    6:7     ,   0b00,  any;         # cfg_test00_addr_mode
-    8:10    ,   0b000, any;         # cfg_test00_data_mode
-    11      ,   0b0  , any;         # cfg_test00_done
-    12:13   ,   0b00,  any;         # cfg_test00_data_sel
-    14:15   ,   0b00,  any;         # cfg_test00_addr_sel
-    16:18   ,   0b001, any;         # cfg_test01_op_type is a read
-    19      ,   0b0,   any;         # cfg_test01_compl_1st_cmd
-    20      ,   0b0,   any;         # cfg_test01_compl_2nd_cmd
-    21      ,   0b0,   any;         # cfg_test01_compl_3rd_cmd
-    22:23   ,   0b00,  any;         # cfg_test01_addr_mode
-    24:26   ,   0b000, any;         # cfg_test01_data_mode
-    27      ,   0b1  , any;         # cfg_test01_done is set
-    28:29   ,   0b00,  any;         # cfg_test01_data_sel
-    30:31   ,   0b00,  any;         # cfg_test01_addr_sel
-    32:34   ,   0b000, any;         # cfg_test02_op_type
-    35      ,   0b0,   any;         # cfg_test02_compl_1st_cmd
-    36      ,   0b0,   any;         # cfg_test02_compl_2nd_cmd
-    37      ,   0b0,   any;         # cfg_test02_compl_3rd_cmd
-    38:39   ,   0b00,  any;         # cfg_test02_addr_mode
-    40:42   ,   0b000, any;         # cfg_test02_data_mode
-    43      ,   0b0  , any;         # cfg_test02_done
-    44:45   ,   0b00,  any;         # cfg_test02_data_sel
-    46:47   ,   0b00,  any;         # cfg_test02_addr_sel
-    48:50   ,   0b000, any;         # cfg_test03_op_type
-    51      ,   0b0,   any;         # cfg_test03_compl_1st_cmd
-    52      ,   0b0,   any;         # cfg_test03_compl_2nd_cmd
-    53      ,   0b0,   any;         # cfg_test03_compl_3rd_cmd
-    54:55   ,   0b00,  any;         # cfg_test03_addr_mode
-    56:58   ,   0b000, any;         # cfg_test03_data_mode
-    59      ,   0b0  , any;         # cfg_test03_done
-    60:61   ,   0b00,  any;         # cfg_test03_data_sel
-    62:63   ,   0b00,  any;         # cfg_test03_addr_sel
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL, expr;
+    0:2     ,   0b000,                   1            ,any;         # cfg_test00_op_type is a write
+    3       ,   0b0,                     1            ,any;         # cfg_test00_compl_1st_cmd
+    4       ,   0b0,                     1            ,any;         # cfg_test00_compl_2nd_cmd
+    5       ,   0b0,                     1            ,any;         # cfg_test00_compl_3rd_cmd
+    6:7     ,   0b00,                    1            ,any;         # cfg_test00_addr_mode
+    8:10    ,   0b000,                   1            ,any;         # cfg_test00_data_mode
+    11      ,   0b0  ,                   1            ,any;         # cfg_test00_done
+    12:13   ,   0b00,                    1            ,any;         # cfg_test00_data_sel
+    14:15   ,   0b00,                    1            ,any;         # cfg_test00_addr_sel
+    16:18   ,   0b001,                   1            ,any;         # cfg_test01_op_type is a read
+    19      ,   0b0,                     1            ,any;         # cfg_test01_compl_1st_cmd
+    20      ,   0b0,                     1            ,any;         # cfg_test01_compl_2nd_cmd
+    21      ,   0b0,                     1            ,any;         # cfg_test01_compl_3rd_cmd
+    22:23   ,   0b00,                    1            ,any;         # cfg_test01_addr_mode
+    24:26   ,   0b000,                   1            ,any;         # cfg_test01_data_mode
+    27      ,   0b1  ,                   1            ,any;         # cfg_test01_done is set
+    28:29   ,   0b00,                    1            ,any;         # cfg_test01_data_sel
+    30:31   ,   0b00,                    1            ,any;         # cfg_test01_addr_sel
+    32:34   ,   0b000,                   1            ,any;         # cfg_test02_op_type
+    35      ,   0b0,                     1            ,any;         # cfg_test02_compl_1st_cmd
+    36      ,   0b0,                     1            ,any;         # cfg_test02_compl_2nd_cmd
+    37      ,   0b0,                     1            ,any;         # cfg_test02_compl_3rd_cmd
+    38:39   ,   0b00,                    1            ,any;         # cfg_test02_addr_mode
+    40:42   ,   0b000,                   1            ,any;         # cfg_test02_data_mode
+    43      ,   0b0  ,                   1            ,any;         # cfg_test02_done
+    44:45   ,   0b00,                    1            ,any;         # cfg_test02_data_sel
+    46:47   ,   0b00,                    1            ,any;         # cfg_test02_addr_sel
+    48:50   ,   0b000,                   1            ,any;         # cfg_test03_op_type
+    51      ,   0b0,                     1            ,any;         # cfg_test03_compl_1st_cmd
+    52      ,   0b0,                     1            ,any;         # cfg_test03_compl_2nd_cmd
+    53      ,   0b0,                     1            ,any;         # cfg_test03_compl_3rd_cmd
+    54:55   ,   0b00,                    1            ,any;         # cfg_test03_addr_mode
+    56:58   ,   0b000,                   1            ,any;         # cfg_test03_data_mode
+    59      ,   0b0  ,                   1            ,any;         # cfg_test03_done
+    60:61   ,   0b00,                    1            ,any;         # cfg_test03_data_sel
+    62:63   ,   0b00,                    1            ,any;         # cfg_test03_addr_sel
 }
 
 ###################################
@@ -1482,53 +2522,53 @@ scom 0x030106A8     {
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef)
 
 scom 0x030106BE     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x1111111111111111, any;         # Fixed data burst 0
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x1111111111111111,            1             ,any;         # Fixed data burst 0
 }
 
 scom 0x030106BF     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x2222222222222222, any;         # Fixed data burst 1
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x2222222222222222,            1             ,any;         # Fixed data burst 1
 }
 
 scom 0x030106C0     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x3333333333333333, any;         # Fixed data burst 2
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x3333333333333333,            1             ,any;         # Fixed data burst 2
 }
 
 scom 0x030106C1     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x4444444444444444, any;         # Fixed data burst 3
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x4444444444444444,            1             ,any;         # Fixed data burst 3
 }
 
 scom 0x030106C2     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x5555555555555555, any;         # Fixed data burst 4
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x5555555555555555,            1             ,any;         # Fixed data burst 4
 }
 
 scom 0x030106C3     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x6666666666666666, any;         # Fixed data burst 5
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x6666666666666666,            1             ,any;         # Fixed data burst 5
 }
 
 scom 0x030106C4     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x7777777777777777, any;         # Fixed data burst 6
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x7777777777777777,            1             ,any;         # Fixed data burst 6
 }
 
 scom 0x030106C5     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x8888888888888888, any;         # Fixed data burst 7
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x8888888888888888,            1             ,any;         # Fixed data burst 7
 }
 
 scom 0x030106C6     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x9999999999999999, any;         # Fixed data burst 0-7 ECC bits
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0x9999999999999999,            1             ,any;         # Fixed data burst 0-7 ECC bits
 }
 
 scom 0x030106C7     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0xAAAAAAAAAAAAAAAA, any;         # Fixed data burst 0-7 SPARE bits
+    bits    ,   scom_data         ,       ATTR_FUNCTIONAL ,expr;
+    0:63    ,   0xAAAAAAAAAAAAAAAA,            1             ,any;         # Fixed data burst 0-7 SPARE bits
 }
 
 
@@ -1538,35 +2578,267 @@ scom 0x030106C7     {
 
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef)
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef)
-# MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming
 #
 
+
 scom 0x030106D0     {
-    bits    ,   scom_data   , expr;
-    0:35    ,   0x000000000, any;          # A0 start address
-    36:37   ,   0b00, any;                 # A0 start address
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    0:35    ,   0x000000000 ,            1            ,     any;          # A0 start address
+    36:37   ,   0b00        ,            1            ,     any;                 # A0 start address
 }
 
+
+
 scom 0x030106D2     {
-    bits    ,   scom_data   , expr;
-    0:35    ,   0x000000000, any;          # A0 End address
-    36:37   ,   0b11, any;                 # A0 End address
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,      expr;
+    0:3     ,   0x0         ,            1            ,     any  ;          # A0 End address
+    4:15    ,   0xFFF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total22_max22)                                                                                                                               ;          # A0 End address
+    4:15    ,   0x7FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23)                                                                                                ;          # A0 End address
+    4:15    ,   0x3FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24)                                                                 ;          # A0 End address
+    4:15    ,   0x1FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25)                                  ;          # A0 End address
+    4:15    ,   0x0FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26)                                  ;          # A0 End address
+    4:15    ,   0x07F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27)                                  ;          # A0 End address
+    4:15    ,   0x03F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29)   ;          # A0 End address
+    4:15    ,   0x01F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29)                                                                                                ;          # A0 End address
+    4:15    ,   0x00F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30)                                                                                                ;          # A0 End address
+    4:15    ,   0x007       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max31)                                                                                                                               ;          # A0 End address
+    4:15    ,   0x7FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total22_max22)                                                                                                                               ;          # A0 End address
+    4:15    ,   0x3FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23)                                                                                                 ;          # A0 End address
+    4:15    ,   0x1FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24)                                                                 ;          # A0 End address
+    4:15    ,   0x0FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25)                                  ;          # A0 End address
+    4:15    ,   0x07F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26)                                  ;          # A0 End address
+    4:15    ,   0x03F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27)                                  ;          # A0 End address
+    4:15    ,   0x01F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29)   ;          # A0 End address
+    4:15    ,   0x00F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29)                                                                                                ;          # A0 End address
+    4:15    ,   0x007       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30)                                                                                                ;          # A0 End address
+    4:15    ,   0x003       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max31)                                                                                                                               ;          # A0 End address
+    4:15    ,   0x3FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total22_max22)                                                                                                                               ;          # A0 End address
+    4:15    ,   0x1FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23)                                                                                                 ;          # A0 End address
+    4:15    ,   0x0FF       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24)                                                                 ;          # A0 End address
+    4:15    ,   0x07F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25)                                  ;          # A0 End address
+    4:15    ,   0x03F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26)                                  ;          # A0 End address
+    4:15    ,   0x01F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27)                                  ;          # A0 End address
+    4:15    ,   0x00F       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29)   ;          # A0 End address
+    4:15    ,   0x007       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29)                                                                                                ;          # A0 End address
+    4:15    ,   0x003       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30)                                                                                                ;          # A0 End address
+    4:15    ,   0x001       ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max31)                                                                                                                               ;          # A0 End address
+    4:15   ,    0x000       ,            1            ,     ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0));          # A0 End address
+    16:35   ,   0x00000     ,            1            ,     ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0));          # A0 End address
+    16:35   ,   0xFFFFF     ,            1            ,     (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE != 0);          # A0 End address
+    36:37   ,   0b11        ,            1            ,     any;                 # A0 End address
 }
 
 ###################################
 # MCBIST Addr Gen Cfg Reg
 ###################################
 
-# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef)
-# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef)
-# MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming
+# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAGRAQ_Q (scomdef)
 #
 
 scom 0x030106D6     {
-    bits    ,   scom_data   , expr;
-    24:25   ,   0b10, any;                 # A0 setup only A0 address gen
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+     0:5    ,   0b000000    ,            1            ,     any;                 # A0 cfg_fixed_width_a0
+    24:25   ,   0b10        ,            1            ,     any;                 # A0 setup only A0 address gen
 }
 
+######
+
+
+
+
+
+############################################
+# MCBIST Port A Socket 0 Addr Map Reg 0
+############################################
+
+# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAMR0A0Q_Q (scomdef)
+#
+
+scom 0x030106C8     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    0:5     ,   0b000000    ,            1            ,     any     ;         #cfg_a0map_mrank0 Master Rank Bit 0 (MSB)
+    6:11    ,   0b000000    ,            1            ,     ((def_mcb_mrank1_unset)                      == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000010    ,            1            ,     ((def_mcb_addr_row17_col12_bnk16_mrank1_2 )  == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000011    ,            1            ,     (((def_mcb_addr_row17_col11_bnk16_mrank1_3 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_3 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_3 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_3 ))  == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000100    ,            1            ,     (((def_mcb_addr_row17_col10_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_4 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_4 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_4 ))  == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000101    ,            1            ,     (((def_mcb_addr_row16_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_5 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_5 )) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000110    ,            1            ,     (((def_mcb_addr_row15_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_6 )||(def_mcb_addr_row16_col12_bnk16_mrank1_6 )||( def_mcb_addr_row17_col12_bnk8_mrank1_6 )   ||(def_mcb_addr_row16_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_6 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_6 ))   == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b000111    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_7 )||(def_mcb_addr_row16_col11_bnk16_mrank1_7 )||(def_mcb_addr_row15_col12_bnk16_mrank1_7 )||( def_mcb_addr_row17_col11_bnk8_mrank1_7 )||( def_mcb_addr_row16_col12_bnk8_mrank1_7 )||(def_mcb_addr_row15_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_7 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_7 )) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b001000    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_8 )||(def_mcb_addr_row15_col11_bnk16_mrank1_8 )||(def_mcb_addr_row14_col12_bnk16_mrank1_8 )||( def_mcb_addr_row17_col10_bnk8_mrank1_8 )||( def_mcb_addr_row16_col11_bnk8_mrank1_8 )||( def_mcb_addr_row15_col12_bnk8_mrank1_8 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_8 ) ||( def_mcb_addr_row14_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_8 )) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b001001    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank1_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_9 )||(def_mcb_addr_row14_col11_bnk16_mrank1_9 )||( def_mcb_addr_row16_col10_bnk8_mrank1_9 )||( def_mcb_addr_row15_col11_bnk8_mrank1_9 )||( def_mcb_addr_row14_col12_bnk8_mrank1_9 )||( def_mcb_addr_row14_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_9 )) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b001010    ,            1            ,     (((def_mcb_addr_row14_col10_bnk8_mrank1_10)  ||(def_mcb_addr_row14_col10_bnk16_mrank1_10)||( def_mcb_addr_row15_col10_bnk8_mrank1_10)||( def_mcb_addr_row14_col11_bnk8_mrank1_10)) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+    6:11    ,   0b001011    ,            1            ,     (( def_mcb_addr_row14_col10_bnk8_mrank1_11) == 1);         #cfg_a0map_mrank1 Master Rank Bit 1
+}
+
+scom 0x030106C8     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    12:17   ,   0b000000    ,            1            ,     ((def_mcb_mrank2_unset));                             #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b000011    ,            1            ,     ((def_mcb_addr_row17_col12_bnk16_mrank2_3 ) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b000100    ,            1            ,     (((def_mcb_addr_row17_col11_bnk16_mrank2_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_4 )) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b000101    ,            1            ,     (((def_mcb_addr_row17_col10_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_5 )) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b000110    ,            1            ,     (((def_mcb_addr_row16_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_6 )) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b000111    ,            1            ,     (((def_mcb_addr_row15_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_7 )||(def_mcb_addr_row16_col12_bnk16_mrank2_7 )||( def_mcb_addr_row17_col12_bnk8_mrank2_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_7 ))   == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b001000    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_8 )||(def_mcb_addr_row16_col11_bnk16_mrank2_8 )||(def_mcb_addr_row15_col12_bnk16_mrank2_8 )||( def_mcb_addr_row17_col11_bnk8_mrank2_8 )||( def_mcb_addr_row16_col12_bnk8_mrank2_8 )   ||(def_mcb_addr_row15_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_8 ))  == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b001001    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_9 )||(def_mcb_addr_row15_col11_bnk16_mrank2_9 )||(def_mcb_addr_row14_col12_bnk16_mrank2_9 )||( def_mcb_addr_row17_col10_bnk8_mrank2_9 )||( def_mcb_addr_row16_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_9 ) ||( def_mcb_addr_row14_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_9 )) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b001010    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank2_10) ||(def_mcb_addr_row15_col10_bnk16_mrank2_10)||(def_mcb_addr_row14_col11_bnk16_mrank2_10)||( def_mcb_addr_row16_col10_bnk8_mrank2_10)||( def_mcb_addr_row15_col11_bnk8_mrank2_10)||( def_mcb_addr_row14_col12_bnk8_mrank2_10) ||( def_mcb_addr_row14_col10_bnk8_mrank2_10) ||( def_mcb_addr_row15_col10_bnk8_mrank2_10) ||( def_mcb_addr_row14_col11_bnk8_mrank2_10)) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b001011    ,            1            ,     (((def_mcb_addr_row14_col10_bnk8_mrank2_11)  ||(def_mcb_addr_row14_col10_bnk16_mrank2_11)||( def_mcb_addr_row15_col10_bnk8_mrank2_11)||( def_mcb_addr_row14_col11_bnk8_mrank2_11))  == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+    12:17   ,   0b001100    ,            1            ,     (( def_mcb_addr_row14_col10_bnk8_mrank2_12) == 1);         #cfg_a0map_mrank2 Master Rank Rank Bit 2
+}
 
+scom 0x030106C8     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    18:23   ,   0b000000    ,            1            ,     ((def_mcb_mrank3_unset)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b000100    ,            1            ,     ((def_mcb_addr_row17_col12_bnk16_mrank3_4 )                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b000101    ,            1            ,     (((def_mcb_addr_row17_col11_bnk16_mrank3_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_5 ))                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b000110    ,            1            ,     (((def_mcb_addr_row17_col10_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_6 ))                                                                                                                                                                                                                                                                                                                                                                           == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b000111    ,            1            ,     (((def_mcb_addr_row16_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_7 )                                                                                                                                                                                                                             ||(def_mcb_addr_row17_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_7 ))                                                                                                                                          == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001000    ,            1            ,     (((def_mcb_addr_row15_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_8 )||(def_mcb_addr_row16_col12_bnk16_mrank3_8 )||( def_mcb_addr_row17_col12_bnk8_mrank3_8 )                                                                                                                                     ||(def_mcb_addr_row16_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_8 ))   == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001001    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_9 )||(def_mcb_addr_row16_col11_bnk16_mrank3_9 )||(def_mcb_addr_row15_col12_bnk16_mrank3_9 )||( def_mcb_addr_row17_col11_bnk8_mrank3_9 )||( def_mcb_addr_row16_col12_bnk8_mrank3_9 )                                             ||(def_mcb_addr_row15_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_9 ))                                                                                                                                                                                       == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001010    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank3_10) ||(def_mcb_addr_row16_col10_bnk16_mrank3_10)||(def_mcb_addr_row15_col11_bnk16_mrank3_10)||(def_mcb_addr_row14_col12_bnk16_mrank3_10)||( def_mcb_addr_row17_col10_bnk8_mrank3_10)||( def_mcb_addr_row16_col11_bnk8_mrank3_10)||( def_mcb_addr_row15_col12_bnk8_mrank3_10) ||(def_mcb_addr_row15_col10_bnk16_mrank3_10) ||(def_mcb_addr_row14_col11_bnk16_mrank3_10) ||( def_mcb_addr_row14_col10_bnk8_mrank3_10) ||( def_mcb_addr_row15_col10_bnk8_mrank3_10) ||( def_mcb_addr_row16_col10_bnk8_mrank3_10) ||( def_mcb_addr_row14_col11_bnk8_mrank3_10) ||( def_mcb_addr_row15_col11_bnk8_mrank3_10) ||( def_mcb_addr_row14_col12_bnk8_mrank3_10))                                                                                                                                                                                                                                                                                                                                                                           == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001011    ,            1            ,     (((def_mcb_addr_row14_col10_bnk16_mrank3_11) ||(def_mcb_addr_row15_col10_bnk16_mrank3_11)||(def_mcb_addr_row14_col11_bnk16_mrank3_11)||( def_mcb_addr_row16_col10_bnk8_mrank3_11)||( def_mcb_addr_row15_col11_bnk8_mrank3_11)||( def_mcb_addr_row14_col12_bnk8_mrank3_11)                                             ||( def_mcb_addr_row14_col10_bnk8_mrank3_11) ||( def_mcb_addr_row15_col10_bnk8_mrank3_11) ||( def_mcb_addr_row14_col11_bnk8_mrank3_11))                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001100    ,            1            ,     (((def_mcb_addr_row14_col10_bnk8_mrank3_12)  ||(def_mcb_addr_row14_col10_bnk16_mrank3_12)||( def_mcb_addr_row15_col10_bnk8_mrank3_12)||( def_mcb_addr_row14_col11_bnk8_mrank3_12)) == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+    18:23   ,   0b001101    ,            1            ,     (( def_mcb_addr_row14_col10_bnk8_mrank3_13)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     == 1);         #cfg_a0map_mrank3 Master Rank Rank Bit 3
+}
+
+scom 0x030106C8     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    24:29   ,   0b000000    ,            1            ,     ((def_mcb_srank0_unset)                                                                                                                                                                                                                       == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b000101    ,            1            ,     ((def_mcb_addr_col12_bnk16_srank0_5 )                                                                                                                                                                                                         == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b000110    ,            1            ,     (((def_mcb_addr_col11_bnk16_srank0_6 ) ||(def_mcb_addr_col12_bnk16_srank0_6 ) ||( def_mcb_addr_col12_bnk8_srank0_6 ))                                                                                                                         == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b000111    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank0_7 ) ||(def_mcb_addr_col11_bnk16_srank0_7 ) ||(def_mcb_addr_col12_bnk16_srank0_7 ) ||( def_mcb_addr_col11_bnk8_srank0_7 ) ||( def_mcb_addr_col12_bnk8_srank0_7 ))                                           == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b001000    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank0_8 ) ||(def_mcb_addr_col11_bnk16_srank0_8 ) ||(def_mcb_addr_col12_bnk16_srank0_8 ) ||( def_mcb_addr_col10_bnk8_srank0_8 ) ||( def_mcb_addr_col11_bnk8_srank0_8 ) ||( def_mcb_addr_col12_bnk8_srank0_8 ))    == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b001001    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank0_9 ) ||(def_mcb_addr_col11_bnk16_srank0_9 ) ||( def_mcb_addr_col10_bnk8_srank0_9 ) ||( def_mcb_addr_col11_bnk8_srank0_9 ) ||( def_mcb_addr_col12_bnk8_srank0_9 ))                                           == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    24:29   ,   0b001010    ,            1            ,     ((( def_mcb_addr_col10_bnk8_srank0_10) ||( def_mcb_addr_col11_bnk8_srank0_10) ||(def_mcb_addr_col10_bnk16_srank0_10) ||( def_mcb_addr_col10_bnk8_srank0_11))                                                                                  == 1);         #cfg_a0map_srank0 Slave Rank Bit 0 (MSB)
+    30:35   ,   0b000000    ,            1            ,     ((def_mcb_srank1_unset)                                                                                                                                                                                                                       == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b000110    ,            1            ,     ((def_mcb_addr_col12_bnk16_srank1_6 )                                                                                                                                                                                                         == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b000111    ,            1            ,     (((def_mcb_addr_col11_bnk16_srank1_7 ) ||(def_mcb_addr_col12_bnk16_srank1_7 ) ||( def_mcb_addr_col12_bnk8_srank1_7 ))                                                                                                                         == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b001000    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank1_8 ) ||(def_mcb_addr_col11_bnk16_srank1_8 ) ||(def_mcb_addr_col12_bnk16_srank1_8 ) ||( def_mcb_addr_col11_bnk8_srank1_8 ) ||( def_mcb_addr_col12_bnk8_srank1_8 ))                                           == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b001001    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank1_9 ) ||(def_mcb_addr_col11_bnk16_srank1_9 ) ||(def_mcb_addr_col12_bnk16_srank1_9 ) ||( def_mcb_addr_col10_bnk8_srank1_9 ) ||( def_mcb_addr_col11_bnk8_srank1_9 ) ||( def_mcb_addr_col12_bnk8_srank1_9 ))    == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b001010    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank1_10) ||(def_mcb_addr_col11_bnk16_srank1_10) ||( def_mcb_addr_col10_bnk8_srank1_10) ||( def_mcb_addr_col11_bnk8_srank1_10) ||( def_mcb_addr_col12_bnk8_srank1_10))                                           == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b001011    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank1_11) ||( def_mcb_addr_col10_bnk8_srank1_11) ||( def_mcb_addr_col11_bnk8_srank1_11))                                                                                                                         == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+    30:35   ,   0b001100    ,            1            ,     (( def_mcb_addr_col10_bnk8_srank1_12)                                                                                                                                                                                                         == 1);         #cfg_a0map_srank1 Slave Rank Bit 1
+}
+
+scom 0x030106C8     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    36:41   ,   0b000000    ,            1            ,     ((def_mcb_srank2_unset)                                                                                                                                                                                                                                                             == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b000111    ,            1            ,     ((def_mcb_addr_col12_bnk16_srank2_7 )                                                                                                                                                                                                                                               == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001000    ,            1            ,     (((def_mcb_addr_col11_bnk16_srank2_8 ) ||(def_mcb_addr_col12_bnk16_srank2_8 ) ||( def_mcb_addr_col12_bnk8_srank2_8 ))                                                                                                                                                               == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001001    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank2_9 ) ||(def_mcb_addr_col11_bnk16_srank2_9 ) ||(def_mcb_addr_col12_bnk16_srank2_9 ) ||( def_mcb_addr_col11_bnk8_srank2_9 ) ||( def_mcb_addr_col12_bnk8_srank2_9 ))                                                                                 == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001010    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank2_10) ||(def_mcb_addr_col11_bnk16_srank2_10) ||(def_mcb_addr_col12_bnk16_srank2_10) ||( def_mcb_addr_col10_bnk8_srank2_10) ||( def_mcb_addr_col11_bnk8_srank2_10) ||( def_mcb_addr_col12_bnk8_srank2_10) ||(def_mcb_addr_col10_bnk16_srank2_11))   == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001011    ,            1            ,     (((def_mcb_addr_col11_bnk16_srank2_11) ||( def_mcb_addr_col10_bnk8_srank2_11) ||( def_mcb_addr_col11_bnk8_srank2_11) ||( def_mcb_addr_col12_bnk8_srank2_11))                                                                                                                        == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001100    ,            1            ,     (((def_mcb_addr_col10_bnk16_srank2_12) ||( def_mcb_addr_col10_bnk8_srank2_12) ||( def_mcb_addr_col11_bnk8_srank2_12))                                                                                                                                                               == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    36:41   ,   0b001101    ,            1            ,     (( def_mcb_addr_col10_bnk8_srank2_13)                                                                                                                                                                                                                                               == 1);         #cfg_a0map_srank2 Slave Rank Rank Bit 2
+    42:47   ,   0b011011    ,            1            ,     (def_mcb_addr_bank3_27      == 1);         #cfg_a0map_bank3  DRAM Bank Address Bit 3 (MSB)
+    42:47   ,   0b011010    ,            1            ,     (def_mcb_addr_bank3_26      == 1);         #cfg_a0map_bank3  DRAM Bank Address Bit 3 (MSB)
+    42:47   ,   0b011001    ,            1            ,     (def_mcb_addr_bank3_25      == 1);         #cfg_a0map_bank3  DRAM Bank Address Bit 3 (MSB)
+    42:47   ,   0b000000    ,            1            ,     (def_mcb_addr_unset_bank3   == 1);         #cfg_a0map_bank3  DRAM Bank Address Bit 3 (MSB)
+    48:53   ,   0b011100    ,            1            ,     (def_mcb_addr_bank2_28      == 1);         #cfg_a0map_bank2  DRAM Bank Address Bit 2 (MSB)
+    48:53   ,   0b011011    ,            1            ,     (def_mcb_addr_bank2_27      == 1);         #cfg_a0map_bank2  DRAM Bank Address Bit 2 (MSB)
+    48:53   ,   0b011010    ,            1            ,     (def_mcb_addr_bank2_26      == 1);         #cfg_a0map_bank2  DRAM Bank Address Bit 2 (MSB)
+    54:59   ,   0b011101    ,            1            ,     (def_mcb_addr_bank1_29      == 1);         #cfg_a0map_bank1  DRAM Bank Address Bit 1
+    54:59   ,   0b011100    ,            1            ,     (def_mcb_addr_bank1_28      == 1);         #cfg_a0map_bank1  DRAM Bank Address Bit 1
+    54:59   ,   0b011011    ,            1            ,     (def_mcb_addr_bank1_27      == 1);         #cfg_a0map_bank1  DRAM Bank Address Bit 1
+}
+
+
+scom 0x030106C9     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    0:5     ,   0b011110    ,            1           ,      (def_mcb_addr_bank0_30    == 1);         #cfg_a0map_bank0 DRAM Bank Address Bit 0
+    0:5     ,   0b011101    ,            1           ,      (def_mcb_addr_bank0_29    == 1);         #cfg_a0map_bank0 DRAM Bank Address Bit 0
+    0:5     ,   0b011100    ,            1           ,      (def_mcb_addr_bank0_28    == 1);         #cfg_a0map_bank0 DRAM Bank Address Bit 0
+    6:11    ,   0b001011    ,            1           ,      (def_mcb_addr_row16_11       == 1);         #cfg_a0map_row16 DRAM Row Address Bit16 (MSB)
+    6:11    ,   0b001010    ,            1           ,      (def_mcb_addr_row16_10       == 1);         #cfg_a0map_row16 DRAM Row Address Bit16 (MSB)
+    6:11    ,   0b001001    ,            1           ,      (def_mcb_addr_row16_9        == 1);         #cfg_a0map_row16 DRAM Row Address Bit16 (MSB)
+    6:11    ,   0b001000    ,            1           ,      (def_mcb_addr_row16_8        == 1);         #cfg_a0map_row16 DRAM Row Address Bit16 (MSB)
+    6:11    ,   0b000000    ,            1           ,      (def_mcb_addr_unset_row16    == 1);         #cfg_a0map_row16 DRAM Row Address Bit16 (MSB)
+    12:17   ,   0b001100    ,            1           ,      (def_mcb_addr_row15_12       == 1);         #cfg_a0map_row15 DRAM Row Address Bit15
+    12:17   ,   0b001011    ,            1           ,      (def_mcb_addr_row15_11       == 1);         #cfg_a0map_row15 DRAM Row Address Bit15
+    12:17   ,   0b001010    ,            1           ,      (def_mcb_addr_row15_10       == 1);         #cfg_a0map_row15 DRAM Row Address Bit15
+    12:17   ,   0b001001    ,            1           ,      (def_mcb_addr_row15_9        == 1);         #cfg_a0map_row15 DRAM Row Address Bit15
+    12:17   ,   0b000000    ,            1           ,      (def_mcb_addr_unset_row15    == 1);         #cfg_a0map_row15 DRAM Row Address Bit15
+    18:23   ,   0b001101    ,            1           ,      (def_mcb_addr_row14_13       == 1);         #cfg_a0map_row14 DRAM Row Address Bit 14
+    18:23   ,   0b001100    ,            1           ,      (def_mcb_addr_row14_12       == 1);         #cfg_a0map_row14 DRAM Row Address Bit 14
+    18:23   ,   0b001011    ,            1           ,      (def_mcb_addr_row14_11       == 1);         #cfg_a0map_row14 DRAM Row Address Bit 14
+    18:23   ,   0b001010    ,            1           ,      (def_mcb_addr_row14_10       == 1);         #cfg_a0map_row14 DRAM Row Address Bit 14
+    18:23   ,   0b000000    ,            1           ,      (def_mcb_addr_unset_row14    == 1);         #cfg_a0map_row14 DRAM Row Address Bit 14
+    24:29   ,   0b001110    ,            1           ,      (def_mcb_addr_row13_14       == 1);         #cfg_a0map_row13 DRAM Row Address Bit 13
+    24:29   ,   0b001101    ,            1           ,      (def_mcb_addr_row13_13       == 1);         #cfg_a0map_row13 DRAM Row Address Bit 13
+    24:29   ,   0b001100    ,            1           ,      (def_mcb_addr_row13_12       == 1);         #cfg_a0map_row13 DRAM Row Address Bit 13
+    24:29   ,   0b001011    ,            1           ,      (def_mcb_addr_row13_11       == 1);         #cfg_a0map_row13 DRAM Row Address Bit 13
+    30:35   ,   0b001111    ,            1           ,      (def_mcb_addr_row12_15       == 1);         #cfg_a0map_row12 DRAM Row Address Bit 12
+    30:35   ,   0b001110    ,            1           ,      (def_mcb_addr_row12_14       == 1);         #cfg_a0map_row12 DRAM Row Address Bit 12
+    30:35   ,   0b001101    ,            1           ,      (def_mcb_addr_row12_13       == 1);         #cfg_a0map_row12 DRAM Row Address Bit 12
+    30:35   ,   0b001100    ,            1           ,      (def_mcb_addr_row12_12       == 1);         #cfg_a0map_row12 DRAM Row Address Bit 12
+    36:41   ,   0b010000    ,            1           ,      (def_mcb_addr_row11_16       == 1);         #cfg_a0map_row11 DRAM Row Address Bit 11
+    36:41   ,   0b001111    ,            1           ,      (def_mcb_addr_row11_15       == 1);         #cfg_a0map_row11 DRAM Row Address Bit 11
+    36:41   ,   0b001110    ,            1           ,      (def_mcb_addr_row11_14       == 1);         #cfg_a0map_row11 DRAM Row Address Bit 11
+    36:41   ,   0b001101    ,            1           ,      (def_mcb_addr_row11_13       == 1);         #cfg_a0map_row11 DRAM Row Address Bit 11
+    42:47   ,   0b010001    ,            1           ,      (def_mcb_addr_row10_17       == 1);         #cfg_a0map_row10 DRAM Row Address Bit 10
+    42:47   ,   0b010000    ,            1           ,      (def_mcb_addr_row10_16       == 1);         #cfg_a0map_row10 DRAM Row Address Bit 10
+    42:47   ,   0b001111    ,            1           ,      (def_mcb_addr_row10_15       == 1);         #cfg_a0map_row10 DRAM Row Address Bit 10
+    42:47   ,   0b001110    ,            1           ,      (def_mcb_addr_row10_14       == 1);         #cfg_a0map_row10 DRAM Row Address Bit 10
+    48:53   ,   0b010010    ,            1           ,      (def_mcb_addr_row9_18        == 1);         #cfg_a0map_row9  DRAM Row Address Bit 9
+    48:53   ,   0b010001    ,            1           ,      (def_mcb_addr_row9_17        == 1);         #cfg_a0map_row9  DRAM Row Address Bit 9
+    48:53   ,   0b010000    ,            1           ,      (def_mcb_addr_row9_16        == 1);         #cfg_a0map_row9  DRAM Row Address Bit 9
+    48:53   ,   0b001111    ,            1           ,      (def_mcb_addr_row9_15        == 1);         #cfg_a0map_row9  DRAM Row Address Bit 9
+    54:59   ,   0b010011    ,            1           ,      (def_mcb_addr_row8_19        == 1);         #cfg_a0map_row8  DRAM Row Address Bit 8
+    54:59   ,   0b010010    ,            1           ,      (def_mcb_addr_row8_18        == 1);         #cfg_a0map_row8  DRAM Row Address Bit 8
+    54:59   ,   0b010001    ,            1           ,      (def_mcb_addr_row8_17        == 1);         #cfg_a0map_row8  DRAM Row Address Bit 8
+    54:59   ,   0b010000    ,            1           ,      (def_mcb_addr_row8_16        == 1);         #cfg_a0map_row8  DRAM Row Address Bit 8
+}
+
+scom 0x030106CA     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    0:5     ,   0b010100    ,            1           ,      (def_mcb_addr_row7_20    == 1);         #cfg_a0map_row7   DRAM Row Address Bit 7
+    0:5     ,   0b010011    ,            1           ,      (def_mcb_addr_row7_19    == 1);         #cfg_a0map_row7   DRAM Row Address Bit 7
+    0:5     ,   0b010010    ,            1           ,      (def_mcb_addr_row7_18    == 1);         #cfg_a0map_row7   DRAM Row Address Bit 7
+    0:5     ,   0b010001    ,            1           ,      (def_mcb_addr_row7_17    == 1);         #cfg_a0map_row7   DRAM Row Address Bit 7
+    6:11    ,   0b010101    ,            1           ,      (def_mcb_addr_row6_21    == 1);         #cfg_a0map_row6   DRAM Row Address Bit 6
+    6:11    ,   0b010100    ,            1           ,      (def_mcb_addr_row6_20    == 1);         #cfg_a0map_row6   DRAM Row Address Bit 6
+    6:11    ,   0b010011    ,            1           ,      (def_mcb_addr_row6_19    == 1);         #cfg_a0map_row6   DRAM Row Address Bit 6
+    6:11    ,   0b010010    ,            1           ,      (def_mcb_addr_row6_18    == 1);         #cfg_a0map_row6   DRAM Row Address Bit 6
+    12:17   ,   0b010110    ,            1           ,      (def_mcb_addr_row5_22    == 1);         #cfg_a0map_row5   DRAM Row Address Bit 5
+    12:17   ,   0b010101    ,            1           ,      (def_mcb_addr_row5_21    == 1);         #cfg_a0map_row5   DRAM Row Address Bit 5
+    12:17   ,   0b010100    ,            1           ,      (def_mcb_addr_row5_20    == 1);         #cfg_a0map_row5   DRAM Row Address Bit 5
+    12:17   ,   0b010011    ,            1           ,      (def_mcb_addr_row5_19    == 1);         #cfg_a0map_row5   DRAM Row Address Bit 5
+    18:23   ,   0b010111    ,            1           ,      (def_mcb_addr_row4_23    == 1);         #cfg_a0map_row4   DRAM Row Address Bit 4
+    18:23   ,   0b010110    ,            1           ,      (def_mcb_addr_row4_22    == 1);         #cfg_a0map_row4   DRAM Row Address Bit 4
+    18:23   ,   0b010101    ,            1           ,      (def_mcb_addr_row4_21    == 1);         #cfg_a0map_row4   DRAM Row Address Bit 4
+    18:23   ,   0b010100    ,            1           ,      (def_mcb_addr_row4_20    == 1);         #cfg_a0map_row4   DRAM Row Address Bit 4
+    24:29   ,   0b011000    ,            1           ,      (def_mcb_addr_row3_24    == 1);         #cfg_a0map_row3   DRAM Row Address Bit 3
+    24:29   ,   0b010111    ,            1           ,      (def_mcb_addr_row3_23    == 1);         #cfg_a0map_row3   DRAM Row Address Bit 3
+    24:29   ,   0b010110    ,            1           ,      (def_mcb_addr_row3_22    == 1);         #cfg_a0map_row3   DRAM Row Address Bit 3
+    24:29   ,   0b010101    ,            1           ,      (def_mcb_addr_row3_21    == 1);         #cfg_a0map_row3   DRAM Row Address Bit 3
+    30:35   ,   0b011001    ,            1           ,      (def_mcb_addr_row2_25    == 1);         #cfg_a0map_row2   DRAM Row Address Bit 2
+    30:35   ,   0b011000    ,            1           ,      (def_mcb_addr_row2_24    == 1);         #cfg_a0map_row2   DRAM Row Address Bit 2
+    30:35   ,   0b010111    ,            1           ,      (def_mcb_addr_row2_23    == 1);         #cfg_a0map_row2   DRAM Row Address Bit 2
+    30:35   ,   0b010110    ,            1           ,      (def_mcb_addr_row2_22    == 1);         #cfg_a0map_row2   DRAM Row Address Bit 2
+    36:41   ,   0b011010    ,            1           ,      (def_mcb_addr_row1_26    == 1);         #cfg_a0map_row1   DRAM Row Address Bit 1
+    36:41   ,   0b011001    ,            1           ,      (def_mcb_addr_row1_25    == 1);         #cfg_a0map_row1   DRAM Row Address Bit 1
+    36:41   ,   0b011000    ,            1           ,      (def_mcb_addr_row1_24    == 1);         #cfg_a0map_row1   DRAM Row Address Bit 1
+    36:41   ,   0b010111    ,            1           ,      (def_mcb_addr_row1_23    == 1);         #cfg_a0map_row1   DRAM Row Address Bit 1
+    42:47   ,   0b011011    ,            1           ,      (def_mcb_addr_row0_27    == 1);         #cfg_a0map_row0   DRAM Row Address Bit 0
+    42:47   ,   0b011010    ,            1           ,      (def_mcb_addr_row0_26    == 1);         #cfg_a0map_row0   DRAM Row Address Bit 0
+    42:47   ,   0b011001    ,            1           ,      (def_mcb_addr_row0_25    == 1);         #cfg_a0map_row0   DRAM Row Address Bit 0
+    42:47   ,   0b011000    ,            1           ,      (def_mcb_addr_row0_24    == 1);         #cfg_a0map_row0   DRAM Row Address Bit 0
+    48:53   ,   0b000000    ,            1           ,      (def_mcb_addr_unset_col13 == 1);     #cfg_a0map_col13  DRAM Column Address Bit 13  (MSB)
+    48:53   ,   0b011101    ,            1           ,      (def_mcb_addr_col13_29 == 1);        #cfg_a0map_col13  DRAM Column Address Bit 13  (MSB)
+    54:59   ,   0b000000    ,            1           ,      (def_mcb_addr_unset_col11 == 1);     #cfg_a0map_col11  DRAM Column Address Bit 11
+    54:59   ,   0b011110    ,            1           ,      (def_mcb_addr_col11_30 == 1);        #cfg_a0map_col11  DRAM Column Address Bit 11
+}
+
+scom 0x030106CB     {
+    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,     expr;
+    0:5     ,   0b011111    ,            1           ,      any;         #cfg_a0map_col9 DRAM Column Address Bit 9
+    6:11    ,   0b100000    ,            1           ,      any;         #cfg_a0map_col8 DRAM Column Address Bit 8
+    12:17   ,   0b100001    ,            1           ,      any;         #cfg_a0map_col7 DRAM Column Address Bit 7
+    18:23   ,   0b100010    ,            1           ,      any;         #cfg_a0map_col6 DRAM Column Address Bit 6
+    24:29   ,   0b100011    ,            1           ,      any;         #cfg_a0map_col5 DRAM Column Address Bit 5
+    30:35   ,   0b100100    ,            1           ,      any;         #cfg_a0map_col4 DRAM Column Address Bit 4
+    36:41   ,   0b100101    ,            1           ,      any;         #cfg_a0map_col3 DRAM Column Address Bit 3
+#    42:47   ,   0b100101    ,            1           ,      any;         #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4
+    42:47   ,   0b000000    ,            1           ,      any;         #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4
+}
 
 
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index c35a52288..37277bdc2 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,8 +1,10 @@
-#-- $Id: mbs_def.initfile,v 1.19 2012/08/21 23:01:12 mwuu Exp $
+#-- $Id: mbs_def.initfile,v 1.23 2012/10/23 14:29:41 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--   1.21  |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests)
+#--   1.20  |tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL
 #--   1.19  |menlowuu|08/21/12| fixed 2 address typo's
 #--   1.18  |tschang |08/20/12| added mbs mcbist setup values for simple write and read test
 #--   1.17  |bellows |07/23/12| made ATTR_MSS_CACHE_ENABLE at centaur level instead of system
@@ -398,15 +400,15 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    = (def_mb
 # Name = MBU.MBS.ECC01 (scomdef)
 # MBSECCQ   MBS Memory ECC Control Register (01)
 scom 0x0201144A   {
-    bits,       scom_data   ;
-    0   ,       0b1     ;  # disable mba23 memory ecc check/correct
+    bits,       scom_data   , MBA0.ATTR_FUNCTIONAL, expr ;
+    0   ,       0b1         ,        1            , any ;  # disable mba01 memory ecc check/correct
 }
 
 # Name = MBU.MBS.ECC23 (scomdef)
 # MBSECCQ   MBS Memory ECC Control Register (23)
 scom 0x0201148A   {
-   bits,       scom_data   ;
-   0   ,       0b1     ;  # disable MBA23 memory ecc check/correct
+    bits,       scom_data   , MBA1.ATTR_FUNCTIONAL, expr ;
+    0   ,       0b1         ,        1            , any ;  # disable MBA23 memory ecc check/correct
 }
 
 ######################
@@ -474,13 +476,19 @@ scom 0x0201140F   {
 
 
 scom 0x0201140D {
-    bits,       scom_data   ,	expr;
-     0:2  ,       0b000   , 	any;		# MBA01_master_rank_0_select is 0 for all cfgs
-     3:5  ,       0b001   , 	any;		# MBA01_master_rank_1_select is 1 for all cfgs
-     6:8  ,       0b010   , 	any;		# MBA01_master_rank_2_select is 2 for all cfgs
-    24:26 ,       0b000   , 	any;		# MBA23_master_rank_0_select is 0 for all cfgs
-    27:29 ,       0b001   , 	any;		# MBA23_master_rank_1_select is 1 for all cfgs
-    30:32 ,       0b010   , 	any;		# MBA23_master_rank_2_select is 2 for all cfgs
+    bits,       scom_data  , MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr;
+     0:2  ,       0b000    ,        1            ,          0          , any;		# MBA01_master_rank_0_select is 0 for all cfgs
+     0:2  ,       0b000    ,        1            ,          1          , any;		# MBA01_master_rank_0_select is 0 for all cfgs
+     3:5  ,       0b001    ,        1            ,          0          , any;		# MBA01_master_rank_1_select is 1 for all cfgs
+     3:5  ,       0b001    ,        1            ,          1          , any;		# MBA01_master_rank_1_select is 1 for all cfgs
+     6:8  ,       0b010    ,        1            ,          0          , any;		# MBA01_master_rank_2_select is 2 for all cfgs
+     6:8  ,       0b010    ,        1            ,          1          , any;		# MBA01_master_rank_2_select is 2 for all cfgs
+    24:26 ,       0b000    ,        0            ,          1          , any;		# MBA23_master_rank_0_select is 0 for all cfgs
+    24:26 ,       0b000    ,        1            ,          1          , any;		# MBA23_master_rank_0_select is 0 for all cfgs
+    27:29 ,       0b001    ,        0            ,          1          , any;		# MBA23_master_rank_1_select is 1 for all cfgs
+    27:29 ,       0b001    ,        1            ,          1          , any;		# MBA23_master_rank_1_select is 1 for all cfgs
+    30:32 ,       0b010    ,        0            ,          1          , any;		# MBA23_master_rank_2_select is 2 for all cfgs
+    30:32 ,       0b010    ,        1            ,          1          , any;		# MBA23_master_rank_2_select is 2 for all cfgs
 }
 
 
@@ -495,17 +503,17 @@ scom 0x0201140D {
 scom 0x0201140A {
     bits,       scom_data   ,	expr;
 #     0:4 ,       0b10001 , 	any;		#-MW to match dials
-     0:4 ,       0b00000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 0);                        # no MBA interleave
-     0:4 ,       0b10000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 23);                       #
-     0:4 ,       0b10001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 24);                       #
-     0:4 ,       0b10010 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 25);                       #
-     0:4 ,       0b10011 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 26);                       #
-     0:4 ,       0b10100 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 27);                       #
-     0:4 ,       0b10101 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 28);                       #
-     0:4 ,       0b10110 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 29);                       #
-     0:4 ,       0b10111 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 30);                       #
-     0:4 ,       0b11000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 31);                       #
-     0:4 ,       0b11001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 32);                       #
+     0:4 ,       0b00000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 0) || (MBA0.ATTR_FUNCTIONAL == 0) || (MBA1.ATTR_FUNCTIONAL == 0);                        # no MBA interleave
+     0:4 ,       0b10000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 23) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 24) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10010 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 25) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10011 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 26) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10100 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 27) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10101 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 28) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10110 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 29) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b10111 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 30) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b11000 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 31) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
+     0:4 ,       0b11001 , (SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT == 32) && (MBA0.ATTR_FUNCTIONAL == 1) && (MBA1.ATTR_FUNCTIONAL == 1);                       #
      5   ,       0b0       , any      ;                       # Z mode only
 }
 
@@ -519,35 +527,35 @@ scom 0x0201140A {
 #
 
 scom 0x0201140B     {
-    bits    ,   scom_data   , expr;
-    0:3     ,   0b0000  , (def_mba01_nomem == 1);                                     # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0001  , (def_type1_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0010  , (def_type2_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0011  , (def_type3_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0100  , (def_type4_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0101  , (def_type5_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0110  , (def_type6_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-    0:3     ,   0b0111  , (def_type7_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-#    0:3     ,   0b1000  , (def_type8_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
-#    4:5     ,   0b01    , any                           ; # temp until ibm type is fully supported             # MBAXCR01Q_MBA01_config_subtype                    D
-    4:5     ,   0b00    , (def_mba01_subtype_A == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
-    4:5     ,   0b01    , (def_mba01_subtype_B == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
-    4:5     ,   0b10    , (def_mba01_subtype_C == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
-    6:7     ,   0b00    , (MBA0.ATTR_EFF_DRAM_DENSITY == 2);   # MBAXCR01Q_MBA01_DRAM_size                         D
-    6:7     ,   0b01    , (MBA0.ATTR_EFF_DRAM_DENSITY == 4);   # MBAXCR01Q_MBA01_DRAM_size                         D
-    6:7     ,   0b10    , (MBA0.ATTR_EFF_DRAM_DENSITY == 8);   # MBAXCR01Q_MBA01_DRAM_size                         D
-    8       ,   0b0     , (def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1);                # MBAXCR01Q_MBA01_Configuration                                          D
-    8       ,   0b1     , (def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    == 1);                # MBAXCR01Q_MBA01_Configuration                                          D
-#    8       ,   0b0     , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0);                # MBAXCR01Q_MBA01_Configuration                                           D
-#    8       ,   0b1     , ((((MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1);                # MBAXCR01Q_MBA01_Configuration   D
-    9       ,   0b1     , (MBA0.ATTR_EFF_DRAM_WIDTH == 4);     # MBAXCR01Q_MBA01_DRAM_Width                    D
-    9       ,   0b0     , (MBA0.ATTR_EFF_DRAM_WIDTH == 8);     # MBAXCR01Q_MBA01_DRAM_Width                    D
-    10:11   ,   0b00    , (SYS.ATTR_MSS_MCA_HASH_MODE == 0);  # MBAXCR01Q_MBA01_Hash_Mode
-    10:11   ,   0b01    , (SYS.ATTR_MSS_MCA_HASH_MODE == 1);  # MBAXCR01Q_MBA01_Hash_Mode
-    10:11   ,   0b10    , (SYS.ATTR_MSS_MCA_HASH_MODE == 2);  # MBAXCR01Q_MBA01_Hash_Mode
-#    12      ,   0b0     , any;							# -MW match dials  # MBAXCR01Q_MBA01_Interleave_Mode
-    12      ,   0b0     , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0);  # MBAXCR01Q_MBA01_Interleave_Mode
-    12      ,   0b1     , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1);  # MBAXCR01Q_MBA01_Interleave_Mode
+    bits    ,   scom_data   , MBA0.ATTR_FUNCTIONAL, expr;
+    0:3     ,   0b0000      ,         1           , (def_mba01_nomem == 1);                                     # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0001      ,         1           , (def_type1_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0010      ,         1           , (def_type2_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0011      ,         1           , (def_type3_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0100      ,         1           , (def_type4_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0101      ,         1           , (def_type5_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0110      ,         1           , (def_type6_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+    0:3     ,   0b0111      ,         1           , (def_type7_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+#    0:3     ,   0b1000      ,         1           , (def_type8_memory_populated_behind_MBA01 == 1);             # MBAXCR01Q_MBA01_config_type    D
+#    4:5     ,   0b01        ,         1           , any                           ; # temp until ibm type is fully supported             # MBAXCR01Q_MBA01_config_subtype                    D
+    4:5     ,   0b00        ,         1           , (def_mba01_subtype_A == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
+    4:5     ,   0b01        ,         1           , (def_mba01_subtype_B == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
+    4:5     ,   0b10        ,         1           , (def_mba01_subtype_C == 1);              # MBAXCR01Q_MBA01_config_subtype                    D
+    6:7     ,   0b00        ,         1           , (MBA0.ATTR_EFF_DRAM_DENSITY == 2);   # MBAXCR01Q_MBA01_DRAM_size                         D
+    6:7     ,   0b01        ,         1           , (MBA0.ATTR_EFF_DRAM_DENSITY == 4);   # MBAXCR01Q_MBA01_DRAM_size                         D
+    6:7     ,   0b10        ,         1           , (MBA0.ATTR_EFF_DRAM_DENSITY == 8);   # MBAXCR01Q_MBA01_DRAM_size                         D
+    8       ,   0b0         ,         1           , (def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1);                # MBAXCR01Q_MBA01_Configuration                                          D
+    8       ,   0b1         ,         1           , (def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    == 1);                # MBAXCR01Q_MBA01_Configuration                                          D
+#    8       ,   0b0         ,         1           , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0);                # MBAXCR01Q_MBA01_Configuration                                           D
+#    8       ,   0b1         ,         1           , ((((MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1);                # MBAXCR01Q_MBA01_Configuration   D
+    9       ,   0b1         ,         1           , (MBA0.ATTR_EFF_DRAM_WIDTH == 4);     # MBAXCR01Q_MBA01_DRAM_Width                    D
+    9       ,   0b0         ,         1           , (MBA0.ATTR_EFF_DRAM_WIDTH == 8);     # MBAXCR01Q_MBA01_DRAM_Width                    D
+    10:11   ,   0b00        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 0);  # MBAXCR01Q_MBA01_Hash_Mode
+    10:11   ,   0b01        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 1);  # MBAXCR01Q_MBA01_Hash_Mode
+    10:11   ,   0b10        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 2);  # MBAXCR01Q_MBA01_Hash_Mode
+#    12      ,   0b0         ,         1           , any;							# -MW match dials  # MBAXCR01Q_MBA01_Interleave_Mode
+    12      ,   0b0         ,         1           , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0);  # MBAXCR01Q_MBA01_Interleave_Mode
+    12      ,   0b1         ,         1           , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1);  # MBAXCR01Q_MBA01_Interleave_Mode
 }
 
 
@@ -560,35 +568,35 @@ scom 0x0201140B     {
 # MBAXCR23Q MBA23 Address Translate Control Register
 #
 scom 0x0201140C     {
-    bits    ,   scom_data   , expr;
-    0:3     ,   0b0000  , (def_mba23_nomem == 1);                                     # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0001  , (def_type1_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0010  , (def_type2_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0011  , (def_type3_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0100  , (def_type4_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0101  , (def_type5_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0110  , (def_type6_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-    0:3     ,   0b0111  , (def_type7_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-#    0:3     ,   0b1000  , (def_type8_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
-#    4:5     ,   0b01    , any                       ;# temp until ibm type is fully supported               # MBAXCR01Q_MBA23_config_subtype                    D
-    4:5     ,   0b00    , (def_mba23_subtype_A == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
-    4:5     ,   0b01    , (def_mba23_subtype_B == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
-    4:5     ,   0b10    , (def_mba23_subtype_C == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
-    6:7     ,   0b00    , (MBA1.ATTR_EFF_DRAM_DENSITY == 2);   # MBAXCR01Q_MBA23_DRAM_size                         D
-    6:7     ,   0b01    , (MBA1.ATTR_EFF_DRAM_DENSITY == 4);   # MBAXCR01Q_MBA23_DRAM_size                         D
-    6:7     ,   0b10    , (MBA1.ATTR_EFF_DRAM_DENSITY == 8);   # MBAXCR01Q_MBA23_DRAM_size                         D
-    8       ,   0b0     , (def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1);                # MBAXCR01Q_MBA23_Configuration                                          D
-    8       ,   0b1     , (def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    == 1);                # MBAXCR01Q_MBA23_Configuration                                          D
-#    8       ,   0b0     , (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0);                # MBAXCR01Q_MBA23_Configuration                                           D
-#    8       ,   0b1     , ((((ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1);                # MBAXCR01Q_MBA23_Configuration   D
-    9       ,   0b1     , (MBA1.ATTR_EFF_DRAM_WIDTH == 4);     # MBAXCR01Q_MBA23_DRAM_Width                    D
-    9       ,   0b0     , (MBA1.ATTR_EFF_DRAM_WIDTH == 8);     # MBAXCR01Q_MBA23_DRAM_Width                    D
-    10:11   ,   0b00    , (SYS.ATTR_MSS_MCA_HASH_MODE == 0);  # MBAXCR01Q_MBA23_Hash_Mode
-    10:11   ,   0b01    , (SYS.ATTR_MSS_MCA_HASH_MODE == 1);  # MBAXCR01Q_MBA23_Hash_Mode
-    10:11   ,   0b10    , (SYS.ATTR_MSS_MCA_HASH_MODE == 2);  # MBAXCR01Q_MBA23_Hash_Mode
-#    12      ,   0b0     , any;							# -MW match dials  # MBAXCR01Q_MBA23_Interleave_Mode
-    12      ,   0b0     , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0);  # MBAXCR01Q_MBA23_Interleave_Mode
-    12      ,   0b1     , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1);  # MBAXCR01Q_MBA23_Interleave_Mode
+    bits    ,   scom_data   , MBA1.ATTR_FUNCTIONAL, expr;
+    0:3     ,   0b0000      ,         1           , (def_mba23_nomem == 1);                                     # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0001      ,         1           , (def_type1_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0010      ,         1           , (def_type2_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0011      ,         1           , (def_type3_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0100      ,         1           , (def_type4_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0101      ,         1           , (def_type5_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0110      ,         1           , (def_type6_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+    0:3     ,   0b0111      ,         1           , (def_type7_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+#    0:3     ,   0b1000      ,         1           , (def_type8_memory_populated_behind_MBA23 == 1);             # MBAXCR01Q_MBA23_config_type    D
+#    4:5     ,   0b01        ,         1           , any                       ;# temp until ibm type is fully supported               # MBAXCR01Q_MBA23_config_subtype                    D
+    4:5     ,   0b00        ,         1           , (def_mba23_subtype_A == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
+    4:5     ,   0b01        ,         1           , (def_mba23_subtype_B == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
+    4:5     ,   0b10        ,         1           , (def_mba23_subtype_C == 1);              # MBAXCR01Q_MBA23_config_subtype                    D
+    6:7     ,   0b00        ,         1           , (MBA1.ATTR_EFF_DRAM_DENSITY == 2);   # MBAXCR01Q_MBA23_DRAM_size                         D
+    6:7     ,   0b01        ,         1           , (MBA1.ATTR_EFF_DRAM_DENSITY == 4);   # MBAXCR01Q_MBA23_DRAM_size                         D
+    6:7     ,   0b10        ,         1           , (MBA1.ATTR_EFF_DRAM_DENSITY == 8);   # MBAXCR01Q_MBA23_DRAM_size                         D
+    8       ,   0b0         ,         1           , (def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1);                # MBAXCR01Q_MBA23_Configuration                                          D
+    8       ,   0b1         ,         1           , (def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    == 1);                # MBAXCR01Q_MBA23_Configuration                                          D
+#    8       ,   0b0         ,         1           , (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_CHIP_UNIT_POS == 0);                # MBAXCR01Q_MBA23_Configuration                                           D
+#    8       ,   0b1         ,         1           , ((((ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1);                # MBAXCR01Q_MBA23_Configuration   D
+    9       ,   0b1         ,         1           , (MBA1.ATTR_EFF_DRAM_WIDTH == 4);     # MBAXCR01Q_MBA23_DRAM_Width                    D
+    9       ,   0b0         ,         1           , (MBA1.ATTR_EFF_DRAM_WIDTH == 8);     # MBAXCR01Q_MBA23_DRAM_Width                    D
+    10:11   ,   0b00        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 0);  # MBAXCR01Q_MBA23_Hash_Mode
+    10:11   ,   0b01        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 1);  # MBAXCR01Q_MBA23_Hash_Mode
+    10:11   ,   0b10        ,         1           , (SYS.ATTR_MSS_MCA_HASH_MODE == 2);  # MBAXCR01Q_MBA23_Hash_Mode
+#    12      ,   0b0         ,         1           , any;							# -MW match dials  # MBAXCR01Q_MBA23_Interleave_Mode
+    12      ,   0b0         ,         1           , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0);  # MBAXCR01Q_MBA23_Interleave_Mode
+    12      ,   0b1         ,         1           , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1);  # MBAXCR01Q_MBA23_Interleave_Mode
 }
 
 
@@ -599,60 +607,118 @@ scom 0x0201140C     {
 ###########################################################################################
 
 ###################################
-# MCBIST Fixed data pattern
+# MCBIST Fixed data pattern MBA01
 ###################################
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef)
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef)
 # Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef)
 
 scom 0x02011681     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x1111111111111111, any;         # Fixed data burst 0
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x1111111111111111,        1            , any;         # Fixed data burst 0
 }
 
 scom 0x02011682     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x2222222222222222, any;         # Fixed data burst 1
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x2222222222222222,        1            , any;         # Fixed data burst 1
 }
 
 scom 0x02011683     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x3333333333333333, any;         # Fixed data burst 2
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x3333333333333333,        1            , any;         # Fixed data burst 2
 }
 
 scom 0x02011684     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x4444444444444444, any;         # Fixed data burst 3
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x4444444444444444,        1            , any;         # Fixed data burst 3
 }
 
 scom 0x02011685     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x5555555555555555, any;         # Fixed data burst 4
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x5555555555555555,        1            , any;         # Fixed data burst 4
 }
 
 scom 0x02011686     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x6666666666666666, any;         # Fixed data burst 5
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x6666666666666666,        1            , any;         # Fixed data burst 5
 }
 
 scom 0x02011687     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x7777777777777777, any;         # Fixed data burst 6
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x7777777777777777,        1            , any;         # Fixed data burst 6
 }
 
 scom 0x02011688     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x8888888888888888, any;         # Fixed data burst 7
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x8888888888888888,        1            , any;         # Fixed data burst 7
 }
 
 scom 0x02011689     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0x9999999999999999, any;         # Fixed data burst 0-7 ECC bits
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x9999999999999999,        1            , any;         # Fixed data burst 0-7 ECC bits
 }
 
 scom 0x0201168A     {
-    bits    ,   scom_data   , expr;
-    0:63    ,   0xAAAAAAAAAAAAAAAA, any;         # Fixed data burst 0-7 SPARE bits
+    bits    ,   scom_data         , MBA0.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0xAAAAAAAAAAAAAAAA,        1            , any;         # Fixed data burst 0-7 SPARE bits
+}
+
+
+###################################
+# MCBIST Fixed data pattern MBA23
+###################################
+# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef)
+# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef)
+# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef)
+
+scom 0x02011781     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x1111111111111111,        1            , any;         # Fixed data burst 0
+}
+
+scom 0x02011782     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x2222222222222222,        1            , any;         # Fixed data burst 1
+}
+
+scom 0x02011783     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x3333333333333333,        1            , any;         # Fixed data burst 2
+}
+
+scom 0x02011784     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x4444444444444444,        1            , any;         # Fixed data burst 3
+}
+
+scom 0x02011785     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x5555555555555555,        1            , any;         # Fixed data burst 4
+}
+
+scom 0x02011786     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x6666666666666666,        1            , any;         # Fixed data burst 5
+}
+
+scom 0x02011787     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x7777777777777777,        1            , any;         # Fixed data burst 6
+}
+
+scom 0x02011788     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x8888888888888888,        1            , any;         # Fixed data burst 7
+}
+
+scom 0x02011789     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0x9999999999999999,        1            , any;         # Fixed data burst 0-7 ECC bits
+}
+
+scom 0x0201178A     {
+    bits    ,   scom_data         , MBA1.ATTR_FUNCTIONAL, expr;
+    0:63    ,   0xAAAAAAAAAAAAAAAA,        1            , any;         # Fixed data burst 0-7 SPARE bits
 }
 
 
diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile
index cab13d0af..821bdfcb9 100644
--- a/src/usr/hwpf/hwp/mc_config/makefile
+++ b/src/usr/hwpf/hwp/mc_config/makefile
@@ -48,7 +48,10 @@ OBJS =  mc_config.o			\
         opt_memmap.o                    \
         mss_eff_config_thermal.o        \
         mss_eff_config_termination.o    \
-        mss_eff_config_rank_group.o
+        mss_eff_config_rank_group.o     \
+        mss_eff_config_cke_map.o        \
+        mss_bulk_pwr_throttles.o        \
+        mss_throttle_to_power.o
 	
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
new file mode 100644
index 000000000..c7407f789
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
@@ -0,0 +1,343 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_bulk_pwr_throttles.C,v 1.10 2012/11/13 16:45:28 bellows Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_bulk_pwr_throttles
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
+// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// applicable CQ component memory_screen
+//
+// DESCRIPTION:
+// The purpose of this procedure is to set the throttle attributes based on a power limit for the dimms on the channel pair
+// At the end, output attributes will be updated with throttle values that will have dimms at or below the limit
+// NOTE:  ISDIMMs and CDIMMs are handled differently
+//   ISDIMMs use a power per DIMM for the thermal power limit from the MRW
+//   CDIMM will use power per CDIMM (power for all virtual dimms) for the thermal power limit from the MRW
+// Plan is to have ISDIMM use the per-slot throttles (thermal throttles) or per-mba throttles (power throttles), and CDIMM to use the per-chip throttles
+// Note that throttle_n_per_mba takes on different meanings depending on how cfg_nm_per_slot_enabled is set
+//   Can be slot0/slot1 OR slot0/MBA throttling
+// Note that  throttle_n_per_chip takes on different meaning depending on how cfg_count_other_mba_dis is set
+//  Can be per-chip OR per-mba throttling
+// ISDIMM:  These registers need to be setup to these values, will be able to do per slot or per MBA throttling
+//   cfg_nm_per_slot_enabled = 1
+//   cfg_count_other_mba_dis = 1
+// CDIMM:  These registers need to be setup to these values, will be able to do per slot or per chip throttling
+//   cfg_nm_per_slot_enabled = 1
+//   cfg_count_other_mba_dis = 0
+//
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.10   | pardeik  |08-NOV-12| attribute name update for runtime per chip throttles
+//   1.9   | pardeik  |25-OCT-12| updated FAPI_ERR sections, use per_chip variables (in if statements) in the throttle update section when channel pair power is greater than the limit, added CQ component comment line
+//   1.8   | pardeik  |19-OCT-12| Changed throttle_n_per_chip to be based on num_mba_with_dimms
+//         | pardeik  |19-OCT-12| Updated default throttle values to represent cmd bus utilization instead of dram bus utilization
+//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram utilization
+//   1.7   | pardeik  |10-OCT-12| Changed throttle attributes and call new function (mss_throttle_to_power) to calculate the power
+//   1.6   | pardeik  |10-APR-12| power calculation fixes and updates
+//   1.5   | pardeik  |04-APR-12| moved cdimm power calculation to end of section instead of having it in multiple places
+//   1.4   | pardeik  |04-APR-12| do channel throttle denominator check as zero only if there are ranks present
+//         | pardeik  |04-APR-12| use else if instead of if after checking throttle denominator to zero
+//   1.3   | pardeik  |03-APR-12| added cdimm power calculation for half of cdimm, changed i_target from mbs to mba
+//   1.2   | pardeik  |03-APR-12| call mss_eff_config_thermal directly
+//   1.1   | pardeik  |28-MAR-12| Updated to use Attributes
+//         | pardeik  |11-NOV-11| First Draft.
+
+
+//------------------------------------------------------------------------------
+//  My Includes
+//------------------------------------------------------------------------------
+#include <mss_bulk_pwr_throttles.H>
+#include <mss_throttle_to_power.H>
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+
+
+extern "C" {
+
+    using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+// Funtions in this file
+//------------------------------------------------------------------------------
+    fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba);
+
+
+//------------------------------------------------------------------------------
+// @brief mss_bulk_pwr_throttles(): This function determines the throttle values from a MBA channel pair power limit
+//
+// @param    const fapi::Target & i_target_mba:  MBA Target passed in
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba)
+    {
+	fapi::ReturnCode rc;
+
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_bulk_pwr_throttles");
+	FAPI_INF("*** Running %s ***", procedure_name);
+
+	enum
+	{
+	    CDIMM  = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM,
+	    RDIMM  = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM,
+	    UDIMM  = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM,
+	    LRDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM,
+	};
+
+// other variables used in this procedure
+	const uint8_t MAX_NUM_PORTS = 2;			// number of ports per MBA
+	const uint8_t MAX_NUM_DIMMS = 2;			// number of dimms per MBA port
+	const float MIN_UTIL = 1;				// Minimum percent data bus utilization (percent of max) allowed (for floor)
+// If this is changed, also change mss_throttle_to_power MAX_UTIL
+	const float MAX_UTIL = 75;				// Maximum theoretical data bus utilization (percent of max) (for ceiling)
+	const uint32_t MEM_THROTTLE_D_DEFAULT = 512;		// default throttle denominator (unthrottled) for cfg_nm_m
+	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_MBA = (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);		// default throttle numerator (unthrottled) for cfg_nm_n_per_mba
+	const uint32_t MEM_THROTTLE_N_DEFAULT_PER_CHIP = (int)(MEM_THROTTLE_D_DEFAULT * (MAX_UTIL / 100) / 4);	// default throttle numerator (unthrottled) for cfg_nm_n_per_chip
+	fapi::Target target_chip;
+	std::vector<fapi::Target> target_mba_array;
+	std::vector<fapi::Target> target_dimm_array;
+	uint32_t channel_pair_watt_target;
+	uint32_t throttle_n_per_mba;
+	uint32_t throttle_n_per_chip;
+	uint32_t throttle_d;
+	uint8_t port;
+	uint8_t dimm;
+	bool not_enough_available_power;
+	bool channel_pair_throttle_done;
+	float channel_pair_power;
+	uint8_t dimm_type;
+	uint8_t num_mba_with_dimms;
+	uint32_t power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	bool thermal_throttle_active;
+	uint8_t mba_index;
+
+// Get input attributes
+	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_WATT_TARGET, &i_target_mba, channel_pair_watt_target);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT, &i_target_mba, power_int_array);
+	if(rc) return rc;
+// runtime throttles will be the thermal throttle values (or zero if not initialized yet)
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
+	if(rc) return rc;
+
+// get number of mba's with dimms for a CDIMM
+	if (dimm_type == CDIMM)
+	{
+// Get Centaur target for the given MBA
+	    rc = fapiGetParentChip(i_target_mba, target_chip);
+	    if(rc) return rc;
+// Get MBA targets from the parent chip centaur
+	    rc = fapiGetChildChiplets(target_chip, fapi::TARGET_TYPE_MBA_CHIPLET, target_mba_array, fapi::TARGET_STATE_PRESENT);
+	    if(rc) return rc;
+	    num_mba_with_dimms = 0;
+	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
+	    {
+		rc = fapiGetAssociatedDimms(target_mba_array[mba_index], target_dimm_array, fapi::TARGET_STATE_PRESENT);
+		if(rc) return rc;
+		if (target_dimm_array.size() > 0)
+		{
+		    num_mba_with_dimms++;
+		}
+	    }
+
+	}
+	else
+	{
+	    // ISDIMMs, set to a value of one since they are handled on a per MBA basis
+	    num_mba_with_dimms = 1;
+	}
+
+///////////////////////////////
+// THROTTLE SECTION
+///////////////////////////////
+
+// Determine if the channel pair power for this MBA is over the limit when the runtime memory throttle settings are used
+// If not over the limit, then use the runtime throttle settings (defined in mss_eff_config_thermal)
+// If over limit, then increase throttle value until it is at or below limit
+// If unable to get power below limit, then call out an error
+
+// Determine whether to base throttles on thermal or power reasons (power throttles can give you better performance than thermal throttles)
+	if ((throttle_n_per_mba == 0) && (throttle_n_per_chip == 0) && (throttle_d == 0))
+	{
+    // runtime throttles are all zero here, they have not been defined yet and need to be
+	    thermal_throttle_active = true;
+    // Set runtime throttles to default values as a starting value
+	    throttle_n_per_mba = MEM_THROTTLE_N_DEFAULT_PER_MBA;
+	    throttle_n_per_chip = MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms;
+	    throttle_d = MEM_THROTTLE_D_DEFAULT;
+	}
+	else if ((throttle_n_per_mba != MEM_THROTTLE_N_DEFAULT_PER_MBA) || (throttle_n_per_chip != (MEM_THROTTLE_N_DEFAULT_PER_CHIP * num_mba_with_dimms)) || (throttle_d != MEM_THROTTLE_D_DEFAULT))
+	{
+    // if runtime throttles are not equal to the default values, then thermal throttles are in place
+	    thermal_throttle_active = true;
+	}
+	else
+	{
+    // runtime throttles are not all zero and equal to the defaults, so no thermal throttles are in place - so now any throttles will be power based
+	    thermal_throttle_active = false;
+	}
+
+// Adjust power limit value as needed here
+// For CDIMM, we want the throttles to be per-chip, and to allow all commands to go to one MBA to get to the power limit
+	if (dimm_type == CDIMM)
+	{
+// Set channel pair power limit to whole CDIMM power limit (multiply by number of MBAs used) and subtract off idle power for dimms on other MBA
+	    channel_pair_watt_target = channel_pair_watt_target * num_mba_with_dimms;
+	    for (port=0; port < MAX_NUM_PORTS; port++)
+	    {
+		for (dimm=0; dimm < MAX_NUM_DIMMS; dimm++)
+		{
+		    channel_pair_watt_target = channel_pair_watt_target - ((num_mba_with_dimms - 1) * (power_int_array[port][dimm]));
+		}
+	    }
+	}
+
+// calculate power and change throttle values in this while loop until limit has been satisfied or throttles have reached the minimum limit
+	not_enough_available_power = false;
+	channel_pair_throttle_done = false;
+	while (channel_pair_throttle_done == false)
+	{
+	    rc = mss_throttle_to_power_calc(
+					    i_target_mba,
+					    throttle_n_per_mba,
+					    throttle_n_per_chip,
+					    throttle_d,
+					    channel_pair_power
+					    );
+	    if(rc)
+	    {
+		FAPI_ERR("Error (0x%x) calling mss_throttle_to_power_calc", static_cast<uint32_t>(rc));
+		return rc;
+	    }
+
+// compare channel pair power to mss_watt_target for channel and decrease throttles if it is above this limit
+// throttle decrease will decrement throttle numerator by one (or increase throttle denominator) and recalculate power until utilization (N/M) reaches a lower limit
+
+	    if (channel_pair_power > channel_pair_watt_target)
+	    {
+// check to see if dimm utilization is greater than the min utilization limit, continue if it is, error if it is not
+		if ((((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type != CDIMM) && (thermal_throttle_active == false)) || (((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type != CDIMM) && (thermal_throttle_active == true)) || (((((float)throttle_n_per_chip * 100 * 4) / throttle_d) > MIN_UTIL) && (dimm_type == CDIMM)))
+		{
+		    if (((throttle_n_per_chip > 1) && (dimm_type != CDIMM) && (thermal_throttle_active == false)) || ((throttle_n_per_chip > 1) && (dimm_type != CDIMM) && (thermal_throttle_active == true)) || ((throttle_n_per_chip > 1) && (dimm_type == CDIMM)))
+		    {
+			if (dimm_type == CDIMM)
+			{
+			    // CDIMMs, use per chip throttling for any thermal or available power limits
+			    throttle_n_per_chip--;
+			}
+			else
+			{
+			    // ISDIMMs, use per slot throttling for thermal power limits
+			    if (thermal_throttle_active == true)
+			    {
+// per_mba throttling (ie.  per dimm for ISDIMMs) will limit performance if all traffic is sent to one dimm, so use the per_chip
+// This works as long as the other dimm is providing termination (for 2 dimms per channel)
+//    If the other dimm is not providing termination, then we would want to redefine the power curve in mss_eff_config_thermal and use the per_mba throttle here
+// It there is only one dimm on channel, then it will provide its own termination and the per_mba and per_chip will effectively do the same throttling (ie.  doesn't matter which one we do in this case)
+// Warning:  If this changes, then the two if statements above need to be modified
+//				throttle_n_per_mba--;
+				throttle_n_per_chip--;
+			    }
+			    else
+			    {
+				// ISDIMMs, use per mba throttling for available power limit
+// Warning:  If this changes, then the two if statements above need to be modified
+				throttle_n_per_chip--;
+			    }
+			}
+		    }
+// increment throttle denominator if numerator is at one (its lowest setting)
+		    else
+		    {
+			throttle_d++;
+		    }
+		    FAPI_DBG("Throttle update [N_per_mba/N_per_chip/M %d/%d/%d]", throttle_n_per_mba, throttle_n_per_chip, throttle_d);
+		}
+// minimum utilization limit was reached for this throttle N/M value
+		else
+		{
+// Throttles can't be changed anymore (already at or below MIN_UTIL)
+		    channel_pair_throttle_done = true;
+		    not_enough_available_power = true;
+		}
+	    }
+// channel pair power is less than limit, so keep existing throttles
+	    else
+	    {
+		FAPI_DBG("There is enough available memory power [Channel Pair Power %4.2f/%d cW]", channel_pair_power, channel_pair_watt_target);
+		channel_pair_throttle_done = true;
+	    }
+	}
+
+	FAPI_DBG("Final Throttle Settings [N_per_mba/N_per_chip/M %d/%d/%d]", throttle_n_per_mba, throttle_n_per_chip, throttle_d);
+
+
+// update output attributes
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
+	if(rc) return rc;
+
+	if (not_enough_available_power == true)
+	{
+	    FAPI_ERR("Not enough available memory power [Channel Pair Power %4.2f/%d cW]", channel_pair_power, channel_pair_watt_target);
+	    FAPI_SET_HWP_ERROR(rc, RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER);
+	    if (rc) fapiLogError(rc);
+	}
+	FAPI_INF("*** %s COMPLETE ***", procedure_name);
+	return rc;
+
+    }
+
+
+} //end extern C
+
+
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
new file mode 100644
index 000000000..2b86242c8
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
@@ -0,0 +1,75 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_bulk_pwr_throttles.H,v 1.3 2012/10/15 13:05:17 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_bulk_pwr_throttles.H
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
+// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// Header file for mss_bulk_pwr_throttles.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
+//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs
+//   1.1   | pardeik  |11-NOV-11| First Draft.
+
+
+
+#ifndef MSS_BULK_PWR_THROTTLES_H_
+#define MSS_BULK_PWR_THROTTLES_H_
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*mss_bulk_pwr_throttles_FP_t)(const fapi::Target & i_target_mba);
+
+extern "C"
+{
+/**
+ * @brief mss_bulk_pwr_throttles procedure. Set dimm and channel throttle attributes based on available centaur mba port power
+ *
+ * @param[in]  i_target_mba  Reference to centaur mba target
+ *
+ * @return ReturnCode
+ */
+
+    fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba);
+
+} // extern "C"
+
+#endif // MSS_BULK_PWR_THROTTLES_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
index d95469964..51abb1a37 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config.C,v 1.11 2012/09/25 17:58:32 mjjones Exp $
+// $Id: mss_eff_config.C,v 1.15 2012/11/16 14:44:04 asaetow Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 //          centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $
 //------------------------------------------------------------------------------
@@ -44,8 +44,38 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.12  |          |         |
-//   1.11  | kjpower  |27-AUG-12| Restructured code, added modularity
+//   1.16  |          |         |
+//   1.15  | asaetow  |15-NOV-12| Added call to mss_eff_config_cke_map().
+//         |          |         | NOTE: DO NOT pick-up without
+//         |          |         | mss_eff_config_cke_map.C v1.3 or newer.
+//         |          |         | Added ATTR_MSS_ALLOW_SINGLE_PORT check. 
+//         |          |         | Added ATTR_EFF_DIMM_SPARE.
+//         |          |         | Fixed NUM_RANKS_PER_DIMM for single drop. 
+//         |          |         | Fixed calc_timing_in_clk() for negative. 
+//         |          |         | Fixed IBM_TYPE and STACK_TYPE. 
+//   1.14  | asaetow  |08-NOV-12| Changed to match new memory_attributes.xml
+//         |          |         | v1.45 or newer.
+//         |          |         | NOTE: DO NOT pick-up without
+//         |          |         | memory_attributes.xml v1.45 or newer.
+//   1.13  | asaetow  |11-OCT-12| Added ATTR_EFF_SCHMOO_ADDR_MODE, 
+//         |          |         | ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN,
+//         |          |         | ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN,
+//         |          |         | ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN,
+//         |          |         | ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN,
+//         |          |         | ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN,
+//         |          |         | ATTR_EFF_DRAM_WR_VREF_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_RD_VREF_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_DRV_IMP_CMD_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO,
+//         |          |         | ATTR_EFF_CEN_SLEW_RATE_CMD_SCHMOO,
+//         |          |         | and ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO.
+//   1.12  | asaetow  |26-SEP-12| Added initial equation for
+//         |          |         | ATTR_EFF_ZQCAL_INTERVAL and
+//         |          |         | ATTR_EFF_MEMCAL_INTERVAL from Ken.
+//   1.11  | kjpower  |26-SEP-12| Restructured code, added modularity
 //   1.10  | bellows  |02-AUG-12| Added in DIMM functional vector for Daniel
 //   1.9   | asaetow  |29-MAY-12| Added divide by 0 check for mss_freq.
 //         |          |         | Added 9 new attributes from
@@ -93,6 +123,7 @@
 //------------------------------------------------------------------------------
 #include <mss_eff_config.H>
 #include <mss_eff_config_rank_group.H>
+#include <mss_eff_config_cke_map.H>
 #include <mss_eff_config_termination.H>
 #include <mss_eff_config_thermal.H>
 
@@ -109,6 +140,7 @@ const uint32_t MSS_EFF_VALID = 255;
 const uint32_t TWO_MHZ = 2000000;
 const uint8_t PORT_SIZE = 2;
 const uint8_t DIMM_SIZE = 2;
+const uint8_t RANK_SIZE = 4;
 
 //------------------------------------------------------------------------------
 // Structure
@@ -120,6 +152,7 @@ struct mss_eff_config_data
 {
     uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE];
     uint8_t dimm_functional;
+    uint8_t allow_single_port;
     uint8_t cur_dram_density;
     uint32_t mss_freq;
     uint32_t mtb_in_ps_u32array[PORT_SIZE][DIMM_SIZE];
@@ -211,6 +244,7 @@ struct mss_eff_config_atts
     // AST HERE: Needs SPD byte68:76
     uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
     uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE];
+    uint8_t eff_dimm_spare[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
     uint8_t eff_dimm_type;
     uint8_t eff_dram_al; // initialized to 1
     uint8_t eff_dram_asr;
@@ -248,8 +282,6 @@ struct mss_eff_config_atts
     uint8_t eff_dram_width;
     uint8_t eff_dram_wr;
     uint8_t eff_dram_wr_lvl_enable;
-    // AST HERE: Needs SPD byte33[7,1:0], currently hard coded to TYPE_1B
-    // initialized to {{2,2},{2,2}}
     uint8_t eff_ibm_type[PORT_SIZE][DIMM_SIZE];
     uint32_t eff_memcal_interval;
     uint8_t eff_mpr_loc;
@@ -262,10 +294,28 @@ struct mss_eff_config_atts
     uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE];
     uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE];
     uint8_t eff_schmoo_mode;
+
+    uint8_t eff_schmoo_addr_mode;
+    uint8_t eff_schmoo_wr_eye_min_margin;
+    uint8_t eff_schmoo_rd_eye_min_margin;
+    uint8_t eff_schmoo_dqs_clk_min_margin;
+    uint8_t eff_schmoo_rd_gate_min_margin;
+    uint8_t eff_schmoo_addr_cmd_min_margin;
+    uint32_t eff_cen_rd_vref_schmoo[PORT_SIZE];
+    uint32_t eff_dram_wr_vref_schmoo[PORT_SIZE];
+    uint32_t eff_cen_rcv_imp_dq_dqs_schmoo[PORT_SIZE];
+    uint32_t eff_cen_drv_imp_dq_dqs_schmoo[PORT_SIZE];
+    uint8_t eff_cen_drv_imp_cntl_schmoo[PORT_SIZE];
+    uint8_t eff_cen_drv_imp_clk_schmoo[PORT_SIZE];
+    uint8_t eff_cen_drv_imp_spcke_schmoo[PORT_SIZE];
+    uint8_t eff_cen_slew_rate_dq_dqs_schmoo[PORT_SIZE];
+    uint8_t eff_cen_slew_rate_cntl_schmoo[PORT_SIZE];
+    uint8_t eff_cen_slew_rate_addr_schmoo[PORT_SIZE];
+    uint8_t eff_cen_slew_rate_clk_schmoo[PORT_SIZE];
+    uint8_t eff_cen_slew_rate_spcke_schmoo[PORT_SIZE];
+
     uint8_t eff_schmoo_param_valid;
     uint8_t eff_schmoo_test_valid;
-    // AST HERE: Needs SPD byte33[7,1:0], currently hard coded to 1
-    // initialized to {{1,1},{1,1}}
     uint8_t eff_stack_type[PORT_SIZE][DIMM_SIZE];
     uint32_t eff_zqcal_interval;
     uint8_t dimm_functional_vector;
@@ -330,7 +380,12 @@ uint32_t calc_timing_in_clk(uint32_t i_mtb_in_ps, uint32_t i_ftb_in_fs,
     uint32_t l_tCK_in_ps;
     // perform calculations
     l_tCK_in_ps = TWO_MHZ/i_mss_freq;
-    l_timing = (i_unit * i_mtb_in_ps) + (i_offset * i_ftb_in_fs);
+    if ( i_offset >= 128 ) {
+       i_offset = 256 - i_offset;
+       l_timing = (i_unit * i_mtb_in_ps) - (i_offset * i_ftb_in_fs);
+    } else {
+       l_timing = (i_unit * i_mtb_in_ps) + (i_offset * i_ftb_in_fs);
+    }
     // ceiling()
     l_timing_in_clk = l_timing / l_tCK_in_ps;
     // check l_timing
@@ -339,9 +394,7 @@ uint32_t calc_timing_in_clk(uint32_t i_mtb_in_ps, uint32_t i_ftb_in_fs,
         l_timing_in_clk += 1;
     }
     // DEBUG HERE:
-    //FAPI_INF("calc_timing_in_clk: l_timing_in_clk = %d, l_tCK_in_ps = %d,
-    // i_mtb_in_ps = %d, i_ftb_in_fs = %d, i_unit = %d, i_offset = %d",
-    //l_timing_in_clk, l_tCK_in_ps, i_mtb_in_ps, i_ftb_in_fs, i_unit, i_offset);
+    //FAPI_INF("calc_timing_in_clk: l_timing_in_clk = %d, l_tCK_in_ps = %d, i_mtb_in_ps = %d, i_ftb_in_fs = %d, i_unit = %d, i_offset = %d", l_timing_in_clk, l_tCK_in_ps, i_mtb_in_ps, i_ftb_in_fs, i_unit, i_offset);
 
     return l_timing_in_clk;
 } // end calc_timing_in_clk()
@@ -651,7 +704,7 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules(
         FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
         return rc;
     }
-    if (
+    if ( (
             ((p_i_mss_eff_config_data->
               cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_VALID)
              && (p_i_mss_eff_config_data->
@@ -661,7 +714,20 @@ fapi::ReturnCode mss_eff_config_verify_plug_rules(
               cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID)
              && (p_i_mss_eff_config_data->
                  cur_dimm_spd_valid_u8array[1][1] == MSS_EFF_EMPTY))
-       )
+       ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) )
+    {
+        FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString());
+        FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+        return rc;
+    }
+    if ( (
+            (p_i_mss_eff_config_data->
+              cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID)
+             || (p_i_mss_eff_config_data->
+                 cur_dimm_spd_valid_u8array[1][0] == MSS_EFF_VALID)
+             || (p_i_mss_eff_config_data->
+                 cur_dimm_spd_valid_u8array[1][1] == MSS_EFF_VALID)
+       ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_TRUE) )
     {
         FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString());
         FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
@@ -979,13 +1045,19 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
         for(int j = 0; j < DIMM_SIZE; j++)
         {
             // i <-> PORT_SIZE, j <-> DIMM_SIZE
-            // initializes to {{1,1},{1,1}} and {{2,2},{2,2}} respectively
-            p_o_atts->eff_stack_type[i][j] = 1;
-            p_o_atts->eff_ibm_type[i][j] = 2;
+            p_o_atts->eff_stack_type[i][j] = 0;
+            p_o_atts->eff_ibm_type[i][j] = 0;
         }
     }
 
     // Assigning values to attributes
+//------------------------------------------------------------------------------
+    p_o_atts->eff_schmoo_wr_eye_min_margin = 70;
+    p_o_atts->eff_schmoo_rd_eye_min_margin = 70;
+    p_o_atts->eff_schmoo_dqs_clk_min_margin = 140;
+    p_o_atts->eff_schmoo_rd_gate_min_margin = 100;
+    p_o_atts->eff_schmoo_addr_cmd_min_margin = 140;
+//------------------------------------------------------------------------------
     switch(p_i_data->dram_device_type[0][0])
     {
         case fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3:
@@ -1009,7 +1081,20 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
             p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM;
             break;
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_UDIMM:
-            p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM;
+            // TODO RTC Task 60572
+            // DIMM SPD Module Type in byte 3 can be 0x82.
+            // 0x80 is CDIMM, 0x02 is unbuffered
+            // Problem 1: Firmware SPD DD only returns the lower 4 bits because
+            //   the top 4 bits are reserved in the spec. There needs to be a
+            //   new SPD attribute for the top bit that can be queried by this
+            //   HWP. HW team to provide updated dimm_spd_attributes.xml. FW
+            //   team to support the new attribute.
+            // Problem 2: This HWP and mss_eff_config_termination fail if
+            //   eff_dimm_type is not CDIMM or RDIMM. Depending on the fix for
+            //   Problem 1, the HWPs need fixing to recognize Unbuffered-CDIMM
+            // The workaround is to treat UDIMM(0x02) as a CDIMM
+            //OLD: p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM;
+            p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
             break;
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM:
             p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM;
@@ -1123,7 +1208,11 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
 //------------------------------------------------------------------------------
     p_o_atts->eff_dram_density = 16;
 
-    for (int l_cur_mba_port = 0; l_cur_mba_port < PORT_SIZE; l_cur_mba_port += 1)
+    uint8_t allow_port_size = 1;
+    if (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) {
+       allow_port_size = PORT_SIZE;
+    }
+    for (int l_cur_mba_port = 0; l_cur_mba_port < allow_port_size; l_cur_mba_port += 1)
     {
         for (int l_cur_mba_dimm = 0; l_cur_mba_dimm <
                 p_o_atts->eff_num_drops_per_port; l_cur_mba_dimm += 1)
@@ -1155,10 +1244,13 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
             }
             else
             {
-               FAPI_ERR("Unsupported DRAM density on %s!",
-                       i_target_mba.toEcmdString());
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-               return rc;
+               p_i_mss_eff_config_data->cur_dram_density = 1;
+               if (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) {
+                  FAPI_ERR("Unsupported DRAM density on %s!",
+                          i_target_mba.toEcmdString());
+                  FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
+                  return rc;
+               }
             }
 //------------------------------------------------------------------------------
             if (p_o_atts->eff_dram_density >
@@ -1415,6 +1507,17 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
         return rc;
     }
 //------------------------------------------------------------------------------
+    // Calculate ZQCAL Interval based on the following equation from Ken:
+    //            0.5
+    //  ------------------------------ = 13.333ms 
+    //  (1.5 * 10) + (0.15 * 150)
+    p_o_atts->eff_zqcal_interval = ( 13333 *
+            p_i_mss_eff_config_data->mss_freq) / 2;
+//------------------------------------------------------------------------------
+    // Calculate MEMCAL Interval based on 1sec interval across all bits per DP18
+    p_o_atts->eff_memcal_interval = (62500 *
+            p_i_mss_eff_config_data->mss_freq) / 2;
+//------------------------------------------------------------------------------
     // Calculate tRFI
     p_o_atts->eff_dram_trfi = (3900 *
             p_i_mss_eff_config_data->mss_freq) / 2000;
@@ -1426,6 +1529,9 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
         for (int l_cur_mba_dimm = 0; l_cur_mba_dimm <
                 DIMM_SIZE; l_cur_mba_dimm += 1)
         {
+          if (p_i_mss_eff_config_data->
+              cur_dimm_spd_valid_u8array[l_cur_mba_port][l_cur_mba_dimm] == MSS_EFF_VALID)
+          {
             if (p_i_data->num_ranks[l_cur_mba_port]
                     [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R4)
             {
@@ -1456,6 +1562,74 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
                 p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
                     [l_cur_mba_dimm] = 0x00;
             }
+            for (int l_cur_mba_rank = 0; l_cur_mba_rank <
+               RANK_SIZE; l_cur_mba_rank += 1)
+            {
+               if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)
+                    && ( l_cur_mba_rank < p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] ))
+               {
+                 p_o_atts->
+                  eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
+                    = fapi::ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE;
+               } else {
+                 p_o_atts->
+                  eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank] 
+                    = fapi::ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE;
+               }  
+            }
+            // AST HERE: Needs SPD byte33[7,1:0], for expanded IBM_TYPE and STACK_TYPE
+            if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
+               if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A;
+               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2) {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B;
+               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4) {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D;
+               } else {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
+                  FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+                  FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+               }
+            } else if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A;
+               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2) {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B;
+               } else {
+                  p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
+                  FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+                  FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+               }
+            } else {
+               p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+               p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
+               FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+          } else {
+             p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
+                 [l_cur_mba_dimm] = 0;
+             p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
+                 [l_cur_mba_dimm] = 0x00;
+            for (int l_cur_mba_rank = 0; l_cur_mba_rank <
+               RANK_SIZE; l_cur_mba_rank += 1)
+            {
+               p_o_atts->
+                eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
+                  = fapi::ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE;
+            }
+            p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
+            p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
+          }
+//------------------------------------------------------------------------------
+          
 //------------------------------------------------------------------------------
             if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
                     [l_cur_mba_dimm] != 0)
@@ -1552,7 +1726,11 @@ fapi::ReturnCode mss_eff_config_write_eff_atts(
                 p_i_atts->eff_dimm_rcd_cntl_word_0_15);
         if(rc) break;
         rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SIZE, &i_target_mba,
-                p_i_atts->eff_dimm_size); if(rc) break;
+                p_i_atts->eff_dimm_size);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SPARE, &i_target_mba,
+                p_i_atts->eff_dimm_spare);
+        if(rc) break;
         rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba,
                 p_i_atts->eff_dimm_type);
         if(rc) break;
@@ -1683,12 +1861,70 @@ fapi::ReturnCode mss_eff_config_write_eff_atts(
         rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba,
                 p_i_atts->eff_schmoo_mode);
         if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba,
+                p_i_atts->eff_schmoo_addr_mode);
+        if(rc) break;
         rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba,
                 p_i_atts->eff_schmoo_param_valid);
         if(rc) break;
         rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba,
                 p_i_atts->eff_schmoo_test_valid);
         if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN, &i_target_mba,
+                p_i_atts->eff_schmoo_wr_eye_min_margin);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN, &i_target_mba,
+                p_i_atts->eff_schmoo_rd_eye_min_margin);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN, &i_target_mba,
+                p_i_atts->eff_schmoo_dqs_clk_min_margin);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN, &i_target_mba,
+                p_i_atts->eff_schmoo_rd_gate_min_margin);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN, &i_target_mba,
+                p_i_atts->eff_schmoo_addr_cmd_min_margin);
+        if(rc) break;
+
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_rd_vref_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba,
+                p_i_atts->eff_dram_wr_vref_schmoo);
+        if(rc) break;
+
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_rcv_imp_dq_dqs_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_drv_imp_dq_dqs_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_drv_imp_cntl_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_drv_imp_clk_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_drv_imp_spcke_schmoo);
+        if(rc) break;
+
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_slew_rate_dq_dqs_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_slew_rate_cntl_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_slew_rate_addr_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_slew_rate_clk_schmoo);
+        if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba,
+                p_i_atts->eff_cen_slew_rate_spcke_schmoo);
+        if(rc) break;
+
         rc = FAPI_ATTR_SET(ATTR_EFF_STACK_TYPE, &i_target_mba,
                 p_i_atts->eff_stack_type);
         if(rc) break;
@@ -1737,6 +1973,13 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba)
     do
     {
 //------------------------------------------------------------------------------
+        // Grab allow single port data
+        rc = FAPI_ATTR_GET(ATTR_MSS_ALLOW_SINGLE_PORT, &i_target_mba, p_l_mss_eff_config_data->allow_single_port);
+        if(rc) break;
+        if ( p_l_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_TRUE ) {
+           FAPI_INF("WARNING: allow_single_port = %d on %s.", p_l_mss_eff_config_data->allow_single_port, i_target_mba.toEcmdString());
+        }
+//------------------------------------------------------------------------------
         // Grab freq/volt data
         rc = fapiGetParentChip(i_target_mba, l_target_centaur);
         if(rc) break;
@@ -1783,8 +2026,9 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba)
         }
 
         // verify SPD data
-        if( p_l_atts->eff_num_drops_per_port
+        if(( p_l_atts->eff_num_drops_per_port
                 != fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_EMPTY )
+          && ( p_l_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE ))
         {
             rc = mss_eff_config_verify_spd_data( i_target_mba,
                     p_l_atts, p_l_spd_data );
@@ -1818,6 +2062,7 @@ fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba)
 
         // Calls to sub-procedures
         rc = mss_eff_config_rank_group(i_target_mba); if(rc) break;
+        rc = mss_eff_config_cke_map(i_target_mba); if(rc) break;
         rc = mss_eff_config_termination(i_target_mba); if(rc) break;
         rc = mss_eff_config_thermal(i_target_mba); if(rc) break;
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
new file mode 100644
index 000000000..6d250915a
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
@@ -0,0 +1,335 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_eff_config_cke_map.C,v 1.3 2012/11/16 14:39:15 asaetow Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_eff_config_cke_map
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
+// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// This procedure takes in attributes and determines proper cke map.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.4   |          |         |
+//   1.3   | asaetow  |14-NOV-12| Added ATTR_EFF_SPCKE_MAP. 
+//   1.2   | asaetow  |13-NOV-12| Added FAPI_ERR for else "Undefined IBM_TYPE". 
+//         |          |         | Removed outter NUM_DROPS_PER_PORT check.
+//   1.1   | asaetow  |07-NOV-12| First Draft.
+
+
+
+//----------------------------------------------------------------------
+//  My Includes
+//----------------------------------------------------------------------
+
+
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+
+
+extern "C" {
+
+
+
+//----------------------------------------------------------------------
+// ENUMs and CONSTs
+//----------------------------------------------------------------------
+
+// Define attribute array size
+const uint8_t PORT_SIZE = 2;
+const uint8_t DIMM_SIZE = 2;
+const uint8_t RANK_SIZE = 4;
+const uint8_t IBM_TYPE_SIZE = 27;
+
+const uint8_t l_cke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = {
+   // UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26
+   //        DIMM0          ,          DIMM1
+   //   0     1     2     3 ,     0     1     2     3
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // UNDEFINED 
+   {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}},  // TYPE_1A
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_1B
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_1C <-- UNDEFINED
+   {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}},  // TYPE_1D
+   {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}},  // TYPE_2A
+   {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}},  // TYPE_2B
+   {{0x80, 0x00, 0x00, 0x00}, {0x08, 0x00, 0x00, 0x00}},  // TYPE_2C
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_3A
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_3B
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_3C
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4C <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5A <-- UNDEFINED
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_5B
+   {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}},  // TYPE_5C
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5D <-- NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6C <-- UNDEFINED
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_7A
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_7B <-- NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_7C
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_8A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_8B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}}; // TYPE_8C <-- UNDEFINED
+
+const uint8_t l_spcke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = {
+   //        DIMM0          ,          DIMM1
+   //   0     1     2     3 ,     0     1     2     3
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // UNDEFINED 
+   {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}},  // TYPE_1A
+   {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}},  // TYPE_1B
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_1C <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_1D <-- NOT SUPPORTED for CDIMM
+   {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}},  // TYPE_2A
+   {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}},  // TYPE_2B
+   {{0x20, 0x00, 0x00, 0x00}, {0x02, 0x00, 0x00, 0x00}},  // TYPE_2C
+   {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}},  // TYPE_3A
+   {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}},  // TYPE_3B
+   {{0x20, 0x10, 0x00, 0x00}, {0x02, 0x01, 0x00, 0x00}},  // TYPE_3C
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_4C <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5B <-- NOT SUPPORTED for CDIMM
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5C <-- NOT SUPPORTED for CDIMM
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5D <-- NOT SUPPORTED for CDIMM, NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6C <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_7A <-- NOT SUPPORTED for CDIMM
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_7B <-- NOT SUPPORTED for CDIMM, NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_7C <-- NOT SUPPORTED for CDIMM
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_8A <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_8B <-- UNDEFINED
+   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}}}; // TYPE_8C <-- UNDEFINED
+
+
+
+//******************************************************************************
+//* name=mss_eff_config_cke_map, param=i_target_mba, return=ReturnCode
+//******************************************************************************
+fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba) {
+   fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+   const char * const PROCEDURE_NAME = "mss_eff_config_cke_map";
+   FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
+
+
+   // Define attribute array size
+
+
+   // Fetch dependent attributes
+   uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
+   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, 
+   uint8_t l_dram_gen_u8;
+   // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
+   uint8_t l_dimm_type_u8;
+   uint8_t l_num_drops_per_port_u8;
+   uint8_t l_ibm_type_u8array[PORT_SIZE][DIMM_SIZE];
+   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_IBM_TYPE, &i_target_mba, l_ibm_type_u8array); if(rc) return rc;
+
+
+   // Define local attribute variables
+   uint8_t l_attr_eff_cke_map[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+   uint8_t l_attr_eff_spcke_map[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+
+
+   for (uint8_t l_cur_port = 0; l_cur_port < PORT_SIZE; l_cur_port += 1) {
+      for (uint8_t l_cur_dimm = 0; l_cur_dimm < DIMM_SIZE; l_cur_dimm += 1) {
+         uint8_t l_ibm_type_index = 0;
+         // UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26
+         if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED ) {
+            l_ibm_type_index = 0;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A ) {
+            l_ibm_type_index = 1;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B ) {
+            l_ibm_type_index = 2;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1C ) {
+            l_ibm_type_index = 3;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D ) {
+            l_ibm_type_index = 4;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2A ) {
+            l_ibm_type_index = 5;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2B ) {
+            l_ibm_type_index = 6;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_2C ) {
+            l_ibm_type_index = 7;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3A ) {
+            l_ibm_type_index = 8;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3B ) {
+            l_ibm_type_index = 9;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_3C ) {
+            l_ibm_type_index = 10;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4A ) {
+            l_ibm_type_index = 11;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4B ) {
+            l_ibm_type_index = 12;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_4C ) {
+            l_ibm_type_index = 13;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5A ) {
+            l_ibm_type_index = 14;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5B ) {
+            l_ibm_type_index = 15;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C ) {
+            l_ibm_type_index = 16;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5D ) {
+            l_ibm_type_index = 17;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6A ) {
+            l_ibm_type_index = 18;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6B ) {
+            l_ibm_type_index = 19;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6C ) {
+            l_ibm_type_index = 20;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7A ) {
+            l_ibm_type_index = 21;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7B ) {
+            l_ibm_type_index = 22;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_7C ) {
+            l_ibm_type_index = 23;
+            if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+               FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8A ) {
+            l_ibm_type_index = 24;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8B ) {
+            l_ibm_type_index = 25;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_8C ) {
+            l_ibm_type_index = 26;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         } else {
+            l_ibm_type_index = 0;
+            FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
+            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+         }
+
+         for (uint8_t l_cur_rank = 0; l_cur_rank < RANK_SIZE; l_cur_rank += 1) {
+            if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) {
+               if ( l_cur_dimm == 0 ) {
+                  l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_cke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank];
+                  if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+                     l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_spcke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank];
+                     FAPI_INF("WARNING: NUM_DROPS_PER_PORT = SINGLE for a CDIMM on %s!", i_target_mba.toEcmdString());
+                  } else {
+                     l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+                  }
+               } else {
+                  l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+                  l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+               }
+            } else if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) {
+               l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_cke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank];
+               if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+                  l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = l_spcke_map_u8array[l_ibm_type_index][l_cur_dimm][l_cur_rank];
+               } else {
+                  l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+               }
+            } else {
+               l_attr_eff_cke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+               l_attr_eff_spcke_map[l_cur_port][l_cur_dimm][l_cur_rank] = 0;
+            }
+         }
+      }
+   }
+
+
+   // Set attributes
+   rc = FAPI_ATTR_SET(ATTR_EFF_CKE_MAP, &i_target_mba, l_attr_eff_cke_map); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_SPCKE_MAP, &i_target_mba, l_attr_eff_spcke_map); if(rc) return rc;
+
+   FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
+   return rc;
+}
+
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
new file mode 100755
index 000000000..6656efad5
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
@@ -0,0 +1,74 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_eff_config_cke_map.H,v 1.1 2012/11/14 01:28:48 asaetow Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_eff_config_cke_map.H
+// *! DESCRIPTION : Header file for mss_eff_config_cke_map.
+// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
+// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+//
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.2   |          |         |
+//   1.1   | asaetow  |13-NOV-12| First Draft.
+
+
+#ifndef MSS_EFF_CONFIG_CKE_MAP_H_
+#define MSS_EFF_CONFIG_CKE_MAP_H_
+
+//----------------------------------------------------------------------
+//  My Includes
+//----------------------------------------------------------------------
+
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+
+typedef fapi::ReturnCode (*mss_eff_config_cke_map_FP_t)(const fapi::Target i_target_mba);
+
+extern "C" {
+
+//******************************************************************************
+//* name=mss_eff_config_cke_map, param=i_target_mba, return=ReturnCode
+//******************************************************************************
+fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba);
+
+} // extern "C"
+
+#endif // MSS_EFF_CONFIG_CKE_MAP_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
index 6865f0fb0..946da5294 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_termination.C,v 1.2 2012/09/05 23:01:02 asaetow Exp $
+// $Id: mss_eff_config_termination.C,v 1.8 2012/12/06 13:45:57 bellows Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -42,7 +42,15 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.3   |          |         |
+//   1.9   |          |         |
+//   1.8   | bellows  |06-DEC-12| Added sim leg for rotator values
+//   1.7   | asaetow  |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF. 
+//   1.6   | asaetow  |17-NOV-12| Fixed ATTR_EFF_ODT_WR for 4R RDIMMs.
+//   1.5   | asaetow  |17-NOV-12| Added PR settings.
+//         |          |         | Fixed RCD settings for RDIMM.
+//   1.4   | asaetow  |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F. 
+//   1.3   | asaetow  |05-NOV-12| Added Paul's SI value for pre-machine parsable workbook.
+//         |          |         | NOTE: DO NOT pick-up without memory_attributes.xml v1.45 or newer.
 //   1.2   | asaetow  |05-SEP-12| Added ATTR_MSS_CAL_STEP_ENABLE.
 //   1.1   | asaetow  |30-APR-12| First Draft.
 
@@ -62,9 +70,113 @@
 
 
 //----------------------------------------------------------------------
-// ENUMs
+// ENUMs and CONSTs
 //----------------------------------------------------------------------
 
+// Define attribute array size
+const uint8_t PORT_SIZE = 2;
+const uint8_t PR_TYPE_SIZE = 48;
+const uint8_t TOPO_SIZE = 25;
+
+const uint8_t PR_VALUE_U8ARRAY[PORT_SIZE][PR_TYPE_SIZE][TOPO_SIZE] = {
+   {{0,95,100,63,67,66,63,63,63,90,95,69,71,73,77,69,71,69,73,76,77,81,73,78,74},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,103,109,0,0,0,0,0,0,98,104,0,0,0,0,0,0,0,69,71,72,77,69,71,68},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,6,9,2,1,2,2,2,2,11,14,12,15,12,15,12,14,10,18,21,17,21,16,20,15},
+   {0,7,9,3,2,3,2,3,3,11,14,11,13,11,13,10,13,9,17,20,16,19,14,18,14},
+   {0,7,9,2,2,2,2,2,2,10,13,12,15,12,15,12,15,10,18,22,18,21,16,20,15},
+   {0,3,3,5,4,5,4,5,4,5,6,11,14,11,14,11,14,9,17,20,17,20,15,19,14},
+   {0,0,0,0,0,0,0,0,1,4,5,8,10,8,10,8,10,7,14,17,14,16,12,15,12},
+   {0,0,0,1,1,1,1,1,1,5,6,12,15,12,15,11,14,10,18,21,17,21,16,20,15},
+   {0,3,3,4,3,4,3,4,4,6,8,13,16,13,16,13,16,11,19,23,18,22,17,21,16},
+   {0,2,2,3,2,3,2,3,3,6,8,13,17,13,17,13,17,11,19,23,19,23,17,22,16},
+   {0,4,4,6,5,6,5,6,5,9,11,16,21,16,21,16,21,14,22,27,22,27,21,26,19},
+   {0,6,8,2,2,2,2,2,2,10,13,12,15,12,15,12,15,10,18,22,18,22,16,21,15},
+   {0,11,14,8,6,8,6,8,7,8,11,9,11,9,11,9,11,7,15,18,15,17,12,16,12},
+   {0,8,10,3,3,3,3,3,3,11,14,12,15,12,15,12,15,10,18,22,18,21,16,21,15},
+   {0,8,10,4,3,4,3,4,4,10,12,11,13,11,13,10,13,9,17,20,16,19,14,18,14},
+   {0,7,10,3,3,3,3,3,3,13,16,14,18,14,18,14,17,12,20,24,19,23,18,23,17},
+   {0,7,9,3,2,3,2,3,3,11,14,12,15,12,15,12,15,10,18,21,17,21,16,20,15},
+   {0,11,14,8,7,8,6,8,7,8,10,7,9,7,9,7,9,6,13,15,13,15,10,14,11},
+   {0,6,7,8,7,8,7,8,7,3,3,9,11,9,11,9,11,7,15,18,14,17,12,16,12},
+   {0,6,6,8,7,8,7,8,7,4,5,10,13,10,13,10,13,8,16,20,16,19,14,18,14},
+   {0,11,14,8,6,8,6,8,7,7,9,7,8,7,8,7,8,5,13,15,12,14,10,13,10},
+   {0,12,15,9,8,9,8,9,8,7,9,8,10,8,10,8,10,7,14,17,14,16,12,15,12},
+   {0,11,14,8,6,8,6,8,7,11,13,11,14,11,14,11,14,9,17,20,17,20,15,19,14},
+   {0,12,15,9,7,9,7,9,8,7,9,6,7,6,7,6,7,5,12,14,11,13,9,12,9},
+   {0,0,0,8,7,8,7,8,7,0,0,9,11,9,11,9,11,7,15,18,14,17,12,16,12},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,31,37,3,2,3,2,3,3,38,44,8,10,8,9,8,10,7,11,14,12,13,12,16,12},
+   {0,0,0,12,10,12,10,12,11,0,0,1,2,1,1,1,1,1,5,6,5,5,6,8,7},
+   {0,24,29,0,0,0,0,0,0,34,40,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,12,14,0,0,0,0,0,1,21,25,10,13,10,13,10,13,9,14,17,14,16,15,20,15},
+   {0,0,0,12,10,12,10,12,11,0,0,1,2,1,2,1,2,1,5,6,5,5,6,8,7},
+   {0,0,0,2,2,2,2,2,3,0,0,10,12,10,12,10,12,8,13,17,14,15,14,19,14},
+   {0,0,0,12,10,12,10,12,11,0,0,4,5,4,5,4,5,3,7,10,8,8,8,12,9},
+   {0,14,16,3,2,3,2,3,3,14,16,3,4,3,4,3,4,3,7,9,7,7,8,11,9},
+   {0,0,0,11,9,11,9,11,10,0,0,1,2,1,1,1,1,1,5,6,5,5,6,8,7},
+   {0,31,37,0,0,0,0,0,0,41,47,0,0,0,0,0,0,0,11,13,11,13,11,14,9},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,1},
+   {0,34,40,0,0,0,0,0,0,34,41,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,19,23,0,0,0,0,0,0,13,15,0,0,0,0,0,0,0,3,4,3,4,3,4,3},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,2},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5,5,5,5,5,6,4},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3},
+   {0,15,17,0,0,0,0,0,0,21,24,0,0,0,0,0,0,0,8,10,8,10,8,10,7},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,3,2,2,2,3,2}},
+   
+   {{0,90,95,70,71,75,68,70,71,91,96,69,71,73,77,69,71,69,73,76,77,81,73,78,74},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,99,105,0,0,0,0,0,0,99,104,0,0,0,0,0,0,0,69,71,72,77,69,71,68},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,11,13,8,7,8,7,8,7,7,9,10,12,10,12,10,12,8,16,19,16,19,14,17,13},
+   {0,9,11,6,5,6,5,6,5,8,10,10,13,10,13,10,13,8,16,20,16,19,14,18,14},
+   {0,12,14,9,7,9,7,9,7,10,12,13,16,13,16,13,16,11,19,23,19,23,17,22,16},
+   {0,2,3,4,3,4,3,4,3,2,2,10,13,11,13,10,13,8,16,20,16,19,14,18,14},
+   {0,0,0,2,2,2,2,2,2,2,3,11,13,11,13,10,13,9,17,20,16,19,14,18,14},
+   {0,0,0,0,0,0,0,0,0,4,4,13,16,13,16,13,16,10,19,23,18,22,17,21,16},
+   {0,1,2,3,2,3,2,3,2,4,5,13,16,13,16,13,16,11,19,23,19,23,17,22,16},
+   {0,0,0,2,1,2,1,2,1,3,4,12,15,12,15,12,15,10,18,22,18,21,16,20,15},
+   {0,7,8,10,8,10,8,10,8,5,5,13,16,13,16,13,16,11,19,23,19,23,17,22,16},
+   {0,5,7,1,1,1,1,1,1,10,12,13,17,13,17,13,16,11,19,23,19,23,17,22,16},
+   {0,12,15,9,8,9,8,9,8,5,7,9,11,9,11,8,10,7,15,17,14,17,12,15,12},
+   {0,6,8,3,2,3,2,3,2,10,12,13,16,13,16,13,16,11,19,23,18,22,17,21,16},
+   {0,10,13,7,6,7,6,7,6,7,8,10,12,10,13,10,12,8,16,19,16,19,14,17,13},
+   {0,9,11,6,5,6,5,6,5,9,11,12,15,12,15,12,15,10,18,22,18,21,16,20,15},
+   {0,7,9,3,3,3,3,3,3,10,12,13,17,13,17,13,17,11,19,23,19,23,17,22,16},
+   {0,10,13,6,5,6,5,6,5,7,9,10,12,10,12,10,12,8,16,19,16,19,13,17,13},
+   {0,4,5,6,5,6,5,6,5,1,1,10,12,10,12,9,12,8,16,19,15,18,13,17,13},
+   {0,4,4,5,4,5,4,5,4,2,2,10,13,10,13,10,12,8,16,19,16,19,14,17,13},
+   {0,11,14,7,6,8,6,8,6,6,8,9,11,9,11,9,11,7,15,18,15,18,13,16,12},
+   {0,12,15,9,7,9,7,9,7,7,9,10,12,10,12,10,12,8,16,19,16,19,14,17,13},
+   {0,15,18,11,9,11,9,11,9,5,7,8,9,8,9,8,9,6,14,16,13,16,11,14,11},
+   {0,13,16,10,9,11,9,11,9,5,7,8,10,8,10,8,9,6,14,16,13,16,11,14,11},
+   {0,0,0,4,3,4,3,4,3,0,0,12,15,12,15,12,15,10,18,22,18,22,16,21,15},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,32,38,3,1,3,2,3,2,31,37,4,4,4,4,4,4,3,7,9,8,7,8,11,9},
+   {0,0,0,5,3,5,4,5,4,0,0,11,14,11,14,11,14,10,15,19,15,17,16,21,15},
+   {0,27,32,0,0,0,0,0,0,36,42,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,14,16,4,3,4,4,5,4,14,15,4,4,4,4,4,4,3,7,9,8,8,8,11,9},
+   {0,0,0,10,7,10,8,10,8,0,0,12,15,12,15,12,15,10,15,20,16,18,17,22,16},
+   {0,0,0,3,2,3,3,3,3,0,0,4,4,4,4,4,4,3,7,9,8,8,8,11,9},
+   {0,0,0,12,9,12,10,12,10,0,0,11,13,11,13,11,13,9,14,18,15,16,15,20,15},
+   {0,14,16,3,1,3,2,3,3,13,15,3,4,3,3,3,4,2,6,8,7,7,7,10,8},
+   {0,0,0,12,10,12,10,13,11,0,0,9,12,9,11,9,12,8,13,16,13,15,14,18,14},
+   {0,33,39,0,0,0,0,0,0,31,36,0,0,0,0,0,0,0,4,4,4,4,4,4,3},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,12,15,12,15,12,15,10},
+   {0,33,40,0,0,0,0,0,0,32,38,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
+   {0,15,18,0,0,0,0,0,0,19,21,0,0,0,0,0,0,0,9,11,9,11,9,11,8},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,14,17,14,17,14,17,12},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,9,10,9,10,9,11,7},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,11,13,11,13,11,13,9},
+   {0,12,14,0,0,0,0,0,0,13,15,0,0,0,0,0,0,0,4,5,4,5,4,5,3},
+   {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,11,13,11,13,10,13,9}}};
+
 
 
 extern "C" {
@@ -79,112 +191,839 @@ fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) {
    const char * const PROCEDURE_NAME = "mss_eff_config_termination";
    FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
 
+
    // Define attribute array size
-   const uint8_t PORT_SIZE = 2;
    const uint8_t DIMM_SIZE = 2;
    const uint8_t RANK_SIZE = 4;
 
+
+   // Fetch dependent attributes
+   uint8_t l_target_mba_pos = 0;
+   uint32_t l_mss_freq = 0;
+   uint32_t l_mss_volt = 0;
+   uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
+   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, 
+   uint8_t l_dram_gen_u8;
+   // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
+   uint8_t l_dimm_type_u8;
+   uint8_t l_num_drops_per_port;
+   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_target_mba_pos);
+   fapi::Target l_target_centaur;
+   rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc;
+   if (l_mss_freq <= 0) {
+      FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
+      FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+   }
+   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc;
+   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc;
+
+
+   // Fetch impacted attributes
+   uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
+   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
+
+   // find out if we are in simulation mode
+   uint8_t l_attr_is_simulation;
+   rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_attr_is_simulation);
+
+
    // Define local attribute variables
-   uint8_t my_attr_mss_cal_step_enable = 0xFF;
-   uint8_t my_attr_eff_cen_drv_imp_cmd = 15;
-   uint8_t my_attr_eff_cen_drv_imp_cntl = 15;
-   uint8_t my_attr_eff_cen_drv_imp_dq_dqs = 24;
-   uint8_t my_attr_eff_cen_rcv_imp_dq_dqs = 15;
-   uint32_t my_attr_eff_cen_rd_vref = 50000;
-   uint8_t my_attr_eff_cen_slew_rate_cmd = 0x0;
-   uint8_t my_attr_eff_cen_slew_rate_cntl = 0x0;
-   uint8_t my_attr_eff_cen_slew_rate_dq_dqs = 0x0;
-   uint8_t my_attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE];
-      my_attr_eff_dram_ron[0][0] = 34;
-      my_attr_eff_dram_ron[0][1] = 34;
-      my_attr_eff_dram_ron[1][0] = 34; 
-      my_attr_eff_dram_ron[1][1] = 34;
-   uint8_t my_attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-      my_attr_eff_dram_rtt_nom[0][0][0] = 20;
-      my_attr_eff_dram_rtt_nom[0][0][1] = 0;
-      my_attr_eff_dram_rtt_nom[0][0][2] = 0;
-      my_attr_eff_dram_rtt_nom[0][0][3] = 0;
-      my_attr_eff_dram_rtt_nom[0][1][0] = 20;
-      my_attr_eff_dram_rtt_nom[0][1][1] = 0;
-      my_attr_eff_dram_rtt_nom[0][1][2] = 0;
-      my_attr_eff_dram_rtt_nom[0][1][3] = 0;
-      my_attr_eff_dram_rtt_nom[1][0][0] = 20;
-      my_attr_eff_dram_rtt_nom[1][0][1] = 0;
-      my_attr_eff_dram_rtt_nom[1][0][2] = 0;
-      my_attr_eff_dram_rtt_nom[1][0][3] = 0;
-      my_attr_eff_dram_rtt_nom[1][1][0] = 20;
-      my_attr_eff_dram_rtt_nom[1][1][1] = 0;
-      my_attr_eff_dram_rtt_nom[1][1][2] = 0;
-      my_attr_eff_dram_rtt_nom[1][1][3] = 0;
-   uint8_t my_attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-      my_attr_eff_dram_rtt_wr[0][0][0] = 60;
-      my_attr_eff_dram_rtt_wr[0][0][1] = 60;
-      my_attr_eff_dram_rtt_wr[0][0][2] = 0;
-      my_attr_eff_dram_rtt_wr[0][0][3] = 0;
-      my_attr_eff_dram_rtt_wr[0][1][0] = 60;
-      my_attr_eff_dram_rtt_wr[0][1][1] = 60;
-      my_attr_eff_dram_rtt_wr[0][1][2] = 0;
-      my_attr_eff_dram_rtt_wr[0][1][3] = 0;
-      my_attr_eff_dram_rtt_wr[1][0][0] = 60;
-      my_attr_eff_dram_rtt_wr[1][0][1] = 60;
-      my_attr_eff_dram_rtt_wr[1][0][2] = 0;
-      my_attr_eff_dram_rtt_wr[1][0][3] = 0;
-      my_attr_eff_dram_rtt_wr[1][1][0] = 60;
-      my_attr_eff_dram_rtt_wr[1][1][1] = 60;
-      my_attr_eff_dram_rtt_wr[1][1][2] = 0;
-      my_attr_eff_dram_rtt_wr[1][1][3] = 0;
-   uint32_t my_attr_eff_dram_wr_vref = 500;
-   uint8_t my_attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-      my_attr_eff_odt_rd[0][0][0] = 0x0;
-      my_attr_eff_odt_rd[0][0][1] = 0x0;
-      my_attr_eff_odt_rd[0][0][2] = 0x0;
-      my_attr_eff_odt_rd[0][0][3] = 0x0;
-      my_attr_eff_odt_rd[0][1][0] = 0x0;
-      my_attr_eff_odt_rd[0][1][1] = 0x0;
-      my_attr_eff_odt_rd[0][1][2] = 0x0;
-      my_attr_eff_odt_rd[0][1][3] = 0x0;
-      my_attr_eff_odt_rd[1][0][0] = 0x0;
-      my_attr_eff_odt_rd[1][0][1] = 0x0;
-      my_attr_eff_odt_rd[1][0][2] = 0x0;
-      my_attr_eff_odt_rd[1][0][3] = 0x0;
-      my_attr_eff_odt_rd[1][1][0] = 0x0;
-      my_attr_eff_odt_rd[1][1][1] = 0x0;
-      my_attr_eff_odt_rd[1][1][2] = 0x0;
-      my_attr_eff_odt_rd[1][1][3] = 0x0;
-   uint8_t my_attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-      my_attr_eff_odt_wr[0][0][0] = 0x0;
-      my_attr_eff_odt_wr[0][0][1] = 0x0;
-      my_attr_eff_odt_wr[0][0][2] = 0x0;
-      my_attr_eff_odt_wr[0][0][3] = 0x0;
-      my_attr_eff_odt_wr[0][1][0] = 0x0;
-      my_attr_eff_odt_wr[0][1][1] = 0x0;
-      my_attr_eff_odt_wr[0][1][2] = 0x0;
-      my_attr_eff_odt_wr[0][1][3] = 0x0;
-      my_attr_eff_odt_wr[1][0][0] = 0x0;
-      my_attr_eff_odt_wr[1][0][1] = 0x0;
-      my_attr_eff_odt_wr[1][0][2] = 0x0;
-      my_attr_eff_odt_wr[1][0][3] = 0x0;
-      my_attr_eff_odt_wr[1][1][0] = 0x0;
-      my_attr_eff_odt_wr[1][1][1] = 0x0;
-      my_attr_eff_odt_wr[1][1][2] = 0x0;
-      my_attr_eff_odt_wr[1][1][3] = 0x0;
+   uint8_t l_attr_mss_cal_step_enable = 0xFF;
+
+   uint32_t l_attr_eff_dimm_rcd_ibt[PORT_SIZE][DIMM_SIZE];
+      l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF;
+      l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF;
+      l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF;
+      l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF;
+   uint8_t l_attr_eff_dimm_rcd_mirror_mode[PORT_SIZE][DIMM_SIZE];
+      l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+      l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+      l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+      l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+
+   uint32_t l_attr_eff_cen_rd_vref[PORT_SIZE];
+      l_attr_eff_cen_rd_vref[0] = fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000;
+      l_attr_eff_cen_rd_vref[1] = fapi::ENUM_ATTR_EFF_CEN_RD_VREF_VDD50000;
+   uint32_t l_attr_eff_dram_wr_vref[PORT_SIZE];
+      l_attr_eff_dram_wr_vref[0] = fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500;
+      l_attr_eff_dram_wr_vref[1] = fapi::ENUM_ATTR_EFF_DRAM_WR_VREF_VDD500;
+
+   uint8_t l_attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE];
+      l_attr_eff_cen_rcv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60;
+      l_attr_eff_cen_rcv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60;
+   uint8_t l_attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE];
+      l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0;
+      l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0;
+   uint8_t l_attr_eff_cen_drv_imp_cntl[PORT_SIZE];
+      l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30;
+      l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30;
+   uint8_t l_attr_eff_cen_drv_imp_addr[PORT_SIZE];
+      l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30;
+      l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30;
+   uint8_t l_attr_eff_cen_drv_imp_clk[PORT_SIZE];
+      l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30;
+      l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30;
+   uint8_t l_attr_eff_cen_drv_imp_spcke[PORT_SIZE];
+      l_attr_eff_cen_drv_imp_spcke[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40;
+      l_attr_eff_cen_drv_imp_spcke[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_SPCKE_OHM40;
+
+   uint8_t l_attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE];
+      l_attr_eff_cen_slew_rate_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS;
+   uint8_t l_attr_eff_cen_slew_rate_cntl[PORT_SIZE];
+      l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS;
+   uint8_t l_attr_eff_cen_slew_rate_addr[PORT_SIZE];
+      l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS;
+   uint8_t l_attr_eff_cen_slew_rate_clk[PORT_SIZE];
+      l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS;
+   uint8_t l_attr_eff_cen_slew_rate_spcke[PORT_SIZE];
+      l_attr_eff_cen_slew_rate_spcke[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_spcke[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS;
+
+   uint8_t l_attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE];
+      l_attr_eff_dram_ron[0][0] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34;
+      l_attr_eff_dram_ron[0][1] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34;
+      l_attr_eff_dram_ron[1][0] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34;
+      l_attr_eff_dram_ron[1][1] = fapi::ENUM_ATTR_EFF_DRAM_RON_OHM34;
+   uint8_t l_attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+      l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE; 
+      l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+      l_attr_eff_dram_rtt_nom[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE;
+   uint8_t l_attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+      l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      l_attr_eff_dram_rtt_wr[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE;
+      
+   uint8_t l_attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+      l_attr_eff_odt_rd[0][0][0] = 0x0;
+      l_attr_eff_odt_rd[0][0][1] = 0x0;
+      l_attr_eff_odt_rd[0][0][2] = 0x0;
+      l_attr_eff_odt_rd[0][0][3] = 0x0;
+      l_attr_eff_odt_rd[0][1][0] = 0x0;
+      l_attr_eff_odt_rd[0][1][1] = 0x0;
+      l_attr_eff_odt_rd[0][1][2] = 0x0;
+      l_attr_eff_odt_rd[0][1][3] = 0x0;
+      l_attr_eff_odt_rd[1][0][0] = 0x0;
+      l_attr_eff_odt_rd[1][0][1] = 0x0;
+      l_attr_eff_odt_rd[1][0][2] = 0x0;
+      l_attr_eff_odt_rd[1][0][3] = 0x0;
+      l_attr_eff_odt_rd[1][1][0] = 0x0;
+      l_attr_eff_odt_rd[1][1][1] = 0x0;
+      l_attr_eff_odt_rd[1][1][2] = 0x0;
+      l_attr_eff_odt_rd[1][1][3] = 0x0;
+   uint8_t l_attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
+      l_attr_eff_odt_wr[0][0][0] = 0x0;
+      l_attr_eff_odt_wr[0][0][1] = 0x0;
+      l_attr_eff_odt_wr[0][0][2] = 0x0;
+      l_attr_eff_odt_wr[0][0][3] = 0x0;
+      l_attr_eff_odt_wr[0][1][0] = 0x0;
+      l_attr_eff_odt_wr[0][1][1] = 0x0;
+      l_attr_eff_odt_wr[0][1][2] = 0x0;
+      l_attr_eff_odt_wr[0][1][3] = 0x0;
+      l_attr_eff_odt_wr[1][0][0] = 0x0;
+      l_attr_eff_odt_wr[1][0][1] = 0x0;
+      l_attr_eff_odt_wr[1][0][2] = 0x0;
+      l_attr_eff_odt_wr[1][0][3] = 0x0;
+      l_attr_eff_odt_wr[1][1][0] = 0x0;
+      l_attr_eff_odt_wr[1][1][1] = 0x0;
+      l_attr_eff_odt_wr[1][1][2] = 0x0;
+      l_attr_eff_odt_wr[1][1][3] = 0x0;
+
+
+   if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+      // IMP
+      l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0;
+      l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0;
+      l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30;
+      l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM30;
+      l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30;
+      l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM30;
+      l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30;
+      l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM30;
+      // SLEW
+      l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS;
+      l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_4V_NS;
+      // RTT and ODT
+      l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+      l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+      l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+      l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+      l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+      l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+      l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+      l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+      l_attr_eff_odt_wr[0][0][0] = 0x80;
+      l_attr_eff_odt_wr[1][0][0] = 0x80;
+   } else if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
+      // IMP
+      l_attr_eff_cen_drv_imp_dq_dqs[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0;
+      l_attr_eff_cen_drv_imp_dq_dqs[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0;
+      l_attr_eff_cen_drv_imp_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40;
+      l_attr_eff_cen_drv_imp_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CNTL_OHM40;
+      l_attr_eff_cen_drv_imp_addr[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40;
+      l_attr_eff_cen_drv_imp_addr[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_ADDR_OHM40;
+      l_attr_eff_cen_drv_imp_clk[0] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40;
+      l_attr_eff_cen_drv_imp_clk[1] = fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_CLK_OHM40;
+      // SLEW
+      l_attr_eff_cen_slew_rate_cntl[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_cntl[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CNTL_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_addr[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_addr[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_ADDR_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_clk[0] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS;
+      l_attr_eff_cen_slew_rate_clk[1] = fapi::ENUM_ATTR_EFF_CEN_SLEW_RATE_CLK_SLEW_3V_NS;
+      // Check DPHY01 or DHPY23
+      if ( l_target_mba_pos == 0 ) {
+         if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+            // RCD TERM
+            l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            // RTT and ODT
+            l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+            l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+            l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+            l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+            l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+            l_attr_eff_odt_rd[0][0][0] = 0x40;
+            l_attr_eff_odt_rd[0][0][1] = 0x40;
+            l_attr_eff_odt_rd[0][0][2] = 0x80;
+            l_attr_eff_odt_rd[0][0][3] = 0x80;
+            l_attr_eff_odt_rd[1][0][0] = 0x40;
+            l_attr_eff_odt_rd[1][0][1] = 0x40;
+            l_attr_eff_odt_rd[1][0][2] = 0x80;
+            l_attr_eff_odt_rd[1][0][3] = 0x80;
+            l_attr_eff_odt_wr[0][0][0] = 0xC0;
+            l_attr_eff_odt_wr[0][0][1] = 0x40;
+            l_attr_eff_odt_wr[0][0][2] = 0xC0;
+            l_attr_eff_odt_wr[0][0][3] = 0x40;
+            l_attr_eff_odt_wr[1][0][0] = 0xC0;
+            l_attr_eff_odt_wr[1][0][1] = 0x40;
+            l_attr_eff_odt_wr[1][0][2] = 0xC0;
+            l_attr_eff_odt_wr[1][0][3] = 0x40;
+         } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+            // RCD TERM
+            l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            // RTT and ODT
+            l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_odt_wr[0][0][0] = 0x80;
+            l_attr_eff_odt_wr[0][0][1] = 0x40;
+            l_attr_eff_odt_wr[1][0][0] = 0x80;
+            l_attr_eff_odt_wr[1][0][1] = 0x40;
+         } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+            // RCD TERM
+            l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+            l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+            // RTT and ODT
+            l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+            l_attr_eff_odt_wr[0][0][0] = 0x80;
+            l_attr_eff_odt_wr[1][0][0] = 0x80;
+         }
+      } else if ( l_target_mba_pos == 1 ) {
+         // Check SINGLE or DUAL Drop
+         if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) {
+            if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_odt_rd[0][0][0] = 0x40;
+               l_attr_eff_odt_rd[0][0][1] = 0x40;
+               l_attr_eff_odt_rd[0][0][2] = 0x80;
+               l_attr_eff_odt_rd[0][0][3] = 0x80;
+               l_attr_eff_odt_rd[1][0][0] = 0x40;
+               l_attr_eff_odt_rd[1][0][1] = 0x40;
+               l_attr_eff_odt_rd[1][0][2] = 0x80;
+               l_attr_eff_odt_rd[1][0][3] = 0x80;
+               l_attr_eff_odt_wr[0][0][0] = 0xC0;
+               l_attr_eff_odt_wr[0][0][1] = 0x40;
+               l_attr_eff_odt_wr[0][0][2] = 0xC0;
+               l_attr_eff_odt_wr[0][0][3] = 0x40;
+               l_attr_eff_odt_wr[1][0][0] = 0xC0;
+               l_attr_eff_odt_wr[1][0][1] = 0x40;
+               l_attr_eff_odt_wr[1][0][2] = 0xC0;
+               l_attr_eff_odt_wr[1][0][3] = 0x40;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_odt_wr[0][0][0] = 0x40;
+               l_attr_eff_odt_wr[0][0][1] = 0x80;
+               l_attr_eff_odt_wr[1][0][0] = 0x40;
+               l_attr_eff_odt_wr[1][0][1] = 0x80;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100;
+               l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM60;
+               l_attr_eff_odt_wr[0][0][0] = 0x80;
+               l_attr_eff_odt_wr[1][0][0] = 0x80;
+            }
+         } else if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) {
+            if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+               l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_nom[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_nom[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM20;
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][2] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][3] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_odt_rd[0][0][0] = 0x20;
+               l_attr_eff_odt_rd[0][0][1] = 0x20;
+               l_attr_eff_odt_rd[0][0][2] = 0x20;
+               l_attr_eff_odt_rd[0][0][3] = 0x20;
+               l_attr_eff_odt_rd[0][1][0] = 0x80;
+               l_attr_eff_odt_rd[0][1][1] = 0x80;
+               l_attr_eff_odt_rd[0][1][2] = 0x80;
+               l_attr_eff_odt_rd[0][1][3] = 0x80;
+               l_attr_eff_odt_rd[1][0][0] = 0x20;
+               l_attr_eff_odt_rd[1][0][1] = 0x20;
+               l_attr_eff_odt_rd[1][0][2] = 0x20;
+               l_attr_eff_odt_rd[1][0][3] = 0x20;
+               l_attr_eff_odt_rd[1][1][0] = 0x80;
+               l_attr_eff_odt_rd[1][1][1] = 0x80;
+               l_attr_eff_odt_rd[1][1][2] = 0x80;
+               l_attr_eff_odt_rd[1][1][3] = 0x80;
+               l_attr_eff_odt_wr[0][0][0] = 0xA0;
+               l_attr_eff_odt_wr[0][0][1] = 0x20;
+               l_attr_eff_odt_wr[0][0][2] = 0x60;
+               l_attr_eff_odt_wr[0][0][3] = 0x20;
+               l_attr_eff_odt_wr[0][1][0] = 0xA0;
+               l_attr_eff_odt_wr[0][1][1] = 0x80;
+               l_attr_eff_odt_wr[0][1][2] = 0x90;
+               l_attr_eff_odt_wr[0][1][3] = 0x80;
+               l_attr_eff_odt_wr[1][0][0] = 0xA0;
+               l_attr_eff_odt_wr[1][0][1] = 0x20;
+               l_attr_eff_odt_wr[1][0][2] = 0x60;
+               l_attr_eff_odt_wr[1][0][3] = 0x20;
+               l_attr_eff_odt_wr[1][1][0] = 0xA0;
+               l_attr_eff_odt_wr[1][1][1] = 0x80;
+               l_attr_eff_odt_wr[1][1][2] = 0x90;
+               l_attr_eff_odt_wr[1][1][3] = 0x80;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM40;
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][1] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_odt_rd[0][0][0] = 0x20;
+               l_attr_eff_odt_rd[0][0][1] = 0x20;
+               l_attr_eff_odt_rd[0][1][0] = 0x80;
+               l_attr_eff_odt_rd[0][1][1] = 0x80;
+               l_attr_eff_odt_rd[1][0][0] = 0x20;
+               l_attr_eff_odt_rd[1][0][1] = 0x20;
+               l_attr_eff_odt_rd[1][1][0] = 0x80;
+               l_attr_eff_odt_rd[1][1][1] = 0x80;
+               l_attr_eff_odt_wr[0][0][0] = 0xA0;
+               l_attr_eff_odt_wr[0][0][1] = 0x60;
+               l_attr_eff_odt_wr[0][1][0] = 0xA0;
+               l_attr_eff_odt_wr[0][1][1] = 0x60;
+               l_attr_eff_odt_wr[1][0][0] = 0xA0;
+               l_attr_eff_odt_wr[1][0][1] = 0x60;
+               l_attr_eff_odt_wr[1][1][0] = 0xA0;
+               l_attr_eff_odt_wr[1][1][1] = 0x60;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+               // RCD TERM
+               l_attr_eff_dimm_rcd_ibt[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_ibt[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200;
+               l_attr_eff_dimm_rcd_mirror_mode[0][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[0][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][0] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               l_attr_eff_dimm_rcd_mirror_mode[1][1] = fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON;
+               // RTT and ODT
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_OHM30;
+               l_attr_eff_dram_rtt_wr[0][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[0][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][0][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_dram_rtt_wr[1][1][0] = fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_OHM120;
+               l_attr_eff_odt_rd[0][0][0] = 0x20;
+               l_attr_eff_odt_rd[0][1][0] = 0x80;
+               l_attr_eff_odt_rd[1][0][0] = 0x20;
+               l_attr_eff_odt_rd[1][1][0] = 0x80;
+               l_attr_eff_odt_wr[0][0][0] = 0xA0;
+               l_attr_eff_odt_wr[0][1][0] = 0xA0;
+               l_attr_eff_odt_wr[1][0][0] = 0xA0;
+               l_attr_eff_odt_wr[1][1][0] = 0xA0;
+            }
+         }
+      } else {
+         FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString());
+         FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+      }
+   } else {
+      FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString());
+      FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+   }
+
+
+   // Modify impacted attributes
+   if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
+      for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) {
+         for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) {
+            uint64_t l_mss_freq_mask        = 0xFFFFFFFFFFCFFFFFLL;
+            uint64_t l_mss_volt_mask        = 0xFFFFFFFFFFFEFFFFLL;
+            uint64_t l_rcd_ibt_mask         = 0xFFBFFFFF8FFFFFFFLL;
+            uint64_t l_rcd_mirror_mode_mask = 0xFFFFFFFF7FFFFFFFLL;
+            if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) {
+               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005050080210000LL;
+            } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 2 ) {
+               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550000210000LL;
+            } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 1 ) {
+               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0C00000001210000LL;
+            } else {
+               l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0000000000000000LL;
+            }
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask; 
+            if ( l_mss_freq <= 933 ) {         // 800Mbps
+               l_mss_freq_mask = 0x0000000000000000LL;
+            } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+               l_mss_freq_mask = 0x0000000000100000LL;
+            } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+               l_mss_freq_mask = 0x0000000000200000LL;
+            } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+               l_mss_freq_mask = 0x0000000000300000LL;
+            } else {                           // 1866Mbps
+               FAPI_ERR("Invalid RDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+            if ( l_mss_volt >= 1420 ) {        // 1.5V
+               l_mss_volt_mask = 0x0000000000000000LL;
+            } else if ( l_mss_volt >= 1270 ) { // 1.35V
+               l_mss_volt_mask = 0x0000000000010000LL;
+            } else {                           // 1.2V 
+               FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            } 
+            if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) {
+               l_rcd_ibt_mask = 0x0000000070000000LL;
+            } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) {
+               l_rcd_ibt_mask = 0x0000000000000000LL;
+            } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_150 ) {
+               l_rcd_ibt_mask = 0x0040000000000000LL;
+            } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200 ) {
+               l_rcd_ibt_mask = 0x0000000020000000LL;
+            } else if ( l_attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_300 ) {
+               l_rcd_ibt_mask = 0x0000000040000000LL;
+            } else {
+               FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+            if ( l_attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) {
+               l_rcd_mirror_mode_mask = 0x0000000000000000LL;
+            } else if ( l_attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON ) {
+               l_rcd_mirror_mode_mask = 0x0000000080000000LL;
+            } else {
+               FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString());
+               FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            }
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask; 
+            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask; 
+         }
+      }
+   }
+
+
+   // PR_VALUE_U8ARRAY[PORT_SIZE][PR_TYPE_SIZE][TOPO_SIZE]
+   uint8_t l_attr_eff_cen_phase_rot[PR_TYPE_SIZE][PORT_SIZE];
+   uint8_t l_topo_index = 0;
+   if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) {
+      if ( l_target_mba_pos == 0 ) {
+         if ( l_mss_freq <= 933 ) {         // 800Mbps
+            l_topo_index = 0;
+         } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+            l_topo_index = 1;
+         } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+            l_topo_index = 1;
+         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+            l_topo_index = 2;
+         } else {                           // 1866Mbps
+            l_topo_index = 2;
+         }
+      } else if ( l_target_mba_pos == 1 ) {
+         if ( l_mss_freq <= 933 ) {         // 800Mbps
+            l_topo_index = 0;
+         } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+            l_topo_index = 9;
+         } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+            l_topo_index = 9;
+         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+            l_topo_index = 10;
+         } else {                           // 1866Mbps
+            l_topo_index = 10;
+         }
+      } else {
+         FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString());
+         FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+      }
+   } else {
+      if ( l_target_mba_pos == 0 ) {
+         if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+            l_topo_index = 8;
+         } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+            if ( l_mss_freq <= 933 ) {         // 800Mbps
+               l_topo_index = 0;
+            } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+               l_topo_index = 4;
+            } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+               l_topo_index = 4;
+            } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+               l_topo_index = 5;
+            } else {                           // 1866Mbps
+               l_topo_index = 5;
+            }
+         } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+            l_topo_index = 3;
+         } else {
+            l_topo_index = 0;
+         }
+      } else if ( l_target_mba_pos == 1 ) {
+         if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE ) {
+            if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+               l_topo_index = 17;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+               if ( l_mss_freq <= 933 ) {         // 800Mbps
+                  l_topo_index = 0;
+               } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+                  l_topo_index = 13;
+               } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+                  l_topo_index = 13;
+               } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+                  l_topo_index = 14;
+               } else {                           // 1866Mbps
+                  l_topo_index = 14;
+               }
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+               if ( l_mss_freq <= 933 ) {         // 800Mbps
+                  l_topo_index = 0;
+               } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+                  l_topo_index = 11;
+               } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+                  l_topo_index = 11;
+               } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+                  l_topo_index = 12;
+               } else {                           // 1866Mbps
+                  l_topo_index = 12;
+               }
+            } else {
+               l_topo_index = 0;
+            }
+         } else if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) {
+            if ( l_num_ranks_per_dimm_u8array[0][0] == 4 ) {
+               l_topo_index = 24;
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 2 ) {
+               if ( l_mss_freq <= 933 ) {         // 800Mbps
+                  l_topo_index = 0;
+               } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+                  l_topo_index = 20;
+               } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+                  l_topo_index = 20;
+               } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+                  l_topo_index = 21;
+               } else {                           // 1866Mbps
+                  l_topo_index = 21;
+               }
+            } else if ( l_num_ranks_per_dimm_u8array[0][0] == 1 ) {
+               if ( l_mss_freq <= 933 ) {         // 800Mbps
+                  l_topo_index = 0;
+               } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
+                  l_topo_index = 18;
+               } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
+                  l_topo_index = 18;
+               } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
+                  l_topo_index = 19;
+               } else {                           // 1866Mbps
+                  l_topo_index = 19;
+               }
+            } else {
+               l_topo_index = 0;
+            }
+         } else {
+            l_topo_index = 0;
+         }
+      } else {
+         FAPI_ERR("Invalid MBA on %s!", i_target_mba.toEcmdString());
+         FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+      }
+   }
+   for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) {
+      for( int l_pr_type_index = 0; l_pr_type_index < PR_TYPE_SIZE; l_pr_type_index += 1 ) {
+         l_attr_eff_cen_phase_rot[l_pr_type_index][l_port] = PR_VALUE_U8ARRAY[l_port][l_pr_type_index][l_topo_index];
+      }
+   }
+
 
    // Set attributes
-   rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, my_attr_mss_cal_step_enable); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CMD, &i_target_mba, my_attr_eff_cen_drv_imp_cmd); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, my_attr_eff_cen_drv_imp_cntl); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, my_attr_eff_cen_rd_vref); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CMD, &i_target_mba, my_attr_eff_cen_slew_rate_cmd); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, my_attr_eff_cen_slew_rate_cntl); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, my_attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, my_attr_eff_dram_ron); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, my_attr_eff_dram_rtt_nom); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, my_attr_eff_dram_rtt_wr); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, my_attr_eff_dram_wr_vref); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, my_attr_eff_odt_rd); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, my_attr_eff_odt_wr); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, l_attr_eff_dimm_rcd_ibt); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, l_attr_eff_dimm_rcd_mirror_mode); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_attr_eff_cen_rd_vref); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_attr_eff_dram_wr_vref); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, l_attr_eff_cen_drv_imp_cntl); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba, l_attr_eff_cen_drv_imp_addr); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba, l_attr_eff_cen_drv_imp_clk); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba, l_attr_eff_cen_drv_imp_spcke); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, l_attr_eff_cen_slew_rate_cntl); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba, l_attr_eff_cen_slew_rate_addr); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba, l_attr_eff_cen_slew_rate_clk); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba, l_attr_eff_cen_slew_rate_spcke); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, l_attr_eff_dram_ron); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, l_attr_eff_dram_rtt_nom); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, l_attr_eff_dram_rtt_wr); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, l_attr_eff_odt_rd); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, l_attr_eff_odt_wr); if(rc) return rc;
+
+   if(l_attr_is_simulation || 1) {
+     FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation);
+
+     for(int i=0;i<2;i++) {
+       l_attr_eff_cen_phase_rot[0][i]=0;
+       l_attr_eff_cen_phase_rot[1][i]=0;
+       l_attr_eff_cen_phase_rot[2][i]=0;
+       l_attr_eff_cen_phase_rot[3][i]=0;
+       l_attr_eff_cen_phase_rot[4][i]=0;
+       l_attr_eff_cen_phase_rot[5][i]=0;
+       l_attr_eff_cen_phase_rot[6][i]=0;
+       l_attr_eff_cen_phase_rot[7][i]=0;
+       l_attr_eff_cen_phase_rot[8][i]=0;
+       l_attr_eff_cen_phase_rot[9][i]=0;
+       l_attr_eff_cen_phase_rot[10][i]=0;
+       l_attr_eff_cen_phase_rot[11][i]=0;
+       l_attr_eff_cen_phase_rot[12][i]=0;
+       l_attr_eff_cen_phase_rot[13][i]=0;
+       l_attr_eff_cen_phase_rot[14][i]=0;
+       l_attr_eff_cen_phase_rot[15][i]=0;
+       l_attr_eff_cen_phase_rot[16][i]=0;
+       l_attr_eff_cen_phase_rot[17][i]=0;
+       l_attr_eff_cen_phase_rot[18][i]=0;
+       l_attr_eff_cen_phase_rot[19][i]=0;
+       l_attr_eff_cen_phase_rot[20][i]=0;
+       l_attr_eff_cen_phase_rot[21][i]=0;
+       l_attr_eff_cen_phase_rot[22][i]=0;
+       l_attr_eff_cen_phase_rot[23][i]=0;
+       l_attr_eff_cen_phase_rot[24][i]=0;
+       l_attr_eff_cen_phase_rot[25][i]=0;
+       l_attr_eff_cen_phase_rot[26][i]=0;
+       l_attr_eff_cen_phase_rot[27][i]=0;
+       l_attr_eff_cen_phase_rot[28][i]=0;
+       l_attr_eff_cen_phase_rot[29][i]=0;
+       l_attr_eff_cen_phase_rot[30][i]=0;
+       l_attr_eff_cen_phase_rot[31][i]=0;
+       l_attr_eff_cen_phase_rot[32][i]=0;
+       l_attr_eff_cen_phase_rot[33][i]=0;
+       l_attr_eff_cen_phase_rot[34][i]=0;
+       l_attr_eff_cen_phase_rot[35][i]=0;
+       l_attr_eff_cen_phase_rot[36][i]=0;
+       l_attr_eff_cen_phase_rot[37][i]=0;
+       l_attr_eff_cen_phase_rot[38][i]=0;
+       l_attr_eff_cen_phase_rot[39][i]=0;
+       l_attr_eff_cen_phase_rot[40][i]=0;
+       l_attr_eff_cen_phase_rot[41][i]=0;
+       l_attr_eff_cen_phase_rot[42][i]=0;
+       l_attr_eff_cen_phase_rot[43][i]=0;
+       l_attr_eff_cen_phase_rot[44][i]=0;
+       l_attr_eff_cen_phase_rot[45][i]=0;
+       l_attr_eff_cen_phase_rot[46][i]=0;
+       l_attr_eff_cen_phase_rot[47][i]=0;
+     }
+   }
+
+
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, l_attr_eff_cen_phase_rot[0]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, l_attr_eff_cen_phase_rot[1]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, l_attr_eff_cen_phase_rot[2]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, l_attr_eff_cen_phase_rot[3]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, l_attr_eff_cen_phase_rot[4]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, l_attr_eff_cen_phase_rot[5]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, l_attr_eff_cen_phase_rot[6]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, l_attr_eff_cen_phase_rot[7]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, l_attr_eff_cen_phase_rot[8]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, l_attr_eff_cen_phase_rot[9]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, l_attr_eff_cen_phase_rot[10]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, l_attr_eff_cen_phase_rot[11]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, l_attr_eff_cen_phase_rot[12]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, l_attr_eff_cen_phase_rot[13]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, l_attr_eff_cen_phase_rot[14]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, l_attr_eff_cen_phase_rot[15]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, l_attr_eff_cen_phase_rot[16]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, l_attr_eff_cen_phase_rot[17]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, l_attr_eff_cen_phase_rot[18]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, l_attr_eff_cen_phase_rot[19]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, l_attr_eff_cen_phase_rot[20]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, l_attr_eff_cen_phase_rot[21]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, l_attr_eff_cen_phase_rot[22]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, l_attr_eff_cen_phase_rot[23]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, l_attr_eff_cen_phase_rot[24]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, l_attr_eff_cen_phase_rot[25]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_PAR, &i_target_mba, l_attr_eff_cen_phase_rot[26]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M_ACTN, &i_target_mba, l_attr_eff_cen_phase_rot[27]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, l_attr_eff_cen_phase_rot[28]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, l_attr_eff_cen_phase_rot[29]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, l_attr_eff_cen_phase_rot[30]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, l_attr_eff_cen_phase_rot[31]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, l_attr_eff_cen_phase_rot[32]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, l_attr_eff_cen_phase_rot[33]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, l_attr_eff_cen_phase_rot[34]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, l_attr_eff_cen_phase_rot[35]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, l_attr_eff_cen_phase_rot[36]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, l_attr_eff_cen_phase_rot[37]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, l_attr_eff_cen_phase_rot[38]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, l_attr_eff_cen_phase_rot[39]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, l_attr_eff_cen_phase_rot[40]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, l_attr_eff_cen_phase_rot[41]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, l_attr_eff_cen_phase_rot[42]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, l_attr_eff_cen_phase_rot[43]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, l_attr_eff_cen_phase_rot[44]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, l_attr_eff_cen_phase_rot[45]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, l_attr_eff_cen_phase_rot[46]); if(rc) return rc;
+   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, l_attr_eff_cen_phase_rot[47]); if(rc) return rc;
 
    FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
    return rc;
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
index e8c23eda6..30a69e334 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.C,v 1.8 2012/06/13 20:53:57 pardeik Exp $
+// $Id: mss_eff_config_thermal.C,v 1.13 2012/11/28 21:33:11 pardeik Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -33,15 +33,15 @@
 // *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
 // *! ADDITIONAL COMMENTS :
 //
+// applicable CQ component memory_screen
+//
 // DESCRIPTION:
 // The purpose of this procedure is to set the default throttle and power attributes for dimms in a given system
-// -- The throttles here are intended to be the thermal runtime throttles for dimm/channel N/M
 // -- The power attributes are the slope/intercept values.  Note that these values are in cW.
 // -- The power values are determined by DRAM Generation and Width (with various uplifts/adders applied)
-//	and will be derived from the model and then verified with hardware measurements
 //	-- Power will be per rank for a given dram generation and width
 //	-- Uplifts will be applied for dimm type, number of ranks
-// -- Thermal values are system dependent and will need to come from the machine readable workbook
+// -- The throttle attributes will setup values for safemode and runtime
 //
 //
 //------------------------------------------------------------------------------
@@ -51,6 +51,11 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.13  | pardeik  |28-NOV-12| fixed hostboot compile errors
+//   1.12  | pardeik  |07-NOV-12| updated to use new SI attributes and their enums
+//   1.11  | pardeik  |22-OCT-12| Use the schmoo attributes to find wc termination, updated hwp errors, removed unneeded variables, added CQ component comment line, updated safemode throttle default values
+//   1.10  | pardeik  |19-OCT-12| Enable TYPE_1D for ODT mapping.  Set ISDIMM supplier power curve to master power curve
+//   1.9   | pardeik  |11-OCT-12| updated to use new attributes, termination power calculation added in
 //   1.8   | pardeik  |13-JUN-12| Major rewrite to have dimm power determined by dram generation and width, with uplifts applied (not based on dimm size lookup table any longer)
 //   1.7   | pardeik  |04-MAY-12| removed typedef from structures, use fapi to define dimm type enums
 //   1.6   | pardeik  |10-APR-12| update cdimm power/int default, change power_thermal_values_t to use int32_t instead of uint32_t in order to identify a negative value correctly, added dimm config to the messages printed out
@@ -61,28 +66,99 @@
 //   1.2   | asaetow  |03-NOV-11| Changed format of file and made function lower case. 
 //   1.1   | pardeik  |01-NOV-11| First Draft.
 
+/*
+TODO ITEMS:
+
+Waiting for platinit attributes to enable sections in this procedure:
+1.  Power Curves to originate from CDIMM VPD (platinit)
+2.  Thermal memory power limit from MRW (platinit)
+3.  Safemode throttles from MRW (platinit)
+4.  ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO and ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO enable sections of this procedure when they are used
+5.  Need runtime throttles non-volatile and initialized to zero by firmware on the first IPL
+6.  Error callouts
+
+*/
 
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  My Includes
+//------------------------------------------------------------------------------
+#include <mss_eff_config_thermal.H>
+#include <mss_bulk_pwr_throttles.H>
+
+//------------------------------------------------------------------------------
 //  Includes
-//----------------------------------------------------------------------
+//------------------------------------------------------------------------------
 #include <fapi.H>
-#include <mss_eff_config_thermal.H>
+
+//------------------------------------------------------------------------------
+//  Constants
+//------------------------------------------------------------------------------
+const uint8_t NUM_PORTS = 2;				// number of ports per MBA
+const uint8_t NUM_DIMMS = 2;				// number of dimms per MBA port
+const uint8_t NUM_RANKS = 4;				// number of ranks per dimm
+const uint32_t ISDIMM_POWER_SLOPE_DEFAULT = 940;		// default power slope (cW/utilization)
+const uint32_t ISDIMM_POWER_INT_DEFAULT = 900;		// default power intercept (cW)
+const uint32_t CDIMM_POWER_SLOPE_DEFAULT = 0x8240;		// default power slope (cW/utilization)
+const uint32_t CDIMM_POWER_INT_DEFAULT = 0x80CE;		// default power intercept (cW)
+const uint8_t IDLE_DIMM_UTILIZATION = 0;		// DRAM data bus utilization percent for the idle power defined in table below - needs to be 0
+const uint8_t ACTIVE_DIMM_UTILIZATION = 70;		// DRAM data bus utilization percent for the active power defined in table below (reads+writes)
+const uint8_t DATA_BUS_READ_PERCENT = 66;		// read percentage of data bus
+const uint8_t DATA_BUS_WRITE_PERCENT = 34;		// write percentage of data bus
+
 
 extern "C" {
 
     using namespace fapi;
 
-// Procedures in this file
-    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target);
+//------------------------------------------------------------------------------
+// Funtions in this file
+//------------------------------------------------------------------------------
+    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba);
+
+    fapi::ReturnCode mss_eff_config_thermal_term(
+						      const char nom_or_wc_term[4],
+						      uint8_t i_port,
+						      uint8_t i_dimm,
+						      uint8_t i_rank,
+						      uint32_t i_dimm_voltage,
+						      uint8_t i_dram_width,
+						      uint8_t i_dram_tdqs,
+						      uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
+						      uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
+						      uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
+						      uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						      uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						      uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						      uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						      uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
+						      uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
+						      float &o_dimm_power_adder_termination
+						      );
 
-//******************************************************************************
-// 
-//******************************************************************************
+    fapi::ReturnCode mss_eff_config_thermal_get_wc_term(
+							const fapi::Target &i_target_mba,
+							uint8_t i_port,
+							uint8_t &o_cen_dq_dqs_rcv_imp_wc,
+							uint8_t &o_cen_dq_dqs_drv_imp_wc
+							);
 
-    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target)
+    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value(
+							      uint8_t i_cen_dq_dqs_drv_imp,
+							      uint8_t &o_cen_dq_dqs_drv_imp
+							      );
+
+//------------------------------------------------------------------------------
+// @brief mss_eff_config_thermal(): This function determines the power and throttle attribute values to use
+//
+// @param    const fapi::Target & i_target_mba:  MBA Target passed in
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba)
     {
 
-	fapi::ReturnCode l_rc;
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
 
 	char procedure_name[32];
 	sprintf(procedure_name, "mss_eff_config_thermal");
@@ -105,281 +181,1214 @@ extern "C" {
 	struct dimm_power_t
 	{
 	    uint32_t	idle;
-	    uint32_t	max;
+	    uint32_t	active;
 	};
 	struct dimm_type_t
 	{
 	    int32_t	udimm;
 	    int32_t	lrdimm;
 	    int32_t	rdimm;
-	    int32_t	cdimm;
-	};
-	struct dimm_voltage_t
-	{
-	    int8_t	volt1500;
-	    int8_t	volt1350;
-	    int8_t	volt1200;
-	};
-	struct dimm_frequency_t
-	{
-	    int8_t	freq1066;
-	    int8_t	freq1333;
-	    int8_t	freq1600;
 	};
 	struct power_data_t
 	{
 	    uint8_t		dram_generation;
 	    uint8_t		dram_width;
 	    uint8_t		dimm_ranks;
-	    dimm_power_t	rank_master_power;
+	    dimm_power_t	rank_power;
 	    dimm_type_t		dimm_type_adder;
-	    dimm_power_t	rank_slave_adder;
-	    dimm_voltage_t	dimm_voltage_adder;
-	    dimm_frequency_t	dimm_frequency_adder;	    
+	    int32_t		dimm_voltage_base;
+	    int32_t		dimm_frequency_base;	    
 	};
 
-power_data_t l_power_table[] =
-{
-// Master Ranks column uses the values in the same table entry for the number of master ranks specified.  Default is to have it use same power for each master rank, so that is why master ranks = 1.  If we need to separate power based on number of master ranks, then have the table setup for descending master rank values.  We always need an entry for master ranks of 1.  Table lookup will stop after first matching entry is found (DRAM Generation, DRAM Width, and Master Ranks = l_dimm_master_ranks_array OR 1)
-//
-// Note:  Slave rank full bw is set to idle, since the active power for full bw will be acounted for the master rank (ie.  only one rank active at a time).  Set slave rank full bw to the slave rank idle bw power value.
+// Master Ranks column uses the values in the same table entry for the number of master ranks specified.  Default is to have it use same power for each master rank, so that is why master ranks = 1.  If we need to separate power based on number of master ranks, then have the table setup for descending master rank values.  We always need an entry for master ranks of 1.  Table lookup will stop after first matching entry is found (DRAM Generation, DRAM Width, and Master Ranks = dimm_master_ranks_array OR 1)
 //
-//  DRAM	DRAM	Master	MasterRankPower	DIMMTypeAdder	SlaveRankAdder	VoltageAdder	FrequencyAdder
-//  Generation	Width	Ranks	(cW)		(cW)		(cW)		(%)		(%)
-//  DDR3	X4	1	idle,full	UDIMM,LRDIMM,	idle,full	1.5,1.35,1.2	1066,1333,1600
-//  or		or				RDIMM,CDIMM
-//  DDR4	X8		
+//            DRAM	DRAM	Master	RankPower	DIMMTypeAdder	BaseVoltage	BaseFrequency
+//            GenerationWidth	Ranks	(cW)		(cW)		(mV)		(MHz)
+//            DDR3	X4	1	idle,full	UDIMM,LRDIMM,	1500,1350,1200	1066,1333,1600
+//            or	or				RDIMM		for values in	for values in
+//            DDR4	X8						this table	this table
 //				
+	power_data_t power_table[] =
+	{
+	    { DDR3,	X4,	1,	{ 70,373},	{0,93,104},	1350,		1066         },
+	    { DDR3,	X8,	1,	{ 52,300},	{0,93,104},	1350,		1066         },
+	    { DDR4,	X4,	1,	{ 70,373},	{0,93,104},	1350,		1066         },
+	    { DDR4,	X8,	1,	{ 52,300},	{0,93,104},	1350,		1066         },
+	};
+
 
-// TODO:  Finalize these values against model.  These are just place holders for now and will work for the time being.
-    { DDR3,	X4,	1,	{ 65,650},	{0,50,100,0},	{ 65,65},	{10,0,-10},     {0,10,20}         },
-    { DDR3,	X8,	1,	{ 50,500},	{0,50,100,0},	{ 50,50},	{10,0,-10},     {0,10,20}         },
-    { DDR4,	X4,	1,	{ 65,650},	{0,50,100,0},	{ 65,65},	{10,0,-10},     {0,10,20}         },
-    { DDR4,	X8,	1,	{ 50,500},	{0,50,100,0},	{ 50,50},	{10,0,-10},     {0,10,20}         },
-};
-
-// Default values defined here
-	const uint8_t l_num_ports = 2;				// number of ports per MBA
-	const uint8_t l_num_dimms = 2;				// number of dimms per MBA port
-	const uint32_t l_dimm_power_slope_default = 940;	// default power slope (cW/utilization)
-	const uint32_t l_dimm_power_int_default = 900;		// default power intercept (cW)
-	const uint32_t l_dimm_throttle_n_default = 100;		// default dimm throttle numerator
-	const uint32_t l_dimm_throttle_d_default = 100;		// default dimm throttle denominator
-	const uint32_t l_channel_throttle_n_default = 100;	// default channel throttle numerator
-	const uint32_t l_channel_throttle_d_default = 100;	// default channel throttle denominator
-	const uint8_t l_idle_dimm_utilization = 0;		// DRAM data bus utilization for the idle power defined in table below
-	const uint8_t l_max_dimm_utilization = 100;		// DRAM data bus utilization for the active power defined in table below
-
-// other variables used in this procedure
-	fapi::Target l_targetCentaur;
-	std::vector<fapi::Target> l_targetDimm;
+// other variables used in this function
+	fapi::Target target_chip;
+	std::vector<fapi::Target> target_mba_array;
+	std::vector<fapi::Target> target_dimm_array;
 	uint8_t port;
 	uint8_t dimm;
+	uint8_t rank;
 	uint8_t entry;
-	uint8_t l_dimm_type;
-	uint8_t l_dimm_ranks_array[l_num_ports][l_num_dimms];
-	uint32_t l_list_sz;
-	uint32_t l_power_slope_array[l_num_ports][l_num_dimms];
-	uint32_t l_power_int_array[l_num_ports][l_num_dimms];
-	uint32_t l_dimm_throttle_n_array[l_num_ports][l_num_dimms];
-	uint32_t l_dimm_throttle_d_array[l_num_ports][l_num_dimms];
-	uint32_t l_channel_throttle_n_array[l_num_ports];
-	uint32_t l_channel_throttle_d_array[l_num_ports];
-	uint8_t l_found_entry_in_table;
-	uint8_t l_dram_width;
-	uint8_t l_dram_gen;
-	uint32_t l_dimm_voltage;
-	uint32_t l_dimm_frequency;
-	uint8_t l_dimm_ranks_configed_array[l_num_ports][l_num_dimms];
-	uint8_t l_dimm_master_ranks_array[l_num_ports][l_num_dimms];
-	int32_t l_dimm_power_adder_type;
-	int8_t l_dimm_power_adder_volt;
-	int8_t l_dimm_power_adder_freq;
-	uint32_t l_dimm_idle_power_adder_slave;
-	uint32_t l_dimm_max_power_adder_slave;
-	int32_t l_dimm_idle_power;
-	int32_t l_dimm_max_power;
-	uint8_t l_dimm_num_slave_ranks;
-
-	l_list_sz = (sizeof(l_power_table))/(sizeof(power_data_t));
+	uint8_t dimm_type;
+	uint8_t dimm_ranks_array[NUM_PORTS][NUM_DIMMS];
+	uint32_t power_table_size;
+	uint32_t power_slope_array[NUM_PORTS][NUM_DIMMS];
+	uint32_t power_int_array[NUM_PORTS][NUM_DIMMS];
+	uint32_t power_slope2_array[NUM_PORTS][NUM_DIMMS];
+	uint32_t power_int2_array[NUM_PORTS][NUM_DIMMS];
+	uint8_t found_entry_in_table;
+	uint8_t dram_width;
+	uint8_t dram_tdqs;
+	uint8_t dram_gen;
+	uint32_t dimm_voltage;
+	uint32_t dimm_frequency;
+	uint8_t dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS];
+	uint8_t dimm_master_ranks_array[NUM_PORTS][NUM_DIMMS];
+	int32_t dimm_power_adder_type;
+	float dimm_power_multiplier_volt;
+	float dimm_power_mulitiplier_freq;
+	float dimm_idle_power;
+	float dimm_active_power;
+	float dimm_power_adder_termination;
+	float dimm_power_adder_termination_largest = 0;
+	uint8_t dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS];
+	uint8_t dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS];
+	uint8_t dimm_dram_ron[NUM_PORTS][NUM_DIMMS];
+	uint8_t cen_dq_dqs_rcv_imp[NUM_PORTS];
+	uint8_t cen_dq_dqs_drv_imp[NUM_PORTS];
+	float dimm_power_adder_termination_wc;
+	float dimm_power_adder_termination_largest_wc = 0;
+	uint8_t cen_dq_dqs_rcv_imp_wc[NUM_PORTS];
+	uint8_t cen_dq_dqs_drv_imp_wc[NUM_PORTS];
+	uint8_t num_dimms_on_port;
+	uint32_t throttle_n_per_mba;
+	uint32_t throttle_n_per_chip;
+	uint32_t throttle_d;
+	uint32_t runtime_throttle_n_per_mba;
+	uint32_t runtime_throttle_n_per_chip;
+	uint32_t runtime_throttle_d;
+	uint8_t dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS];
+	uint8_t dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS];
+	uint8_t ibm_type[NUM_PORTS][NUM_DIMMS];
+	char dram_gen_str[4];
+	uint32_t dimm_thermal_power_limit;
+	uint32_t channel_pair_thermal_power_limit;
+	uint8_t num_mba_with_dimms = 0;
+	uint8_t mba_index;
+	uint8_t dimm_number_registers[NUM_PORTS][NUM_DIMMS];
+	uint8_t dimm_index;
+	uint32_t cdimm_master_power_slope;
+	uint32_t cdimm_master_power_intercept;
+	uint32_t cdimm_supplier_power_slope;
+	uint32_t cdimm_supplier_power_intercept;
+	uint32_t safemode_throttle_n_per_mba;
+	uint32_t safemode_throttle_n_per_chip;
+	uint32_t safemode_throttle_d;
+
+	power_table_size = (sizeof(power_table))/(sizeof(power_data_t));
 
 // Get input attributes
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, l_dimm_ranks_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, l_dimm_master_ranks_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target, l_dimm_ranks_configed_array);
-	if(l_rc) return l_rc;
-// TODO:  Get Attributes for number of registers on ISDIMM and Termination settings being used
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, dram_gen);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, dram_width);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target_mba, dram_tdqs);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, dimm_ranks_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, dimm_master_ranks_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, dimm_ranks_configed_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RON, &i_target_mba, dimm_dram_ron);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_ODT_RD, &i_target_mba, dimm_rank_odt_rd);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_ODT_WR, &i_target_mba, dimm_rank_odt_wr);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, cen_dq_dqs_rcv_imp);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, cen_dq_dqs_drv_imp);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, dram_rtt_nom);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, dram_rtt_wr);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_IBM_TYPE, &i_target_mba, ibm_type);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, num_dimms_on_port);
+	if(rc) return rc;
+// TODO:  use vpd values when power curve data is available from CDIMM VPD (platinit), remove hardcoding
+	cdimm_master_power_slope = CDIMM_POWER_SLOPE_DEFAULT;
+	cdimm_master_power_intercept = CDIMM_POWER_INT_DEFAULT;
+	cdimm_supplier_power_slope = CDIMM_POWER_SLOPE_DEFAULT;
+	cdimm_supplier_power_intercept = CDIMM_POWER_INT_DEFAULT;
+//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_SLOPE, &i_target_mba, cdimm_master_power_slope);
+//	if(rc) return rc;
+//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_MASTER_POWER_INTERCEPT, &i_target_mba, cdimm_master_power_intercept);
+//	if(rc) return rc;
+//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_SLOPE, &i_target_mba, cdimm_supplier_power_slope);
+//	if(rc) return rc;
+//	rc = FAPI_ATTR_GET(ATTR_SPD_CDIMM_SUPPLIER_POWER_INTERCEPT, &i_target_mba, cdimm_supplier_power_intercept);
+//	if(rc) return rc;
+// TODO:  Get Safemode throttles from MRW (platinit), hardcode until available - Keep here until cronus is able to set runtime memory throttles at the end of istep
+	safemode_throttle_n_per_mba = 96;
+//	safemode_throttle_n_per_chip = 32;
+	safemode_throttle_n_per_chip = 96;
+	safemode_throttle_d = 512;
+//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, safemode_throttle_n_per_mba);
+//	if(rc) return rc;
+//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, safemode_throttle_n_per_chip);
+//	if(rc) return rc;
+//	rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR, &i_target_mba, safemode_throttle_d);
+//	if(rc) return rc;
+// TODO:  Get Thermal power Limit from MRW (platinit), hardcode until available
+	if (dimm_type == CDIMM)
+	{
+	    dimm_thermal_power_limit = 5000; // in cW, per CDIMM, high limit
+//	    dimm_thermal_power_limit = 2500; // in cW, per CDIMM
+	}
+	else
+	{
+	    dimm_thermal_power_limit = 2000; // in cW, per ISDIMM, high limit
+//	    dimm_thermal_power_limit = 600; // in cW, per ISDIMM
+	}
+//	rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT, &i_target_mba, dimm_thermal_power_limit);
+//	if(rc) return rc;
+
 
 // Get Centaur target for the given MBA
+	rc = fapiGetParentChip(i_target_mba, target_chip);
+	if(rc) return rc;
 // Get voltage and frequency attributes
-	l_rc = fapiGetParentChip(i_target, l_targetCentaur);
-	if(l_rc)
+	rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &target_chip, dimm_voltage);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &target_chip, dimm_frequency);
+	if(rc) return rc;
+
+// get any attributes from DIMM SPD
+	if (dimm_type != CDIMM)
 	{
-	    FAPI_ERR("Error getting Centaur parent target for the given MBA");
-	    return l_rc;
+	    rc = fapiGetAssociatedDimms(i_target_mba, target_dimm_array, fapi::TARGET_STATE_PRESENT);
+	    if(rc) return rc;
+	    for (dimm_index=0; dimm_index < target_dimm_array.size(); dimm_index++)
+	    {
+		rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &target_dimm_array[dimm_index], port);
+		if(rc) return rc;
+		rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &target_dimm_array[dimm_index], dimm);
+		if(rc) return rc;
+		rc = FAPI_ATTR_GET(ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM, &target_dimm_array[dimm_index], dimm_number_registers[port][dimm]);
+		if(rc) return rc;
+	    }
 	}
-	l_rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_targetCentaur, l_dimm_voltage);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_targetCentaur, l_dimm_frequency);
-	if(l_rc) return l_rc;
 
+// Get number of Centaur MBAs that have dimms present
+	if (dimm_type == CDIMM)
+	{
+	    rc = fapiGetChildChiplets(target_chip, fapi::TARGET_TYPE_MBA_CHIPLET, target_mba_array, fapi::TARGET_STATE_PRESENT);
+	    if(rc) return rc;
+	    num_mba_with_dimms = 0;
+	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
+	    {
+		rc = fapiGetAssociatedDimms(target_mba_array[mba_index], target_dimm_array, fapi::TARGET_STATE_PRESENT);
+		if(rc) return rc;
+		if (target_dimm_array.size() > 0)
+		{
+		    num_mba_with_dimms++;
+		}
+	    }
+	}
 
-// iterate through the MBA ports to define power and thermal attributes
-	for (port=0; port < l_num_ports; port++)
+// determine worst case termination settings here for ISDIMMs (to be used later)
+	if (dimm_type != CDIMM)
 	{
-// initialize channel entries to zero
-	    l_channel_throttle_n_array[port] = 0;
-	    l_channel_throttle_d_array[port] = 0;
-// iterate through the dimms on each port
-	    for (dimm=0; dimm < l_num_dimms; dimm++)
+// get worst case termination values that will be used
+// Only look at Centaur DQ/DQS Driver and Receiver termination settings
+// Note that the DRAM rtt_nom, rtt_wr, and ron will not be allowed to change, all these will stay at the nominal settings
+	    for (port=0; port < NUM_PORTS; port++)
+	    {
+		rc = mss_eff_config_thermal_get_wc_term(
+							i_target_mba,
+							port,
+							cen_dq_dqs_rcv_imp_wc[port],
+							cen_dq_dqs_drv_imp_wc[port]
+							);
+		if(rc)
+		{
+		    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_get_wc_term", static_cast<uint32_t>(rc));
+		    return rc;
+		}
+	    }
+	}
+
+////////////////////////////////////////////////////////////////////////
+// Power Curve Determination
+////////////////////////////////////////////////////////////////////////
+// Iterate through the MBA ports to get power slope/intercept values
+	for (port=0; port < NUM_PORTS; port++)
+	{
+// Get termination power for ISDIMM
+	    if (dimm_type != CDIMM)
+	    {
+		dimm_power_adder_termination_largest=0;
+		dimm_power_adder_termination_largest_wc=0;
+
+// iterate through the dimms on each port to determine termination power to use
+		for (dimm=0; dimm < NUM_DIMMS; dimm++)
+		{
+// calculate the effective net termination for each rank
+		    for (rank=0; rank < NUM_RANKS; rank++)
+		    {
+// nominal termination
+			rc = mss_eff_config_thermal_term(
+							 "NOM",
+							 port,
+							 dimm,
+							 rank,
+							 dimm_voltage,
+							 dram_width,
+							 dram_tdqs,
+							 ibm_type,
+							 dimm_ranks_configed_array,
+							 dimm_dram_ron,
+							 dimm_rank_odt_rd,
+							 dimm_rank_odt_wr,
+							 dram_rtt_nom,
+							 dram_rtt_wr,
+							 cen_dq_dqs_rcv_imp,
+							 cen_dq_dqs_drv_imp,
+							 dimm_power_adder_termination
+							 );
+			if(rc)
+			{
+			    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_term", static_cast<uint32_t>(rc));
+			    return rc;
+			}
+			if (dimm_power_adder_termination > dimm_power_adder_termination_largest)
+			{
+			    dimm_power_adder_termination_largest = dimm_power_adder_termination;
+			}
+
+// worst case termination
+			rc = mss_eff_config_thermal_term(
+							 "WC",
+							 port,
+							 dimm,
+							 rank,
+							 dimm_voltage,
+							 dram_width,
+							 dram_tdqs,
+							 ibm_type,
+							 dimm_ranks_configed_array,
+							 dimm_dram_ron,
+							 dimm_rank_odt_rd,
+							 dimm_rank_odt_wr,
+							 dram_rtt_nom,
+							 dram_rtt_wr,
+							 cen_dq_dqs_rcv_imp_wc,
+							 cen_dq_dqs_drv_imp_wc,
+							 dimm_power_adder_termination_wc
+							 );
+			if(rc)
+			{
+			    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_term", static_cast<uint32_t>(rc));
+			    return rc;
+			}
+			if (dimm_power_adder_termination_wc > dimm_power_adder_termination_largest_wc)
+			{
+			    dimm_power_adder_termination_largest_wc = dimm_power_adder_termination_wc;
+			}
+		    }
+		}
+	    }
+
+// iterate through the dimms on each port again to determine power slope and intercept
+	    for (dimm=0; dimm < NUM_DIMMS; dimm++)
 	    {
 // initialize dimm entries to zero
-		l_dimm_throttle_n_array[port][dimm] = 0;
-		l_dimm_throttle_d_array[port][dimm] = 0;
-		l_power_slope_array[port][dimm] = 0;
-		l_power_int_array[port][dimm] = 0;
+		power_slope_array[port][dimm] = 0;
+		power_int_array[port][dimm] = 0;
+		power_slope2_array[port][dimm] = 0;
+		power_int2_array[port][dimm] = 0;
 // only update values for dimms that are physically present
-		if (l_dimm_ranks_array[port][dimm] > 0)
+		if (dimm_ranks_array[port][dimm] > 0)
 		{
-// TODO:  Placeholder for thermal attributes that will come from machine readable workbook (runtime throttles) - Hardcode these to the default values for now.
-// TODO:  IPL throttles will need to be added into an initfile once available.
-		    l_dimm_throttle_n_array[port][dimm] = l_dimm_throttle_n_default;
-		    l_dimm_throttle_d_array[port][dimm] = l_dimm_throttle_d_default;
-		    l_channel_throttle_n_array[port] = l_channel_throttle_n_default;
-		    l_channel_throttle_d_array[port] = l_channel_throttle_d_default;
-
-// Get the dimm power from table and add on any adjustments (if not found in table - should never happen, then default values will be used)
-		    l_power_slope_array[port][dimm] = l_dimm_power_slope_default;
-		    l_power_int_array[port][dimm] = l_dimm_power_int_default;
-		    l_found_entry_in_table = 0;
-		    for (entry = 0; entry < l_list_sz; entry++) {
-			if ((l_power_table[entry].dram_generation == l_dram_gen) && (l_power_table[entry].dram_width == l_dram_width) && ((l_power_table[entry].dimm_ranks == l_dimm_master_ranks_array[port][dimm]) || (l_power_table[entry].dimm_ranks == 1)))
+
+// CDIMM power slope/intercept will come from VPD
+// Data in VPD needs to be the power per virtual dimm on the CDIMM
+		    if (dimm_type == CDIMM)
+		    {
+			power_slope_array[port][dimm] = cdimm_master_power_slope;
+			power_int_array[port][dimm] = cdimm_master_power_intercept;
+			power_slope2_array[port][dimm] = cdimm_supplier_power_slope;
+			power_int2_array[port][dimm] = cdimm_supplier_power_intercept;
+
+// check to see if data is valid
+			if ((((cdimm_master_power_slope & 0x8000) != 0) && ((cdimm_master_power_intercept & 0x8000) != 0)) && (((cdimm_supplier_power_slope & 0x8000) != 0) && ((cdimm_supplier_power_intercept & 0x8000) != 0)))
 			{
-// get adder for dimm type
-			    if (l_dimm_type == UDIMM) {
-				l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.udimm;
-			    }
-			    else if (l_dimm_type == LRDIMM)
+			    power_slope_array[port][dimm] = cdimm_master_power_slope & 0x1FFF;
+			    power_int_array[port][dimm] = cdimm_master_power_intercept & 0x1FFF;
+			    power_slope2_array[port][dimm] = cdimm_supplier_power_slope & 0x1FFF;
+			    power_int2_array[port][dimm] = cdimm_supplier_power_intercept & 0x1FFF;
+// check to see if data is lab data
+			    if ((((cdimm_master_power_slope & 0x4000) == 0) || ((cdimm_master_power_intercept & 0x4000) == 0)) || (((cdimm_supplier_power_slope & 0x4000) == 0) || ((cdimm_supplier_power_intercept & 0x4000) == 0)))
 			    {
-				l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.lrdimm;
+//TODO:  enable error reporting for this when it makes sense to do (after ship level power curve data is known), remove warning message.  Log error and allow IPL to continue and use the lab data if it is there.
+				FAPI_INF("WARNING:  power curve data is lab data, not ship level data");
+//				FAPI_ERR("power curve data is lab data, not ship level data");
+//				FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_POWER_CURVE_DATA_LAB);
+//				if (rc) fapiLogError(rc);
 			    }
-			    else if (l_dimm_type == CDIMM)
-			    {
-				l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.cdimm;
-			    }
-			    else if ( l_dimm_type == RDIMM )
-			    {
-				l_dimm_power_adder_type = l_power_table[entry].dimm_type_adder.rdimm;
-			    }
-			    else
-			    {
-				FAPI_ERR("UNKNOWN DIMM TYPE FOUND:  ldimm_type");
-				l_dimm_power_adder_type = 0;
-			    }
-// TODO:  Use attribute for number of registers for RDIMM when available - via SPD byte 63 bits 1:0
-// TODO:  Remove the double uplift below when SPD byte 63 is used
-			    // double the uplift for additional register if dimm has more than 2 ranks
-			    if ((l_dimm_master_ranks_array[port][dimm] > 2) && (l_dram_width == X4) && ((l_dimm_type == LRDIMM) || (l_dimm_type == RDIMM)))
+			}
+			else
+			{
+			    power_slope_array[port][dimm] = CDIMM_POWER_SLOPE_DEFAULT;
+			    power_int_array[port][dimm] = CDIMM_POWER_INT_DEFAULT;
+			    power_slope2_array[port][dimm] = CDIMM_POWER_SLOPE_DEFAULT;
+			    power_int2_array[port][dimm] = CDIMM_POWER_INT_DEFAULT;
+			    FAPI_ERR("power curve data not valid, use default values");
+			    FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID);
+			    if (rc) fapiLogError(rc);
+			}
+
+			FAPI_INF("CDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
+		    }
+// ISDIMM power slope/intercept will come from equation
+		    else
+		    {
+// Get the dimm power from table and add on any adjustments (if not found in table - should never happen - then default values will be used)
+			power_slope_array[port][dimm] = ISDIMM_POWER_SLOPE_DEFAULT;
+			power_int_array[port][dimm] = ISDIMM_POWER_INT_DEFAULT;
+
+			found_entry_in_table = 0;
+			for (entry = 0; entry < power_table_size; entry++)
+			{
+			    if ((power_table[entry].dram_generation == dram_gen) && (power_table[entry].dram_width == dram_width) && ((power_table[entry].dimm_ranks == dimm_master_ranks_array[port][dimm]) || (power_table[entry].dimm_ranks == 1)))
 			    {
-				l_dimm_power_adder_type = l_dimm_power_adder_type * 2;
-			    }
+// get adder for dimm type
+				if (dimm_type == UDIMM)
+				{
+				    dimm_power_adder_type = power_table[entry].dimm_type_adder.udimm;
+				}
+				else if (dimm_type == LRDIMM)
+				{
+				    dimm_power_adder_type = power_table[entry].dimm_type_adder.lrdimm;
+				}
+				else // RDIMM
+				{
+				    dimm_power_adder_type = power_table[entry].dimm_type_adder.rdimm;
+				}
+
+
+				if (dimm_type == RDIMM) {
+				    dimm_power_adder_type = dimm_power_adder_type * dimm_number_registers[port][dimm];
+				}
+
 // get adder for dimm voltage
-			    if (l_dimm_voltage == 1200)
-			    {
-				l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1200;
-			    }
-			    else if (l_dimm_voltage == 1350)
-			    {
-				l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1350;
-			    }
-			    else if (l_dimm_voltage == 1500)
-			    {
-				l_dimm_power_adder_volt = l_power_table[entry].dimm_voltage_adder.volt1500;
-			    }
-			    else
-			    {
-				FAPI_ERR("UNKNOWN DIMM VOLTAGE FOUND:  l_dimm_voltage");
-				l_dimm_power_adder_volt = 0;
-			    }
+				dimm_power_multiplier_volt = ((float(dimm_voltage) / power_table[entry].dimm_voltage_base) * (float(dimm_voltage) / power_table[entry].dimm_voltage_base));
 // get adder for dimm frequency
-			    if (l_dimm_frequency == 1066)
-			    {
-				l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1066;
-			    }
-			    else if (l_dimm_frequency == 1333)
-			    {
-				l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1333;
-			    }
-			    else if (l_dimm_frequency == 1600)
-			    {
-				l_dimm_power_adder_freq = l_power_table[entry].dimm_frequency_adder.freq1600;
-			    }
-			    else
-			    {
-				FAPI_ERR("UNKNOWN DIMM FREQ FOUND:  l_dimm_frequency");
-				l_dimm_power_adder_freq = 0;
-			    }
-// get adder for slave ranks
-			    l_dimm_num_slave_ranks=l_dimm_ranks_array[port][dimm] - l_dimm_master_ranks_array[port][dimm];
-			    if (l_dimm_num_slave_ranks > 0)
-			    {
-				l_dimm_idle_power_adder_slave = l_power_table[entry].rank_slave_adder.idle * l_dimm_num_slave_ranks;
-				l_dimm_max_power_adder_slave = l_dimm_idle_power_adder_slave + (l_power_table[entry].rank_slave_adder.max - l_power_table[entry].rank_slave_adder.idle);
-			    }
-			    else
-			    {
-				l_dimm_idle_power_adder_slave = 0;
-				l_dimm_max_power_adder_slave = 0;
+				dimm_power_mulitiplier_freq = (float(dimm_frequency) / power_table[entry].dimm_frequency_base);
+// get adder for termination using equation (in cW)
+				dimm_power_adder_termination = dimm_power_adder_termination_largest * 100;
+				dimm_power_adder_termination_wc = dimm_power_adder_termination_largest_wc * 100;
+// add up power for each dimm on channel and divide by number of dimms to get an average power for each dimm
+// calculate idle and active dimm power (active power includes worst case termination power)
+				dimm_idle_power = ((float(((power_table[entry].rank_power.idle * (dimm_master_ranks_array[port][dimm] + (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm])) + dimm_power_adder_type) * (dimm_power_multiplier_volt) * (dimm_power_mulitiplier_freq)) * num_dimms_on_port) / (num_dimms_on_port)));
+				dimm_active_power = ((float((((power_table[entry].rank_power.idle * (dimm_master_ranks_array[port][dimm] + (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm])) + (power_table[entry].rank_power.active - power_table[entry].rank_power.idle)) + dimm_power_adder_type) * (dimm_power_multiplier_volt) * (dimm_power_mulitiplier_freq)) * num_dimms_on_port - (power_table[entry].rank_power.active - power_table[entry].rank_power.idle) * (num_dimms_on_port - 1) + dimm_power_adder_termination + (dimm_power_adder_termination_wc - dimm_power_adder_termination)) / (num_dimms_on_port)));
+// calculate dimm power slope and intercept (add on 0.5 so value is effectively rounded to nearest integer)
+				power_slope_array[port][dimm] = int((dimm_active_power - dimm_idle_power) / (float(ACTIVE_DIMM_UTILIZATION - IDLE_DIMM_UTILIZATION) / 100) + 0.5);
+				power_int_array[port][dimm] = int(dimm_idle_power + 0.5);
+				power_slope2_array[port][dimm] = power_slope_array[port][dimm];
+				power_int2_array[port][dimm] = power_int_array[port][dimm];
+				if (power_table[entry].dram_generation == DDR3)
+				{
+				    sprintf(dram_gen_str, "DDR3");
+				}
+				if (power_table[entry].dram_generation == DDR4)
+				{
+				    sprintf(dram_gen_str, "DDR4");
+				}
+
+				found_entry_in_table = 1;
+				FAPI_DBG("FOUND ENTRY:  GEN=%s WIDTH=X%d RANK=%d IDLE(%d%%)=%d ACTIVE(%d%%)=%d ADDER[TYPE=%d WCTERM=%4.2f] Multiplier[VOLT=%4.2f FREQ=%4.2f]", dram_gen_str, power_table[entry].dram_width, power_table[entry].dimm_ranks, IDLE_DIMM_UTILIZATION, power_table[entry].rank_power.idle, ACTIVE_DIMM_UTILIZATION, power_table[entry].rank_power.active, dimm_power_adder_type, dimm_power_adder_termination_wc, dimm_power_multiplier_volt, dimm_power_mulitiplier_freq);
+				FAPI_DBG("ISDIMM Power [P%d:D%d][%s:X%d:R%d/%d:%d:%d][IDLE(%d%%)=%4.2f:ACTIVE(%d%%)=%4.2f cW][SLOPE=%d:INT=%d cW]", port, dimm, dram_gen_str, power_table[entry].dram_width, dimm_master_ranks_array[port][dimm], (dimm_ranks_array[port][dimm] - dimm_master_ranks_array[port][dimm]), dimm_voltage, dimm_frequency, IDLE_DIMM_UTILIZATION, dimm_idle_power, ACTIVE_DIMM_UTILIZATION, dimm_active_power, power_slope_array[port][dimm], power_int_array[port][dimm]);
+				FAPI_INF("ISDIMM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
+				break;
 			    }
-// get adder for termination using equation
-// TODO:  Need to add this in once equations are available for termination adder
-
-// calculate idle and max dimm power
-			    l_dimm_idle_power = int((l_power_table[entry].rank_master_power.idle * l_dimm_master_ranks_array[port][dimm] + l_dimm_power_adder_type + l_dimm_idle_power_adder_slave) * (1 + float(l_dimm_power_adder_volt + l_dimm_power_adder_freq) / 100));
-			    l_dimm_max_power = int(((l_power_table[entry].rank_master_power.idle * l_dimm_master_ranks_array[port][dimm] + l_power_table[entry].rank_master_power.max - l_power_table[entry].rank_master_power.idle) + l_dimm_power_adder_type + l_dimm_max_power_adder_slave) * (1 + float(l_dimm_power_adder_volt + l_dimm_power_adder_freq) / 100));
-// caculcate dimm power slope and intercept
-			    l_power_slope_array[port][dimm] = int((l_dimm_max_power - l_dimm_idle_power) / (float(l_max_dimm_utilization - l_idle_dimm_utilization) / 100));
-			    l_power_int_array[port][dimm] = l_dimm_idle_power;
-
-			    l_found_entry_in_table = 1;
-			    FAPI_INF("FOUND ENTRY:  GEN=%d WIDTH=%d RANK=%d IDLE=%d MAX=%d ADDER[SLAVE_IDLE=%d SLAVE_MAX=%d TYPE=%d VOLT=%d FREQ=%d]", l_power_table[entry].dram_generation, l_power_table[entry].dram_width, l_power_table[entry].dimm_ranks, l_power_table[entry].rank_master_power.idle, l_power_table[entry].rank_master_power.max, l_power_table[entry].rank_slave_adder.idle, l_power_table[entry].rank_slave_adder.max, l_dimm_power_adder_type, l_dimm_power_adder_volt, l_dimm_power_adder_freq);
-			    FAPI_INF("DIMM Power Calculated [P%d:D%d:R%d/%d][IDLE=%d:MAX=%d cW][SLOPE=%d:INT=%d cW]", port, dimm, l_dimm_master_ranks_array[port][dimm], l_dimm_num_slave_ranks, l_dimm_idle_power, l_dimm_max_power, l_power_slope_array[port][dimm], l_power_int_array[port][dimm]);
-			    break;
+
+			}
+			if (found_entry_in_table == 0)
+			{
+			    FAPI_ERR( "Failed to Find DIMM Power Values on %s.  Default values will be used [P%d:D%d][Slope=%d:INT=%d cW]", i_target_mba.toEcmdString(), port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm] );
+			    FAPI_SET_HWP_ERROR(rc, RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE);
+			    if (rc) fapiLogError(rc);
 			}
+		    }
+		}
+	    }
+	}
+
+// write output attributes
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE, &i_target_mba, power_slope_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT, &i_target_mba, power_int_array);
+	if(rc) return rc;
+
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE2, &i_target_mba, power_slope2_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT2, &i_target_mba, power_int2_array);
+	if(rc) return rc;
+
+
+////////////////////////////////////////////////////////////////////////
+// Memory Throttle Determination
+////////////////////////////////////////////////////////////////////////
+
+// Runtime throttles will be non-volatile, so don't recalculate them if they have already been set
 
+// TODO:  remove this section when firmware initializes attributes to zero AND runtime throttles are non-volatile
+	runtime_throttle_n_per_mba = 0;
+	runtime_throttle_n_per_chip = 0;
+	runtime_throttle_d = 0;
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
+	if(rc) return rc;
+
+// Get the runtime throttle attributes here
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
+	if(rc) return rc;
+// check to see if runtime throttles are all zero here
+	if ((runtime_throttle_n_per_mba == 0) && (runtime_throttle_n_per_chip == 0) && (runtime_throttle_d == 0))
+	{
+// Values have not been initialized, so get them initialized
+
+// Determine the thermal power limit to use, which represents a single channel pair power limit for the dimms on that channel pair (ie.  power for all dimms attached to one MBA).   The procedure mss_bulk_power_throttles takes the input of channel pair power to determine throttles.
+// CDIMM thermal power limit from MRW is per CDIMM, so divide by number of mbas that have dimms to get channel pair power
+// CDIMM:  Allow all commands to be directed toward one MBA to achieve the power limit
+//   This means that the power limit for a MBA channel pair must be the total CDIMM power limit minus the idle power of the other MBAs logical dimms
+	    if (dimm_type == CDIMM)
+	    {
+		channel_pair_thermal_power_limit = dimm_thermal_power_limit / num_mba_with_dimms;
+	    }
+// ISDIMMs thermal power limit from MRW is per DIMM, so multiply by number of dimms on channel to get channel power and multiply by 2 to get channel pair power
+	    else
+	    {
+		// ISDIMMs
+		channel_pair_thermal_power_limit = dimm_thermal_power_limit * num_dimms_on_port * 2;
+	    }
+
+// Update the channel pair power limit attribute
+	    rc = FAPI_ATTR_SET(ATTR_MSS_MEM_WATT_TARGET, &i_target_mba, channel_pair_thermal_power_limit);
+	    if(rc) return rc;
+
+// Call the procedure function that takes a channel pair power limit and converts it to throttle values
+
+	    FAPI_EXEC_HWP(rc, mss_bulk_pwr_throttles, i_target_mba);
+	    if (rc)
+	    {
+		FAPI_ERR("Error (0x%x) calling mss_bulk_pwr_throttles", static_cast<uint32_t>(rc));
+		return rc;
+	    }
+
+// Read back in the updated throttle attribute values (these are now set to values that will give dimm/channel power underneath the thermal power limit)
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
+	    if(rc) return rc;
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
+	    if(rc) return rc;
+	    rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
+	    if(rc) return rc;
+
+// update output attributes
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, runtime_throttle_n_per_mba);
+	    if(rc) return rc;
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, runtime_throttle_n_per_chip);
+	    if(rc) return rc;
+	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR, &i_target_mba, runtime_throttle_d);
+	    if(rc) return rc;
+
+	}
+
+// Initialize the generic throttle attributes to safemode throttles (since the IPL will be done at the safemode throttles)
+	throttle_n_per_mba = safemode_throttle_n_per_mba;
+	throttle_n_per_chip = safemode_throttle_n_per_chip;
+	throttle_d = safemode_throttle_d;
+
+// write output attributes
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
+	if(rc) return rc;
+
+	FAPI_INF("*** %s COMPLETE ***", procedure_name);
+	return rc;
+    }
+
+//------------------------------------------------------------------------------
+// @brief mss_eff_config_thermal_term(): This function calculates the data bus termination power
+//
+// @param    const char i_nom_or_wc_term[4]:  description of what is being calculated (ie.  NOM or WC)
+// @param    uint8_t i_port:  MBA port being worked on
+// @param    uint8_t i_dimm:  DIMM being worked on
+// @param    uint8_t i_rank:  Rank being worked on
+// @param    uint32_t i_dimm_voltage:  DIMM Voltage
+// @param    uint8_t i_dram_width:  DRAM Width
+// @param    uint8_t i_dram_tdqs:  DRAM TDQS enable/disable
+// @param    uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS]:  IBM bus topology type
+// @param    uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS]:  Master Ranks configured
+// @param    uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS]:  DRAM RON driver impedance
+// @param    uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  Read ODT
+// @param    uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  Write ODT
+// @param    uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM RTT NOM
+// @param    uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS]:  DRAM RTT WR
+// @param    uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS]:  Centaur DQ/DQS receiver impedance
+// @param    uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS]:  Centaur DQ/DQS driver impedance
+// @param    float &o_dimm_power_adder_termination:  Termination Power Calculated in Watts
+
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_eff_config_thermal_term(
+						 const char i_nom_or_wc_term[4],
+						 uint8_t i_port,
+						 uint8_t i_dimm,
+						 uint8_t i_rank,
+						 uint32_t i_dimm_voltage,
+						 uint8_t i_dram_width,
+						 uint8_t i_dram_tdqs,
+						 uint8_t i_ibm_type[NUM_PORTS][NUM_DIMMS],
+						 uint8_t i_dimm_ranks_configed_array[NUM_PORTS][NUM_DIMMS],
+						 uint8_t i_dimm_dram_ron[NUM_PORTS][NUM_DIMMS],
+						 uint8_t i_dimm_rank_odt_rd[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						 uint8_t i_dimm_rank_odt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						 uint8_t i_dram_rtt_nom[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						 uint8_t i_dram_rtt_wr[NUM_PORTS][NUM_DIMMS][NUM_RANKS],
+						 uint8_t i_cen_dq_dqs_rcv_imp[NUM_PORTS],
+						 uint8_t i_cen_dq_dqs_drv_imp[NUM_PORTS],
+						 float &o_dimm_power_adder_termination
+						 )
+    {
+
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+	uint8_t number_nets_term_rd;
+	uint8_t number_nets_term_wr;
+	uint8_t ma0odt01_dimm;
+	uint8_t ma1odt01_dimm;
+	uint8_t ma0odt0_rank;
+	uint8_t ma0odt1_rank;
+	uint8_t ma1odt0_rank;
+	uint8_t ma1odt1_rank;
+	uint8_t rank_mask;
+	float eff_term_rd;
+	float eff_net_term_rd;
+	float term_odt_mult_rd;
+	float eff_term_wr;
+	float eff_net_term_wr;
+	float term_odt_mult_wr;
+	uint8_t cen_dq_dqs_drv_imp_value;
+
+// Get number of nets that will have termination applied from ODT (DQ,DQS,DM,TDQS)
+// number of nets for DQ (9 DRAMs x 8 bits each, or 18 DRAMs x 4 bits each = 72)
+	number_nets_term_rd = 72;
+	number_nets_term_wr = 72;
+// add in number of nets for DQS + DM + TDQS (TDQS only supported for X8, DM only used for writes)
+	if (i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
+	{
+	    number_nets_term_rd = number_nets_term_rd + 36 + 0 + 0;
+	    number_nets_term_wr = number_nets_term_wr + 36 + 0 + 0;
+	}
+	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE))
+	{
+	    number_nets_term_rd = number_nets_term_rd + 18 + 0 + 0;
+	    number_nets_term_wr = number_nets_term_wr + 18 + 9 + 0;
+	}
+	else if ((i_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (i_dram_tdqs == fapi::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE))
+	{
+	    number_nets_term_rd = number_nets_term_rd + 18 + 0 + 18;
+	    number_nets_term_wr = number_nets_term_wr + 18 + 0 + 18;
+	}
+
+// which rank is mapped to the [01]ODT[01] nets, from centaur spec, every type uses Ranks 0,1,4,5, with the following exceptions
+// Type 1D used Ranks 0,2,4,6 in that order (0_ODT0,0_ODT1,1_ODT0,1_ODT1)
+// expect that EFF_ODT_RD and EFF_ODT_WR will be setup correctly so we just need to add up any termination in parallel for the bits set in these attributes
+// Also need to consider if ODT is tied high for writes (if rtt_wr is set for the rank being written to, then it will be assumed that ODT is tied high)
+
+	if (i_ibm_type[i_port][i_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D)
+	{
+	    ma0odt01_dimm = 0;
+	    ma1odt01_dimm = 1;
+	    ma0odt0_rank = 0;
+	    ma0odt1_rank = 2;
+	    ma1odt0_rank = 0;
+	    ma1odt1_rank = 2;
+	}
+	else
+	{
+	    ma0odt01_dimm = 0;
+	    ma1odt01_dimm = 1;
+	    ma0odt0_rank = 0;
+	    ma0odt1_rank = 1;
+	    ma1odt0_rank = 0;
+	    ma1odt1_rank = 1;
+	}
+
+// check to see if rank is configured, only get termination power for these ranks
+	rank_mask = 0x00;
+	if (i_rank == 0)
+	{
+	    rank_mask = 0x80;
+	}
+	else if (i_rank == 1)
+	{
+	    rank_mask = 0x40;
+	}
+	else if (i_rank == 2)
+	{
+	    rank_mask = 0x20;
+	}
+	else if (i_rank == 3)
+	{
+	    rank_mask = 0x10;
+	}
+	if ((i_dimm_ranks_configed_array[i_port][i_dimm] & rank_mask) != 0)
+	{
+// effective net termination = [(active termination in parallel || driver impedance) + active termination in parallel]
+
+
+
+////////////////////////////////////////////////
+// calculate out effective termination for reads
+////////////////////////////////////////////////
+	    eff_term_rd = 0;
+
+// 0ODT0
+	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x80) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    {
+		if (eff_term_rd == 0)
+		{
+		    eff_term_rd = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
+		}
+		else
+		{
+		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 0ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
+
+	    }
+// 0ODT1
+	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x40) != 0) && (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    {
+		if (eff_term_rd == 0)
+		{
+		    eff_term_rd = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
+		}
+		else
+		{
+		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 0ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
+	    }
+// 1ODT0
+	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x20) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    {
+		if (eff_term_rd == 0)
+		{
+		    eff_term_rd = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
+		}
+		else
+		{
+		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 1ODT0 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
+	    }
+// 1ODT1
+	    if (((i_dimm_rank_odt_rd[i_port][i_dimm][i_rank] & 0x10) != 0) && (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE))
+	    {
+		if (eff_term_rd == 0)
+		{
+		    eff_term_rd = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
+		}
+		else
+		{
+		    eff_term_rd = (eff_term_rd * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_rd + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 1ODT1 RD TERMINATION = %4.2f (%d)", i_port, i_dimm, i_rank, eff_term_rd, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
+	    }
+		// calculate out effective read termination
+	    if (eff_term_rd != 0)
+	    {
+		eff_net_term_rd = (float((float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port])) * i_dimm_dram_ron[i_port][i_dimm]) / ((float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port])) + i_dimm_dram_ron[i_port][i_dimm])) + (float(eff_term_rd * i_cen_dq_dqs_rcv_imp[i_port]) / (eff_term_rd + i_cen_dq_dqs_rcv_imp[i_port]));
+		term_odt_mult_rd = 1.25;
+	    }
+	    else
+	    {
+		eff_net_term_rd = (float((i_cen_dq_dqs_rcv_imp[i_port]) * i_dimm_dram_ron[i_port][i_dimm]) / ((i_cen_dq_dqs_rcv_imp[i_port]) + i_dimm_dram_ron[i_port][i_dimm])) + (i_cen_dq_dqs_rcv_imp[i_port]);
+		term_odt_mult_rd = 1;
+	    }
+// writes
+/////////////////////////////////////////////////
+// calculate out effective termination for writes
+/////////////////////////////////////////////////
+	    eff_term_wr = 0;
+
+// check to see if ODT is tied high (rank is not one of the ranks that get ODT driven to it, and rtt_wr or rtt_nom are enabled)
+	    if (((((i_rank != ma0odt0_rank) && (i_rank != ma0odt1_rank)) && (i_dimm == 0)) || (((i_rank != ma1odt0_rank) && (i_rank != ma1odt1_rank)) && (i_dimm == 1))) && ((i_dram_rtt_wr[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    {
+		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
+		if (i_dram_rtt_wr[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_wr[i_port][i_dimm][i_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][i_dimm][i_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][i_dimm][i_rank]);
+		    }
+		}
+		// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][i_dimm][i_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_nom[i_port][i_dimm][i_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][i_dimm][i_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][i_dimm][i_rank]);
+		    }
+
+		}
+		FAPI_DBG("[P%d:D%d:R%d] WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_wr[i_port][i_dimm][i_rank], i_dram_rtt_nom[i_port][i_dimm][i_rank]);
+	    }
+/// 0ODT0
+	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x80) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    {
+		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
+		if ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt0_rank))
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]);
+		    }
+		}
+		// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank]);
+		    }
+
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 0ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt0_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt0_rank]);
+	    }
+// 0ODT1
+	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x40) != 0) && ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    {
+		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
+		if ((i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 0) && (i_rank == ma0odt1_rank))
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]);
+		    }
+		}
+		// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank];
 		    }
-		    if (l_found_entry_in_table == 0)
+		    else
 		    {
-			FAPI_ERR( "WARNING:  Failed to Find DIMM Power Values, so default values will be used [%d:%d][%d:%d]", port, dimm, l_power_slope_array[port][dimm], l_power_int_array[port][dimm] );
+			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank]);
+		    }
+
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 0ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma0odt01_dimm][ma0odt1_rank], i_dram_rtt_wr[i_port][ma0odt01_dimm][ma0odt1_rank]);
+	    }
+// 1ODT0
+	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x20) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    {
+		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
+		if ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt0_rank))
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]);
+		    }
+		}
+		// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank]);
+		    }
+
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 1ODT0 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt0_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt0_rank]);
+	    }
+// 1ODT1
+	    if (((i_dimm_rank_odt_wr[i_port][i_dimm][i_rank] & 0x10) != 0) && ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) || (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)))
+	    {
+		// dynamic ODT enabled, so use rtt_wr (only if the rank being written to has it enabled)
+		if ((i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_WR_DISABLE) && (i_dimm == 1) && (i_rank == ma1odt1_rank))
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_wr + i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]);
 		    }
 		}
+		// dynamic ODT disabled, so use rtt_nom
+		else if (i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank] != fapi::ENUM_ATTR_EFF_DRAM_RTT_NOM_DISABLE)
+		{
+		    if (eff_term_wr == 0)
+		    {
+			eff_term_wr = i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank];
+		    }
+		    else
+		    {
+			eff_term_wr = (eff_term_wr * i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]) / (eff_term_wr + i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank]);
+		    }
+
+		}
+		FAPI_DBG("[P%d:D%d:R%d] 1ODT1 WR TERMINATION = %4.2f (%d/%d)", i_port, i_dimm, i_rank, eff_term_wr, i_dram_rtt_nom[i_port][ma1odt01_dimm][ma1odt1_rank], i_dram_rtt_wr[i_port][ma1odt01_dimm][ma1odt1_rank]);
+	    }
+
+// Translate enum value to a resistance value for i_cen_dq_dqs_drv_imp[i_port]
+	    rc = mss_eff_config_thermal_get_cen_drv_value(
+							  i_cen_dq_dqs_drv_imp[i_port],
+							  cen_dq_dqs_drv_imp_value
+							  );
+	    if(rc)
+	    {
+		FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_get_cen_drv_value", static_cast<uint32_t>(rc));
+		return rc;
+	    }
+
+	    if (eff_term_wr != 0)
+	    {
+		eff_net_term_wr = (float(eff_term_wr * cen_dq_dqs_drv_imp_value) / (eff_term_wr + cen_dq_dqs_drv_imp_value)) + eff_term_wr;
+		term_odt_mult_wr = 1.25;
+	    }
+	    else
+	    {
+		eff_net_term_wr = cen_dq_dqs_drv_imp_value;
+		term_odt_mult_wr = 1;
+	    }
+
+// From Warren:
+// Termination power = (voltage/net termination) * number of nets * (% of traffic on bus*1.25)
+// The net termination is the effective termination that exists between the power rail and ground. So in my calculations this is all the active termination in parallel with the driver impedance + all the active termination in parallel. The value is different for reads and writes. 
+// Number of nets includes the strobe nets (2 nets per strobe)
+// % of traffic on bus is the % of the bus used for data traffic split out from reads and writes. The 1.25 factor is due to the odt_en signals being active longer then the data windows.
+// Value here is in Watts (W)
+	    o_dimm_power_adder_termination = float(i_dimm_voltage) / 1000 * (((float(i_dimm_voltage) / 1000 / eff_net_term_rd) * (number_nets_term_rd) * (float(ACTIVE_DIMM_UTILIZATION) / 100) * (float(DATA_BUS_READ_PERCENT) / 100) * (term_odt_mult_rd)) + ((float(i_dimm_voltage) / 1000 / eff_net_term_wr) * (number_nets_term_wr) * (float(ACTIVE_DIMM_UTILIZATION) / 100) * (float(DATA_BUS_WRITE_PERCENT) / 100) * (term_odt_mult_wr)));
+	    FAPI_DBG("%s TERM:[P%d:D%d:R%d] CEN[DRV=%d RCV=%d] DRAM[DRV=%d ODT_RD=%4.2f ODT_WR=%4.2f]", i_nom_or_wc_term, i_port, i_dimm, i_rank, cen_dq_dqs_drv_imp_value, i_cen_dq_dqs_rcv_imp[i_port], i_dimm_dram_ron[i_port][i_dimm], eff_term_rd, eff_term_wr);
+	    FAPI_DBG("%s TERM POWER:[P%d:D%d:R%d] RD[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] WR[Nets=%d EffTerm=%3.2f ODTMult=%1.2f] TermPower(%d%%)=%2.2f W", i_nom_or_wc_term, i_port, i_dimm, i_rank, number_nets_term_rd, eff_net_term_rd, term_odt_mult_rd, number_nets_term_wr, eff_net_term_wr, term_odt_mult_wr, ACTIVE_DIMM_UTILIZATION, o_dimm_power_adder_termination);
+	}	
+
+	return rc;
+    }
+
+//------------------------------------------------------------------------------
+// @brief mss_eff_config_thermal_get_wc_term(): This function finds the worst case termination settings possible for a given set
+//           of termination settings
+//
+// @param    const fapi::Target &i_target_mba:  MBA Target
+// @param    uint8_t i_port:  MBA port being worked on
+// @param    uint8_t &o_cen_dq_dqs_rcv_imp_wc:  Worst Case Centaur DQ/DQS receiver impedance (output)
+// @param    uint8_t &o_cen_dq_dqs_drv_imp_wc:  Worst Case Centaur DQ/DQS driver impedance (output)
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_eff_config_thermal_get_wc_term(
+							const fapi::Target &i_target_mba,
+							uint8_t i_port,
+							uint8_t &o_cen_dq_dqs_rcv_imp_wc,
+							uint8_t &o_cen_dq_dqs_drv_imp_wc
+							)
+    {
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+
+	uint8_t l_cen_dq_dqs_rcv_imp[NUM_PORTS];
+	uint8_t l_cen_dq_dqs_drv_imp[NUM_PORTS];
+	uint32_t l_cen_dq_dqs_rcv_imp_schmoo[NUM_PORTS];
+	uint32_t l_cen_dq_dqs_drv_imp_schmoo[NUM_PORTS];
+	uint32_t l_loop;
+	uint32_t l_schmoo_mask;
+
+// This lists out the number and enum values for the centaur dq/dqs receiver and driver impedance.  Have the list go from strongest to weakest termination.
+// If the size changes at all, then updates are needed below to get the correct mask
+
+	const uint8_t MAX_CEN_RCV_IMP = 10;
+	uint8_t cen_rcv_imp_array[] = {
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160,
+	    fapi::ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240
+	}; 
+
+	const uint8_t MAX_CEN_DRV_IMP = 16;
+	uint8_t cen_drv_imp_array[] = {
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160,
+	    fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120
+	};
+
+// Get attributes for nominal settings and possible settings to choose from
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_cen_dq_dqs_rcv_imp);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_cen_dq_dqs_drv_imp);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_cen_dq_dqs_rcv_imp_schmoo);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_cen_dq_dqs_drv_imp_schmoo);
+	if(rc) return rc;
+
+// initialize to default values in case below does not find a match
+	o_cen_dq_dqs_rcv_imp_wc = l_cen_dq_dqs_rcv_imp[i_port];
+	o_cen_dq_dqs_drv_imp_wc = l_cen_dq_dqs_drv_imp[i_port];
+
+// find strongest termination setting that could be used, if none found, then use nominal
+	l_schmoo_mask = 0x00000000;
+	for (l_loop=0; l_loop < MAX_CEN_RCV_IMP; l_loop++)
+	{
+	    switch (l_loop)
+	    {
+		case 0:
+		    l_schmoo_mask = 0x80000000;
+		    break;
+		case 1:
+		    l_schmoo_mask = 0x40000000;
+		    break;
+		case 2:
+		    l_schmoo_mask = 0x20000000;
+		    break;
+		case 3:
+		    l_schmoo_mask = 0x10000000;
+		    break;
+		case 4:
+		    l_schmoo_mask = 0x08000000;
+		    break;
+		case 5:
+		    l_schmoo_mask = 0x04000000;
+		    break;
+		case 6:
+		    l_schmoo_mask = 0x02000000;
+		    break;
+		case 7:
+		    l_schmoo_mask = 0x01000000;
+		    break;
+		case 8:
+		    l_schmoo_mask = 0x00800000;
+		    break;
+		case 9:
+		    l_schmoo_mask = 0x00400000;
+		    break;
+		default:
+		    o_cen_dq_dqs_rcv_imp_wc = l_cen_dq_dqs_rcv_imp[i_port];
+	    }
+	    if ((l_cen_dq_dqs_rcv_imp_schmoo[i_port] & l_schmoo_mask) != 0)
+	    {
+		o_cen_dq_dqs_rcv_imp_wc = cen_rcv_imp_array[l_loop];
+		break;
 	    }
 	}
 
-// write output attributes
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE, &i_target, l_power_slope_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT, &i_target, l_power_int_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_NUMERATOR, &i_target, l_dimm_throttle_n_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_DENOMINATOR, &i_target, l_dimm_throttle_d_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR, &i_target, l_channel_throttle_n_array);
-	if(l_rc) return l_rc;
-	l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR, &i_target, l_channel_throttle_d_array);
-	if(l_rc) return l_rc;
+	l_schmoo_mask = 0x00000000;
+	for (l_loop=0; l_loop < MAX_CEN_DRV_IMP; l_loop++)
+	{
+	    switch (l_loop)
+	    {
+		case 0:
+		    l_schmoo_mask = 0x80000000;
+		    break;
+		case 1:
+		    l_schmoo_mask = 0x40000000;
+		    break;
+		case 2:
+		    l_schmoo_mask = 0x20000000;
+		    break;
+		case 3:
+		    l_schmoo_mask = 0x10000000;
+		    break;
+		case 4:
+		    l_schmoo_mask = 0x08000000;
+		    break;
+		case 5:
+		    l_schmoo_mask = 0x04000000;
+		    break;
+		case 6:
+		    l_schmoo_mask = 0x02000000;
+		    break;
+		case 7:
+		    l_schmoo_mask = 0x01000000;
+		    break;
+		case 8:
+		    l_schmoo_mask = 0x00800000;
+		    break;
+		case 9:
+		    l_schmoo_mask = 0x00400000;
+		    break;
+		case 10:
+		    l_schmoo_mask = 0x00200000;
+		    break;
+		case 11:
+		    l_schmoo_mask = 0x00100000;
+		    break;
+		case 12:
+		    l_schmoo_mask = 0x00080000;
+		    break;
+		case 13:
+		    l_schmoo_mask = 0x00040000;
+		    break;
+		case 14:
+		    l_schmoo_mask = 0x00020000;
+		    break;
+		case 15:
+		    l_schmoo_mask = 0x00010000;
+		    break;
+		default:
+		    o_cen_dq_dqs_drv_imp_wc = l_cen_dq_dqs_drv_imp[i_port];
+	    }
+	    if ((l_cen_dq_dqs_drv_imp_schmoo[i_port] & l_schmoo_mask) != 0)
+	    {
+		o_cen_dq_dqs_drv_imp_wc = cen_drv_imp_array[l_loop];
+		break;
+	    }
+	}
 
-	FAPI_INF("*** %s COMPLETE ***", procedure_name);
-	return l_rc;
+	return rc;
     }
 
+
+//------------------------------------------------------------------------------
+// @brief mss_eff_config_thermal_get_cen_drv_value(): This function will translate
+//           the centaur driver impedance enum value to a termination resistance
+//
+// @param    uint8_t &i_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance enum setting (input)
+// @param    uint8_t &o_cen_dq_dqs_drv_imp:  Centaur DQ/DQS driver impedance value (output)
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_eff_config_thermal_get_cen_drv_value(
+							      uint8_t i_cen_dq_dqs_drv_imp,
+							      uint8_t &o_cen_dq_dqs_drv_imp
+							      )
+    {
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+
+	switch (i_cen_dq_dqs_drv_imp)
+	{
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0:
+		o_cen_dq_dqs_drv_imp = 24;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0:
+		o_cen_dq_dqs_drv_imp = 30;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480:
+		o_cen_dq_dqs_drv_imp = 30;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240:
+		o_cen_dq_dqs_drv_imp = 30;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160:
+		o_cen_dq_dqs_drv_imp = 30;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120:
+		o_cen_dq_dqs_drv_imp = 30;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0:
+		o_cen_dq_dqs_drv_imp = 34;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480:
+		o_cen_dq_dqs_drv_imp = 34;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240:
+		o_cen_dq_dqs_drv_imp = 34;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160:
+		o_cen_dq_dqs_drv_imp = 34;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120:
+		o_cen_dq_dqs_drv_imp = 34;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0:
+		o_cen_dq_dqs_drv_imp = 40;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480:
+		o_cen_dq_dqs_drv_imp = 40;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240:
+		o_cen_dq_dqs_drv_imp = 40;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160:
+		o_cen_dq_dqs_drv_imp = 40;
+		break;
+	    case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120:
+		o_cen_dq_dqs_drv_imp = 40;
+		break;
+	    default:
+		o_cen_dq_dqs_drv_imp = 24;
+	}
+
+	return rc;
+    }
+
+
 } //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
index 0e5e395cf..f4d7c7861 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.H,v 1.3 2012/04/03 22:13:03 pardeik Exp $
+// $Id: mss_eff_config_thermal.H,v 1.4 2012/10/15 13:05:10 pardeik Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -42,6 +42,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.4   | pardeik  |11-OCT-12| change i_target to i_target_mba
 //   1.3   | pardeik  |03-APR-12| use mba target instead of mbs
 //   1.2   | pardeik  |26-MAR-12| Removed structure (going into .C file)
 //         | pardeik  |01-DEC-11| Added structures and defines
@@ -58,19 +59,19 @@
 #include <fapi.H>
 
 
-typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)(const fapi::Target & i_target);
+typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)(const fapi::Target & i_target_mba);
 
 
 extern "C" {
 /**
  * @brief mss_eff_config_thermal procedure. Sets up dimm power curve attributes and dimm and channel throttle attributes
  *
- * @param[in]  i_target  Reference to centaur mba target
+ * @param[in]  i_target_mba  Reference to centaur mba target
  *
  * @return ReturnCode
  */
 
-    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target);
+    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba);
 
 } //extern C
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
index 66566da3e..48c356339 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_grouping.C,v 1.10 2012/09/27 11:11:53 bellows Exp $
+// $Id: mss_eff_grouping.C,v 1.16 2012/12/14 08:41:20 gpaulraj Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -38,6 +38,11 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.16   | gpaulraj | 12-14-12| Modified "unable to group dimm size" as Error message
+//  1.15   | bellows  | 12-11-12| Picked up latest updates from Girisankar
+//  1.14   | bellows  | 12-11-12| added ; to DBG line
+//  1.13   | bellows  | 12-07-12| fix for interleaving attr and array bounds
+//  1.11   | bellows  | 11-27-12| review updates
 //  1.10   | bellows  | 09-27-12| Additional Review Updates
 //  1.9    | bellows  | 09-25-12| updates from review, code from Girisankar
 //  1.8    | bellows  | 09-06-12| updates suggested by Van
@@ -66,7 +71,7 @@ extern "C" {
 //----------------------------------------------------
 
   ReturnCode mss_eff_grouping(const fapi::Target & i_target, std::vector<fapi::Target> & i_associated_centaurs); // Target is Proc target & Each MCS connected to each Centaur. Associated centaur is collection of the Centaure location for the processor
-  uint8_t mss_eff_grouping_recursion(uint8_t number);
+  uint8_t mss_eff_grouping_recursion(uint32_t number);
 //ReturnCode mba_collection(std::vector<fapi::Target> & associated_centaurs);
 //ReturnCode mcs_grouping(const fapi::Target & target);
 //ReturnCode mcs_grouping_general();
@@ -104,11 +109,12 @@ extern "C" {
                               std::vector<fapi::Target> & i_associated_centaurs
                               ) {
     ReturnCode rc;
-    Eff_Grouping_Data eff_grouping_data;
+    Eff_Grouping_Data eff_grouping_data,tempgpID;
        //Eff_Grouping_Data &eff_grouping_data;
         //eff_grouping_data.groupID[16][16]={{0}};
-    uint32_t pos=0;
+    //uint32_t pos=0;
     uint64_t mss_base_address;
+    uint64_t mirror_base;
         //uint32_t MBA_size[8][2]={{0}};
         //uint32_t MCS_size[8]={0};
     uint32_t l_unit_pos =0;
@@ -194,137 +200,298 @@ extern "C" {
         FAPI_INF("MCS SIZE %d \n",eff_grouping_data.MCS_size[i]);
       }
       FAPI_INF("Group parsing Starting..");
-      rc =  FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE,&i_target,min_group);
-      if(!rc.ok()) {FAPI_ERR("MSS_INTERLEAV_ENABLE is not available"); return rc;}
-        //rc=mcs_grouping_general();
-      if(!rc.ok()) {FAPI_ERR("MCS Grouping: fails at generating the MCS size"); return rc;}			
 // 	groupID[i][0]=Size;
 //  groupID[i][1]= number of MBA in the group for example 4 MBA in the group
 //  groupID[i][2]= Total size of memory
 //  groupID[i][3] to groupIDsize[i][6]  - group pos indication
-      uint32_t temp[12];
-      uint8_t min_group = 1;
-      uint32_t max_group = 8;
-      uint32_t mirroring =0;
-      uint8_t pos_t=0;
+    //  uint32_t temp[12];
       uint8_t count=0;
-      uint8_t onemcs=0;
-      if ((((eff_grouping_data.MCS_size[0] == eff_grouping_data.MCS_size[4])
-            && (eff_grouping_data.MCS_size[1] == eff_grouping_data.MCS_size[5]))
-           &&(eff_grouping_data.MCS_size[3]==eff_grouping_data.MCS_size[4])
-           &&(eff_grouping_data.MCS_size[5]==eff_grouping_data.MCS_size[6])
-           &&((eff_grouping_data.MCS_size[2] == eff_grouping_data.MCS_size[6])
-              &&(eff_grouping_data.MCS_size[3] ==eff_grouping_data.MCS_size[7])))
-          && l_unit_pos==8)
-      {
-        eff_grouping_data.groupID[0][1] =4;
-        eff_grouping_data.groupID[0][4] =0;
-        eff_grouping_data.groupID[0][5] =2;
-        eff_grouping_data.groupID[0][6] =1;
-        eff_grouping_data.groupID[0][7] =3;
-        eff_grouping_data.groupID[0][0] = eff_grouping_data.MCS_size[4];	
-        gp_pos=1;
-        mirroring =1;
-        FAPI_INF("Mirroring enabled\n");
-      }
-      else if ((((eff_grouping_data.MCS_size[0] == eff_grouping_data.MCS_size[1])
-                 &&(eff_grouping_data.MCS_size[0] == eff_grouping_data.MCS_size[4])
-                 &&(eff_grouping_data.MCS_size[4] == eff_grouping_data.MCS_size[5]))
-                ||((eff_grouping_data.MCS_size[2] == eff_grouping_data.MCS_size[3])
-                   &&(eff_grouping_data.MCS_size[2] == eff_grouping_data.MCS_size[6])
-                   &&(eff_grouping_data.MCS_size[6] == eff_grouping_data.MCS_size[7])))
-               && l_unit_pos==4)
-      {
-        eff_grouping_data.groupID[0][1] =2;
-        eff_grouping_data.groupID[0][4] =4;
-        eff_grouping_data.groupID[0][5] =5;
-        eff_grouping_data.groupID[0][0] = eff_grouping_data.MCS_size[4];
-        eff_grouping_data.groupID[1][1] =2;
-        eff_grouping_data.groupID[1][4] =6;
-        eff_grouping_data.groupID[1][5] =7;
-        eff_grouping_data.groupID[1][0] = eff_grouping_data.MCS_size[5];
-        gp_pos=2;
-        mirroring =1;         	
-        FAPI_INF("Mirroring enabled\n");
-      }
-      else
-      {
-        while(max_group>=min_group)
+        uint8_t done;
+        uint8_t pos;
+        uint8_t config_4MCS[6][4]={{0,1,4,5},{2,3,6,7},{0,1,6,7},{2,3,4,5},{0,1,2,3},{4,5,6,7}};
+        int flag;
+        uint8_t config4_pos[6];
+        uint8_t groups_allowed;
+        // uint8_t tempgpID.groupID[16][16];
+        uint8_t grouped[16];
+        uint8_t check_board;
+        uint8_t gp=0;
+        uint8_t pos1=0;
+        uint8_t pos2=0;
+        uint8_t allowed=0;
+
+
+
+        for(uint8_t i=0;i<6;i++)
+          config4_pos[i]=0;
+
+	rc = FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE,&i_target,groups_allowed);
+	if(!rc.ok()) {FAPI_ERR("MSS_INTERLEAVE_ENABLE is not available"); return rc; }
+	rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,check_board); // system level attribute
+	if (!rc.ok()) { FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP"); return rc; }
+
+
+
+        for(uint8_t i=0;i<16;i++)
         {
-          for(uint8_t i=0;i<16;i++)
-            for(uint8_t j=0;j<16;j++)
-              eff_grouping_data.groupID[i][j]=0;
-          gp_pos=0;
-          count=0;
-          for(pos=0;pos<8;pos++)
-          {
-            eff_grouping_data.groupID[gp_pos][0] = eff_grouping_data.MCS_size[pos];
-            eff_grouping_data.groupID[gp_pos][1] = 1;
-            eff_grouping_data.groupID[gp_pos][4]= pos;
-            gp_pos++;
-          }
-          for(pos_t=0;pos_t<=gp_pos;pos_t++)
-          {
-            for(pos=pos_t+1; pos<=gp_pos;pos++)
-            {
-              if(eff_grouping_data.groupID[pos_t][0] == eff_grouping_data.groupID[pos][0])
-              {
-                if( eff_grouping_data.groupID[pos_t][1]<max_group)
+             grouped[i]=0;
+             for(uint8_t j=0;j<16;j++)
+             {
+                 eff_grouping_data.groupID[i][j]=0;
+                 tempgpID.groupID[i][j]=0;
+             }
+         }
+
+
+        gp_pos=0;
+
+        for(pos=0;pos<8;pos++)
+        {
+             eff_grouping_data.groupID[gp_pos][0] = eff_grouping_data.MCS_size[pos];
+             eff_grouping_data.groupID[gp_pos][1] = 1;
+             eff_grouping_data.groupID[gp_pos][4]= pos;
+
+             if(eff_grouping_data.MBA_size[pos][0]>eff_grouping_data.MBA_size[pos][1])
+                  eff_grouping_data.groupID[gp_pos][15]= eff_grouping_data.MBA_size[pos][0];
+             else
+                  eff_grouping_data.groupID[gp_pos][15]= eff_grouping_data.MBA_size[pos][1];
+
+             gp_pos++;
+         }
+
+
+           done = 0 ;
+           if(!done && (groups_allowed & 0x08) && check_board)
+           {
+          	
+                count =0;
+                for(pos=0;pos< gp_pos;pos++)
                 {
-                  eff_grouping_data.groupID[pos_t][1]++;
-                  eff_grouping_data.groupID[pos_t][eff_grouping_data.groupID[pos_t][1]+3]=pos;
+                    if(eff_grouping_data.groupID[0][0] == eff_grouping_data.groupID[pos][0] && eff_grouping_data.groupID[pos][0] !=0)
+                    {
+                      count++;
+                    }
+                 }
+
+                 if(count == 8)
+                 {
+                   done=1;
+                   eff_grouping_data.groupID[0][1] = 8;
+                   eff_grouping_data.groupID[0][4] = 0;
+                   eff_grouping_data.groupID[0][5] = 4;
+                   eff_grouping_data.groupID[0][6] = 1;
+                   eff_grouping_data.groupID[0][7] = 5;
+                   eff_grouping_data.groupID[0][8] = 2;
+                   eff_grouping_data.groupID[0][9] = 6;
+                   eff_grouping_data.groupID[0][10] = 3;
+                   eff_grouping_data.groupID[0][11] = 7;
+                   for(uint8_t i=1;i<16;i++)
+                     for(uint8_t j=0;j<16;j++)
+                       eff_grouping_data.groupID[i][j]=0;
+                 }
+
+            }
+            if(!done && (groups_allowed & 0x04) && check_board)
+            {
+                 count=0;
+                 for(uint8_t i=0;i<6;i++)
+                 {
+                   flag=0;
+                   for( int j=0;j<4;j++)
+                    {
+                      if((eff_grouping_data.groupID[config_4MCS[i][0]][0]== 0) || (eff_grouping_data.groupID[config_4MCS[i][0]][0] != eff_grouping_data.groupID[config_4MCS[i][j]][0]))
+                       {
+                         flag=1;
+                       }
+                    }
+                    if(!flag)
+                    {
+
+                    config4_pos[i]=1;
+                    count++;
+                    }
+                 }
+                 if(count>=2)
+                 {
+                    if(config4_pos[0] && config4_pos[1])
+                    {
+                       allowed=1;
+                       pos1=0;
+                       pos2=1;
+                    }
+                    else if(config4_pos[2] && config4_pos[3])
+                    {
+                       allowed=1;
+                       pos1=2;
+                       pos2=3;
+                    }
+                    else if(config4_pos[4] && config4_pos[5])
+                    {
+                       allowed=1;
+                       pos1=4;
+                       pos2=5;
+                    }
+                 }
+                 if(allowed)
+                  {
+          	           done =1;
+                         //define the group_data
+                         eff_grouping_data.groupID[0][0] =eff_grouping_data.groupID[config_4MCS[pos1][0]][0];
+                         eff_grouping_data.groupID[0][1] = 4;
+                         eff_grouping_data.groupID[0][4] = config_4MCS[pos1][0];
+                         eff_grouping_data.groupID[0][5] = config_4MCS[pos1][2];
+                         eff_grouping_data.groupID[0][6] = config_4MCS[pos1][1];
+                         eff_grouping_data.groupID[0][7] = config_4MCS[pos1][3];
+                         eff_grouping_data.groupID[0][15] =eff_grouping_data.groupID[config_4MCS[pos1][0]][15];
+
+                         eff_grouping_data.groupID[1][0] =eff_grouping_data.groupID[config_4MCS[pos2][0]][0];
+                         eff_grouping_data.groupID[1][1] = 4;
+                         eff_grouping_data.groupID[1][4] = config_4MCS[pos2][0];
+                         eff_grouping_data.groupID[1][5] = config_4MCS[pos2][2];
+                         eff_grouping_data.groupID[1][6] = config_4MCS[pos2][1];
+                         eff_grouping_data.groupID[1][7] = config_4MCS[pos2][3];
+                         eff_grouping_data.groupID[1][15] =eff_grouping_data.groupID[config_4MCS[pos2][0]][15];
+
+                         for(uint8_t i=2;i<16;i++)
+                           for(uint8_t j=0;j<16;j++)
+                             eff_grouping_data.groupID[i][j]=0;
+                  }
+                  else if (count ==1 || !allowed )
+                  {
+                       for(uint8_t i=0;i<6;i++)
+                       {
+                         if(config4_pos[i])
+                         {
+                           allowed=1;
+                           pos1=i;
+                           break;
+                         }
+                       }
+                       if(allowed)
+                       {
+          	          //define the group_data
+          	           tempgpID.groupID[0][0] = eff_grouping_data.groupID[config_4MCS[pos1][0]][0];
+                           tempgpID.groupID[0][1] = 4;
+                           tempgpID.groupID[0][4] = config_4MCS[pos1][0];
+                           tempgpID.groupID[0][5] = config_4MCS[pos1][2];
+                           tempgpID.groupID[0][6] = config_4MCS[pos1][1];
+                           tempgpID.groupID[0][7] = config_4MCS[pos1][3];
+                           tempgpID.groupID[0][15] = eff_grouping_data.groupID[config_4MCS[pos1][0]][15];
+          	           gp++;
+                           for(int i=0; i<4;i++)
+                           {
+                              eff_grouping_data.groupID[config_4MCS[pos1][i]][0]=0;
+                              grouped[config_4MCS[config4_pos[0]][i]]=1;
+                           }
+                       }
+                   }
+           }
+           if(!done && (groups_allowed & 0x02) && check_board)
+           {
+            for(pos=0;pos< gp_pos;pos=pos+2)
+            {
+                 if(eff_grouping_data.groupID[pos][0] == eff_grouping_data.groupID[pos+1][0] && eff_grouping_data.groupID[pos][0] !=0  )
+                 {
+                  //group
+                  tempgpID.groupID[gp][0] =eff_grouping_data.groupID[pos][0] ;
+                  tempgpID.groupID[gp][1] = 2;
+                  tempgpID.groupID[gp][4] =  pos;
+                  tempgpID.groupID[gp][5] = pos+1;
+                  tempgpID.groupID[gp][15] =eff_grouping_data.groupID[pos][15] ;
+                  grouped[pos]=1;
+                  grouped[pos+1]=1;
                   eff_grouping_data.groupID[pos][0]=0;
-                  eff_grouping_data.groupID[pos][1]=0;
-                }
-                else {}
+                  eff_grouping_data.groupID[pos+1][0]=0;
+                  gp++;
+                 }
+             }
+           }
+           if(!done && (groups_allowed & 0x01)&& !check_board)
+           {
+            for(pos=0;pos< gp_pos;pos++)
+            {
+                 if(eff_grouping_data.groupID[pos][0] !=0  )
+                 {
+                  //group
+                  tempgpID.groupID[gp][0] =eff_grouping_data.groupID[pos][0] ;
+                  tempgpID.groupID[gp][1] = 1;
+                  tempgpID.groupID[gp][4] =  pos;
+                  tempgpID.groupID[gp][15] =eff_grouping_data.groupID[pos][15] ;
+                  grouped[pos]=1;
+                  eff_grouping_data.groupID[pos][0]=0;
+                  gp++;
+                 }
+             }
+           }
+           if(!done)
+           {
+              for(uint8_t i=0;i<8;i++)
+              {
+          		   if(grouped[i] !=1 && eff_grouping_data.groupID[i][0] != 0 )
+          		   FAPI_ERR ("UNABLE TO GROUP MCS%d size is %d", i,eff_grouping_data.groupID[i][0]);
               }
-            }	 	
-          }
-          for(uint8_t i=0;i<8;i++)
-          {
-            if ((eff_grouping_data.groupID[i][0]!= 0) && (eff_grouping_data.groupID[i][1] == max_group))
-            { count += eff_grouping_data.groupID[i][1];FAPI_INF("group ID %dMCS size %d\n",i,eff_grouping_data.groupID[i][1]);}
-          }
-          if (count == l_unit_pos) { FAPI_INF("group done correctly\n");onemcs=0;break;}
-          else{ FAPI_INF("this grouping is not possible with %d\n",max_group);onemcs=0;}
-          max_group= max_group/2;
-        }
-      }  	  	
-   // uint32_t temp[12];
+
+             for(uint8_t i=0;i<gp;i++)
+               for(uint8_t j=0;j<16;j++)
+                 eff_grouping_data.groupID[i][j]=tempgpID.groupID[i][j];
+
+             for(uint8_t i=gp ; i<8 ; i++)
+               for(uint8_t j=0;j<16;j++)
+               eff_grouping_data.groupID[i][j]=0;
+           }
+            flag=0;
+            for(uint8_t i=0;i<16;i++)
+               if(grouped[i])
+                  flag=1;
+            gp_pos=0;
+            if(done || flag)
+            {
+               for(uint8_t i=0;i<16;i++)
+               {
+            	      if( eff_grouping_data.groupID[i][0] !=0)
+            	      {
+                         gp_pos++;
+                         FAPI_INF(" group no= %d , num of MCS = %d , size of MCS = %d \n ", i,eff_grouping_data.groupID[i][1],eff_grouping_data.groupID[i][0]);
+                         for(uint8_t k=0 ; k< eff_grouping_data.groupID[i][1];k++)
+                         {
+            	           FAPI_INF("MCSID%d = %d \n ", k, eff_grouping_data.groupID[i][4+k]);
+                         }
+                      }
+                  }
+             }
+      uint32_t temp[16];
       uint8_t i=0;
       uint8_t j=0;
-    //uint8_t count=0;
-      for(i=0;i<8;i++)
-      {
-        for(j=0;j<12;j++)
-        {
-          FAPI_INF(" groupID[%d][%d] = %d",i,j,eff_grouping_data.groupID[i][j]);
-        }
-        FAPI_INF("\n");
-      }
-      for(pos=0;pos<=gp_pos;pos++)
+      count=0;
+
+    for(pos=0;pos<=gp_pos;pos++)
       {
         eff_grouping_data.groupID[pos][2] = eff_grouping_data.groupID[pos][0]*eff_grouping_data.groupID[pos][1];
+        //eff_grouping_data.groupID[pos+8][2]= eff_grouping_data.groupID[pos][2]/2; // group size when mirrored
+
         count =  mss_eff_grouping_recursion(eff_grouping_data.groupID[pos][2]);
         if(count>1)
         {
           FAPI_INF("MCS pos %d needs alternate bars defintation group Size %d\n",pos,eff_grouping_data.groupID[pos][3]);
-          if (eff_grouping_data.MBA_size[pos][1] > eff_grouping_data.MBA_size[pos][0])
-          {
-            eff_grouping_data.groupID[pos][2] = eff_grouping_data.MBA_size[pos][1]*2*eff_grouping_data.groupID[pos][1];
-            eff_grouping_data.groupID[pos][13] = eff_grouping_data.groupID[pos][1]*eff_grouping_data.MBA_size[pos][1];
-          }
-          else
-          {
-            eff_grouping_data.groupID[pos][2] = eff_grouping_data.MBA_size[pos][0]*2*eff_grouping_data.groupID[pos][1];
-            eff_grouping_data.groupID[pos][13] = eff_grouping_data.groupID[pos][1]*eff_grouping_data.MBA_size[pos][0];
-          }
-          eff_grouping_data.groupID[pos][12] =1;
-        }		
+
+
+
+            eff_grouping_data.groupID[pos][2] = eff_grouping_data.groupID[pos][15]*2*eff_grouping_data.groupID[pos][1];
+            eff_grouping_data.groupID[pos][13] = eff_grouping_data.groupID[pos][1]*(eff_grouping_data.groupID[pos][0]-eff_grouping_data.groupID[pos][15]);
+
+            //mirrored group
+            //eff_grouping_data.groupID[pos+8][2] = eff_grouping_data.groupID[pos][2]/2;  //group size with alternate bars
+            //eff_grouping_data.groupID[pos+8][13] = eff_grouping_data.groupID[pos][13]/2;
+             eff_grouping_data.groupID[pos][12] =1;
+        }
       }
-      for(pos=0;pos<=gp_pos;pos++)
+      for(i=0;i<gp_pos;i++)
       {
-        eff_grouping_data.groupID[pos][2] = eff_grouping_data.groupID[pos][0]*eff_grouping_data.groupID[pos][1];
+          for(j=0;j<12;j++)
+          {
+            FAPI_INF(" groupID[%d][%d] = %d",i,j,eff_grouping_data.groupID[i][j]);
+          }
+          FAPI_INF("\n");
       }
       for(pos=0;pos<=gp_pos;pos++)
       {	
@@ -332,37 +499,102 @@ extern "C" {
         {
           if ( eff_grouping_data.groupID[i][2] > eff_grouping_data.groupID[pos][2])
           {
-            for(j=0;j<12;j++)	temp[j] = eff_grouping_data.groupID[pos][j];
-            for(j=0;j<12;j++)	eff_grouping_data.groupID[pos][j] = eff_grouping_data.groupID[i][j];
-            for(j=0;j<12;j++)	eff_grouping_data.groupID[i][j] = temp[j];
+            for(j=0;j<16;j++)	temp[j] = eff_grouping_data.groupID[pos][j];
+            for(j=0;j<16;j++)	eff_grouping_data.groupID[pos][j] = eff_grouping_data.groupID[i][j];
+            for(j=0;j<16;j++)	eff_grouping_data.groupID[i][j] = temp[j];
           }
           else {}
-        }	
-      }			
+        }
+      }
+
+
+       // calcutate mirrored group size
+       for(pos=0;pos<gp_pos;pos++)
+      {
+        if(eff_grouping_data.groupID[pos][0]!=0 && eff_grouping_data.groupID[pos][1]>1 )
+        {
+          eff_grouping_data.groupID[pos+8][2]= eff_grouping_data.groupID[pos][2]/2; // group size when mirrored
+
+
+          if(eff_grouping_data.groupID[pos][12])
+          {
+            FAPI_INF("Mirrored group pos %d needs alternate bars defintation group Size %d\n",pos,eff_grouping_data.groupID[pos][3]);
+            //mirrored group
+            eff_grouping_data.groupID[pos+8][2] = eff_grouping_data.groupID[pos][2]/2;  //group size with alternate bars
+            eff_grouping_data.groupID[pos+8][13] = eff_grouping_data.groupID[pos][13]/2;
+
+          }
+        }
+      }
+
       rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,mss_base_address);
       mss_base_address =   mss_base_address >> 30;
       if(!rc.ok()) return rc;
-      for(pos=0;pos<=gp_pos;pos++)
+
+      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,mirror_base);
+      mirror_base =   mirror_base >> 30;
+
+      if(!rc.ok()) return rc;
+
+      for(pos=0;pos<gp_pos;pos++)
       {
         if(pos==0)
         {
-          eff_grouping_data.groupID[pos][3] = mss_base_address;
+
+          eff_grouping_data.groupID[pos][3] =mss_base_address;
+          eff_grouping_data.groupID[pos+8][3]=mirror_base;  //mirrored base address
           if(eff_grouping_data.groupID[pos][12])
           {
-            eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2];
+
+            eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2;
+            eff_grouping_data.groupID[pos+8][14] = eff_grouping_data.groupID[pos+8][3]+ eff_grouping_data.groupID[pos+8][2]/2; //mirrored base address with alternate bars
           }
         }
         else
         {
           eff_grouping_data.groupID[pos][3] = eff_grouping_data.groupID[pos-1][3]+eff_grouping_data.groupID[pos-1][2];
+          eff_grouping_data.groupID[pos+8][3]= eff_grouping_data.groupID[pos-1+8][3]+eff_grouping_data.groupID[pos-1+8][2];
+
           if(eff_grouping_data.groupID[pos][12])
           {
-            eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2];
+            eff_grouping_data.groupID[pos][14] = eff_grouping_data.groupID[pos][3]+ eff_grouping_data.groupID[pos][2]/2;
+            eff_grouping_data.groupID[pos+8][14] = eff_grouping_data.groupID[pos+8][3]+ eff_grouping_data.groupID[pos+8][2]/2; //mirrored base address with alternate bars
           }
         }		
       }		
+      ecmdDataBufferBase MC_IN_GP(8);
+      uint8_t mcs_in_group[8];
+      for(uint8_t i=0;i<8;i++)
+           mcs_in_group[i]=0;
+      for(uint8_t i=0;i<gp_pos;i++)
+      {
+        count=0;
+        MC_IN_GP.flushTo0();
+        if(eff_grouping_data.groupID[i][0]!=0)
+        {
+          count = eff_grouping_data.groupID[i][1];
+          for(uint8_t j=0;j<count;j++)
+                 MC_IN_GP.setBit(eff_grouping_data.groupID[i][4+j]);
+          mcs_in_group[i]= MC_IN_GP.getByte(0);
+        }
+       }
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[0]: 0x%x", mcs_in_group[0]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[1]: 0x%x", mcs_in_group[1]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[2]: 0x%x", mcs_in_group[2]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[3]: 0x%x", mcs_in_group[3]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[4]: 0x%x", mcs_in_group[4]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[5]: 0x%x", mcs_in_group[5]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[6]: 0x%x", mcs_in_group[6]);
+       FAPI_DBG("  ATTR_MSS_MEM_MC_IN_GROUP[7]: 0x%x", mcs_in_group[7]);
+
+       rc= FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_target, mcs_in_group);
+       if (!rc.ok())FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP");
+
       uint64_t mem_bases[8];
       uint64_t l_memory_sizes[8];
+      //uint64_t mirror_base;
+      uint64_t mirror_bases[4];
+      uint64_t l_mirror_sizes[4];
         //uint32_t temp[8];
       for(uint8_t i=0;i<8;i++)
       {
@@ -372,11 +604,17 @@ extern "C" {
           FAPI_INF (" No of MCS %4d ",eff_grouping_data.groupID[i][1]);
           FAPI_INF (" Group Size %4d ",eff_grouping_data.groupID[i][2]);
           FAPI_INF (" Base Add.  %4d ",eff_grouping_data.groupID[i][3]);
+          FAPI_INF (" Mirrored Group SIze %4d", eff_grouping_data.groupID[i+8][2]);
+          FAPI_INF (" Mirror Base Add %4d", eff_grouping_data.groupID[i+8][3]);
           for(uint8_t j=4;j<4+eff_grouping_data.groupID[i][1];j++)
           {
             FAPI_INF (" MCSID%d- Pos %4d",(j-4),eff_grouping_data.groupID[i][j]);
           }
           FAPI_INF (" Alter-bar  %4d",eff_grouping_data.groupID[i][12]);
+          FAPI_INF("Alter-bar base add = %4d",eff_grouping_data.groupID[i][14]);
+          FAPI_INF("Alter-bar size = %4d",eff_grouping_data.groupID[i][13]);
+          FAPI_INF("Alter-bar Mirrored Base add = %4d", eff_grouping_data.groupID[i+8][14]);
+          FAPI_INF("Alter-bar Mirrored size = %4d", eff_grouping_data.groupID[i+8][13]);
         }
         else
         {
@@ -465,18 +703,88 @@ extern "C" {
         FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES");
         break;
       }
-      rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32,&i_target,eff_grouping_data.groupID);
+       rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_target, l_memory_sizes);
+        if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES");
+        break;
+      }
+       FAPI_DBG("  ATTR_PROC_MEM_SIZES[0]: %016llx", l_memory_sizes[0]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[1]: %016llx", l_memory_sizes[1]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[2]: %016llx", l_memory_sizes[2]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[3]: %016llx", l_memory_sizes[3]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[4]: %016llx", l_memory_sizes[4]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[5]: %016llx", l_memory_sizes[5]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[6]: %016llx", l_memory_sizes[6]);
+      FAPI_DBG("  ATTR_PROC_MEM_SIZES[7]: %016llx", l_memory_sizes[7]);
+
+      rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32,&i_target, eff_grouping_data.groupID);
       if (!rc.ok())
       {
         FAPI_ERR("Error writing ATTR_MSS_MCS_GROUP");
         break;
       }
+          // process mirrored ranges
+        //
+
+        // read chip base address attribute
+///      rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_chip_target, mirror_base);
+//      if (!rc.ok())
+//      {
+//        FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
+//        break;
+//      }
+
+        // base addresses for distinct mirrored ranges
+      mirror_bases[0] = eff_grouping_data.groupID[8][3];
+      mirror_bases[1] = eff_grouping_data.groupID[9][3];
+      mirror_bases[2] = eff_grouping_data.groupID[10][3];
+      mirror_bases[3] = eff_grouping_data.groupID[11][3];
+
+      mirror_bases[0] = mirror_bases[0]<<30;
+      mirror_bases[1] = mirror_bases[1]<<30;
+      mirror_bases[2] = mirror_bases[2]<<30;
+      mirror_bases[3] = mirror_bases[3]<<30;
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[0]: %016llx", mirror_bases[0]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[1]: %016llx", mirror_bases[1]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[2]: %016llx", mirror_bases[2]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_BASES[3]: %016llx", mirror_bases[3]);
+
+      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_target, mirror_bases);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES");
+        break;
+      }
+
+        // sizes for distinct mirrored ranges
+      l_mirror_sizes[0]=eff_grouping_data.groupID[8][2];
+      l_mirror_sizes[1]=eff_grouping_data.groupID[9][2];
+      l_mirror_sizes[2]=eff_grouping_data.groupID[10][2];
+      l_mirror_sizes[3]=eff_grouping_data.groupID[11][2];
+
+      l_mirror_sizes[0] = l_mirror_sizes[0]<<30;
+      l_mirror_sizes[1] = l_mirror_sizes[1]<<30;
+      l_mirror_sizes[2] = l_mirror_sizes[2]<<30;
+      l_mirror_sizes[3] = l_mirror_sizes[3]<<30;
+
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[0]: %016llx", l_mirror_sizes[0]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[1]: %016llx", l_mirror_sizes[1]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[2]: %016llx", l_mirror_sizes[2]);
+      FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[3]: %016llx", l_mirror_sizes[3]);
+
+      rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_target, l_mirror_sizes);
+      if (!rc.ok())
+      {
+        FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES");
+        break;
+       }
     }while(0);
     return rc;			
   }
 
-  uint8_t  mss_eff_grouping_recursion(uint8_t number){
-    uint8_t temp = number;
+  uint8_t  mss_eff_grouping_recursion(uint32_t number){
+    uint32_t temp = number;
     uint8_t count=0;
     uint8_t buffersize=0;	
     while(1)
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
new file mode 100644
index 000000000..b8c1211dd
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
@@ -0,0 +1,293 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_throttle_to_power.C,v 1.8 2012/10/31 13:40:27 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_throttle_to_power.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_throttle_to_power
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
+// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// applicable CQ component memory_screen
+//
+// DESCRIPTION:
+// The purpose of this procedure is to set the power attributes for each dimm and channel pair
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.8   | pardeik  |25-OCT-12| updated FAPI_ERR sections, added CQ component comment line
+//   1.7   | pardeik  |19-OCT-12| use ATTR_MSS_CHANNEL_PAIR_MAXPOWER instead of ATTR_MSS_CHANNEL_MAXPOWER
+//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram utilization
+//   1.6   | pardeik  |11-OCT-12| updated to use new throttle attributes, made function mss_throttle_to_power_calc
+//   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
+//   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
+//   1.4   | pardeik  |04-APR-12| moved cdimm power calculation to end of section instead of having it in multiple places
+//   1.3   | pardeik  |04-APR-12| use else if instead of if after checking throttle denominator to zero
+//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs, added cdimm power calculation for half of cdimm
+//   1.1   | pardeik  |01-APR-11| Updated to use attributes and fapi functions to loop through ports/dimms
+//         | pardeik  |01-DEC-11| First Draft.
+
+
+//------------------------------------------------------------------------------
+//  My Includes
+//------------------------------------------------------------------------------
+#include <mss_throttle_to_power.H>
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+
+extern "C" {
+
+    using namespace fapi;
+
+
+//------------------------------------------------------------------------------
+// Funtions in this file
+//------------------------------------------------------------------------------
+    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
+
+    fapi::ReturnCode mss_throttle_to_power_calc(
+						const fapi::Target &i_target_mba,
+						uint32_t i_throttle_n_per_mba,
+						uint32_t i_throttle_n_per_chip,
+						uint32_t i_throttle_d,
+						float &channel_pair_power
+						);
+
+
+//------------------------------------------------------------------------------
+// @brief mss_throttle_to_power(): This function will get the throttle attributes and call another function to determine the dimm and channel pair power based on those throttles
+//
+// @param    const fapi::Target &i_target_mba:  MBA Target
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba)
+    {
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+
+	char procedure_name[32];
+	sprintf(procedure_name, "mss_throttle_to_power");
+	FAPI_INF("*** Running %s ***", procedure_name);
+
+	uint32_t throttle_n_per_mba;
+	uint32_t throttle_n_per_chip;
+	uint32_t throttle_d;
+	float channel_pair_power;
+
+// Get input attributes
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA, &i_target_mba, throttle_n_per_mba);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP, &i_target_mba, throttle_n_per_chip);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR, &i_target_mba, throttle_d);
+	if(rc) return rc;
+
+// Call function mss_throttle_to_power_calc
+	rc = mss_throttle_to_power_calc(
+					i_target_mba,
+					throttle_n_per_mba,
+					throttle_n_per_chip,
+					throttle_d,
+					channel_pair_power
+					);
+	if(rc)
+	{
+	    FAPI_ERR("Error (0x%x) calling mss_throttle_to_power_calc", static_cast<uint32_t>(rc));
+	    return rc;
+	}
+
+	FAPI_INF("*** %s COMPLETE ***", procedure_name);
+	return rc;
+
+    }
+
+
+
+//------------------------------------------------------------------------------
+// @brief mss_throttle_to_power_calc(): This function will calculate the dimm and channel pair power and update attributes with the power values
+//
+// @param    const fapi::Target &i_target_mba:  MBA Target
+// @param    uint32_t i_throttle_n_per_mba:  Throttle value for cfg_nm_n_per_mba
+// @param    uint32_t i_throttle_n_per_chip:  Throttle value for cfg_nm_n_per_chip
+// @param    uint32_t i_throttle_d:  Throttle value for cfg_nm_m
+// @param    float &o_channel_pair_power:  channel pair power at these throttle settings
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_throttle_to_power_calc(
+						const fapi::Target &i_target_mba,
+						uint32_t i_throttle_n_per_mba,
+						uint32_t i_throttle_n_per_chip,
+						uint32_t i_throttle_d,
+						float &o_channel_pair_power
+						)
+    {
+	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
+
+	const uint8_t MAX_NUM_PORTS = 2;			// number of ports per MBA
+	const uint8_t MAX_NUM_DIMMS = 2;			// number of dimms per MBA port
+// If this is changed, also change mss_bulk_pwr_throttles MAX_UTIL
+	const float MAX_UTIL = 75;				// Maximum theoretical data bus utilization (percent of max) (for ceiling)
+
+	uint32_t l_power_slope_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	uint32_t l_power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	uint8_t l_dimm_ranks_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	uint8_t l_port;
+	uint8_t l_dimm;
+	float l_dimm_power_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	uint32_t l_dimm_power_array_integer[MAX_NUM_PORTS][MAX_NUM_DIMMS];
+	float l_utilization;
+	float l_channel_power_array[MAX_NUM_PORTS];
+	uint32_t l_channel_power_array_integer[MAX_NUM_PORTS];
+	uint32_t l_channel_pair_power_integer;
+	uint8_t l_num_dimms_on_port;
+
+// get input attributes
+	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_SLOPE, &i_target_mba, l_power_slope_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT, &i_target_mba, l_power_int_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_dimm_ranks_array);
+	if(rc) return rc;
+	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_dimms_on_port);
+	if(rc) return rc;
+
+// add up the power from all dimms for this MBA (across both channels) using the throttle values
+	o_channel_pair_power = 0;
+	l_channel_pair_power_integer = 0;
+	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
+	{
+	    l_channel_power_array[l_port] = 0;
+	    l_channel_power_array_integer[l_port] = 0;
+	    for (l_dimm=0; l_dimm < MAX_NUM_DIMMS; l_dimm++)
+	    {
+// default dimm power is zero (used for dimms that are not physically present)
+		l_dimm_power_array[l_port][l_dimm] = 0;
+		l_dimm_power_array_integer[l_port][l_dimm] = 0;
+		l_utilization = 0;
+// See if there are any ranks present on the dimm (configured or deconfigured)
+		if (l_dimm_ranks_array[l_port][l_dimm] > 0)
+		{
+// N/M throttling has the dimm0 and dimm1 throttles the same for DIMM level throttling, which we plan to use
+// MBA or chip level throttling could limit the commands to a dimm (used along with the dimm level throttling)
+// If MBA/chip throttle is less than dimm throttle, then use MBA/chip throttle
+// If MBA/chip throttle is greater than dimm throttle, then use the dimm throttle
+// If either of these are above the MAX_UTIL, then use MAX_UTIL
+// Get power from each dimm here
+// Note that the MAX_UTIL effectively is the percent of maximum bandwidth for that dimm
+
+		    if (i_throttle_d == 0)
+		    {
+			    // throttle denominator is zero (N/M throttling disabled), set dimm power to the maximum
+			FAPI_DBG("N/M Throttling is disabled (M=0).  Use Max DIMM Power");
+			l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+			l_utilization = (float)MAX_UTIL;
+		    }
+		    else if ((((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port) > (((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d))
+		    {
+			// limited by the mba/chip throttles (ie.  cfg_nm_n_per_chip)
+			if ((((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d) > MAX_UTIL)
+			{
+			    // limited by the maximum utilization
+			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+			    l_utilization = (float)MAX_UTIL;
+			}
+			else
+			{
+			    // limited by the per chip throttles
+			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * (((float)i_throttle_n_per_chip * 4) / i_throttle_d) + l_power_int_array[l_port][l_dimm]);
+			    l_utilization = (((float)i_throttle_n_per_chip * 100 * 4) / i_throttle_d);
+			}
+		    }
+		    else
+		    {
+			// limited by the per mba throttles (ie.  cfg_nm_n_per_mba)
+			if ((((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port) > MAX_UTIL)
+			{
+			    // limited by the maximum utilization
+			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * ((float)MAX_UTIL / 100) + l_power_int_array[l_port][l_dimm]);
+			    l_utilization = (float)MAX_UTIL;
+			}
+			else
+			{
+			    // limited by the per mba throttles
+			    // multiply by number of dimms on port since other dimm has same throttle value
+			    l_dimm_power_array[l_port][l_dimm] = (l_power_slope_array[l_port][l_dimm] * (((float)i_throttle_n_per_mba * 4) / i_throttle_d * l_num_dimms_on_port) + l_power_int_array[l_port][l_dimm]);
+			    l_utilization = (((float)i_throttle_n_per_mba * 100 * 4) / i_throttle_d * l_num_dimms_on_port);
+			}
+		    }
+		}
+// Get dimm power in integer format (add on 1 since value will get truncated)
+		if (l_dimm_power_array[l_port][l_dimm] > 0)
+		{
+		    l_dimm_power_array_integer[l_port][l_dimm] = (int)l_dimm_power_array[l_port][l_dimm] + 1;
+		}
+// calculate channel power by adding up the power of each dimm
+		l_channel_power_array[l_port] = l_channel_power_array[l_port] + l_dimm_power_array[l_port][l_dimm];
+		FAPI_DBG("[P%d:D%d][CH Util %4.2f/%4.2f][Slope:Int %d:%d][Power %4.2f cW]", l_port, l_dimm, l_utilization, MAX_UTIL, l_power_slope_array[l_port][l_dimm], l_power_int_array[l_port][l_dimm], l_dimm_power_array[l_port][l_dimm]);
+	    }
+	    FAPI_DBG("[P%d][Power %4.2f cW]", l_port, l_channel_power_array[l_port]);
+	}
+// get the channel pair power for this MBA (add on 1 since value will get truncated)
+	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
+	{
+	    o_channel_pair_power = o_channel_pair_power + l_channel_power_array[l_port];
+	    if (l_channel_power_array_integer[l_port] > 0)
+	    {
+		l_channel_power_array_integer[l_port] = (int)l_channel_power_array[l_port] + 1;
+	    }
+	}
+	FAPI_DBG("Channel Pair Power %4.2f cW]", o_channel_pair_power);
+
+	if (o_channel_pair_power > 0)
+	{
+	    l_channel_pair_power_integer = (int)o_channel_pair_power + 1;
+	}
+
+// Update output attributes
+	rc = FAPI_ATTR_SET(ATTR_MSS_DIMM_MAXPOWER, &i_target_mba, l_dimm_power_array_integer);
+	if(rc) return rc;
+	rc = FAPI_ATTR_SET(ATTR_MSS_CHANNEL_PAIR_MAXPOWER, &i_target_mba, l_channel_pair_power_integer);
+	if(rc) return rc;
+
+	return rc;
+    }
+
+
+} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
new file mode 100644
index 000000000..ee9398e70
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
@@ -0,0 +1,104 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_throttle_to_power.H,v 1.3 2012/10/15 13:05:23 pardeik Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_throttle_to_power.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2011
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : mss_throttle_to_power.H
+// *! DESCRIPTION : see additional comments below
+// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
+// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
+// *! ADDITIONAL COMMENTS :
+//
+// Header file for mss_throttle_to_power.
+//
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
+//   1.2   | pardeik  |03-APR-12| use mba target instead of mbs
+//   1.1   | pardeik  |01-DEC-11| First Draft.
+
+
+
+#ifndef MSS_THROTTLE_TO_POWER_H_
+#define MSS_THROTTLE_TO_POWER_H_
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+#include <fapi.H>
+
+typedef fapi::ReturnCode (*mss_throttle_to_power_FP_t)(const fapi::Target & i_target_mba);
+
+typedef fapi::ReturnCode (*mss_throttle_to_power_calc_FP_t)(
+						const fapi::Target &i_target_mba,
+						uint32_t i_throttle_n_per_mba,
+						uint32_t i_throttle_n_per_chip,
+						uint32_t i_throttle_d,
+						float &channel_pair_power
+						);
+
+extern "C"
+{
+
+//------------------------------------------------------------------------------
+// @brief mss_throttle_to_power(): This function will get the throttle attributes and call another function to determine the dimm and channel pair power based on those throttles
+//
+// @param    const fapi::Target &i_target_mba:  MBA Target
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
+
+//------------------------------------------------------------------------------
+// @brief mss_throttle_to_power_calc(): This function will calculate the dimm and channel pair power and update attributes with the power values
+//
+// @param    const fapi::Target &i_target_mba:  MBA Target
+// @param    uint32_t i_throttle_n_per_mba:  Throttle value for cfg_nm_n_per_mba
+// @param    uint32_t i_throttle_n_per_chip:  Throttle value for cfg_nm_n_per_chip
+// @param    uint32_t i_throttle_d:  Throttle value for cfg_nm_m
+// @param    float &o_channel_pair_power:  channel pair power at these throttle settings
+//
+// @return fapi::ReturnCode
+//------------------------------------------------------------------------------
+
+    fapi::ReturnCode mss_throttle_to_power_calc(
+						const fapi::Target &i_target_mba,
+						uint32_t i_throttle_n_per_mba,
+						uint32_t i_throttle_n_per_chip,
+						uint32_t i_throttle_d,
+						float &channel_pair_power
+						);
+
+} // extern "C"
+
+#endif // MSS_THROTTLE_TO_POWER_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C
index 63162d0d7..cfaec3cc1 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_freq.C,v 1.17 2012/07/17 13:24:13 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C $              */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_freq.C,v 1.18 2012/09/07 22:22:08 jdsloat Exp $
 /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */
 
 //------------------------------------------------------------------------------
@@ -58,6 +57,7 @@
 //  1.15   | jdsloat  | 06/04/12 | Added a Configuration check
 //  1.16   | jdsloat  | 06/08/12 | Updates per Firware request
 //  1.17   | bellows  | 07/16/12 | added in Id tag
+//  1.18   | jdsloat  | 09/07/12 | Added FTB offset to TAA and TCK
 //
 // This procedure takes CENTAUR as argument.  for each DIMM (under each MBA)
 // DIMM SPD attributes are read to determine optimal DRAM frequency
@@ -95,12 +95,18 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb)
   std::vector<fapi::Target> l_dimm_targets;
   uint8_t l_spd_mtb_dividend=0;
   uint8_t l_spd_mtb_divisor=0;
+  uint8_t l_spd_ftb_dividend=0;
+  uint8_t l_spd_ftb_divisor=0;
   uint32_t l_dimm_freq_calc=0;
   uint32_t l_dimm_freq_min=9999;
   uint8_t l_spd_min_tck_MTB=0;
+  uint8_t l_spd_tck_offset_FTB=0;
+  uint8_t l_spd_tck_offset=0;
   uint32_t l_spd_min_tck=0;
   uint32_t l_spd_min_tck_max=0;
   uint8_t  l_spd_min_taa_MTB=0;
+  uint8_t  l_spd_taa_offset_FTB=0;
+  uint8_t  l_spd_taa_offset=0;
   uint32_t l_spd_min_taa=0;
   uint32_t l_spd_min_taa_max=0;
   uint32_t l_selected_dimm_freq=0;
@@ -195,10 +201,34 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb)
 	      FAPI_ERR("Unable to read the SPD number of ranks");
 	      break;
 	  }
+	  l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TAAMIN,  &l_dimm_targets[j], l_spd_taa_offset_FTB); if(l_rc) return l_rc;
+	  if (l_rc)
+	  {
+	      FAPI_ERR("Unable to read the SPD TAA offset (FTB)");
+	      break;
+	  }
+	  l_rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN,  &l_dimm_targets[j], l_spd_tck_offset_FTB); if(l_rc) return l_rc;
+	  if (l_rc)
+	  {
+	      FAPI_ERR("Unable to read the SPD TCK offset (FTB)");
+	      break;
+	  }
+	  l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND,  &l_dimm_targets[j], l_spd_ftb_dividend); if(l_rc) return l_rc;
+	  if (l_rc)
+	  {
+	      FAPI_ERR("Unable to read the SPD FTB dividend");
+	      break;
+	  }
+	  l_rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR,  &l_dimm_targets[j], l_spd_ftb_divisor); if(l_rc) return l_rc;
+	  if (l_rc)
+	  {
+	      FAPI_ERR("Unable to read the SPD FTB divisor");
+	      break;
+	  }
 
 	  cur_dimm_spd_valid_u8array[cur_mba_port][cur_mba_dimm] = MSS_FREQ_VALID;
 
-	  if ((l_spd_min_tck_MTB == 0)||(l_spd_mtb_dividend == 0)||(l_spd_mtb_divisor == 0)||(l_spd_min_taa_MTB == 0))
+	  if ((l_spd_min_tck_MTB == 0)||(l_spd_mtb_dividend == 0)||(l_spd_mtb_divisor == 0)||(l_spd_min_taa_MTB == 0)||(l_spd_ftb_dividend == 0)||(l_spd_ftb_divisor == 0))
 	  {
 	      //Invalid due to the fact that JEDEC dictates that these should be non-zero.
 	      FAPI_ERR("Invalid data recieved from SPD within MTB Dividend, MTB Divisor, TCK Min, or TAA Min");
@@ -210,6 +240,34 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb)
 	  // Frequency listed with multiplication of 2 as clocking data on both +- edges
 	  l_spd_min_tck =  ( 1000 * l_spd_min_tck_MTB * l_spd_mtb_dividend ) / l_spd_mtb_divisor;
 	  l_spd_min_taa =  ( 1000 * l_spd_min_taa_MTB * l_spd_mtb_dividend ) / l_spd_mtb_divisor;
+
+	  // Adjusting by tck offset -- tck offset represented in 2's compliment as it could be positive or negative adjustment
+	  // No multiplication of 1000 as it is already in picoseconds.
+	  if (l_spd_tck_offset_FTB & 0x80)
+	  {
+	      l_spd_tck_offset_FTB = ~( l_spd_tck_offset_FTB ) + 1;
+	      l_spd_tck_offset = (l_spd_tck_offset_FTB  * l_spd_ftb_dividend )  / l_spd_ftb_divisor;
+	      l_spd_min_tck =  l_spd_min_tck - l_spd_tck_offset;
+	  }
+	  else
+	  {
+	      l_spd_tck_offset = (l_spd_tck_offset_FTB  * l_spd_ftb_dividend )  / l_spd_ftb_divisor;
+	      l_spd_min_tck =  l_spd_min_tck + l_spd_tck_offset;
+	  }
+
+	  // Adjusting by taa offset -- taa offset represented in 2's compliment as it could be positive or negative adjustment
+	  if (l_spd_taa_offset_FTB & 0x80)
+	  {
+	      l_spd_taa_offset_FTB = ~( l_spd_taa_offset_FTB) + 1;
+	      l_spd_taa_offset = (l_spd_taa_offset_FTB  * l_spd_ftb_dividend )  / l_spd_ftb_divisor;
+	      l_spd_min_taa =  l_spd_min_taa - l_spd_taa_offset;
+	  }
+	  else
+	  {
+	      l_spd_taa_offset = (l_spd_taa_offset_FTB  * l_spd_ftb_dividend )  / l_spd_ftb_divisor;
+	      l_spd_min_taa =  l_spd_min_taa + l_spd_taa_offset;
+	  }
+
 	  if ((l_spd_min_tck == 0)||(l_spd_min_taa == 0))
 	  {
 	      //Invalid due to the fact that JEDEC dictates that these should be non-zero.
diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C
index 8aa152e37..3122a28a1 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: mss_volt.C,v 1.11 2012/07/17 13:24:49 bellows Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_volt/mss_volt.C $              */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_volt.C,v 1.12 2012/10/18 14:46:36 jdsloat Exp $
 /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */
 
 //------------------------------------------------------------------------------
@@ -53,6 +52,7 @@
 //  1.9    | jdsloat  | 05/08/12 | Removed debug message
 //  1.10   | jdsloat  | 05/09/12 | Fixed typo
 //  1.11   | bellows  | 07/16/12 | added in Id tag
+//  1.11   | jdsloat  | 10/18/12 | Added check for violation of tolerant voltages of non-functional dimms.
 
 // This procedure takes a vector of Centaurs behind a voltage domain,
 // reads in supported DIMM voltages from SPD and determines optimal
@@ -66,10 +66,18 @@
 #include <fapi.H>
 #include <mss_volt.H>
 
+//----------------------------------------------------------------------
+//  Constants
+//----------------------------------------------------------------------
+const uint32_t MAX_TOLERATED_VOLT = 1500;
+const uint32_t MAX_TOLERATED_DDR3_VOLT = 1500;
+const uint32_t MAX_TOLERATED_DDR4_VOLT = 1200;
+
 fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
 {
 
   fapi::ReturnCode l_rc;
+  uint8_t l_dimm_functionality=0;
   uint8_t l_spd_dramtype=0;
   uint8_t l_spd_volts=0;
   uint8_t l_spd_volts_all_dimms=0x06;  //start assuming all voltages supported
@@ -77,6 +85,7 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
   uint8_t l_dram_ddr4_found_flag=0;
 
   uint32_t l_selected_dram_voltage=0;  //this gets written into all centaurs when done.
+  uint32_t l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; //initially set to the max tolerated voltage
 
   // Iterate through the list of centaurs
   for (uint32_t i=0; i < i_targets_memb.size(); i++)
@@ -90,7 +99,7 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
 	{
       std::vector<fapi::Target> l_dimm_targets;
 	  // Get a vector of DIMM targets
-	  l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets);
+	  l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT);
 	  if (l_rc) return l_rc;
 	  for (uint32_t k=0; k < l_dimm_targets.size(); k++)
 	    {
@@ -98,6 +107,8 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
 	      if (l_rc) return l_rc;
 	      l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_dimm_targets[k], l_spd_volts);
 	      if (l_rc) return l_rc;
+	      l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality);
+	      if (l_rc) return l_rc;
 
 	      // spd_volts:  bit0= NOT 1.5V bit1=1.35V bit2=1.25V, assume a 1.20V in future for DDR4
 	      // check for supported voltage/dram type combo  DDR3=12, DDR4=13
@@ -116,8 +127,13 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
 		  FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE);
 		  return l_rc;
 		}
-	      //AND dimm voltage capabilities together to find aggregate voltage support on all dimms
-	      l_spd_volts_all_dimms = l_spd_volts_all_dimms & l_spd_volts;
+
+	      if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL)
+	      {
+	          //AND dimm voltage capabilities together to find aggregate voltage support on all dimms
+		  l_spd_volts_all_dimms = l_spd_volts_all_dimms & l_spd_volts;
+	      }
+
 	    }
 	}
     }      
@@ -126,37 +142,92 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb)
   // note: only support DDR3=1.35V and DDR4=1.2xV
 
   if (l_dram_ddr3_found_flag && l_dram_ddr4_found_flag)
-    {
+  {
       FAPI_ERR("mss_volt: DDR3 and DDR4 mixing not allowed");
       FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED);
       return l_rc;
-    }
+  }
   if (l_dram_ddr3_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35))
-    {
+  {
       l_selected_dram_voltage=1350;
-    }
+  }
   else if (l_dram_ddr4_found_flag && ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X) == fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X))
-    {
+  {
       l_selected_dram_voltage=1200;
-    }
+  }
   else if ((l_spd_volts_all_dimms & fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5) != fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5)
-    {
+  {
       l_selected_dram_voltage=1500;
-    }
+  }
   else
-    {
+  {
       FAPI_ERR("One or more DIMMs do not support required voltage for DIMM type");
       FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE);
       return l_rc;
-    }
+  }
+
+/*  if( l_selected_dram_voltage > l_supported_dram_voltage)
+  {
+      FAPI_INF( "Selected Voltage larger than highest supported voltage.  Selected Voltage: %d Supported Voltage: %d ", l_selected_dram_voltage, l_supported_dram_voltage);
+      FAPI_INF( "Using supported Voltage.");
+      l_selected_dram_voltage = l_supported_dram_voltage;
+  }
+*/
+
+  // Must check to see if we violate Tolerent voltages of Non-functional Dimms
+  // If so we must error/deconfigure on the centaur level.
+  // Iterate through the list of centaurs
+  for (uint32_t i=0; i < i_targets_memb.size(); i++)
+  {
+      l_tolerated_dram_voltage = MAX_TOLERATED_VOLT; // using 1.5 as this is the largest supported voltage
+      std::vector<fapi::Target> l_mbaChiplets;
+      // Get associated MBA's on this centaur
+      l_rc=fapiGetChildChiplets(i_targets_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
+      if (l_rc) return l_rc;
+      for (uint32_t j=0; j < l_mbaChiplets.size(); j++)
+      {
+	  std::vector<fapi::Target> l_dimm_targets;
+          // Get a vector of DIMM targets
+	  l_rc = fapiGetAssociatedDimms(l_mbaChiplets[j], l_dimm_targets, fapi::TARGET_STATE_PRESENT);
+	  if (l_rc) return l_rc;
+	  for (uint32_t k=0; k < l_dimm_targets.size(); k++)
+	  {
+	      l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_dimm_targets[k], l_dimm_functionality);
+	      if (l_rc) return l_rc;
+
+	      if(l_dimm_functionality == fapi::ENUM_ATTR_FUNCTIONAL_NON_FUNCTIONAL)
+	      {
+		  if ( (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) && (l_tolerated_dram_voltage > MAX_TOLERATED_DDR3_VOLT) )
+		  {
+		      l_tolerated_dram_voltage =  MAX_TOLERATED_DDR3_VOLT;
+		  }
+		  if ( (l_spd_dramtype == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) && (l_tolerated_dram_voltage > MAX_TOLERATED_DDR4_VOLT) )
+		  {
+		      l_tolerated_dram_voltage =  MAX_TOLERATED_DDR4_VOLT;
+		  }
+	      }
+	  }
+      }
+
+      if ( l_tolerated_dram_voltage < l_selected_dram_voltage )
+      {
+	  FAPI_ERR("One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.");
+	  FAPI_ERR("Deconfiguring the associated Centaur.");
+	  const fapi::Target & MASTER_CHIP = i_targets_memb[i];
+	  FAPI_SET_HWP_ERROR(l_rc, RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION);
+	  return l_rc;
+      }
+  }
+
 
   // Iterate through the list of centaurs again, to update ATTR
   for (uint32_t i=0; i < i_targets_memb.size(); i++)
-    {
+  {
       l_rc = FAPI_ATTR_SET(ATTR_MSS_VOLT, &i_targets_memb[i], l_selected_dram_voltage);
       FAPI_INF( "mss_volt calculation complete.  MSS_VOLT: %d", l_selected_dram_voltage);
       if (l_rc) return l_rc;
-    }
+  }
+
   return l_rc;
 }
 
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index c52c348bc..ebb2227cb 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -408,7 +408,18 @@ firmware notes: none</description>
 <attribute>
     <id>ATTR_EFF_CKE_MAP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke consumer: various firmware notes: none</description>
+    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_SPCKE_MAP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
     <valueType>uint8</valueType>
     <writeable/>
     <odmVisable/>
@@ -479,12 +490,54 @@ firmware notes: none</description>
     <description>DRAM Write Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value
+This is for DDR3</description>
     <valueType>uint32</valueType>
     <enum>VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_DRAM_WRDDR4_VREF</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DRAM Write Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value
+This is for DDR4
+The value is from 0 to 50</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF to use on the WR Schmoo.  The LSB corresponds to the highest WR Vref</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -493,26 +546,31 @@ firmware notes: none</description>
     <description>Centaur DQ and DQS Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
-    <enum>OHM24 = 24, OHM30 = 30, OHM34 = 34, OHM40 = 40</enum>
+    <enum>OHM24_FFE0, OHM30_FFE0,
+OHM30_FFE480, OHM30_FFE240, OHM30_FFE160, OHM30_FFE120, OHM34_FFE0, OHM34_FFE480, OHM34_FFE240, OHM34_FFE160, OHM34_FFE120, OHM40_FFE0, OHM40_FFE480, OHM40_FFE240, OHM40_FFE160, OHM40_FFE120</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
-    <id>ATTR_EFF_CEN_DRV_IMP_CMD</id>
+    <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Centaur Command Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+    <description>Centaur Address Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
     <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -521,12 +579,92 @@ firmware notes: none</description>
     <description>Centaur Control Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_CLK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Clock Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Spare Clock Drive Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
     <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible driver strengths and start with the first value down to the last (largest) impedance as the LSB of the 8 bit field.
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+    <persistRuntime/>
 </attribute>
 
 <attribute>
@@ -535,12 +673,25 @@ firmware notes: none</description>
     <description>Centaur DQ and DQS Receiver Impedance Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
     <enum>OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which impedance values can be used and tested in a timing test.  The bits have a one to one correspondence to the possible receiver termination and start with the first value down to the last (largest) impedance as the LSB of the 32 bit field.</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -549,24 +700,79 @@ firmware notes: none</description>
     <description>Centaur DQ and DQS Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
-    <id>ATTR_EFF_CEN_SLEW_RATE_CMD</id>
+    <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Centaur Command Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+    <description>Centaur Address Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Clock Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Centaur Spare Clock Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
+creator: mss_eff_cnfg_termination
+consumer: various
+firmware notes: none
+This is the nominal value</description>
+    <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7
+</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -575,11 +781,74 @@ firmware notes: none</description>
     <description>Centaur Control Slew Rate Used in various locations and is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint8</valueType>
+    <enum>SLEW_3V_NS = 3,
+SLEW_4V_NS = 4,
+SLEW_5V_NS = 5,
+SLEW_6V_NS = 6,
+SLEW_MAXV_NS = 7
+</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Slew Rates that can be selected during timing adjustments.  The fastest rate is the LSB</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -588,12 +857,25 @@ firmware notes: none</description>
     <description>Centaur Read Vref. Used in various locations and is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg_termination
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+This is the nominal value</description>
     <valueType>uint32</valueType>
     <enum>VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_RD_VREF_SCHMOO</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Enables for which VREF value can be used in timing adjustments.  The highest voltage corresponds to the LSB</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
 </attribute>
 
 <attribute>
@@ -1097,10 +1379,27 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
+    <id>ATTR_EFF_SCHMOO_ADDR_MODE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Specifies the schmoo mode to use during draminit_train_adv</description>
+    <valueType>uint8</valueType>
+    <enum>FEW_ADDR= 0, QUARTER_ADDR = 1, HALF_ADDR = 2, FULL_ADDR = 3</enum>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
     <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>Specifies the schmoo test to run during draminit_train_adv. Bit wise.</description>
     <valueType>uint8</valueType>
+    <enum> NONE = 0x00,
+ MCBIST = 0x01,
+ WR_EYE = 0x02,
+ RD_EYE = 0x04,
+ WR_DQS = 0x08,
+ RD_DQS = 0x10</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
@@ -1111,6 +1410,13 @@ firmware notes: none</description>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>Specifies the schmoo parameters to use during draminit_train_adv. Bit wise.</description>
     <valueType>uint8</valueType>
+    <enum> PARAM_NONE = 0x00,
+ DELAY_REG = 0x01,
+ DRV_IMP = 0x02,
+ SLEW_RATE = 0x04,
+ WR_VREF = 0x08,
+ RD_VREF = 0x10,
+ RCV_IMP = 0x20</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
@@ -1193,7 +1499,7 @@ firmware notes: none</description>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>Specifies the memory topology type. See centaur workbook.</description>
     <valueType>uint8</valueType>
-    <enum>UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12, TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25</enum>
+    <enum>UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
@@ -1257,86 +1563,65 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_THROTTLE_NUMERATOR</id>
+    <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Each DIMM can have a throttle amount.  This is the numerator
-creator: mss_eff_cnfg
-consumer: mc_config
-firmware notes: none</description>
+    <description>This is the throttle numerator setting for cfg_nm_n_per_mba creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
-    <array> 2 2</array>
     <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_THROTTLE_DENOMINATOR</id>
+    <id>ATTR_MSS_MEM_THROTTLE_DENOMINATOR</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Each DIMM can have a throttle amount.  This is the denominator
-creator: mss_eff_cnfg
-consumer: mc_config
-firmware notes: none</description>
+    <description>This is the throttle denominator setting for cfg_nm_m creator: mss_eff_cnfg consumer: mc_config  firmware notes: none</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
-    <array> 2 2</array>
     <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR</id>
+    <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>This is a channel throttle amount
-this is the numerator
-creator: mss_eff_cnfg
-consumer: mc config
-firmware notes:none</description>
+    <description>This is the throttle numerator setting for cfg_nm_n_per_chip creator: mss_eff_cnfg consumer: mc_config firmware notes: none</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
-    <array> 2</array>
     <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR</id>
+    <id>ATTR_MSS_MEM_WATT_TARGET</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>This is a channel throttle amount
-this is the denominator
-creator: mss_eff_cnfg
-consumer: mc config
-firmware notes:none</description>
+    <description>Total memory power limit in cW for the dimms on the memory channel pair. Used to compute the throttles on the channel and/or dimms creator: unknown consumer: mss_eff_config firmware notes: none</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
-    <array> 2</array>
     <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_WATT_TARGET</id>
+    <id>ATTR_MSS_POWER_SLOPE</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Total memory watts upper limit for this memory channel. Used to compute the throttles on the channel and/or dimms
-creator: unknown
-consumer: mss_eff_config
-firmware notes: none</description>
+    <description>Master Power slope value for dimm</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
     <odmChangeable/>
-    <array> 2</array>
+    <array> 2 2</array>
     <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_POWER_SLOPE</id>
+    <id>ATTR_MSS_POWER_SLOPE2</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Power slope value for dimm in double drop config</description>
+    <description>Supplier Power slope value for dimm</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
@@ -1348,7 +1633,19 @@ firmware notes: none</description>
 <attribute>
     <id>ATTR_MSS_POWER_INT</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>Power intercept value for dimm in double drop config</description>
+    <description>Master Power intercept value for dimm</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 2</array>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_POWER_INT2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Supplier Power intercept value for dimm</description>
     <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
@@ -1394,6 +1691,17 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
+    <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Bandwidth in GBs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
     <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>Channel Max Bandwidth MRs output from thermal procedures</description>
@@ -1406,6 +1714,17 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
+    <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Bandwidth MRs output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
     <id>ATTR_MSS_DIMM_MAXPOWER</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>DIMM Max Power output from thermal procedures</description>
@@ -1430,26 +1749,103 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
-    <valueType>uint8</valueType>
-    <platInit/>
+    <id>ATTR_MSS_CHANNEL_PAIR_MAXPOWER</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Channel Pair Max Power output from thermal procedures</description>
+    <valueType>uint32</valueType>
+    <writeable/>
     <odmVisable/>
     <odmChangeable/>
+    <persistRuntime/>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_MEMSIZE_MBA</id>
+    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-    <description>At the MBA level, how much memory is available</description>
-    <valueType>uint64</valueType>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_mba</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Runtime throttle denominator setting for cfg_nm_m</description>
+    <valueType>uint32</valueType>
     <writeable/>
     <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_chip</description>
+    <valueType>uint32</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize
+
+<attribute>
+    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_mba</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook safe mode throttle value for denominator cfg_nm_m</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
     <persistRuntime/>
 </attribute>
 
 <attribute>
+    <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_chip</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook Thermal Memory Power Limit</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+-->
+
+<attribute>
+    <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
+    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
+    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
     <id>ATTR_MSS_MCA_HASH_MODE</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>This dial sets up the centaur hash mode policy..   See Centaur workbook chapter 5.
@@ -1484,10 +1880,14 @@ Hash modes values are 0,1 and 2. Used in the intifile </description>
 <attribute>
     <id>ATTR_MSS_CACHE_ENABLE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Value of on or off.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.</description>
+    <description>Value of on or off.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A means only A is enabled and HALF_B means only B is enabled. These values are set in the mss_get_cen_ecid.</description>
     <valueType>uint8</valueType>
-    <enum>OFF = 0, ON = 1</enum>
+    <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5</enum>
+    <!-- TODO RTC 58012. This attribute is not platInit in the master file in eKB/cvs.
+         It is setup by the mss_get_cen_ecid HWP. Before that HWP is integrated, this
+         attribute is platInit and Hostboot firmware defaults the value to ON -->
     <platInit/>
+    <writeable/>
     <odmVisable/>
     <odmChangeable/>
 </attribute>
@@ -1553,20 +1953,6 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-    <id>ATTR_MSS_MCS_GROUP</id>
-    <targetType>TARGET_TYPE_PROC_CHIP</targetType>
-    <description>Data Structure from eff grouping to setup bars to help determine different groups
-   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
- //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
-Measured in GB - THIS ATTRIBUTE WILL EVENTUALLY BE OBSOLETE.  USE MSS_MCS_GROUP_32</description>
-    <valueType>uint8</valueType>
-    <writeable/>
-    <odmVisable/>
-    <odmChangeable/>
-    <array>16 16</array>
-</attribute>
-
-<attribute>
     <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>A bit vector (per Dean's request) specifying if a DIMM is functional.  DIMM attributes, such as SIZE, are qualified by this bit vector.  The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.  0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.  A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
@@ -1608,6 +1994,656 @@ bits6:7  will be consumed together to form COARSE_LVL. </description>
     <persistRuntime/>
 </attribute>
 
+<attribute>
+    <id>ATTR_MSS_SLEW_RATE_DATA</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is port, the second is the impedance of 24,30,34, and 40 Ohms.  The 3rd dimension is the rate: 3,4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 4 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_SLEW_RATE_ADR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances.  The first dimension is the port.  The second is the impedance of 15, 20, 30 and 40 Ohms.  The 3rd dimension is the rate:3, 4,5 or 6 V/ns.  Computed and sent to the correct data blocks in phy_reset.  Also used in advanced training</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2 4 4</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_ECID</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
+Created from running the mss_get_cen_ecid.C</description>
+    <valueType>uint64</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_ALLOW_SINGLE_PORT</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes.  Used in eff_config</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<!-- Comment out until HWP integrated that uses this attribute. Platform needs to initialize
+     At first glance, this looks like it could be a Chip EC Feature Attribute
+
+<attribute>
+    <id>ATTR_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will continue with processing other DP18 blocks, if one fails.  In DD2, this attribute must be set to false so that the failing hardware (centaur) is marked as bad and not the DIMM.  Set by firwmare using the EC level or by a MRW</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+-->
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CLK_P0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CLK_P1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CLK_P0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CLK_P1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A4</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A5</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A6</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A7</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A8</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A9</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A10</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A11</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A12</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A13</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A14</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_A15</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_BA0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_BA1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_BA2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_CASN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_RASN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_CMD_WEN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_PAR</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M_ACTN</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CKE0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CKE1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CKE2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CKE3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CSN0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CSN1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CSN2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_CSN3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_ODT0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M0_CNTL_ODT1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CKE0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CKE1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CKE2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CKE3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CSN0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CSN1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CSN2</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_CSN3</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_ODT0</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD.  This controls the IO M1_CNTL_ODT1</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <array> 2</array>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_DQS_SWIZZLE_TYPE</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1.  Additional types maybe defined if new boards have even different DQS swizzle features</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </attributes>
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
index dfdd0f666..ae76464fe 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
@@ -643,7 +643,10 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
             FAPI_DBG("Starting A bus chiplet clocks ...");
             rc = proc_start_clocks_generic_chiplet(
                 i_target,
-                A_BUS_CHIPLET_0x09000000,
+                // TODO MJJ Updated to A_BUS_CHIPLET_0x08000000 to match new
+                // p8_scom_addresses, this will go away when this HWP is
+                // refreshed
+                A_BUS_CHIPLET_0x08000000,
                 PROC_START_CLOCKS_CHIPLETS_ABUS_CLK_STATUS_REG_EXP);
             if (rc)
             {
@@ -656,7 +659,10 @@ fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
             FAPI_DBG("Starting PCIE chiplet clocks ...");
             rc = proc_start_clocks_generic_chiplet(
                 i_target,
-                PCIE_CHIPLET_0x08000000,
+                // TODO MJJ Updated to PCIE_CHIPLET_0x09000000 to match new
+                // p8_scom_addresses, this will go away when this HWP is
+                // refreshed
+                PCIE_CHIPLET_0x09000000,
                 PROC_START_CLOCKS_CHIPLETS_PCIE_CLK_STATUS_REG_EXP);
             if (rc)
             {
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 8d212a33d..331765b58 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -88,6 +88,7 @@ HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/proc_mvpd_attributes.xml \
                      hwp/ei_bus_attributes.xml \
                      hwp/chip_ec_attributes.xml \
+                     hwp/centaur_ec_attributes.xml \
                      hwp/common_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_memory_attributes.xml \
                      hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml \
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 2e876e046..666bb0d83 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -970,1560 +970,6 @@
 </attribute>
 
 <attribute>
-    <id>MSS_VOLT</id>
-    <description>DRAM Voltage. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_VOLT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_FREQ</id>
-    <description>Frequency of memory channel in MHz. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_FREQ</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_DIMM_MFG_ID_CODE</id>
-    <description>DIMM Manufacturer ID Code. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DIMM_MFG_ID_CODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_RANKS_CONFIGED</id>
-    <description>DIMM ranks configured. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_NUM_RANKS_PER_DIMM</id>
-    <description>Number of ranks per DIMM. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_TYPE</id>
-    <description>Type of DIMM. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_TYPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_WIDTH</id>
-    <description>DRAM Device Width. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_WIDTH</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_GEN</id>
-    <description>DRAM Generation. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_GEN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_PRIMARY_RANK_GROUP0</id>
-    <description>Primary RankGroup0. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_PRIMARY_RANK_GROUP1</id>
-    <description>Primary RankGroup1. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_PRIMARY_RANK_GROUP2</id>
-    <description>Primary RankGroup2. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_PRIMARY_RANK_GROUP3</id>
-    <description>Primary RankGroup3. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SECONDARY_RANK_GROUP0</id>
-    <description>Secondary RankGroup0. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SECONDARY_RANK_GROUP1</id>
-    <description>Secondary RankGroup1. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SECONDARY_RANK_GROUP2</id>
-    <description>Secondary RankGroup2. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SECONDARY_RANK_GROUP3</id>
-    <description>Secondary RankGroup3. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_TERTIARY_RANK_GROUP0</id>
-    <description>Tertiary RankGroup0. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_TERTIARY_RANK_GROUP1</id>
-    <description>Tertiary RankGroup1. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_TERTIARY_RANK_GROUP2</id>
-    <description>Tertiary RankGroup2. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_TERTIARY_RANK_GROUP3</id>
-    <description>Tertiary RankGroup3. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_QUATERNARY_RANK_GROUP0</id>
-    <description>Quaternary RankGroup0. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_QUATERNARY_RANK_GROUP1</id>
-    <description>Quaternary RankGroup1. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_QUATERNARY_RANK_GROUP2</id>
-    <description>Quaternary RankGroup2. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_QUATERNARY_RANK_GROUP3</id>
-    <description>Quaternary RankGroup3. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_ODT_RD</id>
-    <description>Rank Read ODT. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_ODT_RD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_ODT_WR</id>
-    <description>Rank Write ODT. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_ODT_WR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_RON</id>
-    <description>DRAM Ron. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RON</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_RTT_NOM</id>
-    <description>DRAM Rtt_Nom. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RTT_NOM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_RTT_WR</id>
-    <description>DRAM Rtt_WR. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RTT_WR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_WR_VREF</id>
-    <description>DRAM Write Vref. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_WR_VREF</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_DRV_IMP_DQ_DQS</id>
-    <description>Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_DRV_IMP_CMD</id>
-    <description>Centaur Command Drive Impedance. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_DRV_IMP_CMD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_DRV_IMP_CNTL</id>
-    <description>Centaur Control Drive Impedance. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_RCV_IMP_DQ_DQS</id>
-    <description>Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_SLEW_RATE_DQ_DQS</id>
-    <description>Centaur DQ and DQS Slew Rate. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_SLEW_RATE_CMD</id>
-    <description>Centaur Command Slew Rate. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_SLEW_RATE_CMD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_SLEW_RATE_CNTL</id>
-    <description>Centaur Control Slew Rate. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CEN_RD_VREF</id>
-    <description>Centaur Read Vref. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CEN_RD_VREF</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_SIZE</id>
-    <description>DIMM Size. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_SIZE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_SIZE_CONFIGED</id>
-    <description>Actual Configured DIMM Size. Initialized and used by HWPs.
-    </description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_SIZE_CONFIGED</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_DENSITY</id>
-    <description>DRAM Density. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_DENSITY</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRCD</id>
-    <description>DRAM RAS to CAS Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRCD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRRD</id>
-    <description>DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRRD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRP</id>
-    <description>DRAM Row Precharge Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRP</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRAS</id>
-    <description>DRAM ACT to Precharge Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRAS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRC</id>
-    <description>DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRC</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRFI</id>
-    <description>Refresh Interval. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRFI</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRFC</id>
-    <description>DRAM Refresh Recovery Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRFC</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TWTR</id>
-    <description>DRAM Internal Write to Read Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TWTR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TRTP</id>
-    <description>DRAM Internal Read to Precharge Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TRTP</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TFAW</id>
-    <description>DRAM Four ACT Window Delay. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TFAW</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_BL</id>
-    <description>DRAM Burst Length. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_BL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_CL</id>
-    <description>DRAM CAS Latency. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_CL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_AL</id>
-    <description>DRAM Additive Latency. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_AL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_CWL</id>
-    <description>DRAM CAS Write Latency. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_CWL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_RBT</id>
-    <description>DRAM Read Burst Type. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RBT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TM</id>
-    <description>DRAM Test Mode. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_DLL_RESET</id>
-    <description>DRAM DLL Reset. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_DLL_RESET</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_WR</id>
-    <description>DRAM Write Recovery. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_WR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_DLL_PPD</id>
-    <description>DRAM DLL Precharge PD. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_DLL_PPD</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_DLL_ENABLE</id>
-    <description>DRAM DLL Enable. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_DLL_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_TDQS</id>
-    <description>DRAM TDQS. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_TDQS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_WR_LVL_ENABLE</id>
-    <description>DRAM Write Level Enable. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_OUTPUT_BUFFER</id>
-    <description>DRAM output buffer. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_PASR</id>
-    <description>DRAM Partial Array Self-Refresh. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_PASR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_ASR</id>
-    <description>DRAM Auto Self-Refresh. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_ASR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_SRT</id>
-    <description>DRAM Self-Refresh Temperature Range. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_SRT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_MPR_LOC</id>
-    <description>Multi Purpose Register Location. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_MPR_LOC</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_MPR_MODE</id>
-    <description>Multi Purpose Register Mode. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_MPR_MODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_RCD_CNTL_WORD_0_15</id>
-    <description>DIMM RCD Control Word. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint64_t>
-            <default>0</default>
-        </uint64_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_MODE</id>
-    <description>Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_MODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_TEST_VALID</id>
-    <description>Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_PARAM_VALID</id>
-    <description>Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_PARAM_VALID</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_MEMCAL_INTERVAL</id>
-    <description>Specifies the memcal interval in clocks. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_MEMCAL_INTERVAL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_ZQCAL_INTERVAL</id>
-    <description>Specifies the zqcal interval in clocks. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_ZQCAL_INTERVAL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_THROTTLE_NUMERATOR</id>
-    <description>DIMM throttle numerator. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_THROTTLE_NUMERATOR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_THROTTLE_DENOMINATOR</id>
-    <description>DIMM throttle denominator. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_THROTTLE_DENOMINATOR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_THROTTLE_CHANNEL_NUMERATOR</id>
-    <description>Channel throttle numerator. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_THROTTLE_CHANNEL_DENOMINATOR</id>
-    <description>Channel throttle denominator. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_WATT_TARGET</id>
-    <description>Channel total memory watts. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_WATT_TARGET</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_POWER_SLOPE</id>
-    <description>DIMM Power slope value. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_POWER_SLOPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_POWER_INT</id>
-    <description>DIMM Power intercept value. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_POWER_INT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_DIMM_MAXBANDWIDTH_GBS</id>
-    <description>DIMM Max Bandwidth in GBs. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_DIMM_MAXBANDWIDTH_MRS</id>
-    <description>DIMM Max Bandwidth in MRs. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id>
-    <description>Channel Max Bandwidth in GBs. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
-    <description>Channel Max Bandwidth MRs. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_DIMM_MAXPOWER</id>
-    <description>DIMM Max Power output. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_DIMM_MAXPOWER</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CHANNEL_MAXPOWER</id>
-    <description>Channel Max Power output. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CHANNEL_MAXPOWER</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MEMSIZE_MBA</id>
-    <description>At the MBA level, how much memory is available. Initialized by HWP.</description>
-    <simpleType>
-        <uint64_t>
-            <default>0</default>
-        </uint64_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MEMSIZE_MBA</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>EC</id>
     <description>attribute indicating the chip target's EC level</description>
     <simpleType>
@@ -3362,355 +1808,6 @@
 </attribute>
 
 <attribute>
-    <id>EFF_DRAM_BANKS</id>
-    <description>Number of DRAM banks. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_BANKS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_ROWS</id>
-    <description>Number of DRAM rows. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_ROWS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_COLS</id>
-    <description>Number of DRAM columns. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_COLS</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_RCD_IBT</id>
-    <description>DIMM RCD IBT. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_RCD_IBT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_RCD_MIRROR_MODE</id>
-    <description>DIMM RCD Mirror mode. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_RCD_MIRROR_MODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_IBM_TYPE</id>
-    <description>Specifies the memory topology type. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_IBM_TYPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_NUM_DROPS_PER_PORT</id>
-    <description>Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_NUM_DROPS_PER_PORT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_STACK_TYPE</id>
-    <description>Specifies the DRAM package type. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_STACK_TYPE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_NUM_MASTER_RANKS_PER_DIMM</id>
-    <description>Specifies the number of master ranks per DIMM. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_NUM_PACKAGES_PER_RANK</id>
-    <description>Specifies the number of DRAM packages per rank. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_NUM_PACKAGES_PER_RANK</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_NUM_DIES_PER_PACKAGE</id>
-    <description>Specifies the number of DRAM dies per package. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2</array><!-- [drop][port] -->
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_NUM_DIES_PER_PACKAGE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_SPARE_BYTE</id>
-    <description>This says that the system can have a 10th byte. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_SPARE_BYTE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MEM_MC_IN_GROUP</id>
-    <description>A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>8</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MEM_MC_IN_GROUP</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MCA_HASH_MODE</id>
-    <description>sets up the centaur hash mode policy. Mode values are 0, 1, and 2.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MCA_HASH_MODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id>
-    <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
-    <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CACHE_ENABLE</id>
-    <description>
-        Specifies if a Memory Buffer chip L4 cache is enabled or disabled
-        For good memory buffer chips, L4 is enabled
-        Firmware can set to disabled for a particular chip if the cache is
-          not functional
-        1 = enabled, 0 = disabled.
-    </description>
-    <simpleType>
-        <uint8_t>
-            <default>1</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CACHE_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_PREFETCH_ENABLE</id>
-    <description>Prefteching enable. 1 = enable, 0 = disable.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_PREFETCH_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CLEANER_ENABLE</id>
-    <description>L4 cleaner enable. 1 = enable, 0 = disable.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CLEANER_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id>
-    <description>override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>EI_BUS_RX_MSB_LSB_SWAP</id>
     <description>PRBS scramble pattern per lane on DMI bus for p8 and centaur.</description>
     <simpleType>
@@ -4254,245 +2351,6 @@
 <!-- ===== ===== End Memory Map ===== ===== ===== ===== ===== ===== -->
 
 <attribute>
-    <id>MSS_MCS_GROUP</id>
-    <description>Data Structure from eff grouping to setup bars to help determine different groups
-   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
- //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
-Measured in GB</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>16,16</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MCS_GROUP</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MCS_GROUP_32</id>
-    <description>Data Structure from eff grouping to setup bars to help determine different groups
-   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
- //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
-Measured in GB</description>
-    <simpleType>
-        <uint32_t>
-            <default>0</default>
-        </uint32_t>
-        <array>16,16</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MCS_GROUP_32</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
-    <description>A bit vector (per Dean's request) specifying if a DIMM is functional.  DIMM attributes, such as SIZE, are qualified by this bit vector.  The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.  0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.  A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
-This factors in functionality</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_INTERLEAVE_ENABLE</id>
-    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_CKE_MAP</id>
-    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke consumer: various firmware notes: none</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_CKE_MAP</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DIMM_SPARE</id>
-    <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DIMM_SPARE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
-    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
-    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
-    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
-    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
-    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_CAL_STEP_ENABLE</id>
-    <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
-[1] WR_LEVEL
-[2] DQS_ALIGN
-[3] RDCLK_ALIGN
-[4] READ_CTR
-[5] WRITE_CTR
-[6] COARSE_WR
-[7] COARSE_RD
-bits6:7  will be consumed together to form COARSE_LVL. </description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_CAL_STEP_ENABLE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>MSS_MEM_IPL_COMPLETE</id>
-    <description>A numerical number indicating if the memory procedures are complete.  written by mss_setup_bars when the bars are now functional in the processor.  </description>
-    <simpleType>
-        <uint8_t>
-            <default>0</default>
-        </uint8_t>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_MSS_MEM_IPL_COMPLETE</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
   <id>PROC_EPS_GB_PERCENTAGE</id>
   <description>
      firmware notes:
@@ -7951,4 +5809,3441 @@ firmware notes: Used as override attribute for pstate procedure
     </hwpfToHbAttrMap>
 </attribute>
 
+<!-- ===== Attributes supporting memory_attributes.xml HWPF Attributes ===== -->
+
+<attribute>
+    <id>MSS_VOLT</id>
+    <description>DRAM Voltage. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_VOLT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_FREQ</id>
+    <description>Frequency of memory channel in MHz. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_FREQ</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_MFG_ID_CODE</id>
+    <description>DIMM Manufacturer ID Code. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_MFG_ID_CODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_RANKS_CONFIGED</id>
+    <description>DIMM ranks configured. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_NUM_RANKS_PER_DIMM</id>
+    <description>Number of ranks per DIMM. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_TYPE</id>
+    <description>Type of DIMM. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_TYPE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WIDTH</id>
+    <description>DRAM Device Width. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WIDTH</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_GEN</id>
+    <description>DRAM Generation. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_GEN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_PRIMARY_RANK_GROUP0</id>
+    <description>Primary RankGroup0. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_PRIMARY_RANK_GROUP0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_PRIMARY_RANK_GROUP1</id>
+    <description>Primary RankGroup1. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_PRIMARY_RANK_GROUP1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_PRIMARY_RANK_GROUP2</id>
+    <description>Primary RankGroup2. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_PRIMARY_RANK_GROUP2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_PRIMARY_RANK_GROUP3</id>
+    <description>Primary RankGroup3. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_PRIMARY_RANK_GROUP3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SECONDARY_RANK_GROUP0</id>
+    <description>Secondary RankGroup0. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SECONDARY_RANK_GROUP0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SECONDARY_RANK_GROUP1</id>
+    <description>Secondary RankGroup1. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SECONDARY_RANK_GROUP1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SECONDARY_RANK_GROUP2</id>
+    <description>Secondary RankGroup2. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SECONDARY_RANK_GROUP2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SECONDARY_RANK_GROUP3</id>
+    <description>Secondary RankGroup3. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SECONDARY_RANK_GROUP3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_TERTIARY_RANK_GROUP0</id>
+    <description>Tertiary RankGroup0. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_TERTIARY_RANK_GROUP0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_TERTIARY_RANK_GROUP1</id>
+    <description>Tertiary RankGroup1. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_TERTIARY_RANK_GROUP1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_TERTIARY_RANK_GROUP2</id>
+    <description>Tertiary RankGroup2. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_TERTIARY_RANK_GROUP2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_TERTIARY_RANK_GROUP3</id>
+    <description>Tertiary RankGroup3. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_TERTIARY_RANK_GROUP3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_QUATERNARY_RANK_GROUP0</id>
+    <description>Quaternary RankGroup0. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_QUATERNARY_RANK_GROUP0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_QUATERNARY_RANK_GROUP1</id>
+    <description>Quaternary RankGroup1. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_QUATERNARY_RANK_GROUP1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_QUATERNARY_RANK_GROUP2</id>
+    <description>Quaternary RankGroup2. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_QUATERNARY_RANK_GROUP2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_QUATERNARY_RANK_GROUP3</id>
+    <description>Quaternary RankGroup3. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_QUATERNARY_RANK_GROUP3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_ODT_RD</id>
+    <description>Rank Read ODT. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_ODT_RD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_ODT_WR</id>
+    <description>Rank Write ODT. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_ODT_WR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RON</id>
+    <description>DRAM Ron. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RON</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RTT_NOM</id>
+    <description>DRAM Rtt_Nom. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RTT_NOM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RTT_WR</id>
+    <description>DRAM Rtt_WR. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RTT_WR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WR_VREF</id>
+    <description>DRAM Write Vref. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WR_VREF</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WRDDR4_VREF</id>
+    <description>DRAM Write Vref for DDR4. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WRDDR4_VREF</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WR_VREF_SCHMOO</id>
+    <description>Enables for which VREF to use on the WR Schmoo. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WR_VREF_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
+    <description>Enables for which VREF to use on the WR Schmoo for DDR4. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WRDDR4_VREF_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_DQ_DQS</id>
+    <description>Centaur DQ and DQS Drive Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_ADDR</id>
+    <description>Centaur Address Drive Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_CNTL</id>
+    <description>Centaur Control Drive Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array> 
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_CNTL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_CLK</id>
+    <description>Centaur Clock Drive Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_CLK</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_SPCKE</id>
+    <description>Centaur Spare Clock Drive Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_SPCKE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id>
+    <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_CLK_SCHMOO</id>
+    <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id>
+    <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_DRV_IMP_CNTL_SCHMOO</id>
+    <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_RCV_IMP_DQ_DQS</id>
+    <description>Centaur DQ and DQS Receiver Impedance. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id>
+    <description>Enables for which impedance values can be used and tested in a timing test. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_DQ_DQS</id>
+    <description>Centaur DQ and DQS Slew Rate. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_ADDR</id>
+    <description>Centaur Address Slew Rate. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_ADDR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_CLK</id>
+    <description>Centaur Clock Slew Rate. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_CLK</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_SPCKE</id>
+    <description>Centaur Spare Clock Slew Rate. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_CNTL</id>
+    <description>Centaur Control Slew Rate. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_CNTL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id>
+    <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_CLK_SCHMOO</id>
+    <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id>
+    <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id>
+    <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id>
+    <description>Slew Rates that can be selected during timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_RD_VREF</id>
+    <description>Centaur Read Vref. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_RD_VREF</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_RD_VREF_SCHMOO</id>
+    <description>Enables for which VREF value can be used in timing adjustments. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_RD_VREF_SCHMOO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_SIZE</id>
+    <description>DIMM Size. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_SIZE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_BANKS</id>
+    <description>Number of DRAM banks. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_BANKS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_ROWS</id>
+    <description>Number of DRAM rows. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_ROWS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_COLS</id>
+    <description>Number of DRAM columns. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_COLS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_DENSITY</id>
+    <description>DRAM Density. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_DENSITY</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRCD</id>
+    <description>DRAM RAS to CAS Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRCD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRRD</id>
+    <description>DRAM Row ACT to Row ACT Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRRD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRP</id>
+    <description>DRAM Row Precharge Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRAS</id>
+    <description>DRAM ACT to Precharge Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRAS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRC</id>
+    <description>DRAM ACT to ACT/Refresh Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRC</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRFI</id>
+    <description>Refresh Interval. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRFI</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRFC</id>
+    <description>DRAM Refresh Recovery Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRFC</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TWTR</id>
+    <description>DRAM Internal Write to Read Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TWTR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TRTP</id>
+    <description>DRAM Internal Read to Precharge Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TRTP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TFAW</id>
+    <description>DRAM Four ACT Window Delay. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TFAW</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_BL</id>
+    <description>DRAM Burst Length. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_BL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_CL</id>
+    <description>DRAM CAS Latency. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_CL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_AL</id>
+    <description>DRAM Additive Latency. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_AL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_CWL</id>
+    <description>DRAM CAS Write Latency. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_CWL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RBT</id>
+    <description>DRAM Read Burst Type. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RBT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TM</id>
+    <description>DRAM Test Mode. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_DLL_RESET</id>
+    <description>DRAM DLL Reset. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_DLL_RESET</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WR</id>
+    <description>DRAM Write Recovery. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_DLL_PPD</id>
+    <description>DRAM DLL Precharge PD. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_DLL_PPD</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_DLL_ENABLE</id>
+    <description>DRAM DLL Enable. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_DLL_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_TDQS</id>
+    <description>DRAM TDQS. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_TDQS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_WR_LVL_ENABLE</id>
+    <description>DRAM Write Level Enable. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_WR_LVL_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_OUTPUT_BUFFER</id>
+    <description>DRAM output buffer. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_OUTPUT_BUFFER</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_PASR</id>
+    <description>DRAM Partial Array Self-Refresh. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_PASR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_ASR</id>
+    <description>DRAM Auto Self-Refresh. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_ASR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_SRT</id>
+    <description>DRAM Self-Refresh Temperature Range. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_SRT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_MPR_LOC</id>
+    <description>Multi Purpose Register Location. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_MPR_LOC</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_MPR_MODE</id>
+    <description>Multi Purpose Register Mode. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_MPR_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_RCD_CNTL_WORD_0_15</id>
+    <description>DIMM RCD Control Word. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint64_t>
+            <default>0</default>
+        </uint64_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_RCD_IBT</id>
+    <description>DIMM RCD IBT. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_RCD_IBT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_RCD_MIRROR_MODE</id>
+    <description>DIMM RCD Mirror mode. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_RCD_MIRROR_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_MODE</id>
+    <description>Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_ADDR_MODE</id>
+    <description>Specifies the schmoo mode to use during draminit_train_adv. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_ADDR_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_TEST_VALID</id>
+    <description>Specifies the schmoo test to run during draminit_train_adv. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_TEST_VALID</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_PARAM_VALID</id>
+    <description>Specifies the schmoo parameters to use during draminit_train_adv. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_PARAM_VALID</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
+    <description>Specifies the schmoo minimum margin to use during draminit_train_adv. Used to signal possible SI issues in memory.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_MEMCAL_INTERVAL</id>
+    <description>Specifies the memcal interval in clocks. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_MEMCAL_INTERVAL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_ZQCAL_INTERVAL</id>
+    <description>Specifies the zqcal interval in clocks. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_ZQCAL_INTERVAL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_IBM_TYPE</id>
+    <description>Specifies the memory topology type. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_IBM_TYPE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_NUM_DROPS_PER_PORT</id>
+    <description>Specifies the number of DIMM dimensions that are valid per port. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_NUM_DROPS_PER_PORT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_STACK_TYPE</id>
+    <description>Specifies the DRAM package type. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_STACK_TYPE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_NUM_MASTER_RANKS_PER_DIMM</id>
+    <description>Specifies the number of master ranks per DIMM. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_NUM_PACKAGES_PER_RANK</id>
+    <description>Specifies the number of DRAM packages per rank. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_NUM_PACKAGES_PER_RANK</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_NUM_DIES_PER_PACKAGE</id>
+    <description>Specifies the number of DRAM dies per package. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_NUM_DIES_PER_PACKAGE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <description>DIMM throttle numerator. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_THROTTLE_DENOMINATOR</id>
+    <description>DIMM throttle denominator. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_THROTTLE_DENOMINATOR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <description>This is the throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_WATT_TARGET</id>
+    <description>Channel total memory watts. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_WATT_TARGET</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_POWER_SLOPE</id>
+    <description>DIMM Power slope value. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_POWER_SLOPE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_POWER_SLOPE2</id>
+    <description>DIMM Power slope value. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_POWER_SLOPE2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_POWER_INT</id>
+    <description>DIMM Power intercept value. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_POWER_INT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_POWER_INT2</id>
+    <description>DIMM Power intercept value. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_POWER_INT2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_MAXBANDWIDTH_GBS</id>
+    <description>DIMM Max Bandwidth in GBs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_GBS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_MAXBANDWIDTH_MRS</id>
+    <description>DIMM Max Bandwidth in MRs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_MAXBANDWIDTH_MRS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id>
+    <description>Channel Max Bandwidth in GBs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_GBS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
+    <description>Channel Pair Max Bandwidth in GBs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
+    <description>Channel Max Bandwidth MRs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_MAXBANDWIDTH_MRS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
+    <description>Channel Pair Max Bandwidth MRs. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DIMM_MAXPOWER</id>
+    <description>DIMM Max Power output. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2,2</array><!-- [drop][port] -->
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DIMM_MAXPOWER</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_MAXPOWER</id>
+    <description>Channel Max Power output. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_MAXPOWER</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CHANNEL_PAIR_MAXPOWER</id>
+    <description>Channel Pair Max Power output. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CHANNEL_PAIR_MAXPOWER</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_mba. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id>
+    <description>Runtime throttle denominator setting for cfg_nm_m. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+    <description>Runtime throttle numerator setting for cfg_nm_n_per_chip. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_INTERLEAVE_ENABLE</id>
+    <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0xff</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_INTERLEAVE_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MCA_HASH_MODE</id>
+    <description>sets up the centaur hash mode policy. Mode values are 0, 1, and 2.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MCA_HASH_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MBA_ADDR_INTERLEAVE_BIT</id>
+    <description>sets the Centaur address bits used to interleave addresses between MBA01 and MBA23. valid values are 23 through 32.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
+    <description>centaur interleave mode. 1 = 256-BIT, 0 = 128-BIT.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CACHE_ENABLE</id>
+    <description>
+        Specifies if a Memory Buffer chip L4 cache is enabled or disabled
+        For good memory buffer chips, L4 is enabled
+        Firmware can set to disabled for a particular chip if the cache is
+          not functional
+        1 = enabled, 0 = disabled.
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>1</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CACHE_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_PREFETCH_ENABLE</id>
+    <description>Prefteching enable. 1 = enable, 0 = disable.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_PREFETCH_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CLEANER_ENABLE</id>
+    <description>L4 cleaner enable. 1 = enable, 0 = disable.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CLEANER_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id>
+    <description>override the default Centaur MEM PLL settings with user-specified scan chain data. 1 = ON, 0 = OFF.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_LAB_OVERRIDE_FOR_MEM_PLL</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_MC_IN_GROUP</id>
+    <description>A 8 bit vector that would be a designation of which MC are involved in the group. Initialized and used by HWPs.</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>8</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_MC_IN_GROUP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MCS_GROUP_32</id>
+    <description>Data Structure from eff grouping to setup bars to help determine different groups
+   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+ //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+Measured in GB</description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+        <array>16,16</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MCS_GROUP_32</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
+    <description>A bit vector (per Dean's request) specifying if a DIMM is functional.  DIMM attributes, such as SIZE, are qualified by this bit vector.  The attribute ANDed 0x80 means port 0, DIMM 0 is functional, 0x40 means port 0, DIMM 1 is functional.  0x08 means port 1, DIMM 0 is functional and 0x04 means port 1 DIMM 1 is functional.  A fully populated system would have the value of 0xCC. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value. creator: mss_eff_cnfg consumer: various firmware notes: none
+This factors in functionality</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_CAL_STEP_ENABLE</id>
+    <description>A bit vector denoting valid cal steps to run during dram_init_train. [0] EXT_ZQCAL
+[1] WR_LEVEL
+[2] DQS_ALIGN
+[3] RDCLK_ALIGN
+[4] READ_CTR
+[5] WRITE_CTR
+[6] COARSE_WR
+[7] COARSE_RD
+bits6:7  will be consumed together to form COARSE_LVL. </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_CAL_STEP_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MEM_IPL_COMPLETE</id>
+    <description>A numerical number indicating if the memory procedures are complete.  written by mss_setup_bars when the bars are now functional in the processor.  </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MEM_IPL_COMPLETE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_SLEW_RATE_DATA</id>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2, 4, 4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_SLEW_RATE_DATA</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_SLEW_RATE_ADR</id>
+    <description>The 4 bit result of running the slew calibration algorithm at various rates and impedances</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2, 4, 4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_SLEW_RATE_ADR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_ECID</id>
+    <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1
+Created from running the mss_get_cen_ecid.C</description>
+    <simpleType>
+        <uint64_t>
+            <default>0</default>
+        </uint64_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_ECID</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_ALLOW_SINGLE_PORT</id>
+    <description>When this value is true, then mss_eff config will allow a single port to have one dimm and will allow ports to have different sizes.  Used in eff_config</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_ALLOW_SINGLE_PORT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<!-- TODO RTC 59048. These phase rotator attributes need to come from CDIMM VPD. For now
+     they are setup by the mss_eff_config_termination HWP -->
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CLK_P0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CLK_P1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CLK_P1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CLK_P0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CLK_P1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CLK_P1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A3</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A4</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A4</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A5</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A5</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A6</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A6</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A7</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A7</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A8</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A8</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A9</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A9</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A10</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A10</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A11</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A11</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A12</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A12</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A13</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A13</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A14</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A14</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_A15</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_A15</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_BA0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_BA1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_BA2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_BA2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_CASN</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_CASN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_RASN</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_RASN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_CMD_WEN</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_CMD_WEN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_PAR</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_PAR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M_ACTN</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M_ACTN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id>
+    <description>Phase rotator value that comes from termination on the CDIMM VPD</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+        <array>2</array>
+    </simpleType>
+    <persistency>volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_DQS_SWIZZLE_TYPE</id>
+    <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1.  Additional types maybe defined if new boards have even different DQS swizzle features</description>
+    <simpleType>
+        <uint8_t><default>0</default></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_DQS_SWIZZLE_TYPE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MSS_MCS_GROUP</id>
+    <description>Data Structure from eff grouping to setup bars to help determine different groups
+   Non- Mirroring [0-7] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+ //  Mirroring      [8-15] 0 -- MCS size //1-- No of MCS/group //2-- Total group size //3 -- Base address// 4-11 - MCS ID number// 12 --Alter.Bar //13 - A.Group Size // 14 - A.Base address
+Measured in GB</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>16,16</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_MCS_GROUP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_CKE_MAP</id>
+    <description>Rank to CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CKE_MAP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_SPCKE_MAP</id>
+    <description>Rank to Spare CKE map. Used in various locations and is computed in mss_eff_cnfg_cke_map. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg_cke_map consumer: various firmware notes: none</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_SPCKE_MAP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DIMM_SPARE</id>
+    <description>Spare DRAM availability. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.   creator: mss_eff_cnfg consumer: various firmware notes: load from spd</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DIMM_SPARE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<!-- ===== End Attributes supporting memory_attributes.xml HWPF Attributes ===== -->
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index 4ac14088e..59276d94d 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -71,7 +71,7 @@
     </attribute>
     <attribute>
         <id>ALL_MCS_IN_INTERLEAVING_GROUP</id>
-        <default>1</default>
+        <default>0</default>
     </attribute>
     <attribute>
         <id>FREQ_PROC_REFCLOCK</id>
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index 349ad7fc1..d0ea7bed4 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -75,7 +75,7 @@
     </attribute>
     <attribute>
         <id>ALL_MCS_IN_INTERLEAVING_GROUP</id>
-        <default>1</default>
+        <default>0</default>
     </attribute>
     <attribute>
         <id>FREQ_PROC_REFCLOCK</id>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 9754b5713..fe7f3a78d 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -229,6 +229,7 @@
      <attribute><id>PROC_PCIE_NOT_F_LINK</id></attribute>
      <attribute><id>MSS_INTERLEAVE_ENABLE</id></attribute>
      <attribute><id>MSS_MCS_GROUP_32</id></attribute>
+     <attribute><id>MSS_MEM_IPL_COMPLETE</id></attribute>
      <!-- Start pm_attributes_all_plat.xml -->
      <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id></attribute>
      <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id></attribute>
@@ -660,19 +661,43 @@
     <attribute><id>EFF_QUATERNARY_RANK_GROUP3</id></attribute>
     <attribute><id>EFF_ODT_RD</id></attribute>
     <attribute><id>EFF_ODT_WR</id></attribute>
+    <attribute><id>EFF_CKE_MAP</id></attribute>
+    <attribute><id>EFF_SPCKE_MAP</id></attribute>
+    <attribute><id>EFF_DIMM_SPARE</id></attribute>
     <attribute><id>EFF_DRAM_RON</id></attribute>
     <attribute><id>EFF_DRAM_RTT_NOM</id></attribute>
     <attribute><id>EFF_DRAM_RTT_WR</id></attribute>
     <attribute><id>EFF_DRAM_WR_VREF</id></attribute>
+    <attribute><id>EFF_DRAM_WRDDR4_VREF</id></attribute>
+    <attribute><id>EFF_DRAM_WR_VREF_SCHMOO</id></attribute>
+    <attribute><id>EFF_DRAM_WRDDR4_VREF_SCHMOO</id></attribute>
     <attribute><id>EFF_CEN_DRV_IMP_DQ_DQS</id></attribute>
-    <attribute><id>EFF_CEN_DRV_IMP_CMD</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_ADDR</id></attribute>
     <attribute><id>EFF_CEN_DRV_IMP_CNTL</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_CLK</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_SPCKE</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_CLK_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_SPCKE_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_DRV_IMP_CNTL_SCHMOO</id></attribute>
     <attribute><id>EFF_CEN_RCV_IMP_DQ_DQS</id></attribute>
+    <attribute><id>EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO</id></attribute>
     <attribute><id>EFF_CEN_SLEW_RATE_DQ_DQS</id></attribute>
-    <attribute><id>EFF_CEN_SLEW_RATE_CMD</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_ADDR</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_CLK</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_SPCKE</id></attribute>
     <attribute><id>EFF_CEN_SLEW_RATE_CNTL</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_CLK_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_SPCKE_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_ADDR_SCHMOO</id></attribute>
+    <attribute><id>EFF_CEN_SLEW_RATE_CNTL_SCHMOO</id></attribute>
     <attribute><id>EFF_CEN_RD_VREF</id></attribute>
+    <attribute><id>EFF_CEN_RD_VREF_SCHMOO</id></attribute>
     <attribute><id>EFF_DIMM_SIZE</id></attribute>
+    <attribute><id>EFF_DRAM_BANKS</id></attribute>
+    <attribute><id>EFF_DRAM_ROWS</id></attribute>
+    <attribute><id>EFF_DRAM_COLS</id></attribute>
     <attribute><id>EFF_DRAM_DENSITY</id></attribute>
     <attribute><id>EFF_DRAM_TRCD</id></attribute>
     <attribute><id>EFF_DRAM_TRRD</id></attribute>
@@ -703,39 +728,99 @@
     <attribute><id>EFF_MPR_LOC</id></attribute>
     <attribute><id>EFF_MPR_MODE</id></attribute>
     <attribute><id>EFF_DIMM_RCD_CNTL_WORD_0_15</id></attribute>
+    <attribute><id>EFF_DIMM_RCD_IBT</id></attribute>
+    <attribute><id>EFF_DIMM_RCD_MIRROR_MODE</id></attribute>
     <attribute><id>EFF_SCHMOO_MODE</id></attribute>
+    <attribute><id>EFF_SCHMOO_ADDR_MODE</id></attribute>
     <attribute><id>EFF_SCHMOO_TEST_VALID</id></attribute>
     <attribute><id>EFF_SCHMOO_PARAM_VALID</id></attribute>
+    <attribute><id>EFF_SCHMOO_WR_EYE_MIN_MARGIN</id></attribute>
+    <attribute><id>EFF_SCHMOO_RD_EYE_MIN_MARGIN</id></attribute>
+    <attribute><id>EFF_SCHMOO_DQS_CLK_MIN_MARGIN</id></attribute>
+    <attribute><id>EFF_SCHMOO_RD_GATE_MIN_MARGIN</id></attribute>
+    <attribute><id>EFF_SCHMOO_ADDR_CMD_MIN_MARGIN</id></attribute>
     <attribute><id>EFF_MEMCAL_INTERVAL</id></attribute>
     <attribute><id>EFF_ZQCAL_INTERVAL</id></attribute>
-    <attribute><id>MSS_THROTTLE_NUMERATOR</id></attribute>
-    <attribute><id>MSS_THROTTLE_DENOMINATOR</id></attribute>
-    <attribute><id>MSS_THROTTLE_CHANNEL_NUMERATOR</id></attribute>
-    <attribute><id>MSS_THROTTLE_CHANNEL_DENOMINATOR</id></attribute>
-    <attribute><id>MSS_WATT_TARGET</id></attribute>
+    <attribute><id>EFF_IBM_TYPE</id></attribute>
+    <attribute><id>EFF_NUM_DROPS_PER_PORT</id></attribute>
+    <attribute><id>EFF_STACK_TYPE</id></attribute>
+    <attribute><id>EFF_NUM_MASTER_RANKS_PER_DIMM</id></attribute>
+    <attribute><id>EFF_NUM_PACKAGES_PER_RANK</id></attribute>
+    <attribute><id>EFF_NUM_DIES_PER_PACKAGE</id></attribute>
+    <attribute><id>MSS_MEM_THROTTLE_NUMERATOR_PER_MBA</id></attribute>
+    <attribute><id>MSS_MEM_THROTTLE_DENOMINATOR</id></attribute>
+    <attribute><id>MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP</id></attribute>
+    <attribute><id>MSS_MEM_WATT_TARGET</id></attribute>
     <attribute><id>MSS_POWER_SLOPE</id></attribute>
+    <attribute><id>MSS_POWER_SLOPE2</id></attribute>
     <attribute><id>MSS_POWER_INT</id></attribute>
+    <attribute><id>MSS_POWER_INT2</id></attribute>
     <attribute><id>MSS_DIMM_MAXBANDWIDTH_GBS</id></attribute>
     <attribute><id>MSS_DIMM_MAXBANDWIDTH_MRS</id></attribute>
     <attribute><id>MSS_CHANNEL_MAXBANDWIDTH_GBS</id></attribute>
+    <attribute><id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_GBS</id></attribute>
     <attribute><id>MSS_CHANNEL_MAXBANDWIDTH_MRS</id></attribute>
+    <attribute><id>MSS_CHANNEL_PAIR_MAXBANDWIDTH_MRS</id></attribute>
     <attribute><id>MSS_DIMM_MAXPOWER</id></attribute>
     <attribute><id>MSS_CHANNEL_MAXPOWER</id></attribute>
-    <attribute><id>MSS_MEMSIZE_MBA</id></attribute>
-    <attribute><id>EFF_DRAM_BANKS</id></attribute>
-    <attribute><id>EFF_DRAM_ROWS</id></attribute>
-    <attribute><id>EFF_DRAM_COLS</id></attribute>
-    <attribute><id>EFF_DIMM_RCD_IBT</id></attribute>
-    <attribute><id>EFF_DIMM_RCD_MIRROR_MODE</id></attribute>
-    <attribute><id>EFF_IBM_TYPE</id></attribute>
-    <attribute><id>EFF_NUM_DROPS_PER_PORT</id></attribute>
-    <attribute><id>EFF_STACK_TYPE</id></attribute>
-    <attribute><id>EFF_NUM_MASTER_RANKS_PER_DIMM</id></attribute>
-    <attribute><id>EFF_NUM_PACKAGES_PER_RANK</id></attribute>
-    <attribute><id>EFF_NUM_DIES_PER_PACKAGE</id></attribute>
-    <attribute><id>MSS_SPARE_BYTE</id></attribute>
+    <attribute><id>MSS_CHANNEL_PAIR_MAXPOWER</id></attribute>
+    <attribute><id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA</id></attribute>
+    <attribute><id>MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR</id></attribute>
+    <attribute><id>MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP</id></attribute>
     <attribute><id>MSS_EFF_DIMM_FUNCTIONAL_VECTOR</id></attribute>
     <attribute><id>MSS_CAL_STEP_ENABLE</id></attribute>
+    <attribute><id>MSS_SLEW_RATE_DATA</id></attribute>
+    <attribute><id>MSS_SLEW_RATE_ADR</id></attribute>
+    <attribute><id>MSS_ALLOW_SINGLE_PORT</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CLK_P0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CLK_P1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CLK_P0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CLK_P1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A3</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A4</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A5</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A6</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A7</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A8</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A9</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A10</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A11</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A12</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A13</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A14</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_A15</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_BA0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_BA1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_BA2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_CASN</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_RASN</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_CMD_WEN</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_PAR</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M_ACTN</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CKE3</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_CSN3</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M0_CNTL_ODT1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CKE3</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN1</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN2</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_CSN3</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT0</id></attribute>
+    <attribute><id>EFF_CEN_PHASE_ROT_M1_CNTL_ODT1</id></attribute>
+    <attribute><id>MSS_DQS_SWIZZLE_TYPE</id></attribute>
 </targetType>
 
 <targetType>
@@ -844,6 +929,7 @@
     <attribute><id>MSS_VOLT</id></attribute>
     <attribute><id>MSS_FREQ</id></attribute>
     <attribute><id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id></attribute>
+    <attribute><id>MSS_ECID</id></attribute>
     <attribute><id>EI_BUS_RX_MSB_LSB_SWAP</id></attribute>
     <attribute><id>EI_BUS_TX_MSB_LSB_SWAP</id></attribute>
     <attribute>